TLV9364QPWRQ1 [TI]
汽车类、四通道、40V、10.6MHz 轨到轨输出运算放大器 | PW | 14 | -40 to 125;
| 型号： | TLV9364QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类、四通道、40V、10.6MHz 轨到轨输出运算放大器 | PW | 14 | -40 to 125 放大器 运算放大器 |
| 文件： | 总48页 (文件大小：2621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
TLV936x-Q1 适用于成本敏感型系统的汽车类10MHz、40V、轨至轨输出运算放
大器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TLV936x-Q1 系列（TLV9361-Q1、TLV9362-Q1 和
TLV9364-Q1）是一个符合 AEC-Q100 汽车标准的
40V 成本优化型运算放大器系列。
– 温度等级1：–40°C 至+125°C
– 人体放电模型(HBM) 静电放电(ESD) 分级等
级：2A
这些器件具有出色的直流和交流规格，包括轨至轨输
出、低输入电压噪声密度 (6nV/√Hz)、低失调电压
（ 典 型 值 为 ±400µV ） 、 低 温 漂 （ 典 型 值 为
±1.25µV/°C）和10.6MHz 带宽。
– 充电器件模型(CDM) ESD 分级等级：C6
• 低失调电压：±400µV
• 低失调电压漂移：±1.25µV/°C
• 低噪声：1kHz 时为8.5nV/√Hz，6nV/√Hz 宽带
• 高共模抑制：110dB
TLV936x-Q1 的特性（例如 EMIRR 滤波、大输出电流
(±60mA) 以及高压摆率 (25V/µs)）使其成为了一款可
靠的运算放大器，适用于高电压成本敏感型应用。
• 低偏置电流：±10pA
• 轨到轨输出
• 高带宽：10.6MHz GBW，单位增益稳定
• 高压摆率：25 V/µs
• 低静态电流：每个放大器2.6 mA
• 宽电源电压：±2.25V 至±20V，4.5V 至40V
• 强大的EMIRR 性能
TLV936x-Q1 系列运算放大器采用标准封装，额定工作
温度范围为–40°C 至125°C。
封装信息
器件型号(1)
封装尺寸（标称值）
2.00mm x 1.25mm
2.90mm × 1.60mm
3.00mm x 3.00mm
4.90mm × 3.90mm
5.00mm x 4.40mm
8.65mm x 3.90mm
封装
DCK（SC70，5）
DBV（SOT-23，5)
DGK（VSSOP，8）
D（SOIC，8）
TLV9361-Q1
2 应用
• 汽车音响主机
TLV9362-Q1
TLV9364-Q1
• 数字驾驶舱处理单元
• 远程信息处理控制单元
• 紧急呼叫(eCall)
• 汽车有源噪声消除
• 汽车外部放大器
PW（TSSOP，14）
D（SOIC，14）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
RG
RF
R1
VOUT
VIN
C1
1
2pR1C1
f
=
-3 dB
VOUT
VIN
RF
1
( 1 + sR C (
= 1 +
RG
1
1
单极低通滤波器中的TLV936x-Q1
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................19
7.4 Device Functional Modes..........................................24
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Applications.................................................. 25
8.3 Power Supply Recommendations.............................26
8.4 Layout....................................................................... 27
9 Device and Documentation Support............................29
9.1 Device Support......................................................... 29
9.2 Documentation Support............................................ 29
9.3 接收文档更新通知..................................................... 29
9.4 支持资源....................................................................29
9.5 Trademarks...............................................................29
9.6 静电放电警告............................................................ 30
9.7 术语表....................................................................... 30
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information for Single Channel..................... 7
6.5 Thermal Information for Dual Channel........................7
6.6 Thermal Information for Quad Channel...................... 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics.............................................. 11
7 Detailed Description......................................................18
7.1 Overview...................................................................18
7.2 Functional Block Diagram.........................................18
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (Aptil 2023) to Revision A (May 2023)
Page
• 将PW 和D 封装状态从预发布 更改为正在供货 ................................................................................................1
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
5 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
Vœ
1
2
3
5
V+
IN+
4
INœ
INœ
4
OUT
Not to scale
Not to scale
图5-1. TLV9361-Q1 DBV Package,
5-Pin SOT-23
图5-2. TLV9361-Q1 DCK Package,
5-Pin SC70
(Top View)
(Top View)
表5-1. Pin Functions: TLV9361-Q1
PIN
TYPE(1)
DESCRIPTION
NAME
IN+
SOT-23
SC70
3
4
1
5
2
1
3
4
5
2
I
Non-inverting input
Inverting input
I
IN–
OUT
V+
O
—
—
Output
Positive (highest) power supply
Negative (lowest) power supply
V–
(1) I = input, O = output
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
IN2œ
IN2+
Not to scale
图5-3. TLV9362-Q1 D and DGK Package,
8-Pin SOIC and VSSOP
(Top View)
表5-2. Pin Functions: TLV9362-Q1
PIN
TYPE(1)
DESCRIPTION
NAME
IN1+
NO.
3
I
I
Non-inverting input, channel 1
2
Inverting input, channel 1
Non-inverting input, channel 2
Inverting input, channel 2
Output, channel 1
IN1–
IN2+
IN2–
OUT1
OUT2
V+
5
I
6
I
1
O
O
—
—
7
Output, channel 2
8
Positive (highest) power supply
Negative (lowest) power supply
4
V–
(1) I = input, O = output
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
Not to scale
图5-4. TLV9364-Q1 D and PW Package,
SOIC and TSSOP
(Top View)
表5-3. Pin Functions: TLV9364-Q1
PIN
TYPE(1)
DESCRIPTION
NAME
IN1+
NO.
3
I
I
Non-inverting input, channel 1
2
Inverting input, channel 1
Non-inverting input, channel 2
Inverting input, channel 2
Non-inverting input, channel 3
Inverting input, channel 3
Non-inverting input, channel 4
Inverting input, channel 4
Output, channel 1
IN1–
IN2+
5
I
6
I
IN2–
IN3+
10
9
I
I
IN3–
IN4+
12
13
1
I
I
IN4–
OUT1
OUT2
OUT3
OUT4
V+
O
O
O
O
—
—
7
Output, channel 2
8
Output, channel 3
14
4
Output, channel 4
Positive (highest) power supply
Negative (lowest) power supply
11
V–
(1) I = input, O = output
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
0
MAX
UNIT
V
42
(V+) + 0.5
VS + 0.2
10
Supply voltage, VS = (V+) –(V–)
Common-mode voltage(3)
V
(V–) –0.5
Signal input pins
Differential voltage(3)
Current(3)
V
mA
–10
Output short-circuit(2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
Storage temperature, Tstg
150
150
150
°C
°C
°C
–55
–65
(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings causes permanent damage to the device. These are
stress ratings only, based on process and design limitations, and this device has not been designed to function outside the conditions
indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating Conditions for
extended periods, including absolute-maximum-rated conditions, can affect device reliability and performance.
(2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause
excessive heating and eventual destruction.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 ESD Ratings
VALUE
UNIT
TLV9361-Q1
V(ESD)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±2000
±1500
Electrostatic discharge
V
TLV9362-Q1 and TLV9364-Q1
V(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±2500
±1500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
4.5
MAX
UNIT
VS
VI
40
(V+) –2
125
V
V
Supply voltage, (V+) –(V–)
Common mode voltage range
Specified temperature
(V–)
–40
TA
°C
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
6.4 Thermal Information for Single Channel
TLV9361-Q1
DBV
DCK
(SC70)
THERMAL METRIC(1)
UNIT
(SOT-23)
5 PINS
189.3
86.8
5 PINS
202.4
111.6
51.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
55.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
23.6
25.8
ψJT
55.5
51.4
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information for Dual Channel
TLV9362-Q1
D
DGK
(VSSOP)
THERMAL METRIC(1)
Unit
(SOIC)
8 PINS
130.8
74.0
8 PINS
173.9
65.7
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
74.3
95.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.8
10.9
ψJT
73.5
94.1
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Thermal Information for Quad Channel
TLV9364-Q1
D
PW
(TSSOP)
THERMAL METRIC(1)
UNIT
(SOIC)
14 PINS
94.9
14 PINS
120.0
50.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
51.1
51.4
63.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
15.3
8.1
ψJT
51.0
62.5
ψJB
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
6.7 Electrical Characteristics
For VS = (V+) –(V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±0.4
±1.7
±2
VOS
Input offset voltage
mV
VCM = V–
VCM = V–
TA = –40°C to 125°C
dVOS/dT
PSRR
Input offset voltage drift
±1.25
±1.5
1
TA = –40°C to 125°C
TA = –40°C to 125°C
µV/℃
μV/V
µV/V
Input offset voltage versus
power supply
VCM = V–, VS = 5 V to 40
±7.5
V(1)
DC channel separation
INPUT BIAS CURRENT
IB
Input bias current
±10
±10
pA
pA
IOS
Input offset current
NOISE
6
1
μVPP
EN
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
8.5
6
eN
iN
Input voltage noise density
nV/√Hz
fA/√Hz
f = 10 kHz
Input current noise density f = 1 kHz
100
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
V
(V–)
95
(V+) –2
VS = 40 V, V–< VCM
(V+) –2 V
<
110
85
Common-mode rejection
ratio
CMRR
dB
TA = –40°C to 125°C
VS = 5 V, V–< VCM < (V+) –
75
2 V(1)
INPUT IMPEDANCE
ZID
Differential
Common-mode
100 || 9
6 || 1
MΩ|| pF
TΩ|| pF
ZICM
OPEN-LOOP GAIN
VS = 40 V, VCM = VS / 2,
(V–) + 0.1 V < VO < (V+) –
0.1 V
115
100
130
130
VS = 40 V, VCM = VS / 2,
(V–) + 0.12 V < VO < (V+) – TA = –40°C to 125°C
0.12 V
AOL
Open-loop voltage gain
dB
VS = 5 V, VCM = VS / 2,
120
120
(V–) + 0.1 V < VO < (V+) –
0.1 V(1)
TA = –40°C to 125°C
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
10.6
25
MHz
Slew rate
VS = 40 V, G = +1, VSTEP = 10 V, CL = 20 pF(3)
To 0.1%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF
To 0.1%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF
To 0.01%, VS = 40 V, VSTEP = 10 V, G = +1, CL = 20 pF
To 0.01%, VS = 40 V, VSTEP = 2 V, G = +1, CL = 20 pF
G = +1, RL = 10 kΩ, CL = 20 pF
V/μs
0.65
0.3
tS
Settling time
μs
0.86
0.44
64
Phase margin
°
Overload recovery time
VIN × gain > VS
170
ns
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English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
6.7 Electrical Characteristics (continued)
For VS = (V+) –(V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
0.0001%
120
MAX
UNIT
dB
VS = 40 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 10 kΩ
0.0056%
85
Total harmonic distortion +
noise
THD+N
VS = 10 V, VO = 3 VRMS, G = 1, f = 1 kHz, RL = 128 Ω
VS = 10 V, VO = 0.4 VRMS, G = 1, f = 1 kHz, RL = 32 Ω
dB
0.00056%
105
dB
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
6.7 Electrical Characteristics (continued)
For VS = (V+) –(V–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VS = 40 V, RL = no load
VS = 40 V, RL = 10 kΩ
VS = 40 V, RL = 2 kΩ
10
60
Voltage output swing from Positive and negative
100
400
mV
rail
rail headroom
250
ISC
Short-circuit current
±60(2)
mA
pF
CLOAD
Capacitive Load Drive
See 图6-28
Open-loop output
impedance
ZO
IO = 0 A
IO = 0 A
See 图6-25
Ω
POWER SUPPLY
2.6
3
Quiescent current per
amplifier
IQ
mA
3.2
TA = –40°C to 125°C
(1) Specified by characterization only.
(2) At high supply voltage, placing the TLV936x-Q1 in a sudden short to mid-supply or ground will lead to rapid thermal shutdown. Output
current greater than ISC can be achieved if rapid thermal shutdown is avoided as per 图6-12.
(3) See 图6-11 for more information.
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English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
6.8 Typical Characteristics
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
-675 -525 -375 -225 -75
0
75
Offset Voltage (µV)
225 375 525 675
0.1
0.2
0.3
0.4
0.5
0.6
Offset Voltage Drift (µV/°C)
0.7
0.8
0.9
D001
D002
Distribution from 74 amplifiers, TA = 25°C
Distribution from 74 amplifiers
图6-2. Offset Voltage Drift Distribution
图6-1. Offset Voltage Production Distribution
500
2000
1600
1200
800
400
300
200
100
0
400
0
-100
-200
-300
-400
-500
-400
-800
-1200
-1600
-2000
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20 -16 -12
-8
-4
0
Common-Mode Voltage (V)
4
8
12
16
20
D013
D015
VCM = V-
TA = 25°C
Data from 74 amplifiers
Data from 74 amplifiers
图6-3. Offset Voltage vs Temperature
图6-4. Offset Voltage vs Common-Mode Voltage
2000
1600
1200
800
2000
1600
1200
800
400
400
0
0
-400
-800
-1200
-1600
-2000
-400
-800
-1200
-1600
-2000
-20 -16 -12
-8
-4
Common-Mode Voltage (V)
0
4
8
12
16
20
-20 -16 -12
-8
-4
Common-Mode Voltage (V)
0
4
8
12
16
20
D016
D017
TA = 125°C
TA = –40°C
Data from 74 amplifiers
Data from 74 amplifiers
图6-5. Offset Voltage vs Common-Mode Voltage
图6-6. Offset Voltage vs Common-Mode Voltage
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
500
400
300
200
100
0
75
60
45
30
15
0
G=-1
G=1
G=11
G=101
G=1001
-100
-200
-300
-400
-500
-15
-30
-45
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
40
100
1k
10k 100k
Frequency (Hz)
1M
10M
D018
D005
VCM = V–
图6-8. Closed-Loop Gain vs Frequency
Data from 74 amplifiers
图6-7. Offset Voltage vs Power Supply
50
45
40
35
30
25
20
15
10
5
2000
1800
1600
1400
1200
1000
800
IB-
IB+
IOS
IB-
IB+
IOS
600
400
0
-5
200
-10
-15
-20
0
-200
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-20 -16 -12
-8
-4
0
4
8
Common-Mode Voltage (V)
12
16
20
D020
D019
图6-10. Input Bias Current and Offset Current vs Temperature
图6-9. Input Bias Current and Offset Current vs Common-Mode
Voltage
V+
V+ - 1V
V+ - 2V
V+ - 3V
V+ - 4V
V+ - 5V
V+ - 6V
V+ - 7V
50
SR+
SR-
45
40
35
30
25
20
15
10
5
V+ - 8V
-40°C
25°C
V+ - 9V
125°C
V+ - 10V
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
0
0
0.5
1
1.5
2
2.5
3
Input Step (V)
3.5
4
4.5
5
D021
D035
VS = 40 V
图6-11. Slew Rate vs Input Step Voltage
图6-12. Output Voltage Swing vs Output Current (Sourcing)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
V- + 10V
V- + 9V
V- + 8V
V- + 7V
V- + 6V
V- + 5V
V- + 4V
V- + 3V
V- + 2V
V- + 1V
V-
V+
V+ - 1V
V+ - 2V
V+ - 3V
V+ - 4V
V+ - 5V
-40°C
25°C
125°C
-40°C
25°C
125°C
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
0
10
20
30
40
Output Current (mA)
50
60
70
80
90 100
D022
D049
VS = 40 V
VS = 5 V
图6-13. Output Voltage Swing vs Output Current (Sinking)
图6-14. Output Voltage Swing vs Output Current (Sourcing)
V- + 5V
-40°C
25°C
120
CMRR
PSRR+
PSRR-
105
90
75
60
45
30
15
0
125°C
V- + 4V
V- + 3V
V- + 2V
V- + 1V
V-
0
10
20
30
40
50
60
Output Current (mA)
70
80
90 100
1k
10k
100k
Frequency (Hz)
1M
10M
D050
D006
VS = 5 V
图6-15. Output Voltage Swing vs Output Current (Sinking)
图6-16. CMRR and PSRR vs Frequency
1000
100
10
60
1000
100
10
60
80
80
100
120
140
100
120
140
1
1
0.1
0.1
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D023
D051
VS = 40 V
VS = 5 V
图6-17. CMRR vs Temperature
图6-18. CMRR vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
100
10
80
2
1.5
1
100
120
140
160
0.5
0
1
-0.5
-1
0.1
-1.5
-2
0.01
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D024
Time (1s/div)
图6-19. PSRR vs Temperature
D025
图6-20. 0.1-Hz to 10-Hz Noise
2.8
2.4
2
100
10
1
1.6
1.2
0.8
0.4
0
0
4
8
12
16
20
24
Supply Voltage (V)
28
32
36
40
10
100
1k
Frequency (Hz)
10k
D026
D007
图6-21. Input Voltage Noise Spectral Density vs Frequency
VCM = V–
图6-22. Quiescent Current vs Supply Voltage
2.6
2.55
2.5
2.45
2.4
2.35
2.3
2.25
2.2
2.15
2.1
2.05
2
1.95
1.9
1.85
1.8
145
140
135
130
125
120
115
110
105
100
VS = 2.7V
VS = 5V
VS = 40V
Vs=2.7V
Vs=5V
Vs=40V
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D028
D24_
图6-24. Open-Loop Voltage Gain vs Temperature (dB)
VCM = V–
图6-23. Quiescent Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
1000
100
10
70
60
50
40
30
20
10
0
1
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
0.1
100
1k
10k 100k
Frequency (Hz)
1M
10M
0
80
160
240 320
Capacitive Load (pF)
400
480
560
D099
D029
图6-25. Open-Loop Output Impedance vs Frequency
20-mVpp Output Step, G = -1
图6-26. Small-Signal Overshoot vs Capacitive Load
70
70
65
60
55
50
45
40
35
30
25
20
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
60
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
50
40
30
20
10
0
0
80
160
240 320
Capacitive Load (pF)
400
480
560
0
20 40 60 80 100 120 140 160 180 200 220
Capacitive Load (pF)
D030
D004
20-mVpp Output Step, G = +1
G = +1
图6-27. Small-Signal Overshoot vs Capacitive Load
图6-28. Phase Margin vs Capacitive Load
Input
Output
Input
Output
Time (100ns/div)
Time (100ns/div)
D032
D053
G = –10
G = –10
图6-29. Positive Overload Recovery
图6-30. Negative Overload Recovery
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
20
10
0
20
10
0
Input
Output
Input
Output
-10
-20
-10
-20
Time (2 µs/div)
Time (2 µs/div)
D033
D054
CL = 20 pF, G = 1, 20-mVpp step response
CL = 20 pF, G = -1, 20-mVpp step response
图6-31. Small-Signal Step Response
图6-32. Small-Signal Step Response
4
3
4
3
Input
Output
Input
Output
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
Time (2 µs/div)
Time (2 µs/div)
D034
D055
CL = 20 pF, G = 1, 5-Vpp step response
CL = 20 pF, G = -1, 5-Vpp step response
图6-33. Large-Signal Step Response
图6-34. Large-Signal Step Response
45
40
35
30
25
20
15
10
5
-60
Vs=40V
Vs=16V
Vs=2.7V
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
0
100
100
1k
10k 100k
Frequency (Hz)
1M
10M
1k
10k
100k
Frequency (Hz)
1M
10M
100M
D011
D009
图6-36. Channel Separation vs Frequency
图6-35. Maximum Output Voltage vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±20 V, VCM = VS / 2, RLOAD = 10 kΩ(unless otherwise noted)
120
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
D012
图6-37. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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7 Detailed Description
7.1 Overview
The TLV936x-Q1 family (TLV9361-Q1, TLV9362-Q1, and TLV9364-Q1) is a family of 40-V, cost-optimized
operational amplifiers. These devices offer strong general-purpose DC and AC specifications, including rail-to-
rail output, low offset (±400 µV, typ), low offset drift (±1.25 µV/°C, typ), and 10.6-MHz bandwidth.
Convenient features such as wide differential input-voltage range, high output current (±60 mA), and high slew
rate (25 V/μs) make the TLV936x-Q1 a robust operational amplifier for high-voltage, cost-sensitive applications.
The TLV936x-Q1 family of op amps is available in standard packages and is specified from –40°C to 125°C.
7.2 Functional Block Diagram
Slew
Boost
IN+
IN-
+
OUT
PCH Input
Stage
–
Gain
Stage
Output
Stage
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7.3 Feature Description
7.3.1 EMI Rejection
The TLV936x-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV936x-Q1 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. 图 7-1
shows the results of this testing on the TLV936x-Q1. 表 7-1 lists the EMIRR IN+ values for the TLV936x-Q1 at
particular frequencies commonly encountered in real-world applications. 表 7-1 lists applications that can be
centered on or operated near the particular frequency shown. The EMI Rejection Ratio of Operational Amplifiers
application report contains detailed information on the topic of EMIRR performance as relates to op amps and is
available for download from www.ti.com.
120
110
100
90
80
70
60
50
40
30
20
10M
100M
Frequency (Hz)
1G
D012
图7-1. EMIRR Testing
表7-1. TLV936x-Q1 EMIRR IN+ for Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
50.0 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
5 GHz
56.3 dB
65.6 dB
70.0 dB
78.9 dB
91.0 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
7.3.2 Thermal Protection
The internal power dissipation of any amplifier causes the internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the TLV936x-Q1 is 150°C.
Exceeding this temperature causes damage to the device. The TLV936x-Q1 has a thermal protection feature
that reduces damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 170°C. 图 7-2 shows an application example for the
TLV9362-Q1 that has significant self heating because of the power dissipation (0.954 W). In this example, both
channels have a quiescent power dissipation while one of the channels has a significant load. Thermal
calculations indicate that for an ambient temperature of 55°C, the device junction temperature reaches 180°C.
The actual device, however, turns off the output drive to recover towards a safe junction temperature. 图 7-2
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shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so
the output is 3 V.
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When self heating causes the device junction temperature to increase above the internal limit, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. If
the condition that caused excessive power dissipation is not removed, the amplifier oscillates between a
shutdown and enabled state until the output fault is corrected. Please note that thermal performance can vary
greatly depending on the package selected and the PCB layout design. This example uses the thermal
performance of the SOIC (8) package.
One channel has load
Consider IQ of two channels
TA = 55°C
3 V
30 V
PD = 0.954W
JA = 131°C/W
0 V
TJ = 131°C/W × 0.954W + 55°C
TJ = 180°C (expected)
ꢀ
TLV9362
170ºC
ꢁ
IOUT = 30 mA
+
3 V
–
RL
100
+
–
VIN
3 V
图7-2. Thermal Protection
7.3.3 Capacitive Load and Stability
The TLV936x-Q1 features an output stage capable of driving moderate capacitive loads, and by leveraging an
isolation resistor, the device can easily be configured to driver large capacitive loads. Increasing the gain
enhances the ability of the amplifier to drive greater capacitive loads; see 图 7-3 and 图 7-4. The particular op
amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing
whether an amplifier is stable in operation.
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
RISO = 0W, Overshoot (+)
RISO = 0W, Overshoot (-)
RISO = 50W, Overshoot (+)
RISO = 50W, Overshoot (-)
0
80
160
240 320
Capacitive Load (pF)
400
480
560
0
80
160
240 320
Capacitive Load (pF)
400
480
560
D030
D029
图7-3. Small-Signal Overshoot vs Capacitive Load 图7-4. Small-Signal Overshoot vs Capacitive Load
(20-mVpp Output Step, G = +1) (20-mVpp Output Step, G = -1)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
resistor, RISO, in series with the output, as shown in 图 7-5. This resistor significantly reduces ringing and
maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the
capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing
the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low
output levels. A high capacitive load drive makes the TLV936x-Q1 an excellent choice for applications such as
reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in 图 7-5 uses an isolation
resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased
phase margin.
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+Vs
+
Vout
Riso
Cload
+
Vin
-Vs
œ
图7-5. Extending Capacitive Load Drive With the TLV9361-Q1
7.3.4 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage
breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to
the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them
from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and relevance to an electrical overstress event is
helpful. 图 7-6 shows an illustration of the ESD circuits contained in the TLV936x-Q1 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
TVS
RF
+VS
VDD
50
50
R1
RS
IN–
IN+
–
+
Power-Supply
ESD Cell
RL
ID
+
–
VIN
VSS
–VS
TVS
图7-6. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is; during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit
(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
7.3.5 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the TLV936x-Q1 is approximately 170 ns.
7.3.6 Typical Specifications and Distributions
Designers often have questions about a typical specification of an amplifier to design a more robust circuit. Due
to natural variation in process technology and manufacturing procedures, every specification of an amplifier
exhibits some amount of deviation from the ideal value, like an amplifier's input offset voltage. These deviations
often follow Gaussian (bell curve), or normal distributions, and circuit designers can leverage this information to
guard band their system, even when there is not a minimum or maximum specification in the Electrical
Characteristics table.
0.00312% 0.13185%
0.13185% 0.00312%
0.00002%
0.00002%
2.145% 13.59% 34.13% 34.13% 13.59% 2.145%
1
1 1 1 1 1 1 1 1
1
1
1
ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1
ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61
ꢀ
图7-7. Ideal Gaussian Distribution
图 7-7 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is
the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-
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thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the
mean (from µ –σto µ + σ).
Depending on the specification, values listed in the typical column of the Electrical Characteristics table are
represented in different ways. As a general rule, if a specification naturally has a nonzero mean (for example,
like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a
mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation
(µ + σ) to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV936x-
Q1, the typical input voltage offset is 400 µV, so 68.2% of all TLV936x-Q1 devices are expected to have an offset
from
–400 µV to 400 µV. At 4 σ (±1600 µV), 99.9937% of the distribution has an offset voltage less than ±1600 µV,
which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are specified by TI, and units outside these
limits are removed from production material. For example, the TLV936x-Q1 family has a maximum offset voltage
of 1.7 mV at 125°C, and even though this corresponds to about 4.25 σ (≈2 in 100,000 units), which is unlikely,
TI verifies that any unit with larger offset than 1.7 mV is removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of
sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-
σvalue corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and can be an option
as a wide guardband to design a system around. In this case, the TLV936x-Q1 family does not have a maximum
or minimum for offset voltage drift, but based on the typical value of 1.25 µV/°C in the Electrical Characteristics
table, the 6-σ value is calculated for offset voltage drift is about 7.5 µV/°C. When designing for worst-case
system conditions, this value can be used to estimate the worst possible offset across temperature without
having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and
unless there is a value in the minimum or maximum specification column, TI cannot verify the performance of a
device. This information must be used only to estimate the performance of a device.
7.4 Device Functional Modes
The TLV936x-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the TLV936x-Q1 is 40 V (±20 V).
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English Data Sheet: SBOSAD6
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ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TLV936x-Q1 family offers excellent DC precision and DC performance. These devices operate up to 40-V
supply rails and offer true rail-to-rail output, low offset voltage and offset voltage drift, as well as 10.6-MHz
bandwidth and high output drive. These features make the TLV936x-Q1 a robust, high-performance operational
amplifier for high-voltage cost-sensitive applications.
8.2 Typical Applications
8.2.1 Low-Side Current Measurement
图 8-1 shows the TLV936x-Q1 configured in a low-side current sensing application. For a full analysis of the
circuit shown in 图 8-1 including theory, calculations, simulations, and measured data, see TI Precision Design
TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.
VCC
5 V
LOAD
+
VOUT
–
RSHUNT
ILOAD
100 m
LM7705
RF
5.76 k
RG
120
图8-1. TLV936x-Q1 in a Low-Side, Current-Sensing Application
8.2.2 Design Requirements
The design requirements for this design are:
• Load current: 0 A to 1 A
• Max output voltage: 4.9 V
• Maximum shunt voltage: 100 mV
8.2.3 Detailed Design Procedure
The transfer function of the circuit in 图8-1 is given in 方程式1:
V
= I
× R × Gain
SHUNT
(1)
OUT
LOAD
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English Data Sheet: SBOSAD6
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ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set from
0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
defined using 方程式2:
V
SHUNT_MAX
100 mV
1 A
R
=
=
= 100 mΩ
(2)
SHUNT
I
LOAD_MAX
Using 方程式 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV936x-Q1 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV936x-Q1
to produce the necessary output voltage is calculated using 方程式3:
V
− V
− V
OUT_MAX
OUT_MIN
Gain =
(3)
V
IN_MAX
IN_MIN
Using 方程式 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. 方程式 4 is
used to size the resistors, RF and RG, to set the gain of the TLV936x-Q1 to 49 V/V.
R
F
Gain = 1 +
(4)
R
G
Choosing RF as 5.76 kΩ, RG is calculated to be 120 Ω. RF and RG were chosen as 5.76 kΩ and 120 Ω because
the values are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also
be used. However, excessively large resistors generate thermal noise that exceeds the intrinsic noise of the op
amp. 图8-2 shows the measured transfer function of the circuit shown in 图8-1.
8.2.4 Application Curves
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
ILOAD (A)
1
图8-2. Low-Side, Current-Sense, Transfer Function
8.3 Power Supply Recommendations
The TLV936x-Q1 is specified for operation from 4.5 V to 40 V (±2.25 V to ±20 V); many specifications apply from
–40°C to 125°C.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum
Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
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English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in 图8-4, keeping RF and RG
close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
8.4.2 Layout Example
V-
C3
INPUT
OUTPUT
2
1
3
R3
+
–
4
C4
C2
V+
R1
C1
R2
图8-3. Schematic for Non-inverting Configuration Layout Example
GND
GND
OUTPUT
V-
GND
图8-4. Operational Amplifier Board Layout for Non-inverting Configuration - SC70 (DCK) Package
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
9 Device and Documentation Support
9.1 Device Support
9.1.1 Development Support
9.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
备注
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
9.1.1.2 TI Precision Designs
The TLV936x-Q1 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/
precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications
experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,
bill of materials, and measured performance of many useful circuits.
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers
• Texas Instruments, AN31 amplifier circuit collection application report
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
• Texas Instruments, Capacitive Load Drive Solution using an Isolation Resistor reference design
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TINA-TI™ is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
所有商标均为其各自所有者的财产。
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Product Folder Links: TLV9361-Q1 TLV9362-Q1 TLV9364-Q1
English Data Sheet: SBOSAD6
TLV9361-Q1, TLV9362-Q1, TLV9364-Q1
ZHCSRX5A –APRIL 2023 –REVISED MAY 2023
www.ti.com.cn
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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English Data Sheet: SBOSAD6
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9361QDBVRQ1
TLV9361QDCKRQ1
TLV9362QDGKRQ1
TLV9362QDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DGK
D
5
5
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
2W1H
1NL
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
VSSOP
SOIC
8
2S6T
8
T9362D
TLV9364QPWRQ1
TSSOP
PW
14
T9364PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV9361-Q1, TLV9362-Q1, TLV9364-Q1 :
Catalog : TLV9361, TLV9362, TLV9364
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9361QDBVRQ1
TLV9361QDCKRQ1
TLV9362QDGKRQ1
TLV9362QDRQ1
SOT-23
SC70
DBV
DCK
DGK
D
5
5
3000
3000
2500
3000
3000
180.0
178.0
330.0
330.0
330.0
8.4
9.0
3.2
2.4
5.3
6.4
6.9
3.2
2.5
3.4
5.2
5.6
1.4
1.2
1.4
2.1
1.6
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
VSSOP
SOIC
8
12.4
12.4
12.4
12.0
12.0
12.0
8
TLV9364QPWRQ1
TSSOP
PW
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9361QDBVRQ1
TLV9361QDCKRQ1
TLV9362QDGKRQ1
TLV9362QDRQ1
SOT-23
SC70
DBV
DCK
DGK
D
5
5
3000
3000
2500
3000
3000
210.0
180.0
366.0
356.0
356.0
185.0
180.0
364.0
356.0
356.0
35.0
18.0
50.0
35.0
35.0
VSSOP
SOIC
8
8
TLV9364QPWRQ1
TSSOP
PW
14
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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