TLVM23615 [TI]
3-36V 输入 1-6V 输出 1.5A 同步降压电源模块;
| 型号： | TLVM23615 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-36V 输入 1-6V 输出 1.5A 同步降压电源模块 电源电路 |
| 文件： | 总50页 (文件大小：2491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLVM23615, TLVM23625
ZHCSRM8A –FEBRUARY 2023 –REVISED MARCH 2023
TLVM236x5 采用HotRod™ QFN 封装的3V 至36V 输入、1V 至6V 输出、1.5A、
2.5A 同步降压转换器电源模块
1 特性
3 说明
• 功能安全型
TLVM236x5 是一款 1.5A 或2.5A、36V 输入同步直流/
直流降压电源模块，它在紧凑且易于使用的 3.5mm ×
4.5mm × 2mm、11 引脚 QFN 封装中整合了引线框上
倒装芯片 (FCOL) 封装、功率 MOSFET、集成电感器
和启动电容器。小型 HotRod™ QFN 封装技术可提高
热性能，确保可在高环境温度下工作。器件可通过电阻
反馈分压器配置为1V 至6V 输出。
– 有助于进行功能安全系统设计的文档
• 多功能同步降压直流/直流模块：
– 集成MOSFET、电感器、CBOOT 电容器和控制
器
– 3V 至36V 的宽输入电压范围
– 高达40V 的输入瞬态保护
– 结温范围为–40°C 至+125°C
– 4.5mm × 3.5mm × 2mm 超模压塑料封装
– 使用RT 引脚可在200kHz 至2.2MHz 范围内调
节频率
TLVM236x5 旨在满足常开型工业应用的低待机功耗要
求。自动模式可在轻负载运行时进行频率折返，在输入
电压(VIN) 为13.5V 时实现1.5µA 的空载电流消耗和高
轻负载效率。PWM 和 PFM 模式之间的无缝转换以及
低 MOSFET 导通电阻可确保在整个负载范围内提供出
色的效率。
• 在整个负载范围内具有超高效率：
– 在12V VIN、
5V VOUT、1MHz、IOUT = 2.5A 时效率高于88%
– 在VIN = 24V、
TLVM236x5 采用具有内部补偿的峰值电流模式架构，
用于维持稳定运行和超小的输入电容。RT 引脚可用于
在200kHz 至2.2MHz 范围内设置频率，来避开噪声敏
感频带。
VOUT = 5V、1MHz、IOUT = 2.5A 时效率高于
87%
– 在VIN = 13.5V 时待机IQ 低至1.5µA
• 针对超低EMI 要求进行了优化：
– Flip-Chip On Lead (FCOL) 封装
– 电感器和启动电容器集成
– 符合CISPR 11 B 类要求
• 输出电压和电流选项：
– 可调输出电压范围为1V 至6V
• 适用于可扩展电源：
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TLVM23615
TLVM23625
RDN（QFN-FCMOD，
11）
3.50mm × 4.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 与以下器件引脚兼容：
• TPSM365R6（65V，600mA）
• 使用TLVM236x5 并借助WEBENCH® Power
Designer 创建定制设计方案
2 应用
• 工厂自动化
• 测试和测量
• 电网基础设施
95
90
85
80
75
VIN
CIN
VIN
EN
SW
BOOT
TLVM236x5
VOUT
VOUT
COUT
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
5V, 2MHz
70
RFBT
65
60
55
50
FB
VCC
RT
CVCC
RFBB
PGOOD
GND
0.001
0.01
0.1
Load Current (A)
1
2.5
效率与输出电流的关系VIN = 24V
典型电路原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSCI2
TLVM23615, TLVM23625
ZHCSRM8A –FEBRUARY 2023 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................21
9 Application and Implementation..................................27
9.1 Application Information............................................. 27
9.2 Typical Application.................................................... 28
9.3 Best Design Practices...............................................37
9.4 Power Supply Recommendations.............................37
9.5 Layout....................................................................... 37
10 Device and Documentation Support..........................40
10.1 Device Support....................................................... 40
10.2 Documentation Support.......................................... 40
10.3 支持资源..................................................................41
10.4 Trademarks.............................................................41
10.5 静电放电警告.......................................................... 41
10.6 术语表..................................................................... 41
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 System Characteristics............................................... 9
7.7 Typical Characteristics..............................................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
8.2 Functional Block Diagram.........................................12
Information.................................................................... 42
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (February 2023) to Revision A (March 2023)
Page
• 删除了 TLVM23615 的产品预发布说明...............................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SNVSCI2
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5 Device Comparison Table
EXTERNAL SYNC
ORDERABLE
DEVICE
OUTPUT
VOLTAGE
OUTPUT
CURRENT
(MODE
FSW
SPREAD SPECTRUM
PART NUMBER (1)
Configuration)
No
Adjustable
with RT resistor
Adjustable
(1 V to 6 V)
TLVM23615
TLVM23625
TLVM23615RDNR
TLVM23625RDNR
1.5 A
(Default PFM
at light load)
No
No
No
Adjustable
with RT resistor
Adjustable
(1 V to 6 V)
2.5 A
(Default PFM
at light load)
(1) For more information on device orderable part numbers, see 节10.1.3.
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ZHCSRM8A –FEBRUARY 2023 –REVISED MARCH 2023
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6 Pin Configuration and Functions
MODE/SYNC (A)
RT (B) GND
FB
9
PGOOD
VCC
1
8
11
10
BOOT
SW
EN
2
3
7
6
VIN
SW
VOUT
4
5
A. Pin 11 factory-set for fixed switching frequency MODE/SYNC variants only.
B. See Device Comparison Table for more details. Pin 11 trimmed and factory-set for externally adjustable switching frequency RT variants
only.
图6-1. RDN Package, 11-Pin QFN-FCMOD , Top View (All Variants)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified
window thresholds. A 10-kΩto 100-kΩpullup resistor is required to a suitable pullup voltage. If not used, this
pin can be left open or connected to GND.
1
PGOOD
A
High = power OK, Low = power bad. PGOOD pin goes low when EN = Low.
Precision enable input pin. High = ON, Low = OFF. Can be connected to VIN. Precision enable allows the pin to
be used as an adjustable UVLO. Can be connected directly to VIN. The module can be turned off by using an
open-drain or collector device to connect this pin to GND. An external voltage divider can be placed between
this pin, GND, and VIN to create an external UVLO.Do not float this pin.
2
EN
A
Input supply voltage. Connect the input supply to these pins. Connect a high-quality bypass capacitor or
capacitors directly to this pin and GND in close proximity to the module. Refer to 节9.5.2 for input capacitor
placement example.
3
4
VIN
P
P
Output voltage. The pin is connected to the internal output inductor. Connect the pin to the output load and
connect external output capacitors between the pin and GND.
VOUT
Power module switch node. Do not place any external component on this pin or connect to any signal. The
amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
5, 6
7
SW
BOOT
VCC
P
P
P
Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected from this
pin to SW within the module to provide the bootstrap voltage.
Internal LDO output. Used as supply to internal control circuits. Do not connect to external loads. Can be used
as logic supply for power-good flag. Connect a high-quality 1-µF capacitor from this pin to GND.
8
Feedback input. For the adjustable output, connect the mid-point of the feedback resistor divider to this pin.
Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect
the lower resistor (RFBB) of the feedback divider to GND. When connecting with feedback resistor divider, keep
this FB trace short and as small as possible to avoid noise coupling. See 节9.5.2 for a feedback resistor
placement.
9
FB
A
10
11
GND
RT
G
A
Power ground terminal. Connect to system ground. Connect to CIN with short, wide traces.
When the part is configured as the RT pin variant, the switching frequency in the part can be adjusted from 200
kHz to 2.2 MHz based on the resistor value connected between RT and GND.
A = Analog, P = Power, G = Ground
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English Data Sheet: SNVSCI2
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7 Specifications
7.1 Absolute Maximum Ratings
Limits apply over TJ = –40°C to 125°C (unless otherwise noted). ((1))
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
40
UNIT
V
VIN to GND
CBOOT to SW
5.5
5.5
40
V
RT to GND
Input voltage
V
EN to GND
V
FB to GND
PG to GND
VCC to GND
16
V
20
V
5.5
40
V
–0.3
–0.3
–0.3
–
Output voltage
SW to GND((3))
V
VOUT to GND
16
V
Input current
PG
10
mA
°C
°C
°C
TJ
Junction temperature
Ambient temperature
Storage temperature
125
105
150
–40
–40
–55
TA
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤200 ns with a duty cycle of ≤0.01%.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001((1))
±2000
V
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per ANSI/ESDA/
JEDEC JS-002((2))
±1000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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English Data Sheet: SNVSCI2
TLVM23615, TLVM23625
ZHCSRM8A –FEBRUARY 2023 –REVISED MARCH 2023
www.ti.com.cn
7.3 Recommended Operating Conditions
Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN
3
NOM
MAX
UNIT
V
Input voltage
Output voltage
Output current
Output current
Frequency
TJ
VIN (Input voltage range after start-up)
Output Adjustment Range((1))
TLVM23625 IOUT((2))
36
6
1
V
0
2.5
A
TLVM23615 IOUT((2))
0
1.5
A
FSW set by RT
200
–40
–40
2200
125
105
kHz
°C
°C
Operating junction temperature
Operating ambient temperature
TA
(1) Under no conditions should the output voltage be allowed to fall below zero volts.
(2) Maximum continuous DC current may be derated when operating with high switching frequency or high ambient temperature. Refer to
the Typical Characteristics section for details.
7.4 Thermal Information
TLVM23615 / TLVM23625
THERMAL METRIC ((1))
RDN
11 Pins
22
UNIT
RθJA
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance (TLM23625EVM )
Junction-to-ambient thermal resistance (JESD 51-7)
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
54.1
52.1
16.6
8.1
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.3
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report. The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design
purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent
the performance obtained in an actual application.
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English Data Sheet: SNVSCI2
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7.5 Electrical Characteristics
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, FSW = 1000 kHz (unless otherwise noted). Minimum and
maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm
and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Before Start-up
3.2
3.35
2.7
1.2
0.3
3.5
3
V
V
VIN
Input voltage rising threshold
Once Operating
2.45
IQ_VIN
Input operating quiescent current (non-switching)
VIN shutdown quiescent current
TA = 25°C, VEN = 3.3 V, VFB = 1.5 V
VEN = 0 V, TA = 25°C
µA
µA
ISDN_VIN
ENABLE
VEN_RISE
VEN_HYS
VEN_WAKE
ILKG-EN
EN voltage rising threshold
EN voltage hysteresis
1.16
0.275
0.5
1.23
0.353
0.7
1.3
0.404
1
V
V
EN wake-up threshold
V
Enable pin input leakage current
VEN = VIN = 24 V
10
nA
INTERNAL LDO VCC
VCC
Internal LDO VCC output voltage
VFB = 0 V, IVCC = 1 mA
TA = 25°C, IOUT = 0 A
3.1
3.3
1.0
3.5
+1
V
FEEDBACK
VFB
Feedback voltage
V
%
Over the VIN range, VOUT = 1 V, IOUT = 0
A, FSW = 200 kHz
VFB_ACC
Feedback voltage accuracy
Input current into FB pin
–1
IFB
Adjustable configuration, VFB = 1.0 V
10
nA
CURRENT
IL_HS
High-side switch current limit (TLVM23625)
Low-side switch current limit (TLVM23625)
Negative current limit (TLVM23625)
Minimum peak current limit (TLVM23625)
High-side switch current limit (TLVM23615)
Low-side switch current limit (TLVM23615)
Negative current limit (TLVM23615)
Minimum peak current limit (TLVM23615)
Zero-cross current limit
Duty cycle approaches 0%
4.2
4.9
2.9
–2
0.6
3
5.5
A
A
IL_LS
2.38
3.42
IL_NEG
IPEAKMIN
IL_HS
A
Auto mode
A
Duty cycle approaches 0%
2.58
1.44
3.42
2.06
A
IL_LS
1.75
–2
0.4
80
A
IL_NEG
IPEAKMIN
IZC
A
Auto mode
Auto mode
A
mA
Ratio of FB voltage to in-regulation FB voltage to
enter hiccup
VHICCUP
tW
Not during soft start
40
50
%
Short circuit wait time ("hiccup" time before soft start)
30
2
75
ms
((1))
SOFT-START
tSS
Time from first SW pulse to VREF at 90%
3.5
4.6
ms
VIN ≥4.2 V
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English Data Sheet: SNVSCI2
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www.ti.com.cn
7.5 Electrical Characteristics (continued)
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, FSW = 1000 kHz (unless otherwise noted). Minimum and
maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm
and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER GOOD
PGOV
PG upper threshold - rising
PG lower threshold - falling
% of VOUT setting (adjustable output)
% of VOUT setting (adjustable output)
104
89
108
91
111
%
%
PGUV
94.2
PG upper threshold hysteresis for OV
PG upper threshold hysteresis for UV
Input voltage for valid PG output
Low level PG function output voltage
Low level PG function output voltage
Delay time to PG high signal
% of VOUT setting
2
2
2.4
3.3
2.8
4.6
1.5
0.4
0.4
4
%
%
V
PGHYS
% of VOUT setting
VIN_PG_VALID
VPG_LOW
VPG_LOW
tPG_FLT_RISE
tRESET_FILTER
RPGD
RPGD_PU = 10 kΩ, VEN = 0 V
2 mA pullup to PG pin, VEN = 3.3 V
2 mA pullup to PG pin, VEN = 3.3 V
V
V
1.35
25
2.5
40
ms
µs
Ω
PGOOD deglitch delay at falling edge
PGOOD ON resistance
75
VEN = 3.3 V, 200 uA pullup current
VEN = 0 V, 200 uA pullup current
100
100
RPGD
PGOOD ON resistance
Ω
SWITCHING FREQUENCY
Switching frequency range by SYNC(Mode/Sync
variant)
fSYNC_RANGE
200
2500
kHz
fADJ_RANGE
fSW_RT1
SYNCHRONIZATION
Switching frequency range by RT (RT variant)
200
2200
2300
kHz
kHz
2.2 MHZ switching frequency programmed by RT
2000
2200
2.1
RRT = 0 kΩ (RT pin tied to GND)
tB
Blanking of EN after rising or falling edges(1)
4
28
µs
POWER STAGE
Voltage on CBOOT pin compared to SW which will
turn off high-side switch
VBOOT_UVLO
V
tON_MIN
tON_MAX
tOFF_MIN
Minimum ON pulse width((1))
Maximum ON pulse width((1))
Minimum OFF pulse width
FPWM mode, VOUT = 1 V, IOUT = 1 A
HS timeout in dropout
65
9
75
13
85
ns
µs
ns
6
VIN = 4 V, IOUT = 1 A
60
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
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7.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Input supply current when in
regulation
VIN = 24 V, VOUT = 3.3 V(RFBT = 23.2 kΩ), VEN = VIN, FSW = 1000 kHz,
IIN
6.9
7
μA
μA
IOUT = 0 A,PFM
Input supply current when in
regulation
VIN = 24 V, VOUT = 5 V(RFBT = 40.2 kΩ), VEN = VIN, FSW = 1000 kHz,
IOUT = 0 A,PFM
IIN
OUTPUT VOLTAGE
3
VFB
Load regulation
VOUT = 3.3 V, VIN = 24 V, IOUT = 0.4 A to full load(FPWM)
VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 2.5 A
mV
mV
mV
10
VFB
Line regulation
Load transient
VOUT = 3.3 V, VIN = 24 V, IOUT = 1 A to 2.5 A @ 2 A/μs,
COUT(derated) = 32 uF
VOUT
100
EFFICIENCY
86
84
88
86
VOUT = 3.3 V, VIN = 12 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
VOUT = 3.3 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
VOUT = 5 V, VIN = 24 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
VOUT = 5 V, VIN = 36 V, IOUT = 2.5 A, VLDOIN = VOUT, FSW = 1 MHz
%
%
%
%
Efficiency
η
Thermal Shutdown
TSDN
Thermal shutdown threshold
Thermal shutdown hysteresis
Temperature rising
158
168
15
186
20
°C
°C
THYST
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7.7 Typical Characteristics
Unless otherwise specified, the following conditions apply: TA = 25°C , VIN = 13.5 V.
1
0.9995
0.999
0.7
0.6
0.5
0.4
0.3
0.2
VIN = 13.5V
VIN = 24V
0.9985
0.998
0.9975
-40
-10
20
50
80
105
-40
-10
20
50
80
105
Temperature (°C)
Temperature (°C)
图7-2. Feedback Voltage (VFB) Accuracy Versus Temperature
图7-1. Shutdown Supply Current (ISDN_VIN) Versus Temperature
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8 Detailed Description
8.1 Overview
The TLVM236x5 is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 36-V
supply voltage. The device is intended for step-down conversions from 5-V, 12-V, 24-V, and 36-V supply rails.
With an integrated buck converter, inductor, and boot capacitor, the TLVM236x5 delivers up to 2.5-A DC load
current with high efficiency and ultra-low input quiescent current in a compact solution size. Control-loop
compensation is not required, reducing design time and external component count.
The TLVM236x5 operates over a wide range of switching frequencies and duty ratios. If the minimum ON-time or
OFF-time cannot support the desired duty ratio, the switching frequency is reduced automatically, maintaining
the output voltage regulation. In addition, the PGOOD output feature with built-in delayed release allows the
elimination of the reset supervisor in many applications.
With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin or an external clock signal,
the TLVM236x5 incorporates specific features to improve EMI performance in noise-sensitive applications:
• An optimized package that incorporates flip chip on lead (FCOL) technology and pinout design enables a
shielded switch-node layout that mitigates radiated EMI.
• Clock synchronization and FPWM mode enable constant switching frequency across the load current range.
• Inductor and boot capacitor integration
The TLVM236x5 module also includes inherent protection features for robust system requirements:
• An open-drain PGOOD indicator for power-rail sequencing and fault reporting
• Precision enable input with hysteresis, providing:
– Programmable line undervoltage lockout (UVLO)
– Remote ON and OFF capability
• Internally fixed output-voltage soft start with monotonic start-up into pre-biased loads
• Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
• Thermal shutdown with automatic recovery
These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement
is designed for a simple layout, requiring few external components. See Layout for a layout example.
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8.2 Functional Block Diagram
VCC
MODE/SYNC VARIANTS
ONLY
MODE
CLOCK
/SYNC
OSCILLATOR
SLOPE
COMPENSATION
RT
LDO
VCC UVLO
TSD
RT VARIANTS ONLY
VIN
THERMAL
SHUTDOWN
FSW FOLDBACK
SYS ENABLE
BOOT
ENABLE
EN
0.1
F
HS CURRENT SENSE
VIN
ERROR
AMPLIFIER
–
+
+
–
FB
COMP
MAX
TSD
+
CLOCK
SW
SW
and
MIN
LIMITS
+
HS CURRENT
2.2 H
–
VOUT
LIMIT
SYS ENABLE
SYS ENABLE
CONTROL
LOGIC and
DRIVER
SOFT-
START
and
TSD
GND
VREF
BANDGAP
VCC UVLO
LS CURRENT
LIMIT
–
+
–
+
MIN
LS CURRENT
LIMIT
FB
PGOOD
VOUT UV/OV
FPWM or AUTO
VOUT UV/OV
LS CURRENT SENSE
PGOOD
LOGIC
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8.3 Feature Description
8.3.1 Input Voltage Range
With a steady-state input voltage range from 3 V to 36 V, the TLVM236x5 module is intended for step-down
conversions from typical 12-V to 36-V input supply rails, as example. The schematic circuit in 图 8-1 shows all
the necessary components to implement a TLVM236x5-based buck regulator using a single input supply.
VIN
EN
SW
VIN = 3 V to 36 V
CIN
BOOT
TLVM236x5
VOUT = 1 V to 6 V
IOUT(max) = 2.5 A
COUT
VOUT
RFBT
FB
VCC
RT
CVCC
VCC
RPGOOD
RFBB
PGOOD
GND
PGOOD
indicator
RRT
图8-1. TLVM236x5 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
Take extra care to ensure that the voltage at the VIN pin does not exceed the absolute maximum voltage rating
of 40 V during line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute maximum
ratings can damage the IC.
8.3.2 Output Voltage Selection
The TLVM236x5 output voltage can be set by two external resistors, RFBT and RFBB. Connect RFBT between
VOUT at the regulation point and the FB pin. Connect RFBB between the FB pin and AGND.
The TLVM236x5 has an adjustable output voltage range from 1.0 V to 6 V. To ensure that the power module
regulates to the desired output voltage, the typical minimum value for the parallel combination of RFBT and RFBB
is 5 kΩwhile the typical maximum value is 10 kΩas shown in 方程式 3. 方程式 2 and 方程式 3 can be used as
a starting point to determine the value of RFBT. Reference 表 8-1 for a list of acceptable resistor values for
various output voltages.
5 kΩ < R
R
≤ 10 kΩ
(1)
(2)
FBT
FBB
V
V
OUT
R
kΩ = R
kΩ ×
OUT
– 1
FBT
FBT
FBB
1 V
V
R
≤ 10 kΩ ×
(3)
1 V
For adjustable output options, an addition feedforward capacitor, CFF, in parallel with the RFBT can be needed to
optimize the transient response. See CFF Selection for additional information.
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VOUT
RFBT
FB
RFBB
AGND
图8-2. Setting Output Voltage for Adjustable Output Variant
表8-1. Standard RFBT Values, Recommended FSW and Minimum COUT
RFBT (kΩ) (1)
VOUT (V)
1.0
RECOMMENED FSW (kHz)
COUT(MIN) (µF) (EFFECTIVE)
Short
2
400
500
500
600
600
750
750
800
1000
300
200
160
120
100
65
1.2
1.5
4.99
8.06
10
1.8
2.0
2.5
15
3.0
20
50
3.3
23.2
40.2
40
5.0
25
(1) RFBB = 10 kΩ
8.3.3 Input Capacitors
Input capacitors are required to limit the input ripple voltage to the module due to switching-frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over a
wide temperature range. 方程式 4 gives the input capacitor RMS current. The highest input capacitor RMS
current occurs at D = 0.5, at which point, the RMS current rating of the capacitors must be greater than half the
output current.
2
∆ I
2
OUT
L
I
=
D × I
× 1 − D +
(4)
CIN, rms
12
where
• D = VOUT / VIN is the module duty cycle.
Ideally, the DC and AC components of the input current to the buck stage are provided by the input voltage
source and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source
current of amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input
capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resulting
capacitive component of the AC ripple voltage is a triangular waveform. Together with the ESR-related ripple
component, 方程式5 gives the peak-to-peak ripple voltage amplitude.
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I
× D × 1 − D
OUT
∆ V
=
+ I
× R
ESR
(5)
IN
OUT
F
× C
SW
IN
方程式6 gives the input capacitance required for a particular load current.
D × 1 − D × I
OUT
× I
C
≥
(6)
IN
F
×
∆ V − R
SW
IN ESR OUT
where
• ΔVIN is the input voltage ripple specification.
The TLVM236x5 requires a minimum of a 4.7-µF ceramic type input capacitance. Only use high-quality ceramic
type capacitors with sufficient voltage and temperature rating. The ceramic input capacitors provide a low
impedance source to the power module in addition to supplying the ripple current and isolating switching noise
from other circuits. Additional capacitance can be required for applications with transient load requirements. The
voltage rating of the input capacitors must be greater than the maximum input voltage. To compensate for the
derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing
multiple capacitors in parallel. 表8-2 includes a preferred list of capacitors by vendor.
表8-2. Recommended Input Capacitors
CAPACITOR CHARACTERISTICS
VENDOR (1)
DIELECTRIC
PART NUMBER
CASE SIZE
VOLTAGE RATING (V)
CAPACITANCE (µF) (2)
TDK
Wurth
X7R
X7R
C3225X7R1H475K2 50AB
885012209048
1210
1210
0402
HA0
50
50
50
50
4.7
4.7
0.1
100
Murata
X5R
GRM155R61H104M E14D
EMVY500ADA101M HA0G
Chemi-Con
Electrolytic
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
8.3.4 Output Capacitors
表 8-1 lists the TLVM236x5 minimum amount of required output capacitance. The effects of DC bias and
temperature variation must be considered when using ceramic capacitance. For ceramic capacitors, the package
size, voltage rating, and dielectric material contribute to differences between the standard rated value and the
actual effective value of the capacitance.
When adding additional capacitance above COUT(MIN), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See 表8-3 for a preferred list of output capacitors by vendor.
表8-3. Recommended Output Capacitors
CAPACITOR CHARACTERISTICS
TEMPERATURE
COEFFICIENT
VENDOR (1)
PART NUMBER
CASE SIZE
VOLTAGE (V)
CAPACITANCE (µF) (2)
TDK
TDK
X7R
X7R
X7R
X7R
CNA6P1X7R1E226M250AE
CGA6P1X7R1C226 M250AC
885012209028
1210
1210
1210
1210
25
16
25
16
22
22
10
10
Wurth
Wurth
885012209014
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
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8.3.5 Enable, Start-Up, and Shutdown
Voltage at the EN pin controls the start-up or remote shutdown of the TLVM236x5. The part stays shut down as
long as the EN pin voltage is less than VEN-WAKE.With the voltage at the EN pin greater than VEN-WAKE, the
device enters device standby mode and the internal LDO powers up to generate VCC. As the EN voltage
increases further, approaching VEN-RISE, the device finally starts to switch, entering start-up mode with a soft
start. During the device shutdown process, when the EN input voltage measures less than (VEN-RISE–VEN-HYST),
the regulator stops switching and re-enters device standby mode. Any further decrease in the EN pin voltage,
below VEN-WAKE, and the device is then firmly shut down. The high-voltage compliant EN input pin can be
connected directly to the VIN input pin if remote precision control is not needed. The EN input pin must not be
allowed to float.
The various EN threshold parameters and their values are listed in the Electrical Characteristics. 图 8-3 shows
the precision enable behavior and 图 8-4 shows a typical remote EN start-up waveform in an application. After
EN goes high, after a delay of about 1 ms, the output voltage begins to rise with a soft start and reaches close to
the final value in about 3.5 ms (tss). After a delay of about 2.5 ms (tPG_FLT_RISE), the PGOOD flag goes high.
During start-up, the device is not allowed to enter FPWM mode until the soft-start time has elapsed. This time is
measured from the rising edge of EN.
EN
VEN_RISE
VEN_HYS
VEN-WAKE
VCC
3.3V
0
VOUT
VOUT
0
图8-3. Precision Enable Behavior
VOUT (1 V/DIV)
PGOOD (1 V/DIV)
EN (5 V/DIV)
2 ms/DIV
图8-4. Enable Start-Up VIN = 24 V, VOUT = 3.3 V, IOUT = 2.5 A
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External UVLO through EN Pin
In some cases, an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in 图 8-5. The input voltage at which the device turns on is designated
as VON while the turn-off voltage is VOFF. First, a value for RENB is chosen in the range of 10 kΩto 100 kΩ, then
方程式7and 方程式8 are used to calculate RENT and VOFF, respectively.
VIN
RENT
EN
RENB
AGND
图8-5. Setup for External UVLO Application
V
ON
R
=
− 1 × R
(7)
(8)
ENT
ENB
V
EN_RISE
V
EN_HYS
V
= V × 1 −
OFF
ON
V
EN_RISE
where
• VON is the VIN turn-on voltage.
• VOFF is the VIN turn-off voltage.
• Refer to electrical characteristics table for other terms.
8.3.6 Switching Frequency (RT)
The select orderables in the TLVM236x5 family with the RT pin allow power designers to set any desired
operating frequency between 200 kHz and 2.2 MHz in their applications. See 图 8-6 to determine the resistor
value needed for the desired switching frequency or simply select from 表8-5. The RT pin and the
MODE/SYNC pin variants share the same pin location. The power supply designer can either use the RT pin
variant and adjust the switching frequency of operation as warranted by the application or use the MODE/SYNC
variant and synchronize to an external clock signal. See 表8-4 for selection on programming the RT pin.
表8-4. RT Pin Setting
RT INPUT
VCC
SWITCHING FREQUENCY
1 MHz
GND
2.2 MHz
RT to GND
Adjustable according to 图8-6
No Switching
Float (Not Recommended)
18286
RT =
Fsw1.021
(9)
where
• RT is the frequency setting resistor value (kΩ).
• FSW is the switching frequency (kHz).
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80
70
60
50
40
30
20
10
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
图8-6. RT Values vs Frequency
The switching frequency must be selected based on the output voltage setting of the device. See 表 8-5 for RRT
resistor values and the allowable output voltage range for a given switching frequency for common input
voltages.
表8-5. Switching Frequency Versus Output Voltage (IOUT = 2.5 A)
VIN = 5 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
RRT
(kΩ)
FSW (kHz)
VOUT RANGE (V)
VOUT RANGE (V)
VOUT RANGE (V)
VOUT RANGE (V)
MIN
1
MAX
1.75
2
MIN
1
MAX
1.5
4
MIN
1
MAX
MIN
1
MAX
200
400
81.6
40.2
26.7
19.8
15.8
13.2
11.3
9.76
8.66
7.77
7.06
1.25
3
1.25
2.5
4
1
1
1
1.25
2
600
1
2.5
3
1
5
1.25
1.5
2
5
800
1
1
5.5
6
6
2.25
2.5
3
6
1000
1200
1400
1600
1800
2000
2200
1
3.5
3.5
3.5
3.5
3
1
6
6
1
1.5
1.5
1.5
1.5
1.5
1.5
6
2.5
3
6
6
1
6
6
3.5
4
6
1
6
3
6
6
1
6
3.5
3.5
4.5
6
5
6
1
3
6
6
5.5
6
6
1
3
6
6
6
8.3.7 Power-Good Output Operation
The power-good feature using the PGOOD pin of the TLVM236x5 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output remains low under device fault
conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents
false flag operation for any short duration excursions in the output voltage, such as during line and load
transients. Output voltage excursions lasting less than tRESET_FILTER do not trip the power-good flag. Power-good
operation can best be understood in reference to 图8-7. 表8-6 gives a more detailed breakdown of the PGOOD
operation. Here, VPG is defined as the PGUV scaled version of VOUT (target regulated output voltage) and
UV
VPG as the PGHYS scaled version of VOUT, where both PGUV and PGHYS are listed in Electrical Characteristics.
DuriHnYgS the initial power up, a total delay of 6 ms (typical) is encountered from the time VEN_RISE is triggered to
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the time that the power-good is flagged high. This delay only occurs during the device start-up and is not
encountered during any other normal operation of the power-good function. When EN is pulled low, the power-
good flag output is also forced low. With EN low, power-good remains valid as long as the input voltage
(VIN_PG_VALID is ≥1.5 V (max)).
The power-good output scheme consists of an open-drain n-channel MOSFET, which requires an external pullup
resistor connected to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an
appropriate resistor, as desired. If this function is not needed, the PGOOD pin can be open or grounded. Limit
the current into this pin to ≤4 mA.
Input
Output
Voltage Voltage
Input Voltage
tRESET_FILTER
tPG_FLT_RISE
tPG_FLT_RISE
tRESET_FILTER
tRESET_FILTER
VPG
HYS
tRESET_FILTER
VPG (falling)
UV
VIN (rising)
VIN_HYS
VIN_PG_VALID
GND
VOUT
PGOOD
Small glitches
do not cause
reset to signal
a fault
PG may not
be valid if
input is below
VIN_PG-VALID
Small glitches do not
reset tPG_FLT_RISE timer
PG may not be
valid if input is
below VIN_PG-VALID
Startup
delay
图8-7. Power-Good Operation (OV Events Not Included)
表8-6. Fault Conditions for PGOOD (Pull Low)
FAULT CONDITION ENDS (AFTER WHICH tPGOOD_ACT MUST PASS
BEFORE PGOOD OUTPUT IS RELEASED)
FAULT CONDITION INITIATED
Output voltage in regulation:
VOUT < V
AND t > tRESET_FILTER
PGUV
V
+ V
< VOUT < V
- V
PGUV
PGHYS
PGOV PGHYS
VOUT > VPG AND t > tRESET_FILTER
Output voltage in regulation
OV
TJ > TSDN
TJ < TSDN-THYST AND output voltage in regulation
EN > VEN_RISE AND output voltage in regulation
EN < VEN_RISE - VEN_HYS
8.3.8 Internal LDO, VCC and VOUT/FB Input
The TLVM236x5 uses the internal LDO output and the VCC pin for all internal power supply. The VCC rail
typically measures 3.3 V. During start-up, VCC momentarily exceeds the normal operating voltage, then drops to
the normal operating voltage.
8.3.9 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
The high-side switch driver circuit requires a bias voltage higher than VIN to ensure the HS switch is turned ON.
There is an internal 0.1-μF capacitor connected between BOOT and SW that operates as a charge pump to
boost the voltage on the BOOT terminal to (SW + VCC). The boot diode is integrated on the TLVM236x5 die to
minimize physical solution size. The BOOT rail has an UVLO setting. This UVLO has a threshold of VBOOT-UVLO
and is typically set at 2.1 V. If the BOOT capacitor is not charged above this voltage with respect to the SW pin,
then the part initiates a charging sequence, turning on the low-side switch before attempting to turn on the high-
side device.
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8.3.10 Soft Start and Recovery from Dropout
When designing with the TLVM236x5, slow rise in output voltage due to recovery from dropout and soft start
must be considered as a two separate operating conditions, as shown in 图8-8 and 图8-9. Soft start is triggered
by any of the following conditions:
• Power is applied to the VIN pin of the device, releasing undervoltage lockout.
• EN is used to turn on the device.
• Recovery from shutdown due to overtemperature protection
After soft start is triggered, the power module takes the following actions:
• The reference used in the power module to regulate the output voltage is slowly ramped up. The net result is
that output voltage, if previously 0 V, takes tSS to reach 90% of the desired value.
• Operating mode is set to auto mode of operation, activating the diode emulation mode for the low-side
MOSFET. This allows start-up without pulling the output low. This is true even when there is a voltage already
present at the output during a pre-bias start-up.
If selected, FPWM
is enabled only
after completion of
tSS
If selected, FPWM
is enabled only
after completion of
tSS
Triggering event
Triggering event
tEN
tSS
tEN
tSS
V
V
VEN
VEN
VOUT Set
Point
VOUT Set
Point
VOUT
VOUT
90% of
VOUT Set
Point
90% of
VOUT Set
Point
t
t
0 V
0 V
Time
Time
图8-8. Soft Start With and Without Pre-bias Voltage
8.3.10.1 Recovery from Dropout
Any time the output voltage falls more than a few percent, output voltage ramps up slowly. This condition, called
graceful recovery from dropout in this document, differs from soft start in two important ways:
• The reference voltage is set to approximately 1% above what is needed to achieve the existing output
voltage.
• If the device is set to FPWM, it continues to operate in that mode during its recovery from dropout. If output
voltage were to suddenly be pulled up by an external supply, the TLVM236x5 can pull down on the output.
Note that all protections that are present during normal operation are in place, preventing any catastrophic
failure if output is shorted to a high voltage or ground.
V
Load
current
VOUT Set
Point
and max
output
Slope
VOUT
the same
as during
soft start
current
t
Time
图8-9. Recovery from Dropout
Whether output voltage falls due to high load or low input voltage, after the condition that causes output to fall
below its set point is removed, the output climbs at the same speed as during start-up. 图8-9 shows an example
of this behavior.
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8.3.11 Overcurrent Protection (Hiccup Mode)
The TLVM236x5 is protected from overcurrent conditions by using cycle-by-cycle current limiting circuitry on both
the high-side (HS) and low-side (LS) MOSFETs. The current is compared every switching cycle to the current
limit threshold. During an overcurrent condition, the output voltage decreases with reduced switching frequency.
High-side MOSFET overcurrent protection is implemented by the typical peak-current mode control scheme. The
HS switch current is sensed when the HS is turned on after a short blanking time. The HS switch current is
compared to the minimum of a fixed current set point or the output of the internal error amplifier loop minus the
slope compensation every switching cycle. Because the output of the internal error amplifier loop has a
maximum value and slope compensation increases with duty cycle, HS current limit decreases with increased
duty factor if duty cycle is above 35%.
When the LS switch is turned on, the current going through it is also sensed and monitored. Like the high-side
device, the low-side device has a turn-off commanded by the internal error amplifier loop. In the case of the low-
side device, turn-off is prevented if the current exceeds this value, even if the oscillator normally starts a new
switching cycle. Also like the high-side device, there is a limit on how high the turn-off current is allowed to be.
This is called the low-side current limit. If the LS current limit is exceeded, the LS MOSFET stays on and the HS
switch is not to be turned on. The LS switch is turned off after the LS current falls below this limit and the HS
switch is turned on again as long as at least one clock period has passed since the last time the HS device has
turned on.
If, during current limit, the voltage on the FB input falls below about 0.4 V (VHICCUP) due to a short circuit, the
device enters hiccup mode. In this mode, the device stops switching for tW or about 50 ms, and then goes
through a normal re-start with soft start. If the short-circuit condition remains, the device runs in current limit for
about 5 ms (typical) and then shuts down again. This cycle repeats as long as the short-circuit condition persists.
8.3.12 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal switches when the device junction
temperature exceeds 168°C (typical). Thermal shutdown does not trigger below 158°C (minimum). After thermal
shutdown occurs, hysteresis prevents the part from switching until the junction temperature drops to
approximately 153°C (typical). When the junction temperature falls below 153°C (typical), the TLVM236x5
attempts another soft start.
While the TLVM236x5 is shut down due to high junction temperature, power continues to be provided to VCC. To
prevent overheating due to a short circuit applied to VCC, the LDO that provides power for VCC has reduced
current limit while the part is disabled due to high junction temperature. The LDO only provides a few
milliamperes during thermal shutdown.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage is below 0.7 V
(typical), the power module does not have any output voltage and the device is in shutdown mode. In shutdown
mode, the quiescent current drops to typically 250 nA.
8.4.2 Standby Mode
The internal LDO has a lower EN threshold than the output EN threshold. When the EN pin voltage is above 1 V
(maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCC
voltage at 3.3 V typical. The internal power MOSFETs of the SW node remain off unless the voltage on EN pin
goes above its precision enable threshold. The TLVM236x5 also employs UVLO protection.
8.4.3 Active Mode
The TLVM236x5 is in active mode whenever the EN pin is above VEN_RISE, VIN is greater than VIN (min), and no
other fault conditions are present. The simplest way to enable the operation is to connect the EN pin to VIN,
which allows self start-up when the applied input voltage exceeds the minimum VIN (min).
Depending on the load current, input voltage, and output voltage, the TLVM236x5 is in one of five modes:
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• Continuous conduction mode (CCM) with fixed switching frequency (fSW) when load current is above half of
the inductor current ripple
• Auto mode - Light Load Operation: PFM where fSW is decreased at very light load
• FPWM mode - Light Load Operation: Continuous conduction mode (CCM) when the load current is lower
than half of the inductor current ripple
• Minimum on time: At high input voltage and low output voltages, the fSW is reduced to maintain regulation
• Dropout mode: When fSW is reduced to minimize voltage dropout
8.4.3.1 CCM Mode
The following operating description of the TLVM236x5 refers to Functional Block Diagram. In CCM, the
TLVM236x5 supplies a regulated output voltage by turning on the internal high-side (HS) and low-side (LS)
switches with varying duty cycle (D). During the HS switch on time, the SW pin voltage, VSW, swings up to
approximately VIN, and the inductor current increases with a linear slope. The HS switch is turned off by the
control logic. During the HS switch off time, tOFF, the LS switch is turned on. Inductor current discharges through
the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The buck
module converter loop adjusts the duty cycle to maintain a constant output voltage. D is defined by the on time
of the HS switch over the switching period:
D = TON / TSW
(10)
In an ideal buck module converter where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage:
D = VOUT / VIN
(11)
8.4.3.2 Auto Mode –Light-Load Operation
The TLVM236x5 can have two behaviors while lightly loaded. One behavior, called auto mode operation, allows
for seamless transition between normal current mode operation while heavily loaded and highly efficient light-
load operation. The other behavior, called FPWM mode, maintains full frequency even when unloaded. Which
mode the TLVM236x5 operates in depends on which variant from this family is selected. Note that all parts
operate in FPWM mode when synchronizing frequency to an external signal.
The light-load operation is employed in the TLVM236x5 only in auto mode. The light load operation employs two
techniques to improve efficiency:
• Diode emulation, which allows DCM operation (See 图8-10)
• Frequency reduction (See 图8-11)
Note that while these two features operate together to improve light load efficiency, they operate independently
of each other.
8.4.3.2.1 Diode Emulation
Diode emulation prevents reverse current through the inductor which potentially requires a lower frequency
needed to regulate given a fixed peak inductor current. Diode emulation also limits ripple current as frequency is
reduced. With a fixed peak current, as output current is reduced to zero, frequency must be reduced to near zero
to maintain regulation.
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tON
VOUT
VIN
D =
VSW
<
tSW
VIN
tOFF
tON
tHIGHZ
0
t
tSW
iL
ILPK
IOUT
0
t
In auto mode, the low-side device is turned off after SW node current is near zero. As a result, after output current is less than half of
what inductor ripple can be in CCM, the part operates in DCM which is equivalent to the statement that diode emulation is active.
图8-10. PFM Operation
The TLVM236x5 has a minimum peak inductor current setting (see IPEAKMIN in Electrical Characteristics) while in
auto mode. After current is reduced to a low value with fixed input voltage, on time is constant. Regulation is
then achieved by adjusting frequency. This mode of operation is called PFM mode regulation.
8.4.3.2.2 Frequency Reduction
The TLVM236x5 reduces frequency whenever output voltage is high. This function is enabled whenever the
internal error amplifier compensation output, COMP, an internal signal, is low and there is an offset between the
regulation set point of VOUT/FB and the voltage applied to VOUT/FB. The net effect is that there is larger output
impedance while lightly loaded in auto mode than in normal operation. Output voltage must be approximately 1%
high when the part is completely unloaded.
VOUT
Current
Limit
1% Above
Set point
VOUT Set
Point
IOUT
Output Current
0
In auto mode, after output current drops below approximately 1/10th the rated current of the part, output resistance increases so that
output voltage is 1% high while the buck is completely unloaded.
图8-11. Steady State Output Voltage Versus Output Current in Auto Mode
In PFM operation, a small DC positive offset is required on the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed on VOUT. If the DC offset on VOUT is not acceptable, a
dummy load at VOUT or FPWM mode can be used to reduce or eliminate this offset.
8.4.3.3 FPWM Mode –Light-Load Operation
In FPWM mode, frequency is maintained while the output is lightly loaded. To maintain frequency, a limited
reverse current is allowed to flow through the inductor. Reverse current is limited by negative current limit
circuitry, see Electrical Characteristics for negative current limit values.
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VSW
tON
VOUT
VIN
D =
≈
tSW
VIN
tOFF
tON
0
t
tSW
iL
ILPK
IOUT
0
Iripple
t
In FPWM mode, Continuous Conduction (CCM) is possible even if IOUT is less than half of Iripple
.
图8-12. FPWM Mode Operation
For all devices, in FPWM mode, frequency reduction is still available if output voltage is high enough to
command minimum on time even while lightly loaded, allowing good behavior during faults which involve output
being pulled up.
8.4.3.4 Minimum On-Time (High Input Voltage) Operation
The TLVM236x5 continues to regulate output voltage even if the input-to-output voltage ratio requires an on time
less than the minimum on time of the chip with a given clock setting. This is accomplished using valley current
control. At all times, the compensation circuit dictates both a maximum peak inductor current and a maximum
valley inductor current. If for any reason, valley current is exceeded, the clock cycle is extended until valley
current falls below that determined by the compensation circuit. If the power module is not operating in current
limit, the maximum valley current is set above the peak inductor current, preventing valley control from being
used unless there is a failure to regulate using peak current only. If the input-to-output voltage ratio is too high,
such that the inductor current peak value exceeds the peak command dictated by compensation, the high-side
device cannot be turned off quickly enough to regulate output voltage. As a result, the compensation circuit
reduces both peak and valley current. After a low enough current is selected by the compensation circuit, valley
current matches that being commanded by the compensation circuit. Under these conditions, the low-side device
is kept on and the next clock cycle is prevented from starting until inductor current drops below the desired valley
current. Because on time is fixed at its minimum value, this type of operation resembles that of a device using a
Constant On-Time (COT) control scheme; see 图8-13.
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tON
VOUT
VIN
VSW
D =
≈
tSW
VIN
tON = tON_MIN
tOFF
0
t
- IOUT‡RDSLS
tSW > Clock setting
iL
IOUT
Iripple
ILVLY
t
0
In valley control mode, minimum inductor current is regulated, not peak inductor current.
图8-13. Valley Current Mode Operation
8.4.3.5 Dropout
Dropout operation is defined as any input-to-output voltage ratio that requires frequency to drop to achieve the
required duty cycle. At a given clock frequency, duty cycle is limited by minimum off time. After this limit is
reached as shown in 图 8-15 if clock frequency was to be maintained, the output voltage can fall. Instead of
allowing the output voltage to drop, the TLVM236x5 extends the high-side switch on time past the end of the
clock cycle until the needed peak inductor current is achieved. The clock is allowed to start a new cycle after
peak inductor current is achieved or after a pre-determined maximum on time, tON-MAX, of approximately 9 µs
passes. As a result, after the needed duty cycle cannot be achieved at the selected clock frequency due to the
existence of a minimum off time, frequency drops to maintain regulation. As shown in 图 8-14, if input voltage is
low enough so that output voltage cannot be regulated even with an on time of tON-MAX, output voltage drops to
slightly below the input voltage by VDROP. For additional information on recovery from dropout, refer to 节
8.3.10.1.
Input
Voltage
VOUT
VDROP
Output
Output
Setting
Voltage
VIN
0
Input Voltage
FSW
FSW-NOM
≅110kHz
VIN
0
Input Voltage
Output voltage and frequency versus input voltage: If there is little difference between input voltage and output voltage setting, the IC
reduces frequency to maintain regulation. If input voltage is too low to provide the desired output voltage at approximately 110 kHz,
input voltage tracks output voltage.
图8-14. Frequency and Output Voltage in Dropout
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tON
VOUT
VIN
VSW
D =
≈
tSW
tOFF = tOFF_MIN
VIN
tON < tON_MAX
0
t
- IOUT‡RDSLS
tSW > Clock setting
iL
ILPK
IOUT
Iripple
t
0
Switching waveforms while in dropout. Inductor current takes longer than a normal clock to reach the desired peak value. As a result,
frequency drops. This frequency drop is limited by tON-MAX
.
图8-15. Dropout Waveforms
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLVM236x5 only requires a few external components to convert from a wide range of supply voltages to a
fixed output voltage. To expedite and streamline the process of designing of a TLVM236x5, WEBENCH online
software is available to generate complete designs, leveraging iterative design procedures and access to
comprehensive component databases. The following section describes the design procedure to configure the
TLVM236x5 power module.
As mentioned previously, the TLVM236x5 also integrates several optional features to meet system design
requirements, including precision enable, UVLO, and PGOOD indicator. The application circuit detailed below
shows TLVM236x5 configuration options suitable for several application use cases. Refer to the
TLVM23625EVM User's Guide for more detail.
备注
All of the capacitance values given in the following application information refer to effective values
unless otherwise stated. The effective value is defined as the actual capacitance under DC bias and
temperature, not the rated or nameplate values. Use high-quality, low-ESR, ceramic capacitors with
an X7R or better dielectric throughout. All high value ceramic capacitors have a large voltage
coefficient in addition to normal tolerances and temperature effects. Under DC bias the capacitance
drops considerably. Large case sizes and higher voltage ratings are better in this regard. To help
mitigate these effects, multiple capacitors can be used in parallel to bring the minimum effective
capacitance up to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank must be made to
ensure that the minimum value of effective capacitance is provided.
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9.2 Typical Application
图 9-1 shows a typical application circuit for the TLVM236x5. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of switching frequencies and output capacitance.
VIN
VOUT
VOUT
SW
VIN
EN
CIN
CHF
4.7 µF
COUT
BOOT
RFBT
RT
PGOOD
FB
C
B
A
VCC
RFBB
CVCC
1 µF
GND
A = 200 kHz to 2.2 MHz
or
B = 2.2 MHz
or
C = 1 MHz
A. The RT pin is factory-set for externally adjustable switching frequency RT variants only. See Switching Frequency (RT) for details.
图9-1. Example Application Circuit (TLVM236x5)
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9.2.1 Design Requirements
Detailed Design Procedure provides instructions to design and select components according to 表9-1.
表9-1. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
5.5 V to 36 V
5 V
Input voltage
Output voltage
Maximum output current
Switching frequency
0 A to 2.5 A
1 MHz
9.2.2 Detailed Design Procedure
The design procedure that follows and the resulting component selection is illustrated in 图9-2.
5V
5.5 V to 36 V
VIN
EN
VOUT
SW
4.7 µF
50 VDC
2 × 22 µF
16VDC
0.1 µF
50 VDC
BOOT
40.2 k
RT
PGOOD
FB
VCC
10 k
1 µF
GND
16 VDC
图9-2. 5-V VOUT Design Example
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLVM236x5 devices with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial
3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power
Designer provides a customized schematic along with a list of materials with real-time pricing and
component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Choosing the Switching Frequency
The recommended switching frequency for standard output voltages can be found in 表 8-1. For a 5-V output,
the recommended switching frequency is 1 MHz. To set the switching frequency to 1 MHz, connect the RT pin to
VCC.
9.2.2.3 Setting the Output Voltage
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The adjustable output voltage is externally set with a resistor divider. For more information on how to choose the
feedback resistor values, please see Output Voltage Selection. The recommended value of RFBB is 10 kΩ. For
more information The value for RFBT can be selected from 表8-1 or calculated using 方程式12:
V
V
OUT
1V
R
kΩ = R
kΩ ×
− 1
(12)
FBT
FBB
For the desired output voltage of 5 V, the formula yields a value of 40.2 kΩ. Choose the closest available
standard value of 40.2 kΩfor RFBT
.
9.2.2.4 Input Capacitor Selection
The TLVM236x5 requires a minimum input capacitance of 4.7 μF. TI recommends an additional 0.1-μF
capacitor in parallel for improved bypassing. High-quality ceramic type capacitors with sufficient voltage and
temperature rating are required. The voltage rating of input capacitors must be greater than the maximum input
voltage. For this design, a 4.7 μF and a 0.1 μF, 50-V rated capacitor are used.
Using an electrolytic capacitor on the input in parallel with the ceramics is often desirable. This fact is especially
true if long leads or traces are used to connect the input supply to the regulator. The moderate ESR of this
capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Refer to 表8-2 for example input capacitor part numbers to consider.
9.2.2.5 Output Capacitor Selection
For a 5 V output, the TLVM236x5 requires a minimum of 25 µF effective output capacitance for proper operation
(see 表 8-1). High-quality ceramic type capacitors with sufficient voltage and temperature rating are required.
Additional output capacitance can be added to reduce ripple voltage or for applications with transient load
requirements.
In practice, the output capacitor has the most influence on the transient response and loop-phase margin. Load
transient testing and bode plots are the best way to validate any given design and must always be completed
before the application goes into production.
Limit the maximum value of total output capacitance to about 10 times the design value, or 1000 µF, whichever
is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well
as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load
and loop stability must be performed.
For this design example, select 2 x 22 µF, 16 V, 1210 case size, ceramic capacitors, which have a total effective
capacitance of approximately 40 µF at 5 V. Review 表8-3 for example output capacitor selection.
9.2.2.6 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1 µF, 16 V ceramic capacitor connected from VCC to GND for proper operation. In general, this output
must not be loaded with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Power-Good Output Operation). A value in the range of 10 kΩ to 100 kΩ is a good
choice in this case. The nominal output voltage on VCC is 3.3 V; see Electrical Characteristics for limits.
9.2.2.7 CFF Selection
In some cases, a feedforward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. Optimizing Transient Response of Internally Compensated DC-DC Converters
with Feedforward Capacitor application report is helpful when experimenting with a feedforward capacitor.
Due to the nature of the feedback detect circuitry, the value of CFF must be limited to ensure that the desired
output voltage is established when configuring for adjustable output voltages. 方程式 13 must be followed to
ensure CFF remains below the maximum value.
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V
OUT
C
< C
×
OUT
(13)
FF
6
1.2 × 10
9.2.2.8 Power-Good Signal
Applications requiring a power-good signal to indicate that the output voltage is present and in regulation must
use a pullup resistor between the PGOOD pin and a valid voltage source. This voltage source can be VCC or
VOUT, as example.
9.2.2.9 Maximum Ambient Temperature
As with any power conversion device, the TLVM236x5 dissipates internal power while operating. The effect of
this power dissipation is to raise the internal temperature of the power module above ambient. The internal die
and inductor temperature (TJ) is a function of the ambient temperature, the power loss, and the effective thermal
resistance, RθJA, of the module and PCB combination. The maximum junction temperature for the TLVM236x5
must be limited to 125°C. This limit establishes a limit on the maximum module power dissipation and, therefore,
the load current. 方程式 14 shows the relationships between the important parameters. Seeing that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current is easy. The
power module efficiency can be estimated by using the curves provided in this data sheet. If the desired
operating conditions cannot be found in one of the curves, interpolation can be used to estimate the efficiency.
Alternatively, the EVM can be adjusted to match the desired application requirements and the efficiency can be
measured directly. The correct value of RθJA is more difficult to estimate. Lastly, safe-operation-area curves and
module thermal captures developed through bench analysis on the EVM can be used to provide insights on the
output power capability. These curves can be found in the Application Curves section of the data sheet.
As stated in the Semiconductor and IC Package Thermal Metrics application report the values given in Thermal
Information section are not valid for design purposes and must not be used to estimate the thermal performance
of the application. The values reported in that table were measured under a specific set of conditions that are
rarely obtained in an actual application.
T − T
J
A
η
1
η
I
=
×
×
(14)
OUT, max
R
1 − η
θJA
where
• ηis the efficiency.
The effective RθJA (TLVM23625EVM = 22°C/W) is a critical parameter and depends on many factors such as
the following:
• Power dissipation
• Air temperature/flow
• PCB area
• Copper heat-sink area
• Adjacent component placement
• Number of thermal vias under the package
The IC Power loss mentioned above is the overall power loss minus the loss that comes from the inductor DC
resistance. The overall power loss can be approximated by using WEBENCH for a specific operating condition
and temperature.
Use the following resources as guides to optimal thermal PCB design and estimating RθJA for a given
application environment:
• Thermal Design by Insight not Hindsight Application Report
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages Application Report
• Semiconductor and IC Package Thermal Metrics Application Report
• Thermal Design Made Simple with LM43603 and LM43602 Application Report
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• PowerPAD™ Thermally Enhanced Package Application Report
• PowerPAD™ Made Easy Application Report
• Using New Thermal Metrics Application Report
• PCB Thermal Calculator
9.2.2.10 Other Connections
• The RT pin can be connected to AGND for a switching frequency of 2.2 MHz or tied to VCC for a switching
frequency of 1 MHz. A resistor connected between the RT pin and GND can be used to set the desired
operating frequency between 200 kHz and 2.2 MHz.
• For the MODE/SYNC pin variant, connecting this pin to an external clock forces the device into SYNC
operation. Connecting the MODE/SYNC pin low allows the device to operate in PFM mode at light load.
Connecting the MODE/SYNC pin high puts the device into FPWM mode and allows full frequency operation
independent of load current.
• A resistor divider network on the EN pin can be added for a precision input undervoltage lockout (UVLO)
• Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
• A pullup resistor between the PGOOD pin and a valid voltage source to generate a power-good signal.
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9.2.3 Application Curves
COUT = 2 × 22 uF (1210,16VDC)
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
5V, 2MHz
5V, 2MHz
0.001
0.01
0.1
1
2.5
0.001 0.501 1.001 1.501 2.001
2.5
Load Current (A)
Load Current (A)
图9-3. 12VIN Efficiency (Log)
图9-4. 12VIN Efficiency (Linear)
110
105
100
95
95
90
85
80
75
70
65
60
55
50
90
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
85
80
5V, 2MHz
1.8V, 300kHz
2.5V, 800kHz
5V/3.3V, 1MHz
5V/3.3V, 2MHz
75
70
0.001
0.01 0.1
Load Current (A)
1
2.5
65
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
Load Current (A)
图9-6. 24VIN Efficiency (Log)
图9-5. 12VIN: Max Ambient Temperature vs Load Current
(Analysis on TLVM23625EVM)
110
95
90
85
80
75
70
105
100
95
90
85
80
75
70
65
60
55
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
5V, 2MHz
65
60
1.8V, 300kHz
2.5V, 800kHz
5V/3.3V, 1MHz
5V/3.3V, 2MHz
55
50
0.001 0.501 1.001 1.501 2.001
Load Current (A)
2.5
0.5
0.75
1
1.25
1.5
Load Current (A)
1.75
2
2.25
2.5
图9-8. 24VIN: Max Ambient Temperature vs Load Current
图9-7. 24VIN Efficiency (Linear)
(Analysis on TLVM23625EVM)
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9.2.3 Application Curves (continued)
COUT = 2 × 22 uF (1210,16VDC)
95
90
85
80
75
70
95
90
85
80
75
70
65
60
55
50
45
40
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
5V, 2MHz
1.8V, 300kHz
2.5V, 800kHz
3.3V, 1MHz
5V, 1MHz
65
60
55
50
45
40
5V, 2MHz
0.001
0.01 0.1
Load Current (A)
1
2.5
0.001 0.501 1.001 1.501 2.001
Load Current (A)
2.5
图9-9. 36VIN Efficiency (Log)
图9-10. 36VIN Efficiency (Linear)
110
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
1.8V, 300kHz
2.5V, 800kHz
5V/3.3V, 1MHz
5V/3.3V, 2MHz
0.5
0.75
1
1.25
1.5
Load Current (A)
1.75
2
2.25
2.5
图9-11. 36VIN: Maximum Ambient Temperature vs Load Current
(Analysis on TLVM23625EVM)
VIN = 24 V
VOUT = 5 V
COUT = 2 × 22 uF
(1210,16VDC)
1 MHz (FPWM)
0 A to 2.5 A,1 A/µs
图9-12. Load Transient
VIN = 12 V
VOUT = 3.3 V
2 A, 500 kHz
VIN = 24 V
1.25 A to 2.5 A,1
A/µs
VOUT = 5 V
1 MHz (FPWM)
图9-14. EVM Thermal Performance
图9-13. Load Transient
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9.2.3 Application Curves (continued)
COUT = 2 × 22 uF (1210,16VDC)
VIN = 12 V
VOUT = 3.3 V
2 A, 1 MHz
VIN = 12 V
VOUT = 3.3 V
2 A, 2.2 MHz
图9-15. EVM Thermal Performance
图9-16. EVM Thermal Performance
VIN = 24 V
VOUT = 3.3 V
2 A, 1 MHz
VIN = 24 V
VOUT = 3.3 V
2 A, 500 kHz
图9-18. EVM Thermal Performance
图9-17. EVM Thermal Performance
VIN = 24 V
VOUT = 3.3 V
2 A, 2.2 MHz
图9-19. EVM Thermal Performance
VIN = 24 V
VOUT = 5 V
Fsw = 1 MHz
Load = 2.5 A
Board = TLVM23625EVM
图9-20. CISPR 11, Class B, CE Scan 150 kHz–30 MHz
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9.2.3 Application Curves (continued)
COUT = 2 × 22 uF (1210,16VDC)
CISPR 11 Class B QPk Radiated Emmissions
60
55
50
45
40
35
30
25
20
15
10
5
Horizontal Amplitude
Vertical Amplitude
Class B (3M) QPk Limit
30 40 50 6070 100
200 300 400500 700 1000
Frequency (MHz)
VIN = 24 V
VOUT = 5 V
Board = TLVM23625EVM (No Filter)
图9-21. CISPR 11 RE, 3-Meter, Scan 30 MHz–1 GHz
Fsw = 1 MHz
Load = 2.5 A
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9.3 Best Design Practices
• Do not exceed the Absolute Maximum Ratings.
• Do not exceed the Recommended Operating Conditions.
• Do not exceed the ESD Ratings.
• Do not allow the EN input to float.
• Do not allow the output voltage to exceed the input voltage, nor go below ground.
• Follow all the guidelines and suggestions found in this data sheet before committing the design to production.
TI application engineers are ready to help critique your design and PCB layout to help make your project a
success.
9.4 Power Supply Recommendations
The TLVM236x5 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded regulator circuit. Estimate the average input current with 方程式15.
V
× I
OUT OUT
I
=
(15)
IN
V
× η
IN
where
• ηis the efficiency
If the module is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the
low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage
transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input
voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can
cause false UVLO triggering and a system reset.
The best way to solve such issues is to reduce the distance from the input supply to the module and use an
electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps
damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range
of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage
steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input
circuit configurations.
9.5 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. Use the following guidelines to design a PCB with the best power conversion performance, optimal
thermal performance, and minimal generation of unwanted EMI.
9.5.1 Layout Guidelines
The PCB layout of any DC/DC module is critical to the optimal performance of the design. Poor PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the module regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
to a great extent, the EMI performance of the regulator is dependent on the PCB layout. In a buck converter
module, the most critical PCB feature is the loop formed by the input capacitor or capacitors and power ground,
as shown in 图 9-22. This loop carries large transient currents that can cause large transient voltages when
reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the power
module. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible
to reduce the parasitic inductance. Layout Exmple shows a recommended layout for the critical components of
the TLVM236x5.
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1. Place the input capacitors as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and
routed with short, wide traces to the VCC and GND pins.
3. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF, if
used, physically close to the device. The connections to FB and GND must be short and close to those pins
on the device. The connection to VOUT can be somewhat longer. However, the latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
4. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and as a heat
dissipation path.
5. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the power module and maximizes efficiency.
6. Provide enough PCB area for proper heat-sinking. Sufficient amount of copper area must be used to ensure
a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom
PCB layers must be made with two ounce copper and no less than one ounce. If the PCB design uses
multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-
spreading ground planes.
7. Use multiple vias to connect the power planes to internal layers.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies Application Report
• Simple Switcher PCB Layout Guidelines Application Report
• Construction Your Power Supply- Layout Considerations Seminar
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
VIN
SW
GND
图9-22. Current Loops with Fast Edges
9.5.1.1 Ground and Thermal Considerations
As previously mentioned, TI recommends using one of the middle layers as a solid ground plane. A ground
plane provides shielding for sensitive circuits and traces as well as a quiet reference potential for the control
circuitry. Connect the GND pin to the ground planes using vias next to the bypass capacitors. The GND trace, as
well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the
ground plane contains much less noise; use for sensitive routes.
TI recommends providing adequate device heat-sinking by having enough copper near the GND pin. See
图 9-23 for example layout. Use as much copper as possible, for system ground plane, on the top and bottom
layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting
from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness, and proper layout,
provides low current conduction impedance, proper shielding and lower thermal resistance.
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9.5.2 Layout Example
Maintain continuous ground pours
Keep FB, RT, VCC trace small
VCC
FB
Top Layer
Mid layer
GND
RT
VOUT
VOUT
~100nF, 0402/0603
capacitor nearest to Vin pin
VIN
Keep output cap close
Keep input cap close
Large VOUT pour for cooling
图9-23. Example Layout
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLVM236x5 devices with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial
3. Compare the generated design with other possible solutions from Texas Instruments. The WEBENCH Power
Designer provides a customized schematic along with a list of materials with real-time pricing and
component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.1.3 Device Nomenclature
图 10-1 shows the device naming nomenclature of the TLVM236x5. See 节 5 for the availability of each variant.
Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order
quantities apply.
TLVM X 236 XX X RDNR
SPREAD SPECTRUM
2: No
3: Yes
OUTPUT CURRENT MAX
15: 1.5 A
25: 2.5 A
F
SW MODE OPTION
PACKAGE
RDNR = QFN 11-pin large reel
F: MODE/SYNC Trim
* (Fixed Frequency FSW = 1 MHz)
* No alpha character means FSW is
set by the RT pin
图10-1. Device Naming Nomenclature
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Thermal Design by Insight not Hindsight Application Report
• Texas Instruments, A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
Application Report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics Application Report
• Texas Instruments, Thermal Design Made Simple with LM43603 and LM43602 Application Report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package Application Report
• Texas Instruments, PowerPAD™ Made Easy Application Report
• Texas Instruments, Using New Thermal Metrics Application Report
Copyright © 2023 Texas Instruments Incorporated
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• Texas Instruments, Layout Guidelines for Switching Power Supplies Application Report
• Texas Instruments, Simple Switcher PCB Layout Guidelines Application Report
• Texas Instruments, Construction Your Power Supply- Layout Considerations Seminar
• Texas Instruments, Low Radiated EMI Layout Made Simple with LM4360x and LM4600x Application Report
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
HotRod™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLVM23615RDNR
TLVM23625RDNR
ACTIVE QFN-FCMOD
ACTIVE QFN-FCMOD
RDN
RDN
11
11
3000 RoHS & Green
3000 RoHS & Green
SN
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
23615
23625
Samples
Samples
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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16-Mar-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLVM23615RDNR
TLVM23625RDNR
QFN-
FCMOD
RDN
RDN
11
11
3000
3000
330.0
17.6
3.8
4.8
2.3
8.0
12.0
Q1
QFN-
330.0
17.6
3.8
4.8
2.3
8.0
12.0
Q1
FCMOD
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Mar-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLVM23615RDNR
TLVM23625RDNR
QFN-FCMOD
QFN-FCMOD
RDN
RDN
11
11
3000
3000
336.0
336.0
336.0
336.0
48.0
48.0
Pack Materials-Page 2
PACKAGE OUTLINE
QFN-FCMOD - 2.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDN0011A
3.6
3.4
B
A
4.6
4.4
PIN 1 INDEX AREA
2.1
1.9
C
SEATING PLANE
0.05
0
0.08
C
SYMM
(0.2) TYP
(0.2)
8X (0.25)
1.15
1.05
2X
6X 0.5
2X 0.3
2.1
2
4
5
2X
PKG
0.35
6X
3
1
0.15
0.1
6
8
2X 0.65
2X 1.15
C
A B
0.05
C
1.4
1.3
2X 1.9
11
9
0.425
0.325
0.1
0.65
0.55
2X
2X
1
0.8
0.4
0.2
4X
C A B
0.1
C
A
B
0.05
C
1.025
0.825
2X
0.05
C
2X 0.5
4226623/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
QFN-FCMOD - 2.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDN0011A
2X (1.125)
2X (0.5)
(0.3)
9
1
(2.23)
2X
(0.8)
2X (2.06)
11
2X
(0.37)
2X (1.96)
8
(1.69)
(1.48)
(1.52)
(1.23)
2X (1.15)
4X(0.65)
3
6
2X (0.2)
6X (0.25)
4X (1.1)
(0.23)
0.000 PKG
2X (0.3)
6X
(0.5)
2X (0.55)
2X (0.59)
(0.77)
2X
(2.05)
2X
(1.75)
4
5
2X (1.05)
8X
(0.25)
2X (1.41)
2X (1.55)
(1.77)
(Ø0.2)
TYP
(R0.05) TYP
(0.56)
(0.9)
2X (1.1)
(0.385) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226623/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
QFN-FCMOD - 2.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDN0011A
2X (1.125)
2X (0.5)
(0.3)
11
9
8
1
2X
(0.8)
2X (2.06)
2X
(0.37)
2X (1.96)
(1.69)
(1.52)
4X (1.1)
2X (1.15)
(0.65)
6X (0.25)
2X (0.2)
4
5
0.000 PKG
2X (0.23)
2X (0.3)
8X
(0.25)
2X (2.05)
2X
(0.62)
2X (1)
2X (1.75)
6X (0.5)
4X
(0.51)
2X (1.77)
(R0.05) TYP
6X (0.93)
8X (0.375)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
PIN 4 & 5:
72% SOLDER COVERAGE BY AREA
SCALE: 20X
4226623/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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