TM124GU8A-60 [TI]

1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE;
TM124GU8A-60
型号: TM124GU8A-60
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE

动态存储器 内存集成电路
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TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
Organization . . . 1 048 576 × 8  
Single 5-V Power Supply (±10% Tolerance)  
SINGLE IN-LINE  
MODULE  
(TOP VIEW)  
30-Pin Single In-Line Memory Module  
(SIMM)  
TM124GU8A Utilizes Two 4-Megabit  
Dynamic RAMs in Plastic Small-Outline  
J-Lead Packages (SOJs)  
V
CC  
1
CAS  
DQ1  
A0  
2
3
4
5
6
7
8
9
Long Refresh Period  
A1  
. . . 16 ms (1024 Cycles)  
DQ2  
A2  
All Inputs, Outputs, Clocks Fully TTL  
Compatible  
A3  
V
SS  
3-State Outputs  
DQ3 10  
A4 11  
Performance Ranges:  
A5 12  
ACCESS  
TIME  
ACCESS  
TIME  
READ  
OR  
DQ4 13  
A6 14  
(t  
RAC  
)
(t  
AA  
)
WRITE  
CYCLE  
(MIN)  
A7 15  
DQ5 16  
A8 17  
A9 18  
NC 19  
DQ6 20  
(MAX)  
60 ns  
70 ns  
80 ns  
(MAX)  
30 ns  
35 ns  
40 ns  
TM124GU8A-60  
TM124GU8A-70  
TM124GU8A-80  
110 ns  
130 ns  
150 ns  
W
21  
22  
V
SS  
DQ7 23  
NC 24  
DQ8 25  
NC 26  
RAS 27  
NC 28  
Low Power Dissipation  
Operating Free-Air Temperature Range  
0°C to 70°C  
description  
NC 29  
V
CC  
30  
The TM124GU8A is a dynamic random-access  
memory module organized as 1 048 576 × 8 in a  
30-pin leadless single in-line memory module  
(SIMM).  
PIN NOMENCLATURE  
The TM124GU8A is composed of two TMS44400,  
1 048 576 × 4 bit dynamic RAMs in 20/26-lead  
plastic small-outline J-lead packages (SOJs).  
A0–A9  
CAS  
Address Inputs  
Column-Address Strobe  
DQ1–DQ8  
NC  
Data In/Data Out  
No Internal Connect  
Row-Address Strobe  
5-V Supply  
The TM124GU8A is mounted on a substrate with  
decoupling capacitors. The onboard capacitors  
eliminate the need for bypassing on the  
motherboard and offer superior performance over  
equivalent leaded capacitors due to reduced lead  
inductance. With the elimination of bypass  
capacitors on the motherboard, reduced PC  
board size, and fewer plated through-holes, a cost  
savings can be realized.  
RAS  
V
CC  
V
SS  
Ground  
The TM124GU8A features RAS access times of 60 ns, 70 ns, and 80 ns. All inputs and outputs, including clocks,  
are compatible with Series 74 TTL. All address lines and data in are latched on-chip to simplify system design.  
Data out is unlatched to allow greater system flexibility.  
The TM124GU8A is characterized for operation from 0°C to 70°C.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
operation  
The TM124GU8A operates as two TMS44400s connected as shown in the functional block diagram. The  
common I/O features of the TM124GU8A dictates the use of early write cycles to prevent contention on the DQ  
lines.  
specifications  
Refresh period is extended to 16 milliseconds and, during this period, each of the 1024 rows must be strobed  
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.  
single in-line memory module and components  
PC substrate: 1,27 mm (0.05 inch) nominal thickness on contact area  
Bypass capacitors: Multilayer ceramic  
Contact area for socketable devices: Nickel plate and solder plate over copper  
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
functional block diagram  
1024K × 4  
A0–A9  
RAS  
CAS  
W
A0–A9  
10  
DQ1  
DQ2  
DQ3  
DQ4  
DQ1  
DQ2  
DQ3  
DQ4  
RAS  
CAS  
W
OE  
V
DD  
V
SS  
1024K × 4  
A0–A9  
RAS  
CAS  
W
10  
DQ5  
DQ6  
DQ7  
DQ8  
DQ5  
DQ6  
DQ7  
DQ8  
OE  
V
DD  
V
SS  
V
CC  
C...C  
V
SS  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V  
Voltage range on V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V  
CC  
Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W  
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and  
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of  
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTE 1: All voltage values are with respect to V  
.
SS  
3
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
recommended operating conditions  
MIN NOM MAX  
UNIT  
V
V
V
V
Supply voltage  
4.5  
2.4  
– 1  
0
5
5.5  
6.5  
0.8  
70  
CC  
IH  
IL  
High-level input voltage  
V
Low-level input voltage (see Note 2)  
Operating free-air temperature  
V
T
A
°C  
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic  
voltage levels only.  
electrical characteristics over full ranges of recommended operating conditions (unless otherwise  
noted)  
TM124GU8A-60 TM124GU8A-70 TM124GU8A-80  
PARAMETER  
TEST CONDITIONS  
UINT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
V
V
High-level output voltage  
Low-level output voltage  
I
I
= – 5 mA  
2.4  
2.4  
2.4  
V
V
OH  
OH  
= 4.2 mA  
0.4  
0.4  
0.4  
OL  
OL  
V = 0 to 6.5 V, V  
= 5.5 V,  
All other pins = 0 V to V  
I
CC  
I
I
I
Input current (leakage)  
Output current (leakage)  
±10  
±10  
±10  
µA  
µA  
I
CC  
V
V
= 0 to V  
,
O
CC  
= 5.5 V, CAS high  
±10  
±10  
±10  
O
CC  
Read or write cycle current  
(see Note 3)  
Minimum cycle, V  
CC  
= 5.5 V  
210  
180  
160  
mA  
CC1  
After 1 memory cycle,  
RAS and CAS high,  
4
2
4
2
4
2
mA  
mA  
V
IH  
= 2.4 V (TTL)  
I
Standby Current  
CC2  
After 1 memory cycle,  
RAS and CAS high,  
V
IH  
= V  
– 0.2 V (CMOS)  
CC  
Average refresh current  
(see Note 3)  
Minimum cycle, V = 5.5 V,  
CC  
RAS cycling, CAS high  
I
I
210  
180  
180  
160  
160  
140  
mA  
mA  
CC3  
t
= minimum, V  
= 5.5 V,  
CC  
Average page current  
(see Note 4)  
c(P)  
RAS low, CAS cycling  
CC4  
NOTES: 3. Measured with a maximum of one address change while RAS = V  
.
IL  
4. Measured with a maximum of one address change while CAS = V  
.
IH  
4
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
capacitance over recommended ranges of supply voltage and operating free-air temperature,  
f = 1 MHz  
PARAMETER  
Input capacitance, address inputs  
MIN  
MAX  
10  
7
UNIT  
pF  
C
C
C
C
i(A)  
Input capacitance, data inputs/outputs  
Input capacitance, strobe inputs  
Input capacitance, W input  
pF  
i(DQ)  
i(RC)  
i(W)  
14  
14  
pF  
pF  
switching characteristics over recommended ranges of supply voltage and operating free-air  
temperature  
TM124GU8A-60 TM124GU8A-70 TM124GU8A-80  
PARAMETER  
UNIT  
MIN  
MAX  
30  
MIN  
MAX  
35  
MIN  
MAX  
40  
t
t
t
t
t
t
Access time from column-address  
Access time from CAS low  
ns  
ns  
ns  
ns  
ns  
ns  
AA  
15  
18  
20  
CAC  
CPA  
RAC  
CLZ  
OFF  
Access time from column precharge  
Access time from RAS low  
35  
40  
45  
60  
70  
80  
CAS to output in low Z  
0
0
0
0
0
0
Output disable time after CAS high (see Note 5)  
15  
18  
20  
NOTE 5:  
t
is specified when the otuput is no longer driven.  
OFF  
5
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature  
TM124GU8A-60  
TM124GU8A-70  
TM124GU8A-80  
UNIT  
MIN  
110  
40  
60  
60  
15  
10  
40  
15  
0
MAX  
MIN  
130  
45  
70  
70  
18  
10  
50  
15  
0
MAX  
MIN  
150  
50  
80  
80  
20  
10  
60  
15  
0
MAX  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Random read or write cycle (see Note 6)  
Page-mode read or write cycle time (see Note 7)  
Page-mode pulse duration, RAS low  
Non-page-mode pulse duration, RAS low  
Pulse duration, CAS low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
PC  
100 000  
10 000  
10 000  
100 000  
10 000  
10 000  
100 000  
10 000  
10 000  
RASP  
RAS  
CAS  
CP  
Pulse duration, CAS high  
Pulse duration, RAS high (precharge)  
Write pulse duration  
RP  
WP  
Column-address setup time before CAS low  
Row-address setup time before RAS low  
Data setup time  
ASC  
ASR  
DS  
0
0
0
0
0
0
Read setup time before CAS low  
0
0
0
RCS  
CWL  
RWL  
WCS  
WSR  
WTS  
CAH  
DHR  
DH  
W low setup time before CAS high  
W low setup time before RAS high  
W low setup time before CAS low  
W high setup time (CAS-before-RAS refresh only)  
W low setup time (test mode only)  
Column-address hold time after CAS low  
Data hold time after RAS low (see Note 8)  
Data hold time  
15  
15  
0
18  
18  
0
20  
20  
0
10  
10  
10  
50  
10  
50  
10  
0
10  
10  
15  
55  
15  
55  
10  
0
10  
10  
15  
60  
15  
60  
10  
0
Column-address hold time after RAS low (see Note 8)  
Row-address hold time after RAS low  
Read hold time after CAS high (see Note 9)  
Read hold time after RAS high (see Note 9)  
Write hold time after CAS low  
AR  
RAH  
RCH  
RRH  
WCH  
WCR  
WHR  
WTH  
0
0
0
15  
50  
10  
10  
15  
55  
10  
10  
15  
60  
10  
10  
Write hold time after RAS low (see Note 8)  
W high hold time (CAS-before-RAS refresh only)  
W low hold time (test mode only)  
Continued next page.  
NOTES: 6. All cycle times assume t = 5 ns.  
T
7. To assure t  
min, t  
should be greater than or equal to 5 ns.  
PC  
8. The minimum value is measured when t  
ASC  
is set to t  
RCD  
min as a reference.  
RCD  
must be satisfied for a read cycle.  
9. Either t  
or t  
RCH  
RRH  
6
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
timing requirements over recommended ranges of supply voltage and operating free-air  
temperature (concluded)  
TM124GU8A-60  
TM124GU8A-70  
TM124GU8A-80  
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Delay time, RAS low to CAS high  
(CAS-before-RAS refresh only)  
t
15  
15  
20  
ns  
CHR  
t
t
Delay time, CAS high to RAS low  
Delay time, RAS low to CAS high  
0
0
0
ns  
ns  
CRP  
60  
70  
80  
CSH  
Delay time, CAS low to RAS low  
(CAS-before-RAS refresh only)  
t
10  
10  
10  
ns  
CSR  
t
t
t
t
t
t
t
t
t
t
t
Delay time, RAS low to column-address (see Note 10)  
Delay time, column-address to RAS high  
Delay time, column-address to CAS high  
Delay time, RAS low to CAS low (see Note 10)  
Delay time, RAS high to CAS low (CBR only)  
Delay time, CAS low to RAS high  
15  
30  
30  
20  
0
30  
45  
15  
35  
35  
20  
0
35  
52  
15  
40  
40  
20  
0
40  
60  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
RAD  
RAL  
CAL  
RCD  
RPC  
RSH  
TAA  
TCPA  
TRAC  
REF  
T
15  
35  
40  
65  
18  
40  
45  
75  
20  
45  
50  
85  
Access time from address (test mode)  
Access time from column precharge (test mode)  
Access time from RAS (test mode)  
Refresh time interval  
16  
50  
16  
50  
16  
50  
Transition time  
2
2
2
NOTE 10: The maximum value is specified only to assure access time.  
7
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
TM124GU8A  
1 048 576-WORD BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE  
SMMS181A–JANUARY 1991–REVISED JANUARY 1993  
30-pin U-A single in-line memory module  
5,28 (0.208) MAX  
89,03 (3.505)  
88,77 (3.495)  
3,18 (0.125)  
TYP  
16,64  
(0.655)  
MAX  
10,16  
(0.400)  
TYP  
Pin Spacing 2,54 (0.100) T.P.  
(see Note A)  
1, 37 (0.054)  
1, 19 (0.047)  
1,78 (0.070) TYP  
3,38 (0.133) TYP  
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES  
NOTE A: Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.  
device symbolization  
TM124GU8A  
– SS  
YYMMT  
YY = Year Code  
MM = Month Code  
T
= Assembly Site Code  
–SS = Speed  
NOTE: The location of the part number may vary.  
Printed in U. S. A.  
SMMS181A  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1998, Texas Instruments Incorporated  

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