TM16ER72LP [TI]
SYNCHRONOUS DYNAMIC RAM MODULES;
| 型号： | TM16ER72LP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SYNCHRONOUS DYNAMIC RAM MODULES |
| 文件： | 总14页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SMMS694 − AUGUST 1997
D
Organization
− TM16ER72HP-xx . . . 16777216 × 72 Bits
− TM16ER72LP-xx . . . 16777216 × 72 Bits
D
Long Refresh Periods:
− TM16ER72HP: 64 ms (4096 Cycles)
− TM16ER72LP: 64 ms (8192 Cycles)
D
D
Single 3.3-V Power Supply
( 10% Tolerance)
D
D
3-State Output
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) With Buffer for Use With
Socket
D
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
D
TM16ER72xP-xx — Uses 18 64M-Bit
High-Speed (16M×4-Bit) Dynamic RAMs
High-Speed, Low-Noise LVTTL Interface
D
D
D
Performance Ranges
D
High-Reliability 32-Lead 400-Mil-Wide
Surface-Mount Thin Small-Outline Package
(TSOP) (DGE Suffix)
ACCESS ACCESS ACCESS EDO
TIME
TIME
TIME CYCLE
t
t
t
t
HPC
RAC
CAC
AA
(MAX)
40 ns
50 ns
60 ns
(MAX)
11 ns
13 ns
15 ns
(MAX)
20 ns
25 ns
30 ns
(MIN)
16 ns
20 ns
25 ns
D
Intended for Workstation/Server
Applications
’16ER72xx-40
’16ER72xx-50
’16ER72xx-60
description
The TM16ER72HP is a 128M-byte, 168-pin, buffered dual-in-line memory module (DIMM). The DIMM is
composed of eighteen TMS465409, 16777216 × 4-bit 4K-refresh EDO dynamic random-access memories
(DRAMs), each in a 400-mil, 32-pin plastic thin small-outline package (TSOP) (DGE suffix), and two
SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with
decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).
The TM16ER72LP is a 128M-byte, 168-pin, buffered DIMM. The DIMM is composed of eighteen TMS464409,
16777216 × 4-bit 8K-refresh EDO DRAMs, each in a 400-mil, 32-pin plastic TSOP (DGE suffix), and two
SN74LVC162244 16-bit buffers, each in a 48-lead plastic TSOP package mounted on a substrate with
decoupling capacitors. See the TMS465409 data sheet (literature number SMKS895).
These modules are intended for multimodule workstation/server applications where buffering is needed for
address and control signals. Two copies of address 0 (A0 and B0) are defined to allow maximum performance
for 4-byte applications that interleave between two 4-byte banks. A0 is common to the DRAMs used for
DQ0−DQ31, while B0 is common to the DRAMs used for DQ32−DQ63.
operation
The TM16ER72xP operates as eighteen TMS46x409s that are connected as shown in the TM16ER72xP
functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ꢧꢤ ꢥ ꢛ ꢫꢜ ꢦꢩ ꢡ ꢥ ꢤ ꢞꢝ ꢧꢤ ꢪ ꢤ ꢬꢞ ꢦꢠꢤ ꢜꢢꢭ ꢗ ꢩꢡ ꢟꢡ ꢣꢢ ꢤꢟ ꢛꢥ ꢢꢛ ꢣ ꢧꢡ ꢢꢡ ꢡꢜ ꢧ ꢞꢢ ꢩꢤꢟ
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Copyright 1997, Texas Instruments Incorporated
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1
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SMMS694 − AUGUST 1997
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
TM16ER72xP
(SIDE VIEW)
PIN NOMENCLATURE − TM16ER72HP
A[0:11]
A[0:11]
B0
DQ[0:63]
CB[0:7]
Row Address Inputs
Column Address Inputs
Addr0 for Bank 2 Devices
Data In/Data Out
Check Bit In/Check Bit Out
Column-Address Strobe
ID Pins
1
CAS0 and CAS4
ID[0:1]
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
NC
PD[1:8]
PDE
Row-Address Strobe
Write Enable
Output Enable
10
11
No-Connect Pin
Presence Detect
Presence Detect Enable
3.3-V Supply
V
DD
V
SS
Ground
PIN NOMENCLATURE − TM16ER72LP
A[0:12]
A[0:10]
B0
DQ[0:63]
CB[0:7]
Row Address Inputs
Column Address Inputs
Addr0 for Bank 2 Devices
Data In/Data Out
Check Bit In/Check Bit Out
Column-Address Strobe
ID Pins
CAS0 and CAS4
ID[0:1]
40
41
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
NC
Row-Address Strobe
Write Enable
Output Enable
No-Connect Pin
PD[1:8]
PDE
Presence Detect
Presence Detect Enable
3.3-V Supply
V
DD
V
SS
Ground
PRESENCE DETECT
- 40 -50
PIN
- 60
1
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
84
0
0
ID1
0
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SMMS694 − AUGUST 1997
Pin Assignments
PIN
PIN
NAME
PIN
PIN
NO.
1
NAME
NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NO.
85
NAME
NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
V
SS
V
SS
V
SS
V
SS
2
DQ0
DQ1
DQ2
DQ3
OE2
RAS2
CAS4
NC
86
DQ32
DQ33
DQ34
DQ35
NC
NC
3
87
4
88
NC
5
89
NC
6
V
DD
WE2
90
V
DD
PDE
7
DQ4
DQ5
DQ6
DQ7
DQ8
V
DD
91
DQ36
DQ37
DQ38
DQ39
DQ40
V
DD
8
NC
NC
92
NC
NC
9
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB2
CB3
94
CB6
CB7
95
V
SS
V
SS
96
V
SS
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
DQ16
DQ17
DQ18
DQ19
97
DQ41
DQ42
DQ43
DQ44
DQ45
DQ48
DQ49
DQ50
DQ51
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
V
DD
V
DD
V
DD
DQ20
NC
V
DD
DQ52
NC
DQ14
DQ15
CB0
DQ46
DQ47
CB4
NC
NC
NC
NC
CB1
NC
CB5
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ53
DQ54
DQ55
NC
NC
NC
NC
V
DD
V
SS
V
DD
NC
V
SS
WE0
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
CAS0
NC
NC
NC
NC
NC
RAS0
OE0
V
DD
V
DD
V
SS
DQ28
DQ29
DQ30
DQ31
V
SS
A1
DQ60
DQ61
DQ62
DQ63
A0
A2
A3
A5
A4
A6
V
SS
A7
V
SS
A8
PD1
PD3
PD5
PD7
ID0
A9
PD2
PD4
PD6
PD8
ID1
A10
A12
A11
NC
V
DD
NC
V
DD
NC
NC
V
DD
B0
V
DD
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SMMS694 − AUGUST 1997
buffered dual-in-line memory module and components
The buffered dual-in-line memory module and components include:
D
D
D
PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM16ER72xP
RAS0
WE0
OE0
RAS2
WE2
OE2
CAS0
CAS4
CAS OE
DQ[0:3]
W
RAS
RAS
RAS
RAS
RAS
RAS
RAS
RAS
RAS
CAS OE
DQ[0:3]
W
RAS
RAS
U0
UB0
DQ[0:3]
DQ[4:7]
DQ[32:35]
DQ[36:39]
DQ[40:43]
DQ[44:47]
CB[4:7]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
W
U1
UB1
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
RAS
U2
UB2
DQ[8:11]
DQ[12:15]
CB[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
W
RAS
U3
UB3
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
RAS
U8
UB8
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
W
RAS
U4
UB4
DQ[16:19]
DQ[20:23]
DQ[24:27]
DQ[28:31]
DQ[48:51]
DQ[52:55]
DQ[56:59]
DQ[60:63]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
RAS
U5
UB5
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
RAS
U6
UB6
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
RAS
UB7
U7
V
DD
U[0:8], UB[0:8]
A0
B0
U[0:8]
Two 0.1 µF (Minimum)
per DRAM
UB[0:8]
A[1:n]
A[1:n]: U[0:8], UB[0:8]
V
SS
U[0:8], UB[0:8]
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢏ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢄ ꢐꢀ ꢄ ꢑꢒꢄꢒ ꢍꢒꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕꢖ ꢖ ꢄꢅꢄ ꢒ ꢒꢌ ꢑꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔ ꢒꢕ ꢏꢄ ꢘ
SMMS694 − AUGUST 1997
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
DD
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM16ER72xP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
Supply voltage
3
3.3
0
3.6
DD
SS
IH
Supply voltage
V
High-level input voltage
Low-level input voltage
Ambient temperature
2
−0.3
0
V
DD
+ 0.3
0.8
V
V
IL
T
A
70
°C
5
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SMMS694 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM16ER72HP
’16ER72HP-40
’16ER72HP-50
’16ER72HP-60
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= − 2 mA
= − 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
V
OH
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
CC
DD
All others = 0 V to V
I
I
20
20
20
20
20
20
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V ,
DD
DD
CASx high
O
Average read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
2880
18
2340
18
1980
18
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RASx and CASx high
Average standby
current
I
CC2
V
IH
= V − 0.2 V (LVCMOS),
DD
After one memory cycle,
RASx and CASx high
9
9
9
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
‡¶
I
2880
2340
1980
mA
CC3
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
= 3.6 V,
t
= MIN,
DD
RASx low,
HPC
I
I
2700
2880
2160
2340
1800
1980
mA
mA
CC4
CASx cycling
Average CBR
refresh current
V
DD
= 3.6 V,
Minimum cycle,
CC5
RASx low after CASx low
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RASx = V
Measured with a maximum of one address change during each EDO cycle, t
IL
HPC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢏ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢄ ꢐꢀ ꢄ ꢑꢒꢄꢒ ꢍꢒꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕꢖ ꢖ ꢄꢅꢄ ꢒ ꢒꢌ ꢑꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔ ꢒꢕ ꢏꢄ ꢘ
SMMS694 − AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM16ER72LP
’16ER72LP-40
’16ER72LP-50
’16ER72LP-60
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= − 2 mA
= − 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
V
OH
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
CC
DD
All others = 0 V to V
I
I
20
20
20
20
20
20
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V ,
DD
DD
CASx high
O
Average read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
2250
18
1800
18
1620
18
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RASx and CASx high
Average standby
current
I
CC2
V
IH
= V − 0.2 V (LVCMOS),
DD
After one memory cycle,
RASx and CASx high
9
9
9
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
‡¶
I
2250
1800
2250
mA
CC3
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
= 3.6 V,
t
= MIN,
DD
RASx low,
HPC
I
I
2520
2880
1980
2340
1620
1980
mA
mA
CC4
CASx cycling
Average CBR
refresh current
V
DD
= 3.6 V,
Minimum cycle,
CC5
RASx low after CASx low
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RASx = V
Measured with a maximum of one address change during each EDO cycle, t
IL
HPC
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆꢇ
ꢈ
ꢉ
ꢂ
ꢃ
ꢊ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢏ
ꢉ
ꢄ ꢐꢀ ꢄꢑ ꢒ ꢄꢒ ꢍꢒ ꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕ ꢖꢖ ꢄꢅ ꢄꢒ ꢒꢌ ꢑ ꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔꢒ ꢕꢏ ꢄꢘ
ꢂ
ꢃ
ꢊ
SMMS694 − AUGUST 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’16ER72xP
PARAMETER
UNIT
MIN MAX
C
C
C
C
C
C
Input capacitance, A0−A10
Input capacitance, OEx
Input capacitance, CASx
Input capacitance, RASx
Input capacitance, WEx
Output capacitance
6
6
pF
pF
pF
pF
pF
pF
i(A)
i(OE)
i(CAS)
i(RAS)
i(W)
6
65
6
9
o
NOTE 2:
V
DD
= NOM supply voltage 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’16ER72xP-40 ’16ER72xP-50 ’16ER72xP-60
PARAMETER
UNIT
MIN
MAX
25
MIN
MAX
30
MIN
MAX
35
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from CASx (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
16
18
20
CAC
CPA
RAC
OEA
CLZ
REZ
CEZ
OEZ
WEZ
Access time from CASx precharge (see Note 4)
Access time from RASx (see Note 4)
27
33
40
45
50
60
Access time from OEx (see Note 4)
16
18
20
Delay time, CASx to output in low impedance
Output buffer turn off delay from RASx (see Note 5)
Output buffer turn off delay from CASx (see Note 5)
Output buffer turn off delay from OEx (see Note 5)
Output buffer turn off delay from WEx (see Note 5)
2
3
5
5
3
2
3
5
5
3
2
3
5
5
3
11
16
16
11
13
18
18
13
15
20
20
15
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
4. Access times are measured with output reference levels of V
=2 V and V =0.8 V.
OL
OH
5. The maximum values of t
, t
, t
, and t are specified when the outputs are no longer driven. Data-in must not be driven
REZ CEZ OEZ
WEZ
until one of the applicable maximum values is satisfied.
EDO timing requirements
’16ER72xP-40
’16ER72xP-50
’16ER72xP-60
UNIT
MIN
16
45
34
5
MAX
MIN
20
55
38
7
MAX
MIN
25
64
46
10
5
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page mode, read-write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
OCH
CP
Delay time, RASx active to CASx precharge
Hold time, OEx from CASx
Hold time, output from CASx
5
5
Pulse duration, CASx active
6
10000
8
10000
10 10000
Pulse duration, WEx active (output disable only)
Setup time, OEx before CASx
Pulse duration, CASx precharge
Precharge time, OEx
5
5
5
5
5
5
6
8
10
5
5
5
OEP
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢏ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢄ ꢐꢀ ꢄ ꢑꢒꢄꢒ ꢍꢒꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕꢖ ꢖ ꢄꢅꢄ ꢒ ꢒꢌ ꢑꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔ ꢒꢕ ꢏꢄ ꢘ
SMMS694 − AUGUST 1997
ac timing requirements (see Note 3)
’16ER72xP-40
’16ER72xP-50
’16ER72xP-60
UNIT
MIN
69
MAX
MIN
84
MAX
MIN
104
140
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write
Cycle time, read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
97
116
RWC
RASP
RAS
RP
Pulse duration, RASx active, fast page mode (see Note 6)
Pulse duration, RASx active, non-page mode (see Note 6)
Pulse duration, RASx precharge
40 100 000
50 100 000
60 100 000
40
25
7
10 000
50
30
9
10 000
60
40
11
11
11
0
10 000
Pulse duration, write command
WP
Pulse duration, RASx active, self-refresh (see Note 9)
Pulse duration, RASx precharge after self-refresh
Setup time, column address
7
9
RASS
RPS
ASC
ASR
DS
7
9
0
0
Setup time, row address
5
5
5
Setup time, data in (see Note 7)
5
5
5
Setup time, read command
0
0
0
RCS
CWL
RWL
Setup time, write command before CASx precharge
Setup time, write command before RASx precharge
7
9
11
12
8
10
Setup time, write command before CASx active
(early-write only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, WEx high before RAS low (CBR refresh only)
Setup time, WEx low before RAS low (test mode only)
Setup time, CASx referenced to RASx (CBR refresh only)
Hold time, column address
7
7
7
7
7
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRP
WTS
CSR
CAH
DH
3
3
3
12
11
4
8
10
15
8
Hold time, data in (see Note 7)
13
6
Hold time, row address
RAH
RCH
RRH
WCH
ROH
WRH
WTH
CHR
OEH
CHS
RHCP
AWD
CPW
CRP
CWD
OED
RAD
Hold time, read command referenced to CASx (see Note 8)
Hold time, read command referenced to RASx (see Note 8)
0
0
0
− 2
7
− 2
9
− 2
11
10
12
12
8
Hold time, write command during CASx active (early-write only)
Hold time, RASx referenced to OEx
6
8
Hold time, WEx high after RAS low (CBR refresh)
Hold time, WEx low after RAS low (test mode only)
Hold time, CASx referenced to RASx (CBR refresh only)
Hold time, OEx command
8
10
10
6
8
4
12
12
27
34
37
3
14
14
33
41
45
3
16
16
40
48
54
3
Hold time, CASx active after RASx precharge (self-refresh)
Hold time, RASx active from CASx precharge
Delay time, column address to write command (read-write only)
Delay time, WEx low after CASx precharge (read-write only)
Delay time, CASx precharge to RASx
Delay time, CASx to write command (read-write only)
Delay time, OEx to data in
31
13
12
35
15
8
39
17
10
Delay time, RASx to column address (see Note 9)
30
20
25
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
6. In a read-write cycle, t
RWD
and t must be observed.
RWL
7. Referenced to the later of CASx or WEx in write operations
8. Either t or t must be satisfied for a read cycle.
9. The maximum value is specified only to ensure access time.
RCH RRH
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆꢇ
ꢈ
ꢉ
ꢂ
ꢃ
ꢊ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢏ
ꢉ
ꢄ ꢐꢀ ꢄꢑ ꢒ ꢄꢒ ꢍꢒ ꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕ ꢖꢖ ꢄꢅ ꢄꢒ ꢒꢌ ꢑ ꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔꢒ ꢕꢏ ꢄꢘ
ꢂ
ꢃ
ꢊ
SMMS694 − AUGUST 1997
ac timing requirements (see Note 3) (continued)
’16ER72xP-40 ’16ER72xP-50 ’16ER72xP-60
UNIT
MIN
25
14
12
3
MAX
MIN
30
17
10
3
MAX
MIN
35
23
12
3
MAX
t
t
t
t
t
t
t
t
t
t
t
Delay time, column address to RASx precharge
Delay time, column address to CASx precharge
Delay time, RASx to CASx (see Note 9)
Delay time, RASx precharge to CASx
Delay time, CASx active to RASx precharge
Delay time, RASx to write command (read-write only)
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RASx (test mode)
Refresh time interval
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RAL
CAL
RCD
RPC
RSH
RWD
TAA
TCPA
TRAC
REF
T
20
47
31
39
16
92
30
35
17
18
67
35
40
55
20
79
40
45
65
32
30
32
30
32
30
Transition time
2
2
2
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
9. The maximum value is specified only to ensure access time.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢏ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢄ ꢐꢀ ꢄ ꢑꢒꢄꢒ ꢍꢒꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕꢖ ꢖ ꢄꢅꢄ ꢒ ꢒꢌ ꢑꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔ ꢒꢕ ꢏꢄ ꢘ
SMMS694 − AUGUST 1997
device symbolization (TM16ER72HP illustrated)
TM16ER72HP
-SS
YYMMT
Buffered Key Position
3.3-V Voltage Key Position
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE A: Location of symbolization may vary.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆꢇ
ꢈ
ꢉ
ꢂ
ꢃ
ꢊ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢏ
ꢉ
ꢄ ꢐꢀ ꢄꢑ ꢒ ꢄꢒ ꢍꢒ ꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕ ꢖꢖ ꢄꢅ ꢄꢒ ꢒꢌ ꢑ ꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔꢒ ꢕꢏ ꢄꢘ
ꢂ
ꢃ
ꢊ
SMMS694 − AUGUST 1997
MECHANICAL DATA
BU (R-PDIM-N168)
DUAL IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
(Note D)
0.054 (1,37)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.046 (1,17)
0.050 (1,27)
0.125 (3,18)
0.039 (1,00) TYP
0.125 (3,18)
0.014 (0,35) MAX
0.118 (3,00) TYP
0.118 (3,00) DIA
2 Places
0.700 (17,78) TYP
1.255 (31,88)
1.245 (31,62)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088183/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-161
D. Dimension includes de-panelization variations; applies between notch and tab edge.
E. Outline may vary above notches to allow router/panelization irregularities.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢏ ꢉ ꢂ ꢃ ꢊ ꢆꢆ ꢆ ꢊ ꢇ ꢂ ꢃ ꢋ ꢌ ꢆꢇ ꢍꢋ ꢎ ꢀ
ꢄ ꢐꢀ ꢄ ꢑꢒꢄꢒ ꢍꢒꢓꢀꢓꢍꢔ ꢕꢀ ꢋꢕꢖ ꢖ ꢄꢅꢄ ꢒ ꢒꢌ ꢑꢓꢁ ꢎꢗ ꢅꢓꢁ ꢁ ꢔ ꢒꢕ ꢏꢄ ꢘ
SMMS694 − AUGUST 1997
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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-
ITT
TM16PN0071
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
TM16PN1181
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
TM16PN1201
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
TM16PN1351
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
TM16PN1361
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
TM16PN1371
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
TM16PN1381
Rack and Panel Connector, 16 Contact(s), Male, PlugWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ITT
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