TM248GBK32 [TI]
DYNAMIC RAM MODULES;
| 型号： | TM248GBK32 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DYNAMIC RAM MODULES |
| 文件： | 总11页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
Organization
Presence Detect
TM124FBK32 . . . 1 048 576 × 32
TM248GBK32 . . . 2 097 152 × 32
Performance Ranges:
ACCESS ACCESS ACCESS EDO
Single 5-V Power Supply
TIME
TIME
TIME CYCLE
72-pin Single In-Line Memory Module
(SIMM) for Use With Sockets
t
t
t
t
HPC
RAC
AA
CAC
(MIN) (MIN)
(MAX)
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
(MAX)
30 ns
35 ns
40 ns
30 ns
35 ns
40 ns
’124FBK32-60
’124FBK32-70
’124FBK32-80
’248GBK32-60
’248GBK32-70
’248GBK32-80
15 ns
18 ns
20 ns
15 ns
18 ns
20 ns
25 ns
30 ns
35 ns
25 ns
30 ns
35 ns
TM124FBK32 Utilizes Eight 4M-Bit Dynamic
RAMs (DRAMs) in Plastic Small-Outline
J-Lead (SOJ) Packages
TM248GBK32 Utilizes Sixteen 4M-Bit
DRAMs in Plastic SOJ Packages
Long Refresh Period
16 ms (1024 Cycles)
Low Power Dissipation
All Inputs, Outputs, Clocks Fully TTL
Compatible
Operating Free-Air Temperature
Range . . . 0°C to 70°C
†
3-State Output
Gold-Tabbed Versions Available:
– TM124FBK32
– TM248GBK32
Common CAS Control for Eight Common
Data-In and Data-Out Lines, In Four Blocks
Tin-Lead- (Solder-) Tabbed Versions
Available:
– TM124FBK32S
Extended Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
– TM248GBK32S
JEDEC First Generation 72-Pin SIMM
Pinout
description
TM124FBK32
The TM124FBK32 is a 4M-byte DRAM organized as four times 1 048 576 × 8 in a 72-pin leadless SIMM. The
SIMM is composed of eight TMS44409, 1 048 576 × 4-bit DRAMs, each in a 20/26-lead plastic SOJ package,
mounted on a substrate together with decoupling capacitors. Each TMS44409 is described in the TMS44409
data sheet. The TM124FBK32 is available in the single-sided BK leadless module for use with sockets.
TM248GBK32
The TM248GBK32 is a 8M-byte DRAM organized as four times 2 097 152 × 8 in a 72-pin leadless SIMM. The
SIMM is composed of sixteen TMS44409, 1 048 576 × 4-bit DRAMs, each in a 20/26-lead plastic SOJ package,
mounted on a substrate together with decoupling capacitors. Each TMS44409 is described in the TMS44409
data sheet. The TM248GBK32 is available in the double-sided BK leadless module for use with sockets.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
operation
TM124FBK32
The TM124FBK32 operates as eight TMS44409DJs connected as shown in the functional block diagram. Refer
to the TMS44409 data sheet for details of operation. The common I/O feature of the TM124FBK32 dictates the
use of early write cycles to prevent contention on D and Q.
TM248GBK32
The TM248GBK32 operates as sixteen TMS44409DJs connected as shown in the functional block diagram.
Refer to the TMS44409 data sheet for details of operation. The common I/O feature of the TM248GBK32
dictates the use of early write cycles to prevent contention on D and Q.
specifications
Refresh period is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS
in order to retain data. A0–A9 address lines must be refreshed every 16 ms as required by the TMS44409
DRAM. CAS can remain high during the refresh sequence to conserve power.
single in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124FBK32 and TM248GBK32: Nickel plate and gold plate over copper
Contact area for TM124FBK32S and TM248GBK32S: Nickel plate and tin-lead over copper
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
†
†
†
BK SINGLE IN-LINE PACKAGE
(TOP VIEW)
TM124FBK32
TM248GBK32
(SIDE VIEW)
(SIDE VIEW)
V
1
2
3
4
5
6
7
8
SS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
V
CC
A8
A9
RAS3
RAS2
NC
NC
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
Address Inputs
SS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
A0–A9
CAS0, CAS3
DQ0–DQ31
NC
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
PD1– PD4
RAS0–RAS3
V
V
CC
Ground
SS
W
Write Enable
V
CC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
PRESENCE DETECT
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
SS
V
SS
NC
V
SS
PD1
PD2
PD3
PD4
TM124FBK32
V
SS
V
SS
V
SS
NC
NC
V
V
NC
NC
SS
SS
NC
NC
NC
NC
NC
NC
NC
V
SS
V
SS
TM248GBK32
V
SS
NC
NC
NC
†
The packages shown here are for pinout reference only and are not drawn to scale.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram (for TM124FBK32 and TM248GBK32, Side 1)
A0–A9
10
RAS0
RAS2
CAS2
W
CAS3
CAS0
CAS1
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
10
10
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ0–
DQ3
DQ8–
DQ11
DQ16–
DQ19
DQ24–
DQ27
10 1M × 4
A0–A9
RAS
10 1M × 4
A0–A9
RAS
10
10
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
W
CAS
OE
W
CAS
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ4–
DQ7
DQ12–
DQ15
DQ20–
DQ23
DQ28–
DQ31
functional block diagram (for TM248GBK32, Side 2)
A0–A9
10
RAS1
RAS3
CAS2
W
CAS3
CAS0
CAS1
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
10
10
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ0–
DQ3
DQ8–
DQ11
DQ16–
DQ19
DQ24–
DQ27
10 1M × 4
A0–A9
RAS
10 1M × 4
A0–A9
RAS
10
10
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
W
CAS
OE
W
CAS
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ4–
DQ7
DQ12–
DQ15
DQ20–
DQ23
DQ28–
DQ31
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM124FBK32, TM124FBK32S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM248GBK32, TM248GBK32S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
6.5
0.8
70
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
’124FBK32-60 ’124FBK32-70 ’124FBK32-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
0.4
0.4
0.4
OL
OL
V = 0 to 6.5 V,
All other pins = 0 to V
V
= 5 V,
I
CC
CC
I
I
I
Input current (leakage)
Output current (leakage)
±10
±10
±10
µA
µA
I
V
O
= 0 to V
,
V
= 5.5 V,
CC
CC
±10
±10
±10
O
CAS high
Read- or write-cycle current
(see Note 3)
Minimum cycle,
V
= 5.5 V
840
720
640
mA
CC1
CC
After one memory cycle,
RAS and CAS high,
16
8
16
8
16
8
V
IH
=2.4 V (TTL)
I
Standby current
mA
CC1
After one memory cycle,
RAS and CAS high,
V
IH
= V
– 0.2 V (CMOS)
CC
Minimum cycle,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
V
= 5.5 V,
CC
Average refresh current
(RAS-only or CBR) (see Note 3)
I
I
840
720
720
640
640
560
mA
mA
CC3
t
= minimum, = 5.5 V,
V
CC
Average page current
(see Note 4)
PC
RAS low, CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
.
IL
4. Measured with a maximum of one address change while CAS = V
.
IH
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
’248GBK32-60 ’248GBK32-70 ’248GBK32-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
0.4
0.4
0.4
OL
OL
V = 0 to 6.5 V,
All other pins = 0 to V
V
= 5 V,
I
CC
CC
I
I
I
Input current (leakage)
Output current (leakage)
±20
±20
±20
µA
µA
I
V
O
= 0 to V
,
V
= 5.5 V,
CC
CC
±20
±20
±20
O
CAS high
Read- or write-cycle current
(see Note 3)
Minimum cycle,
V
= 5.5 V
856
736
656
mA
CC1
CC
After one memory cycle,
RAS and CAS high,
32
16
32
16
32
16
V
IH
=2.4 V (TTL)
I
Standby current
mA
CC1
After one memory cycle,
RAS and CAS high,
V
IH
= V
– 0.2 V (CMOS)
CC
Minimum cycle,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
V
= 5.5 V,
CC
Average refresh current
(RAS-only or CBR)
(see Note 3)
I
I
1680
736
1440
656
1280
576
mA
mA
CC3
t
= minimum, = 5.5 V,
V
CC
Average EDO current
(see Note 4)
PC
RAS low, CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
4. Measured with a maximum of one address change while CAS = V
.
IL
.
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature
f = 1 MHz (see Note 5)
’124FBK32
MIN MAX
’248GBK32
MIN MAX
UNIT
C
C
C
C
C
Input capacitance, address inputs
Input capacitance, RAS
40
28
14
56
7
80
28
pF
pF
pF
pF
pF
i(A)
i(R)
Input capacitance, CAS
28
i(C)
Input capacitance, write-enable input
Output capacitance on DQ pins
112
14
i(W)
o(DQ)
NOTE 5:
V
CC
equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’124FBK32-60
’248GBK32-60
’124FBK32-70
’248GBK32-70
’124FBK32-80
’248GBK32-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
30
15
60
35
35
18
70
40
ns
ns
ns
ns
ns
ns
ns
AA
20
CAC
RAC
CPA
CLZ
REZ
WEZ
Access time from RAS low
80
Access time from column precharge
CAS to output in the low-impedance state
Output disable time after RAS high (see Note 6)
Output disable time after W low (see Note 6)
45
0
3
3
0
3
3
0
3
3
15
15
18
18
20
20
NOTE 6:
t
and t are specified when the output is no longer driven.
WEZ
REZ
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’124FBK32-60
’248GBK32-60
’124FBK32-70
’248GBK32-70
’124FBK32-80
’248GBK32-80
UNIT
MIN
25
80
50
3
MAX
MIN
30
90
55
3
MAX
MIN
35
MAX
t
t
t
t
t
t
t
Cycle time, EDO page-mode read or write
Cycle time, EDO read-write
Hold time, CAS from RAS
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
DOH
CAS
WPE
CP
100
60
Hold time, output from CAS
Pulse duration, CAS
3
10 10000
12 10000
15 10000
Pulse duration, W (output disable only)
Precharge time, CAS
5
5
5
5
5
5
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
timing requirements over recommended range of supply voltage and operating free-air
temperature
’124FBK32-60
’248GBK32-60
’124FBK32-70
’248GBK32-70
’124FBK32-80
’248GBK32-80
UNIT
MIN
110
150
MAX
MIN
130
175
MAX
MIN
150
200
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, read-write
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RC
RWC
RASP
RAS
RP
Pulse duration, page-mode, RAS low
Pulse duration, non-page-mode, RAS low
Pulse duration, RAS high (precharge)
Pulse duration, W low
60 100 000
70 100 000
80 100 000
60
40
10
100
110
0
10 000
70
50
10
100
130
0
10 000
80
60
10
100
150
0
10 000
WP
Pulse duration, self-refresh entry from RAS low
Pulse duration, RAS precharge after self-refresh
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
RASS
RPS
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
0
0
0
RCS
CWL
RWL
WCS
WRP
CAH
DH
10
10
0
12
12
0
15
15
0
Setup time, W high before RAS low (see Note 8)
Hold time, column address after CAS low
Hold time, data after CAS low
10
10
10
10
0
10
15
15
10
0
10
15
15
10
0
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, W high after RAS high (see Note 9)
Hold time, W low after CAS low
RAH
RCH
RRH
WCH
WRH
RHCP
CHS
CHR
CRP
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
0
0
0
10
10
35
– 50
10
5
15
10
40
– 50
10
5
15
10
45
– 50
10
5
Hold time, W high after RAS low (see Note 8)
Hold time, RAS high from CAS precharge
Hold time, CAS low after RAS high (self-refresh)
Delay time, RAS low to CAS high (see Note 8)
Delay time, CAS high to RAS low
Delay time, CAS low to RAS low (see Note 8)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR only)
Delay time, CAS low to RAS high
5
5
5
15
30
20
20
0
30
45
15
35
25
20
0
35
52
15
40
30
20
0
40
60
10
12
15
Refresh time interval
16
30
16
30
16
30
Transition time
2
2
2
NOTES: 7. All cycled times assume t = 5 ns.
T
8. CBR refresh only
9. Either t
or t
must be satisfied for a read cycle.
RCH
RRH
10. Maximum value specified only to assure access time.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124FBK32, TM124FBK32S 1048576 BY 32-BIT
TM248GBK32, TM248GBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULES
SMMS664A – DECEMBER 1995 – REVISED JUNE 1996
MECHANICAL DATA
BK (R-PSIM-N72)
SINGLE-IN-LINE MEMORY MODULE
0.054 (1,37)
0.047 (1,19)
4.255 (108,08)
4.245 (107,82)
0.125 (3,18) TYP
1.005 (25,53)
0.995 (25,27)
0.128 (3,25)
0.120 (3,05)
0.050 (1,27)
0.040 (1,02) TYP
0.010 (0,25) MAX
0.400 (10,16) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
(For Double-Sided SIMM)
4040197/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization (TM124FBK32 illustrated)
TM124FBK32
–SSL
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
–SS = Speed Code
L = Temperature Range
NOTE: Location of symbolization may vary.
10
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