TM2FJ64EPN-60 [TI]
2MX64 EDO DRAM MODULE, 60ns, DMA144, DIMM-144;
| 型号： | TM2FJ64EPN-60 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX64 EDO DRAM MODULE, 60ns, DMA144, DIMM-144 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
Organization
High-Speed, Low-Noise LVTTL Interface
– TM2xJ64xPN-xx . . . 2097152 × 64 Bits
Long Refresh Period:
Single 3.3-V Power Supply
(±10% Tolerance)
– TM2EJ64DPN: 32 ms (2048 cycles)
– TM2EJ64EPN: 64 ms (4096 cycles)
JEDEC 144-Pin Small Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
Low-Power, Battery-Backup Refresh
Available:
– TM2FJ64DPN: 128 ms (2048 cycles)
– TM2FJ64EPN: 128 ms (4096 cycles)
TM2xJ64xPN-xx — Utilizes Eight 16M-Bit
(2M×8-Bit) Dynamic RAMs in TSOPs
3-State Output
Performance ranges
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
ACCESS ACCESS ACCESS
TIME TIME TIME
EDO
CYCLE
t
t
t
t
RAC
CAC
AA
HPC
Serial Presence-Detect (SPD) Using
EEPROM
MAX
50 ns
60 ns
70 ns
MAX
13 ns
15 ns
18 ns
MAX
25 ns
30 ns
35 ns
MIN
’2xJ64xPN-50
’2xJ64xPN-60
’2xJ64xPN-70
20 ns
25 ns
30 ns
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
description
The TM2EJ64DPN is a 16M-byte, 144-pin, small outline dual-in-line memory module (SODIMM). The SODIMM
is composed of eight TMS427809A, 2097152 × 8-bit 2K-refresh EDO dynamic random-access memories
(DRAMs), each in a 400-mil, 28-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a
substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS894).
The TM2EJ64EPN is an 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809A,
2097152 × 8-bit 4K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a
substrate with decoupling capacitors. See the TMS426809A data sheet (literature number SMKS894).
The TM2FJ64DPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS427809AP,
2097152 × 8-bit 2K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809AP data sheet (literature
number SMKS894).
The TM2FJ64EPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809AP,
2097152 × 8-bit 4K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809AP data sheet (literature
number SMKS894).
operation
The TM2xJ64xPN operates as eight TMS42x809A/Ps, connected as shown in the functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
TM2xJ64xPN
(SIDE VIEW)
PIN NOMENCLATURE
Row Address Inputs
†
A[0:11]
A[0:9]
Column Address Inputs
Data In/Data Out
Column-Address Strobe
Row-Address Strobe
Write Enable
DQ[0:63]
CAS[0:7]
RAS0
WE0
1
OE0
Output Enable
SDA
SCL
NC
Serial PD Address/Data
Serial PD Clock
No-Connect Pin
3.3-V Supply
V
DD
V
SS
Ground
†
A11 is NC for TM2xJ64DPN
59
61
143
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
Pin Assignments
PIN
PIN
PIN
PIN
NO.
1
NAME
NO.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NAME
NO.
73
NAME
NO.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NAME
V
V
DQ8
OE
A9
SS
2
DQ40
DQ9
74
NC
NC
SS
3
DQ0
DQ32
DQ1
75
V
V
A10
NC
SS
4
DQ41
DQ10
DQ42
DQ11
DQ43
76
SS
5
77
NC
NC
NC
NC
V
V
DD
6
DQ33
DQ2
78
DD
7
79
CAS2
CAS6
CAS3
CAS7
8
DQ34
DQ3
80
9
V
81
V
DD
DD
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQ35
V
82
V
DD
V
V
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
83
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
V
V
DD
SS
84
DD
SS
DQ4
DQ36
DQ5
85
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
86
87
DQ37
DQ6
88
89
DQ38
DQ7
90
V
V
91
V
V
SS
SS
DQ39
92
SS
SS
V
V
NC
NC
NC
NC
NC
NC
93
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
V
V
SS
DD
94
SS
DD
CAS0
CAS4
CAS1
CAS5
95
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
96
97
98
V
V
V
DD
99
DD
V
DD
100
101
102
103
104
105
106
107
108
DD
A0
A3
A1
A4
A2
A5
NC
NC
V
V
DD
DD
WE0
NC
A6
A7
V
V
SS
SS
RAS0
NC
A8
SDA
SCL
A11
V
SS
NC
V
V
SS
SS
DD
DD
V
SS
NC
V
V
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
small outline dual-in-line memory module and components
The small–outline dual-in-line memory module and components include:
PC substrate: 1,10
0,1 mm (0.04 inch) nominal thickness
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM2xJ64xPN
RAS0
WE0
OE0
RAS0
WE0
OE0
CAS0
CAS OE W RAS
CAS4
CAS OE W RAS
DQ[0:7]
DQ[0:7]
U0
DQ[32:39]
DQ[0:7]
UB0
CAS1
CAS OE W RAS
CAS5
CAS OE W RAS
DQ[8:15]
DQ[0:7]
U1
DQ[40:47]
DQ[0:7]
UB1
CAS6
CAS OE W RAS
CAS2
CAS OE W RAS
DQ[48:55]
DQ[0:7]
UB2
DQ[16:23]
DQ[0:7]
U2
CAS7
CAS OE W RAS
CAS3
CAS OE W RAS
DQ[56:63]
DQ[0:7]
UB3
DQ[24:31]
DQ[0:7]
U3
TM2xJ64DPN:
A[0:10]
SPD EEPROM
A[0:10] : U[0:3], UB[0:3]
A[0:11] : U[0:3], UB[0:3]
SCL
SDA
A0
A1
A2
TM2xJ64EPN:
A[0:11]
V
SS
V
DD
U[0:3], UB[0:3]
Two 0.1 µF
(minimum) per
DRAM
V
SS
U[0:3], UB[0:3]
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM2xP64DPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM2xP64EPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
V
Supply voltage
3
3.3
0
3.6
DD
Supply voltage
V
SS
High-level input voltage
High-level input voltage for the SPD device
Low-level input voltage
Ambient temperature
2
2
V
DD
+ 0.3
V
IH
5.5
0.8
70
V
IH-SPD
IL
–0.3
0
V
T
A
°C
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’2xJ64xPN
PARAMETER
UNIT
MIN MAX
C
C
C
C
C
C
C
C
Input capacitance, A0–A10
Input capacitance, OE0
Input capacitance, CASx
Input capacitance, RAS0
Input capacitance, WE0
Output capacitance
42
58
9
pF
pF
pF
pF
pF
pF
pF
pF
i(A)
i(OE)
i(CAS)
i(RAS)
i(W)
58
58
9
o
Input/output capacitance, SDA input
9
i/o(SDA)
i(SPD)
Input capacitance, SA0, SA1, SA2, SCL inputs
7
NOTE 2:
V
DD
= NOM supply voltage ±10%, and the bias on pins under test is 0 V.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EJ64DPN
’2EJ64DPN-50
’2EJ64DPN-60
’2EJ64DPN-70
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA
= – 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
OH
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
DD
DD
All others = 0 V to V
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
DD
DD
CASx high
O
O
Read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
960
16
8
800
16
8
720
16
8
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RAS0 and CASx high
I
Standby current
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RAS0 and CASx high
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RAS0 cycling,
‡§
‡¶
I
I
960
880
800
720
720
640
mA
mA
CC3
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
= 3.6 V,
t
= MIN,
DD
RAS0 low,
HPC
CASx cycling
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS0 = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM2EJ64EPN
’2EJ64EPN-50
’2EJ64EPN-60
’2EJ64EPN-70
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA
= – 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
OH
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
DD
DD
All others = 0 V to V
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
DD
DD
CASx high
O
O
Read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
720
16
8
560
16
8
480
16
8
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RAS0 and CASx high
I
Standby current
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RAS0 and CASx high
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
‡¶
I
I
720
800
560
720
480
640
mA
mA
CC3
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
= 3.6 V,
t
= MIN,
DD
RAS0 low,
HPC
CASx cycling
CC4
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS0 = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperture
(unless otherwise noted) (continued)
TM2FJ64DPN
’2FJ64DPN-50
’2FJ64DPN-60
’2FJ64DPN-70
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA
= – 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
OH
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
DD
DD
All others = 0 V to V
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
DD
DD
CASx high
O
O
Read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
960
8
800
8
720
8
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RAS0 and CASx high
I
Standby current
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RAS0 and CASx high
1.2
1.2
1.2
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RAS0 cycling,
‡§
‡¶
I
960
800
720
mA
CC3
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
DD
= 3.6 V,
t
= MIN,
HPC
I
I
880
1.6
720
1.6
640
1.6
mA
mA
CC4
RAS0 low,
CASx cycling
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RAS0 < 0.2 V,
CC6
min
RASS
Average battery
back-up
t
V
= 31.25 µs,
t
≤ 300 ns
RC
RAS
operating current
(equivalent
refresh time is
128 ms), CBR
only
– 0.2 V ≤ V ≤ 3.9 V,
DD
IH
0 V ≤ V ≤ 0.2 V, WE0 and OE0 =
I
2.8
2.8
2.8
mA
IL
CC10
V
,
IH
Address and data stable
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS0 = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM2FJ64EPN
’2FJ64EPN-50
’2FJ64EPN-60
’2FJ64EPN-70
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
I
I
I
I
= – 2 mA
= – 100 µA
= 2 mA
LVTTL
2.4
2.4
2.4
High-level output
voltage
OH
OH
OL
OL
V
V
OH
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
0.4
0.2
0.4
0.2
0.4
0.2
Low-level output
voltage
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
I
DD
DD
All others = 0 V to V
I
I
± 10
± 10
± 10
± 10
± 10
± 10
µA
µA
I
Output current
(leakage)
V
= 3.6 V,
V
= 0 V to V ,
DD
DD
CASx high
O
O
Read- or
write-cycle
current
‡§
I
V
V
= 3.6 V,
Minimum cycle
720
8
560
8
480
8
mA
mA
mA
CC1
DD
= 2 V (LVTTL),
IH
After one memory cycle,
RAS0 and CASx high
I
Standby current
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RAS0 and CASx high
1.2
1.2
1.2
Average refresh
current
(RAS-only
V
= 3.6 V,
Minimum cycle,
DD
RAS0 cycling,
‡§
‡¶
I
720
560
480
mA
CC3
CASx high (RAS-only refresh),
RAS0 low after CASx low (CBR)
refresh or CBR)
Average EDO
current
V
DD
= 3.6 V,
t
= MIN,
HPC
I
I
800
2
720
2
640
2
mA
mA
CC4
RAS0 low,
CASx cycling
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RAS0 < 0.2 V,
CC6
min
RASS
Average battery
back-up
t
V
= 31.25 µs,
t
≤ 300 ns
RC
RAS
operating current
(equivalent
refresh time is
128 ms), CBR
only
– 0.2 V ≤ V ≤ 3.9 V,
DD
IH
0 V ≤ V ≤ 0.2 V, WE0 and OE0 =
I
2.8
2.8
2.8
mA
IL
CC10
V
,
IH
Address and data stable
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RAS0 = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’2XJ64xPN-50 ’2XJ64xPN-60 ’2XJ64xPN-70
PARAMETER
UNIT
MIN
MAX
25
MIN
MAX
30
MIN
MAX
35
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from CASx (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
13
15
18
CAC
CPA
RAC
OEA
CLZ
REZ
CEZ
OEZ
WEZ
Access time from CASx precharge (see Note 4)
Access time from RAS0 (see Note 4)
28
35
40
50
60
70
Access time from OE0 (see Note 4)
13
15
18
Delay time, CASx to output in low impedance
Output buffer turn off delay from RAS0 (see Note 5)
Output buffer turn off delay from CASx (see Note 5)
Output buffer turn off delay from OE0 (see Note 5)
Output buffer turn off delay from WE0 (see Note 5)
0
3
3
3
3
0
3
3
3
3
0
3
3
3
3
13
13
13
13
15
15
15
15
18
18
18
18
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
4. Access times are measured with output reference levels of V
=2 V and V =0.8 V.
OL
OH
5. Themaximumvaluesoft
,t
,t
,andt arespecifiedwhentheoutputsarenolongerdriven.Data-inshouldnotbedriven
REZ CEZ OEZ
WEZ
until one of the applicable maximum values is satisfied.
EDO timing requirements (see Note 3)
’2XJ64xPN-50
’2XJ64xPN-60
’2XJ64xPN-70
UNIT
MIN
20
57
40
7
MAX
MIN
25
68
48
10
5
MAX
MIN
30
78
58
10
5
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page mode, read-write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
CP
Delay time, RAS0 active to CASx precharge
Hold time, OE0 from CASx
Hold time, output from CASx
5
Pulse duration, CASx active
8
10000
10 10000
12 10000
Pulse duration, WE0 active (output disable only)
Pulse duration, CASx precharge
Setup time, OE0 before CASx
Precharge time, OE0
7
7
10
10
5
7
10
10
5
8
8
OCH
OEP
5
NOTE 3: With ac parameters, it is assumed that t = 2 ns.
T
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
ac timing requirements (see Note 3)
’2xJ64xPN-50
’2xJ64xPN-60
’2xJ64xPN-70
UNIT
MIN
84
MAX
MIN
104
135
MAX
MIN
124
160
70
70
50
10
100
130
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write
ns
ns
ns
ns
ns
ns
s
RC
Cycle time, read-write
111
RWC
RASP
RAS
RP
Pulse duration, RAS0 active, fast page mode (see Note 6)
Pulse duration, RAS0 active, non-page mode (see Note 6)
Pulse duration, RAS0 precharge
50 100 000
60 100 000
100 000
10 000
50
30
8
10 000
60
40
10
100
110
0
10 000
Pulse duration, write command
WP
Pulse duration, RAS0 active, self refresh (see Note 7)
Pulse duration, RAS0 precharge after self refresh
Setup time, column address
100
90
0
RASS
RPS
ASC
ASR
DS
ns
ns
ns
ns
ns
ns
ns
Setup time, row address
0
0
0
Setup time, data in (see Note 8)
0
0
0
Setup time, read command
0
0
0
RCS
CWL
RWL
Setup time, write command before CASx precharge
Setup time, write command before RAS0 precharge
8
10
10
12
12
8
Setup time, write command before CASx active
(early-write only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
Setup time, WE0 high before RAS0 low (CBR refresh only)
Setup time, CASx referenced to RAS0 (CBR refresh only)
Hold time, column address
10
5
10
5
10
5
ns
ns
ns
ns
ns
ns
ns
WRP
CSR
CAH
DH
8
10
10
10
0
12
12
10
0
Hold time, data in (see Note 8)
8
Hold time, row address
8
RAH
RCH
RRH
Hold time, read command referenced to CASx (see Note 9)
Hold time, read command referenced to RAS0 (see Note 9)
0
0
0
0
Hold time, write command during CASx active
(early-write only)
t
8
10
12
ns
WCH
t
t
t
t
t
t
Hold time, RAS0 referenced to OE0
8
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ROH
WRH
CHR
OEH
RHCP
CHS
Hold time, WE0 high after RAS0 low (CBR refresh only)
Hold time, CASx referenced to RAS0 (CBR refresh only)
Hold time, OE0 command
10
10
10
13
15
18
Hold time, RAS0 active from CASx precharge
Hold time, CASx referenced to RAS0 (self refresh only)
28
35
40
– 50
– 50
– 50
Delay time, column address to write command
(read-write only)
t
42
5
49
5
57
5
ns
ns
AWD
t
Delay time, CASx precharge to RAS0
CRP
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
6. In a read-write cycle, t
RWD
and t
must be observed.
≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.
RWL
7. During the period of 10 µs ≤ t
RASS
8. Referenced to the later of CASx or WE0 in write operations
9. Either t or t must be satisfied for a read cycle.
RRH
RCH
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
ac timing requirements (see Note 3) (continued)
’2xJ64xPN-50
’2xJ64xPN-60
’2xJ64xPN-70
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
t
t
t
t
t
t
t
t
t
Delay time, CASx to write command (read-write only)
Delay time, OE0 to data in
ns
ns
ns
ns
ns
ns
ns
ns
ns
CWD
OED
RAD
RAL
0
0
0
Delay time, RAS0 to column address (see Note 10)
Delay time, column address to RAS0 precharge
Delay time, column address to CASx precharge
Delay time, RAS0 to CASx (see Note 10)
Delay time, RAS0 precharge to CASx
8
10
10
0
12
12
0
8
0
CAL
5
5
5
RCD
RPC
RSH
RWD
5
5
5
Delay time, CASx active to RAS0 precharge
Delay time, RAS0 to write command (read–write only)
8
10
79
12
92
67
Delay time, CASx precharge to write command
(read-write only)
t
45
54
62
ns
CPW
’2EJ64DPN
32
64
32
64
32
64
ms
t
t
Refresh time interval
Transition time
’2EJ64EPN
’2FJ64xPN
REF
128
30
128
30
128
30
2
2
2
ns
T
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
10. The maximum value is specified only to ensure access time.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
Tables in this section list the SPD contents as follows:
Table 1–TM2EJ64DPN
Table 3–TM2FJ64DPN
Table 2–TM2EJ64EPN
Table 4–TM2FJ64EPN
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
serial presence detect (continued)
Table 1. Serial Presence-Detect Data for the TM2EJ64DPN
’2EJ64DPN-50
’2EJ64DPN-60
’2EJ64DPN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written into
serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
11
08h
02h
0Bh
0Ah
01h
256 bytes
EDO
11
08h
02h
0Bh
0Ah
01h
256 bytes
EDO
11
08h
02h
0Bh
0Ah
01h
Fundamental memory type (FPM,
EDO, SDRAM)
Number of row addresses on this
assembly
Number of column addresses on
this assembly
10
10
10
Number of module banks on this
assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of this
assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RAS0 access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
CAC
CAC
CAC
SODIMM configuration type
(non-parity, parity, ECC)
11
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
13
14
62
63
Refresh rate/type
15.6 µs
x8
00h
08h
00h
01h
29h
15.6 µs
x8
00h
08h
00h
01h
35h
15.6 µs
x8
00h
08h
00h
01h
42h
DRAM width, primary DRAM
Error-checking SDRAM data width
SPD revision
N/A
Rev. 1
41
N/A
Rev. 1
53
N/A
Rev. 1
66
Checksum for bytes 0–62
Manufacturer’s JEDEC ID code per
JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
†
Assembly serial number
†
99–125 Manufacturer specific data
†
126–127 Vendor specific data
‡
128–166 System integrator’s specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
serial presence detect (continued)
Table 2. Serial Presence-Detect Data for the TM2EJ64EPN
’2EJ64EPN-50
’2EJ64EPN-60
’2EJ64EPN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Ch
09h
01h
256 bytes
08h
02h
0Ch
09h
01h
256 bytes
08h
02h
0Ch
09h
01h
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
12
EDO
12
EDO
12
Number of row addresses on this
assembly
Number of column addresses on
this assembly
9
9
9
Number of module banks on this
assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of this
assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RAS0 access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
CAC
CAC
CAC
SODIMM configuration type
(non-parity, parity, ECC)
11
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
13
14
62
63
Refresh rate/type
15.6 µs
x8
00h
08h
00h
01h
29h
15.6 µs
x8
00h
08h
00h
01h
35h
15.6 µs
08h
00h
08h
00h
01h
42h
DRAM width, primary DRAM
Error-checking SDRAM data width
SPD revision
N/A
Rev. 1
41
N/A
Rev. 1
53
N/A
Rev. 1
66
Checksum for bytes 0–62
Manufacturer’s JEDEC ID code
per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
†
Assembly serial number
†
99–125 Manufacturer specific data
†
126–127 Vendor specific data
‡
128–166 System integrator’s specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
serial presence detect (continued)
Table 3. Serial Presence-Detect Data for the TM2FJ64DPN
’2FJ64DPN-50
’2FJ64DPN-60
’2FJ64DPN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
11
08h
02h
0Bh
0Ah
01h
256 bytes
EDO
11
08h
02h
0Bh
0Ah
01h
256 bytes
EDO
11
08h
02h
0Bh
0Ah
01h
Fundamental memory type (FPM,
EDO, SDRAM)
Number of row addresses on this
assembly
Number of column addresses on
this assembly
10
10
10
Number of module banks on this
assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of this
assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RAS0 access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
CAC
CAC
CAC
SODIMM configuration type
(non-parity, parity, ECC)
11
12
Non-parity
00h
80h
Non-parity
00h
80h
Non-parity
00h
80h
15.6 µs /
self-refresh
15.6 µs /
self-refresh
15.6 µs /
self-refresh
Refresh rate/type
13
14
62
63
DRAM width, primary DRAM
Error-checking SDRAM data width
SPD revision
x8
N/A
Rev. 1
169
08h
00h
01h
A9h
x8
N/A
Rev. 1
181
08h
00h
01h
B5h
x8
N/A
Rev. 1
194
08h
00h
01h
C2h
Checksum for bytes 0–62
Manufacturer’s JEDEC ID code
per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer specific data
†
126–127 Vendor specific data
‡
128–166 System integrator’s specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
serial presence detect (continued)
Table 4. Serial Presence-Detect Data for the TM2FJ64EPN
’2FJ64EPN-50
’2FJ64EPN-60
’2FJ64EPN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Ch
09h
02h
256 bytes
08h
02h
0Ch
09h
02h
256 bytes
08h
02h
0Ch
09h
02h
Fundamental memory type (FPM,
EDO, SDRAM)
EDO
12
EDO
12
EDO
12
Number of row addresses on this
assembly
Number of column addresses on
this assembly
9
9
9
Number of module banks on this
assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of this
assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RAS0 access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
CAC
CAC
CAC
SODIMM configuration type
(non-parity, parity, ECC)
11
12
Non-parity
00h
80h
Non-parity
00h
80h
Non-parity
00h
80h
15.6 µs/
self-refresh
15.6 µs/
self-refresh
15.6 µs/
self-refresh
Refresh rate/type
13
14
62
63
DRAM width, primary DRAM
Error-checking SDRAM data width
SPD revision
x8
N/A
Rev. 1
169
08h
00h
01h
A9h
x8
N/A
Rev. 1
181
08h
00h
01h
B5h
x8
N/A
Rev. 1
194
08h
00h
01h
C2h
Checksum for bytes 0–62
Manufacturer’s JEDEC ID code
per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer specific data
†
126–127 Vendor specific data
‡
128–166 System integrator’s specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
device symbolization (TM2EJ64DPN illustrated)
TM2EJ64DPN
-SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE A: Location of symbolization may vary.
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM2EJ64DPN, TM2FJ64DPN 2097152 BY 64-BIT
TM2EJ64EPN, TM2FJ64EPN 2097152 BY 64-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES — SODIMM
SMMS685 – AUGUST 1997
MECHANICAL DATA
BDM (R-SODIMM-N144)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69)
2.655 (67,44)
0.044 (1,12)
0.036 (0,91)
Notch 0.157 (4,00) x 0.079 (2,00) Deep
(2 Places)
Notch 0.060 (1,52) x 0.158 (4,01) Deep
0.031 (0,79)
0.024 (0,61) TYP
0.010 (0,25) MAX
0.788 (20,00) TYP
1.005 (25,53)
0.995 (25,27)
0.157 (4,00)
0.126 (3,20)
0.098 (2,49)
0.196 (4,98)
0.095 (2,41) MAX
0.150 (3,81) MAX
(For Double Sided Module Only)
4088187/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-190
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明