TM4100GAD8-60 [TI]
4194304 BY 8-BIT DRAM MODULE;
| 型号： | TM4100GAD8-60 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4194304 BY 8-BIT DRAM MODULE 动态存储器 |
| 文件： | 总7页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C – MARCH 1992 – REVISED JUNE 1995
Organization . . . 4194304 × 8
SINGLE IN-LINE MODULE
(TOP VIEW)
Single 5-V Power Supply (±10% Tolerance)
30-Pin Single In-Line Memory Module
(SIMM) for Use With Sockets
Utilizes Eight 4-Megabit DRAMs in Plastic
Small-Outline J-Lead Packages (SOJs)
V
CC
1
2
3
4
5
6
7
8
9
CAS
DQ1
A0
Long Refresh Period
16 ms (1024 Cycles)
A1
DQ2
A2
All Inputs, Outputs, Clocks Fully TTL
Compatible
A3
V
SS
3-State Output
DQ3 10
A4 11
Performance Ranges:
A5 12
DQ4 13
A6 14
A7 15
DQ5 16
A8 17
A9 18
A10 19
DQ6 20
ACCESS ACCESS ACCESS
TIME TIME TIME
READ
OR
t
t
t
CAC
WRITE
CYCLE
(MIN)
RAC
AA
(MAX)
’4100GAD8-60 60 ns
’4100GAD8-70 70 ns
’4100GAD8-80 80 ns
(MAX)
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20 ns
110 ns
130 ns
150 ns
W
21
22
V
SS
Common CAS Control for Eight Common
Data-In and Data-Out Lines
DQ7 23
NC 24
DQ8 25
NC 26
RAS 27
NC 28
Low Power Dissipation
Operating Free-Air Temperature Range
0°C to 70°C
NC 29
V
CC
30
description
description
The TM4100GAD8 is a dynamic random-access
memory (DRAM) module organized as 4194304
× 8 bits in a 30-pin leadless single in-line memory
module (SIMM).
PIN NOMENCLATURE
A0–A10
CAS
Address Inputs
Column-Address Strobe
The SIMM is composed of eight TMS44100DJ
4194304 × 1-bit DRAMs in 20/26-lead plastic
small-outline J-lead packages (SOJ) mounted on
a substrate with decoupling capacitors.
DQ1–DQ8
NC
Data In/Data Out
No Internal Connection
Row-Address Strobe
5-V Supply
RAS
V
V
CC
Ground
SS
The TM4100GAD8 is available in the AD
single-sided, leadless module for use with
sockets.
W
Write Enable
The TM4100GAD8 is characterized for operation
from 0°C to 70°C.
operation
TheTM4100GAD8operatesaseightTMS44100DJsconnectedasshowninthefunctionalblockdiagram. Refer
to the TMS44100 data sheet for details of its operation. The common I/O feature of the TM4100GAD8 dictates
the use of early-write cycles to prevent contention on D and Q.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C – MARCH 1992 – REVISED JUNE 1995
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
functional block diagram
A0–A10
RAS
CAS
W
4096 × 1
4096 × 1
A0–A10
RAS
CAS
W
11
11
11
11
11
11
11
11
A0–A10
RAS
CAS
W
Q
Q
Q
Q
Q
Q
Q
Q
DQ1
DQ5
V
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
V
V
SS
V
SS
CC
CC
4096 × 1
A0-A10
RAS
CAS
W
4096 × 1
A0–A10
RAS
CAS
W
DQ2
V
DQ6
V
V
SS
V
SS
CC
CC
4096 × 1
A0–A10
RAS
CAS
W
4096 × 1
A0–A10
RAS
CAS
W
DQ3
V
DQ7
V
V
SS
V
SS
CC
CC
4096 × 1
A0–A10
RAS
CAS
W
4096 × 1
A0–A10
RAS
CAS
W
DQ4
V
DQ8
V
V
SS
V
SS
CC
CC
V
CC
SS
C . . . .C
V
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C – MARCH 1992 – REVISED JUNE 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Supply voltage range on V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Operating free-air temperature range, T
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM MAX
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
5.5
6.5
0.8
70
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’4100GAD8-60
’4100GAD8-70 ’4100GAD8-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
±10
±10
±10
µA
µA
I
CC
V
V
= 0 V to V ,
CC
O
±10
±10
±10
O
= 5.5 V,
CAS high
CC
Read- or write-cycle current
(see Note 3)
V
= 5.5 V,
Minimum cycle
840
720
640
mA
CC1
CC
V
IH
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high,
16
8
16
8
16
8
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
CAS high (RAS only);
RAS low after CAS low (CBR )
Average refresh current
(RAS only or CBR )
(see Note 3)
‡
I
I
840
720
720
640
640
560
mA
mA
CC3
‡
V
= 5.5 V, = minimum,
t
Average page current
(see Note 4)
CC
RAS low,
PC
CAS cycling
CC4
‡
CAS-before-RAS (CBR) refresh
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C – MARCH 1992 – REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
MIN
MAX
40
UNIT
pF
C
C
C
C
Input capacitance, A0–A10
Input capacitance, CAS and RAS
Input capacitance, W
i(A)
i(RC)
i(W)
O
56
pF
56
pF
Output capacitance (pins DQ1–DQ8)
12
pF
NOTE 5:
V
CC
= 5 V ± 0.5 V and the bias on the pin under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’4100GAD8-60 ’4100GAD8-70
’4100GAD8-80
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
t
Access time from column address
Access time from CAS low
30
35
40
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
CPA
RAC
CLZ
OFF
Access time from column precharge
Access time from RAS low
35
40
45
60
70
80
CAS to output in low impedance
Output disable time after CAS high (see Note 6)
0
0
0
0
15
0
18
0
20
NOTE 6:
t
is specified when the output is no longer driven.
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4100GAD8-60 ’4100GAD8-70
’4100GAD8-80
UNIT
MIN
110
40
15
0
MAX
MIN
130
45
15
0
MAX
MIN
150
50
20
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Note 8)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
PC
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
CAH
DHR
DH
Delay time, RAS low to CAS high
60
10
15
30
30
20
0
70
10
15
35
35
20
0
80
10
15
40
40
20
0
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low
30
45
35
52
40
60
Delay time, CAS low to RAS high
15
10
50
10
50
18
15
55
15
55
20
15
60
15
60
Hold time, column address after CAS low
Hold time, data after RAS low (see Note 9)
Hold time, data
Hold time, column address after RAS low (see Note 9)
AR
NOTES: 7. All cycle times assume t = 5 ns.
T
ASC
8. To assure t
min, t
should be ≥ t
.
PC
CP
9. The minimum value is measured when t
10. The maximum value is specified only to assure access time.
is set to t
RCD
min as a reference.
RCD
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C – MARCH 1992 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4100GAD8-60
’4100GAD8-70
’4100GAD8-80
UINT
MIN
10
0
MAX
MIN
10
0
MAX
MIN
10
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 11)
Hold time, W high after RAS high (see Note 11)
Hold time, write after CAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RAH
RCH
RRH
WCH
WCR
WRH
WTH
RASP
RAS
CAS
CP
0
0
0
15
50
10
10
15
55
10
10
15
60
10
10
Hold time, W low after RAS low (see Note 9)
Hold time, W high after RAS low (CBR refresh only)
Hold time, W low (test mode only)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, CAS low
60 100 000
70 100 000
80 100 000
60
15
10
40
15
0
10 000
10 000
70
18
10
50
15
0
10 000
10 000
80
20
10
60
15
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, write
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
Setup time, W high before RAS low (CBR refresh only)
Setup time, W low (test mode only)
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RAS (test mode)
Refresh time interval
0
0
0
RCS
CWL
RWL
WCS
WRP
WTS
TAA
15
15
0
18
18
0
20
20
0
10
10
35
40
65
10
10
40
45
75
10
10
45
50
85
TCPA
TRAC
REF
T
16
50
16
50
16
50
Transition time
2
2
2
NOTES: 9. The minimum value is measured when t
is set to t min as a reference.
RCD
RCD
11. Either t
or t
must be satisfied for a read cycle.
RRH
RCH
device symbolization
TM4100GAD8
– SS
YYMMT
YY = Year Code
MM = Month Code
T
= Assembly Site Code
–SS = Speed
NOTE A: The location of symbolization may vary.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100GAD8
4194304 BY 8-BIT DRAM MODULE
SMMS508C – MARCH 1992 – REVISED JUNE 1995
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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