TM4EJ64NPU [TI]
EXTENDED-DATA-OUT DYNAMIC RAM MODULES ââ SODIMM;
| 型号： | TM4EJ64NPU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EXTENDED-DATA-OUT DYNAMIC RAM MODULES ââ SODIMM |
| 文件： | 总24页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
D
Organization
− TM4xJ64xPU-xx . . . 4194304 × 64 Bits
− TM8xJ64xPU-xx . . . 8388608 × 64 Bits
Single 3.3-V Power Supply
( 10% Tolerance)
D
Long Refresh Periods:
− TMxEJ64KPU: 64 ms (4096 Cycles)
− TMxEJ64NPU: 64 ms (8192 Cycles)
− TMxFJ64KPU: 128 ms (4096 Cycles)
− TMxFJ64NPU: 128 ms (8192 Cycles)
D
D
D
Extended Data Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
JEDEC 144-Pin Small-Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
D
D
D
Serial Presence-Detect (SPD) Using
EEPROM
D
D
TM4xJ64xPU-xx — Utilizes Four 64M-Bit
High-Speed (4M×16-Bit) Dynamic RAMs
TM4xJ64xPU-xx — Utilizes Eight 64M-Bit
High-Speed (4M×16-Bit) Dynamic RAMs
Ambient Temperature Range
0°C to 70°C
Performance Ranges
D
High-Speed, Low-Noise LVTTL Interface
ACCESS ACCESS ACCESS EDO
D
High-Reliability 50-Lead 400-Mil-Wide
Surface-Mount Thin Small-Outline Package
(TSOP) (DGE Suffix)
TIME
TIME
TIME CYCLE
t
t
t
t
HPC
RAC
CAC
AA
(MAX)
40 ns
50 ns
60 ns
(MAX)
11 ns
13 ns
15 ns
(MAX)
20 ns
25 ns
30 ns
(MIN)
16 ns
20 ns
25 ns
D
D
3-State Output
’xxJ64xPU-40
’xxJ64xPU-50
’xxJ64xPU-60
Gold-Plated Contacts
description
The TM4xJ64KPU is a 32M-byte, 144-pin, small-outline dual-in-line memory module (SODIMM). The SODIMM
is composed of four TMS465169/P, 4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO
dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package
(TSOP) (DGE suffix) package mounted on a substrate with decoupling capacitors. See the TMS465169/P data
sheet (literature number SMHS566).
The TM4xJ64NPU is a 32M-byte, 144-pin SODIMM. The SODIMM is composed of four TMS464169/P,
4194304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169/P data sheet
(literature number SMHS566).
The TM8xJ64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS465169/P,
4194304 × 16-bit 4K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
The TM8xJ64NPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS464169/P,
4194304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
operation
The TM4xJ64xPU operates as four TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional
block diagram. The TM8xJ64xPU operates as eight TMS46x169/Ps that are connected as shown in the
TMxxJ64xPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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ꢭꢪ ꢫ ꢡ ꢱꢢ ꢬꢯ ꢧ ꢫ ꢪ ꢤꢣ ꢭꢪ ꢰ ꢪ ꢲꢤ ꢬꢦꢪ ꢢꢨꢳ ꢚ ꢯꢧ ꢥꢧ ꢩꢨ ꢪꢥ ꢡꢫ ꢨꢡ ꢩ ꢭꢧ ꢨꢧ ꢧꢢ ꢭ ꢤꢨ ꢯꢪꢥ
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Copyright 1997, Texas Instruments Incorporated
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1
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SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
TM4xJ64xPU TM8xJ64xPU
(SIDE VIEW) (SIDE VIEW)
PIN NOMENCLATURE − TMxxJ64KPU
A[0:11]
A[0:9]
DQ[0:63]
CAS[0:7]
RAS0 and RAS1
WE0
Row Address Inputs
Column Address Inputs
Data In/Data Out
Column-Address Strobe
Row-Address Strobe
Write Enable
1
OE0
Output Enable
SDA
SCL
Serial PD Address/Data
Serial PD Clock
NC
No-Connect Pin
3.3-V Supply
Ground
V
DD
V
SS
PIN NOMENCLATURE − TMxxJ64NPU
A[0:12]
A[0:8]
DQ[0:63]
CAS[0:7]
RAS0 and RAS1
WE0
Row Address Inputs
Column Address Inputs
Data In/Data Out
Column-Address Strobe
Row-Address Strobe
Write Enable
59
61
OE0
Output Enable
SDA
SCL
Serial PD Address/Data
Serial PD Clock
NC
No-Connect Pin
3.3-V Supply
Ground
V
DD
V
SS
143
2
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SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
Pin Assignments
PIN
PIN
PIN
PIN
NO.
1
NAME
NO.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NAME
NO.
73
NAME
OE0
NC
NO.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
NAME
V
V
DQ8
A9
SS
2
DQ40
DQ9
74
A12
A10
NC
SS
3
DQ0
DQ32
DQ1
75
V
V
SS
4
DQ41
DQ10
DQ42
DQ11
DQ43
76
SS
5
77
NC
NC
NC
NC
V
V
DD
6
DQ33
DQ2
78
DD
7
79
CAS2
CAS6
CAS3
CAS7
8
DQ34
DQ3
80
9
V
V
81
V
DD
DD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQ35
82
V
DD
DD
V
V
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
83
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
V
V
DD
SS
84
DD
SS
DQ4
DQ36
DQ5
85
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
86
87
DQ37
DQ6
88
89
DQ38
DQ7
90
V
91
V
SS
SS
SS
SS
DQ39
V
92
V
V
V
NC
NC
NC
NC
NC
NC
93
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
V
V
SS
DD
94
SS
DD
CAS0
CAS4
CAS1
CAS5
95
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
96
97
98
V
V
DD
99
DD
DD
V
V
DD
100
101
102
103
104
105
106
107
108
A0
A3
A1
A4
A2
A5
NC
NC
V
V
DD
DD
WE0
NC
A6
A7
V
V
SS
SS
RAS0
NC
A8
SDA
SCL
A11
V
SS
RAS1
NC
V
V
SS
SS
DD
DD
V
SS
V
V
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SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
small-outline dual-in-line memory module and components
The small-outline dual-in-line memory module and components include:
D
D
D
PC substrate: 1,10 " 0,1 mm (0.04 inch) nominal thickness
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
The following table shows the SODIMM modules and devices (Ux/UBx) that are used.
Table 1. Component Table
MODULE
DEVICES USED
U[0:3]
TM4xJ64xPU
TM8xJ64xPU
U[0:3], UB[0:3]
functional block diagram for the TMxxJ64xPU
RAS0
WE0
OE0
RAS1
CS
LCAS
W
RAS
RAS
RAS
RAS
CS
LCAS
DQ[0:7]
W
RAS
RAS
RAS
RAS
CAS0
DQ[0:7]
DQ[0:7]
U0
UB0
CAS1
DQ[8:15]
UCAS
DQ[8:15]
UCAS
DQ[8:15]
CS
LCAS
W
CS
W
CAS2
DQ[16:23]
LCAS
DQ[0:7]
DQ[0:7]
U1
UB1
CAS3
DQ[24:31]
UCAS
DQ[8:15]
UCAS
DQ[8:15]
CS
W
CS
W
CAS4
DQ[32:39]
LCAS
DQ[0:7]
LCAS
DQ[0:7]
U2
UB2
SPD EEPROM
CAS5
DQ[40:47]
UCAS
UCAS
SCL
SDA
DQ[8:15]
DQ[8:15]
A0
A1
A2
V
SS
CS
W
CS
W
CAS6
DQ[48:55]
LCAS
LCAS
DQ[0:7]
DQ[0:7]
†
A[0:12] U[0:3], UB[0:3]
A[0:12]
U3
UB3
LEGEND: SPD = Serial Presence Detect
CS = Chip Select
CAS7
DQ[56:63]
UCAS
UCAS
DQ[8:15]
DQ[8:15]
†
4
A12 is not used in TM4xJ64KPU, TM8xP64KPU
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢉ
ꢕ
ꢌ
ꢕꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖ
ꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
DD
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM4xJ64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W
TM8xJ64xPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
V
Supply voltage
3
3.3
0
3.6
DD
SS
IH
Supply voltage
V
High-level input voltage
2
2
V
DD
+ 0.3
V
-SPD High-level input voltage for the SPD device
Low-level input voltage
5.5
0.8
70
V
IH
IL
−0.3
0
V
T
A
Ambient temperature
°C
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂꢊ
ꢀꢁ
ꢁ
ꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖ
ꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM4xJ64KPU
’4xJ64KPU-40
’4xJ64KPU-50
’4xJ64KPU-60
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= − 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= − 100 µA
= 2 mA
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
10
10
10
10
10
10
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V = 0 V to V
O DD
,
DD
CASx high
I
O
Average
read- or
write-cycle
current
‡§
I
V
= 3.6 V,
DD
Minimum cycle
640
4
520
4
440
4
mA
mA
CC1
V
IH
= 2 V LVTTL),
After one memory cycle,
RASx and CASx high
Average
standby
current
I
CC2
V
= V − 0.2 V
DD
IH
(LVCMOS),
’4EJ64KPU
’4FJ64KPU
2
2
2
mA
mA
After one memory cycle,
RASx and CASx high
.6
.6
.6
RASx-only
refresh,
average
refresh
V
= 3.6 V,
Minimum cycle,
CASx high
DD
RASx cycling,
§
I
640
520
440
CC3
curren
V
= 3.6 V,
t
= MIN,
Average
EDO current
DD
RASx low,
HPC
‡¶
I
I
600
640
480
520
400
440
mA
mA
CC4
CASx cycling
Average
CBR refresh
current
V
DD
= 3.6 V,
Minimum cycle,
CC5
RASx low after CASx low
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RASx < 0.2 V,
min
#
I
I
1.2
1.6
1.2
1.6
1.2
1.6
mA
mA
CC6
RASS
Average
battery
back-up
operating
current,
CBR only
t
V
= 31.25 µs,
DD
t
≤ 300 ns,
RC
RAS
− 0.2 V ≤ V ≤ 3.9 V,
IH
#
CC10
0 V ≤ V ≤ 0.2 V, WE0 and OE0 = V
Address and data stable
,
IL
IH
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
For TM4FJ64KPU only
HPC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢀꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗ
ꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4xJ64NPU
’4xJ64NPU-40
’4xJ64NPU-50
’4xJ64NPU-60
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= − 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= − 100 µA
= 2 mA
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
10
10
10
10
10
10
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V = 0 V to V
O DD
,
DD
CASx high
I
O
Average
read- or
write-cycle
current
‡§
I
V
= 3.6 V,
DD
Minimum cycle
540
4
440
4
400
4
mA
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
Average
standby
current
I
CC2
V
= V − 0.2 V
DD
IH
(LVCMOS),
’4EJ64NPU
’4FJ64NPU
2
2
2
mA
mA
After one memory cycle,
RAS and CASx high
.6
.6
.6
RASx-only
refresh,
average
refresh
V
= 3.6 V,
Minimum cycle,
CASx high
DD
RASx cycling,
§
I
540
440
400
CC3
curren
V
= 3.6 V,
t
= MIN,
Average
EDO current
DD
RASx low,
HPC
‡¶
I
I
560
640
440
520
360
440
mA
mA
CC4
CASx cycling
Average
CBR refresh
current
V
DD
= 3.6 V,
Minimum cycle,
CC5
RASx low after CASx low
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RASx < 0.2 V,
min
#
I
I
1.2
1.6
1.2
1.6
1.2
1.6
mA
mA
CC6
RASS
Average
battery
back-up
operating
current, CBR
only
t
V
= 31.25 µs,
DD
t
≤ 300 ns,
RC
RAS
− 0.2 V ≤ V ≤ 3.9 V,
IH
#
CC10
0 V ≤ V ≤ 0.2 V, WE0 and OE0 = V
Address and data stable
,
IL
IH
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
For TM4FJ64NPU only
HPC
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂꢊ
ꢀꢁ
ꢁ
ꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖ
ꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM8xJ64KPU
’8xJ64KPU-40
’8xJ64KPU-50
’8xJ64KPU-60
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= − 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= − 100 µA
= 2 mA
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
10
10
10
10
10
10
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V = 0 V to V
O DD
,
DD
CASx high
I
O
Average
read- or
write-cycle
current
‡§
I
V
= 3.6 V,
DD
Minimum cycle
644
8
524
8
444
8
mA
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
Average
standby
current
I
CC2
V
= V − 0.2 V
DD
IH
(LVCMOS),
’8EJ64KPU
’8FJ64KPU
4
4
4
mA
mA
After one memory cycle,
RASx and CASx high
1.2
1.2
1.2
RASx-only
refresh,
average
refresh
V
= 3.6 V,
Minimum cycle,
CASx high
DD
RASx cycling,
§
I
644
524
444
CC3
curren
V
= 3.6 V,
t
= MIN,
Average
EDO current
DD
RASx low,
HPC
‡¶
I
I
604
644
484
524
404
444
mA
mA
CC4
CASx cycling
Average
CBR refresh
current
V
DD
= 3.6 V,
Minimum cycle,
CC5
RASx low after CASx low
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RASx < 0.2 V,
min
#
I
I
2.4
3.2
2.4
3.2
2.4
3.2
mA
mA
CC6
RASS
Average
battery
back-up
operating
current,
CBR only
t
V
= 31.25 µs,
DD
t
≤ 300 ns,
RC
RAS
− 0.2 V ≤ V ≤ 3.9 V,
IH
#
CC10
0 V ≤ V ≤ 0.2 V, WE0 and OE0 = V
Address and data stable
,
IL
IH
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
For TM8FJ64KPU only
HPC
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢀꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕ
ꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM8xJ64NPU
’8xJ64NPU-40
’8xJ64NPU-50
’8xJ64NPU-60
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= − 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= − 100 µA
= 2 mA
LVCMOS
LVTTL
V
−0.2
V
−0.2
V
−0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
10
10
10
10
10
10
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V = 0 V to V
O DD
,
DD
CASx high
I
O
Average
read- or
write-cycle
current
‡§
I
V
= 3.6 V,
DD
Minimum cycle
544
8
444
8
404
8
mA
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
Average
standby
current
I
CC2
V
= V − 0.2 V
DD
IH
(LVCMOS),
’8EJ64NPU
’8FJ64NPU
4
4
4
mA
mA
After one memory cycle,
RASx and CASx high
1.2
1.2
1.2
RASx-only
refresh,
average
refresh
V
= 3.6 V,
Minimum cycle,
CASx high
DD
RASx cycling,
§
I
544
444
404
CC3
curren
V
= 3.6 V,
t
= MIN,
Average
EDO current
DD
RASx low,
HPC
‡¶
I
I
564
644
444
524
364
444
mA
mA
CC4
CASx cycling
Average
CBR refresh
current
V
DD
= 3.6 V,
Minimum cycle,
CC5
RASx low after CASx low
Average
self-refresh
current
CASx < 0.2 V,
Measured after t
RASx < 0.2 V,
min
#
I
I
2.4
3.2
2.4
3.2
2.4
3.2
mA
mA
CC6
RASS
Average
battery
back-up
operating
current,
CBR only
t
V
= 31.25 µs,
DD
t
≤ 300 ns,
RC
RAS
− 0.2 V ≤ V ≤ 3.9 V,
IH
#
CC10
0 V ≤ V ≤ 0.2 V, WE0 and OE0 = V
Address and data stable
,
IL
IH
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change during each EDO cycle, t
For TM8FJ64NPU only
HPC
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂꢊ
ꢀꢁ
ꢁ
ꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’4xJ64xPU
’8xJ64xPU
PARAMETER
UNIT
MIN MAX
MIN MAX
C
C
C
C
C
C
Input capacitance, A0−A12
22
16
9
42
30
9
pF
pF
pF
pF
pF
pF
i(A)
Input capacitance, OE0
Input capacitance, CASx
Input capacitance, RASx
Input capacitance, WE0
Output capacitance
i(OE)
i(CAS)
i(RAS)
i(W)
16
16
9
16
30
16
o
C
C
Input/output capacitance, SDA input
9
7
9
7
pF
pF
i/o(SDA)
i(SPD)
Input capacitance,SPD inputs (except SDA)
NOTE 2:
V
DD
= NOM supply voltage 10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’xxJ64xPU-40 ’xxJ64xPU-50 ’xxJ64xPU-60
PARAMETER
UNIT
MIN
MAX
20
MIN
MAX
25
MIN
MAX
30
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from CASx (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
11
13
15
CAC
CPA
RAC
OEA
CLZ
OEZ
REZ
CEZ
WEZ
Access time from CASx precharge (see Note 4)
Access time from RASx (see Note 4)
22
28
35
40
50
60
Access time from OE0 (see Note 4)
11
13
15
Delay time, CASx to output in the low-impedance state
Output buffer turnoff delay from OE0 (see Note 5)
Output buffer turnoff delay from RASx (see Note 5)
Output buffer turnoff delay from CASx (see Note 5)
Output buffer turnoff delay from WE0 (see Note 5)
0
3
3
3
3
0
3
3
3
3
0
3
3
3
3
11
11
11
11
13
13
13
13
15
15
15
15
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
4. Access times are measured with output reference levels of V
= 2 V and V = 0.8 V.
OL
OH
5. The MAX specifications of t
, t
, t
and t are specified when the output is no longer driven. Data-in should not be driven
REZ CEZ WEZ
OEZ
until one of the applicable maximum specifications is satsified.
EDO timing requirements (see Note 3)
’xxJ64xPU-40
’xxJ64xPU-50
’xxJ64xPU-60
UNIT
MIN
16
47
32
5
MAX
MIN
20
57
40
5
MAX
MIN
25
68
48
5
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page-mode read or write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
CP
Delay time, RASx active to CASx precharge
Hold time, OE0 from CASx
Hold time, output from CASx active
Pulse duration, CASx active (see Note 6)
Pulse duration, WE0 (output disable only)
Pulse duration, CASx precharge
5
5
5
6
10000
8
10000
10
5
10000
5
5
6
8
10
5
Setup time, OE0 before CASx
5
5
OCH
OEP
Precharge time, OE0 (output disable only)
5
5
5
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
6. In a read-write cycle, t
CWD
and t must be observed.
CWL
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢈ
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ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎ
ꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
ac timing requirements (see Note 3)
’xxJ64xPU-40
’xxJ64xPU-50
’xxJ64xPU-60
UNIT
MIN
69
MAX
MIN
84
MAX
MIN
104
135
MAX
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, read-write
92
111
RWC
RASP
RAS
RP
Pulse duration, RASx active, page mode (see Note 7)
40 100 000
50 100 000
60 100 000
Pulse duration, RASx active, nonpage mode (see Note 7)
Pulse duration, RASx precharge
40
25
6
10 000
50
30
8
10 000
60
40
10
0
10 000
Pulse duration, write command
WP
Setup time, column address
0
0
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data in (see Note 8)
0
0
0
Setup time, read command
0
0
0
RCS
CWL
RWL
Setup time, write command before CASx precharge
Setup time, write command before RASx precharge
6
8
10
10
6
8
Setup time, write command before CASx active
(early-write only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
Setup time, write before RASx active (CBR refresh only)
Setup time, CASx referenced to RASx (CBR refresh only)
Hold time, column address
5
5
6
6
6
0
0
5
5
8
8
8
0
0
5
5
ns
ns
ns
ns
ns
ns
ns
WRP
CSR
CAH
DH
10
10
10
0
Hold time, data in (see Note 8)
Hold time, row address
RAH
RCH
RRH
Hold time, read command referenced to CASx (see Note 9)
Hold time, read command referenced to RASx (see Note 9)
0
Hold time, write command during CASx active
(early-write only)
t
6
8
10
ns
WCH
t
t
t
t
t
Hold time, RASx active from CASx precharge
Hold time, OE0 command
22
11
28
13
8
35
15
ns
ns
ns
ns
ns
RHCP
OEH
ROH
WRH
CHS
Hold time, RASx referenced to OE0
6
10
Hold time, write after RASx active (CBR refresh only)
Hold time, CASx active after RASx precharge (self-refresh)
6
8
10
− 50
− 50
− 50
Delay time, column address to write command
(read-write only)
t
35
42
49
ns
AWD
t
t
Delay time, CASx referenced to RASx (CBR refresh only)
Delay time, CASx precharge to RASx
6
5
8
5
10
5
ns
ns
CHR
CRP
Delay time, CASx to write command
(read-write operation only)
t
26
30
34
ns
CWD
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
7. In a read-write cycle, t
and t must be observed.
RWD
RWL
8. Referenced to the later of CASx or WE0 in write operations
9. Either t or t must be satisfied for a read cycle.
RRH RCH
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢁ
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ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂ
ꢊ
ꢀꢁ
ꢁ
ꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
ac timing requirements (see Note 3) (continued)
’xxJ64xPU-40 ’xxJ64xPU-50 ’xxJ64xPU-60
UNIT
MIN
11
8
MAX
MIN
13
10
25
15
12
5
MAX
MIN
15
12
30
18
14
5
MAX
t
t
t
t
t
t
t
t
t
t
t
Delay time, OE0 to data in
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ms
ms
ns
OED
RAD
RAL
Delay time, RASx to column address (see Note 10)
Delay time, column address to RASx precharge
Delay time, column address to CASx precharge
Delay time, RASx to CASx (see Note 10)
Delay time, RASx precharge to CASx
20
25
30
20
12
10
5
CAL
29
37
45
RCD
RPC
RSH
RWD
CPW
RASS
RPS
Delay time, CASx active to RASx precharge
Delay time, RASx active to write command (read-write only)
6
8
10
79
54
100
110
55
37
100
70
67
45
100
90
Delay time, CASx precharge to write command (read-write only)
Pulse duration, RASx active, self-refresh (see Note 11)
Pulse duration, RASx precharge after self refresh
’xEJ64xPU
64
128
50
64
128
50
64
128
50
t
Refresh time interval
REF
T
’xFJ64xPU
t
Transition time
1
1
1
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
10. The maximum value is specified only to assure access time.
11. During the period of 10 µs ≤ t
RASS
≤ 100 µs, the device is in transition state from normal operational mode to self-refresh mode.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢅ
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ꢀ
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ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎ
ꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢀꢁ
ꢕ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect
The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
Tables in this section list the SPD contents as follows:
Table 2—TM4EJ64KPU
Table 4—TM8EJ64KPU
Table 6—TM4FJ64KPU
Table 8—TM8FJ64KPU
Table 3—TM4EJ64NPU
Table 5—TM8EJ64NPU
Table 7—TM4FJ64NPU
Table 9—TM8FJ64NPU
Table 2. Serial-Presence-Detect Data for the TM4EJ64KPU
’4EJ64KPU-40
’4EJ64KPU-50
’4EJ64KPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
12
08h
02h
0Ch
0Ah
01h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
01h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
01h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
10
10
10
Number of module banks on
this assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
12
13
Refresh rate/type
15.6 µs
00h
10h
15.6 µs
00h
10h
15.6 µs
00h
10h
DRAM width, primary DRAM
x16
x16
x16
Error-checking SDRAM data
width
14
N/A
00h
N/A
00h
N/A
00h
62
63
SPD revision
Rev. 1
38
01h
26h
Rev. 1
50
01h
32h
Rev. 1
62
01h
3Eh
Checksum for bytes 0−62
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂꢊ
ꢀꢁ
ꢁꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖ
ꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM4EJ64KPU (Continued)
’4EJ64KPU-40
’4EJ64KPU-50
’4EJ64KPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
data
128−166
TBD
TBD
TBD
‡
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢀꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖ
ꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM4EJ64NPU
’4EJ64NPU-40
’4EJ64NPU-50
’4EJ64NPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Dh
09h
01h
256 bytes
08h
02h
0Dh
09h
01h
256 bytes
08h
02h
0Dh
09h
01h
Fundamental memory type
(FPM, EDO, SDRAM)
EDO
13
EDO
13
EDO
13
Number of row addresses on
this assembly
Number of column addresses
on this assembly
9
9
9
Number of module banks on
this assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
12
13
Refresh rate/type
15.6 µs
00h
10h
15.6 µs
00h
10h
15.6 µs
00h
10h
DRAM width, primary DRAM
x16
x16
x16
Error-checking SDRAM data
width
14
N/A
00h
N/A
00h
N/A
00h
62
63
SPD revision
Rev. 1
38
01h
26h
Rev. 1
50
01h
32h
Rev. 1
62
01h
3Eh
Checksum for bytes 0−62
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
data
128−166
TBD
TBD
TBD
‡
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂꢊ
ꢀ
ꢁ
ꢁꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM8EJ64KPU
’8EJ64KPU-40
’8EJ64KPU-50
’8EJ64KPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
12
08h
02h
0Ch
0Ah
02h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
02h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
02h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
10
10
10
Number of module banks on
this assembly
2 banks
64 bits
2 banks
64 bits
2 banks
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
12
13
Refresh rate/type
15.6 µs
00h
10h
15.6 µs
00h
10h
15.6 µs
00h
10h
DRAM width, primary DRAM
x16
x16
x16
Error-checking SDRAM data
width
14
N/A
00h
N/A
00h
N/A
00h
62
63
SPD revision
Rev. 1
39
01h
27h
Rev. 1
51
01h
33h
Rev. 1
63
01h
3Fh
Checksum for bytes 0−62
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
data
128−166
TBD
TBD
TBD
‡
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢀ
ꢁ
ꢕ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕ
ꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗ
ꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 5. Serial-Presence-Detect Data for the TM8EJ64NPU
8EJ64NPU-40
’8EJ64NPU-50
’8EJ64NPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Dh
09h
02h
256 bytes
08h
02h
0Dh
09h
02h
256 bytes
08h
02h
0Dh
09h
02h
Fundamental memory type
(FPM, EDO, SDRAM)
EDO
13
EDO
13
EDO
13
Number of row addresses on
this assembly
Number of column addresses
on this assembly
9
9
9
Number of module banks on
this assembly
2 banks
64 bits
2 banks
64 bits
2 banks
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
12
13
Refresh rate/type
15.6 µs
00h
10h
15.6 µs
00h
10h
15.6 µs
00h
10h
DRAM width, primary DRAM
x16
x16
x16
Error-checking SDRAM data
width
14
N/A
00h
N/A
00h
N/A
00h
62
63
SPD revision
Rev. 1
39
01h
27h
Rev. 1
51
01h
33h
Rev. 1
63
01h
3Fh
Checksum for bytes 0−62
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
data
128−166
TBD
TBD
TBD
‡
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂ
ꢊ
ꢀꢁ
ꢁꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖ
ꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 6. Serial-Presence-Detect Data for the TM4FJ64KPU
’4FJ64KPU-40
’4FJ64KPU-50
’4FJ64KPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
12
08h
02h
0Ch
0Ah
01h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
01h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
01h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
10
10
10
Number of module banks on
this assembly
1 banks
64 bits
1 banks
64 bits
1 banks
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
15.6 µs/self-
refresh
15.6 µs/self-
refresh
15.6 µs/self-
refresh
12
13
14
Refresh rate/type
80h
10h
00h
80h
10h
00h
80h
10h
00h
DRAM width, primary DRAM
x16
N/A
x16
N/A
x16
N/A
Error-checking SDRAM data
width
62
63
SPD revision
Rev. 1
166
01h
A6h
Rev. 1
178
01h
B2h
Rev. 1
190
01h
Checksum for bytes 0−62
BEh
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
128−166
TBD
TBD
TBD
‡
data
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢀ
ꢁ
ꢕ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕ
ꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 7. Serial-Presence-Detect Data for the TM4FJ64NPU
’4FJ64NPU-40
’4FJ64NPU-50
’4FJ64NPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Dh
09h
01h
256 bytes
08h
02h
0Dh
09h
01h
256 bytes
08h
02h
0Dh
09h
01h
Fundamental memory type
(FPM, EDO, SDRAM)
EDO
13
EDO
13
EDO
13
Number of row addresses on
this assembly
Number of column addresses
on this assembly
9
9
9
Number of module banks on
this assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
15.6 µs/self-
refresh
15.6 µs/self-
refresh
15.6 µs/self-
refresh
12
13
14
Refresh rate/type
80h
10h
00h
80h
10h
00h
80h
10h
00h
DRAM width, primary DRAM
x16
N/A
x16
N/A
x16
N/A
Error-checking SDRAM data
width
62
63
SPD revision
Rev. 1
166
01h
A6h
Rev. 1
178
01h
B2h
Rev. 1
190
01h
Checksum for bytes 0−62
BEh
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
128−166
TBD
TBD
TBD
‡
data
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂꢊ
ꢀꢁ
ꢁ
ꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 8. Serial-Presence-Detect Data for the TM8FJ64KPU
’8FJ64KPU-40
’8FJ64KPU-50
’8FJ64KPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
12
08h
02h
0Ch
0Ah
02h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
02h
256 bytes
EDO
12
08h
02h
0Ch
0Ah
02h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
10
10
10
Number of module banks on
this assembly
2 banks
64 bits
2 banks
64 bits
2 banks
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
SODIMM configuration type
t
= 40 ns
= 11 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
t
CAC
CAC
CAC
11
(non-parity,
parity,
error
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
15.6 µs/self-
refresh
15.6 µs/self-
refresh
15.6 µs/self-
refresh
12
13
14
Refresh rate/type
80h
10h
00h
80h
10h
00h
80h
10h
00h
DRAM width, primary DRAM
x16
N/A
x16
N/A
x16
N/A
Error-checking SDRAM data
width
62
63
SPD revision
Rev. 1
167
01h
A7h
Rev. 1
179
01h
B3h
Rev. 1
191
01h
BFh
Checksum for bytes 0−62
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
128−166
TBD
TBD
TBD
‡
data
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎ
ꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢀ
ꢁ
ꢕ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢕ
ꢌ
ꢕꢕ
ꢌ
ꢐ
ꢕ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓꢑ
ꢔ
ꢀ
ꢃ
ꢖꢀ
ꢃ
ꢊ
ꢗ
ꢃ
ꢗ
ꢓ
ꢗ
ꢘ
ꢀ
ꢘ
ꢓ
ꢙ
ꢈ
ꢀ
ꢗ
ꢒ
ꢊ
ꢘ
ꢁ
ꢔ
ꢚ
ꢛ
ꢘ
ꢁ
ꢁ
ꢙ
ꢗ
ꢈ
ꢜ
ꢃ
ꢝ
ꢞ
ꢝ
ꢙ
ꢗꢔ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
serial presence detect (continued)
Table 9. Serial-Presence-Detect Data for the TM8FJ64NPU
8FJ64NPU-40
’8FJ64NPU-50
’8FJ64NPU-60
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes written
into serial memory during
module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Dh
09h
02h
256 bytes
08h
02h
0Dh
09h
02h
256 bytes
08h
02h
0Dh
09h
02h
Fundamental memory type
(FPM, EDO, SDRAM)
EDO
13
EDO
13
EDO
13
Number of row addresses on
this assembly
Number of column addresses
on this assembly
9
9
9
Number of module banks on
this assembly
2 banks
64 bits
2 banks
64 bits
2 banks
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
t
t
= 40 ns
= 19 ns
28h
0Bh
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
RAC
RAC
RAC
10
CAC
CAC
CAC
DIMM
(non-parity,
configuration
parity,
type
error
11
Non-parity
00h
Non-parity
00h
Non-parity
00h
correcting code [ECC])
15.6 µs/self-
refresh
15.6 µs/self-
refresh
15.6 µs/self-
refresh
12
13
14
Refresh rate/type
80h
10h
00h
80h
10h
00h
80h
10h
00h
DRAM width, primary DRAM
x16
N/A
x16
N/A
x16
N/A
Error-checking SDRAM data
width
62
63
SPD revision
Rev. 1
167
01h
A7h
Rev. 1
179
01h
B3h
Rev. 1
191
01h
BFh
Checksum for bytes 0−62
Manufacturer’s JEDEC ID code
per JEP-106E
64−71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73−90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93−94
95−98
Manufacturing date
†
Assembly serial number
†
99−125 Manufacturer specific data
†
126−127 Vendor specific data
System integrator’s specific
128−166
TBD
TBD
TBD
‡
data
167−255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module dependent.
These TBD values are determined and programmed by the customer (optional).
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢃ
ꢁ
ꢁ
ꢂ
ꢕ
ꢃ
ꢃ
ꢃ
ꢊ
ꢄ
ꢄ
ꢅ
ꢅ
ꢗ
ꢂ
ꢂ
ꢃ
ꢆ
ꢆ
ꢗ
ꢇ
ꢇ
ꢓ
ꢈ
ꢈ
ꢗ
ꢉ
ꢉ
ꢘ
ꢀ
ꢁ
ꢕ
ꢂ
ꢃ
ꢙ
ꢃ
ꢄ
ꢈ
ꢄ
ꢅ
ꢅ
ꢀ
ꢂ
ꢊ
ꢇ
ꢒ
ꢇ
ꢈ
ꢊ
ꢈ
ꢉ
ꢘ
ꢉ
ꢀ
ꢁ
ꢕ
ꢂ
ꢋ
ꢛ
ꢋ
ꢄ
ꢄ
ꢅ
ꢘ
ꢅ
ꢂ
ꢁ
ꢂ
ꢆ
ꢆ
ꢇ
ꢁ
ꢇ
ꢈ
ꢙ
ꢈ
ꢉ
ꢗ
ꢉ
ꢀ
ꢀ
ꢈ
ꢁ
ꢂ
ꢋ
ꢋ
ꢝ
ꢄ
ꢅ
ꢂ
ꢂ
ꢊ
ꢝ
ꢊ
ꢇ
ꢙ
ꢇ
ꢈ
ꢗ
ꢈ
ꢉ
ꢔ
ꢉ
ꢂ
ꢌ
ꢎ
ꢕ
ꢂ
ꢌ
ꢌ
ꢐ
ꢕ
ꢂ
ꢑ
ꢒ
ꢅ
ꢅ
ꢂ
ꢂ
ꢓ
ꢓ
ꢑ
ꢑ
ꢔ
ꢔ
ꢀ
ꢀ
ꢀ
ꢁ
ꢂ
ꢊ
ꢀꢁ
ꢁꢕ
ꢄ
ꢅ
ꢕ
ꢌ
ꢑ
ꢒ
ꢖ
ꢀ
ꢀ
ꢘ
ꢓ
ꢗ
ꢁ
ꢔ
ꢚ
ꢜ
ꢃ
ꢞ
ꢁ
ꢁ
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
device symbolization (TM4EJ64KPU illustrated)
TM4EJ64KPU
-SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTES: A. Location of symbolization may vary.
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁꢂ
ꢋ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢂ
ꢌ
ꢎ
ꢂ
ꢌ
ꢐ
ꢂ
ꢑ
ꢒ
ꢅ
ꢂ
ꢓ
ꢑ
ꢔ
ꢀ
ꢀꢁ
ꢕ
ꢃꢄ
ꢅ
ꢂ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢃ
ꢄ
ꢅ
ꢂ
ꢊ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢕ
ꢋ
ꢄ
ꢅ
ꢂ
ꢆ
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SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
MECHANICAL DATA
BDM (R-SODIMM-N144)
SMALL OUTLINE DUAL IN-LINE MEMORY MODULE
2.665 (67,69)
2.655 (67,44)
0.044 (1,12)
Notch 0.060 (1,52) x 0.158 (4,01) Deep
0.036 (0,91)
Notch 0.157 (4,00) x 0.079 (2,00) Deep
(2 Places)
0.031 (0,79)
0.024 (0,61) TYP
0.098 (2,49)
0.010 (0,25) MAX
0.788 (20,00) TYP
1.005 (25,53)
0.995 (25,27)
0.157 (4,00)
0.126 (3,20)
0.196 (4,98)
0.095 (2,41) MAX
0.150 (3,81) MAX
(For Double Sided Module Only)
4088187/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-190
23
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