TM4EP72BJN-50 [TI]
EXTENDED-DATA-OUT DYNAMIC RAM MODULES; 扩展-DATA -OUT动态内存模块
| 型号： | TM4EP72BJN-50 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | EXTENDED-DATA-OUT DYNAMIC RAM MODULES |
| 文件： | 总22页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
Organization
Long Refresh Periods:
– TM4EP64xxN-xx . . . 4194304 × 64 Bits
– TM4EP72xxN-xx . . . 4194304 × 72 Bits
– TM4EPxxCxN: 64 ms (4096 Cycles)
– TM4EPxxBxN: 32 ms (2048 Cycles)
Single 3.3-V Power Supply
3-State Output
(±10% Tolerance)
Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
Serial Presence-Detect (SPD) Using
EEPROM
TM4EP64xxN-xx — Utilizes Sixteen 16M-Bit
High-Speed (4M×4-Bit) Dynamic RAMs
Ambient Temperature Range
TM4EP72xxN-xx — Utilizes Eighteen
16M-Bit High-Speed (4M×4-Bit) Dynamic
RAMs
0°C to 70°C
Gold-Plated Contacts
Performance Ranges
High-Speed, Low-Noise LVTTL Interface
ACCESS ACCESS ACCESS EDO
High-Reliability Plastic 24/26-Lead
300-Mil-Wide Surface-Mount Small-Outline
J-Lead (SOJ) Package (DJ Suffix) and
24/26-Lead 300-Mil-Wide Surface-Mount
Thin Small-Outline Package (TSOP)
(DGA Suffix)
TIME
TIME
TIME CYCLE
t
t
t
t
HPC
RAC
CAC
AA
(MAX)
50 ns
60 ns
70 ns
(MAX)
13 ns
15 ns
18 ns
(MAX)
25 ns
30 ns
35 ns
(MIN)
20 ns
25 ns
30 ns
’4EPxxxxN-50
’4EPxxxxN-60
’4EPxxxxN-70
description
The TM4EP64xxN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of
sixteen TMS42x409A, 4194304 × 4-bit EDO dynamic random-access memories (DRAMs), each in a 300-mil,
26-pin plastic thin small-outline package (TSOP) (DGA suffix) mounted on a substrate with decoupling
capacitors. See the TMS42x409A data sheet (literature number SMKS893). The TM4EP64xJN is available with
an SOJ package (DJ suffix).
The TM4EP72xxN is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS42x409A,
4194304 × 4-bit EDO DRAMs, each in a 300-mil, 26-pin plastic TSOP (DGA suffix) mounted on a substrate with
decoupling capacitors. See the TMS42x409A data sheet (literature number SMKS893). The TM4EP72xJN is
available with an SOJ packaage (DJ suffix).
operation
The TM4EP64xxN operates as 16 TMS42x409As that are connected as shown in the TM4EP64xxN functional
block diagram. The TM4EP72xxN operates as 18 TMS42x409As that are connected as shown in the
TM4EP72xxN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
TM4EP64xxN
(SIDE VIEW)
TM4EP72xxN
(SIDE VIEW)
PIN NOMENCLATURE – TM4EPxxBxN
A[0:10]
A[0:10]
DQ[0:63]
CB[0:7]
Row-Address Inputs
Column-Address Inputs
Data In/Data Out
Check Bit In/Check Bit Out
Column-Address Strobe
Row-Address Strobe
Write Enable
1
CAS[0:7]
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
SA[0:2]
Output Enable
10
11
Serial Presence Detect (SPD)
Device Add Input
SPD Address/Data
SPD Clock
SDA
SCL
NC
No Connect
V
DD
V
SS
3.3-V Supply
Ground
PIN NOMENCLATURE – TM4EPxxCxN
A[0:11]
A[0:9]
DQ[0:63]
CB[0:7]
Row-Address Inputs
Column-Address Inputs
Data In/Data Out
Check Bit In/Check Bit Out
Column-Address Strobe
Row-Address Strobe
Write Enable
CAS[0:7]
40
41
RAS0 and RAS2
WE0 and WE2
OE0 and OE2
SA[0:2]
Output Enable
Serial Presence Detect (SPD)
Device Add Input
SPD Address/Data
SPD Clock
SDA
SCL
NC
No Connect
V
DD
V
SS
3.3-V Supply
Ground
84
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
Pin Assignments
PIN
PIN
NAME
PIN
NAME
PIN
NAME
NO.
1
NAME
NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NO.
85
NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
V
SS
V
SS
V
SS
2
DQ0
DQ1
DQ2
DQ3
OE2
RAS2
CAS2
CAS3
WE2
86
DQ32
DQ33
DQ34
DQ35
NC
NC
3
87
4
88
CAS6
CAS7
NC
5
89
6
V
DD
90
V
DD
7
DQ4
DQ5
DQ6
DQ7
DQ8
V
DD
91
DQ36
DQ37
DQ38
DQ39
DQ40
V
DD
8
NC
NC
92
NC
NC
9
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB2
CB3
94
CB6
CB7
95
V
SS
V
SS
96
V
SS
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
DQ16
DQ17
DQ18
DQ19
97
DQ41
DQ42
DQ43
DQ44
DQ45
DQ48
DQ49
DQ50
DQ51
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
V
DD
V
DD
V
DD
DQ20
NC
V
DD
DQ52
NC
DQ14
DQ15
CB0
DQ46
DQ47
CB4
NC
NC
NC
NC
CB1
V
SS
CB5
V
SS
V
SS
DQ21
DQ22
DQ23
V
SS
DQ53
DQ54
DQ55
NC
NC
NC
NC
V
DD
V
SS
V
DD
NC
V
SS
WE0
DQ24
DQ25
DQ26
DQ27
DQ56
DQ57
DQ58
DQ59
CAS0
CAS1
RAS0
OE0
CAS4
CAS5
NC
V
DD
NC
V
DD
V
SS
DQ28
DQ29
DQ30
DQ31
V
SS
DQ60
DQ61
DQ62
DQ63
A0
A2
A1
A3
A4
A5
A6
V
SS
A7
V
SS
A8
NC
NC
A9
NC
NC
A10
NC
A11
NC
NC
SA0
SA1
SA2
V
DD
NC
SDA
SCL
V
DD
NC
NC
V
DD
NC
V
DD
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
PC substrate: 1,27
0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM4EP64xxN
RAS0
WE0
OE0
RAS2
WE2
OE2
CAS0
CAS
OE
W
RAS
RAS
RAS
RAS
RAS
RAS
RAS
RAS
CAS4
CAS
OE
W
RAS
RAS
U0
UB0
DQ[0:3]
DQ[0:3]
DQ[32:35]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
U1
UB1
DQ[4:7]
DQ[36:39]
CAS1
CAS
OE
W
CAS5
CAS
OE
W
RAS
RAS
U2
UB2
DQ[8:11]
DQ[0:3]
DQ[40:43]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
U3
UB3
DQ[12:15]
DQ[44:47]
CAS2
CAS
OE
W
CAS6
CAS
OE
W
RAS
RAS
U4
UB4
DQ[16:19]
DQ[0:3]
DQ[48:51]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
U5
UB5
DQ[20:23]
DQ[52:55]
CAS3
CAS
OE
W
CAS7
CAS
OE
W
RAS
U6
UB6
DQ[24:27]
DQ[0:3]
DQ[56:59]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
RAS
U7
UB7
DQ[28:31]
DQ[60:63]
TM4EP64xxN:
A[0:11]
†
A[0:11] : U[0:7], UB[0:7]
V
DD
U[0:7], UB[0:7]
SPD EEPROM
Two 0.1 µF
(minimum) per
DRAM
SCL
SDA
A0 A1 A2
V
SS
U[0:7], UB[0:7]
SA0 SA1 SA2
†
A11 is not used in TM4EP64BxN
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
functional block diagram for the TM4EP72xxN
RAS0
WE0
OE0
RAS2
WE2
OE2
CAS0
CAS
OE
W
RAS
RAS
RAS
RAS
RAS
RAS
RAS
RAS
RAS
CAS4
CAS
OE
W
RAS
RAS
U0
UB0
DQ[0:3]
DQ[0:3]
DQ[32:35]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
W
U1
UB1
DQ[4:7]
DQ[36:39]
CAS1
CAS
OE
W
CAS5
CAS
OE
RAS
U2
UB2
DQ[8:11]
DQ[0:3]
DQ[40:43]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
W
RAS
U3
UB3
DQ[12:15]
DQ[44:47]
CAS1
CAS
OE
W
CAS5
CAS
OE
RAS
U8
UB8
CB[0:3]
DQ[0:3]
CB[4:7]
DQ[0:3]
CAS2
CAS
OE
W
CAS6
CAS
OE
W
W
RAS
U4
UB4
DQ[16:19]
DQ[0:3]
DQ[48:51]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
RAS
U5
UB5
DQ[20:23]
DQ[52:55]
CAS3
CAS
OE
W
CAS7
CAS
OE
W
RAS
U6
UB6
DQ[24:27]
DQ[0:3]
DQ[56:59]
DQ[0:3]
CAS OE
DQ[0:3]
W
CAS OE
DQ[0:3]
W
RAS
UB7
U7
DQ[28:31]
DQ[60:63]
TM4EP72xxN:
A[0:11]
†
A[0:11] : U[0:8], UB[0:8]
V
DD
U[0:8], UB[0:8]
SPD EEPROM
Two 0.1 µF
(minimum) per
DRAM
SCL
SDA
A0 A1 A2
V
SS
U[0:8], UB[0:8]
SA0 SA1 SA2
†
A11 is not used in TM4EP72BxN
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM4EP64xxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
TM4EP72xxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
Supply voltage
3
3.3
0
3.6
V
V
V
V
DD
SS
IH
Supply voltage
High-level input voltage
2
2
V
DD
+ 0.3
5.5
-SPD High-level input voltage for the SPD device
Low-level input voltage
IL
IL
V
–0.3
0
0.8
70
V
T
A
Ambient temperature
°C
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted)
TM4EP64BxN
’4EP64BxN-50
’4EP64BxN-60
’4EP64BxN-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
I
± 20
± 20
± 20
± 20
± 20
± 20
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V
,
DD
DD
CASx high
O
Average
read- or
write-cycle
current
‡§
I
V = 3.6 V,
DD
Minimum cycle
1920
1600
1440
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
32
16
32
16
32
16
mA
mA
Average
standby
current
I
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RASx and CASx high
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
I
I
1920
1760
1600
1440
1440
1280
mA
mA
CC3
(RASx-only
refresh
or CBR)
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
DD
RASx low,
HPC
CASx cycling
CC4
EDO current
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP72BxN
’4EP72BxN-50
’4EP72BxN-60
’4EP72BxN-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
I
± 20
± 20
± 20
± 20
± 20
± 20
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V
,
DD
DD
CASx high
O
Average
read- or
write-cycle
current
‡§
I
V = 3.6 V,
DD
Minimum cycle
2160
1800
1620
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
36
18
36
18
36
18
mA
mA
Average
standby
current
I
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RASx and CASx high
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
I
I
2160
1980
1800
1620
1620
1440
mA
mA
CC3
(RAS-only
refresh
or CBR)
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
DD
RASx low,
HPC
CASx cycling
CC4
EDO current
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP64CxN
’4EP64CxN-50
’4EP64CxN-60
’4EP64CxN-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
I
± 20
± 20
± 20
± 20
± 20
± 20
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V
,
DD
DD
CASx high
O
Average
read- or
write-cycle
current
‡§
I
V = 3.6 V,
DD
Minimum cycle
1440
1120
960
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
32
16
32
16
32
16
mA
mA
Average
standby
current
I
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RASx and CASx high
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
I
I
1440
1600
1120
1440
960
mA
mA
CC3
(RASx-only
refresh
or CBR)
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
DD
RASx low,
HPC
CASx cycling
1280
CC4
EDO current
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
(unless otherwise noted) (continued)
TM4EP72CxN
’4EP72CxN-50
’4EP72CxN-60
’4EP72CxN-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
OH
OH
OL
OL
V
V
V
OH
= – 100 µA
= 2 mA
LVCMOS
LVTTL
V
–0.2
V
–0.2
V
–0.2
DD
DD
DD
Low-level
output
voltage
0.4
0.2
0.4
0.2
0.4
0.2
V
OL
= 100 µA
LVCMOS
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
DD
All others = 0 V to V
I
I
I
± 20
± 20
± 20
± 20
± 20
± 20
µA
µA
I
DD
Output
current
(leakage)
V
= 3.6 V,
V
O
= 0 V to V
,
DD
DD
CASx high
O
Average
read- or
write-cycle
current
‡§
I
V = 3.6 V,
DD
Minimum cycle
1620
1260
1080
mA
CC1
V
IH
= 2 V (LVTTL),
After one memory cycle,
RASx and CASx high
36
18
36
18
36
18
mA
mA
Average
standby
current
I
CC2
V
IH
= V
– 0.2 V (LVCMOS),
DD
After one memory cycle,
RASx and CASx high
Average
refresh
current
V
= 3.6 V,
Minimum cycle,
DD
RASx cycling,
‡§
I
I
1620
1800
1260
1620
1080
1440
mA
mA
CC3
(RASx-only
refresh
or CBR)
CASx high (RASx-only refresh),
RASx low after CASx low (CBR)
Average
‡¶
V
= 3.6 V,
t
= MIN,
DD
RASx low,
HPC
CASx cycling
CC4
EDO current
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
Measured with a maximum of one address change while RASx = V
IL
Measured with a maximum of one address change during each EDO cycle, t
HPC
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)
’4EP64xxN
’4EP72xxN
PARAMETER
UNIT
MIN MAX
MIN MAX
C
C
C
C
C
C
C
C
Input capacitance, A0–A11
Input capacitance, OEx
Input capacitance, CASx
Input capacitance, RASx
Input capacitance, WEx
Output capacitance
82
58
16
58
58
8
92
65
23
65
65
8
pF
pF
pF
pF
pF
pF
pF
pF
i(A)
i(OE)
i(CAS)
i(RAS)
i(W)
o
Input/output capacitance, SDA input
9
9
i/o(SDA)
i(SPD)
Input capacitance, SA0, SA1, SA2, SCL inputs
7
7
NOTE 2:
V
DD
= NOM supply voltage ±10%, and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and ambient temperature
(see Note 3)
’4EP64xxN-50 ’4EP64xxN-60 ’4EP64xxN-70
’4EP72xxN-50 ’4EP72xxN-60 ’4EP72xxN-70
PARAMETER
UNIT
MIN
MAX
25
MIN
MAX
30
MIN
MAX
35
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from CASx (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
13
15
18
CAC
CPA
RAC
OEA
CLZ
REZ
CEZ
OEZ
WEZ
Access time from CASx precharge (see Note 4)
Access time from RASx (see Note 4)
28
35
40
50
60
70
Access time from OEx (see Note 4)
13
15
18
Delay time, CASx to output in low impedance
Output buffer turn-off delay from RASx (see Note 5)
Output buffer turn-off delay from CASx (see Note 5)
Output buffer turn-off delay from OEx (see Note 5)
Output buffer turn-off delay from WEx (see Note 5)
0
3
3
3
3
0
3
3
3
3
0
3
3
3
3
13
13
13
13
15
15
15
15
18
18
18
18
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
4. Access times are measured with output reference levels of V
=2 V and V =0.8 V.
OL
OH
5. Themaximumvaluesoft
,t
,t
,andt
arespecifiedwhentheoutputsarenolongerdriven.Data-inshouldnotbedriven
REZ CEZ OEZ
WEZ
until one of the applicable maximum values is satisfied.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
EDO timing requirements (see Note 3)
’4EP64xxN-50
’4EP72xxN-50
’4EP64xxN-60
’4EP72xxN-60
’4EP64xxN-70
’4EP72xxN-70
UNIT
MIN
20
57
40
7
MAX
MIN
25
68
48
10
5
MAX
MIN
30
78
58
10
5
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, EDO page mode, read-write
Cycle time, EDO read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
CHO
DOH
CAS
WPE
OCH
CP
Delay time, RASx active to CASx precharge
Hold time, OEx from CASx
Hold time, output from CASx
5
Pulse duration, CASx active
8
10000
10 10000
12 10000
Pulse duration, WEx active (output disable only)
Setup time, OEx before CASx
Pulse duration, CASx precharge
Precharge time, OEx
7
7
10
10
5
7
10
10
5
8
8
5
OEP
NOTE 3: With ac parameters, it is assumed that t = 2 ns.
T
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
ac timing requirements (see Note 3)
’4EP64xxN-50
’4EP72xxN-50
’4EP64xxN-60
’4EP72xxN-60
’4EP64xxN-70
’4EP72xxN-70
UNIT
MIN
84
MAX
MIN
104
135
MAX
MIN
124
160
MAX
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, read-write
111
RWC
RASP
RAS
RP
Pulse duration, RASx active, fast-page mode (see Note 6)
Pulse duration, RASx active, non-page mode (see Note 6)
Pulse duration, RASx precharge
50 100 000
60 100 000
70 100 000
50
30
8
10 000
60
40
10
0
10 000
70
50
10
0
10 000
Pulse duration, write command
WP
Setup time, column address
0
ASC
ASR
DS
Setup time, row address
0
0
0
Setup time, data in (see Note 7)
0
0
0
Setup time, read command
0
0
0
RCS
CWL
RWL
Setup time, write command before CASx precharge
Setup time, write command before RASx precharge
8
10
10
12
12
8
Setup time, write command before CASx active
(early-write only)
t
0
0
0
ns
WCS
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, WEx high before RASx low (CBR refresh only)
Setup time, WEx low before RASx low (test mode only)
Setup time, CASx referenced to RASx (CBR refresh only)
Hold time, column address
10
10
5
10
10
5
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRP
WTS
CSR
CAH
DH
8
10
10
10
0
12
12
10
0
Hold time, data in (see Note 7)
8
Hold time, row address
8
RAH
RCH
RRH
WCH
ROH
WRH
WTH
CHR
OEH
CHS
RHCP
AWD
CPW
CRP
CWD
OED
RAD
RAL
Hold time, read command referenced to CASx (see Note 8)
Hold time, read command referenced to RASx (see Note 8)
Hold time, write command during CASx active (early-write only)
Hold time, RASx referenced to OEx
0
0
0
0
8
10
10
10
10
10
15
– 50
35
49
54
5
12
10
10
10
10
18
– 50
40
57
62
5
10
10
10
10
13
– 50
28
42
45
5
Hold time, WEx high after RASx low (CBR refresh)
Hold time, WEx low after RASx low (test mode only)
Hold time, CASx referenced to RASx (CBR refresh only)
Hold time, OEx command
Hold time, CASx referenced to RASx (self-refresh only)
Hold time, RASx active from CASx precharge
Delay time, column address to write command (read-write only)
Delay time, WEx low after CASx precharge (read-write only)
Delay time, CASx precharge to RASx
Delay time, CASx to write command (read-write only)
Delay time, OEx to data in
30
13
10
25
18
34
15
12
30
20
40
18
12
35
25
Delay time, RASx to column address (see Note 9)
Delay time, column address to RASx precharge
Delay time, column address to CASx precharge
25
30
35
CAL
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
6. In a read-write cycle, t
and t
must be observed.
RWD
7. Referenced to the later of CASx or WEx in write operations
8. Either t or t must be satisfied for a read cycle.
RWL
RCH
RRH
9. The maximum value is specified only to ensure access time.
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
ac timing requirements (see Note 3) (continued)
’4EP64xxN-50 ’4EP64xxN-60 ’4EP64xxN-70
’4EP72xxN-50 ’4EP72xxN-60 ’4EP72xxN-70
UNIT
MIN
12
0
MAX
MIN
14
0
MAX
MIN
14
0
MAX
t
t
t
t
t
t
t
t
t
Delay time, RASx to CASx (see Note 9)
Delay time, RASx precharge to CASx
Delay time, CASx active to RASx precharge
Delay time, RASx to write command (read-write only)
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RASx (test mode)
Refresh time interval
37
45
52
ns
ns
ns
ns
ns
ns
ns
ms
ns
RCD
RPC
RSH
RWD
TAA
8
10
79
35
40
65
12
92
40
45
75
67
30
35
55
TCPA
TRAC
REF
T
32
30
32
30
32
30
Transition time
2
2
2
NOTES: 3. With ac parameters, it is assumed that t = 2 ns.
T
9. The maximum value is specified only to ensure access time.
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte Serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing
parameters (see Table 1 through Table 4). Only the first 128 bytes are programmed by Texas Instruments, while
theremaining128bytesareavailableforcustomeruse. ProgrammingisdonethroughanIICbususingtheclock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
SPD contents for the TM4EPxxxxN devices are listed in the following tables:
Table 1–TM4EP64BxN
Table 3–TM4EP72BxN
Table 2–TM4EP64CxN
Table 4–TM4EP72CxN
Table 1. Serial-Presence-Detect Data for the TM4EP64BxN
’4EP64BxN-50
’4EP64BxN-60
’4EP64BxN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes
written into serial memory
during module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
10
08h
02h
0Ah
0Ah
01h
256 bytes
EDO
10
08h
02h
0Ah
0Ah
01h
256 bytes
EDO
10
08h
02h
0Ah
0Ah
01h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
10
10
10
Number of module banks on
this assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
RAC
RAC
RAC
DIMM configuration type
(non-parity, parity, ECC)
11
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
13
Refresh rate/type
15.6 µs
00h
04h
15.6 µs
00h
04h
15.6 µs
00h
04h
DRAM width, primary DRAM
x4
x4
x4
Error-checking SDRAM data
width
14
N/A
00h
N/A
00h
N/A
00h
62
63
SPD revision
Rev. 1
36
01h
24h
Rev. 1
48
01h
30h
Rev. 1
61
01h
3Dh
Checksum for bytes 0–62
Manufacturer’s JEDEC ID
code per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
serial presence detect (continued)
Table 1. Serial-Presence-Detect Data for the TM4EP64BxN (Continued)
’4EP64BxN-50
’4EP64BxN-60
’4EP64BxN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
TBD
TBD
TBD
TBD
TBD
DATA
ITEM
TBD
TBD
TBD
TBD
TBD
DATA
ITEM
TBD
TBD
TBD
TBD
TBD
DATA
†
93–94
95–98
Manufacturing date
†
Assembly serial number
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
‡
128–166 System-integrator-specific data
167–255 Open
†
‡
TBD indicates that values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM4EP64CxN
’4EP64CxN-50
’4EP64CxN-60
’4EP64CxN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes
written into serial memory
during module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256
EDO
11
08h
02h
0Bh
09h
01h
256
EDO
11
08h
02h
0Bh
09h
01h
256
EDO
11
08h
02h
0Bh
09h
01h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
9
9
9
Number of module banks on
this assembly
1 bank
64 bits
1 bank
64 bits
1 bank
64 bits
6
7
Data width of this assembly
Data width continuation
40h
00h
40h
00h
40h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
RAC
RAC
RAC
DIMM configuration type
(non-parity, parity, ECC)
11
Non-parity
00h
Non-parity
00h
Non-parity
00h
12
13
Refresh rate/type
15.6 µs
00h
04h
15.6 µs
00h
04h
15.6 µs
00h
04h
DRAM width, primary DRAM
x4
x4
x4
Error-checking SDRAM data
width
14
N/A
00h
N/A
00h
N/A
00h
62
63
SPD revision
Rev. 1
36
01h
24h
Rev. 1
48
01h
30h
Rev. 1
61
01h
3Dh
Checksum for bytes 0–62
Manufacturer’s JEDEC ID
code per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
System-integrator-specific
128–166
TBD
TBD
TBD
‡
data
167–255 Open
†
‡
TBD indicates that values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
serial presence detection (continued)
Table 3. Serial-Presence-Detect Data for the TM4EP72BxN
’4EP72BxN-50
’4EP72BxN-60
’4EP72BxN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes
written into serial memory
during module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
EDO
10
08h
02h
0Ah
0Ah
01h
256 bytes
EDO
10
08h
02h
0Ah
0Ah
01h
256 bytes
EDO
10
08h
02h
0Ah
0Ah
01h
Fundamental memory type
(FPM, EDO, SDRAM)
Number of row addresses on
this assembly
Number of column addresses
on this assembly
10
10
10
Number of module banks on
this assembly
1 bank
72 bits
1 bank
72 bits
1 bank
72 bits
6
7
Data width of this assembly
Data width continuation
48h
00h
48h
00h
48h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
RAC
RAC
RAC
DIMM configuration type
(non-parity, parity, ECC)
11
ECC
02h
ECC
02h
ECC
02h
12
13
Refresh rate/type
15.6 µs
00h
04h
15.6 µs
00h
04h
15.6 µs
00h
04h
DRAM width, primary DRAM
x4
x4
x4
Error-checking SDRAM data
width
14
x4
04h
x4
04h
x4
04h
62
63
SPD revision
Rev. 1
50
01h
32h
Rev. 1
62
01h
3Eh
Rev. 1
75
01h
4Bh
Checksum for bytes 0–62
Manufacturer’s JEDEC ID
code per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
System-integrator-specific
128–166
TBD
TBD
TBD
‡
data
167–255 Open
†
‡
TBD indicates that values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM4EP72CxN
’4EP72CxN-50
’4EP72CxN-60
’4EP72CxN-70
BYTE
NO.
FUNCTION DESCRIBED
ITEM
DATA
ITEM
DATA
ITEM
DATA
Defines number of bytes
written into serial memory
during module manufacturing
0
128 bytes
80h
128 bytes
80h
128 bytes
80h
Total number of bytes of SPD
memory device
1
2
3
4
5
256 bytes
08h
02h
0Bh
09h
01h
256 bytes
08h
02h
0Bh
09h
01h
256 bytes
EDO
11
08h
02h
0Bh
09h
01h
Fundamental memory type
(FPM, EDO, SDRAM)
EDO
11
EDO
11
Number of row addresses on
this assembly
Number of column addresses
on this assembly
9
9
10
Number of module banks on
this assembly
1
1
2
6
7
Data width of this assembly
Data width continuation
72 bits
48h
00h
72 bits
48h
00h
72 bits
48h
00h
Voltage interface standard of
this assembly
8
LVTTL
01h
LVTTL
01h
LVTTL
01h
9
RASx access time of module
CASx access time of module
t
t
= 50 ns
= 13 ns
32h
0Dh
t
t
= 60 ns
= 15 ns
3Ch
0Fh
t
t
= 70 ns
= 18 ns
46h
12h
RAC
RAC
RAC
10
RAC
RAC
RAC
DIMM configuration type
(non-parity, parity, ECC)
11
ECC
02h
ECC
02h
ECC
02h
12
13
Refresh rate/type
15.6 µs
00h
04h
15.6 µs
00h
04h
15.6 µs
00h
04h
DRAM width, primary DRAM
x4
x4
x4
Error-checking SDRAM data
width
14
x4
04h
x4
04h
x4
04h
62
63
SPD revision
Rev. 1
50
01h
32h
Rev. 1
62
01h
3Eh
Rev. 1
75
01h
4Bh
Checksum for bytes 0–62
Manufacturer’s JEDEC ID
code per JEP-106E
64–71
97h
9700...00h
97h
9700...00h
97h
9700...00h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
System-integrator-specific
128–166
TBD
TBD
TBD
‡
data
167–255 Open
†
‡
TBD indicates that values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
device symbolization (TM4EP64BPN illustrated)
TM4EP64BPN
Unbuffered Key Position
-SS
3.3-V Voltage Key Position
YY = Year Code
YYMMT
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE A: Location of symbolization may vary.
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4EP64BJN, TM4EP64BPN, TM4EP64CJN, TM4EP64CPN 4194304 BY 64-BIT
TM4EP72BJN, TM4EP72BPN, TM4EP72CJN, TM4EP72CPN 4194304 BY 72-BIT
EXTENDED-DATA-OUT DYNAMIC RAM MODULES
SMMS682A – AUGUST 1997– REVISED MARCH 1998
MECHANICAL DATA
BR (R-PDIM-N168)
DUAL IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
(Note D)
0.054 (1,37)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.046 (1,17)
0.050 (1,27)
0.125 (3,18)
0.039 (1,00) TYP
0.125 (3,18)
0.014 (0,35) MAX
0.118 (3,00) TYP
0.700 (17,78) TYP
1.005 (25,53)
0.118 (3,00) DIA
2 Places
0.995 (25,27)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088180/A 07/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-161
D. Dimension includes de-panelization variations; applies between notch and tab edge.
E. Outline may vary above notches to allow router/panelization irregularities.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current and complete.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1998, Texas Instruments Incorporated
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