TM893NBM36H [TI]
DYNAMIC RANDOM-ACCESS MEMORY MODULES; 动态随机存取内存模块
| 型号： | TM893NBM36H |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DYNAMIC RANDOM-ACCESS MEMORY MODULES |
| 文件： | 总11页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
Organization
Present Detect
TM893NBM36H/I . . . 8388608 × 36
Operating Free-Air Temperature Range
Single 5-V Power Supply (±10% Tolerance)
0°C to 70°C
72-Pin Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
TM893NBM36H/I – Uses Sixteen 16M-Bit
and Eight 4M-Bit DRAMs in Plastic
Small-Outline J-Lead (SOJ) Packages
t
t
t
WRITE
CYCLE
RAC
AA
CAC
(MAX)
(MAX)
(MAX)
(MIN)
’893NBM36H/I-60 60 ns
’893NBM36H/I-70 70 ns
’893NBM36H/I-80 80 ns
30 ns
35 ns
40 ns
15 ns
18 ns
20 ns
110 ns
130 ns
150 ns
Long Refresh Period
32 ms (2048 Cycles)
All Inputs, Outputs, Clocks Fully
TTL-Compatible
†
Gold-Tabbed Versions Available:
TM893NBM36H
3-State Output
Tin-Lead (Solder)-Tabbed Versions
Available:
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
TM893NBM36I
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
The TM893NBM36H/I is a 32M-byte dynamic random-access memory (DRAM) organized as four times
8388608 × 9 (bit 9 is generally used for parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen
TMS417400ADJ 4194304 × 4-bit DRAMs, each in a 24/26-lead plastic SOJ package, and eight TMS44100DJ
4194304 × 1-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate with decoupling
capacitors. The TMS417400ADJ and TMS44100DJ are described in the TMS417400A (literature number
SMKS889) and TMS44100 (literature number SMHS561) data sheets, respectively. The TM893NBM36A
SIMM is available in the double-sided, BM leadless module for use with sockets.
operation
The TM893NBM36H/I operates as sixteen TMS417400ADJ DRAMs and eight TMS44100DJ DRAMs
connected as shown in the functional block diagram and in Table 1. The common I/O feature dictates the use
of early-write cycles to prevent contention on D and Q.
Table 1. Connection Table
RASx
DATA BLOCK
CASx
SIDE 1
RAS0
RAS0
RAS2
RAS2
SIDE 2
RAS1
RAS1
RAS3
RAS3
DQ0–DQ8
CAS0
CAS1
CAS2
CAS3
DQ9–DQ17
DQ18–DQ26
DQ27–DQ35
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
refresh
The refresh period is extended to 32 ms, and, during this period, each of the 2048 rows must be strobed with
RAS to retain data. Address line A10 must be used as the most significant refresh address line (lowest
frequency) to ensure correct refresh for both TMS417400A and TMS44100. Address lines A0–A9 must be
refreshed every 16 ms as required by the TMS44100 DRAM. To conserve power, CAS can remain high during
the refresh sequence.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full V
(RAS-only or CBR-refresh) cycle.
level is achieved. These eight initialization cycles must include at least one refresh
CC
single in-line memory module and components
PC substrate: 1, 27 ± 0,1 mm (0.05 inch) nominal thickness; inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM893NBM36H: Nickel plate and gold plate over copper
Contact area for TM893NBM36I: Nickel plate and tin/lead over copper
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
TM893NBM36H/I
(SIDE VIEW)
BM SINGLE IN-LINE PACKAGE
(TOP VIEW)
fRnrce
V
1
2
3
4
SS
DQ0
DQ18
DQ1
DQ19
DQ2
5
6
DQ20
DQ3
7
8
DQ21
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
V
CC
A8
A9
RAS3
RAS2
DQ26
DQ8
DQ17
DQ35
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
SS
PIN NOMENCLATURE
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
A0–A10
Address Inputs
CAS0–CAS3
DQ0–DQ35
NC
PD1–PD4
RAS0–RAS3
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
V
V
W
CC
SS
Ground
Write Enable
V
CC
PRESENCE DETECT
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
70 ns
60 ns
NC
NC
NC
V
SS
V
SS
V
SS
NC
V
SS
TM893NBM36H/I
V
SS
NC
NC
NC
PD1
PD2
PD3
PD4
NC
V
SS
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram (TM893NBM36H/I, side 1)
11
A0–A10
RAS0
W
RAS2
CAS2
CAS3
CAS0
CAS1
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ18–
DQ21
DQ27–
DQ30
DQ0–
DQ3
DQ9–
DQ12
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ22–
DQ25
DQ31–
DQ34
DQ4–
DQ7
DQ13–
DQ16
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
11
11
11
11
D
Q
DQ26
D
Q
DQ35
DQ8
DQ17
D
Q
D
Q
functional block diagram (TM893NBM36H/I, side 2)
11
A0–A10
RAS1
W
RAS3
CAS2
CAS3
CAS0
CAS1
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ18–
DQ21
DQ27–
DQ30
DQ0–
DQ3
DQ9–
DQ12
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ22–
DQ25
DQ31–
DQ34
DQ4–
DQ7
DQ13–
DQ16
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
11
11
11
11
D
Q
DQ26
D
Q
DQ35
DQ8
DQ17
D
Q
D
Q
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM893NBM36H, TM893NBM36I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX UNIT
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
5.5
6.5
0.8
70
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
’893NBM36H/I-60 ’893NBM36H/I-70 ’893NBM36H/I-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
= 5.5 V,
0.4
± 20
± 20
0.4
± 20
± 20
0.4
± 20
± 20
OL
OL
V
V = 0 V to 6.5 V,
I
Input current
(leakage)
CC
I
I
µA
µA
All other pins = 0 V to V
CC
= 0 V to V
V
= 5.5 V,
CC
CAS high
V
,
CC
Output current
(leakage)
O
I
O
Read- or
write-cycle
current
(one RAS active,
see Note 3)
I
V = 5.5 V,
CC
Minimum cycle
1324
1184
1064
mA
CC1
V
IH
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
48
24
48
24
48
24
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
Average refresh
current
(RAS only or
CBR,
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
I
I
1324
1184
1064
704
mA
mA
CC3
CAS high (RAS-only refresh);
RAS low after CAS low (CBR)
see Note 3)
Average page
current
(one RAS active, RAS low,
V
= 5.5 V,
t
= MIN,
CC
PC
CAS cycling
944
824
CC4
see Note 4)
†
For test conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz (see Note 5)
’893NMB36H/I
PARAMETER
UNIT
MIN
MAX
120
42
C
C
C
C
Input capacitance, A0–A10
pF
pF
pF
pF
pF
pF
i(A)
i(R)
i(C)
i(W)
Input capacitance, RAS inputs
Input capacitance, CAS inputs
Input capacitance, write-enable input
42
168
14
DQ pins
C
Output capacitance
o(DQ)
Parity pins
24
NOTE 5:
V
CC
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’893NBM36H/I-60 ’893NBM36H/I-70 ’893NBM36H/I-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
RAC
CPA
CLZ
OFF
OH
Access time from RAS low
60
70
80
Access time from column precharge
CAS low to output in the low-impedance state
Output disable time after CAS high (see Note 6)
Output disable time, start of CAS high
35
40
45
0
0
3
0
0
3
0
0
3
15
18
20
NOTE 6:
t
is specified when the output is no longer driven.
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’893NBM36H/I-60 ’893NBM36H/I-70 ’893NBM36H/I-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, random read or write (see Note 7)
110
130
150
ns
ns
RC
Cycle time, page-mode read or write
(see Notes 7 and 8)
40
45
50
PC
t
t
t
t
t
t
t
t
t
t
t
t
t
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, CAS low
60
60
15
10
40
10
0
100 000
10 000
10 000
70
70
18
10
50
10
0
100 000
10 000
10 000
80
80
20
10
60
10
0
100 000
10 000
10 000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RASP
RAS
CAS
CP
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, W low
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
ASC
ASR
DS
0
0
0
0
0
0
0
0
0
RCS
CWL
RWL
WCS
15
15
0
18
18
0
20
20
0
Setup time, W high before RAS low
(CBR refresh only)
t
10
10
10
ns
WRP
t
t
t
t
t
t
t
t
Hold time, column address after CAS low
Hold time, RAS high from CAS precharge
Hold time, data after CAS low
10
35
10
10
0
15
40
15
10
0
15
45
15
10
0
ns
ns
ns
ns
ns
ns
ns
ns
CAH
RHCP
DH
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, W high after RAS high (see Note 9)
Hold time, W low after CAS low
RAH
RCH
RRH
WCH
WRH
0
0
0
10
10
15
10
15
10
Hold time, W high after RAS low (CBR refresh only)
NOTES: 7. All cycle times assume t = 5 ns.
T
8. To assure t
min, t
should be ≥ t .
CP
PC
or t
ASC
must be satisfied for a read cycle.
RCH
9. Either t
RRH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’893NBM36H/I-60 ’893NBM36H/I-70 ’893NBM36H/I-80
UNIT
MIN
10
5
MAX
MIN
10
5
MAX
MIN
10
5
MAX
t
t
t
t
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
ns
ns
ns
ns
CHR
CRP
CSH
CSR
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address
(see Note 10)
t
15
30
45
15
35
52
15
40
60
ns
RAD
t
t
t
t
t
t
t
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR refresh only)
Delay time, CAS low to RAS high
Refresh time interval
30
30
20
5
35
35
20
5
40
40
20
5
ns
ns
ns
ns
ns
ms
ns
RAL
CAL
RCD
RPC
RSH
REF
T
15
18
20
32
30
32
30
32
30
Transition time
3
3
3
NOTE 10: The maximum value is specified only to assure access time.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM893NBM36H, TM893NBM36I 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS677 – MARCH 1997
MECHANICAL DATA
BM (R-PSIM-N72)
SINGLE/DOUBLE-SIDED IN-LINE MEMORY MODULE
4.255 (108,08)
4.245 (107,82)
0.054 (1,37)
0.047 (1,19)
0.125 (3,18) TYP
1.305 (33,15)
1.295 (32,89)
0.128 (3,25)
0.120 (3,05)
0.050 (1,27)
0.040 (1,02) TYP
0.010 (0,25) MAX
0.400 (10,16) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
4088175/A 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization (TM497MBM36H illustrated)
TM497MBM36H
–SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE A: Location of symbolization may vary.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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