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TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

TMDS181x 6Gbps TMDS 重定时器

1 特性

3 说明

1

•

HDMI™ 输入端口与输出端口间具有时钟和数据恢

复 (CDR) 电路，支持高达 6Gbps 的数据速率

TMDS181x 是一款数字视频接口 (DVI) 或高清多媒体

接口 (HDMI™) 重定时器。TMDS181x 支持四条

TMDS 通道，音频返回通道 (SPDIF_IN/ARC_OUT) 和

数字显示控制 (DDC) 接口。TMDS181x 支持高达

6Gbps 的信号传输速率，可实现最高分辨率达

4k2k60p 24 位/像素和高达 WUXGA 16 位色深或

1080p，并且具有较高的刷新率。TMDS181x 经配置

可支持 HDMI2.0a 标准。TMDS181x 在低于 1.0Gbps

的数据速率下会自动配置为重驱动器，而在高于该速率

时会自动配置为重定时器。重驱动器模式支持

HDMI1.4b，数据速率高达 3.4Gbps

在重定时器模式下可兼容高达 6Gbps 的 HDMI™

电气参数

支持 4k2k60p 和高达 WUXGA 16 位色深或

1080p，具有更高的刷新率

•

对输入流重新定时以补偿随机抖动

自适应接收器均衡器或可编程固定均衡器

I²C 和引脚设置可编程

5+ 位对内偏移补偿

支持单端模式 ARC

链路调试工具包括位于RX 均衡器之后眼图

TMDS181x 支持双电源轨（V_DD为 1.2V，V_CC为

3.3V），有助于降低功耗。该器件采用多种电源管理

方法来降低整体功耗。TMDS181x 通过 I²C 或引脚设

置支持固定的接收 EQ 增益或自适应接收 EQ 控制，

以补偿不同长度的输入电缆或电路板走线。

48 引脚 7mm × 7mm 0.5mm 间距超薄型四方扁平

无引线 (VQFN) 封装

•

扩展商业温度范围为 0°C 至 85°C (TMDS181)

工业温度范围为 -40°C 至 85°C (TMDS181I)

2 应用

器件信息⁽¹⁾

•

数字电视

器件型号

TMDS181

TMDS181I

封装

封装尺寸（标称值）

数字投影仪

VQFN (48)

7.00mm × 7.00mm

音频/视频设备

Blu-Ray™DVD

监视器

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

台式机/一体化计算机

有源线缆

空白

简化电路原理图

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1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLASE75

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 8

6.5 Power Supply Electrical Characteristics ................... 8

6.6 TMDS Differential Input Electrical Characteristics .... 9

8

9

Detailed Description ............................................ 24

8.1 Overview ................................................................. 24

8.2 Functional Block Diagram ....................................... 25

8.3 Feature Description................................................. 25

8.4 Device Functional Modes........................................ 31

8.5 Register Maps......................................................... 33

Application and Implementation ........................ 40

9.1 Application Information............................................ 40

9.2 Typical Applications ................................................ 40

10 Power Supply Recommendations ..................... 47

11 Layout................................................................... 48

11.1 Layout Guidelines ................................................. 48

11.2 Layout Example .................................................... 49

12 器件和文档支持 ..................................................... 50

12.1 文档支持................................................................ 50

12.2 相关链接................................................................ 50

12.3 接收文档更新通知 ................................................. 50

12.4 社区资源................................................................ 50

12.5 商标....................................................................... 50

12.6 静电放电警告......................................................... 50

12.7 Glossary................................................................ 50

13 机械、封装和可订购信息....................................... 50

6.7 TMDS Differential Output Electrical

Characteristics ......................................................... 10

6.8 DDC, I²C, HPD, and ARC Electrical

Characteristics ......................................................... 11

6.9 Power-Up and Operation Timing Requirements..... 12

6.10 TMDS Switching Characteristics........................... 13

6.11 HPD Switching Characteristics ............................. 14

6.12 DDC and I²C Switching Characteristics................ 14

6.13 Typical Characteristics.......................................... 15

Parameter Measurement Information ................ 15

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (July 2016) to Revision D

Page

•

Added Note 5 to the Power Supply Electrical Characteristic table ....................................................................................... 8

Deleted text "which is needed for certain HDMI CTS test." from the third paragraph in the Overview section .................. 24

Changed section: Input Signal Detect Block ....................................................................................................................... 28

Changed H to X in the first row of the HPD_SNK column in Table 12 ................................................................................ 47

Changed the IN_Dx column in Table 12 ............................................................................................................................. 47

Changes from Revision B (April 2016) to Revision C

Page

•

Recommended Operating Conditions, Changed the CONTROL PINS section .................................................................... 7

DDC, I²C, HPD, and ARC Electrical Characteristics, Changed the DDC AND I²C section ................................................. 11

Changes from Revision A (October 2015) to Revision B

Page

•

Recommended Operating Conditions, Added V_IL"Low-level input voltage at HPD, OE" ...................................................... 7

Recommended Operating Conditions, Moved pin OE From: V_IHMIN value of 2 V To: V_IHMIN value of 2.6 V ................... 7

Power-Up and Operation Timing Requirements, Deleted the VDD_ramp and VCC_ramp MIN values ............................. 12

Changed Figure 1 ................................................................................................................................................................ 12

DDC Functional Description , Changed text "address 22h (see Figure 31) through the I2C interface." To: "address

0Bh through the I2C interface." ............................................................................................................................................ 32

•

Added Note to 11–400-kbps in Table 6................................................................................................................................ 35

Added Note to 11–400-kbps in Table 6................................................................................................................................ 36

2

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

Changes from Original (August 2015) to Revision A

Page

•

已将器件状态从“产品预览”更新为“量产数据” .......................................................................................................................... 1

Absolute Maximum Ratings, Changed max value from 1.56 V to VCC + 0.3V; added input current and Min value............. 6

Absolute Maximum Ratings, Added Max Input Current on Main Link Differential Input pins................................................. 6

Recommended Operating Conditions, Updated the note showing the values shown are only for Microcontroller

driven and not values based upon pull up or pull down resistors. ........................................................................................ 7

•

Power Supply Electrical Characteristics, Increased Max Value of ISD2 from 10 to 15mA ................................................... 8

TMDS Differential Input Electrical Characteristics, Changed Max Receiver impedance value to 115 ................................. 9

DDC, I²C, HPD, and ARC Electrical Characteristics, Inserted values for SCL/SDA_SNK ................................................. 11

TMDS Switching Characteristics, Changed from 6000 to 3400 .......................................................................................... 13

Table 4, Deleted Clear and NA Access Tags ...................................................................................................................... 34

Table 8, Removed reg20h[5:4] ARC_SWING ..................................................................................................................... 39

Figure 35, Removed 1k pullup from switch as not needed ................................................................................................. 43

Pin Strapping Configuration for HDMI2.0a and HDMI1.4b , Added Note for VSADJ resistor value in Compliance Pin

Strapping section ................................................................................................................................................................. 46

•

Pin Strapping Configuration for HDMI2.0a and HDMI1.4b , Changed De-emphasis value from 0 dB to -2 dB for

recommended configuration for compliance testing............................................................................................................. 46

I²C Control for HDMI2.0a and HDMI1.4b, Added Note for VSADJ resistor value in Compliance I2C control section

and included register that can increase or decrease the VOD swing ................................................................................. 46

3

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

5 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

48

47

46

45

44

43

42

41

40

39

38

37

36

TX_TERM_CTL

SWAP/POL

1

2

35

OUT_D2p

OUT_D2n

HPD_SNK

OUT_D1p

OUT_D1n

GND

IN_D2p

IN_D2n

3

4

5

6

34

33

HPD_SRC

IN_D1p

32

31

IN_D1n

GND

30

29

7

8

Db5

IN_D0p

OUT_D0p

OUT_D0n

A1

9

28

27

IN_D0n

I2C_EN/PIN

IN_CLKp

10

11

OUT_CLKp

OUT_CLKn

26

25

IN_CLKn

12

13

14

15

16

17

18

19

20

21

22

23

24

4

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

Pin Functions⁽¹⁾

TYPE⁽²⁾

DESCRIPTION

NAME

VCC

NO.

13, 43

P

3.3 V power supply

VDD

14, 23, 24, 37, 48

1.2 V power supply

7, 19, 41, 30,

Thermal pad

GND

G

Ground

MAIN LINK INPUT PINS

IN_D2p/n

2, 3

5, 6

I

Channel 2 differential input

Channel 1 differential input

Channel 0 differential input

Clock differential input

IN_D1p/n

IN_D0p/n

8, 9

IN_CLKp/n

11, 12

MAIN LINK OUTPUT PINS (FAIL SAFE)

OUT_D2n/p

OUT_D1n/p

OUT_D0n/p

OUT_CLKn/p

34, 35

31, 32

28, 29

25, 26

O

TMDS data 2 differential output

TMDS data 1 differential output

TMDS data 0 differential output

TMDS data clock differential output

HOT PLUG DETECT PINS

HPD_SRC

4

O

I

Hot plug detect output to source side

Hot plug detect input from sink side

HPD_SNK

33

AUDIO RETURN CHANNEL AND DDC PINS

SPDIF_IN

ARC_OUT

45

44

SPDIF signal input

Audio return channel output

I/O

SDA_SRC

SCL_SRC

47

46

Source side TMDS port bidirectional DDC data line

Source side TMDS port bidirectional DDC clock line

SDA_SNK

SCL_SNK

39

38

Sink side TMDS port bidirectional DDC data line

Sink side TMDS port bidirectional DDC clock line

CONTROL PINS

Operation enable/reset pin

OE = L: Power-down mode

OE = H: Normal operation

Internal weak pull up: Resets device when transitions from H to L

OE

42

17

I

Signal detector circuit enable

SIG_EN = L: Signal detect circuit disabled:

SIG_EN = H: Signal detect circuit enabled: When no valid clock device enters

standby mode.

SIG_EN

Internal weak pull down

De-emphasis control when I2C_EN/PIN = Low.

PRE_SEL = L: –2 dB

PRE_SEL = No Connect: 0 dB

I

PRE_SEL

20

21

3 level

PRE_SEL = H: Reserved

When I2C_EN/PIN = High de-emphasis is controlled through I²C

Input receive equalization pin strap when I2C_EN/PIN = Low

EQ_SEL = L: Fixed EQ at 7.5 dB at 3 GHz

I

EQ_SEL = No Connect: Adaptive EQ

EQ_SEL/A0

3 level

EQ_SEL = H: Fixed at 14 dB at 3 GHz

When I2C_EN/PIN = High address bit 1

Note: 3 level for pin strap programming but 2 level when I²C address

I2C_EN/PIN = High; puts device into I²C Control Mode

I2C_EN/PIN = Low; puts device into pin strap mode

I2C_EN/PIN

SCL_CTL

10

15

I

Note: I²C CSR is addressable at all times, but features that can be controlled by pin

strapping can only be changed by I²C when this pin is pulled high

I²C clock signal

Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be

changed by I²C

(1) (H) Logic high (pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (pin strapped to GND through 65 kΩ resistor); (for mid-level

= No connect)

(2) G = Ground, I = Input, O = Output, P = Power

5

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Pin Functions⁽¹⁾(continued)

TYPE⁽²⁾

DESCRIPTION

NAME

SDA_CTL

VSadj

NO.

16

I²C data signal

I/0

Note: When I2C_EN = Low Pin strapping takes priority and those functions cannot be

changed by I²C

22

I

TMDS-compliant voltage swing control nominal resistor to GND

High address bit 2 for I²C programming

Weak internal pull down

A1

27

Note: When in Pin Strapping Mode leave pin as No connect

Transmit termination control

TX_TERM_CTL = H, no transmit termination

TX_TERM_CTL = L, transmit termination impedance in approximately 75 to 150 Ω

TX_TERM_CTL = No Connect, automatically selects the termination impedance

Data rate (DR) > 3.4 Gbps – 75 to 150 Ω differential near end termination

2 Gbps > DR < 3.4 Gbps – 150 to 300 Ω differential near end termination

DR < 2 Gbps – no termination

I

TX_TERM_CTL

36

3 level

Note: If left floating will be in automatic select mode.

Input lane SWAP and polarity control pin

I

SWAP/POL = H: receive lanes polarity swap (retimer mode only)

SWAP/POL = L: receive lanes swap (redriver and retimer mode)

SWAP/POL = No Connect: normal operation

SWAP/POL

NC

1

3 level

18, 40

NA

No connect

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

MIN

–0.3

MAX

UNIT

V_CC

Supply voltage⁽³⁾

V_DD

4

V

–0.3

1.4

VCC + 0.3V

4

Main link input differential voltage (IN_Dx, IN_CLKx) I_IN= 15mA

TMDS outputs ( OUT_Dx)

V_CC- 0.75V

–0.3

Voltage

V

HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1, PRE_SEL, EQ_SEL/A0,

I2C_EN/PIN, SIG_EN, TX_TERM_CTL,

–0.3

4

HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC, SCL_SRC

Main link input current (IN_Dx, IN_CLKx)

Continuous power dissipation

6

Input Current I_IN

T_stg

15

mA

°C

See Thermal Information

–65 150

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

1.1

NOM

3.3

MAX UNIT

V_CC

Supply voltage nominal value 3.3 V

Supply voltage nominal value 1.2 V

Case temperature

3.465

1.27

92.7

85

V

V_DD

1.2

V

T_CASE

°C

TMDS181

TMDS181I

0

Operating free-air

temperature

T_A

–40

85

MAIN LINK DIFFERENTIAL PINS

V_{ID_PP}Peak-to-peak input differential voltage

75

1560 mVpp

V_CC

0.1

+

V_IC

Input common mode voltage

Data rate

V_CC– 0.4

V

d_R

0.25

4.5

6

Gbps

R_VSADJTMDS compliant swing voltage bias resistor nominal

7.06

kΩ

CONTROL PINS

V_I-DC

DC input voltage

Control pins

–0.3

3.6

0.3

0.8

1.4

V

Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL

pins only

(1)

V_IL

Low-level input voltage at OE

Mid-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL

pins only

(1)

V_IM

1

1.2

V

High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL, SWAP/POL,

OE⁽²⁾pins only

(1)

V_IH

2.6

V_OL

V_OH

I_IH

Low-level output voltage

High-level output voltage

High-level input current

0.4

V

2.4

–30

–25

–50

30

25

µA

mA

µA

kΩ

I_IL

Low-level input current

I_OS

Short-circuit output current

High impedance output current

Pullup resistance on OE pin

50

I_OZ

10

R_OEPU

150

250

(1) These values are based upon a microcontroller driving the control pins. The pullup/pulldown/floating resistor configuration will set the

internal bias to the proper voltage level which will not match the values shown here.

(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup

resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

7

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

6.4 Thermal Information

TMDS181x

RGZ (VQFN)

48 PINS

31.1

THERMAL METRIC⁽¹⁾⁽²⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

18.2

8.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

8.1

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Test conditions for Ψ_JBand Ψ_JTare clarified in the Semiconductor and IC Package Thermal Metrics.

6.5 Power Supply Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX⁽²⁾

UNIT

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V

IN_Dx: V_{ID_PP}= 1200 mV, 6 Gbps TMDS pattern, V_I= 3.3 V,

I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= NC,

SDA_CTL/CLK_CTL = 0 V

Device power dissipation

(retimer operation)

(3)(4)

P_D1

800

900

mW

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V

IN_Dx: V_{ID_PP}= 1200 mV, 2.97 Gbps TMDS pattern, V_I= 3.3 V,

I2C_EN/PIN = L, PRE_SEL= NC, EQ_SEL= H,

SDA_CTL/CLK_CTL = 0 V

Device power dissipation

(redriver operation)

P_D2

500

600

mW

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V, HPD = H, No

valid input signal

(3)(4)(5)

P_SD1

P_SD2

Device power in standby

50

10

100

30

mW

Device power in power down

OE = L, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V

IN_Dx: V_{ID_PP}= 1200 mV, 6 Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC,

SDA_CTL/CLK_CTL = 0 V

VCC supply current (TMDS

6Gpbs retimer mode)

(3)(4)

I_CC1

I_DD1

I_CC2

I_DD2

131

332

92

150

350

mA

OE = H, V_CC= 3.3 V/3.465 V, VDD = 1.2 V/1.27 V

IN_Dx: V_{ID_PP}= 1200 mV, 6 Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = NC,

SDA_CTL/CLK_CTL = 0 V

VDD supply current (TMDS

6Gpbs retimer mode)

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V

IN_Dx: V_{ID_PP}= 1200 mV, 2.97 Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V

VCC supply current (TMDS

6Gpbs redriver mode)

OE = H, V_CC= 3.3 V/3.465 V, V_DD= 1.2 V/1.27 V

IN_Dx: V_{ID_PP}= 1200 mV, 3.4 Gbps TMDS pattern

I2C_EN/PIN = L, PRE_SEL = NC, EQ_CTL = H,

SDA_CTL/CLK_CTL = 0 V

VDD supply current (TMDS

6Gpbs redriver mode)

187

OE = H, V_CC= 3.3 V/3.465 V, VDD = 1.2

V/1.27 V, HPD = H: No valid signal on

IN_CLK

3.3 V rail⁽³⁾

6

15

50

(5)

I_SD1

Standby current

mA

1.2 V rail

40

3.3 V rail⁽³⁾

1.2 V rail

2

5

OE = L, V_CC= 3.3 V/3.465 V, V_DD= 1.2

V/1.27 V

I_SD2

Power-down current

3.5

15

(1) The typical rating is simulated at 3.3 V V_CCand 1.2 V V_DDand at 27°C temperature unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C temperature unless otherwise noted

(3) I_CCis a direct result of the source design as the TMDS181x integrated receive termination resistor accounts for 85 to 110 mA.

(4) I_DDis impacted by ARC usage. Connecting a 500 kΩ resistor to GND at SPDIF reduces the value by more than 20 mA

(5) The measurements were made with no active source connected.

8

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6.6 TMDS Differential Input Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX⁽²⁾

UNIT

D_{R_RX_DATA_R}TMDS data lanes data rate

0.25

6

Gbps

(Retimer Mode)

T

D_{R_RX_DATA_R}TMDS data lanes data rate

0.25

3.4

Gbps

MHz

(Redriver Mode)

D

D_{R_RX_CLK}

t_{RX_DUTY}

t_{CLK_JIT}

TMDS clock lanes clock rate

Input clock duty circle

25

340

60%

0.3

40%

50%

Input clock jitter tolerance

Input data jitter tolerance

Tbit

ps

t_{DATA_JIT}

Test the TTP2, see Figure 12

150

Test at TTP2 when DR = 1.6 Gbps, see

Figure 12

t_{RX_INTRA}

t_{RX_INTER}

E_QH(D)

Input intrapair skew tolerance

Input interpair skew tolerance

112

ps

ns

dB

1.8

15

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = H; fixed EQ gain, test at 6

Gbps

15

Fixed EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = L; fixed EQ gain, test at 6

Gbps

E_QL(D)

7.5

dB

Adaptive EQ gain for data lane

IN_D(0,1,2)n/p

EQ_SEL/A0 = NC; adaptive EQ

(Retimer Mode Only)

E_QZ(D)

E_Q(c)

2

dB

Ω

EQ gain for clock lane IN_CLKn/p EQ_SEL/A0 = H,L,NC

3

100

3.3

Input differential termination

impedance

R_INT

85

115

V_ITERM

Input termination voltage

OE = H

3.465

V

(1) The typical rating is simulated at 3.3 V V_CCand 1.2 V V_DDand at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C unless otherwise noted

9

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6.7 TMDS Differential Output Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

V_CC– 10

MAX⁽²⁾UNIT

Single-ended high level output

voltage

Data rate ≤1.65 Gbps

PRE_SEL = NC; TX_TERM_CTL = H; OE

= H; DR = 750 Mbps; VSadj = 7.06 kΩ;

V_CC+ 10

Single-ended high level output

voltage

Data rate >1.65 Gbps and

<3.4 Gbps

PRE_SEL = NC; TX_TERM_CTL = NC;

OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;

V_CC-200

V_CC+ 10

V

V_OH

Single-ended high level output

voltage

PRE_SEL = NC; TX_TERM_CTL = L; OE

= H; DR = 6 Gbps; VSadj = 7.06 kΩ;

V_CC– 400

V_CC– 600

V_CC– 700

V_CC+ 10

Data rate >3.4 Gbps and < 6

Gbps⁽²⁾

Single-ended low level output

voltage

Data rate ≤1.65 Gbps

PRE_SEL = NC; TX_TERM_CTL = H; OE

= H; DR = 750 Mbps; VSadj = 7.06 kΩ;

V_CC– 400

Single-ended low level output

voltage

Data rate >1.65 Gbps and

<3.4 Gbps

PRE_SEL = NC; TX_TERM_CTL = NC;

OE = H; DR = 2.97 Gbps; VSadj = 7.06 kΩ;

V_CC– 400

V

V_OL

Single-ended low level output

voltage

PRE_SEL = NC; TX_TERM_CTL = L; OE

= H; DR = 6 Gbps; VSadj = 7.06 kΩ;

V_CC– 1000

V_CC– 400

Data rate >3.4 Gbps and < 6

Gbps⁽²⁾

PRE_SEL = NC; TX_TERM_CTL =

H/NC/L; OE = H; DR = 270 Mbps/2.97/6

Gbps VSadj = 7.06 kΩ;

Single-ended output voltage

swing on data lane

V_{SWING_DA}

400

200

500

300

20

600

400

mV

PRE_SEL = NC; TX_TERM_CTL = H; OE

= H; Data rate ≤ 3.4 Gbps; VSadj = 7.06

kΩ;

Single-ended output voltage

swing on clock lane

V_{SWING_CLK}

PRE_SEL = NC; TX_TERM_CTL = NC;

OE = H; Data rate > 3.4 Gbps; VSadj =

7.06 kΩ;

Change in single-end output

voltage swing per 100 Ω

ΔVSadj

ΔV_SWING

mV

Change in steady state output

common mode voltage

between logic levels

ΔV_OCM(SS)

–5

5

Output differential voltage

before pre-emphasis

V_SADJ= 7.06 kΩ; PRE_SEL = NC see

Figure 10

V_OD(PP)

V_OD(SS)

800

600

1200

1075

mV

Steady state output differential V_SADJ= 7.06 kΩ; PRE_SEL = L, see

voltage

Figure 11

3.4 Gbps < R_bit≤ 3.712 Gps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; VSadj = 7.06 kΩ;

335

Total TMDS data lanes output

differential voltage for

HDMI2.0. Retimer Mode Only

See Figure 14

–19.66 ×

(R_bit²) +

(106.74 × R_bit)

3.712 Gbps < R_bit< 5.94 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; VSadj = 7.06 kΩ;

V_{OD_range}

mV

+ 209.58

5.94 Gbps ≤ R_bit≤ 6.0 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; VSadj = 7.06 kΩ;

150

I_OS

Short-circuit current limit

Main link output shorted to GND

50

45

mA

Failsafe condition leakage

current

V_CC= 0 V; V_DD= 0 V; TMDS Outputs

pulled to 3.3 V through 50 Ω resistor;

I_LEAK

μA

Source termination resistance

for HDMI2.0

R_TERM

75

150

Ω

(1) The typical rating is simulated at 3.3 V V_CCand 1.2 V V_DDand at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C unless otherwise noted

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6.8 DDC, I²C, HPD, and ARC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX⁽²⁾UNIT

DDC AND I²C

SCL/SDA_SNK, SCL/SDA_SRC DC

input voltage

–0.3

5.5

3.6

V

V_I-DC

SCL/SDA_CTL, DC input voltage

SCL/SDA_SNK, SCL/SDA_SRC Low

level input voltage

0.3 x V_CC

V_IL

SCL/SDA_CTL Low level input

voltage

0.3 x V_CC

V

SCL/SDA_SNK, SCL/SDA_SRC high

level input voltage

3

V_IH

SCL/SDA_CTL high level input

voltage

0.7 x V_CC

I₀= 3 mA and V_CC> 2 V

I₀= 3 mA and V_CC< 2 V

0.4

SCL/SDA_CTL, SCL/SDA_SRC low

level output voltage

V_OL

V

0.2 x V_CC

SCL clock frequency fast I2C mode

for local I2C control

f_SCL

400

kHz

pF

Total capacitive load for each bus line

(DDC and local I2C pins)

C_bus

HPD

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

HPD_SNK

2.1

V

V_IL

HPD_SNK

0.8

3.6

0.1

V_OH

V_OL

I_OH= –500 µA; HPD_SRC,

I_OL= 500 µA; HPD_SRC,

2.4

0

V_CC= 0 V; V_DD= 0 V; HPD_SNK =

5 V;

I_LEAK

Failsafe condition leakage current

40

μA

Device powered; V_IH= 5 V;

I_{H_HPD}includes R_pdHPDresistor

current

40

I_{H_HPD}

High-level input current

µA

Device powered; V_IL= 0.8 V;

I_{L_HPD}includes R_pdHPDresistor

current

30

R_pdHPD

HPD input termination to GND

V_CC= 0 V

150

0

190

220

kΩ

SPDIF AND ARC

Operating DC voltage for single mode

ARC output

V_EL

Test at ARC_OUT, see Figure 22

5

V

V_{IN_DC}

Operating DC voltage for SPDIF input

Signal amplitude of SPDIF input

0.05

0.6

V

V_{SP_SW}

0.2

0.4

0.5

Test at ARC_OUT, 55 Ω external

termination resistor, see Figure 22

V_ElSWING

Signal amplitude on the ARC output

Signal frequency on ARC

0.6

V

5.645

±0.1%

CLK_ARC

Test at ARC_OUT, see Figure 22

3.687

13.517

55%

MHz

Duty cycle

Data rate

t_EDGE

Output clock duty cycle

SPDIF input DR

45%

50%

7.373

11.29

27.034 Mbps

Rise/fall time for ARC output

From 10% to 90% voltage level

0.4

UI

Input termination resistance for

SPDIF

R_{_IN_SPDIF}

R_est

75

55

Ω

Single mode output termination

resistance

0.1 MHz to 128× the maximum

frame rate

36

75

Ω

(1) The typical rating is simulated at 3.3 V V_CCand 1.2 V V_DDand at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C unless otherwise noted

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6.9 Power-Up and Operation Timing Requirements

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

0

NOM

MAX

UNIT

µs

t_d1

V_DDstable before V_CC

200

t_d2

V_DDand V_CCstable before OE assertion

CDR active operation after retimer mode initial

CDR turn off time after retimer mode de-assert

V_DDsupply ramp up requirements

V_CCsupply ramp up requirements

100

µs

t_d3

15

120

100

ms

ns

t_d4

VDD_ramp

VCC_ramp

ms

(1) See Operation Timing for more information

t

d2

h9

t

d1

ë_//ꢀ ë₅₅

ë₅₅ꢀ ë_//

Figure 1. Power-Up Timing for TMDS181

t_d3

/5w !ctive

t_d4

wetimer mode

h9 5e-assert or

Iꢀ5_{bY 5e-assert or

wedriver mode

Figure 2. CDR Timing for TMDS181

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6.10 TMDS Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

REDRIVER MODE

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX⁽²⁾

UNIT

d_R

Data rate (redriver mode)

250

3400

600

Mbps

ps

Propagation delay time (low to

high)

t_PLH

Propagation delay time (high to

low)

t_PHL

250

800

ps

Transition time (rise and fall

time); measured at 20% and

80% levels for data lanes.

TMDS clock meets t_T3for all

three times.

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; 1.48 Gbps and 2.97 Gbps data

lines, 148 MHz and 297 MHz clock

t_T1(1.4b)

75

ps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H; 1.48 Gbps, 2.97 Gbps

t_T3

100

ps

Default setting for internal intra-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps; See Figure 8

t_{SK_INTRA}

Intra-pair output skew

Inter-pair output skew

40

Default setting for internal inter-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps; See Figure 8

t_{SK_INTER}

100

ps

DR = 2.97 Gbps, PRE_SEL = NC,

EQ_SEL/A0 = NC ; . See Figure 12 at

TTP3

Total output data jitter

HDMI1.4b

t_JITD1(1.4b)

0.2

Tbit

CLK = 25 MHz, 74.25 MHz, 75 MHz, 150

MHz, 297 MHz

t_JITC1(1.4b)

Total output clock jitter

0.25

RETIMER MODE

d_R

Data rate (retimer mode)

0.25

6

Gbps

Automatic redriver to retimer

crossover (when selected)

Measured with input signal applied = 200

mVpp

d_XVR

0.75

1

1.25

f_CROSSOVERCrossover frequency hysteresis

250

0.4

MHz

PLLB_W

Data retimer PLL bandwidth

Default loop bandwidth setting

Tested when data rate >1.0Gbps

1

Input clock frequency detection

and retimer acquisition time

t_ACQ

180

µs

Tbit

ps

I_JT1

Input clock jitter tolerance

0.3

TX_TERM_CTL = L; PRE_SEL = NC; 6

Gbps data lines,

t_T1(2.0)

45

75

Transition time (rise and fall

time); measured at 20% and

80% levels for data lanes.

TMDS clock meets t_T3for all

three times.

TX_TERM_CTL = NC; PRE_SEL = NC;

1.48 Gbps and 2.97 Gbps data lines, 148

MHz and 297 MHz clock

t_{T1 (1.4b)}

ps

TX_TERM_CTL = NC; PRE_SEL = NC;

1.48 Gbps, 2.97 Gbps, 6 Gbps data lines,

148 MHz, 297 MHz clock

t_T3

100

t_DCD

OUT_CLK ± duty cycle

Inter-pair output skew

40%

50%

60%

0.2

Default setting for internal inter-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data

lines, 148 MHz, 297 MHz clock; See

Figure 8

t_{SK_INTER}

Tch

Default setting for internal intra-pair skew

adjust, TX_TERM_CTL = NC; PRE_SEL =

NC; 1.48 Gbps, 2.97 Gbps, 6 Gbps data

lines, 148 MHz, 297 MHz clock; See

Figure 8

t_{SK_INTRA}

Intra-pair output skew

Total output clock jitter

0.15

0.25

Tbit

CLK = 25 MHz, 74.25 MHz, 75 MHz, 150

MHz, 297 MHz

t_JITC1(1.4b)

(1) The typical rating is simulated at 3.3 V V_CCand 1.2 V V_DDand at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C unless otherwise noted

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TMDS Switching Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX⁽²⁾

UNIT

t_JITC1(2.0)

DR = 6 Gbps: CLK = 150 MHz

0.3

Tbit

3.4 Gbps < R_bit≤ 3.712 Gps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H

0.4

2

3.712 Gbps < R_bit< 5.94 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H

–0.0332R_bit

+

Total output data jitter

See Figure 14

t_JITD2

0.2312R_bit

Tbit

0.1998

5.94 Gbps ≤ R_bit≤ 6.0 Gbps

TX_TERM_CTL = NC; PRE_SEL = NC;

OE = H

0.6

6.11 HPD Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP⁽¹⁾

MAX⁽²⁾

UNIT

ns

t_PD(HPD)

t_T(HPD)

Propagation delay from HPD_SNK to

See Figure 16; not valid during

switching time

40

2

120

HPD_SRC; rising edge and falling edge⁽²⁾

HPD logical disconnected timeout

See Figure 17

ms

(1) The typical rating is simulated at 3.3 V V_CCand 1.2 V V_DDand at 27°C unless otherwise noted

(2) The maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C unless otherwise noted

6.12 DDC and I²C Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

V_CC= 3.3 V

MIN

TYP

MAX UNIT

t_r

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Pulse duration, SCL high

300

ns

μs

ns

μs

t_f

t_HIGH

t_LOW

t_SU1

0.6

1.3

100

0.6

1.3

Pulse duration, SCL low

Setup time, SDA to SCL

t_{ST, STA}

t_HD,STA

t_ST,STO

t_(BUF)

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

Bus free time between stop and start condition

Source to sink: 100kbps pattern;

t_PLH1

t_PHL1

t_PLH2

t_PHL2

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

360

230

250

200

ns

Cb(Sink) = 400 pF⁽¹⁾; see Figure 20

Sink to source: 100kbps pattern;

Cb(Source) = 100 pF⁽¹⁾; see Figure 21

(1) Cb = total capacitance of one bus line in pF.

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6.13 Typical Characteristics

200

180

160

140

120

100

80

350

325

300

275

250

225

200

175

150

125

100

75

1.2V

3.3V

1.2V

3.3V

60

40

50

0

0.5

1

1.5

2

2.5

3

3.5

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

Data Rate (Gbps)

D001

D002

Figure 3. Current vs Data Rate Redriver Mode

Figure 4. Current vs Data Rate Retimer Mode

1600

1400

1200

1000

800

600

400

200

0

VOD No Term

VOD 150 to 300 W

VOD 75 to 150 W

4

4.5

5

5.5

6

6.5

7

7.5

8

VSADJ (kW)

D003

Figure 5. VSADJ vs VOD

7 Parameter Measurement Information

V_CC

3.3 ë

50 Ω

0.ꢀ pC

5+

ò

ù

Receiver

Driver

V_ID

V_D+

V_Y

5t

V_ID= V_D+œ V_Dœ

V_OD= V_Yœ V_Z

V_Dœ

V_Z

V_ICM= (V_D++ V_Dœ

)

V_OC= (V_Y+ V_Z)

2

Figure 6. TMDS Main Link Test Circuit

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Parameter Measurement Information (continued)

4.0 V

V_CC

V_ID

2.6 V

V_ID+

V_ID(pp)

0 V

V_IDœ

t_PHL

80%

t_PLH

80%

V_OD(pp)

V_OD

0 V

20%

t_f

20%

t_r

Figure 7. Input/Output Timing Measurements

t_{SK_INTRA}

TMDS_OUTxp

TMDS_OUTxn

50%

t_{SK_INTER}

TMDS_OUTyp

TMDS_OUTyn

Figure 8. TMDS Output Skew Measurements

V_OC

Figure 9. HDMI/DVI TMDS Output Common Mode Measurement

ûV_OC(SS)

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Parameter Measurement Information (continued)

ëh5(tt)

tw9_{9[=ù

ësadj = 7.06YQ

Figure 10. Output Differential Waveform

tw9_{9[ = ù

ësadj = 7.06 lQ

tw9_{9[ = [

ësadj = 7.06 lQ

1^sꢀbiꢀ

2^ndꢀo ꢁ biꢀ

ëh5({{)

ëh5(tt)

Figure 11. Output De-Emphasis Waveform

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Parameter Measurement Information (continued)

Avcc⁽⁴⁾

R_T

(5)

R_T

SMA

REF

Cable

EQ

Data +

Coax

RX

+EQ

OUT

Data œ

Parallel⁽⁶⁾

BERT

Jitter Test

Instrument^(2,3)

FR4 PCB trace⁽¹⁾

and AC coupling

capacitors

Device

FR4 PCB trace

AVcc

R_T

[No Pre-

emphasis]

R_T

REF

Cable

EQ

SMA

Coax

Clk+

RX

+EQ

OUT

Clkœ

Jitter Test

Instrument^(2,3)

TTP4_EQ

TTP4

TTP1

TTP2

TTP3

TTP2_EQ

A. The FR4 trace between TTP1 and TTP2 is designed to emulate 1 to 8 inches of FR4, AC coupling capacitor,

connector, and another 1 to 8 inches of FR4. Trace width = 4 mils. 100-Ω differential impedance.

B. All jitter is measured at a BER of 10-9

C. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1

D. AVCC = 3.3 V

E. R_T= 50 Ω,

F. The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.

Figure 12. HDMI Output Jitter Measurement

HDMI Mask

mV

75

V

20

TMDS181 Post EQ

0

Eye Mask

œ20

œ75

H

T_bit

ps

0.3

0.5

0.7

œ33.7 œ25

25

33.7

Figure 13. Input Eye Mask Post EQ – TTP2_EQ

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Parameter Measurement Information (continued)

V

0

H

0

0.5

A. See Table 1.

Figure 14. Output Eye Mask at TTP4_EQ

Table 1. Output Eye Mask V and H Values

TMDS Data Rate (Gbps)

3.4 < DR < 3.712

H (T_bit

)

V (mV)

0.6

335

3.712 < DR < 5.94

5.94 ≤ DR ≤ 6.0

–0.0332R_bit²+0.2312 R_bit+ 0.1998

–19.66R_bit²+ 106.74R_bit+ 209.58

0.4

150

It5_{bY

It5_{w/

190Kꢀ

100Kꢀ

Figure 15. HPD Test Circuit

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HPD_SNK

V_CC

50%

0 V

t_PD(HPD)

HPD_SRC

V_CC

50%

0 V

Figure 16. HPD Timing Diagram 1

HPD_SNK

50%

V_CC

0 V

V_CC

HPD Logical Disconnect

Timeout

t_T(HPD)

HPD_SRC

0 V

Logically

Disconnected

Device Logically

Connected

Figure 17. HPD Logic Disconnect Timeout

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t_HD,STA

t_f

t_r

SCL

t_ST,STO

SDA

t_(BUF)

START

STOP

Figure 18. START and STOP Condition Timing

t_HIGH

t_LOW

SCL

t_ST,STA

SDA

t_SU1

Figure 19. SCL and SDA Timing

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SDA_SRC/SCL_SRC

INPUT

½ Vcc

t_PLH1

t_PHL1

80%

20%

SDA_SNK/SCL_SNK

OUTPUT

½ Vcc

t_f

t_r

Figure 20. DDC Propagation Delay – Source to Sink

SDA_SNK/SCL_SNK

INPUT

½ Vcc

t_PHL2

t_PLH2

80%

20%

SDA_SRC/SCL_SRC

OUTPUT

½ Vcc

t_f

t_r

Figure 21. DDC Propagation Delay – Sink to Source

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1 µF

ARC_OUT

SPDIF_IN

Receiver

Rest

V_EL

V_{EL SWING}

Figure 22. ARC Output

UI

0.4 UI

Figure 23. Rise and Fall Time of ARC

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8 Detailed Description

8.1 Overview

The TMDS181 is a DVI or HDMI™ retimer. The TMDS181 supports four TMDS channels, audio return channel

(SPDIF_IN/ARC_OUT), hot plug detect, and DDC interfaces. The TMDS181 supports signaling rates up to 6

Gbps in retimer mode to allow for the highest resolutions of 4k2k60p 24 bits per pixel and up to WUXGA 16-bit

color depth or 1080p with higher refresh rates. In redriver mode it supports HDMI1.4b with data rates up to 3.4

Gbps. The TMDS181 can be configured to support the HDMI2.0a standard which includes higher data rate, lower

clock swing, and clock frequency. The TMDS181 can automatically configure itself as a redriver at low data rate

(<1.0 Gbps) or as a retimer above this data rate. For passing compliance and reducing system-level design

issues, several features are included such as TMDS output amplitude adjust using an external resistor on the

VSADJ pin and source termination selection control. Device operation and configuration can be programmed by

pin strapping or I²C. Four TMDS181s can be used on one I²C bus when I2C_EN enable and device address set

by A0/A1.

To reduce active power, the TMDS181 supports dual power supply rails of 1.2 V on VDD and 3.3 V on VCC.

There are several methods of power management, such as going into power-down mode using three methods:

•

HPD is low

Writing a 1 to register 09h[3]

De-asserting OE

De-asserting OE clears the I²C registers, thus once reasserted the device must be reprogrammed if I²C was

used for device setup. Upon return to normal active operation from reasserted OE or reasserted HPD, the

TMDS181 requires the source to write a 1 to the TMDS_CLOCK_RATIO_STATUS bit for the TMDS181 to

resume 1/40^thclock mode. The TMDS181 does not reset this bit based upon a DDC read transaction. The

SIG_EN pin enables the signal detect circuit that provides an automatic power-management feature during

normal operation. When no valid signal is present on the inputs, the device will enter standby mode. By disabling

the detect circuit, the receiver block is always on. DDC bridge supports the HDMI2.0 SCDC communication, 100

Kbps data rate default and 400 kbps adjustable by software.

TMDS181 supports both fixed EQ gain control or adaptive equalization to compensate for different lengths of

input cables or board traces. The EQ gain can be software adjusted by I²C control or selection between two fixed

values or adaptive (Retimer Mode Only) equalization by pin strapping EQ_SEL pin. The customer can pull up or

down TX_TERM_CTL through a 65 kΩ resistor to change the termination impedance for improved output

performance when working in HDMI1.4b or leave it not connected. When not connected, the TMDS181 in

conjunction with the rate detect automatically changes its output termination to meet HDMI1.4b or HDMI2.0a

needs. For HDMI1.4b a transmitter termination of 150 Ω to 300 Ω is allowed for data rates above 2 Gbps to

compensate for reflections. The automatic termination selection will configure the TMDS181 for this. It is

important to note that there are times that this is not the best solution and no termination may be needed to pass

compliance. For HDMI2.0a the 75 Ω to 150 Ω transmitter termination is required and the link will not work if this

is not set.

The TMDS181 supports the audio return channel to support HDMI1.4b. To make implementation easier, the

TMDS181 supports input pin swapping and input polarity swap. When swapping the input pins, IN_CLK and

IN_D2 swap and IN_D1 and IN_D0 swap with each other. Swap works in both retimer and redriver mode.

Polarity swap exchanges the N and P channel polarity in each input lane and is only available during retimer

mode. Lane swap and polarity swap can be implemented at the same time in retimer mode.

Two temperature gradient versions of the device are available: extended commercial temperature range 0ºC to

85ºC (TMDS181) and industrial temperature range from –40ºC to 85ºC (TMDS181I).

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8.2 Functional Block Diagram

HPD_SRC

HPD_SNK

190<Q

SIGNAL

DETECT

VBIAS

SIG_DET_OUT

VSADJ

50Q

OUT_CLKp

IN_CLKp

IN_CLKn

TMDS

EQ

OUT_CLKn

Data Registers

SWAP

PLL

VBIAS

PLL Control

SERDES

50Q

IN_D[2:0]p

IN_D[2:0]n

OUT_D[2:0]p

EQ

TMDS

OUT_D[2:0]n

Control Block, I2C Registers

TERM_SEL

EQ_CTL

I2C_EN/PIN

PRE_SEL

Enable

EQ_SEL

A0

SIG_DET_OUT

EQ_SEL/A0

A1

SIG_EN

PRE_SEL

OE

TX_TERM_CTL

SWAP/POL

A1

Local I2C

Control

SDA_CTL

SCL_CTL

DDC Snoop Block

SDA_SRC

SDA_SNK

ACTIVE DDC BLOCK

SCL_SRC

SCL_SNK

SPDIF_IN

ARC_OUT

ARC Function

GND

1.2V

3.3V

VDD

VCC

VREG

8.3 Feature Description

8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It

is critical to transition the OE from a low level to a high level after the V_CCsupply has reached the minimum

recommended operating voltage. Achieve this transition by a control signal to the OE input, or by an external

capacitor connected between OE and GND. To ensure the TMDS181 is properly reset, the OE pin must be de-

asserted for at least 100 μs before being asserted. When OE is reasserted, the TMDS181 must be

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Feature Description (continued)

reprogrammed if it was programmed by I²C and not pin strapping. When implementing the external capacitor, the

size of the external capacitor depends on the power up ramp of the V_CCsupply, where a slower ramp-up results

in a larger-value external capacitor. Refer to the latest reference schematic for TMDS181; consider

approximately 200 nF capacitor as a reasonable first estimate for the size of the external capacitor. Figure 24

and Figure 25 show both OE implementations.

h9

ww{Ç = 200 YΩ

/

Figure 24. External Capacitor Controlled OE

GPO

OE

C

Figure 25. OE Input from Active Controller

8.3.2 Operation Timing

TMDS181 starts to operate after the OE signal is properly set after power-up timing completes. See Figure 1,

Figure 2, and Power-Up and Operation Timing Requirements. If OE is held low until V_DDand V_CCbecome stable,

there is no rail sequence requirement.

8.3.3 Swap and Polarity Working

TMDS181 incorporates swap function, which can set the input lanes in swap mode. The IN_D2 routes to the

OUT_CLK position. The IN_D1 swaps with IN_D0. The swap function only changes the input pins. The EQ setup

follows the new mapping (see Figure 26). This function can be used with the SWAP/POL pin 1 and control the

register 0x09h bit 7 for SWAP enable. Lane swap function works in both redriver and retimer mode.

The TMDS181 can also swap the input polarity signals. When SWAP/POL is high the n and p pins on each lane

will swap. Polarity swap only works when in retimer mode. Take care when this function is enabled and the

device is in automatic crossover mode between redriver and retimer modes. When the data rate drops to the

redriver level, the polarity swap is lost.

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Table 2. SWAP Function⁽¹⁾

Normal Operation

SWAP = L or CSR 0x09h bit 7 is 1’b1

IN_D2 → OUT_D2

IN_D1 → OUT_D1

IN_D0 → OUT_D0

IN_CLK → OUT_CLK

IN_D2 → OUT_CLK

IN_D1 → OUT_D0

IN_D0 → OUT_D1

IN_CLK → OUT_D2

(1) The output lanes never change, only the input lanes change. See

Figure 26.

36

35

34

33

32

Çꢁwa_/Ç[

hÜÇ_ꢀ2p

hÜÇ_ꢀ2n

{í!tꢂth[

1

2

{í!tꢂth[

36

35

34

33

32

Çꢁwa_/Ç[

hÜÇ_ꢀ2p

hÜÇ_ꢀ2n

1

2

Lb_ꢀ2p

Lb_ꢀ2n

Lb_ꢀ2p

Lb_ꢀ2n

ꢀ!Ç! [!bꢁ2

/[h/Y [!bꢁ

3

Itꢀ_{bY

hÜÇ_ꢀ1p

4

Itꢀ_{bY

hÜÇ_ꢀ1p

Itꢀ_{w/

Lb_ꢀ1p

Itꢀ_{w/

Lb_ꢀ1p

4

5

ꢀ!Ç! [!bꢁ1

ꢀ!Ç! [!bꢁ0

hÜÇ_ꢀ1n

Lb_ꢀ1n

Dbꢀ

31

30

Lb_ꢀ1n

Dbꢀ

6

31

30

6

Dbꢀ

7

Dbꢀ

7

29

28

27

26

25

Lb_ꢀ0p

hÜÇ_ꢀ0p

hÜÇ_ꢀ0n

!1

8

Lb_ꢀ0p

hÜÇ_ꢀ0p

hÜÇ_ꢀ0n

29

28

27

26

25

8

ꢀ!Ç! [!bꢁ0

ꢀ!Ç! [!bꢁ1

Lb_ꢀ0n

L2/_ꢁbꢂtLb

Lb_/[Yp

9

Lb_ꢀ0n

L2/_ꢁbꢂtLb

Lb_/[Yp

9

10

11

12

10

11

12

!1

hÜÇ_/[Yp

hÜÇ_/[Yn

/[h/Y [!bꢁ

hÜÇ_/[Yp

hÜÇ_/[Yn

ꢀ!Ç! [!bꢁ2

Lb_/[Yn

{í!t = ù

Ln bormal íorking

{í!t = [

Ln {wap íorking

Figure 26. TMDS181 Swap Function

8.3.4 TMDS Inputs

Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each

input data channel contains an adaptive or fixed equalizer to compensate for cable or board losses. The voltage

at the TMDS input pins must be limited below the absolute maximum ratings. An unused input should not be

connected to ground because this would result in excessive current flow damaging the device. An unused input

channel can be externally biased to prevent output oscillation. The complementary input pin is recommended to

be grounded through a 1 kΩ resistor and the other pin left open. The input pins can be polarity changed through

the local I²C register when in retimer mode.

8.3.5 TMDS Inputs Debug Tools

There are two methods for debugging a system to make sure the inputs to the TMDS181 are valid. A TMDS

error checker is implemented to provide a rough bit error rate per data lane. This allows the system implementer

to determine how the link between the source and TMDS181 is performing on all three data lanes. See RX

PATTERN VERIFIER CONTROL/STATUS Register.

If a high error count is evident, the TMDS181 has a way to view the general eye quality. A tool is available that

uses the I²C link to download the data that can be plotted for an eye diagram. This is available per data lane.

This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal on the

data pins. A clock at the proper frequency is required on the IN_CLK pins to generate the expected output data

rate.

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8.3.6 Receiver Equalizer

Equalizers are used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board

traces and cables. TMDS181 supports fixed receiver equalizer (Retimer and Redriver Mode) and adaptive

receiver equalizer (Retimer Mode) by setting the EQ_SEL/A0 pin or through I²C reg0Ah[5]. When EQ_SEL/A0 is

high, the EQ gain is fixed to 14 dB and when set low ,the EQ gain is set to 7.5 dB. TMDS181 operates in

adaptive equalizer mode when the EQ_SEL/A0 pin is left floating. The EQ gain is automatically adjusted based

on the data rate to compensate for trace or cable loss. Various fixed EQ values can be set through local I²C

control, reg0Dh[5:1]. The fixed EQ value can be programmed for both the data and clock. Adaptive equalization

is the default setting.

Figure 27. Adaptive EQ Gain Curve for >3.4 Gbps

8.3.7 Input Signal Detect Block

When SIG_EN is enabled, the TMDS looks for a valid TMDS clock signal input. The device is fully functional

when a valid signal is detected. If no valid TMDS clock signal is detected, the device enters standby mode

waiting for a valid signal at the clock input. The internal CDR is shut down and all of the TMDS outputs are in

high-Z status. TMDS signal detect circuit can be set as enable by SIG_EN pin or through local I²C control but is

default disabled. Implementer should activate this function in normal operation for power saving.

8.3.8 Audio Return Channel

The audio return channel in TMDS181 enables a TV, through a single HDMI cable, to send audio data upstream

to an A/V receiver or surround audio controller, increasing user flexibility and eliminating the need for any

separate S/PDIF audio connection. The TMDS181 supports single mode audio return channel. Customer can

import the S/PDIF signal to SPDIF_IN and send out the signal from ARC_OUT and pass through the general

HDMI cable to audio receiver. By I²C control, customer can disable ARC_OUT by register. Default enable after

initialize.

8.3.9 Transmitter Impedance Control

HDMI2.0a standard requires a termination impedance in the 75 Ω to 150 Ω range for data rates >3.4 Gbps.

Source termination is disabled at data rates <2 Gbps. When the data rate is between 2 Gbps and 3.4 Gbps, the

output signal may be better if the termination value is between 150 Ω to 300 Ω, depending upon system

implementation. It is important to note that there are times that this is not the best solution and no termination

may be needed to pass compliance. TMDS181 supports three different source termination impedances for

HDMI1.4b and HDMI2.0a. Pin 36, TX_TERM_CTL, offers a selection option to choose the output termination

impedance value. This function can be programmed using I²C, reg0Bh[4:3] TX_TERM_CTL. For HDMI2.0a the

75 Ω to 150 Ω transmitter termination is required and the link will not work if this is not set.

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Table 3. TX Termination Control

PIN 36

CONFIGURATION

DESCRIPTION

TX_TERM_CTL = H

TX_TERM_CTL = L

The transmitter has no termination

The transmit termination impedance is approximately 75 Ω to 150 Ω to support

HDMI2.0a

TX_TERM_CTL = NC Automatically selects the impedance

•

DR > 3.4 Gbps – 75 Ω to 150 Ω differential near end termination

2 Gbps > DR < 3.4 Gbps – 150 Ω to 300 Ω differential near-end termination

DR < 2 Gbps – No termination

8.3.10 TMDS Outputs

A 1% precision resistor, 7.06 kΩ, is recommended to be connected from VSADJ pin to ground to allow the

differential output swing to comply with TMDS signal levels. The differential output driver provides a typical 10

mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.

A_VCC

V_CC

TMDS181

Zo = RT

TMDS DRIVER

TMDS RECEIVER

Figure 28. TMDS Driver and Termination Circuit

Referring to Figure 28, if V_CC(TMDS181 supply) and AVCC (sink termination supply) are both powered, the

TMDS output signals are high impedance when OE = high. The normal operating condition is that both supplies

are active. Refer to Figure 28, if V_CCis on and AVCC is off, the TMDS outputs source a typical 5-mA current

through each termination resistor to ground. A total of 33 mW of power is consumed by the terminations

independent of the OEB logical selection. When AVCC is powered on, normal operation (OE controls output

impedance) is resumed. When the power source of the device is off and the power source to termination is on,

the I_O(off)output leakage current specification ensures the leakage current is limited to 45 μA or less. The V_ODof

the clock and data lanes can be reduced through I²C. See Table 12 for details. Figure 3 shows the different

output voltages based on the different VSADJ settings.

8.3.11 Pre-Emphasis/De-Emphasis

The TMDS181 provides de-emphasis as a way to compensate for ISI loss between the TMDS181 outputs to a

TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL

pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal

pre-conditioning to offset interconnect losses from the TMDS181 device to the TMDS receiver. De-emphasis is

recommended to be set at 0 dB while connecting to a receiver through short PCB route. When pulled to ground

though a 65 kΩ resistor - 2 dB can be realized, see Figure 11. When using I²C, reg0Ch[1:0] is used to make

these adjustments.

As there are times that true pre-emphasis may be the best solution there are two ways to accomplish this. If pin

strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the VOD swing

and then pulling the PRE_SEL pin to ground using the 65 kΩ resistor, see Figure 29. If using I²C there are two

methods to accomplish this. The first is similar to pin strapping by reducing the VSADJ resistor value and then

implementing - 2 dB de-emphasis. The second method is to set reg0Ch[7:5] = 011 and set reg0Ch[1:0] = 01

which will accomplish the same pre-emphasis setting, see Figure 30.

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NOTE

De-emphasis is only implement able during retimer mode. In redriver mode this function is

not available.

tw9_{9[ = ù

ësadj = 7.06YQ

tw9_{9[ = [

ësadj = 4.5YQ

1^sꢁbiꢁ

ëh5(tt) = 1400mëpp

2^ndꢁo ꢂ biꢁ

ëh5({{) = 11ꢀ0mëpp

Figure 29. Output Pre-Emphasis Using Pin Strapping

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tw9_{9[ = ù

ësadj = 7.06YQ

L2/ weg0/hꢀ7:5] = 011

weg0/ꢀ1:0] = 01

1^sꢀbiꢀ

2^ndꢀo ꢁ biꢀ

ëh5(tt) = 1200mëpp

ëh5({{) = 1020mëpp

Figure 30. Output Pre-Emphasis Using I²C

8.4 Device Functional Modes

8.4.1 Retimer Mode

Clock and data recovery circuits (CDR) are used to track, sample, and retime the equalized data bit streams. The

CDRs are designed with a loop bandwidth to minimize the amount of jitter transfer from the video source to the

TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz will be transferred to the TMDS outputs.

Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce

the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock

approximately above 100 MHz when jitter cleaning is needed for robust operation when this option is enabled

(default). The retimer operates at about 1 Gbps to 6 Gbps DR.

When systems switch to higher data rates above 3.4 Gbps, the CDR operates at between 85 MHz to 150 MHz

pixel clock (3.4+ to 6.0 Gbps), supporting up to 4K2K high resolution with a 60 Hz refresh rate, or 3D 1080p

HDTV. At pixel clock below 100 MHz, the TMDS181 automatically bypasses the internal retimer and operates as

a redriver. When the video source changes resolution, the internal retimer starts the acquisition process to

determine the input clock frequency and acquire lock to new data bit streams. During the clock frequency

detection period and the retimer acquisition period that last approximately 7 ms, the TMDS drivers can be kept

active (default) or programmed to be disabled to avoid sending invalid clock or data to the downstream receiver.

The TMDS181 can be configured to work as a redriver (full range), crossover (redriver-retimer), and retimer (full

range).

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Device Functional Modes (continued)

8.4.2 Redriver Mode

The TMDS181 also has a redriver mode that can be enabled through I²C, at reg0Ah[1:0] DEV_FUNC_MODE,

which compensates for ISI channel loss. In this mode, power is reduced as the CDR and PLL are turned off.

When in automatic mode, the TMDS181 is in redriver mode for data rates <1.0 Gbps. By using I²C, the device

can be put in redriver mode for the complete data range of 250 Mbps to 3.4 Gbps. This is done by writing a 00 to

register 0Ah[1:0]. If the link has excessive random jitter, then retimer mode is the best operating mode. When in

redriver mode, the device only compensates for ISI loss. When in redriver mode compliance is not guaranteed as

skew compensation and retiming functions are disabled. If a significant amount of random jitter is present, the

system may not pass compliance at the connector.

8.4.3 DDC Training for HDMI2.0a Data Rate Monitor

As part of discovery, the source reads the sink’s E-EDID information to understand the capabilities of the sink.

Part of this read is HDMI Forum Vendor Specific Data Block (HF-VSDB) MAX_TMDS_Character_Rate byte to

determine the data rate supported. Depending upon the value, the source writes to slave address 0xA8 offset

0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The TMDS181 snoops this write to determine the TMDS clock ratio

and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is

set to 1/40^thof TMDS bit period. If a 0 is written, then the TMDS clock is set to 1/10^thof TMDS bit period. The

TMDS181 defaults to 1/10^thof TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. When

HPD is deasserted, this bit is reset to default values. If the source does not write this bit, the TMDS181 will not

be configured for TMDS clock 1/40^thmode in support of HDMI2.0a. As the TMDS181 is in the system link, but

not recognized as part of the link, it is possible that the source could read the sink EDID where this bit is set and

does not rewrite this bit. If the TMDS181 has entered a power-down state, this bit is cleared and does not re-set

on a read. To work properly, the bit has to be set again with a write by the source.

8.4.4 DDC Functional Description

The TMDS181 solves sink/source level issues by implementing a master/slave control mode for the DDC bus.

When the TMDS181 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it will transfer the

data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the

feedback from the downstream device, the TMDS181 will pull up or pull down the SDA_SRC bus and deliver the

signal to the source.

The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct

value to address 0Bh through the I²C interface. The DDC lines are 5 V tolerant when the device is powered off.

NOTE

The TMDS181 utilizes clock stretching for DDC transactions. As there are sources and

sinks that do not perform this function correctly a system may not work correctly as DDC

transactions are incorrectly transmitted/received. To overcome this a snoop configuration

can be implemented where the SDA/SCL from the source is connected directly to the

SDA/SCL sink. The TMDS181 will need its SDA_SNK and SCL_SNK pins connected to

this link in order to correctly configure the TMDS_CLOCK_RATIO_STATUS bit. Care must

be taken when this configuration is being implemented as the voltage levels for DDC

between the source and sink may be different, 3.3 V vs 5 V; See Figure 35 and See

Figure 36

8.4.5 Mode Selection Functional Description

Mode selection definition: This bit lets the receiver know where the device is located in a system for the purpose

of centering the AEQ point. The TMDS181 is targeting sink applications, so the default value is 1, which will

center the EQ at 12 to 13 dB depending upon TMDS_CLOCK_RATIO_STATUS value (see Equalization Control

Register). If the TMDS181 is in a source application, the value should be changed to a value of 0, which centers

the EQ at 6.5 to 7.5 dB depending upon the TMDS_CLOCK_RATIO_STATUS value.

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8.5 Register Maps

8.5.1 Local I²C Overview

The TMDS181 local I²C interface is always enabled, but will only be able to overwrite pin strapped features when

I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals are used for I²C clock and data respectively. The

TMDS181 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1

(January 2000), and supports the fast mode transfer up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7-

bit device address for TMDS181 decides by the combination of EQ_SEL/A0 and A1. Figure 31 clarifies the

TMDS181 target address.

Figure 31. TMDS181 I²C Device Address Description

A1/A0

00

7 (MSB)

6

0

5

1

4

1

3

1

0

2

1

0

1

0

1

0

1

0 (W/R)

0/1

HEX

BC/BD

BA/BB

B8/B9

B6/B7

1

01

0/1

10

0/1

11

0/1

The typical source application of the TMDS181 is as a retimer in a TV connecting the HDMI output connector

and an internal HDMI transmit through flat cables. The register setup can adjust by source side. When TMDS181

is used in a sink side application, it receives data from input connector and transmits to receiver. Local I²C buses

run at 400 kHz supporting fast-mode I²C operation.

The following procedure is used to write to the TMDS181 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TMDS181 7-bit address and a

zero-value W/R bit to indicate a write cycle.

2. The TMDS181 acknowledges the address cycle.

3. The master presents the sub-address (I²C register within TMDS181) to be written, consisting of one byte of data, MSB-

first.

4. The TMDS181 acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I²C register.

6. The TMDS181 acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an

acknowledge from the TMDS181.

8. The master terminates the write operation by generating a stop condition (P).

The following procedure is used to read the TMDS181 I²C registers.

1. The master initiates a read operation by generating a start condition (S), followed by the TMDS181 7-bit address and a

one-value W/R bit to indicate a read cycle.

2. The TMDS181 acknowledges the address cycle.

3. The TMDS181 transmits the contents of the memory registers MSB-first starting at register 00h.

4. The TMDS181 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte

transfer; the I²C master acknowledges reception of each data byte transfer.

5. If an ACK is received, the TMDS181 transmits the next byte of data.

6. The master terminates the read operation by generating a stop condition (P).

NOTE

Upon reset, the TMDS181 sub-address is always set to 0x00. When no sub-address is

included in a read operation, the TMDS181 sub-address increments from the previous

acknowledged read or write data byte. If it is required to read from a sub-address that is

different from the TMDS181 internal sub-address, a write operation with only a sub-

address specified is needed before performing the read operation.

33

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Refer to Local I²C Control Bit Access TAG Convention for TMDS181 local I²C register descriptions. Reads from

reserved fields not described return zeros, and writes are ignored.

8.5.2 Local I²C Control Bit Access TAG Convention

Reads from reserved fields return zero, and writes to read-only reserved registers are ignored. All addresses not

defined by this specification are considered reserved. Reads from these addresses return zero and writes are

ignored.

BIT ACCESS TAG CONVENTIONS

A table of bit descriptions is typically included for each register description that indicates the bit field name, field

description, and the field access tags. Table 4 describes the field access tags.

Table 4. Field Access Tags

ACCESS TAG

NAME

Read

Write

Set

DESCRIPTION

R

W

S

The field will be read by software

The field will be written by software

The field will be set by a write of 1. Writes of 0 to the field have no effect

Hardware may autonomously update this field

U

Update

8.5.3 CSR Bit Field Definitions

8.5.3.1 ID Registers

Table 5. ID Registers Field Descriptions

ADDRESS

BITS

DESCRIPTION

ACCESS

00h~07h

7:0

DEVICE_ID

R

These fields return a string of ASCII characters “TMDS181” followed by one space

character.

TMDS181: Address 0x00 – 0x07 = {- 0x54”T”, 0x4D”M”, 0x44”D”, 0x53”S”, 0x31”1”,

0x38”8”, 0x31”1”, 0x20},

08h

7:0

REV _ID. This field identifies the device revision.

0000001 – TMDS181 revision 1

R

34

TMDS181, TMDS181I

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ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

8.5.3.2 MISC CONTROL Register

Table 6. MISC CONTROL Register Field Descriptions

ADDRESS

BITS

DEFAULT DESCRIPTION

ACCESS

09h

7

1’b0

LANE_SWAP. This field swaps the input lanes as per Figure 26.

RWU

0 – Disable (default) no lane swap

1 – Enable: Swaps input lanes (redriver and retimer mode)

Note: Field is loaded from SWAP/POL pin; Writes are ignored when I2C_EN/PIN = 0

6

1’b0

LANE_POLARITY swaps the input data and clock lanes polarity.

0 – Disabled (default) no polarity swap

RWU

1 – Swaps the input data and clock lane polarity (retimer mode only)

Note: Field is loaded from SWAP/POL pin; Writes are ignored when I2C_EN/PIN = 0

5

4

1’b0

Reserved

R

SIG_EN. This field enables the clock lane activity detect circuitry. (Redriver mode only

because the retimer requires a clock input to work, so without a clock input, the

device enters standby regardless)

RWU

0 – Disable (default) Clock detector circuit closed and receiver always works in

normal operation.

1 – Enable, clock detector circuit makes the receiver automatically enter the standby

state when no valid data detect.

Note: Field is loaded from SIG_EN pin; Writes are ignored when I2C_EN/PIN = 0

3

2

1’b0

PD_EN

RW

0 – Normal working (default)

1 – Forced power down by I²C, lowest power state

HPD_AUTO_PWRDWN_DISABLE

0 – Automatically enters power-down mode based on HPD_SNK (default)

1 – Does not automatically enter power down mode

I2C_DR_CTL. I²C data rate supported for configuring device.

1:0

2’b10

00 – 5 Kbps

01 – 10 Kbps

10 – 100 Kbps (default)

11 – 400 Kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling

400 Kbps mode)

0Ah

7

6

5

4

1’b1

1’b0

1’b1

Application mode selection (see Device Functional Modes)

TMDS181

0 – Source

1 – Sink (default)

RW

HPDSNK_GATE_EN. The field sets the functional relationship between HPD_SNK

and HPD_SRC.

0 – HPD_SNK passed through to the HPD_SRC (default)

1 – HPD_SNK does not pass through to the HPD_SRC.

EQ_ADA_EN. This field enables the equalizer functioning state.

0 – Fixed EQ

1 – Adaptive EQ (default)

RWU

RW

Writes are ignored when I2C_EN/PIN = 0

EQ_EN. This field enables the equalizer.

0 -- EQ disable

1 – EQ enable (default)

Writes are ignored when I2C_EN/PIN = 0

3

2

1’b0

Reserved

R

APPLY_RXTX_CHANGES, Self-clearing write-only bit.

W

Writing a 1 to this bit will apply new TX_TERM, HDMI_TWPST1, EQ_EN,

EQ_ADA_EN, VSWING, Fixed EQ Value settings to the clock and data lanes. Writes

to the respective registers do not take immediate effect.

This bit does not need to be written if I²C configuration occurs while HPD_SNK are

low, I²CPD_EN = 1 or there is no HDMI clock applied and SIGN_EN is high.

1:0

2’b01

DEV_FUNC_MODE. This field selects the device working function mode.

00 – Redriver mode: 250 Mbps – 3.4 Gbps

RW

01 – Automatic redriver to retimer crossover at 1.0 Gbps (default)

10 – Automatic retimer when HDMI2.0a based upon

TMDS_CLOCK_RATIO_STATUS

11 – Retimer mode across full range 250 Mbps to 6 Gbps

When changing crossover point, need to toggle PD_EN or toggle external HPD_SNK.

35

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Table 6. MISC CONTROL Register Field Descriptions (continued)

ADDRESS

BITS

7:5

DEFAULT DESCRIPTION

3’b000 Reserved

ACCESS

R

0Bh

4:3

2'b00

TX_TERM_CTL. Controls termination for HDMI TX.

RWU

00 – No termination (default)

01 – 150 Ω to 300 Ω

10 – Reserved

11 – 75 Ω to 150 Ω

Note: Writes are ignored when I2C_EN/PIN = 0; reflects the value of TX_TERM_CTL

pin.

2

1

1'b0

DDC_DR_SEL Defines the DDC output speed for DDC bridge

0 = 100 kbps (default)

1 = 400 kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be set before enabling

400 Kbps mode)

RW

TMDS_CLOCK_RATIO_STATUS. This field is updated from snoop of DDC write to

slave address 0xA8 offset 0x20 bit 1 that occurred on the SDA_SRC/SCL_SRC

interface. When bit 1 of address 0xA8 offset 0x20 in the SCDC register set is written

to a 1’b1, then this field will be set to a 1’b1. When bit 1 of address 0xA8 offset 0x20

is written to a 1’b0, then this field will be set to a 1’b0. This field is reset to default

value whenever HPD_SNK is de-asserted for greater than 2 ms.

RWU

0 – TMDS Clock is 1/10 of TMDS bit period (default)

1 – TMDS Clock is 1/40 of TMDS bit period

0

1'b0

DDC_TRAIN_SETDISABLE; This field indicate the DDC training block function status.

If disabled the device will only work in HDMI1.x or DVI modes.

0 – DDC training enable (default)

1 – DDC training disable

Note: To force TMDS_CLOCK_RATIO_STATUS to 1 this register bit must be set to 1

which will force the 1/40 mode for HDMI2.0

RW

0Ch

7:5

3’b000

VSWING_DATA: Data output swing control

000 – Vsadj set (default)

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

4:2

3’b000

VSWING_CLK: Clock output swing control: Default is set by Vsadj resistor value and

the value of reg_0Dh[0].

RW

000 – Vsadj (default)

001 – Increase by 7%

010 – Increase by 14%

011 – Increase by 21%

100 – Decrease by 30%

101 – Decrease by 21%

110 – Decrease by 14%

111 – Decrease by 7%

1:0

2’b00

HDMI_TWPST1[1:0]. HDMI de-emphasis FIR post-cursor-1 signed tap weight.

RWU

(Retimer Mode Only)

00 – No de-emphasis (default)

01 – 2 dB de-emphasis

10 – Reserved

11 – Reserved

Note: Reflects value of PRE_SEL pin; Writes are ignored when I2C_EN/PIN = 0

36

TMDS181, TMDS181I

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ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

8.5.3.3 Equalization Control Register

Table 7. Equalization Control Register Field Descriptions

ADDRESS

BITS

7:6

DEFAULT DESCRIPTION

ACCESS

0Dh

2’b00

Reserved

R

5:3

1’b000

Data lane EQ – Sets fixed EQ values

HDMI1.x

RW

HDMI2.0a

000 – 0 dB (default)

001 – 4.5 dB

000 – 0 dB (default)

001 – 3 dB

010 – 6.5 dB

010 – 5 dB

011 – 8.5 dB

011 – 7.5 dB

100 – 9.5 dB

101 – 11 dB

110 – 13 dB

111 – 14.5 dB

100 – 10.5 dB

101 – 12 dB

110 – 14 dB

111 – 16.5 dB

2:1

1’b00

Clock lane EQ - Sets fixed EQ values

HDMI1.x

RW

HDMI2.0a

00 – 0 dB (default)

01 – 1.5 dB

00 – 0 dB (default)

01 – 1.5 dB

10 – 3 dB

11 – RSVD

11 – 4.5 dB

0

1’b0

DIS_HDMI2_SWG:

0 – Clock V_ODis half of set values when TMDS_CLOCK_RATIO_STATUS states

in HDMI2.0a mode (default)

1 – Disables TMDS_CLOCK_RATIO_STATUS control of the clock VOD so output

swing is at full swing.

37

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.5.3.4 RX PATTERN VERIFIER CONTROL/STATUS Register

Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description⁽¹⁾

ADDRESS

BITS

DEFAULT

DESCRIPTION

ACCESS

0Eh

7:4

4’b0000

PV_SYNC[3:0]. Pattern timing pulse. This field is updated for 8UI once every cycle

of the PRBS generator. 1 bit per lane.

R

3:0

4’b0000

PV_LD[3:0]. Load pattern-verifier controls into RX lanes. When asserted high, the

PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values are enabled into the

corresponding RX lane. These values are then latched and held when PV_LD[n] is

subsequently deasserted low. 1 bit per lane.

RWU

0Fh

10h

7:4

3:0

7

4’b0000

1’b0

PV_FAIL[3:0]. Pattern verification mismatch detected. 1 bit per lane.

PV_TIP[3:0]. Pattern search/training in progress. 1 bit per lane.

RU

RW

PV_CP20. Customer pattern length 20/16 bits.

0 – 16 bits (default)

1 – 20 bits

6

1’b0

Reserved

R

5:3

3’b000

PV_LEN[2:0]. PRBS pattern length

000 – PRBS7 (default)

001 – PRBS11

RW

010 – PRBS23

011 – PRBS31

100 – PRBS15

101 – PRBS15

110 – PRBS20

111 – PRBS20

2:0

3’b000

PV_SEL[24:0]. Pattern select control

RW

000 – Disabled (default)

001 – PRBS

010 - Clock

011 - Custom

1xx – Timing only mode with sync pulse spacing defined by PV_LEN

11h

12h

13h

7:0

7:4

3:0

7:3

2:0

7

‘h00

PV_CP[7:0]. Custom pattern data.

RW

R

PV_CP[15:8]. Custom pattern data.

4’b0000

5’b00000

3’b000

1’b0

Reserved

PV_CP[19:16]. Custom pattern data. Used when PV_CP20 = 1’b1.

Reserved

RW

R

14h

15h

PV_THR[2:0]. Pattern-verifier retain threshold.

DESKEW_CMPLT. Indicates that TMDS lane deskew has completed when high.

Reserved

RW

R

6:5

4

2’b00

R

1’b0

BERT_CLR. Clear BERT counter (on rising edge).

TST_INTQ_CLR. Clear latched interrupt flag.

TST_SEL[2:0]. Test interrupt source select.

PV_DP_EN[3:0]. Enable datapath verified based on DP_TST_SEL, 1 bit per lane.

Reserved

RSU

RW

R

3

1’b0

2:0

7:4

3

3’b000

4’b0000

1’b0

16h

2:0

3’b000

DP_TST_SEL[2:0] Selects pattern reported by BERT_CNT[11:0], TST_INT[0] and

TST_INTQ[0] and PV_DP_EN is non-zero.

000 – TMDS disparity or data errors (default)

001 – FIFO errors

RW

010 – FIFO overflow errors

011 – FIFO underflow errors

100 – TMDS deskew status

101,110,111 – Reserved

17h

7:4

3:0

7:0

7:4

3:0

4’b0000

‘h00

TST_INTQ[3:0]. Latched interrupt flag. 1 bit per lane.

TST_INT[3:0]. Test interrupt flag. 1 bit per lane.

BERT_CNT[7:0]. BERT error count. Lane 0

Reserved

RU

R

18h

19h

4’b0000

BERT_CNT[11:8]. BERT error count. Lane 0

RU

(1) If PV_DP_EN is used to monitor TMDS data path errors the counters for lanes 0, 1, 2, and 3 are ignored.

38

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description⁽¹⁾(continued)

ADDRESS

1Ah

BITS

7:0

7:4

3:0

7:0

7:4

3:0

7:0

7:4

3:0

7

DEFAULT

‘h00

DESCRIPTION

ACCESS

RU

R

BERT_CNT[19:12]. BERT error count. Lane 1

Reserved

1Bh

4’b0000

‘h00

BERT_CNT[23:20]. BERT error count. Lane 1

BERT_CNT[31:24]. BERT error count. Lane 2

Reserved

RU

R

1Ch

1Dh

4’b0000

‘h00

BERT_CNT[35:32]. BERT error count. Lane 2

BERT_CNT[19:12]. BERT error count. Lane 3

Reserved

RU

R

1Eh

4’b0000

‘h00

1Fh

20h

BERT_CNT[23:20]. BERT error count. Lane 3

RU

R

1’b0

Power Down Status Bit.

0 – Normal Operation (default)

1 – Device in Power Down Mode

6

1’b0

Standy Status Bit.

0 – Normal Operation (default)

1 – Device in Standby Mode

R

5:0

6’b000000

Reserved

39

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMDS181 was defined to work in many applications. This includes source applications like a Blu-ray™ DVD

player or AVR. The adaptive receive equalizer makes it ideal for sink applications like UHDTV, monitors, and

projectors where cable length can be widely varied. When in a sink application, the designer must consider

several system-level architectures. The TMDS181 is also capable of working in an active cable to extend the

cable length even further.

9.2 Typical Applications

9.2.1 Source Side Application

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40

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

Typical Applications (continued)

9.2.1.1 Design Requirements

The TMDS181 can be designed into many different applications. All applications have certain requirements for

the system to work properly. Two voltage rails are required to support the lowest power consumption possible.

The OE pin must have a 0.1 µF capacitor to ground. This pin can be driven by a processor, but the pin needs to

change states after voltage rails have stabilized. The best way to configure the device is by using I²C. However,

pin strapping is provided because I²C is not available in all cases. As sources may have different naming

conventions, it is necessary to confirm that the link between the source and the TMDS181 are correctly mapped.

A swap function is provide for the input pins in case signaling is reversed between source and device. The

control pin values in Table 9 are based upon driving pins with a microcontroller; otherwise, the shown

pullup/pulldown configuration meet device levels. Table 9 provides information on expected values in order to

perform properly.

Table 9. Design Parameters

DESIGN PARAMETER

VALUE

3.3 V

V_CC

V_DD

1.2 V

Main link input voltage

V_ID= 75 mVpp to 1.2 Vpp

65 kΩ resistor connected to GND

Not connected

Control pin max voltage for low

Control pin voltage range mid

Control pin min voltage for high

VSADJ resistor

65 kΩ resistor connected to Vcc

7.06 kΩ 1%

9.2.1.2 Detailed Design Procedure

The TMDS181 is a signal conditioning device that provides several forms of signal conditioning to support

compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished using

receive equalization, retiming, and output driver configure ability. The transmitter drives 2 to 3 inches of board

trace and connector when compliance is required at the connector.

To design in the TMDS181 for a source side application, the designer must understand the following.

•

Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.

Based upon this loss profile and signal swing, determine the optimal location for the TMDS181 in order to

pass source electrical compliance, usually within 2 to 3 inches of the connector.

•

Use the typical application Figure 32 for information on control pin resistors.

The TMDS181 has a receiver adaptive equalizer, but can also be configured using EQ_SEL control pin.

Set the V_OD, pre-emphasis and termination levels appropriately to support compliance by using the

appropriate VSADJ resistor value and setting PRE_SEL and TX_TERM_CTL control pins.

•

The thermal pad must be connected to ground.

See schematics in Figure 32 on recommended decoupling capacitors from V_CCpins to ground.

41

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

9.2.1.3 Application Curves

Figure 33. Input Eye After 3M Cable at 5.94Gbps

Figure 34. Output Eye from TMDS181 after 3M Input Cable

at 5.94Gbps

9.2.2 Sink Side Application

For a sink side application, HPD needs consideration. The TMDS181 drives the HPD signal to 3.3 V, which

meets requirements, but if 5 V HPD signaling is required, the two circuits shown in Figure 35 are required. As

sources are not consistent in implementing all aspects of the DDC link, TI recommends to configure the

TMDS181 as per Figure 35. Another consideration for how HPD is implemented is the architecture and behavior

of the HDMI RX/scalar. The standard requires sinks to clear the TMDS_CLOCK_RATIO_STATUS in the SCDC

when either +5 V power signal from source is not present or when hot plug detect pin goes low for 100 ms or

more. When HPD goes low, the TMDS181 automatically clears this bit. The TMDS181 expects the

TMDS_CLOCK_RATIO_STATUS bit to be set with a write from source to receiver/sink. If this does not happen,

the TMDS181 may come up in the wrong configuration. Until the HDMI ecosystem matures, TI recommends to

implement sink application as per Figure 36 to address this.

Designing the TMDS181 into a sink side application requires similar care as for a source side application.

However, because compliance is at the receiver, there is more flexibility for the transmitter to the HDMI

RX/chipset link. Because many different reflection points are possible, the TMDS181 allows for swing, pre-

emphasis, and transmitter termination control that can help minimize these reflections. The TMDS181 has a 3.3

V HPD drive capability which meets requirements. In cases where the designer needs to support 5 V HPD drive

capability, the circuit shown in Figure 35 is required.

To design in the TMDS181 for a source side application, the designer must understand the following.

•

Determine the loss profile between the RX/chipset and the HDMI/DVI connector

Based upon this loss profile and signal swing, determine the optimal location for the TMDS181 to pass sink

electrical compliance.

•

Use the typical application Figure 35 for information on control pin resistors.

The TMDS181 has a receiver adaptive equalizer, but can also be configured using EQ_SEL control pin.

Set the V_OD, pre-emphasis and termination levels appropriately to support a link between TMDS181 and

HDMI RX/chipset by using the appropriate VSADJ resistor value and setting PRE_SEL and TX_TERM_CTL

control pins.

•

The thermal pad must be connected to ground.

See schematics in Figure 35 on recommended decoupling capacitors from VCC pins to ground.

Because the HDMI ecosystem supporting 4k2kp60 is not mature, TI recommends to design the TMDS181

into the sink application as shown in Figure 36.

42

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

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hÜÇ_ꢀ1n

hÜÇ_ꢀ0p

hÜÇ_ꢀ0n

hÜÇ_ꢅ[Yp

hÜÇ_ꢅ[Yn

5

ꢀ1p

6

ꢀ1n

8

ꢀ0p

ꢆ

ꢀ0n

11

12

Çꢂꢀ{_ꢅ[Yp

Çꢂꢀ{_ꢅ[Yn

hptional

h9

5ë

ꢅ!{9_Dꢄꢀ1

ꢅ!{9_Dꢄꢀ2

ꢅ!{9_Dꢄꢀ3

ꢅ!{9_Dꢄꢀ4

Lf 5ë is required. {ee 5ë

Itꢀ implemenꢁaꢁion

below

47YQ

38

3ꢆ

ꢀꢀꢅ_{ꢅ[

ꢀꢀꢅ_{ꢀ!

{ꢅ[_{ꢄY

{ꢀ!_{ꢄY

4

Itꢀ_{ꢃꢅ

Itꢀ

ꢂꢂ/_{/[

ꢂꢂ/_{ꢂ!

IꢀꢂL_5ë

1YQ

46

47

{ꢅ[_{ꢃꢅ

{ꢀ!_{ꢃꢅ

IꢀꢂL_5ë

ꢂꢂ/_{/[

0.01uC

1uC

45

33

ꢀꢀꢅ_{ꢅ[

ꢀꢀꢅ_{ꢀ!

{tꢀLC_Lꢄ

Itꢀ_{ꢄY

{tꢀLC

Itꢀ

ꢂꢂ/_{ꢂ!

40

18

ꢄꢅ

500YQ

2^ndmetꢁod to implement Iꢃꢂ

in bypassing Iꢃꢂ_{w/ and

tieing Iꢃꢂ_{ꢅY to 5ë from

IꢂꢀL /onnecotr

ꢅ9ꢅ

!ꢃꢅ

ꢅ9ꢅ

weduces ꢃoꢄer /onsumption

Lf !w/ not used in system

ëꢅꢅ

1uC

44

!ꢃꢅ_hÜÇ

ÇI9ꢃꢂ![ t!ꢀ

Dꢄꢀ

55Q

65lQ

1

65lQ

41

Lmplementation specific.

ꢀay not be needed if {ource

ꢁas implemented

{í!t/th[

L2ꢅ_9ꢄ/tLꢄ

{LD_9ꢄ

7

10

17

20

21

27

36

Dꢄꢀ

ëꢅꢅ

1ꢆ

30

Dꢄꢀ

tꢃ9_{9[

9v_{9[/!0

!1

2YQ

15

L2ꢅ_{ꢅ[

L2ꢅ_{ꢀ!

{ꢅ[_ꢅÇ[

{ꢀ!_ꢅÇ[

16

Çó_Ç9ꢃꢂ_ꢅÇ[

hptional

42

h9

65lQ

h9

65lQ

0.1uC

ëꢀꢀ

22

ë{!ꢀW

ëꢅꢅ

7.06YQ

10uC

0.1uC 0.1uC 0.1uC 0.1uC 0.01uC 0.01uC

1%

0.01uC

10uC

0.1uC

14

24

23

37 48

13 43

ëꢅꢅ

ëꢀꢀ

5 ë Itꢀ Lmplemenꢁaꢁion

5ë

1lQ

5ë

10Q

1lQ

Itꢀ

100Q

Itꢀ_{ꢃꢅ

100lQ

Figure 35. TMDS181 in Sink Side Application (Including 5 V HPD Implementation)

43

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

I5aL/5ëL

/onnector

I5aL wó/{cꢀlꢀr

3ꢂ

34

32

31

2ꢃ

28

26

2ꢂ

2

3

Ça5{_52p

Ça5{_52n

Ça5{_51p

Ça5{_51n

Ça5{_50p

Ça5{_50n

Ça5{_ꢁ[Yp

Ça5{_ꢁ[Yn

Db51

Db52

52p

52n

Lb_52p

Lb_52n

Lb_51p

Lb_51n

Lb_50p

Lb_50n

Lb_ꢁ[Yp

Lb_ꢁ[Yn

hÜÇ_52p

hÜÇ_52n

hÜÇ_51p

hÜÇ_51n

hÜÇ_50p

hÜÇ_50n

hÜÇ_ꢁ[Yp

hÜÇ_ꢁ[Yn

ꢂ

Db53

Db54

Db5ꢂ

Db56

51p

6

51n

8

50p

ꢃ

50n

11

12

Ça5{_ꢁ[Yp

Ça5{_ꢁ[Yn

ꢂë

I5aL_ꢂë

ꢁ!{9_Db51

ꢁ!{9_Db52

ꢁ!{9_Db53

ꢁ!{9_Db54

18

40

4

47YQ

bꢁ

1YQ

38

3ꢃ

55ꢁ_{ꢁ[

55ꢁ_{5!

h9

{ꢁ[_{bY

{5!_{bY

Iꢃꢂ

It5_{wꢁ

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ꢂꢂ/_{/[

ꢂꢂ/_{ꢂ!

hptional

h9

46

47

{ꢁ[_{wꢁ

{5!_{wꢁ

0.01uC

Iꢃꢂ

1uC

4ꢂ

33

ꢂꢂ/_{/[

ꢂꢂ/_{ꢂ!

55ꢁ_{ꢁ[

55ꢁ_{5!

{t5LC_Lb

It5_{bY

{t5LC

It5

500YQ

ꢁ9ꢁ

!wꢁ

ꢁ9ꢁ

weduces ꢃoꢄer /onsumption

Lf !w/ not used in system

ëꢁꢁ

1uC

44

!wꢁ_hÜÇ

ÇI9wa![ t!5

Db5

55Q

65lQ

1

65lQ

41

Lmplementation specific.

ꢀay not be needed if {ource

ꢁas implemented

{í!t/th[

L2ꢁ_9b/tLb

{LD_9b

7

10

17

20

21

27

36

Db5

ëꢁꢁ

1ꢃ

30

Db5

tw9_{9[

9v_{9[/!0

!1

2YQ

1ꢂ

L2ꢁ_{ꢁ[

L2ꢁ_{5!

{ꢁ[_ꢁÇ[

{5!_ꢁÇ[

16

Çó_Ç9wa_ꢁÇ[

hptional

42

h9

65lQ

h9

65lQ

0.1uC

ëꢁꢁ

ë55

22

10uC

0.01uC 0.1uC

ë{!5W

7.06YQ

1%

0.1uC

10uC

0.1uC 0.1uC 0.1uC 0.01uC 0.01uC

14

24

23

37 48

13 43

ëꢁꢁ

ë55

Figure 36. TMDS181 in Sink Side Application

44

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

9.2.3 Application Chain Showing DDC Connections

The DDC circuitry inside the TMDS181 allows multiple stage operation (see Figure 36). The retimer devices can

be connected to any of the bus segments. The number of devices that can be connected in series is limited by

repeater delay/time of flight considerations for the maximum bus speed requirements.

SOURCE

Active Cable

SINK

5 V

3.3 V

5 V

3.3 V

RUPsource

Rup Rup

RUPsink

SLK_SRC SLK_SINK

SLK_SINK

SLK_SRC

RSLK

SLK_SRC SLK_SINK

TSCL

TSDA

SDA_SRC

SDA_SRC SDA_SINK

SDA_SINK

RSDA

SDA_SRCSDA_SINK

C1

C3

C2

C1

C2

BUS

SLAVE

BUS

MASTER

TMDS181

Figure 37. Typical Series Application

9.2.3.1 Detailed Design Procedure

9.2.3.1.1 DDC Pullup Resistors

NOTE

This section is informational only and subject to change depending upon the specific

system implementation.

The pullup resistor value is determined by two requirements.

1. The maximum sink current of the I²C buffer: The maximum sink current is 3 mA or slightly higher for an I²C driver

supporting standard-mode I²C operation.

V_CC

R_{up(m in)}

=

I_{sin k}

(1)

2. The maximum transition time on the bus: The maximum transition time, T, of an I²C bus is set by an RC time constant.

The parameter, k, can be calculated from Equation 3 by solving for t, the times at which certain voltage thresholds are

reached. Different input threshold combinations introduce different values of t. Table 10 summarizes the possible values

of k under different threshold combinations.

T = k × RC

where

•

R is the pullup resistor value.

C is the total load capacitance.

(2)

(3)

œ t

V(t) = V_DDì (1 œ e ^RC

)

45

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Table 10. Value k upon Different Input Threshold Voltages

Vth–\Vth+

0.1VCC

0.7VCC

1.0986

1.0415

0.9808

0.9163

0.8473

0.65VCC

0.9445

0.8873

0.8267

0.7621

0.6931

0.6VCC

0.8109

0.7538

0.6931

0.6286

0.5596

0.55VCC

0.6931

0.6360

0.5754

0.5108

0.4418

0.5VCC

0.5878

0.5306

0.4700

0.4055

0.3365

0.45VCC

0.4925

0.4353

0.3747

0.3102

0.2412

0.4VCC

0.4055

0.3483

0.2877

0.2231

0.1542

0.35VCC

0.3254

0.2683

0.2076

0.1431

0.0741

0.3VCC

0.2513

0.1942

0.1335

0.0690

0.15VCC

0.2VCC

0.25VCC

0.3VCC

From Equation 1, R_up(min)= 5.5 V / 3 mA = 1.83 kΩ to operate the bus under a 5 V pullup voltage and provide <3

mA when the I²C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is allowed,

R_up(min)can be as low as 1.375 kΩ. If DDC working at standard mode of 100 Kbps, the maximum transition time

T is fixed, 1 μs, and using the k values from Table 10, the recommended maximum total resistance of the pullup

resistors on an I²C bus can be calculated for different system setups. If DDC working in fast mode of 400 Kbps,

the transition time should be set at 300 ns according to I²C specification. To support the maximum load

capacitance specified in the HDMI specification, calculate Ccable(max) = 700 pF / Csource = 50 pF / Ci = 50 pF,

R(max) as shown in Table 11.

Table 11. Pullup Resistor Upon Different Threshold Voltages and 800 pF Loads

Vth-\Vth+

0.1VCC

0.15VCC

0.2VCC

0.25VCC

0.3VCC

0.7VCC

1.14

1.2

0.65VCC

1.32

0.6VCC

1.54

1.66

1.8

0.55VCC

1.8

0.5VCC

2.13

0.45VCC

2.54

0.4VCC

3.08

3.59

4.35

5.6

0.35VCC

3.84

0.3VCC

4.97

6.44

9.36

18.12

—

UNIT

kΩ

1.41

1.97

2.36

2.87

4.66

kΩ

1.27

1.36

1.48

1.51

2.17

2.66

3.34

6.02

kΩ

1.64

1.99

2.23

2.45

3.08

4.03

8.74

kΩ

1.8

2.83

3.72

5.18

8.11

16.87

kΩ

To accommodate the 3-mA drive current specification, a narrower threshold voltage range is required to support

a maximum 800-pF load capacitance for a standard-mode I²C bus.

9.2.3.1.2 Compliance Testing

Compliance testing is very system design specific. Properly designing the system and configuring the TMDS181

can help pass compliance for a system. The following information is a starting point to help prepare for

compliance testing. As each system is different there are many features in the TMDS181 to help tune the circuit.

These include fixed RX equalization, adaptive RX equalization, V_ODadjust by several methods, pre-emphasis/de-

emphasis, and source termination. Passing both HDMI2.0a and HDMI1.4b compliance is easier to accomplish

when using I²C as this provides more fine tuning capability.

9.2.3.1.2.1 Pin Strapping Configuration for HDMI2.0a and HDMI1.4b

•

VSADJ Resistor = 7.06 kΩ: Note: This value may be changed in order to improve Intra-pair skew margin but

will increase output V_ODso care must be taken to avoid V_ODand V_Lcompliance issues.

•

PRE_SEL = L for -2 dB (For Intra-pair Skew)

TX_TERM_CTL = NC for Auto Select.

9.2.3.1.2.2 I²C Control for HDMI2.0a and HDMI1.4b

•

VSADJ Resistor = 7.06 kΩ: This value may be changed in order to improve Intra-pair skew but will increase

V_ODso care must be taken to avoid V_ODand V_Lcompliance issues. The V_ODcan be increased or decreased

by using I²C Reg0Ch[7:2]

•

PRE_SEL = Reg0Ch[1:0] = 01 for -2 dB (Labeled HDMI_TWPST)

TX_TERM_CTL = NC for Auto Select.

–

Reg0Bh[4:3] = 00 → No TX Term; HDMI1.4b < 2 Gbps (This may be best value for all HDMI1.4b)

Reg0Bh[4:3] = 01 → 150 Ω to 300 Ω; HDMI1.4b > 2 Gbps

Reg0Bh[4:3] = 11 → 75 Ω to 150 Ω; HDMI2.0a

46

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

10 Power Supply Recommendations

To minimize the power consumption of customer application, TMSD181 used the dual power supply. V_CCis 3.3 V

with 5% range to support the I/O voltage. V_DDis 1.2 V to supply the internal digital control circuit. TMDS181

operates in three different working states.

•

Power-down mode:

–

OE = Low puts the device into its lowest power state by shutting down all function blocks.

–

When OE is reasserted, the transitions from L → H create a reset, and if the device is programmed

through I²C, it must be reprogrammed.

–

Writing a 1 to register 09h[3].

OE = High, HPD_SNK = Low

•

Standby mode: HPD_SNK = High, but no valid clock signal detect on clock lane.

Normal operation: Working in redriver or retimer

When HPD asserts, the device CDR and output enables based on the signal detector circuit result.

HPD_SRC = HPD_SNK in all conditions. The HPD channel is operational when V_CCis over 3 V.

NOTE

1. When the TMDS181 is put into a power-down state, the I²C registers are cleared. This is

important as the TMDS_CLOCK_RATIO_STATUS bit will be cleared. If cleared and HDMI2.0

resolutions are to be supported, the TMDS181 expects the source to write a 1 to this bit

location. If this does not happen, the PLL will not be set properly and no video may be evident.

2. Power performance of the TMDS181 is highly dependent upon the HDMI transmitter

architecture driving the TMDS181 receiver. The TMDS181 has integrated the termination

resistors, which increases the power consumption on the 3.3 V rail by as much as 400 mW.

This is the power required by the HDMI transmitter to switch and not needed by the TMDS181

to operate properly.

Table 12. Power-Up and Operation Timing Requirements

INPUTS

SIG_EN

STATUS

DATA

RATE

OUT_Dx

OUT_CLK

HPD_SNK OE

IN_CLK

HPD_SRC

IN_Dx

SDA/SCL_CTL

DDC

ARC

MODE

X

L

H or L

X

H

L

RX Termination On

Disable

Active

High-Z

Disabled

Disable

Power-down mode

H

Power-down mode

by W 1 to 09h[3]

H

H or L

X

H

RX Termination On

Active

High-Z

Disabled

Active

Disable

Active

H

D0-D2 disabled

with RX termination

On, IN_CLK active

No valid

TMDS clock

Standby mode

(squelch waiting)

(no valid

signal)

H or L

(no valid

signal)

D0-D2 disabled

with RX termination

On, IN_CLK activee

No valid

TMDS clock

Retimer

mode

Standby mode

(Squelch waiting)

H

Active

High-Z

Active

H

Valid TMDS

clock

Retimer

mode

(Valid

signal)

RX active

TX active

Normal operation

L

No valid

TMDS clock

Redriver

mode

(no valid

signal)

H

Valid TMDS

clock

Redriver

mode

(Valid

signal)

47

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

For the TMDS181 on a high-K board: It is required to solder the PowerPAD™ onto the thermal land to ground.

A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the

TMDS181 can operate over the full temperature range by soldering the PowerPAD onto the thermal land.

On a low-K board: For the device to operate across the temperature range on a low-K board, the designer must

use a 1-oz Cu trace connecting the GND pins to the thermal land. A simulation shows R_θJA= 100.84°C/W

allowing 545 mW power dissipation at 70°C ambient temperature. A general PCB design guide for PowerPAD

packages is provided in PowerPAD Thermally Enhanced Package, SLMA002. TI recommends using at a

minimum a four-layer stack to accomplish a low-EMI PCB design. TI recommends six layers as the TMDS181 is

a two-voltage-rail device.

•

Routing the high-speed TMDS traces on the top layer avoids the use of vias (and their discontinuities) and

allows for clean interconnects from the HDMI connectors to the retimer inputs and outputs. It is important to

match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew.

•

Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for

transmission link interconnects and provides an excellent low-inductance path for the return current flow.

•

Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.

Routing slower-speed control signals on the bottom layer allows for greater flexibility because these signal

links usually have margin to tolerate discontinuities such as vias.

•

If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to

the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also, the

power and ground plane of each power system can be placed closer together, thus increasing the high-

frequency bypass capacitance significantly.

Layer 1: TMDS signal layer

5 to 10 mils

20 to 40 mils

5 to 10 mils

Layer 2: Ground Plane

Layer 3: V_CCPower Plane

Layer 4: V_DDPower Plane

Layer 5: Ground Plane

Layer 3: Power Plane

Layer 4: Control signal layer

Layer 6: Control signal layer

Figure 38. Recommended 4- or 6-Layer PCB Stack

48

TMDS181, TMDS181I

www.ti.com.cn

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

11.2 Layout Example

1µC

!ꢄ/_ꢆÜÇ

ꢀꢀQ

Db5

1µC

{ꢁ5LC_Lb

{5!_{bY

{/[_{ꢄ/

2kQ

ë_//

2kQ

ꢀë

2kQ

ë_//

ꢀë

{5!_{ꢄ/

{/[_{bY

aꢂtch Iigh {peed trꢂces

length ꢂs close ꢂs possiꢃle to

minimize {kew

6ꢀkQ

ë_//

{í!ꢁꢅꢁꢆ[

6ꢀkQ

Db5

6ꢀkQ

ë_//

Çó_Ç9ꢄa_/Ç[

1

6ꢀkQ

Db5

Lb_52pꢅn

ꢆÜÇ_52pꢅn

Iꢁ5_{bY

Iꢁ5_{ꢄ/

Lb_51pꢅn

ꢆÜÇ_51pꢅn

Db5

Lb_50pꢅn

ꢆÜÇ_50pꢅn

6ꢀkQ

ë_//

6ꢀkQ

ë_//

!1

L2/_9bꢅꢁLb

6ꢀkQ

Db5

6ꢀkQ

Db5

ꢆÜÇ_/[Ypꢅn

Lb_/[Ypꢅn

{/[_/Ç[

ꢁlꢂce ë_//ꢂnd ë₅₅decoupling

cꢂps ꢂs close to ë_//ꢂnd ë₅₅

pins ꢂs possiꢃle

ë_//

2kQ

ë{!5W

{5!_/Ç[

aꢂtch Iigh {peed trꢂces

length ꢂs close ꢂs possiꢃle to

minimize {kew

A. If ARC is not used, tie a 500 kΩ resistor to GND at the SPDIF_IN pin.

B. The 55 Ω resistor to GND on the ARC_OUT pin is implementation specific and may not be needed if it is already

implemented elsewhere.

Figure 39. Layout Example – Source Side

49

TMDS181, TMDS181I

ZHCSE70D –AUGUST 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

本节标识的文档均在本规范中引用。为简化文本，文中的大多数参考文献均用文档标签 [文档标签] 标识，而不使用

完整的文档标题。

1. [HDMI] 高清多媒体接口规范版本 1.4b，2011 年 10 月

2. [HDMI] 高清多媒体接口规范版本 2.0a，2015 年 3 月

3. [HDMI] 高清多媒体接口 CTS 版本 1.4b，2011 年 10 月

4. [HDMI] 高清多媒体接口 CTS 版本 2.0k，2015 年 6 月

5. [I²C] I²C 总线规范版本 2.1，2000 年 1 月

12.2 相关链接

下面的表格列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的

快速链接。

表 13. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具和软件

请单击此处

支持和社区

请单击此处

TMDS181

TMDS181I

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

PowerPAD, E2E are trademarks of Texas Instruments.

Blu-Ray, Blu-ray are trademarks of Blu-ray Disc Association.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

50

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1 MAX

C

SEATING PLANE

0.05

0.00

0.08 C

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

2X

5.5

0.30

0.18

36

48X

1

0.1

0.05

C B A

48

37

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

49

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

12

25

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

49

(R0.05) TYP

(6.8)

9X

METAL

TYP

(

1.17)

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMDS181
厂家：	TEXAS INSTRUMENTS
描述：	6Gbps HDMI 2.0 TMDS 重定时器
文件：	总59页 (文件大小：2474K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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