TMP101NA250G4 [TI]

Digital Temperature Sensor with I2C Interface;


型号：	TMP101NA250G4
厂家：	TEXAS INSTRUMENTS
描述：	Digital Temperature Sensor with I2C Interface
文件：	总19页 (文件大小：761K)
中文：	中文翻译
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TMP100

TMP101

SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

Digital Temperature Sensor

with I Ct Interface

F_DEATURES

DESCRIPTION

The TMP100 and TMP101 are two-wire, serial output

temperature sensors available in SOT23-6 packages.

Requiring no external components, the TMP100 and

TMP101 are capable of reading temperatures with a

resolution of 0.0625°C.

DIGITAL OUTPUT: I C Serial 2-Wire

RESOLUTION: 9- to 12-Bits, User-Selectable

ACCURACY:

2.0°C from −25°C to +85°C (max)

3.0°C from −55°C to +125°C (max)

LOW QUIESCENT CURRENT:

45µA, 0.1µA Standby

The TMP100 and TMP101 feature SMBus and I C

interface compatibility, with the TMP100 allowing up to

eight devices on one bus. The TMP101 offers SMBus alert

function with up to three devices per bus.

WIDE SUPPLY RANGE: 2.7V to 5.5V

TINY SOT23-6 PACKAGE

The TMP100 and TMP101 are ideal for extended

temperature measurement in a variety of communication,

computer, consumer, environmental, industrial, and

instrumentation applications.

A_DPPLICATIONS

POWER-SUPPLY TEMPERATURE

MONITORING

COMPUTER PERIPHERAL THERMAL

PROTECTION

The TMP100 and TMP101 are specified for operation over

a temperature range of −55°C to +125°C.

NOTEBOOK COMPUTERS

CELL PHONES

BATTERY MANAGEMENT

OFFICE MACHINES

THERMOSTAT CONTROLS

ENVIRONMENTAL MONITORING AND HVAC

ELECTROMECHANICAL DEVICE

TEMPERATURE

Temperature

Diode

Temperature

Diode

Control

Logic

Control

Logic

Te mp.

Sensor

Temp.

Sensor

SCL

SDA

ADD0

V+

SCL

SDA

ADD0

V+

∆Σ

A/D

Converter

∆Σ

A/D

Converter

Serial

Interface

Serial

Interface

GND

Config

and Temp

Config

and Temp

ADD1

ALERT

OSC

TMP100

TMP101

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

I C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners.

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

(1)

ABSOLUTE MAXIMUM RATINGS

Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V

handledwith appropriate precautions. Failure to observe

(2)

proper handling and installation procedures can cause damage.

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.5V

Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +150°C

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

Junction Temperature (T max) . . . . . . . . . . . . . . . . . . . . . . +150°C

ESD Rating, Human Body Model . . . . . . . . . . . . . . . . . . . . . 2000V

Machine Model . . . . . . . . . . . . . . . . . . . . . . . 200V

(1)

(2)

Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

Input voltage rating applies to all TMP100 and TMP101 input

voltages.

(1)

ORDERING INFORMATION

PRODUCT

PACKAGE-LEAD

SOT23-6

PACKAGE DESIGNATOR

PACKAGE MARKING

TMP100

DBV

T100

T101

TMP101

SOT23-6

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site

at www.ti.com.

PIN CONFIGURATION

Top View

SOT23 Top View

SOT23

SCL

SDA

ADD0

V+

SCL

GND

SDA

ADD0

V+

GND

ALERT

ADD1

TMP100

TMP101

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

ELECTRICAL CHARACTERISTICS

At T = −55°C to +125°C and V+ = 2.7V to 5.5V, unless otherwise noted.

TMP100, TMP101

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

TEMPERATURE INPUT

Range

−55

+125

2.0

°C

Accuracy (temperature error)

−25°C to +85°C

−55°C to +125°C

Selectable

0.5

1.0

3.0

Resolution

0.0625

DIGITAL INPUT/OUTPUT

Input Logic Levels:

0.7(V+)

−0.5

6.0

0.3(V+)

Input Current, I

0V ≤ V ≤ 6V

µA

Output Logic Levels:

SDA

= 3mA

= 4mA

0.15

9 to 12

0.4

ALERT

Resolution

Selectable

9-Bit

Bits

s/s

Conversion Time

10-Bit

11-Bit

12-Bit

9-Bit

150

300

600

160

320

Conversion Rate

10-Bit

11-Bit

12-Bit

POWER SUPPLY

Operating Range

Quiescent Current

2.7

5.5

Serial Bus Inactive

µA

Serial Bus Active, SCL Frequency = 400kHz

Serial Bus Active, SCL Frequency = 3.4MHz

Serial Bus Inactive

150

0.1

Shutdown Current

Serial Bus Active, SCL Frequency = 400kHz

Serial Bus Active, SCL Frequency = 3.4MHz

100

TEMPERATURE RANGE

Specified Range

−55

−60

+125

+150

°C

Storage Range

Thermal Resistance

SOT23-6 Surface-Mount

200

°C/W

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

TYPICAL CHARACTERISTICS

At T = +25°C and V+ = 5.0V, unless otherwise noted.

QUIESCENT CURRENT vs TEMPERATURE

SHUTDOWN CURRENT vs TEMPERATURE

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V+ = 5V

V+ = 2.7V

Serial Bus Inactive

−

0.1

−

40 20

80 100 120 140

Temperature ( C)

CONVERSION TIME vs TEMPERATURE

TEMPERATURE ACCURACY vs TEMPERATURE

400

2.0

1.5

1.0

0.5

0.0

350

300

250

V+ = 5V

−

0.5

1.0

1.5

2.0

V+ = 2.7V

−

NOTE: 12−bit resolution.

3 Typical Units

−

40 20

80 100 120 140

Temperature ( C)

QUIESCENT CURRENT WITH

BUS ACTIVITY vs TEMPERATURE

180

160

140

120

100

125 C

25 C

125 C

25 C

−

55 C

−

55 C

FAST MODE

10k

Hs MODE

100k

10M

SCL Frequency (Hz)

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To maintain the accuracy in applications requiring air or

surface temperature measurement, care should be taken

to isolate the package and leads from ambient air

temperature. A thermally-conductive adhesive will assist

in achieving accurate surface temperature measurement.

APPLICATIONS INFORMATION

The TMP100 and TMP101 are digital temperature sensors

optimal for thermal management and thermal protection

applications. The TMP100 and TMP101 are I²C and

SMBus interface-compatible and are specified over a

temperature range of −55°C to +125°C.

POINTER REGISTER

The TMP100 and TMP101 require no external

components for operation except for pull-up resistors on

SCL, SDA, and ALERT, although a 0.1µF bypass

capacitor is recommended, as shown in Figure 1 and

Figure 2.

Figure 3 shows the internal register structure of the

TMP100 and TMP101. The 8-bit Pointer Register of the

TMP100 and TMP101 is used to address a given data

identify which of the data registers should respond to a

read or write command. Table 1 identifies the bits of the

Pointer Register byte. Table 2 describes the pointer

address of the registers available in the TMP100 and

TMP101. Power-up Reset value of P1/P0 is 00.

V+

0.1 F

Pointer

ALERT

(Output)

SCL

SDA

To I²C

Controller

TMP101

ADD0

(Input)

Temperature

NOTE: (1) SCL, SDA and ALERT

require pull−up resistors for

I²C bus applications.

SCL

Configuration

I/O

GND

Control

Interface

T_LOW

Figure 1. Typical Connections of the TMP101

SDA

V+

T_HIGH

0.1 F

Figure 3. Internal Register Structure of the

TMP100 and TMP101

ADD1

(Input)

SCL

SDA

To I²C

Controller

Table 1. Pointer Register Type

TMP100

ADD0

(Input)

NOTE: (1) SCL and SDA

require pull−up resistors for

I²C bus applications.

Table 2. Pointer Addresses of the TMP100 and

TMP101 Registers

GND

TemperatureRegister (READ Only)

Configuration Register (READ/WRITE)

Figure 2. Typical Connections of the TMP100

LOW

HIGH

The die flag of the lead frame is connected to pin 2. The

sensing device of the TMP100 and TMP101 is the chip

itself. Thermal paths run through the package leads as well

as the plastic package. The lower thermal resistance of

metal causes the leads to provide the primary thermal

path. The GND pin of the TMP100 or TMP101 is directly

connected to the metal lead frame, and is the best choice

for thermal input.

TEMPERATURE REGISTER

The Temperature Register of the TMP100 or TMP101 is a

12-bit read-only register that stores the output of the most

recent conversion. Two bytes must be read to obtain data

and are described in Table 3 and Table 4. The first 12 bits

are used to indicate temperature with all remaining bits

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

equal to zero. Data format for temperature is summarized

in Table 5. Following power-up or reset, the Temperature

the SD bit is 1. The device will shutdown once the current

conversion is completed. For SD equal to 0, the device will

maintain continuous conversion.

Table 3. Byte 1 of Temperature Register

THERMOSTAT MODE (TM)

The Thermostat Mode bit of the TMP101 indicates to the

device whether to operate in Comparator Mode (TM = 0)

or Interrupt Mode (TM = 1). For more information on

comparator and interrupt modes, see the HIGH and LOW

Limit Registers section.

T11

T10

Table 4. Byte 2 of Temperature Register

POLARITY (POL)

The Polarity Bit of the TMP101 allows the user to adjust the

polarity of the ALERT pin output. If POL = 0, the ALERT pin

will be active LOW, as shown in Figure 4. For POL = 1 the

ALERT pin will be active HIGH, and the state of the ALERT

pin is inverted.

Table 5. Temperature Data Format

TEMPERATURE

DIGITAL OUTPUT

(BINARY)

(°C)

HEX

128

127.9375

100

0111 1111 1111

0110 0100 0000

0101 0000 0000

0100 1011 0000

0011 0010 0000

0001 1001 0000

0000 0000 0100

0000 0000 0000

1111 1111 1100

1110 0111 0000

1100 1001 0000

1000 0000 0000

7FF

640

500

4B0

320

190

004

000

FFC

E70

C90

800

0.25

0.0

−0.25

−25

−55

−128

T_HIGH

Measured

Temperature

T_LOW

TMP101 ALERT PIN

(Comparator Mode)

POL = 0

The user can obtain 9, 10, 11, or 12 bits of resolution by

addressing the Configuration Register and setting the

resolution bits accordingly. For 9-, 10-, or 11-bit resolution,

the most significant bits in the Temperature Register are

used with the unused LSBs set to zero.

TMP101 ALERT PIN

(Interrupt Mode)

POL = 0

TMP101 ALERT PIN

(Comparator Mode)

POL = 1

TMP101 ALERT PIN

(Interrupt Mode)

POL = 1

CONFIGURATION REGISTER

The Configuration Register is an 8-bit read/write register

used to store bits that control the operational modes of the

temperature sensor. Read/write operations are performed

MSB first. The format of the Configuration Register for the

TMP100 and TMP101 is shown in Table 6, followed by a

breakdown of the register bits. The power-up/reset value

of the Configuration Register is all bits equal to 0. The

OS/ALERT bit will read as 1 after power-up/reset.

Read

Time

Read

Figure 4. Output Transfer Function Diagrams

FAULT QUEUE (F1/F0)

A fault condition occurs when the measured temperature

exceeds the user-defined limits set in the T_HIGHand T_LOW

Registers. Additionally, the number of fault conditions

required to generate an alert may be programmed using

the Fault Queue. The Fault Queue is provided to prevent

a false alert due to environmental noise. The Fault Queue

requires consecutive fault measurements in order to

trigger the alert function. If the temperature falls below

Table 6. Configuration Register Format

BYTE

OS/ALERT

POL

SHUTDOWN MODE (SD)

The Shutdown Mode of the TMP100 and TMP101 allows

the user to save maximum power by shutting down all

device circuitry other than the serial interface, which

reduces current consumption to less than 1µA. For the

TMP100 and TMP101, Shutdown Mode is enabled when

T_LOW, prior to reaching the number of programmed

consecutive faults limit, the count is reset to 0. Table 7

defines the number of measured faults that may be

programmed to trigger an alert condition in the device.

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

Table 7. Fault Settings of the TMP100 and

TMP101

In Interrupt Mode (TM = 1) the ALERT Pin becomes active

when the temperature equals or exceeds T_HIGHfor a

consecutive number of fault conditions. The ALERT pin

remains active until a read operation of any register occurs

or the device successfully responds to the SMBus Alert

Response Address. The ALERT pin will also be cleared if

the device is placed in Shutdown Mode. Once the ALERT

pin is cleared, it will only become active again by the

temperature falling below T_LOW. When the temperature

falls below T_LOW, the ALERT pin will become active and

remain active until cleared by a read operation of any

Response Address. Once the ALERT pin is cleared, the

above cycle will repeat with the ALERT pin becoming

CONSECUTIVE FAULTS

CONVERTER RESOLUTION (R1/R0)

The Converter Resolution Bits control the resolution of the

internal Analog-to-Digital (A/D) converter. This allows the

user to maximize efficiency by programming for higher

resolution or faster conversion time. Table 8 identifies the

Resolution Bits and relationship between resolution and

conversion time.

active when the temperature equals or exceeds T_HIGH

The ALERT pin can also be cleared by resetting the device

with the General Call Reset command. This will also clear

the state of the internal registers in the device returning the

device to Comparator Mode (TM = 0).

Table 8. Resolution of the TMP100 and TMP101

CONVERSION TIME

(typical)

RESOLUTION

9 Bits (0.5°C)

40ms

Both operational modes are represented in Figure 4.

Table 9 and Table 10 describe the format for the T_HIGHand

T_LOWregisters. Power-up Reset values for T_HIGHand

10 Bits (0.25°C)

11 Bits (0.125°C)

12 Bits (0.0625°C)

80ms

160ms

320ms

T_LOWare: T_HIGH= 80°C and T_LOW= 75°C. The format of

the data for T_HIGHand T_LOWis the same as for the

Temperature Register.

OS/ALERT (OS)

The TMP100 and TMP101 feature

One-Shot

Temperature Measurement Mode. When the device is in

Shutdown Mode, writing a 1 to the OS/ALERT bit will start

a single temperature conversion. The device will return to

the shutdown state at the completion of the single

conversion. This is useful to reduce power consumption in

the TMP100 and TMP101 when continuous monitoring of

temperature is not required.

Table 9. Bytes 1 and 2 of T

HIGH

BYTE

H11

H10

BYTE

Table 10. Bytes 1 and 2 of T

LOW

Reading the OS/ALERT bit will provide information about

the Comparator Mode status. The state of the POL bit will

invert the polarity of data returned from the OS/ALERT bit.

For POL = 0, the OS/ALERT will read as 1 until the

temperature equals or exceeds T_HIGHfor the programmed

number of consecutive faults, causing the OS/ALERT bit

to read as 0. The OS/ALERT bit will continue to read as 0

until the temperature falls below T_LOWfor the programmed

number of consecutive faults when it will again read as 1.

The status of the TM bit does not affect the status of the

OS/ALERT bit.

BYTE

L11

L10

BYTE

All 12 bits for the Temperature, T_HIGH, and T_LOWregisters

are used in the comparisons for the ALERT function for all

converter resolutions. The three LSBs in T_HIGHand T_LOW

can affect the ALERT output even if the converter is

configured for 9-bit resolution.

SERIAL INTERFACE

HIGH AND LOW LIMIT REGISTERS

The TMP100 and TMP101 operate only as slave devices

on the I²C bus and SMBus. Connections to the bus are

made via the open-drain I/O lines SDA and SCL. The

TMP100 and TMP101 support the transmission protocol

for fast (up to 400kHz) and high-speed (up to 3.4MHz)

modes. All data bytes are transmitted most significant bit

first.

In Comparator Mode (TM = 0), the ALERT pin of the

TMP101 becomes active when the temperature equals or

exceeds the value in T_HIGHand generates a consecutive

number of faults according to fault bits F1 and F0. The

ALERT pin will remain active until the temperature falls

below the indicated T_LOWvalue for the same number of

faults.

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Data transfer is then initiated and sent over eight clock

pulses followed by an Acknowledge Bit. During data

transfer SDA must remain stable while SCL is HIGH, as

any change in SDA while SCL is HIGH will be interpreted

as a control signal.

SERIAL BUS ADDRESS

To program the TMP100 and TMP101, the master must

first address slave devices via a slave address byte. The

slave address byte consists of seven address bits, and a

direction bit indicating the intent of executing a read or

write operation.

Once all data have been transferred, the master generates

a STOP condition indicated by pulling SDA from LOW to

HIGH, while SCL is HIGH.

The TMP100 features two address pins to allow up to eight

devices to be addressed on a single I²C interface. Table 11

describes the pin logic levels used to properly connect up

to eight devices. Float indicates the pin is left unconnected.

The state of pins ADD0 and ADD1 is sampled on the first

I²C bus communication and should be set prior to any

activity on the interface.

WRITING/READING TO THE TMP100 AND

TMP101

Accessing a particular register on the TMP100 and

TMP101 is accomplished by writing the appropriate value

to the Pointer Register. The value for the Pointer Register

is the first byte transferred after the I²C slave address byte

with the R/W bit LOW. Every write operation to the

TMP100 and TMP101 requires a value for the Pointer

Table 11. Address Pins and Slave Addresses for

the TMP100

ADD1

ADD0

SLAVE ADDRESS

1001000

1001001

1001010

1001100

1001101

1001110

1001011

1001111

When reading from the TMP100 and TMP101, the last

value stored in the Pointer Register by a write operation is

used to determine which register is read by a read

operation. To change the register pointer for a read

operation, a new value must be written to the Pointer

address byte with the R/W bit LOW, followed by the Pointer

can then generate a START condition and send the I²C

slave address byte with the R/W bit HIGH to initiate the

read command. See Figure 7 for details of this sequence.

If repeated reads from the same register are desired, it is

not necessary to continually send the Pointer Register

bytes as the TMP100 and TMP101 will remember the

Pointer Register value until it is changed by the next write

operation.

Float

The TMP101 features one address pin and an ALERT pin,

allowing up to three devices to be connected per bus. Pin

logic levels are described in Table 12. The address pins of

the TMP100 and TMP101 are read after reset or in

response to an I²C address acquire request. Following

reading, the state of the address pins is latched to

minimize power dissipation associated with detection.

Table 12. Address Pins and Slave Addresses for

the TMP101

SLAVE MODE OPERATIONS

The TMP100 and TMP101 can operate as slave receivers

or slave transmitters.

ADD0

SLAVE ADDRESS

Float

1001000

1001001

1001010

Slave Receiver Mode:

The first byte transmitted by the master is the slave

address, with the R/W bit LOW. The TMP100 or TMP101

then acknowledges reception of a valid address. The next

byte transmitted by the master is the Pointer Register. The

TMP100 or TMP101 then acknowledges reception of the

Pointer Register byte. The next byte or bytes are written to

the register addressed by the Pointer Register. The

TMP100 and TMP101 will acknowledge reception of each

data byte. The master may terminate data transfer by

generating a START or STOP condition.

BUS OVERVIEW

The device that initiates the transfer is called a master, and

the devices controlled by the master are slaves. The bus

must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates

the START and STOP conditions.

To address a specific device, a START condition is

initiated, indicated by pulling the data-line (SDA) from a

HIGH to LOW logic level while SCL is HIGH. All slaves on

the bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended.

During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge

and pulling SDA LOW.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave

address, with the R/W bit HIGH. The slave acknowledges

reception of a valid slave address. The next byte is

transmitted by the slave and is the most significant byte of

the register indicated by the Pointer Register. The master

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SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The

master acknowledges reception of the data byte. The

master may terminate data transfer by generating a

Not-Acknowledge on reception of any data byte, or

generating a START or STOP condition.

GENERAL CALL

The TMP100 and TMP101 respond to the I²C General Call

address (0000000) if the eighth bit is 0. The device will

acknowledge the General Call address and respond to

commands in the second byte. If the second byte is

00000100, the TMP100 and TMP101 will latch the status

of their address pins, but will not reset. If the second byte

is 00000110, the TMP100 and TMP101 will latch the status

of their address pins and reset their internal registers.

SMBus ALERT FUNCTION

The TMP101 supports the SMBus Alert function. When

the TMP101 is operating in Interrupt Mode (TM = 1), the

ALERT pin of the TMP101 may be connected as an

SMBus Alert signal. When a master senses that an ALERT

condition is present on the ALERT line, the master sends

an SMBus Alert command (00011001) on the bus. If the

ALERT pin of the TMP101 is active, the TMP101 will

acknowledge the SMBus Alert command and respond by

returning its slave address on the SDA line. The eighth bit

(LSB) of the slave address byte will indicate if the

temperature exceeding T_HIGHor falling below T_LOW

caused the ALERT condition. For POL = 0, this bit will be

POR (POWER-ON RESET)

The TMP100 and TMP101 both have on-chip power-on

reset circuits that reset the device to default settings when

the device is powered on. This circuit activates when the

power supply is less than 0.3V for more than 100ms. If the

TMP100 and TMP101 are powered down by removing

supply voltage from the device, but the supply voltage is

not assured to be less than 0.3V, it is recommended to

issue a General Call reset command on the I²C interface

bus to ensure that the TMP100 and TMP101 are

completely reset.

LOW if the temperature is greater than or equal to T_HIGH

This bit will be HIGH if the temperature is less than T_LOW

The polarity of this bit will be inverted if POL = 1. Refer to

Figure 8 for details of this sequence.

HIGH-SPEED MODE

In order for the I²C bus to operate at frequencies above

400kHz, the master device must issue an Hs-mode master

code (00001XXX) as the first byte after a START condition

to switch the bus to high-speed operation. The TMP100

and TMP101 will not acknowledge this byte as required by

the I²C specification, but will switch their input filters on

SDA and SCL and their output filters on SDA to operate in

Hs-mode, allowing transfers at up to 3.4MHz. After the

Hs-mode master code has been issued, the master will

transmit an I²C slave address to initiate a data transfer

operation. The bus will continue to operate in Hs-mode

until a STOP condition occurs on the bus. Upon receiving

the STOP condition, the TMP100 and TMP101 will switch

their input and output filters back to fast-mode operation.

If multiple devices on the bus respond to the SMBus Alert

command, arbitration during the slave address portion of

the SMBus alert command will determine which device will

clear its ALERT status. If the TMP101 wins the arbitration,

its ALERT pin will become inactive at the completion of the

SMBus Alert command. If the TMP101 loses the

arbitration, its ALERT pin will remain active.

The TMP100 will also respond to the SMBus ALERT

command if its TM bit is set to 1. Since it does not have an

ALERT pin, the master needs to periodically poll the

device by issuing an SMBus Alert command. If the

TMP100 has generated an ALERT, it will acknowledge the

SMBus Alert command and return its slave address in the

next byte.

ꢆ ꢠ ꢀꢡ ꢢ ꢢ

ꢆ ꢠ ꢀꢡ ꢢ ꢡ

www.ti.com

SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not limited and

is determined by the master device. The receiver

acknowledges the transfer of data.

TIMING DIAGRAMS

The TMP100 and TMP101 are I²C and SMBus

compatible. Figure 5 to Figure 8 describe the various

operations on the TMP100 and TMP101. Bus definitions

are given below. Parameters for Figure 5 are defined in

Table 13.

Acknowledge: Each receiving device, when addressed,

is obliged to generate an Acknowledge bit. A device that

acknowledges must pull down the SDA line during the

Acknowledge clock pulse in such a way that the SDA line

is stable LOW during the HIGH period of the Acknowledge

clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data

transfer can be signaled by the master generating a

Not-Acknowledge on the last byte that has been

transmitted by the slave.

Bus Idle: Both SDA and SCL lines remain HIGH.

Start Data Transfer: A change in the state of the SDA line,

from HIGH to LOW, while the SCL line is HIGH, defines a

START condition. Each data transfer is initiated with a

START condition.

Stop Data Transfer: A change in the state of the SDA line

from LOW to HIGH while the SCL line is HIGH defines a

STOP condition. Each data transfer is terminated with a

repeated START or STOP condition.

Table 13. Timing Diagram Definitions

FAST MODE

HIGH-SPEED MODE

PARAMETER

UNITS

MIN

MAX

MIN

MAX

SCLK Operating Frequency

0.4

3.4

MHz

(SCLK)

Bus Free TIme Between STOP and START Conditions

600

160

(BUF)

Hold time after repeated START condition.

After this period, the first clock is generated.

(HDSTA)

Repeated START Condition Setup Time

STOP Condition Setup Time

Data HOLD Time

600

160

(SUSTA)

(SUSTO)

(HDDAT)

Data Setup Time

100

1300

600

(SUDAT)

SCLK Clock LOW Period

SCLK Clock HIGH Period

Clock/Data Fall Time

160

(LOW)

(HIGH)

300

160

Clock/Data Rise Time

for SCLK ≤ 100kHz

1000

ꢆꢠ ꢀ ꢡꢢ ꢢ

ꢆꢠ ꢀ ꢡꢢ ꢡ

www.ti.com

SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

I C TIMING DIAGRAMS

t_(LOW)

t_F

t_R

t_(HDSTA)

SCL

t_(SUSTO)

t_(HDSTA)

t_(HIGH)t_(SUSTA)

t_(HDDAT)

t_(SUDAT)

SDA

t_(BUF)

Figure 5. I C Timing Diagram

SCL

SDA

…

A1 A0 R/W

ACK By

Start By

Master

ACK By

TMP100 or TMP101

Frame 2 Pointer Register Byte

Frame 1 I²C Slave Address Byte

SCL

(Continued)

SDA

(Continued)

D7 D6

D4 D3 D2 D1

D4 D3 D2 D1 D0

ACK By

Stop By

TMP100 or TMP101

TMP100 or TMP101 Master

Frame 3 Data Byte 1

Frame 4 Data Byte 2

Figure 6. I C Timing Diagram for Write Word Format

ꢆ ꢠ ꢀꢡ ꢢ ꢢ

ꢆ ꢠ ꢀꢡ ꢢ ꢡ

www.ti.com

SBOS231G − JANUARY 2002 − REVISED NOVEMBER 2007

…

SCL

SDA

R/W

Start By

Master

ACK By

TMP100 or TMP101

ACK By

TMP100 or TMP101

Frame 1 I²C Slave Address Byte

Frame 2 Pointer Register Byte

SCL

(Continued)

…

SDA

(Continued)

…

A0 R/W

D4 D3

Start By

Master

ACK By

TMP100 or TMP101

From

TMP100 or TMP101

ACK By

Master

Frame 3 I²C Slave Address Byte

Frame 4 Data Byte 1 Read Register

SCL

(Continued)

SDA

(Continued)

D7 D6

From

TMP100 or TMP101

ACK By

Master

Stop By

Master

Frame 5 Data Byte 2 Read Register

Figure 7. I C Timing Diagram for Read Word Format

ALERT

SCL

SDA

R/W

Status

Start By

Master

ACK By

TMP100 or TMP101

From

NACK By Stop By

Master

TMP100 or TMP101 Master

Frame 1 SMBus ALERT Response Address Byte

Frame 2 Slave Address From TMP100

Figure 8. Timing Diagram for SMBus ALERT

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

SN0312100DBVR

TMP100NA/250

TMP100NA/250G4

TMP100NA/3K

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

SOT-23

DBV

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-55 to 125

T100

ACTIVE

DBV

250

Green (RoHS

& no Sb/Br)

T100

T101

Green (RoHS

& no Sb/Br)

3000

250

Green (RoHS

& no Sb/Br)

-55 to 125

TMP100NA/3KG4

TMP101NA/250

TMP101NA/250G4

TMP101NA/3K

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

3000

Green (RoHS

& no Sb/Br)

TMP101NA/3KG4

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TMP100, TMP101 :

Automotive: TMP101-Q1

•

Enhanced Product: TMP100-EP

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMP100NA/250

TMP100NA/3K

SOT-23

DBV

250

178.0

9.0

3.23

3.17

1.37

4.0

8.0

3000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMP100NA/250

TMP100NA/3K

SOT-23

DBV

250

180.0

18.0

3000

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TMP101NA250G4 [TI]

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