TMP1075DGKT [TI]
1°C I²C 温度传感器，性能已升级，与业界通用 LM75/TMP75 相当 | DGK | 8 | -55 to 125;
| 型号： | TMP1075DGKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1°C I²C 温度传感器，性能已升级，与业界通用 LM75/TMP75 相当 | DGK | 8 | -55 to 125 温度传感 输出元件 传感器 换能器 温度传感器 |
| 文件： | 总48页 (文件大小：3300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMP1075
SBOS854E – MARCH 2018 – REVISED AUGUST 2021
TMP1075 Temperature Sensor With I2C and SMBus Interface in Industry Standard
LM75 Form Factor and Pinout
1 Features
3 Description
•
Temperature accuracy:
The TMP1075 is the most accurate and lowest
power replacement to the industry standard LM75
and TMP75 digital temperature sensors. Available
in SOIC-8, VSSOP-8, WSON-8, and SOT563-6
packages, the TMP1075 offers pin-to-pin and
software compatibility to quickly upgrade any existing
xx75 design. The TMP1075 additional new packages
are a 2.0 × 2.0 mm DFN and a 1.6 × 1.6 mm
SOT563-6 reducing the printed circuit board (PCB)
footprint by 82% and 89% compared to the SOIC
package, respectively.
– ±0.25°C (typical) from −55°C to +125°C
– ±1°C (maximum) from −40 °C to +110°C
– ±2°C (maximum) from −55°C to +125°C
Low power consumption:
•
– 2.7-μA Average current
– 0.37-μA Shutdown current
Supply range options from: 1.62 V to 5.5 V
Temperature independent of supply
Digital interface: SMBus, I2C
Software compatibility with industry standard LM75
and TMP75
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The TMP1075 has
a
±1°C accuracy over
a
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Can coexist in I3C mixed fast mode bus
Resolution: 12 Bits
Supports up to 32 I2C addresses
ALERT pin function
wide temperature range and offers an on-chip 12-
bit analog-to-digital converter (ADC) providing a
temperature resolution of 0.0625°C.
Compatible with two-wire SMBus and I2C interfaces,
the TMP1075 support up to 32 device addresses and
provides SMBus Reset and Alert function.
NIST traceability
2 Applications
Device Information(1)
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Power-supply temperature monitoring
Computer peripheral thermal protection
Notebook computers
Cell phones
Battery management
Office machines
Thermostat controls
Environmental monitoring and HVAC
Electro mechanical device temperature
PART NUMBER
PACKAGE
VSSOP / DGK (8)
SOIC / D (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
4.90 mm × 3.91 mm
2.00 mm × 2.00 mm
TMP1075
WSON / DSG (8)
SOT563 / DRL (6)(2) 1.20 mm × 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Available as the TMP1075N orderable.
Supply Voltage
3
1.7 V to 5.5 V (TMP1075)
1.62 V to 3.6 V (TMP1075N)
Average
Average ê3s
Min/Max Limit
2.5
2
1.5
1
Pullup Resistors
5 k
Supply Bypass
Capacitor
0.01 µF
0.5
0
SDA
SCL
V+
A0
-0.5
-1
Two-Wire
Host Controller
-1.5
-2
A1*
A2*
-2.5
ALERT
GND
-3
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D00X
*Pin is not available on
TMP1075N
DGK and D packages
Temperature Accuracy
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP1075
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SBOS854E – MARCH 2018 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Device Comparison.........................................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings ....................................... 6
8.2 ESD Ratings .............................................................. 6
8.3 Recommended Operating Conditions ........................6
8.4 Thermal Information ...................................................7
8.5 Electrical Characteristics:TMP1075 ...........................7
8.6 Electrical Characteristics: TMP1075N ....................... 8
8.7 Timing Requirements:TMP1075 ................................ 9
8.8 Timing Requirements: TMP1075N ...........................10
8.9 Switching Characteristics .........................................10
8.10 Typical Characteristics............................................ 11
9 Detailed Description......................................................13
9.1 Overview...................................................................13
9.2 Functional Block Diagram.........................................13
9.3 Feature Description...................................................14
9.4 Device Functional Modes..........................................20
9.5 Register Map.............................................................22
10 Application and Implementation................................26
10.1 Application Information........................................... 26
10.2 Typical Application.................................................. 26
11 Power Supply Recommendations..............................27
12 Layout...........................................................................28
12.1 Layout Guidelines................................................... 28
12.2 Layout Example...................................................... 28
13 Device and Documentation Support..........................31
13.1 Receiving Notification of Documentation Updates..31
13.2 Support Resources................................................. 31
13.3 Trademarks.............................................................31
13.4 Electrostatic Discharge Caution..............................31
13.5 Glossary..................................................................31
14 Mechanical, Packaging, and Orderable
Information.................................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (October 2019) to Revision E (August 2021)
Page
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Added TMP1075N features to list.......................................................................................................................1
Added typical accuracy specification to features list...........................................................................................1
Added the SOT563 (TMP1075N orderable) package.........................................................................................1
Added TMP1075N temperature range to description (continued section)..........................................................4
Added Device Comparison Section....................................................................................................................4
Added figures for different package options....................................................................................................... 5
Added column for TMP1075N pin numbers........................................................................................................5
Added TMP1075N Specifications.......................................................................................................................6
Added TMP1075NDRL Temperature Error vs. Temperature graph .................................................................11
Added TMP1075N information in Overview Section.........................................................................................13
Changed the Functional Block Diagram to apply to TMP1075N...................................................................... 13
Added number of I2C addresses available on TMP1075N to Serial Bus Address Section. ............................15
Added table for TMP1075N address options. ..................................................................................................15
Updated internal register structure figure to apply to TMP1075N.....................................................................15
Added typical specification for TMP1075N timeout ......................................................................................... 17
Added clarification on timeout function to include SCL.....................................................................................17
Removed redundant information to accurate describe all packages................................................................20
Added TMP1075N OS bit behavior.................................................................................................................. 20
Added TMP1075N Continuous Conversion Mode information.........................................................................20
Updated Conversion Rate Diagram to reflect all TMP1075 and TMP1075N....................................................20
Clarified what TM bit behavior for TMP1075 and TMP1075N ......................................................................... 21
Added table note to indicate Device ID register is not available on TMP1075N...............................................22
Added TMP1075N configuration register information ......................................................................................23
Updated text to indicate that device ID register does not apply to TMP1075N................................................ 25
Added number of I2C addresses available on TMP1075N...............................................................................26
Changed Typical Connections figure to apply to TMP1075N........................................................................... 26
Removed redundant Application Curve section................................................................................................26
Updated text to include TMP1075N information...............................................................................................26
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Updated Migrating From the xx75 Device Family section to specify TMP1075 compatible packages ............27
Included TMP1075N information to Power Supply Recommendations............................................................27
Added figures to the Layout Example section for each package......................................................................28
Changes from Revision C (January 2019) to Revision D (October 2019)
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Added software compatibility to feature list........................................................................................................ 1
Updated absolute max for Power supply V+ to 6.5V from 6V.............................................................................6
Updated absolute max for Input voltage on SCL, SDA, A1, A0 to 6.5V from 6V................................................6
Updated pointer register to be part of the serial interface description.............................................................. 15
Updated the register map table to new format..................................................................................................22
Added access type codes for register bits........................................................................................................22
Updated temperature register format and bit definition table............................................................................22
Updated configuration register format and bit definition table ......................................................................... 23
Updated low limit register format and bit definition table ................................................................................. 24
Updated high limit register format and bit definition table ................................................................................24
Updated device ID register format and bit definition table ...............................................................................25
Changes from Revision B (December 2018) to Revision C (January 2019)
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Changed TMP1075DSG package moved from Preview to Production Data......................................................1
Changed min/max limit from 1.5°C to 1°C in the Temperature Accuracy (DGK & D) graph...............................1
Changed min/max limit from 1.5°C to 1°C in the DGK & D Temperature Error vs. Temperature graph........... 11
Added DSG Temperature Error vs. Temperature graph ...................................................................................11
Changes from Revision A (June 2018) to Revision B (December 2018)
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Added TMP1075DSG package ......................................................................................................................... 1
Updated description section of the data sheet and added a Description (continued) section............................ 1
Added TMP1075 configuration register support for single byte read and write................................................23
Added Software support section for migrating from xx75 to TMP1075 ........................................................... 27
Changes from Revision * (March 2018) to Revision A (June 2018)
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Changed the TMP1075DGK orderable status from Advanced Information to Production Data.........................1
Added SOIC and DFN packages........................................................................................................................1
Changed the Functional Block Diagram .......................................................................................................... 13
Changed Digital Temperature Output crossreference from: Temperature Register (0x00) to: Temperature
Data Format .....................................................................................................................................................14
Changed the Temperature Data Format table ................................................................................................. 14
Changed and renamed the Address Pins and Slave Addresses for the TMP1075 table to Address Pins State
..........................................................................................................................................................................15
Changed the Two-Wire Timing Diagrams section ............................................................................................18
Added content to the Device Functional Modes section ..................................................................................20
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5 Description (continued)
The TMP1075 is designed for accurate and cost-effective temperature measurement in virtually any
telecommunication, enterprise, industrial and personal electronics equipment.
The TMP1075 D, DGK, and DSG packages are specified for operation over a temperature range of −55°C to
+125°C and the TMP1075N DRL package is specified over the −40°C to +125°C temperature range.
The TMP1075 units are 100% tested on a production setup that is NIST traceable and verified with equipment
that is calibrated to ISO/IEC 17025 accredited standards.
6 Device Comparison
Table 6-1 lists the key specification and feature differences between the different TMP1075 packages.
Table 6-1. Package Feature and Spec Comparison
TMP1075
TMP1075N
DRL
SPEC/FEATURE
D
DGK
DSG
Supply Voltage
Temperature Range
Body Size
1.7 V to 5.5 V
1.7 V to 5.5 V
–55°C to +125°C
3.00 mm × 3.00 mm
1.7 V to 5.5 V
1.62 V to 3.6V
–55°C to +125°C
4.90 mm × 3.91 mm
–55°C to +125°C
2.00 mm × 2.00 mm
–40°C to +125°C
1.60 mm × 1.20 mm
±1.0°C: –10°C to +60°C
Accuracy
±1.0°C: –40°C to +110°C ±1.0°C: –40°C to +110°C ±1.0°C : –40°C to +75°C
±2.0°C: –55°C to +125°C ±2.0°C: –55°C to +125°C ±2.0°C: –55°C to +125°C ±2.0°C: –40°C to +125°C
I2C Addresses
32
32
32
4
Conversion Rate
Settings
Yes
Yes
Yes
No
Device ID
Yes
Yes
Yes
No
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7 Pin Configuration and Functions
SDA
SCL
1
2
3
4
8
7
6
5
V+
A0
A1
A2
SDA
1
8
V+
A0
SCL
2
3
7
6
ALERT
A1
A2
ALERT
GND
GND
4
5
.
Figure 7-2. DGK Package 8-Pin VSSOP Top View
Figure 7-1. D Package 8-Pin SOIC Top View
V+
SDA
SCL
1
8
SCL
GND
1
2
3
6
5
4
SDA
V+
A0
2
3
7
6
A1
A2
ALERT
GND
ALERT
A0
4
5
1. Pin 1 is determined by orienting the package
marking as indicated in the diagram.
2. Referred to as the TMP1075N orderable
throughout the document.
.
.
Figure 7-3. DSG Package 8-Pin WSON Top View
Figure 7-4. DRL Package 6-Pin SOT563 Top View
Table 7-1. Pin Functions
PIN
SOIC /
VSSOP /
WSON
I/O
DESCRIPTION
NAME
SOT563
A0
7
6
5
3
4
2
1
4
—
—
3
I
I
Address select A0: Connect to GND, V+, SDA, or SCL
Address select A1: Connect to GND, V+, SDA, or SCL
Address select A2: Connect to GND or V+
Overtemperature alert; Open-drain output that requires a pullup resistor
Ground
A1
A2
I
ALERT
GND
SCL
SDA
O
—
I
2
1
Serial clock
6
I/O
Serial data. Open-drain output that requires a pullup resistor
Supply voltage, 1.7 V to 5.5 V (TMP1075); 1.62 V to 3.6 V
(TMP1075N)
V+
8
5
I
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
6.5
4
UNIT
TMP1075
TMP1075N
TMP1075
TMP1075N
V
Power supply, V+
Input voltage SCL, SDA, A1, A0
Input voltage SCL, SDA, A0
–0.3
–0.3
6.5
4
V
V
(V+)+0.3 and
≤4
Input voltage ALERT
TMP1075N
TMP1075
V
Input voltage A2 pin
–0.3
–55
(V+) + 0.3
150
V
Operating temperature
Junction temperature, TJ
Storage temperature, Tstg
°C
°C
°C
150
–60
130
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE
2000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX
5.5
UNIT
V
TMP1075
TMP1075N
TMP1075
TMP1075N
Supply voltage
1.62
–55
-40
3.3
3.6
V
125
125
°C
°C
Operating free-air temperature, TA
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8.4 Thermal Information
TMP1075
DGK (VSSOP)
8 PINS
TMP1075
D (SOIC)
8 PINS
TMP1075
DSG (WSON)
8 PINS
TMP1075N
DRL (SOT)
6 PINS
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
202.5
130.4
87.4
210.3
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal
resistance
RθJC(top)
RθJB
82
76.9
72.3
32
111.1
54
105.0
87.5
6.1
Junction-to-board thermal resistance
124.4
17.9
Junction-to-top characterization
parameter
ΨJT
9.8
Junction-to-board characterization
parameter
ΨJB
122.6
71.9
54.4
87.0
°C/W
Junction-to-case (bottom) thermal
resistance
RθJC(bot)
MT
__
__
28.1
5.0
__
__
°C/W
Thermal mass
16.6
64.2
mJ/°C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics:TMP1075
at TA = –55°C to +125°C and V+ = 1.7 V to 5.5 V (unless noted); typical specification are at TA = 25°C and V+=3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TEMPERATURE INPUT
Range
–55
125
±1
°C
°C
–40°C to +110°C
±0.25
±0.25
±0.25
±0.25
DGK, D
DSG
Accuracy
(temperature
error)
–55°C to +125°C
–40°C to +75°C
–55°C to +125°C
±2
±1
°C
°C
±2
Accuracy (temperature error)
vs. supply
PSRR
±0.03 °C/V
Resolution
1 LSB (12 bit)
0.0625
0.0625
0.0625
°C
°C
°C
Repeatability(1)
Long-term drift(3)
25°C, V+= 3.3 V(2)
500 hours at 150°C, 5.5V
DIGITAL INPUT/OUTPUT
Input capacitance
5
pF
V
VIH
VIL
IIN
High-level input logic
Low-level input logic
Leakage input current
Input voltage hysteresis
Low-level output logic
ADC Conversion time
0.7(V+)
–0.25
0.3(V+)
0.25
V
µA
mV
V
0
600
0.15
5.5
27.5
55
SCL and SDA pins
VOL
IOL = -3 mA, SDA and ALERT pins
one-shot mode
0
0.4
7
4.5
ms
R1 = 0, R0 = 0 (default)
R1 = 0, R0 = 1
TC
Conversion Time
ms
R1 = 1, R0 = 0
110
220
0.3
0
R1 = 1, R0 = 1
Reset time
The time between reset till ADC conversion start
ms
%
Conversion Rate Variation
–10
1.7
10
POWER SUPPLY
Operating voltage range
3.3
5.5
V
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at TA = –55°C to +125°C and V+ = 1.7 V to 5.5 V (unless noted); typical specification are at TA = 25°C and V+=3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
R1 = 0, R0 = 0 (default)
10
20
9
µA
R1 = 0, R0 = 1
5.5
4
Quiescent current (serial bus
inactive)
IQ
R1 = 1, R0 = 0
6
µA
R1 = 1, R0 = 1
2.7
52
4
During 5.5 ms active conversion
85
µA
µA
Serial bus active, SCL frequency = 400 kHz,
A0=A1=A2=GND
13
ISD
Shutdown current
Serial bus inactive, A0=A1=A2=SCL=SDA=V+,
25°C
0.37
0.65
3.5
µA
µA
Serial bus inactive, A0=A1=A2=SCL=SDA=V+
Supply rising, Power-on Reset
0.37
1.22
1.1
Power supply thresholds
V
Supply failing, Brown-out Detect
(1) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
(2) One-shot mode setup, 1 sample per minute for 24 hours.
(3) Long-term drift is determined using accelerated operational life testing at a junction temperature of 150°C.
8.6 Electrical Characteristics: TMP1075N
At TA = 25°C and V+ = 1.62 to 3.6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TEMPERATURE SENSOR
Temperature Operating
Range
-40
125
°C
°C
-10°C to 60°C
-40°C to 125°C
0.25
0.5
0.2
12
±1
±2
TERR
PSR
TRES
tCONV
Temperature accuracy
DC power supply rejection
Temperature resolution
Conversion time
0.5 °C/V
Bits
Including sign bit
LSB
62.5
26
m°C
35
ms
DIGITAL INPUT/OUTPUT
CIN
VIH
VIL
Input capacitance
Input logic high level
Input logic low level
Input leakage current
Output low level
3
pF
V
0.7 x V+
3.6
0.3 x V+
1
V
IIN
0 V< V+ < 3.6 V
μA
V
VOL
VOL
SDA, ALERT (V+ > 2 V, IOL = 3 mA)
SDA, ALERT (V+ < 2 V, IOL = 3 mA)
0
0
0.4
Output low level
0.2 x V+
V
POWER SUPPLY
V+
Operating supply range
1.62
3.6
10
V
Serial bus inactive
7
15
85
0.5
10
80
Average current
consumption
IDD_AVG
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 2.85 MHz
Serial bus inactive
μA
1
μA
μA
μA
IDD_SD Shutdown current
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 2.85 MHz
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8.7 Timing Requirements:TMP1075
minimum and maximum specifications are over –55°C to 125°C and V+ = 1.7 V to 5.5 V (unless otherwise noted)(1)
FAST MODE
HIGH-SPEED MODE
UNIT
MIN
MAX
MIN
0.001
160
MAX
f(SCL)
t(BUF)
SCL operating frequency
0.001
0.4
2.56
MHz
ns
Bus-free time between STOP and START conditions
1300
Hold time after repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
600
160
ns
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
t(HIGH)
t(VDAT)
tFDA
Repeated START condition setup time
STOP condition setup time
Data hold time(2)
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
130
Data setup time
100
1300
600
20
SCL clock low period
250
60
SCL clock high period
Data valid time (data response time)(3)
Data fall time
900
300
300
300
30
130
100
40
tR
Clock rise time
tF
Clock fall time
40
ttimeout
tRC
Timeout (SCL = SDA = GND)
Clock/ data rise time for SCL = 100 kHz
20
20
30
1000
(1) The host and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release.
(2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.
(3) t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse). = time for data signal from
SCL LOW to SDA output (HIGH to LOW, depending on which is worse).
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8.8 Timing Requirements: TMP1075N
minimum and maximum specifications are over –40°C to 125°C and V+ = 1.62 V to 3.6 V (unless otherwise noted)(1)
FAST MODE
HIGH-SPEED MODE
UNIT
MIN
MAX
MIN
0.001
160
MAX
f(SCL)
t(BUF)
SCL operating frequency
0.001
0.4
2.85
MHz
ns
Bus-free time between STOP and START conditions
600
Hold time after repeated START condition.
After this period, the first clock is generated.
t(HDSTA)
600
160
ns
t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
t(LOW)
Repeated START condition setup time
STOP condition setup time
Data hold time(2)
600
600
160
160
25
ns
ns
ns
ns
ns
ns
ns
100
900
105
80
Data setup time
100
25
SCL clock low period
SCL clock high period
Data fall time
1300
600
210
60
t(HIGH)
tFD
300
300
1000
300
300
40
tRD
Data rise time
SCLK ≤100 kHz
tRC
Clock rise time
40
40
40
ns
ns
tFC
Clock fall time
ttimeout
Timeout (SCL = SDA = GND)
30
30
ms
(1) The host and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release.
(2) The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.
8.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
tLPF
Spike filter for I3C compatibility
SCL= 12.5 MHz
50
ns
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8.10 Typical Characteristics
at TA = 25°C, V+ = 3.3 V, and apply to D, DGK, and DSG packages (unless otherwise noted)
3
2.5
2
3
2.5
2
Average
Average ê3s
Min/Max Limit
Average
Average ê3s
Min/Max Limit
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
-2.5
-3
-3
-55
-35
-15
5
25
45
65
85
105 125
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
Temperature (èC)
D00X
D00X
Figure 8-1. DGK & D Temperature Error vs.
Temperature
Figure 8-2. DSG Temperature Error vs.
Temperature
1.5
V+ = 5.5 V
V+ = 3.3 V
V+ = 1.7 V
1
0.5
0
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D002
Figure 8-4. Shutdown Current vs. Temperature
Figure 8-3. TMP1075NDRL Temperature Error vs.
Temperature
14
650
27.5 mSec
55 mSec
110 mSec
220 mSec
10
V+ = 5.5 V
V+ = 4.5 V
V+ = 3.3 V
V+ = 2.5 V
V+ = 1.7 V
Limit
600
12
550
500
450
400
350
300
250
200
150
100
50
8
6
4
2
0
0
0
10
20
30
40
50
60
VIN/VSupply (%)
70
80
90 100
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D004
D002
Figure 8-6. Supply Current vs. Input Cell Voltage
Figure 8-5. Average Current vs. Conversion Rates
and Temperature
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90
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1 MHz
400 KHz
100 KHz
V+ = 1.7 V
V+ = 2.5 V
V+ = 3.3 V
V+ = 5.5 V
80
70
No I2C
60
50
40
30
20
10
0
-10
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
0
1
2
3
4
5
6
Pin Sink Current (mA)
7
8
9 10 11 12 13 14 15 16 17
D005
D006
Figure 8-7. Supply Current vs. I2C Bus Clock and
Supply Voltage in Shutdown Mode
Figure 8-8. ALERT Pin Output Voltage vs. Sink
Current
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-55
-35
-15
5
25
45
65
85
105 125
Temperature (èC)
D007
Figure 8-9. Sampling Period Change vs. Temperature (1.7 V to 5.5 V)
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9 Detailed Description
9.1 Overview
The TMP1075 device is a digital temperature sensor that is optimal for thermal management and thermal
protection applications. The TMP1075 is a SMBus and is I2C interface-compatible. It is also capable of
coexisting in an I3C bus when in Mixed Fast Mode. The TMP1075 non-N orderables are specified over a
temperature range of −55°C to +125°C and the TMP1075N orderable is specified over the −40°C to +125°C
temperature range. The Figure 9-1 section shows an internal block diagram of TMP1075 device.
The temperature sensor thermal path runs through the package leads as well as the plastic package. The leads
provide the primary thermal path due to the lower thermal resistance of the metal.
9.2 Functional Block Diagram
V+
A2*
A0, A1*
Serial
Interface
SCL
SDA
V+
Register
Bank
**
ALERT
Control
Logic
Oscillator
Internal
Thermal
BJT Sensor
Temperature
ADC
Sensor
Circuitry
GND
*Pin is not available on TMP1075N
** ESD Diode only in TMP1075N
Figure 9-1. Functional Block Diagram
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9.3 Feature Description
9.3.1 Digital Temperature Output
The digital output from each temperature measurement conversion is stored in the read-only temperature
register. Which is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes
must be read to obtain data. However, only the first 12 MSBs are used to indicate temperature while the
remaining 4 LSB are set to zero. Table 9-1 lists the data format for the temperature. Negative numbers are
represented in binary two's-complement format. After power-up or reset, the temperature register reads 0°C until
the first conversion is complete.
Table 9-1. Temperature Data Format
TEMPERATURE
(°C)
DIGITAL OUTPUT
BINARY
HEX
7FF0
6400
5000
4B00
3200
1900
0040
0010
0000
FFF0
FFC0
E700
CE00
8000
127.9375
100
0111 1111 1111 0000
0110 0100 0000 0000
0101 0000 0000 0000
0100 1011 0000 0000
0011 0010 0000 0000
0001 1001 0000 0000
0000 0000 0100 0000
0000 0000 0001 0000
0000 0000 0000 0000
1111 1111 1111 0000
1111 1111 1100 0000
1110 0111 0000 0000
1100 1110 0000 0000
1000 000 0000 0000
80
75
50
25
0.25
0.0625
0
–0.0625
–0.25
–25
–50
–128
9.3.2 I2C and SMBus Serial Interface
The TMP1075 operates as a target device on the two-wire, SMBus and I2C interface-compatible bus.
Connections to the bus are made through the open-drain I/O line SDA and SCL input pin. The SDA and SCL
pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and
bus noise. The TMP1075 supports the transmission protocol for fast mode up to 400 kHz and high-speed mode
up to 2.56 MHz. All data bytes are transmitted MSB first.
9.3.2.1 Bus Overview
The device that initiates the data transfer is called a host, and the devices controlled by the host are the target.
The bus must be controlled by a host device that generates the SCL that controls the bus access and generates
the START and STOP conditions.
To address a specific device, a START condition is initiated. This is indicated by the host pulling the data line
SDA from a high to low logic level when SCL is high. All target devices on the bus shift in the device address
byte on the rising edge of the clock with the last bit indicating whether a read or write operation is intended.
During the ninth clock pulse, the device being addressed responds to the host by generating an Acknowledge
and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge bit. During data
transfer, SDA must remain stable when SCL is high because any change in SDA when SCL is high is interpreted
as a control signal.
When all data are transferred, the host generates a STOP condition indicated by pulling SDA from low to high
logic level when SCL is high.
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9.3.2.2 Serial Bus Address
To communicate with the TMP1075, the host must first address devices through an address byte. The device
address byte consists of seven address bits and a direction bit indicating the intent of executing a read or write
operation.
The TMP1075 features three address pins to allow up to 32 devices (TMP1075N: 4) to be addressed on a single
bus interface. Table 9-2 and Table 9-3 describe the pin logic levels used to configure the TMP1075 I2C address.
The state of pins A0, A1, and A2 is sampled on every bus communication and must be set prior to any activity on
the interface.
Table 9-2. TMP1075 Address Pins State
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
0
7-BIT ADDRESS
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
A0
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
0
7-BIT ADDRESS
1010000
1010001
1010010
1010011
1010100
1010101
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Table 9-3. TMP1075N Address Pins State
A0
7-BIT ADDRESS
0
1001000
1001001
1001010
1001011
1
SDA
SCL
9.3.2.3 Pointer Register
Figure 9-2 shows the internal register structure of the TMP1075, and Table 9-5 lists the pointer addresses of the
register map. Table 9-4 shows that the register map reset value of the pointer register is 00h.
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Pointer
Register
Temperature
Register
SCL
Con gura on
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Device ID*
* Not available on TMP1075N package
Figure 9-2. Internal Register Structure
9.3.2.3.1 Pointer Register Byte [reset = 00h]
Table 9-4. Pointer Register Byte
P7
P6
P5
P4
P3
P2
P1
P0
0
0
0
0
Register Bits
9.3.2.4 Writing and Reading to the TMP1075
Accessing a particular register on the TMP1075 device is accomplished by writing the appropriate value to the
pointer register. After Reset, the register value is set to zero. The value for the pointer register is the first byte
transferred after the device address byte with the R/W bit low. Every write operation to the TMP1075 requires a
value for the pointer register (see Figure 9-3).
When reading from the TMP1075 device, the last value stored in the pointer register by a write operation is used
to determine which register is read by a read operation. To change the register pointer for a read operation,
a new value must be written to the pointer register. This action is accomplished by issuing a device address
byte with the R/ W bit low, followed by the pointer register byte. No additional data are required. The host can
then generate a START condition and send the device address byte with the R/ W bit high to initiate the read
command. See Figure 9-5 for details of this sequence. If repeated reads from the same register are desired, the
pointer register bytes do not have to be continually sent because the TMP1075 remembers the pointer register
value until the value is changed by the next write operation.
Register bytes are sent MSB first.
9.3.2.5 Operation Mode
The TMP1075 can operate as a receiver or transmitter. As a target device, the TMP1075 never drives the SCL
line.
9.3.2.5.1 Receiver Mode
The first byte transmitted by the host is the device address with the R/W bit low. The TMP1075 then
acknowledges reception of a valid address. The next byte transmitted by the host is the pointer register. The
TMP1075 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the
register addressed by the pointer register. The TMP1075 acknowledges reception of each data byte. The host
can terminate data transfer by generating a START or STOP condition.
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9.3.2.5.2 Transmitter Mode
The first byte is transmitted by the host and is the device address, with the R/W bit high. The target device
acknowledges reception of a valid device address. The next byte is transmitted by the device and is the most
significant byte of the register indicated by the Pointer register. The host acknowledges reception of the data
byte. The next byte transmitted by the device is the least significant byte. The host acknowledges reception of
the data byte. The host can terminate data transfer by generating a Not-Acknowledge on reception of any data
byte, or generating a START or STOP condition.
9.3.2.6 SMBus Alert Function
The TMP1075 supports the SMBus Alert function. When the TMP1075 is operating in interrupt mode (TM = 1),
the ALERT pin of the TMP1075 can be connected as an SMBus Alert signal. When a host senses that an alert
condition is present on the ALERT line, the host sends an SMBus Alert command (00011001) on the bus. If
the ALERT pin of the TMP1075 is active, the devices acknowledge the SMBus Alert command and respond by
returning the device address on the SDA line. The eighth bit (LSB) of the device address byte indicates if the
temperature exceeding THIGH or falling below TLOW caused the alert condition. This bit is equal to POL if the
temperature is greater than or equal to THIGH. This bit is equal to POL if the temperature is less than TLOW. See
Figure 9-8 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert command, arbitration during the device address
portion of the SMBus Alert command determines which device clears the alert status. If the TMP1075 wins the
arbitration, the ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP1075
loses the arbitration, the ALERT pin remains active.
9.3.2.7 General Call- Reset Function
The TMP1075 responds to the two-wire general call address (0000 000) if the eighth bit is 0. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000 110, the TMP1075 resets the internal registers to the power-up reset values.
9.3.2.8 High-Speed Mode (HS)
For the two-wire bus to operate at frequencies above 400 kHz, the host device must issue an HS mode host
code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The
TMP1075 device does not acknowledge this byte, but it does switch the input filters on the SDA and SCL and
the output filters on the SDA to operate in HS mode. After the HS mode host code is issued, the host transmits
a two-wire device address to initiate a data transfer operation. The bus continues to operate in HS mode until
a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP1075 switches the input and
output filters back to fast-mode operation.
9.3.2.9 Coexists in I3C Mixed Fast Mode
A bus with both I3C and I2C interfaces is referred to as a mixed fast mode with clock speeds up to 12.5 MHz.
In order for the TMP1075, which is an I2C device, to coexist in the same bus, the device incorporated a spike
suppression filter of 50 ns on the SDA and SCL pins to avoid any interference to the bus when communicating
with I3C devices.
9.3.2.10 Time-Out Function
The TMP1075 resets the serial interface if SCL is held low by the host or SDA is held low by the TMP1075 for 25
ms (TMP1075N: 30 ms) (typical) between a START and STOP condition. The TMP1075 releases the SDA bus
and waits for a START condition. To avoid activating the time-out function, a communication speed of at least 1
kHz must be maintained.
9.3.3 Timing Diagrams
The TMP1075 is two-wire SMBus and I2C interface-compatible. Figure 9-3 to Figure 9-8 describe the various
operations on the TMP1075. The following list provides bus definitions.
Bus Idle: Both SDA and SCL lines remain high.
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Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the host device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device
that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA
line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken
into account. On a host receive, the termination of the data transfer can be signaled by the host generating a
Not-Acknowledge on the last byte that is transmitted by the target device.
9.3.4 Two-Wire Timing Diagrams
9
1
9
1
SCL
SDA
…
…
1
0
A4 A3
A2
A1 A0
R/W
0
0
0
0
P3
P2
P1
P0
Start By
Host
ACK By
Device
ACK By
Device
Frame 1 Two Wire Device Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
SDA
D7
D6 D5
D4 D3 D2
D1 D0
D15 D14 D13 D12 D11 D10 D9 D8
(Continued)
ACK By
Device
ACK By
Device
Stop By
Host
Frame 3 Data Byte 1
Frame 4 Data Byte 2
Figure 9-3. Two-Wire Timing Diagram for Write Word Format
9
1
9
1
SCL
SDA
…
…
A6
1
A5
A4
A3 A2
A1
A0
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
Device
ACK By
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Device Address Byte
9
9
SCL
(Continued)
SDA
(Continued)
D15 D14 D13 D12 D11 D10 D9 D8
StopBy
Master
ACK By
Device
Frame 3 Data Byte 1
Figure 9-4. Two-Wire Timing Diagram for Write Single Byte Format
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1
9
1
9
…
SCL
SDA
…
A2
1
0
A4
A3
A1
0
0
0
0
P3
P2
P1
P0
A0
R/W
Start By
Host
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Device Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
…
(Continued)
SDA
…
R/W
1
0
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
(Continued)
Start By
Host
ACK By
Device
From
ACK By
Device
Host
Frame 3 Two-Wire Device Address Byte
9
Frame 4 Data Byte 1 Read Register
1
SCL
(Continued)
SDA
D7 D6
D5
D4
D3
D2
D1
D0
(Continued)
From
ACK By
Host
Stop By
Host
Device
Frame 5 Data Byte 2 Read Register
Figure 9-5. Two-Wire Timing Diagram for Read Word Format
1
9
1
9
…
…
SCL
A2
SDA
1
0
A4
A3
A1
0
0
0
0
P3
P2
P1
P0
A0
R/W
Start By
Host
ACK By
Device
ACK By
Device
Frame 1 Two-Wire Device Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
SDA
R/W
1
0
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
(Continued)
Stop By
Host
Start By
Host
ACK By
Device
From
NACK By
Host
Device
Frame 3 Two-Wire Device Address Byte
Frame 4 Data Byte 1 Read Register
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Figure 9-6. Two-Wire Timing Diagram for Read Single Byte Format
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1
9
1
9
SCL
SDA
0
1
1
0
0
0
0
0
0
0
R/W
1
0
0
0
0
0
Start By
Host
ACK By
From
Host
ACK By
Stop By
Host
Device
Device
Frame 1 Address Byte
Frame 2 Command Byte
Figure 9-7. General-Call Reset Command Timing Diagram
ALERT
1
9
1
9
SCL
SDA
Status
0
0
0
1
1
0
0
R/W
1
0
A4
A3
A2
A1
A0
NACK By Stop By
Host Host
Start By
Host
ACK By
Device
From
Device
Frame 2 Device Address Byte
Frame 1 SMBus ALERT Response Address Byte
Figure 9-8. Timing Diagram for SMBus Alert
9.4 Device Functional Modes
9.4.1 Shutdown Mode (SD)
Shutdown mode (SD) of the TMP1075 device allows the user to conserve power by shutting down all device
circuitry except the serial interface, which significantly reduces the current consumption. SD is initiated when the
SD bit in the configuration register is set to 1. When SD is equal to 0, the device stays in continuous conversion
mode.
9.4.2 One-Shot Mode (OS)
The TMP1075 features a one-shot mode (OS) temperature measurement. When the device is in shutdown
mode, writing 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state
at the completion of the single conversion. This feature is useful to reduce power consumption in the TMP1075
when continuous temperature monitoring is not required.
When the configuration register is read, the OS bit always reads 0 on TMP1075 non-N orderables. On the
TMP1075N orderable, the OS bit reads back 0 during the one-shot conversion and 1 after the conversion cycle.
9.4.3 Continuous Conversion Mode (CC)
When the device is operating in continuous conversion mode (SD=0), every conversion cycle consists of an
active conversion, followed by a standby (see Figure 9-9). The device consumes a higher current during an
active conversion, and lower current during standby. Active conversion time is 5.5 ms (TMP1075N: 23 ms)
before the part goes in standby. Table 9-8 shows the list of conversion cycle configured using [R1:R0] bits in the
configuration register.
1 Conversion Cycle
Ac ve Conversion
Standby
Ac ve
Conversion me
Ac ve
Conversion me
Start of
Conversion
Start-Up
Figure 9-9. Conversion Rate Diagram
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9.4.4 Thermostat Mode (TM)
The thermostat mode bit indicates whether ALERT pin operates in comparator mode (TM = 0) or interrupt mode
(TM = 1). ALERT pin mode is controlled by TM (bit 9) of the configuration register. Any write to the TM bit
changes the ALERT pin to a none active condition, clears the faults count, and clears the alert interrupt history
on the TMP1075 non-N orderables. The ALERT pin can be disabled in both comparator and interrupt modes if
both limit registers are set to the rail values TLOW = –128°C and THIGH = +127.9375°C on the TMP1075 non-N
orderables.
9.4.4.1 Comparator Mode (TM = 0)
In comparator mode (TM = 0), the ALERT pin becomes active when the temperature equals or exceeds the
value in THIGH for a consecutive number of Fault Queue bits [F1:F0]. The ALERT pin remains active until the
temperature falls below the indicated TLOW value for the same number of faults.
The difference between the two limits acts as a hysteresis on the comparator output, and a fault counter
prevents false alerts as a result of system noise. The SMBus Alert response function is ignored in the
comparator mode.
9.4.4.2 Interrupt Mode (TM = 1)
In interrupt mode (TM = 1), the device starts to compare temperature readings with the high limit register value.
The ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of
conversions as set by the Fault Queue bits [F1:F0]. The ALERT pin remains active until it is cleared by one
of three events: a read of any register, a successful SMBus Alert response, or a shutdown command. After
the ALERT pin is cleared, the device starts to compare temperature readings with the TLOW. The ALERT pin
becomes active again only when the temperature drops below TLOW for a consecutive number of conversions
as set by the Fault Queue bits. The ALERT pin remains active until cleared by any of the same three clearing
events. After the ALERT pin is cleared by one of the events, the cycle repeats and the device resumes to
compare the temperature to THIGH. The interrupt mode history is cleared by a change in the TM=0 bit, setting the
device to SD mode, or resetting the device on the TMP1075 non-N orderables.
9.4.4.3 Polarity Mode (POL)
The polarity bit allows the user to adjust the polarity of the ALERT pin output. If the POL bit is set to 0 (default),
the ALERT pin becomes active low. When POL bit is set to 1, the ALERT pin becomes active high and the state
of the ALERT pin is inverted. Figure 9-10 shows the operation of the ALERT pin in various modes.
THIGH
Measured
Temperature
TLOW
ALERT PIN
(ComparatorMode)
POL=0
ALERT PIN
(InterruptMode)
POL=0
ALERT PIN
(ComparatorMode)
POL=1
ALERT PIN
(InterruptMode)
POL=1
Read
Read
Time
Read
Figure 9-10. Output Transfer Function Diagrams
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9.5 Register Map
Table 9-5. TMP1075 Register Map
ADDRESS
00h
TYPE
R
RESET
ACRONYM
REGISTER NAME
Temperature result register
Configuration register
Low limit register
SECTION
Go
0000h TEMP
00FFh CFGR
4B00h LLIM
5000h HLIM
7500h DIEID
01h
R/W
R/W
R/W
R
Go
02h
Go
03h
0Fh(1)
High limit register
Go
Device ID register
Go
(1) Device ID register not available on TMP1075N
Note
TMP1075 Configuration register supports single byte read and write for software compatibility with
xx75 standard temperature sensors.
9.5.1 Register Descriptions
Table 9-6. TMP1075 Access Type Codes
Access Type
Code
R
Description
Read Type
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
9.5.1.1 Temperature Register (address = 00h) [default reset = 0000h]
The temperature register of the TMP1075 is a 12-bit, read-only register that stores the result of the most recent
conversion (see Figure 9-11). Data is represented in binary two's complement format. The first 12 bits are used
to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read
if that information is not needed. Following power-up or reset, the temperature register value is 0°C until the first
conversion is complete.
Figure 9-11. Temperature Register
15
14
13
T9
12
11
10
T6
9
8
T11
R-0
T10
R-0
T8
T7
T5
T4
R-0
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
0
2
0
1
0
0
0
T3
T2
T1
T0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
Table 9-7. Temperature Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:4
T[11:0]
R
000h
12-bit, read-only register that stores the most recent
temperature conversion results.
3:0
—
R
0h
Not used
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9.5.1.2 Configuration Register (address = 01h) [default reset = 00FFh (60A0h TMP1075N)]
The configuration register is an 16-bit read/write register used to store bits that control the operational modes
of the temperature sensor. Read and write operations are performed MSB first. Figure 9-12 shows the format of
the configuration register for the TMP1075, followed by a breakdown of the register bits. The power-up or reset
value of the configuration register are all bits equal to 00FFh (TMP1075N: 60A0h). Only single byte writes and
reads must be used when pointing to the configuration register for proper operation on the TMP1075N orderable.
Figure 9-12. Configuration Register: TMP1075
15
OS
14
R1
13
12
11
10
9
8
R0
F1
F0
POL
TM
SD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
Figure 9-13. Configuration Register: TMP1075N
15
OS
14
R1
13
12
11
10
9
8
R0
F1
F0
POL
TM
SD
R/W-0
R-1
R-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
1
6
0
5
x
4
0
3
0
2
0
1
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 9-8. Configuration Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
OS
R/W
0
One-shot conversion mode. Writing 1, starts a single
temperature conversion. Read returns 0.
14:13
R[1:0]
R/W
R (TMP1075N)
0
Conversion rate setting when device is in continuous
conversion mode
11 (TMP1075N)
00: 27.5 ms conversion rate
01: 55 ms conversion rate
10: 110 ms conversion rate
11: 220 ms conversion rate (35 ms TMP1075N)
12:11
F[1:0]
R/W
0
Consecutive fault measurements to trigger the alert
function
00: 1 fault
01: 2 faults
10: 3 faults (4 faults TMP1075N)
11: 4 faults (6 faults TMP1075N)
10
9
POL
TM
SD
—
R/W
R/W
R/W
R/W
0
0
0
Polarity of the output pin
0: Active low ALERT pin
1: Active high ALERT pin
Selects the function of the ALERT pin
0: ALERT pin functions in comparator mode
1: ALERT pin functions in interrupt mode
8
Sets the device in shutdown mode to conserve power
0: Device is in continuous conversion
1: Device is in shutdown mode
7:0
FFh
Not used
A0h (TMP1075N)
Reserved on TMP1075N package
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Note
The configuration register supports single-byte read and write over I2C bus to ensure software
compatibility with other xx75 standard temperature sensors like TMP75 and LM75. When a single
byte write is performed, the data byte on the I2C bus updates the register bits 15-8. Similarly when a
single byte read is performed, the data bits 15-8 is transferred over the I2C bus.
9.5.1.3 Low Limit Register (address = 02h) [default reset = 4B00h]
The register is configured as a 12-bit, read/write register and data is represented in two's complement format.
Figure 9-14 shows the layout for TLOW is the same as the temperature register. The default reset value is 4B00h
and corresponds to 75°C.
Figure 9-14. Low Limit Register
15
L11
14
L10
13
L9
12
11
10
L6
9
8
L8
L7
L5
L4
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
7
6
5
4
3
0
2
0
1
0
0
0
L3
L2
L1
L0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-9. Low Limit Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:4
L[11:0]
R/W
4B0h
12-bit, read-write register that stores the low limit for comparison
with temperature results.
3:0
—
R/W
0h
Not used
9.5.1.4 High Limit Register (address = 03h) [default reset = 5000h]
The register is configured as a 12-bit, read/write register and data is represented in two's complement format.
Figure 9-15 show the layout for THIGH is the same as the temperature register. The default reset value is 5000h
and corresponds to 80°C.
Figure 9-15. High Limit Register
15
14
13
H9
12
11
10
H6
9
8
H11
H10
H8
H7
H5
H4
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
0
2
0
1
0
0
0
H3
H2
H1
H0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-10. High Limit Register Field Description
BIT
FIELD
TYPE
RESET
DESCRIPTION
15:4
H[11:0]
R/W
500h
12-bit, read-write register that stores the high limit for
comparison with temperature results.
3:0
—
R/W
0h
Not used
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9.5.1.5 Device ID Register (address = 0Fh) [default reset = 7500]
Figure 9-16 shows this read-only register reads the device ID, and this register only available on the TMP1075
non-N orderables.
Figure 9-16. Device ID Register
15
DID15
R-0
14
DID14
R-1
13
DID13
R-1
12
DID12
R-1
11
10
DID10
R-1
9
8
DID11
R-0
DID9
R-0
DID8
R-1
7
6
5
4
3
2
1
0
DID7
R-0
DID6
R-0
DID5
R-0
DID4
R-0
DID3
R-0
DID2
R-0
DID1
R-0
DID0
R-0
Table 9-11. Device ID Register Field Description
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
DID[15:0]
R/W
7500h
16-bit, read-only register that stores the die ID for the device.
The MSB reads the static value 75h to indicate the device name
for TMP1075
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TMP1075 can measure the PCB temperature of the location where the user mounts the device. The
TMP1075 features two-wire SMBus and I2C interface compatibility, with the TMP1075 allowing up to 32
(TMP1075N: 4) devices on one bus. The TMP1075 requires a pullup resistor on the SDA pin, and if needed, on
the SCL and ALERT pins. A 0.01-μF bypass capacitor is also required (see Figure 10-1 ).
10.2 Typical Application
Supply Voltage
1.7 V to 5.5 V (TMP1075)
1.62 V to 3.6 V (TMP1075N)
Pullup Resistors
5 k
Supply Bypass
Capacitor
0.01 µF
SDA
SCL
V+
A0
Two-Wire
Host Controller
ALERT
GND
Figure 10-1. Typical Connections
10.2.1 Design Requirements
The recommended value for the pullup resistor is 5 kΩ. In some applications, the pullup resistor can be lower
or higher than 5 kΩ, but the maximum current through the pullup current is recommended to not exceed 3 mA
on the SCL and SDA pins. The SCL, SDA, A0, and A1, lines can be pulled up to a supply that is higher than
V+. The ALERT line can be pulled up to a supply higher than V+ on the TMP1075 non-N orderables. The A2 pin
can only be connected to GND or V+. When the ALERT pin is not used, it can either be connected GND or left
floating.
10.2.2 Detailed Design Procedure
Place the TMP1075 device in close proximity to the heat source that must be monitored with a proper layout
for good thermal coupling. This placement ensures that temperature changes are captured within the shortest
possible time interval. To maintain accuracy in applications that require air or surface temperature measurement,
take care to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive is
helpful in achieving accurate surface temperature measurement.
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10.2.2.1 Migrating From the xx75 Device Family
The TMP1075 is designed specifically to be a pin-to-pin compatible replacement with xx75 family of devices.
This includes considerations for software compatibility. The two byte registers of the TMP1075 dynamically
support single byte read or write, meaning that replacing older xx75 standard temperature sensors should not
require any updates to existing code.
10.2.3 Application Curve
For application curves, see Table 10-1:
Table 10-1. Table of Graphs
FIGURE
TITLE
Figure 8-9
Sampling Period Change vs. Temperature (1.7 V to 5.5 V)
11 Power Supply Recommendations
The TMP1075 D, DGK, and DSG packages operate with a power supply in the range of 1.7 V to 5.5 V
(TMP1075N DRL package operates from 1.62 V to 3.6 V). A power-supply bypass capacitor is required for
precision and stability. Place this power-supply bypass capacitor as close to the supply and ground pins of
the device as possible. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies can require a bigger bypass capacitor to reject power-supply noise.
To minimize device self-heating and improve temperature precision, it is recommended to:
•
•
•
•
•
•
Use the minimum supply voltage rail available
Avoid communication over I2C bus during ADC conversion
Use one-shot mode to minimize power consumption
Set I2C signal levels VIL close to ground and VIH above 90% of V+
Maintain the I2C bus signals positive edge less than 1 µs by using a pull-up resistor < 10 kΩ
Connect the address pins A0 and A1 to either ground or V+
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12 Layout
12.1 Layout Guidelines
Place the power-supply bypass capacitor as close to the supply and ground pins as possible. The recommended
value of this bypass capacitor is 0.01 μF. Pullup the open-drain output pins SDA and ALERT through 5-kΩ pullup
resistors. The SCL requires a pullup resistor only if the microprocessor output is open drain.
12.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Supply Bypass
Capacitor
Pull-Up Resistors
Supply Voltage
SDA
SCL
V+
A0
A1
A2
ALERT
GND
Serial Bus Traces
Ground Plane for
Thermal Coupling
to Heat Source
Heat Source
Figure 12-1. Layout Example (D Package)
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Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
V+
SDA
A0
A1
A2
SCL
ALERT
GND
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 12-2. Layout Example (DGK Package)
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
V+
A0
A1
A2
SCL
ALERT
GND
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 12-3. Layout Example (DSG Package)
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Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
SCL
GND
ALERT
SDA
V+
Supply Voltage
ADD0
Supply Bypass
Capacitor
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 12-4. Layout Example (DRL Package)
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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22-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP1075DGKR
TMP1075DGKT
TMP1075DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
6
6
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-40 to 125
-40 to 125
1075
1075
1075
1AE
1AE
N75
N75
NIPDAUAG
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
2500 RoHS & Green
3000 RoHS & Green
TMP1075DSGR
TMP1075DSGT
TMP1075NDRLR
TMP1075NDRLT
WSON
DSG
DSG
DRL
DRL
WSON
250
4000 RoHS & Green
250 RoHS & Green
RoHS & Green
SOT-5X3
SOT-5X3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP1075DGKR
TMP1075DGKT
TMP1075DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
6
2500
250
330.0
330.0
330.0
180.0
180.0
180.0
12.4
12.4
12.4
8.4
5.3
5.3
6.4
2.3
2.3
2.0
3.4
3.4
5.2
2.3
2.3
1.8
1.4
1.4
8.0
8.0
8.0
4.0
4.0
4.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q2
Q2
Q3
2500
3000
250
2.1
TMP1075DSGR
TMP1075DSGT
TMP1075NDRLT
WSON
WSON
SOT-5X3
DSG
DSG
DRL
1.15
1.15
0.75
8.4
8.0
250
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMP1075DGKR
TMP1075DGKT
TMP1075DR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
8
8
6
2500
250
366.0
366.0
853.0
210.0
210.0
210.0
364.0
364.0
449.0
185.0
185.0
185.0
50.0
50.0
35.0
35.0
35.0
35.0
2500
3000
250
TMP1075DSGR
TMP1075DSGT
TMP1075NDRLT
WSON
WSON
SOT-5X3
DSG
DSG
DRL
250
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/B 12/2020
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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