TMP116NAIDRVR [TI]
具有 64 位非易失性存储器的 0.2C 数字温度传感器 | DRV | 6 | -55 to 125;
| 型号： | TMP116NAIDRVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 64 位非易失性存储器的 0.2C 数字温度传感器 | DRV | 6 | -55 to 125 温度传感 存储 传感器 温度传感器 |
| 文件： | 总48页 (文件大小：2096K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
具有兼容 SMBus 和 I2C 接口的 TMP116 高精度、低功耗数字温度传感器
1 特性
3 说明
1
•
TMP116 精度（无需校准）：
TMP116 系列（TMP116、TMP116N）包括具有集成
EEPROM 存储器的低功耗、高精度温度传感器。
TMP116 可提供 16 位温度结果，具有 0.0078°C 的分
辨率，且无需校准即可实现高达 ±0.2°C 的精度。
TMP116 可兼容 I2C 和 SMBus 接口，具有可编程警报
功能，在单路总线上最多可支持 4 个器件。
–
–
–
–10°C 至 +85°C 范围内为 ±0.2°C（最大值）
–40°C 至 +105°C 范围内为 ±0.25°C（最大值）
+105°C 至 +125°C 范围内为 ±0.3°C（最大
值）
•
•
TMP116N 精度（无需校准）：
–
–
–25°C 至 +85°C 范围内为 ±0.3°C（最大值）
–40°C 至 +125°C 范围内为 ±0.4°C（最大值）
TMP116 不仅节省功耗，而且消耗最低电流，能够最
大限度减少自发热并提高测量精度。TMP116 在 1.9V
至 5.5V 电压范围内运行，电流消耗通常为 3.5µA。
低静态电流：
–
–
3.5μA、1Hz 转换周期
250nA 关断电流
TMP116 器件运行温度范围为 –55°C 至 +125°C，精
度比 A 类 RTD 要高，但电流消耗不足 PT100 RTD 典
型激励电流的五分之一。相比于 RTD，TMP116 更易
于使用，无需校准、外部电路、匹配的线迹和开尔文连
接。
•
•
•
•
•
•
•
电源电压范围：1.9V 至 5.5V
分辨率：0.0078°C 时为 16 位 (1 LSB)
可编程温度警报限值
可选择的平均值
通用 EEPROM：64 位
NIST 可追溯性
SMBus™、I2C 接口兼容性
TMP116 装置在生产调试阶段经完全测试，可通过
NIST 进行追溯，且使用经 ISO/IEC 17025 认证标准校
准的设备进行了验证。
器件信息(1)
2 应用
器件型号
TMP116
封装
WSON (6)
封装尺寸（标称值）
•
•
•
•
•
•
•
•
医疗级别：符合 ASTM 和 ISO 规范
2.00mm × 2.00mm
环境监控和恒温器
可穿戴设备
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
资产跟踪和冷链
燃气表和热量计
测试和测量
RTD 替代：PT100、PT500、PT1000
热电偶冷端补偿
空白
简化电路原理图
温度精度
1.9 V to 5.5 V
Supply Voltage
0.5
Average
116N Max Limit
Avg 3ꢀ
0.4
0.3
0.2
0.1
0
5 kꢀ
Pullup
Resistors
116 Max Limit
TMP116
-0.1
-0.2
-0.3
-0.4
-0.5
Two-Wire
Host Controller
1
6
5
4
SCL
SDA
V+
2
3
GND
116 Min Limit
116N Min Limit
0.1-µF
Supply Bypass
Capacitor
ALERT
ADD0
-55 -40 -20
0
20
40
60
Temperature (°C)
80 100
125
150
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS740
TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 12
7.5 Programming........................................................... 17
7.6 Registers Map......................................................... 24
Application and Implementation ........................ 32
8.1 Application Information............................................ 32
Power Supply Recommendations...................... 36
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Two-Wire Interface Timing........................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagrams ..................................... 10
7.3 Feature Description................................................. 10
8
9
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 38
11 器件和文档支持 ..................................................... 39
11.1 文档支持 ............................................................... 39
11.2 接收文档更新通知 ................................................. 39
11.3 社区资源................................................................ 39
11.4 商标....................................................................... 39
11.5 静电放电警告......................................................... 39
11.6 Glossary................................................................ 39
12 机械、封装和可订购信息....................................... 39
7
4 修订历史记录
Changes from Original (May 2017) to Revision A
Page
•
•
•
•
添加了可选择的平均值特性..................................................................................................................................................... 1
Added thermal mass parameter to the Thermal Information table ........................................................................................ 4
Added tablenote to the temperature cycling and hysteresis parameter................................................................................. 5
Added TI recommendation to not solder the thermal pad to the PCB in the Layout Guidelines section............................. 36
2
Copyright © 2017–2019, Texas Instruments Incorporated
TMP116, TMP116N
www.ti.com.cn
ZHCSG96A –MAY 2017–REVISED MAY 2019
5 Pin Configuration and Functions
DRV Package
6-Pin WSON
Top View
SCL
1
2
3
6
5
4
SDA
V+
GND
Thermal
Pad
ALERT
ADD0
Pin Functions
PIN
I/O
DESCRIPTION
NO. NAME
1
2
3
4
5
6
SCL
GND
ALERT
ADD0
V+
I
—
O
I
Serial clock
Ground
Overtemperature alert or data-ready signal. Open-drain output; requires a pullup resistor if used.
Address select. Connect to GND, V+, SDA, or SCL.
I
Supply voltage: 1.9 V to 5.5 V
SDA
I/O Serial data input and open-drain output; requires a pullup resistor.
Copyright © 2017–2019, Texas Instruments Incorporated
3
TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
MIN
–0.3
–0.3
–55
–65
MAX
6
UNIT
V
Supply voltage, V+
Voltage at SCL, SDA, ALERT, and ADD0
Operating junction temperature, TJ
Storage temperature, Tstg
6
V
150
150
°C
°C
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±2000
±1000
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
1.9
NOM
MAX
5.5
UNIT
V+
TA
Supply voltage
3.3
V
Operating free-air temperature
–55
150
°C
6.4 Thermal Information
TMP116
THERMAL METRIC(1)
DRV (WSON)
6 PINS
68.7
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
mJ/°C
RθJC(top)
RθJC(bot)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Thermal Mass
70.3
9.5
38.3
ψJT
1.7
ψJB
38.6
MT
5.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017–2019, Texas Instruments Incorporated
TMP116, TMP116N
www.ti.com.cn
ZHCSG96A –MAY 2017–REVISED MAY 2019
6.5 Electrical Characteristics
minimum and maximum specifications are over –55°C to +125°C and V+ = 1.9 V to 5.5 V (unless otherwise noted); typical
specifications are at TA = 25°C and V+ = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE-TO-DIGITAL CONVERTER
–10°C to +85°C, V+ = 3.3 V
–0.2
–0.25
–0.3
–0.4
–0.3
–0.4
–0.5
0
±0.1
±0.2
±0.25
±0.3
±0.2
±0.3
±0.4
20
0.2
0.25
0.3
0.4
0.3
0.4
0.5
55
–40°C to +105°C, V+ = 3.0 V to 3.6 V
+105°C to +125°C, V+ = 3.0 V to 3.6 V
–40°C to +125°C, V+ = 1.9 V to 5.5 V(2)
–25°C to +85°C, V+ = 3.3 V
TMP116
Temperature
accuracy(1)
°C
TMP116N
–40°C to +125°C, V+ = 3.0 V to 3.6 V
–40°C to +125°C V+ = 1.9 V to 5.5 V(2)
One-shot mode, 8 averages, TA = 25°C
DC power-supply sensitivity
Temperature resolution (LSB)
Repeatability(3)
m°C/V
m°C
LSB
°C
7.8125
±1
V+ = 3.3 V, 8 averages, 1-Hz sampling
300 hours at 150°C(4)
Long-term stability and drift
±0.02
Temperature cycling and
hysteresis(1)(5)
±1
3
LSB
DIGITAL INPUT/OUTPUT
Input capacitance
pF
V
VIH
VIL
IIN
Input logic high level
Input logic low level
Input current
0.7 (V+)
0.3 (V+)
0.2
V
–0.2
0
µA
V
VOL
VOL
S
A
SDA output logic low level
ALERT output logic low level
IOL = –3 mA
IOL = –3 mA
0.4
0
0.4
V
POWER SUPPLY
Active conversion, serial bus inactive
135
3.5
220
4.5
1-Hz conversion cycle, averaging mode off,
serial bus inactive, 25°C
IQ
Quiescent current
µA
1-Hz conversion cycle, 8 averages mode,
serial bus inactive, 25°C
16
21
22
1-Hz conversion cycle, averaging mode off,
serial bus active, SCL frequency = 400 kHz
ISB
Standby current(6)
Shutdown current
Serial bus inactive, SCL and SDA = V+, 25°C
Serial bus inactive, SCL and SDA = V+, 25°C
Serial bus inactive, SCL and SDA = V+, 125°C
Serial bus active, SCL frequency = 400 kHz
ADC conversion off; serial bus inactive
V+ rising
1.25
0.25
2.1
0.5
8.5
µA
µA
ISD
17
240
1.6
IEE
EEPROM write quiescent current
Power-on-reset threshold voltage
Brownout detect
µA
V
VPOR
V+ falling
1.1
V
Reset time
Time required by device to reset
1 conversion
1.5
ms
ms
Active conversion time
13.5
15.5
17
(1) 8 averages, 1-Hz conversion cycle. Measurements are taken in oil bath.
(2) ±0.75°C maximum error between –55°C to –40°C.
(3) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
(4) Long-term stability is determined using accelerated operational life testing at a junction temperature of 150°C.
(5) Hysteresis is defined as the ability to reproduce a temperature reading as the temperature varies from room → hot → room → cold →
room. The temperatures used for this test are –40°C, 25°C, and 125°C.
(6) Quiescent current between conversions.
Copyright © 2017–2019, Texas Instruments Incorporated
5
TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
www.ti.com.cn
Electrical Characteristics (continued)
minimum and maximum specifications are over –55°C to +125°C and V+ = 1.9 V to 5.5 V (unless otherwise noted); typical
specifications are at TA = 25°C and V+ = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EEPROM
Programming time
Number of writes
Data retention time
7
50,000
100
ms
1,000
10
Times
Years
6.6 Two-Wire Interface Timing
minimum and maximum specifications are over –55°C to 125°C and V+ = 1.9 V to 5.5 V (unless otherwise noted); typical
specifications are at TA = 25°C and V+ = 3.3 V; values are based on statistical analysis of samples tested during initial
release
MIN
1
MAX
UNIT
kHz
ns
fSCL
tBUF
SCL operating frequency
400
Bus free time between STOP and START conditions
1300
Hold time after repeated START condition.
After this period, the first clock is generated.
tHD;STA
600
ns
tSU;STA
tSU;STO
tHD;DAT
tVD;DAT
tSU;DAT
tLOW
Repeated START condition setup time
STOP condition setup time
Data hold time
600
600
0
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ms
Data valid time(1)
0.9
Data setup time
100
1300
SCL clock low period
tHIGH
SCL clock high period
600
tF – SDA
tF, tR – SCL
tR
Data fall time
20 × (V+ / 5.5)
300
300
1000
40
Clock fall and rise time
Rise time for SCL ≤ 100 kHz
Serial bus timeout (SDA bus released if there is no clock)
20
(1) tVD;DATA = time for data signal from SCL low to SDA output (high to low, depending on which is worse).
tLOW
tF
tHIGH
tR
VIH
VIL
SCL
SDA
tSU;STO
tHD;DAT
tVD;DAT
tSU;STA
tHD;STA
tBUF
tSU;DAT
VIH
VIL
P
S
S
P
图 1. Two-Wire Timing Diagram
6
版权 © 2017–2019, Texas Instruments Incorporated
TMP116, TMP116N
www.ti.com.cn
ZHCSG96A –MAY 2017–REVISED MAY 2019
6.7 Typical Characteristics
at TA = 25°C, V+ = 3.3 V, and measurement taken in oil bath (unless otherwise noted)
70
60
50
40
30
20
10
0
0.5
0.4
0.3
0.2
0.1
0
Average
116N Max Limit
Avg 3ꢀ
1 Shot, No Conv Cycles
8 Averages, Conv Cycle = 1 s
1 Conversion, Conv Cycle = 500 ms
116 Max Limit
-0.1
-0.2
-0.3
-0.4
-0.5
-10
-20
-30
-40
116 Min Limit
116N Min Limit
-55 -40 -20
0
20
40
60
Temperature (°C)
80 100
125
150
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Supply Voltage (V)
1-Hz conversion cycle, 8 averages mode
图 2. Temperature Error vs Temperature
图 3. Temperature Error vs Supply Voltage
100
90
80
70
60
50
40
30
20
80
70
60
50
40
30
20
10
0
V = +1.9 V, St. Dev = 0.91
V = +3.3 V, St. Dev = 1.01
V = +5 V, St. Dev = 0.96
10
0
-10
-20
-30
-40
-50
-60
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-4
-3
-2
-1
0
1
Data Distribution (LSB)
2
3
4
Supply Voltage (V)
Continuous conversion, no conversion cycle normalized to 3.3V
图 4. Temperature Error vs Supply Voltage in still air
图 5. Data Reading Distribution Over Supply Voltage
(No Averaging)
80
80
Avrg 8, St. Dev = 0.51
Avrg 32, St. Dev = 0.56
Avrg 64, St. Dev = 0.61
-40°C, St. Dev = 1.12
25°C, St. Dev = 1.01
125°C, St. Dev = 1.05
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
-4
-3
-2
-1
Data Distribution (LSB)
0
1
2
3
4
-4
-3
-2
-1
Data Distribution (LSB)
0
1
2
3
4
图 6. Data Reading Distribution Over Temperature
图 7. Data Reading Distribution Over Averaging Number
(No Averaging)
版权 © 2017–2019, Texas Instruments Incorporated
7
TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, V+ = 3.3 V, and measurement taken in oil bath (unless otherwise noted)
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
5.5 V
3.3 V
1.9 V
5.5 V
3.3 V
1.9 V
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
–50
–25
Temperature (°C)
Temperature (°C)
Serial bus inactive
Serial bus inactive
图 8. Quiescent Current in Shutdown Mode
图 9. Quiescent Current in Standby Mode
110
100
90
80
70
60
50
40
30
20
10
0
200
180
160
140
120
100
80
5.5 V
3.3 V
1.9 V
150èC
125èC
100èC
25èC
0èC
-50èC
60
1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 6.3 6.8
Supply Voltage (V)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Bus Frequency (MHz)
Continuous conversion mode, serial bus inactive
SCL, SDA, ADD0 pins are constantly clocked
图 10. Quiescent Current During Active Conversion
图 11. Quiescent Current in Shutdown Mode
5
4
1
1.9 V
3.3 V
5.5 V
+125èC
+25èC
-50èC
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
2
1
0
-1
-2
-3
-4
-5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
-55
-25
5
35 65
Temperature (°C)
95
125
150
Supply Voltage (V)
Serial bus inactive
图 12. Power Consumption During Active Conversion
Normalized to 25°C and V+ = 3.3 V
图 13. Active Conversion Time vs Temperature
8
版权 © 2017–2019, Texas Instruments Incorporated
TMP116, TMP116N
www.ti.com.cn
ZHCSG96A –MAY 2017–REVISED MAY 2019
Typical Characteristics (接下页)
at TA = 25°C, V+ = 3.3 V, and measurement taken in oil bath (unless otherwise noted)
10
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.9 V
3.3 V
5.5 V
1.9 V
2 V
3.3 V
5.5 V
8
6
4
2
0
-2
-4
-6
-8
-10
-50 -30 -10 10
30
50
70
90 110 130 150
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
Sink Current (mA)
Temperature (èC)
Normalized to 25°C and V+ = 3.3 V
图 14. Standby Time vs Temperature
图 15. ALERT Pin Output Voltage vs Pin Sink Current
650
600
550
500
450
400
350
300
250
200
150
100
50
5.5 V
4.4 V
3.3 V
2 V
0
0
10
20
30
40
50
60
70
80
90 100
Vin / V+ (%)
Input voltage of SCL, SDA, or ADD0 pin
图 16. Supply Current vs Input Cell Input Voltage
版权 © 2017–2019, Texas Instruments Incorporated
9
TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TMP116 is a digital output temperature sensor that is optimal for thermal-management and thermal-
protection applications. The TMP116 is two-wire, SMBus, and I2C interface-compatible. The device is specified
over an operating temperature range of –55°C to +125°C. 图 17 shows a block diagram of the TMP116. 图 18
shows the ESD protection circuitry contained in the TMP116.
7.2 Functional Block Diagrams
Temperature
Diode
Temp.
Sensor
1
2
3
Control
Logic
6
5
4
SCL
GND
SDA
DS
A/D
Converter
Serial
Interface
V+
Config.
and Temp.
Register
ALERT
OSC
ADD0
图 17. Internal Block Diagram
SCL
SDA
V+
GND
Core
ALERT
ADD0
图 18. Equivalent Internal ESD Circuitry
7.3 Feature Description
7.3.1 Power Up
After the supply voltage reaches within the operating range, the device requires 1.5 ms to power up before
conversions begin. The device can be programmed to startup in shutdown mode as well; see the EEPROM
Programming section. The temperature register stores –256°C before the first conversion end.
10
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TMP116, TMP116N
www.ti.com.cn
ZHCSG96A –MAY 2017–REVISED MAY 2019
Feature Description (接下页)
7.3.2 Temperature Result and Limits
At the end of every conversion or averaging cycle, the device updates the temperature register with the
conversion result. The data reading in the result register is in two's complement format, has a data width of 16
bits, and a resolution of 7.8125 m°C. 表 1 shows multiple examples of possible binary data that can be read from
the temperature result register and the corresponding hexadecimal and decimal equivalents.
The TMP116 also has alert status flags and alert pin functionality that use the temperature limits stored in the low
limit register and high limit register. The alert registers use the same data format as the temperature register.
表 1. 16-Bit Temperature Data Format
TEMPERATURE REGISTER VALUE
TEMPERATURE
(0.0078125°C RESOLUTION)
(°C)
BINARY
HEX
8000
F380
FFF0
FFFF
0000
0001
0010
0080
0C80
3200
7FFF
–256
–25
1000 0000 0000 0000
1111 0011 1000 0000
1111 1111 1111 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0001 0000
0000 0000 1000 0000
0000 1100 1000 0000
0011 0010 0000 0000
0111 1111 1111 1111
–0.1250
–0.0078125
0
0.0078125
0.1250
1
25
100
255.9921
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7.4 Device Functional Modes
7.4.1 Temperature Conversions
The TMP116 can be configured to operate in various conversion modes by using the MOD[1:0] bits. These
modes provide flexibility to operate the device in the most power efficient way required for the intended
application.
7.4.1.1 Conversion Cycle
When the device is operating in continuous conversion mode (see the Continuous Conversion Mode (CC)
section), every conversion cycle consists of an active conversion period followed by a standby period. During
active conversion the device typically consumes 135 µA, and during the low-power standby period the device
typically consumes 1.25 µA, as indicated in 表 1. 图 19 shows a current consumption profile of a conversion
cycle. The duration of the active conversion period and standby period can be configured using the CONV[2:0]
and AVG[1:0] bits in the configuration register, thereby allowing the average current consumption of the device to
be optimized based on the application requirements. Changing the conversion cycle period also affects the
temperature result update rate because the temperature result register is updated at the end of every conversion
or averaging cycle.
1 Conversion Cycle
Active Conversion
Standby
15.5 ms
15.5 ms
Start-Up
Start of
Conversion
图 19. Conversion Cycle Timing Diagram
7.4.1.2 Averaging
Noise in the conversion result can be reduced by configuring the device to report the average of multiple
temperature conversions using the AVG[1:0] bits. When the TMP116 is configured to perform averaging, the
device executes the configured number of conversions while accumulating the results and reports the average of
all conversion results at the end of the process. As illustrated in the noise histograms of 图 6 and 图 7, the
temperature result output has a repeatability of approximately ±3 LSBs when there is no averaging and ±1 LSB
when the device is configured to perform eight averages or higher. As illustrated in 图 20, this improvement in
noise performance is achieved with the tradeoff of an increase in the active conversion time in a conversion
cycle, thereby increasing the average active current consumption. For example, a single active conversion
typically takes 15.5 ms so if the device is configured to report an average of eight conversions then the active
conversion time is 124 ms (15.5 ms × 8). Use 公式 1 to factor in this increase in active conversion time to
accurately calculate the average current consumption of the device. The average current consumption of the
device can be decreased by increasing the amount of time the device spends in standby period as compared to
active conversion. Under the factory EEPROM settings, the device is configured to report an average of eight
conversions with a conversion cycle time of 1 second.
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Device Functional Modes (接下页)
1 Second
124 ms
8 Conv
8 Averages, 1-Hz CC
Standby
15.5 ms
I2C Temperature or
Configuration Register Read
Data_Ready Flag
图 20. Averaging Timing Diagram
Use 公式 1 to calculate the average current consumption of the device in continuous mode.
(Active Current Consumptionì Active Conversion Time) + (Standby Current ConsumptionìStandby Time)
Conversion Cycle Time
(1)
7.4.1.3 Continuous Conversion Mode (CC)
When the MOD[1:0] bits are set to 00, the TMP116 operates in continuous conversion mode. In this mode, the
device continuously performs temperature conversions as illustrated in 图 19 and updates the temperature result
register at the end of every conversion or averaging cycle. As described in the Conversion Cycle section, every
conversion cycle consists of an active conversion period followed by a standby period whose duration can be
configured using the CONV and AVG bits in the configuration register. The configuration is based on the
temperature accuracy, power consumption, and temperature update rate. At the end of a conversion, the
Data_Ready flag in the configuration register is set. The Data_Ready flag is cleared by reading the configuration
register or the temperature result register. The state of the Data_Ready flag can also be monitored on the
ALERT pin by setting the DR/nAlert_EN bit in the configuration register.
7.4.1.4 Shutdown Mode (SD)
When 01 is written to the MOD bits in the configuration register, the device instantly aborts the currently running
conversion and enters a low-power shutdown mode. In this mode, the device powers down all active circuitry. In
SD mode, the device typically consumes only 250 nA, which makes the TMP116 suitable for low-power
consumption applications, such as battery-operated systems.
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Device Functional Modes (接下页)
7.4.1.5 One-Shot Mode (OS)
When in shutdown mode, a single conversion can be performed by writing 11 to MOD bits in the configuration
register, referred to as a one-shot conversion. After completing a one-shot conversion, the device returns to the
low-power shutdown mode. A one-shot conversion cycle only consists of active conversion time and no standby
period unlike CC mode. Thus, the duration of a one-shot conversion is only affected by the settings in the AVG
bits. 图 21 shows a timing diagram for this mode with an AVG setting of 00 and 图 22 shows a timing diagram for
this mode with an AVG setting of 01. At the end of a one-shot conversion, the Data_Ready flag in the
configuration register is set. The Data_Ready flag is cleared by read of the configuration register or temperature
result register. The state of the Data_Ready flag can also be monitored on the ALERT pin by setting the
DR/nAlert_EN bit in the configuration register.
Shutdown
15.5 ms
(One-Shot Conversion)
图 21. One-Shot Timing Diagram With No Averaging
Shutdown
125 ms
(One-Shot Conversion)
图 22. One-Shot Timing Diagram With 8 Averages
7.4.2 Therm and Alert Modes
The TMP116 can be used to detect if the temperature has crossed a certain temperature limit or if the device is
within a certain temperature range by using the therm or alert functions built into the device. At the end of every
conversion, the TMP116 compares the converted temperature result to the values stored in the low limit register
and high limit register and sets or clears the corresponding status flags in the configuration register, as described
in this section.
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Device Functional Modes (接下页)
7.4.2.1 Alert Mode
When the T/nA bit in the configuration register is set to 0, the device is in alert mode. In this mode, the device
compares the conversion result at the end of every conversion with the values in the low limit register and high
limit register. If the temperature result exceeds the value in the high limit register, the HIGH_Alert status flag in
the configuration register is set. On the other hand, if the temperature result is lower than the value in the low
limit register, the LOW_Alert status flag in the configuration register is set. As shown in 图 23, in alert mode the
status flags can be cleared by performing an I2C read of the configuration register.
Configuring the device in alert mode also affects the behaviour of the ALERT pin. In this mode, the device
asserts the ALERT pin when either the HIGH_Alert or the LOW_Alert status flag is set as shown in 图 23. The
ALERT pin can be deasserted by either performing an I2C read of the configuration register (which also clears
the status flags) or by performing an SMBus alert response command (see the SMBus Alert Function section).
The polarity of the ALERT pin can be changed by using the POL bit setting in the configuration register.
This mode effectively makes the device behave like a window limit detector and can be used in applications
where detecting if the temperature goes outside of the specified range is needed.
High temperature limit
Temperature
Low temperature limit
Temperature conversions
HIGH_Alert Status Flag
LOW_Alert Status Flag
ALERT pin (POL = 0)
Configuration Register I2C Read
SMBus Alert Response Command
图 23. Alert Mode Timing Diagram
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Device Functional Modes (接下页)
7.4.2.2 Therm Mode
When the T/nA bit in the configuration register is set to 1 the device is in therm mode. In this mode, the device
compares the conversion result at the end of every conversion with the values in the low limit register and high
limit register and sets the HIGH_Alert status flag in the configuration register if the temperature exceeds the
value in the high limit register. When set, the device clears the HIGH_Alert status flag if the conversion result
goes below the value in the low limit register. Thus, the difference between the high and low limits effectively acts
like a hysteresis. In this mode, the LOW_Alert status flag is disabled and always reads 0. Unlike the alert mode,
I2C reads of the configuration register do not affect the status bits. The HIGH_Alert status flag is only set or
cleared at the end of conversions based on the value of the temperature result compared to the high and low
limits.
As in alert mode, configuring the device in therm mode also affects the behaviour of the ALERT pin. In this
mode, the device asserts the ALERT pin if the HIGH_Alert status flag is set and deasserts the ALERT pin when
the HIGH_Alert status flag is cleared. In therm mode, the ALERT pin cannot be cleared by performing an I2C
read of the configuration register or by performing an SMBus alert response command. As in alert mode, the
polarity of the active state of the ALERT pin can be changed by using the POL bit setting in the configuration
register.
Thus, this mode effectively makes the device behave like a high-limit threshold detector and can be used in
applications where detecting if the temperature has gone above a desired threshold is needed. 图 24 shows a
timing diagram of this mode.
High temperature limit
Temperature
Low temperature limit
Temperature conversions
HIGH_Alert Status Flag
ALERT pin (POL = 0)
I2C Read
图 24. Therm Mode Timing Diagram
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7.5 Programming
7.5.1 EEPROM Programming
7.5.1.1 EEPROM Overview
The device consists of a user-programmable EEPROM that can be used for two purposes:
•
•
Storing the reset values of configuration register and alert registers
Four 16-bit locations for general-purpose use; see the EEPROM[4:1] registers
On reset, the device goes through a reset sequence that loads the values programmed in the EEPROM into the
respective register map locations. This process takes approximately 1.5 ms. When the reset sequence is
completed the device starts operating in accordance to the configuration parameters that are loaded from the
EEPROM. Any I2C writes performed during this initial period to the registers are ignored. I2C read transactions
can still be performed with the device during the reset period. While the reset sequence is being executed, the
EEPROM_Busy status flag in the EEPROM unlock register is cleared.
During production, the EEPROM in the TMP116 is programmed with reset values as shown in 表 3. The
Programming the EEPROM section describes how to change these values. Additionally, during production a
unique ID is programmed in the general-purpose EEPROM locations. This unique ID is used to support NIST
traceability. The TMP116 units are 100% tested on a production setup that is NIST traceable and verified with
equipment that is calibrated to ISO/IEC 17025 accredited standards. Only reprogram the general-purpose
EEPROM[4:1] locations if NIST traceability is not desired.
7.5.1.2 Programming the EEPROM
To prevent accidental programming, the EEPROM is locked by default. When locked, any I2C writes to the
register map locations are performed only on the volatile registers and not on the EEPROM.
图 25 illustrates a flow chart describing the EEPROM programming sequence. To program the EEPROM, first
unlock the EEPROM by setting the EUN bit in the EEPROM unlock register. After the EEPROM is unlocked, any
subsequent I2C writes to the register map locations program a corresponding non-volatile memory location in the
EEPROM. Programming a single location typically takes 7 ms to complete and consumes 230 µA. Do not
perform any I2C writes until programming is completed. During programming, the EEPROM_busy flag is set.
Read this flag to monitor if the programming is complete. After programming the desired data, issue a general-
call reset command to trigger a software reset. The programmed data from the EEPROM are then loaded to the
corresponding register map locations as part of the reset sequence. This command also clears the EUN bit and
automatically locks the EEPROM to prevent any further accidental programming. The application must avoid
temperature conversions when the EEPROM is unlocked.
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Programming (接下页)
Start
Set Bit 15 of the EEPROM
Unlock Register to 1 to Unlock
Write Desired Data to the Register
Wait 7 ms
EEPROM_Busy = 1
(Still Programming)
Read Back EEPROM_Busy
From EEPROM Unlock
Register
EEPROM_Busy = 0
(Programming Complete)
Program Another Location?
Yes
No
General-Call Reset
Read Programed Registers to Verify
End
图 25. EEPROM Programming Sequence
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Programming (接下页)
7.5.2 Pointer Register
图 26 shows the internal register structure of the TMP116. The 8-bit pointer register of the device is used to
address a given data register. The power-up reset value is 00. By default, the TMP116 reads the temperature on
power-up.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
EEPROM1 to 4
图 26. Internal Registers Structures
7.5.3 I2C and SMBus Interface
7.5.3.1 Serial Interface
The TMP116 operates as a slave device on the two-wire, SMBus and I2C interface-compatible bus. Connections
to the bus are made through the open-drain I/O lines SDA and SCL pins. The SDA and SCL pins feature
integrated spike-suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise.
The device supports the transmission protocol for fast (1 kHz to 400 kHz) mode. Register bytes are sent with the
most significant byte first, followed by the least significant byte.
7.5.3.1.1 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus is controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions.
To address a specific device, a START condition is initiated, indicated by pulling the data line (SDA) from a high-
to low-logic level when the SCL pin is high. All slaves on the bus shift in the slave address byte on the rising
edge of the clock, with the last bit indicating whether a read or write operation is intended. During the ninth clock
pulse, the slave being addressed responds to the master by generating an acknowledge and pulling the SDA pin
low.
A data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During the data
transfer, the SDA pin must remain stable when the SCL pin is high because any change in the SDA pin when the
SCL pin is high is interpreted as a START or STOP signal.
When all data are transferred, the master generates a repeated START or STOP condition. The STOP condition
is indicated by pulling the SDA pin from low to high when the SCL pin is high.
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Programming (接下页)
7.5.3.1.2 Serial Bus Address
To communicate with the TMP116, the master must first address slave devices through an address byte. The
address byte consists of seven address bits and a read-write (R/W) bit indicating the intent of executing a read or
write operation.
The TMP116 features an address pin to allow up to four devices to be addressed on a single bus. 表 2 describes
the pin connection used to properly address up to four devices. x represents the read-write (R/W) bit.
表 2. Address Pin and Slave Addresses
DEVICE ADDRESS
1001000x
ADD0 PIN CONNECTION
Ground
V+
1001001x
1001010x
SDA
SCL
1001011x
7.5.3.1.3 Writing and Reading Operation
Accessing a particular register on the TMP116 is accomplished by writing the register address to the pointer
register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP116 requires a value for the pointer register.
When reading from the TMP116, the last value stored in the pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the pointer register. This action is accomplished by issuing an address byte with the
R/W bit low, followed by the pointer register byte. No additional data are required. The master can then generate
a START condition and send the slave address byte with the R/W bit high to initiate the read command; see 图
28 for details of this sequence. If repeated reads from the same register are desired, continuously sending the
pointer register bytes is not necessary because the TMP116 retains the pointer register value until the value is
changed by the next write operation.
Register bytes are sent with the most significant byte first, followed by the least significant byte.
7.5.3.1.4 Slave Mode Operations
The TMP116 can operate as a slave receiver or slave transmitter. As a slave device, the TMP116 never drives
the SCL line.
7.5.3.1.4.1 Slave Receiver Mode
The first byte transmitted by the master is the slave address with the R/W bit low. The TMP116 then
acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The
TMP116 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the
register addressed by the pointer register. The TMP116 acknowledges reception of each data byte. The master
can terminate data transfer by generating a START or STOP condition.
7.5.3.1.4.2 Slave Transmitter Mode
The first byte transmitted by the master is the slave address with the R/W bit high. The slave acknowledges
reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of
the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The
master can terminate data transfer by generating a not-acknowledge on reception of any data byte or by
generating a START or STOP condition.
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7.5.3.1.5 SMBus Alert Function
The TMP116 supports the SMBus alert function. When the ALERT pin is connected to an SMBus alert signal and
a master senses that an alert condition is present, the master can send out an SMBus ALERT command (0001
1001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus ALERT command and
responds by returning the slave address on the SDA line. The eighth bit (LSB) of the slave address byte
indicates if the alert condition is caused by the temperature exceeding T(HIGH) or falling below T(LOW). The LSB is
high if the temperature is greater than T(HIGH), or low if the temperature is less than T(LOW); see 图 29 for details of
this sequence.
If multiple devices on the bus respond to the SMBus ALERT command, arbitration during the slave address
portion of the SMBus ALERT command determines which device clears the alert status of that device. The
device with the lowest two-wire address wins the arbitration. If the TMP116 wins the arbitration, the TMP116
ALERT pin becomes inactive at the completion of the SMBus ALERT command. If the TMP116 loses the
arbitration, the TMP116 ALERT pin remains active.
7.5.3.1.6 General-Call Reset Function
The TMP116 responds to a two-wire, general-call address (0000 000) if the eighth bit is 0. The device
acknowledges the general-call address and responds to commands in the second byte. If the second byte is
0000 0110, the TMP116 internal registers are reset to power-up values.
7.5.3.1.7 Timeout Function
The TMP116 resets the serial interface if the SCL line is held low by the master or the SDA line is held low by
the TMP116 for 35 ms (typical) between a START and STOP condition. The TMP116 releases the SDA line if
the SCL pin is pulled low and waits for a START condition from the host controller. To avoid activating the
timeout function, maintain a communication speed of at least 1 kHz for the SCL operating frequency.
7.5.3.1.8 Timing Diagrams
The TMP116 is two-wire, SMBus, and I2C interface-compatible. 图 27 to 图 30 describe the various operations on
the TMP116. Parameters for 图 1 are defined in Two-Wire Interface Timing. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the SDA line from high to low when the SCL line is high defines a
START condition. Each data transfer is initiated with a START condition.
Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a
STOP condition. Each data transfer is terminated with a repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and
is determined by the master device.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that
acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line
is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data transfer can be signaled by the master generating a
not-acknowledge (1) on the last byte transmitted by the slave.
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1
9
1
9
SCL
¼
A0
0
A1
0
P3
P2
P1
P0
SDA
1
0
0
1
R/W
0
0
0
¼
Start By
Master
ACK By
ACK By
Device
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(Continued)
ACK By
Device
ACK By
Stop By
Master
Device
Frame 3 Data Byte 1
Frame 4 Data Byte 2
图 27. Write Word Command Timing Diagram
1
9
1
9
SCL
SDA
¼
A1
A0
1
0
0
1
0
R/W
0
0
0
0
P3
P2
P1
P0
¼
Start By
ACK By
ACK By
Master
Device
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
SCL
¼
(Continued)
SDA
¼
1
0
0
1
R/W
0
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
(Continued)
Start By
Master
ACK By
From
ACK By
Master
Device
Device
Frame 3 Two-Wire Slave Address Byte
Frame 4 Data Byte 1 Read Register
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4
D3
D2
D1
D0
(Continued)
From
NACK By Stop By
Master
Device
Master
Frame 5 Data Byte 2 Read Register
图 28. Read Word Command Timing Diagram
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ALERT
1
9
1
9
SCL
SDA
0
A1(1) A0(1)
Status
0
0
0
1
1
0
0
R/W
1
0
0
1
Start By
ACK By
From
NACK By Stop By
Master
Device
Device
Master
Master
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address From Device
图 29. SMBus ALERT Timing Diagram
1
9
1
9
SCL
SDA
0
1
1
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
Start By
Master
ACK By
Device
From
Master
ACK By
Device
Stop By
Master
Frame 1 Address Byte
Frame 2 Command Byte
图 30. General-Call Reset Command Timing Diagram
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7.6 Registers Map
表 3. Register Map
ADDRESS
00h
TYPE
R
RESET
8000h
ACRONYM
REGISTER NAME
Temperature register
SECTION
Go
TEMP
01h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0220h(1)
6000h(1)
8000h(1)
0000h
0000h(1)
0000h(1)
0000h(1)
0000h(1)
1116h
CFGR
Configuration register
High limit register
Go
02h
HIGH_LIM
LOW_LIM
EEPROM_UL
EEPROM1
EEPROM2
EEPROM3
EEPROM4
DEVICE_ID
Go
03h
Low limit register
Go
04h
EEPROM unlock register
EEPROM1 register
EEPROM2 register
EEPROM3 register
EEPROM4 register
Device ID register
Go
05h
Go
06h
Go
07h
Go
08h
Go
0Fh
Go
(1) This value is stored in electrically-erasable, programmable read-only memory (EEPROM) during device manufacturing. The device reset value can be changed by writing the relevant code
in the EEPROM cells (see the EEPROM Overview section).
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7.6.1 Register Descriptions
表 4. TMP116 Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write
Write Type
W
W
Reset or Default Value
-n
Value after reset or the default value
7.6.1.1 Temperature Register (address = 00h) [default reset = 8000h]
This register is a 16-bit, read-only register that stores the output of the most recent conversion. One LSB equals
7.8125 m°C. Data are represented in binary two's complement format. Following power-up or a general-call
reset, the temperature register reads –256°C until the first conversion is complete (see the Power Up section).
图 31. Temperature Register
15
14
13
12
11
10
9
8
T15
R-1
T14
R-0
T13
R-0
T12
R-0
T11
R-0
T10
R-0
T9
T8
R-0
R-0
7
6
5
4
3
2
1
0
T7
T6
T5
T4
T3
T2
T1
T0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
表 5. Temperature Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
T[15:0]
R
8000h
16-bit, read-only register that stores the most recent temperature
conversion results.
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7.6.1.2 Configuration Register (address = 01h) [Factory default reset = 0220h]
图 32. Configuration Register
15
HIGH_Alert
R-0
14
LOW_Alert
R-0
13
Data_Ready
R-0
12
EEPROM_Busy
R-0
11
MOD1(1)
10
MOD0(2)
9
8
CONV2(2)
CONV1(2)
R/W-0
R/W-0
R/W-1
R/W-0
7
6
5
4
3
2
1
0
CONV0(2)
AVG1(2)
AVG0(2)
T/nA(2)
POL(2)
DR/Alert(2)
—
—
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R-0
R-0
(1) The MOD1 bit cannot be stored in EEPROM. The device can only be programmed to start up in shutdown mode or continuous
conversion mode.
(2) These bits can be stored in EEPROM. The factory setting for this register is 0220.
表 6. Configuration Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
HIGH_Alert
R
0
High Alert flag:
1: Set when the conversion result is higher than the high limit
0: Cleared on read of configuration register
Therm mode:
1: Set when the conversion result is higher than the therm limit
0: Cleared when the conversion result is lower than the
hysteresis
14
13
LOW_Alert
R
R
0
0
Low Alert flag:
1: Set when the conversion result is lower than the low limit
0: Cleared when the configuration register is read
Therm mode: Always set to 0
Data_Ready
Data ready flag.
This flag indicates that the conversion is complete and the
temperature register can be read. Every time the temperature
register or configuration register is read, this bit is cleared. This
bit is set at the end of the conversion when the temperature
register is updated. Data ready can be directed to the ALERT pin
by setting bit 2 of the configuration register.
12
EEPROM_Busy
MOD[1:0]
R
0
0
EEPROM busy flag.
The value 1 of the flag indicates that the EEPROM is busy during
programming or power-up.
11:10
R/W
Set Temperature conversion mode.
00: Continuous conversion (CC)
01: Shutdown (SD)
10: Continuous conversion (CC), same as 00 (reads back = 00)
11: One-shot conversion (OS)
9:7
6:5
CONV[2:0]
AVG[1:0]
R/W
R/W
100
01
Conversion cycle bit.
See 表 7 for the standby time between conversions.
Conversion averaging modes.
These bits determine the number of conversion results that are
collected and averaged before updating the temperature register.
The average is an accumulated average and not a running
average. 表 7 lists the bit settings for AVG.
4
3
T/nA
POL
R/W
R/W
R/W
R
0
0
0
0
Therm/alert mode select.
1: Therm mode
0: Alert mode
ALERT pin polarity bit.
1: Active high
0: Active low
2
DR/Alert
—
ALERT pin select bit.
1: ALERT pin reflects the status of the data ready flag
0: ALERT pin reflects the status of the alert flags
1:0
Not used
26
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表 7. Conversion Cycle Time in CC Mode
AVG[1:0] = 00
AVG[1:0] = 01
AVG[1:0] = 10
AVG[1:0] = 11
Number of averaged
1
8
32
64
samples
Active conversion time
CONV[2:0] = 000
CONV[2:0] = 001
CONV[2:0] = 010
CONV[2:0] = 011
CONV[2:0] = 100
CONV[2:0] = 101
CONV[2:0] = 110
CONV[2:0] = 111
15.5 ms
15.5 ms(1)
125 ms(2)
250 ms(2)
500 ms(2)
1 s(2)
4 s(2)
8 s(2)
16 s(2)
125 ms
125 ms(1)
125 ms(1)
250 ms(3)
500 ms(3)
1 s(3)
4 s(3)
8 s(3)
16 s(3)
500 ms
500 ms(1)
500 ms(1)
500 ms(1)
500 ms(1)
1 s(4)
4 s(4)
8 s(4)
16 s(4)
1 s
1 s(1)
1 s(1)
1 s(1)
1 s(1)
1 s(1)
4 s(5)
8 s(5)
16 s(5)
(1) In this mode there is no standby time in the conversion cycle.
(2) In this mode the standby time is the difference of the value and 15.5 ms.
(3) In this mode the standby time is the difference of the value and 125 ms.
(4) In this mode the standby time is the difference of the value and 500 ms.
(5) In this mode the standby time is the difference of the value and 1 s.
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7.6.1.3 High Limit Register (address = 02h) [Factory default reset = 6000h]
This register is a 16-bit, read/write register that stores the high limit for comparison with the temperature result.
The register format is same as the temperature register. Following power-up or a general-call reset, the high-limit
register is loaded with the stored value from the EEPROM. The factory default reset value is 6000h or 192°C.
图 33. High Limit Register
15
14
13
12
11
10
9
8
H15
H14
H13
H12
H11
H10
H9
H8
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
H7
H6
H5
H4
H3
H2
H1
H0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 8. High Limit Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
H[15:0]
R/W
6000h
16-bit, read/write register that stores the high limit for comparison
with the temperature result.
7.6.1.4 Low Limit Register (address = 03h) [Factory default reset = 8000h]
This register is configured as a 16-bit, read/write register that stores the low limit for comparison with the
temperature result. The register format is same as the temperature register. Following power-up or reset, the
low-limit register is loaded with the stored value from the EEPROM. The factory default reset value is 8000h or
–256°C.
图 34. Low Limit Register
15
L15
14
L14
13
L13
12
L12
11
L11
10
L10
9
8
L9
L8
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
L7
L6
L5
L4
L3
L2
L1
L0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 9. Low Limit Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
L[15:0]
R/W
8000h
16-bit, read/write register that stores the low limit for comparison
with the temperature result.
28
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7.6.1.5 EEPROM Unlock Register (address = 04h) [reset = 0000h]
图 35. EEPROM Unlock Register
15
14
EEPROM_Busy
R-0
13
—
12
—
11
—
10
—
9
8
EUN
R/W-0
—
—
R-0
R-0
R-0
R-0
R-0
R-0
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
表 10. EEPROM Unlock Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15
EUN
R/W
0
EEPROM unlock.
0: EEPROM is locked for programming: writes to all EEPROM
addresses (such as configuration, limits, and EEPROM locations
1-4) are written to registers in digital logic and are not
programmed in the EEPROM
1: EEPROM unlocked for programming: any writes to writable
registers program the respective location in the EEPROM
14
EEPROM_Busy
R
0
EEPROM busy. This flag is the mirror of the EEPROM busy flag
(bit 12) in the configuration register.
0: Indicates that the EEPROM is ready, which means that the
EEPROM has finished the last transaction and is ready to
accept new commands
1: Indicates that the EEPROM is busy, which means that the
EEPROM is currently completing a programming operation or
performing power-up on reset load
13:0
—
R
0
Not used
7.6.1.6 EEPROM1 Register (address = 05h) [reset = XXXXh]
The EEPROM1 register is a 16-bit register that be used as a scratch pad by the customer to store general-
purpose data. This register has a corresponding EEPROM location. Writes to this address when the EEPROM is
locked write data into the register and not to the EEPROM. Writes to this register when the EEPROM is unlocked
causes the corresponding EEPROM location to be programmed; see the Programming the EEPROM section.
EEPROM[4:1] are preprogrammed during manufacturing with the unique ID that can be overwritten. In order to
support NIST traceability, do not delete or reprogram EEPROM[4:1].
图 36. EEPROM1 Register
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
表 11. EEPROM1 Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
D[15:0]
R/W
xxxxh
This 16-bit register can be used as a scratch pad by the
customer.
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7.6.1.7 EEPROM2 Register (address = 06h) [reset = XXXXh]
This register function the same as the EEPROM1 register.
图 37. EEPROM2 Register
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
表 12. EEPROM2 Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
D[15:0]
R/W
xxxxh
This 16-bit register can be used as a scratch pad by the
customer.
7.6.1.8 EEPROM3 Register (address = 07h) [reset = 0000h]
This register function is the same as the EEPROM1 register.
图 38. EEPROM3 Register
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 13. EEPROM3 Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
D[15:0]
R/W
0
This 16-bit register can be used as a scratch pad by the
customer.
30
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7.6.1.9 EEPROM4 Register (address = 08h) [reset = XXXXh]
This register function is the same as the EEPROM1 register.
图 39. EEPROM4 Register
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
表 14. EEPROM4 Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
D[15:0]
R/W
xxxxh
This 16-bit register can be used as a scratch pad by the
customer.
7.6.1.10 Device ID Register (address = 0Fh) [reset = 1116h]
This read-only register indicates the device ID.
图 40. Device ID Register
15
DID15
R-0
14
DID14
R-0
13
DID13
R-0
12
DID12
R-1
11
DID11
R-0
10
DID10
R-0
9
8
DID9
R-0
DID8
R-1
7
6
5
4
3
2
1
0
DID7
R-0
DID6
R-0
DID5
R-0
DID4
R-1
DID3
R-0
DID2
R-1
DID1
R-1
DID0
R-0
表 15. Device ID Register Field Descriptions
BIT
15:0
FIELD
TYPE
RESET
DESCRIPTION
DID[15:0]
R
1116h
These bits indicate the device ID.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP116 is used to measure the temperature of the board location where the device is mounted. The
programmable address options allow up to four locations on the board to be monitored on a single serial bus.
8.1.1 Typical Application
1.9 V to 5.5 V
5 kꢀ
5 kꢀ
5 kꢀ
1
6
3
5
2
4
SCL
SDA
SCL
V+
GND
0.1 …F
SDA
TMP116
2-Wire Interface SMBus,
I²C Compatible Controller
GND
ALERT
ADD0
INT
GND
GND
GND
NOTE: The SDA and ALERT pins require pullup resistors.
图 41. Typical Connections
8.1.1.1 Design Requirements
The TMP116 operates only as a slave device and communicates with the host through the I2C-compatible serial
interface. SCL is the input pin, SDA is a bidirectional pin, and ALERT is the output. The TMP116 requires a
pullup resistor on the SCL, SDA, and ALERT pins. The recommended value for the pullup resistors is 5 kΩ. In
some applications the pullup resistor can be lower or higher than 5 kΩ. A 0.1-µF bypass capacitor is
recommended to be connected between V+ and GND. An SCL pullup resistor is required if the system
microprocessor SCL pin is open-drain. Use a ceramic capacitor type with according temperature range, placed
as close as possible to the V+ pin of the TMP116. The ALERT output pin can be connected to a microcontroller
interrupt that triggers an event that occurred when the temperature limit exceeds the programmable value or
indicates conversion end. It is recommended that the ALERT pin be connected to ground.
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Application Information (接下页)
8.1.1.2 Detailed Design Procedure
8.1.1.2.1 Noise and Averaging
The device temperature sampling distribution (without internal averaging) covers an area of approximately six
neighboring codes. The noise area of the six codes remains the same at full supply and full temperature range
with a standard deviation of approximately 1 LSB. The device provides an averaging tool for 8, 32, and 64
samples. As illustrated in 图 7, even the 8-sample averaging reduces the internal noise distribution to a
theoretical minimum of 2 LSB. This averaging means that if the system temperature slowly changes and the
supply voltage is stable, then the 8-sample averaging can be enough to neutralize the device internal noise and
provide stable temperature readings. However, if the system temperature is noisy (such as when measuring air
flow temperatures) or noisy power supply line or intensive communication in the I2C line, then higher averaging
numbers are recommended to be used.
8.1.1.2.2 Self-Heating Effect (SHE)
During ADC conversion some power is dissipated that heats the device despite the small power consumption of
the TMP116. Consider the self-heating effect (SHE) for certain precise measurements. 图 42 shows the device
SHE in still air at 25°C after the supply is switched on. The device package, is soldered to the 11-mm × 20-mm ×
1.1-mm size coupon board. The board is located horizontally, with the device on top. The TMP116 is in
continuous conversion mode with 64 sampling averaging and zero conversion cycle time. There is no digital bus
activity aside from reading temperature data one time each second. As shown in 图 42, the SHE stabilization
time in still air is greater when the device dissipates more power.
70
60
50
40
30
20
10
1.9 V
3 V
4 V
5 V
5.5 V
0
0
10
20
30
40
50
60
70
80
90
Time (Sec)
图 42. Self-Heating in Still Air vs. Temperature and Dissipated Power
The SHE drift is strongly proportional to the device dissipated power. The SHE drift is also proportional to the
device temperature because the consumption current with the same supply voltage increases with temperature.
图 43 shows the SHE drifts versus temperature and dissipated power at 25°C for the same coupon board and
the same conditions described previously.
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Application Information (接下页)
90
80
70
60
50
40
30
20
10
0
700 uWt
630 uWt
500 uWt
410 uWt
370 uWt
225 uWt
-50
-25
0
25
50
75
100 125 150 175
Temperature (èC)
图 43. Self-Heating in Still Air vs. Temperature and Dissipated Power at 25°C
To estimate the SHE for similar size boards, calculate the device consumption power for 25°C and use the
corresponding power line shown in 图 43. For example, in CC mode without duty cycle at a 3.3-V supply at 25°C,
the device dissipates 410 µWt. So self-heating in still air is approximately 40 m°C for the described condition and
rises to 52 m°C at 150°C.
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Application Information (接下页)
The following methods can reduce the SHE:
•
System calibration removes not only the self-heating error and power-supply rejection ratio (PSRR) effect but
also compensates the temperature shift caused by the thermal resistance between the device and the
measured object.
•
If practical, use the device one-shot mode. If continuous conversion is needed, use the conversion cycle
mode with significant standby time. For example, in most cases an 8-sample averaging (125 ms) with a 1-
second conversion cycle provides enough time for the device to cool down to the environment temperature
and removes the SHE.
•
•
•
Use the minimal acceptable power supply voltage.
Use a printed-circuit board (PCB) layout that provides minimal thermal resistance to the device.
Avoid using small-value pullup resistors on the SDA and ALERT pins. Instead, use pullup resistors larger than
2 kΩ.
•
•
Ensure that the SCL and SDA signal levels remain below 10% or above 90% of the device supply voltage.
Avoid heavy bypass traffic on the data line. Communication to other devices on the same data line increases
the supply current even if the device is in SD mode.
•
Use the highest available communication speed.
8.1.1.2.3 Synchronized Temperature Measurements
When four temperature measurements are needed in four different places simultaneously, triggering by reset is
recommended. In this method, four devices are programed with control registers set to CC mode with a
conversion cycle time of 16 s. All four devices are connected to same two-wire bus with four different bus
addresses. The bus general-call reset command is issued by the master. This command triggers all devices to
reset (which takes approximately 1.5 ms) and triggers a simultaneous temperature sampling according to
configuration registers setting. The master has 16 seconds to read data from the devices.
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9 Power Supply Recommendations
The TMP116 operates on a power-supply range from 1.9 V to 5.5 V. The device is trimmed for operation at a
3.3-V supply, but can measure temperature accurately in the full supply range. A power-supply bypass capacitor
is required, which must be placed as close as possible to the device. A recommended value for this supply
bypass capacitor is 100 nF. Applications with noisy or high-impedance power supplies may require additional
decoupling capacitors to reject power-supply noise.
The TMP116 is a very low-power device and generates low noise on the supply bus. Applying an RC filter to the
V+ pin of the device can further reduce any noise that the TMP116 might propagate to other components. RF in
图 44 must be less than 0.5 kΩ and CF must be at least 100 nF. Take care that the V+ pin voltage is not less
than 1.9 V. The package thermal pad is not connected to the device ground and should be left unsoldered for the
best measurement accuracy. If the thermal pad is soldered it must be left floating or connected to ground.
1.9 V to 5.5 V
TI Device
SCL
SDA
0.5 kΩ
GND
V+
CF ≥ 100 nF
ALERT
ADD0
Copyright © 2017, Texas Instruments Incorporated
图 44. Noise-Reduction Techniques
10 Layout
10.1 Layout Guidelines
注
To achieve a high precision temperature reading for a rigid PCB, do not solder down the
thermal pad. For a flexible PCB, the user can solder the thermal pad to increase board
level reliability. If thermal pad is soldered it should be connected to the ground or left
floating.
For more information on board layout, refer to the related Precise Temperature Measurements With TMP116
(SNOA986) and Wearable Temperature Sensing Layout Considerations Optimized for Thermal Response
(SNIA021) application reports on ti.com.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended
value of this bypass capacitor is 0.1 μF. In some cases, the pullup resistor can be the heat source, therefore,
maintain some distance between the resistor and the device.
Mount the TMP116 on the PCB pad to provide the minimum thermal resistance to the measured object surface
or to the surrounding air. The PCB layout should minimize the device self-heating effect, reduce the time delay
as temperature changes, and minimize the temperature offset between the device and the measured object.
1. Soldering the TMP116 thermal pad to the PCB minimizes the thermal resistance to the PCB, reduces the
response time as temperature changes and minimizes the temperature offset between the device and
measured object. Simultaneously the soldering of the thermal pad will, however, introduce mechanical stress
that can be a source of additional measurement error. For cases when system calibration is not planned, TI
recommends not soldering the thermal pad to the PCB. Due to the small thermal mass of the device, not
soldering the thermal pad will have a minimal impact on the described characteristics. Manual device
soldering to PCB creates additional mechanical stress to package, therefore to prevent precision degradation
36
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Layout Guidelines (接下页)
a standard PCB reflow oven process is highly recommended.
2. If the device is used to measure solid surface temperature:
–
–
–
–
–
–
–
–
Use PCB with minimal thickness.
Prevent PCB bending which can create a mechanical stress to package.
Cover bottom of the PCB with copper plane.
Remove bottom solder mask and cover exposed copper with gold layer if possible.
Use thermal conductive paste between PCB and object surface.
If PCB has unused internal layers, extend these layers under the sensor.
Minimize amount of copper wires on top of the board.
To minimize temperature “leakage” to surrounding air locate sensor in place with minimal air movement.
Horizontal surfaces are preferable.
–
To minimize temperature offset due to “leakage” to surrounding air cover sensor with thermo isolating
foam, tape or at least cover with a stain.
3. If the device is used to measure moving air temperature:
–
Because moving air temperature usually has a lot of fluctuations the PCB increased thermal mass
reduces measurement noise.
–
–
–
–
Design PCB soldering pads bigger than usual, especially package corner pads.
Use a PCB with thicker copper layers if possible.
Cover both side of unused board space with copper layer.
Place PCB vertically along air flow.
4. If the device is used to measure still air temperature:
–
–
–
–
–
–
–
Miniaturize the board to reduce thermal mass. Smaller thermal mass results in faster thermal response.
Place two copper planes of equal size to the top and bottom of the exposed pad.
Remove the top solder mask.
To prevent oxidation, cover any exposed copper with solder paste.
Thermal isolation is required to avoid thermal coupling from heat source components through the PCB.
Avoid running the copper plane underneath the temperature sensor.
Maximize the air gap between the sensor and the surrounding copper areas (anti-etch), especially when
close to the heat source.
–
Create a PCB cutout between sensor and other circuits. Leave a narrow channel away from heat source
components as a routing bridge into the island.
–
–
If the heat source is top side, avoid running traces on top; instead, route all signals on the bottom side.
Place the board vertically to improve air flow and to reduce dust collection.
版权 © 2017–2019, Texas Instruments Incorporated
37
TMP116, TMP116N
ZHCSG96A –MAY 2017–REVISED MAY 2019
www.ti.com.cn
10.2 Layout Example
VIA to Power or Ground Plane
VIA to Internal Layer
1.9 V to 5.5 V
5 kꢁ
5 kꢁ
5 kꢁ
MCU INT
I²C Bus
SCL
SDA
V+
1
2
3
6
5
4
GND
Exposed
Thermal Pad
0.1 ꢀF
ALERT
ADD0
图 45. Layout Recommendation
38
版权 © 2017–2019, Texas Instruments Incorporated
TMP116, TMP116N
www.ti.com.cn
ZHCSG96A –MAY 2017–REVISED MAY 2019
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
德州仪器 (TI)，《TMP116 环境空气温度测量》应用报告 (SNOA966)
德州仪器 (TI)，《使用 TMP116 温度传感器替代电阻式温度检测器》应用报告 (SNOA969)
德州仪器 (TI)，《温度传感器：表面贴装器件的 PCB 指南》应用报告 (SNOA967)
德州仪器 (TI)，《使用 TMP116 进行精确的温度测量》应用报告 (SNOA986)
德州仪器 (TI)，《针对热响应优化的可穿戴温度检测布局的注意事项》应用报告 (SNIA021)
德州仪器 (TI)，具有 I2C 和 SMBus 接口且采用行业标准 LM75 外形尺寸和引脚输出的 TMPx75 温度传感器数
据表 (SBOS288)
•
德州仪器 (TI)，《具有 I2C 和 SMBus 接口且采用行业标准 LM75 外形尺寸和引脚输出的 TMP275 ±0.5°C 温度
传感器》数据表 (SBOS363)
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
SMBus is a trademark of Intel Corporation.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2019, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP116AIDRVR
TMP116AIDRVT
TMP116NAIDRVR
TMP116NAIDRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
6
6
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
T116
T116
116N
116N
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-May-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP116AIDRVR
TMP116AIDRVT
TMP116NAIDRVR
TMP116NAIDRVT
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
6
6
6
6
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-May-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMP116AIDRVR
TMP116AIDRVT
TMP116NAIDRVR
TMP116NAIDRVT
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
6
6
6
6
3000
250
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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