TMP320C6202GJC100 [TI]
FIXED-POINT DIGITAL SIGNAL PROCESSOR; 定点数字信号处理器
| 型号： | TMP320C6202GJC100 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 文件： | 总70页 (文件大小：1074K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
D
D
High-Performance Fixed-Point Digital
Signal Processor (DSP) − TMS320C6205
− 5-ns Instruction Cycle Time
− 200-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 1600 MIPS
D
32-Bit/33-MHz
Interconnect (PCI) Master/Slave Interface
Conforms to:
Peripheral
Component
PCI Specification 2.2
Power Management Interface 1.1
Meets Requirements of PC99
− PCI Access to All On-Chip RAM,
Peripherals, and External Memory
(via EMIF)
− Four 8-Deep x 32-Wide FIFOs for
Efficient PCI Bus Data Transfer
− 3.3/5-V PCI Operation
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Supports 4-Wire Serial EEPROM
Interface
VelociTI Advanced-Very-Long-Instruction-
Word (VLIW) TMS320C62x DSP Core
− Eight Highly Independent Functional
Units:
− Six ALUs (32-/40-Bit)
− Two 16-Bit Multipliers (32-Bit Result)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
D
D
Instruction Set Features
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle
D
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
− Normalization
1M-Bit On-Chip SRAM
− 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
− 512K-Bit Dual-Access Internal Data
(64K Bytes)
− Organized as Two 32K-Byte Blocks for
Improved Concurrency
D
D
D
D
D
Two 32-Bit General-Purpose Timers
†
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Synchronous
Memories: SDRAM or SBSRAM
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− 52M-Byte Addressable External Memory
Space
288-Pin MicroStar BGA Package
(GHK Suffix)
0.15-µm/5-Level Metal Process
− CMOS Technology
3.3-V I/Os, 1.5-V Internal, 5-V Voltage
Tolerance for PCI I/O Pins
D
D
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
Flexible Phase-Locked-Loop (PLL) Clock
Generator
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Table of Contents
GHK BGA package (bottom view) . . . . . . . . . . . . . . . . . . . 3
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
functional and CPU (DSP core) block diagram . . . . . . . . . 6
CPU (DSP core) description . . . . . . . . . . . . . . . . . . . . . . . . 7
memory map summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . 10
parameter measurement information . . . . . . . . . . . . . . . 34
input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 37
synchronous-burst memory timing . . . . . . . . . . . . . . . . . 40
synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 42
HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCI I/O timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PCI reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PCI serial EEPROM interface timing . . . . . . . . . . . . . . . 52
multichannel buffered serial port timing . . . . . . . . . . . . . 53
DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 63
JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
power-down mode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
power-supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 31
absolute maximum ratings over operating case
temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
recommended operating conditions . . . . . . . . . . . . . . . . . 32
recommended operating conditions (PCI only) . . . . . . . . 32
electrical characteristics over recommended
rangesof supply voltage and operating
case temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
electrical characteristics over recommended ranges
of supply voltage and operating case
temperature (PCI only) . . . . . . . . . . . . . . . . . . . . . . . 33
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
GHK BGA package (bottom view)
GHK 288-PIN BALL GRID ARRAY (BGA) PACKAGE
(BOTTOM VIEW)
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
description
The TMS320C62x DSPs (including the TMS320C6205 device) compose the fixed-point DSP generation in
the TMS320C6000 DSP platform. The TMS320C6205 (C6205) device is based on the high-performance,
advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI),
making the C6205 an excellent choice for multichannel and multifunction applications.
With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6205
offers cost-effective solutions to high-performance DSP-programming challenges. The C6205 DSP possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. This
processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.
The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit
multipliers for a 32-bit result. The C6205 can produce two multiply-accumulates (MACs) per cycle for a total of
400 million MACs per second (MMACS). The C6205 DSP also has application-specific hardware logic, on-chip
memory, and additional on-chip peripherals.
The C6205 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a peripheral component interconnect (PCI) module that
supports 33-MHz master/slave interface and 4-wire serial EEPROM interface, and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The C6205 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
TMS320C6000 is a trademark of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
device characteristics
Table 1 provides an overview of the C6205 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc.
Table 1. Characteristics of the C6205 Processor
HARDWARE FEATURES
EMIF
C6205
1
DMA
4-Channel With Throughput Enhancements
PCI
1
Peripherals
McBSPs
2
32-Bit Timers
Size (Bytes)
Organization
Size (Bytes)
Organization
2
64K
Internal Program Memory
Internal Data Memory
1 Block: 64K Bytes Cache/Mapped Program
64K
2 Blocks: Four 16-Bit Banks per Block, 50/50 Split
CPU ID+Rev ID
Frequency
Control Status Register (CSR.[31:16])
0x0003
MHz
200
Cycle Time
ns
5 ns (C6205-200)
Core (V)
1.5
I/O (V)
3.3
Voltage
Voltage Tolerance for PCI I/O Pins (V)
5.0
PLL Options
CLKIN frequency multiplier
Bypass (x1), x4, x6, x7, x8, x9, x10, and x11
288-Pin MicroStar BGA (GHK)
0.15 µm
BGA Package
16 x 16 mm
Process Technology
µm
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
Product Status
PD
(For more details on the C6000 DSP part
numbering, see Figure 4)
Device Part Numbers
TMX320C6205GHK
C6000 is a trademark of Texas Instruments.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
functional and CPU (DSP core) block diagram
C6205 Digital Signal Processor
SDRAM or
SBSRAM
Internal Program Memory
1 Block Program/Cache
(64K Bytes)
Program
Access/Cache
Controller
32
SRAM
External Memory
Interface (EMIF)
ROM/FLASH
I/O Devices
C62x DSP Core
Timer 0
Timer 1
Instruction Fetch
Instruction Dispatch
Instruction Decode
Control
Registers
Control
Logic
Multichannel
Buffered Serial
Port 0
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
Data Path A
Data Path B
Test
A Register File
B Register File
In-Circuit
Emulation
Multichannel
Buffered Serial
Port 1
Interrupt
Control
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Selector
Peripheral Control Bus
Internal Data
Memory
Data
Access
Controller
(64K Bytes)
2 Blocks of 4 Banks
Each
EEPROM
Direct Memory
Access Controller
(DMA)
Power-
Down
Logic
(4 Channels)
Master/Slave
PCI Interface
32
PLL
Boot Configuration
(x1, x4, x6, x7, x8,
x9, x10, x11)
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
CPU (DSP core) description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see the Functional and CPU (DSP Core) Block
Diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers
belonging to that side. Additionally, each side features a single data bus connected to all the registers on the
other side, by which the two sets of functional units can access data from the register files on the opposite side.
While register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle, register access using the register file across the CPU supports one read and one write
per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
256-bit wide fetch-packet boundary, the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
CPU (DSP core) description (continued)
src1
src2
.L1
dst
long dst
long src
8
8
32
ST1
8
long src
long dst
dst
Register
File A
(A0−A15)
Data Path A
.S1
src1
src2
dst
src1
.M1
.D1
src2
LD1
dst
src1
src2
DA1
2X
1X
src2
src1
dst
DA2
LD2
.D2
src2
.M2
.S2
src1
dst
src2
Register
File B
(B0−B15)
Data Path B
src1
dst
long dst
long src
8
32
8
ST2
8
long src
long dst
dst
.L2
src2
src1
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
memory map summary
Table 2 shows the memory map address ranges of the C6205 device. The C6205 device has the capability of
a MAP 0 or MAP 1 memory block configuration. The maps differ in that MAP 0 has external memory mapped
at address 0x0000 0000 and MAP 1 has internal memory mapped at address 0x0000 0000. These memory
block configurations are set up at reset by the boot configuration pins (generically called BOOTMODE[4:0]). For
the C6205 device, the BOOTMODE configuration is handled, at reset, by the expansion bus module (specifically
XD[4:0] pins). For more detailed information on the C6205 device settings, which include the device boot mode
configuration at reset and other device-specific configurations, see TMS320C620x/C670x DSP Boot Modes
and Configuration (literature number SPRU642).
Table 2. TMS320C6205 Memory Map Summary
MEMORY BLOCK DESCRIPTION
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
MAP 0
MAP 1
Internal Program RAM
Reserved
External Memory Interface (EMIF) CE0
EMIF CE0
64K
4M – 64K
12M
0000 0000 – 0000 FFFF
0001 0000 – 003F FFFF
0040 0000 – 00FF FFFF
0100 0000 – 013F FFFF
0140 0000 – 0140 FFFF
0141 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01A8 FFFF
01A9 0000 – 01FF FFFF
0200 0000 – 02FF FFFF
0300 0000 – 03FF FFFF
0400 0000 – 7FFF FFFF
8000 0000 – 8000 FFFF
8001 0000 – FFFF FFFF
EMIF CE0
EMIF CE0
EMIF CE1
EMIF CE0
4M
Internal Program RAM
Reserved
EMIF CE1
64K
EMIF CE1
4M – 64K
256K
EMIF Registers
DMA Controller Registers
Reserved
256K
256K
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
Interrupt Selector Registers
Reserved
256K
256K
256K
256K
256K
256K
PCI Registers
320K
Reserved
6M – 576K
16M
EMIF CE2
EMIF CE3
16M
Reserved
2G – 64M
64K
Internal Data RAM
Reserved
2G – 64K
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
signal groups description
CLKIN
CLKOUT2
CLKMODE0
RESET
NMI
PLLV
PLLG
PLLF
Clock/PLL
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
Reset and
Interrupts
INUM3
INUM2
INUM1
INUM0
TMS
TDO
TDI
IEEE Standard
1149.1
(JTAG)
Emulation
TCK
TRST
EMU1
EMU0
DMAC3
DMAC2
DMAC1
DMAC0
DMA Status
RSV11
RSV10
RSV9
RSV8
RSV7
Power-Down
Status
PD
RSV6
RSV5
RSV4
Reserved
RSV3
RSV2
RSV1
RSV0
Control/Status
Figure 2. CPU (DSP Core) Signals
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
signal groups description (continued)
ARE
AOE
AWE
ARDY
Asynchronous
32
ED[31:0]
Data
Memory
Control
CE3
CE2
CE1
CE0
Memory Map
Space Select
SDA10
Synchronous
SDRAS/SSOE
Memory
SDCAS/SSADS
Control
20
SDWE/SSWE
EA[21:2]
Word Address
Byte Enables
BE3
BE2
BE1
BE0
HOLD
HOLDA
HOLD/
HOLDA
EMIF
(External Memory Interface)
TOUT1
TINP1
TOUT0
TINP0
Timer 1
Timer 0
Timers
McBSP1
Transmit
McBSP0
Transmit
CLKX1
FSX1
DX1
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
CLKR0
FSR0
DR0
Receive
Clock
Receive
Clock
CLKS1
CLKS0
McBSPs
(Multichannel Buffered Serial Ports)
Figure 3. Peripheral Signals
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
signal groups description (continued)
32
AD[31:0]
Data/Address
Clock
PCLK
PIDSEL
PDEVSEL
PFRAME
PINTA
PPAR
PRST
PCBE3
PCBE2
PCBE1
PCBE0
Command
Byte Enable
Control
PIRDY
PSTOP
PTRDY
PGNT
PREQ
Arbitration
PSERR
PPERR
Error
PME
3.3VauxDET
PWR_WKP
3.3Vaux
XSP_DO
XSP_CS
XSP_CLK
XSP_DI
Serial
EEPROM
Control
Power
Management
PCI Interface
Figure 3. Peripheral Signals (Continued)
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
CLOCK/PLL
CLKIN
J3
I
Clock Input
Clock output at half of device speed
DUsed for synchronous memory interface
Clock mode select 0
CLKOUT2
T19
O
DSelects whether the on-chip PLL is used or bypassed. For more details, see the Clock PLL section.
CLKMODE0
L3
I
DThe PLL Multiply Factor is selected at boot configuration. For more details, see the EMIF − Data
pin descriptions and the clock PLL section.
‡
§
PLLV
K5
L2
L1
A
PLL analog V connection for the low-pass filter
CC
‡
§
PLLG
A
PLL analog GND connection for the low-pass filter
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
‡
§
PLLF
A
TMS
TDO
TDI
E17
D19
D18
D17
C19
E18
F15
I
JTAG test-port mode select (features an internal pullup)
JTAG test-port data out
O/Z
I
I
I
JTAG test-port data in (features an internal pullup)
JTAG test-port clock
TCK
TRST
EMU1
EMU0
JTAG test-port reset (features an internal pulldown)
¶
I/O/Z
I/O/Z
Emulation pin 1, pullup with a dedicated 20-kΩ resistor
¶
Emulation pin 0, pullup with a dedicated 20-kΩ resistor
RESET AND INTERRUPTS
Device reset
RESET
NMI
C3
A8
I
I
Nonmaskable interrupt
DEdge-driven (rising edge)
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
B15
C15
A16
B16
A15
F12
A14
B14
C14
External interrupts
I
DEdge-driven
DPolarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
Active interrupt identification number
INUM2
O
DValid during IACK for all active interrupts (not just external)
INUM1
DEncoding order follows the interrupt-service fetch-packet ordering
INUM0
POWER-DOWN STATUS
PD
B18
O
Power-down modes 2 or 3 (active if high)
†
‡
§
¶
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
PCI INTERFACE
PCLK
W5
D2
E3
E2
E1
F3
I
PCI input clock
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
F5
F1
G3
H3
H2
J1
H1
M2
M1
N2
N1
T1
I/O/Z
PCI Data-Address bus
V2
U2
U1
W3
W2
V1
U4
W4
U5
V5
U6
V6
V3
W6
U7
G2
M3
T2
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PCBE3
PCBE2
PCBE1
PCBE0
I/O/Z
PCI command/byte enable signals
V4
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
PCI INTERFACE (CONTINUED)
PCI interrupt A
PINTA
C1
F2
O/Z
O/Z
O/Z
PREQ
PSERR
PPERR
PRST
PCI bus request (bus arbitration)
PCI system error
PCI parity error
P5
P2
I/O/Z
C2
R2
D1
N5
P1
I
I/O/Z
I
PCI reset
PDEVSEL
PGNT
PCI device select
PCI bus grant (bus arbitration)
PCI frame
PFRAME
PIRDY
I/O/Z
I/O/Z
I/O/Z
I
PCI initiator ready
PCI parity
PPAR
T3
PIDSEL
PSTOP
PTRDY
XSP_CLK
XSP_DI
XSP_DO
XSP_CS
H5
R1
N3
C17
C18
B19
C11
PCI initialization device select
PCI stop
I/O/Z
I/O/Z
O
PCI target ready
Serial EEPROM clock
I
Serial EEPROM data in, pulldown with a dedicated 20-kΩ resistor
Serial EEPROM data out
O
O
Serial EEPROM chip select
3.3-V auxiliary power supply detect.
3.3VauxDET
B1
I
Used to indicate the presence of 3.3Vaux. A weak pulldown must be implemented to this pin.
3.3-V auxiliary power supply voltage
3.3Vaux
PME
B2
D3
A2
S
O
I
Power management event
PWR_WKP
Power wakeup signal
EMIF − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
CE2
CE1
CE0
BE3
BE2
BE1
BE0
V18
U17
W18
V17
U16
W17
V16
W16
Memory space enables
O/Z
DEnabled by bits 24 and 25 of the word address
DOnly one asserted during any external data access
Byte-enable control
DDecoded from the two lowest bits of the internal address
DByte-write enables for most types of memory
O/Z
DCan be directly connected to SDRAM read and write mask signal (SDQM)
EMIF − ADDRESS
EA21
EA20
EA19
EA18
EA17
V7
W7
U8
V8
O/Z
External address (word address)
W8
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
EMIF − ADDRESS (CONTINUED)
NO.
EA16
W9
V9
EA15
EA14
EA13
EA12
EA11
EA10
EA9
U9
W10
V10
U10
W11
V11
U11
R11
W12
U12
R12
W13
V13
O/Z
External address (word address)
EA8
EA7
EA6
EA5
EA4
EA3
EA2
EMIF − DATA
ED31
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
ED13
ED12
ED11
ED10
ED9
F14
E19
F17
G15
F18
F19
G17
G18
G19
H17
H18
H19
J18
External data
DUsed for transfer of EMIF data
DAlso controls initialization of DSP modes at reset via pullup/pulldown resistors
ED31
ED27
ED23
ED15
ED8
-
-
-
-
-
PLL_Conf2
PLL_Conf1
PLL_Conf0
EEPROM autoinitialization
Endianness
I/O/Z
J19
ED[7:5] - EEPROM size
ED[4:0] - Bootmode
K15
K17
K18
K19
L17
L18
L19
M19
M18
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
EMIF − DATA (CONTINUED)
NO.
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
M17
N19
P19
N15
P18
P17
R19
R18
R17
I/O/Z
External data
EMIF − ASYNCHRONOUS MEMORY CONTROL
Asynchronous memory read-enable
ARE
AOE
AWE
U14
W14
V14
O/Z
O/Z
O/Z
I
Asynchronous memory output-enable
Asynchronous memory write-enable
Asynchronous memory ready input
ARDY
W15
EMIF − SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SDA10
U19
V19
U18
T17
O/Z
O/Z
O/Z
O/Z
SDRAM address 10 (separate for deactivate command)
SDRAM column-address strobe/SBSRAM address strobe
SDRAM row-address strobe/SBSRAM output-enable
SDRAM write-enable/SBSRAM write-enable
EMIF − BUS ARBITRATION
SDCAS/SSADS
SDRAS/SSOE
SDWE/SSWE
HOLD
P14
V15
I
Hold request from the host
HOLDA
O
Hold-request-acknowledge to the host
TIMER 0
TOUT0
TINP0
E5
C5
O
I
Timer 0 or general-purpose output
Timer 0 or general-purpose input
Timer 1
TOUT1
TINP1
A5
B5
O
I
Timer 1 or general-purpose output
Timer 1 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3
DMAC2
DMAC1
DMAC0
A17
B17
C16
A18
O
DMA action complete
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
CLKR0
CLKX0
DR0
A12
B9
I
External clock source (as opposed to internal)
Receive clock
I/O/Z
I/O/Z
I
C9
Transmit clock
A10
B10
E10
A9
Receive data
DX0
O/Z
I/O/Z
I/O/Z
Transmit data
FSR0
FSX0
Receive frame sync
Transmit frame sync
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
NO.
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
External clock source (as opposed to internal)
Receive clock
CLKS1
C6
B6
E6
A7
B7
C7
A6
I
CLKR1
CLKX1
DR1
I/O/Z
I/O/Z
I
Transmit clock
Receive data
DX1
O/Z
I/O/Z
I/O/Z
Transmit data
FSR1
FSX1
Receive frame sync
Transmit frame sync
RESERVED FOR TEST
RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
RSV10
RSV11
C8
A4
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
Reserved (leave unconnected, do not connect to power or ground)
SUPPLY VOLTAGE PINS
I
K3
I
L5
O
O
O
O
O
O
O
O
O
T18
A3
B3
B4
C4
K2
J17
N18
B8
E7
E8
E9
E11
E13
H14
K14
L15
M14
P15
R8
DV
S
3.3-V I/O supply voltage
DD
R9
R10
R13
R14
U15
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
NO.
B12
E14
F9
F10
G5
H15
J2
J5
CV
S
1.5-V core supply voltage
DD
J15
M5
M15
N17
P6
P9
P12
U13
PCI SUPPLY VOLTAGE PINS
G1
P3
U3
F6
J6
V
V
S
S
3.3/5-V PCI clamp pins
IOP
L6
R3
R6
R7
3.3-V PCI power supply pins
DDP
GROUND PINS
A11
A13
B11
B13
C10
C12
C13
E12
G7
V
SS
GND
Ground pins
G8
G9
G10
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NAME
NO.
G11
G12
G13
H7
H8
H9
H10
H11
H12
H13
J7
J8
J9
J10
J11
J12
J13
K1
K7
K8
V
SS
GND
Ground pins
K9
K10
K11
K12
K13
L7
L8
L9
L10
L11
L12
L13
M7
M8
M9
M10
M11
M12
M13
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Signal Descriptions (Continued)
SIGNAL
NAME
†
TYPE
DESCRIPTION
GROUND PINS (CONTINUED)
NO.
N7
N8
N9
N10
N11
N12
N13
V12
V
SS
GND
Ground pins
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 DSP family member devices, including documentation. See
this document for further information on TMS320 DSP documentation or any TMS320 DSP support products
from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide
(SPRU052), contains information about TMS320 DSP-related products from other companies in the industry.
To receive TMS320 DSP literature, contact the Literature Response Center at 800/477-8924.
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and select
“Find Development Tools”. For device-specific tools, under “Semiconductor Products” select “Digital Signal
Processors”, choose a product family, and select the particular DSP device. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.
22
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GHK), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -200 is 200 MHz).
Figure 4 provides a legend for reading the complete device name for any TMS320C6000 DSP family member.
For the C6205 device orderable part numbers (P/Ns), see the Texas Instruments web site on the Worldwide
web at http://www.ti.com URL, or contact the nearest TI field sales office, or authorized distributor.
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
device and development-support tool nomenclature (continued)
(
)
TMS 320
C
6205 GHK
200
PREFIX
DEVICE SPEED RANGE
TMX= Experimental device
100 MHz
120 MHz
150 MHz
167 MHz
200 MHz
233 MHz
250 MHz
300 MHz
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
=
−40°C to 105°C, extended temperature
DEVICE FAMILY
320 = TMS320t DSP family
†
PACKAGE TYPE
GFN = 256-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
GLW = 340-pin plastic BGA
GHK = 288-pin plastic MicroStar BGAt
TECHNOLOGY
C = CMOS
DEVICE
C6000 DSP:
6201
6204
6205
6211
6211B
6414
6415
6416
6701
6711
6712
6202
6202B
6203
†
BGA
=
Ball Grid Array
Figure 4. TMS320C6000 DSP Platform Device Nomenclature (Including the TMS320C6205 Device)
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
documentation support
Extensive documentation supports all TMS320 DSP family devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices and tools; technical briefs;
development-support tools; on-line help; and hardware and software applications. The following is a brief,
descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 DSP core (CPU) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) briefly
describes the functionality of the peripherals available on the C6000 DSP platform of devices, such as the
64-/32-/16-bit external memory interfaces (EMIFs), 32-/16-bit host-port interfaces (HPIs), multichannel buffered
serial ports (McBSPs), direct memory access (DMA), enhanced direct-memory-access (EDMA) controller,
expansion bus (XB), peripheral component interconnect (PCI), clocking and phase-locked loop (PLL); and
power-down modes.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x
devices, associated development tools, and third-party support.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of the latest C6000 DSP documentation, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
See the Worldwide Web URL for the new How to Begin Development with the TMS320C6205 DSP application
report (literature number SPRA596) which describes the functionalities unique to the C6205 device, especially
the peripheral component interconnect (PCI) module interface.
C62x and C67x are trademarks of Texas Instruments.
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
clock PLL
Most of the internal C6205 clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 5,
Table 3, and Table 4 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Figure 6 shows the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the C6205 device and the external
clock oscillator circuit. Noise coupling into PLLF directly impacts PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section.
3.3V
PLLV
Internal to C6205
ED[31,27,23]
PLL
(see Table 3)
C4
C3
10 mF
CLKMODE0
(see Table 3)
PLLMULT
PLLCLK
0.1 mF
CLKIN
CLKIN
1
0
CPU
CLOCK
LOOP FILTER
C2
C1
R1
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000 DSP device as possible. Best performance is achieved
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.
E. At power up, the PLL requires a falling edge of RESET to initialize the PLL engine. It may be necessary to toggle reset in order to
establish proper PLL operation.
Figure 5. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
3.3V
PLLV
Internal to C6205
PLL
CLKMODE0
PLLMULT
PLLCLK
CLKIN
LOOP FILTER
CLKIN
1
0
CPU
CLOCK
NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF to PLLG.
B. The 3.3-V supply for PLLV must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
Figure 6. External PLL Circuitry for x1 (Bypass) PLL Mode Only
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
clock PLL (continued)
Table 3. C6205 PLL Multiply Modes and x1 (Bypass) Options
PLL MULTIPLY
FACTORS
CPU CLOCK FREQ
f(CPU clock)
†
‡
‡
‡
CLKMODE0
ED[31]
ED[27]
ED[23]
0
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
x1 (Bypass)
1 × f
1 × f
4 × f
8 × f
(CLKIN)
(CLKIN)
(CLKIN)
(CLKIN)
x1 (Bypass)
x4
x8
x10
x6
10 × f
(CLKIN)
(CLKIN)
(CLKIN)
(CLKIN)
6 × f
9 × f
7 × f
x9
x7
1
x11
11 × f
(CLKIN)
†
CLKMODE0 equal to 0 denotes on-chip PLL bypassed
CLKMODE0 equal to 1 denotes on-chip PLL used, except when configuration bits (ED[31], ED[27], and
ED[23]) are 0 at device reset.
ED[31], ED[27], and ED[23] are the on-chip PLL configuration bits that are latched during device reset,
along with the other boot configuration bits ED[31:0].
‡
§
Table 4. C6205 PLL Component Selection Table
CPU CLOCK
FREQUENCY
(CLKOUT1)
CLKIN
RANGE
(MHZ)
CLKOUT2
RANGE
(MHZ)
TYPICAL
LOCK TIME
(MS)
R1 [+ 1%]
(W)
C1 [+ 10%]
C2 [+ 10%]
CLKMODE
(NF)
(PF)
RANGE (MHZ)
x4
x6
32.5−50
21.7−33.3
18.6−28.6
16.3−25
x7
x8
130−200
65−100
60.4
27
560
75
x9
14.4−22.2
13−20
x10
x11
11.8−18.2
§
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
power-down mode logic
Figure 7 shows the power-down mode logic on the C6205.
CLKOUT1
TMS320C6205
Internal Clock Tree
PD1
PD2
IFR
Power-
Clock
PLL
Internal
Internal
IER
Down
Logic
Peripheral
Peripheral
PD
CSR
PWRD
CPU
(pin)
PD3
CLKIN
RESET
†
Figure 7. Power-Down Mode Logic
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
triggering, wake-up, and effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 8 and described in Table 5.
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU
and Instruction Set Reference Guide (literature number SPRU189).
31
16
15
14
13
12
11
10
9
8
Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
Reserved
R/W-0
PD3
PD2
PD1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 8. PWRD Field of the CSR Register
Power-down mode PD1 takes effect eight to nine clock cycles after the instruction that sets the PWRD bits in the
CSR.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where PD1
took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed first,
then the program execution returns to the instruction where PD1 took effect. The GIE bit in CSR and the NMIE
bit in the interrupt enable register (IER) must also be set in order for the interrupt service routine to execute;
otherwise, execution returns to the instruction where PD1 took effect upon PD1 mode termination by an enabled
interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 5 summarizes all the power-down modes.
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
Table 5. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
POWER-DOWN
MODE
WAKE-UP METHOD
—
EFFECT ON CHIP’S OPERATION
000000
001001
No power-down
PD1
—
CPU halted (except for the interrupt logic)
Wake by an enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, DMA transactions can proceed between
peripherals and internal memory.
Wake by an enabled or
non-enabled interrupt
010001
011010
PD1
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
†
PD2
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked.
†
011100
PD3
Wake by a device reset
All others
Reserved
—
—
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A
normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing
the amount of time between the core supply power up and the I/O supply power up can minimize the effects
of this current draw.
A dual-power supply with simultaneous sequencing, such as that available with TPS563xx controllers or
PT69xx plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the
Using the TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also
be used to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize
the logic within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage ranges: CV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.3 V
DD
DV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
(PCI), V
(PCI), V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
IOP
DDP
Input voltage ranges: (except PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
I
(PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
IP
IOP
Output voltage ranges: (except PCI), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
O
(PCI), V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
OP
IOP
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
MIN NOM
MAX
1.57
3.46
0
UNIT
V
CV
DV
Supply voltage, Core
Supply voltage, I/O
1.43
3.14
0
1.5
3.3
0
DD
V
DD
V
V
V
Supply ground
V
SS
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating case temperature
2
V
IH
IL
0.8
−8
8
V
I
I
mA
mA
_C
OH
OL
T
C
0
90
recommended operating conditions (PCI only)
OPERATION
3.3 V
3.3 V
5 V
MIN
3
NOM
MAX
3.6
UNIT
‡
V
V
3.3-V PCI power supply voltage
3.3
3.3
5
V
V
V
DDP
3
3.6
3.3/5-V PCI Clamp voltage (PCI)
IOP
4.75
−0.5
−0.5
5.25
3.3 V
5 V
V
V
V
V
+ 0.5
IOP
IOP
IOP
IOP
V
V
V
Input voltage (PCI)
V
V
V
IP
+ 0.5
+ 0.5
+ 0.5
3.3 V
5 V
0.5V
IOP
High-level input voltage (PCI)
Low-level input voltage (PCI)
CMOS-compatible
CMOS-compatible
IHP
ILP
2
3.3 V
5 V
−0.5
−0.5
0.3V
IOP
0.8
‡
The 3.3-V PCI power supply voltage should follow similar sequencing as the I/O buffers supply voltage, see the power-supply sequencing section
of this data sheet.
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage (except PCI)
Low-level output voltage (except PCI)
DV = MIN,
I
I
= MAX
= MAX
2.4
OH
DD
OH
OL
DV = MIN,
0.6
10
10
V
OL
DD
†
I
I
Input current
V = V to DV
µA
µA
I
I
SS
DD
Off-state output current
V
O
= DV or 0 V
OZ
DD
Supply current, CPU + CPU memory
access
I
CV = NOM,
CPU clock = 200 MHz
290
mA
DD2V
DD
‡
‡
I
I
Supply current, peripherals
CV = NOM,
CPU clock = 200 MHz
CPU clock = 200 MHz
240
100
mA
mA
pF
DD2V
DD
‡
Supply current, I/O pins
DV = NOM,
DD
DD3V
C
C
Input capacitance
Output capacitance
10
10
i
pF
o
†
‡
TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.
Measured with average activity (50% high/50% low power). For more details on CPU, peripheral, and I/O activity, see the TMS320C6000 Power
Consumption Summary application report (literature number SPRA486).
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted) (PCI only)
TEST CONDITIONS AND
PARAMETER
PCI SIDE
All PCI pins
All PCI pins
MIN
MAX
UNIT
V
OPERATION
§
I
I
I
I
= −0.5 mA
3.3 V
5 V
0.9V
OHP
OHP
OLP
OLP
IOP
V
V
High-level output voltage (PCI)
Low-level output voltage (PCI)
OHP
= −2 mA
= 1.5 mA
= 6 mA
2.4
§
3.3 V
5 V
0.1V
IOP
V
OLP
0.55
0 < V < V
3.3 V
5 V
10
IP
IOP
§
I
I
Low-level input leakage current (PCI)
High-level input leakage current (PCI)
All PCI pins
µA
µA
ILP
V
IP
IP
= 0.5 V
= 2.7 V
−70
§
All PCI pins
V
5 V
70
IHP
§
Input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
comm
C
T
I
OH
Where:
I
=
=
=
=
2 mA
2 mA
0.8 V
OL
I
OH
V
C
comm
15−30-pF typical load-circuit capacitance
T
Figure 9. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 10. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, V MAX
IL
IH
OL
and V MIN for output clocks, V MAX and V
MIN for PCI input clocks, and V
MAX and V MIN for
OH
ILP
IHP
OLP
OHP
PCI output clocks.
V
ref
= V MIN (or V MIN or
IH OH
V
IHP
MIN or V
MIN)
OHP
V
ref
= V MAX (or V MAX or
IL OL
V
ILP
MAX or V
MAX)
OLP
Figure 11. Rise and Fall Transition Time Voltage Reference Levels
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN†‡§ (see Figure 12)
−200
PLL mode x4,
x6, x7, x8, x9,
x10, x11
PLL mode
x1
NO.
UNIT
MIN
5 * M
0.4C
0.4C
MAX
MIN
5
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
0.45C
0.45C
5
0.6
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11). For more details, see the clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
IL
IH
1
4
2
CLKIN
3
4
Figure 12. CLKIN Timings
timing requirements for PCLKIN¶ (see Figure 13)
−200
NO.
UNIT
MIN MAX
1
2
3
4
t
t
t
t
Cycle time, PCLK
30
11
11
ns
ns
c(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
∆v/∆t slew rate, PCLK
w(PCLKH)
w(PCLKL)
sr(PCLK)
ns
1
4
V/ns
¶
When the 5-V PCI clamp is used, the reference points for the rise and fall transitions are measured V MAX and V
MIN for 5 V operation.
ILP
IHP
When the 3.3-V PCI clamp is used, the reference points for the rise and fall transitions are measured at V
operation.
MAX and V
MIN for 3.3 V
ILP
IHP
2 V MIN
Peak to Peak for
5V signaling
or
IOP
0.4 V
MIN
Peak to Peak for
3V signaling
1
4
2
PCLK
3
4
Figure 13. PCLK Timings
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2†‡ (see Figure 14)
−200
NO.
PARAMETER
UNIT
MIN
MAX
P + 0.7
P + 0.7
0.6
2
3
4
t
t
t
Pulse duration, CLKOUT2 high
P − 0.7
P − 0.7
ns
ns
ns
w(CKO2H)
w(CKO2L)
t(CKO2)
Pulse duration, CLKOUT2 low
Transition time, CLKOUT2
†
‡
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
P = 1/CPU clock frequency in nanoseconds (ns).
OL
OH
1
4
2
CLKOUT2
3
4
Figure 14. CLKOUT2 Timings
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§¶ (see Figure 15 − Figure 18)
−200
NO.
UNIT
MIN
1.5
MAX
3
4
6
7
t
t
t
t
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
Setup time, ARDY high before ARE low
Hold time, ARDY high after ARE low
ns
ns
ns
ns
su(EDV-AREH)
3.5
h(AREH-EDV)
−[(RST − 3) * P − 6]
(RST − 3) * P + 3
su(ARDYH-AREL)
h(AREL-ARDYH)
9
t
t
t
t
t
Setup time, ARDY low before ARE low
Hold time, ARDY low after ARE low
Pulse width, ARDY high
−[(RST − 3) * P − 6]
(RST − 3) * P + 3
2P
ns
ns
ns
ns
ns
su(ARDYL-AREL)
10
11
15
16
h(AREL-ARDYL)
w(ARDYH)
Setup time, ARDY high before AWE low
Hold time, ARDY high after AWE low
−[(WST − 3) * P − 6]
(WST − 3) * P + 3
su(ARDYH-AWEL)
h(AWEL-ARDYH)
18
19
t
t
Setup time, ARDY low before AWE low
Hold time, ARDY low after AWE low
−[(WST − 3) * P − 6]
(WST − 3) * P + 3
ns
ns
su(ARDYL-AWEL)
h(AWEL-ARDYL)
†
‡
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
§
¶
switching characteristics over recommended operating conditions for asynchronous memory
cycles‡§¶# (see Figure 15 − Figure 18)
−200
NO.
PARAMETER
UNIT
MIN
TYP
MAX
4P + 5
4P + 5
1
2
t
t
t
t
t
t
t
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Pulse width, ARE low
RS * P − 2
RH * P − 2
ns
ns
ns
ns
ns
ns
ns
osu(SELV-AREL)
oh(AREH-SELIV)
w(AREL)
5
RST * P
8
Delay time, ARDY high to ARE high
3P
WS * P − 2
WH * P − 2
d(ARDYH-AREH)
osu(SELV-AWEL)
oh(AWEH-SELIV)
w(AWEL)
12
13
14
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Pulse width, AWE low
WST * P
17
t
Delay time, ARDY high to AWE high
3P
ns
d(ARDYH-AWEH)
‡
RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are
programmed via the EMIF CE space control registers.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.
Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for an additional
7P ns following the end of the cycle.
§
¶
#
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
†
CPU Clock
1
2
CEx
1
1
2
2
BE[3:0]
EA[21:2]
3
4
ED[31:0]
AOE
1
2
5
6
7
ARE
AWE
ARDY
†
CPU clock is an internal signal.
Figure 15. Asynchronous Memory Read Timing (ARDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
†
CPU Clock
1
1
1
2
2
2
CEx
BE[3:0]
EA[21:2]
3
4
ED[31:0]
AOE
1
9
2
8
10
ARE
AWE
11
ARDY
†
CPU clock is an internal signal.
Figure 16. Asynchronous Memory Read Timing (ARDY Used)
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3
Hold = 2
†
CPU Clock
12
12
12
12
13
13
13
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
15
16
ARE
14
AWE
ARDY
†
CPU clock is an internal signal.
Figure 17. Asynchronous Memory Write Timing (ARDY Not Used)
Setup = 2 Strobe = 3
Not Ready
Hold = 2
†
CPU Clock
12
12
12
12
13
13
13
13
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
17
18
19
AWE
11
ARDY
†
CPU clock is an internal signal.
Figure 18. Asynchronous Memory Write Timing (ARDY Used)
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (see Figure 19)
−200
MIN MAX
NO.
UNIT
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
2.5
1.5
ns
ns
su(EDV-CKO2H)
h(CKO2H-EDV)
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 19 and Figure 20)
−200
NO.
PARAMETER
UNIT
MIN
P − 0.8
P − 4
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-CKO2H)
oh(CKO2H-CEV)
osu(BEV-CKO2H)
oh(CKO2H-BEIV)
osu(EAV-CKO2H)
oh(CKO2H-EAIV)
osu(ADSV-CKO2H)
oh(CKO2H-ADSV)
osu(OEV-CKO2H)
oh(CKO2H-OEV)
osu(EDV-CKO2H)
oh(CKO2H-EDIV)
osu(WEV-CKO2H)
3
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
P − 0.8
P − 4
4
5
P − 0.8
P − 4
6
9
P − 0.8
P − 4
10
11
12
13
14
15
16
P − 0.8
P − 4
§
Output setup time, EDx valid before CLKOUT2 high
P − 1
Output hold time, EDx invalid after CLKOUT2 high
P − 4
Output setup time, SDWE/SSWE valid before CLKOUT2 high
Output hold time, SDWE/SSWE valid after CLKOUT2 high
P − 0.8
P − 4
oh(CKO2H-WEV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
CLKOUT2
1
2
CEx
3
BE1
4
6
BE[3:0]
BE2
A2
BE3
A3
BE4
5
A1
A4
8
EA[21:2]
ED[31:0]
7
Q1
Q2
Q3
10
Q4
9
†
SDCAS/SSADS
11
12
†
SDRAS/SSOE
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 19. SBSRAM Read Timing
CLKOUT2
1
2
CEx
BE[3:0]
3
BE1
4
6
BE2
A2
BE3
A3
BE4
A4
5
A1
EA[21:2]
13
14
10
Q1
Q2
Q3
Q4
ED[31:0]
9
†
SDCAS/SSADS
†
SDRAS/SSOE
15
16
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.
Figure 20. SBSRAM Write Timing
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 21)
−200
MIN MAX
NO.
UNIT
7
8
t
t
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
1.25
3
ns
ns
su(EDV-CKO2H)
h(CKO2H-EDV)
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 21−Figure 26)
−200
NO.
PARAMETER
UNIT
MIN
P − 1
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-CKO2H)
oh(CKO2H-CEV)
osu(BEV-CKO2H)
oh(CKO2H-BEIV)
osu(EAV-CKO2H)
oh(CKO2H-EAIV)
osu(CASV-CKO2H)
oh(CKO2H-CASV)
osu(EDV-CKO2H)
oh(CKO2H-EDIV)
osu(WEV-CKO2H)
oh(CKO2H-WEV)
osu(SDA10V-CKO2H)
oh(CKO2H-SDA10IV)
osu(RASV-CKO2H)
oh(CKO2H-RASV)
P − 3.5
P − 1
3
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
4
P − 3.5
P − 1
5
6
P − 3.5
P − 1
9
10
11
12
13
14
15
16
17
18
P − 3.5
P − 3
§
Output setup time, EDx valid before CLKOUT2 high
Output hold time, EDx invalid after CLKOUT2 high
P − 3.5
P − 1
Output setup time, SDWE/SSWE valid before CLKOUT2 high
Output hold time, SDWE/SSWE valid after CLKOUT2 high
Output setup time, SDA10 valid before CLKOUT2 high
Output hold time, SDA10 invalid after CLKOUT2 high
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
P − 3.5
P − 1
P − 3.5
P − 1
P − 3.5
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
CLKOUT2
CEx
1
5
2
3
4
BE[3:0]
EA[15:2]
BE1
BE2
CA3
BE3
7
6
CA1
CA2
8
D1
D2
D3
ED[31:0]
SDA10
15
9
16
10
†
SDRAS/SSOE
†
SDCAS/SSADS
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 21. Three SDRAM READ Commands
WRITE
WRITE
WRITE
CLKOUT2
CEx
1
3
5
2
4
6
BE[3:0]
BE1
CA1
BE2
CA2
D2
BE3
CA3
D3
EA[15:2]
11
12
D1
ED[31:0]
SDA10
15
16
†
SDRAS/SSOE
9
10
14
†
SDCAS/SSADS
13
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 22. Three SDRAM WRT Commands
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
CLKOUT2
1
5
2
CEx
BE[3:0]
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
†
SDRAS/SSOE
†
SDCAS/SSADS
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 23. SDRAM ACTV Command
DCAB
CLKOUT2
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
15
16
SDA10
17
18
†
SDRAS/SSOE
†
SDCAS/SSADS
13
14
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 24. SDRAM DCAB Command
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
CLKOUT2
CEx
1
2
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
17
9
18
10
†
SDRAS/SSOE
†
SDCAS/SSADS
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 25. SDRAM REFR Command
MRS
CLKOUT2
1
2
6
CEx
BE[3:0]
5
EA[15:2]
ED[31:0]
SDA10
MRS Value
17
18
10
14
†
SDRAS/SSOE
9
†
SDCAS/SSADS
13
†
SDWE/SSWE
†
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
Figure 26. SDRAM MRS Command
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 27)
−200
MIN MAX
NO.
UNIT
3
t
Output hold time, HOLD low after HOLDA low
P
ns
oh(HOLDAL-HOLDL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 27)
−200
NO.
PARAMETER
UNIT
MIN
4P
0
MAX
§
1
2
4
5
t
t
t
t
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
ns
ns
ns
ns
d(HOLDL-EMHZ)
d(EMHZ-HOLDAL)
d(HOLDH-EMLZ)
d(EMLZ-HOLDAH)
2P
7P
2P
3P
0
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
1
4
†
EMIF Bus
C6205
C6205
†
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 27. HOLD/HOLDA Timing
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
RESET TIMING
timing requirements for reset (see Figure 28)
−200
MIN MAX
NO.
UNIT
†
‡
Width of the RESET pulse (PLL stable)
10P
ns
µs
ns
ns
1
t
w(RST)
§
Width of the RESET pulse (PLL needs to sync up)
250
‡#
¶
10
11
t
t
Setup time, ED boot configuration bits valid before RESET high
5P
su(ED)
¶
‡
Hold time, ED boot configuration bits valid after RESET high
5P
h(ED)
†
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL
are stable.
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only. The RESET signal is not connected internally to the Clock PLL circuit.
The PLL requires a minimum of 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time,
RESET must be asserted to ensure proper device operation. See the clock PLL section for power up (specifically Figure 5, Note E) and for PLL
lock times (Table 4).
ED[31:0] are the boot configuration pins during device reset.
A 250 µs setup time before the rising edge of RESET is required when using CLKMODE x4, x6, x7, x8, x9, x10, or x11.
¶
#
switching characteristics over recommended operating conditions during reset‡|| (see Figure 28)
−200
NO.
PARAMETER
UNIT
MIN
MAX
4P
2
3
4
5
6
7
8
9
t
t
t
t
t
t
t
t
Delay time, RESET low to CLKOUT2 invalid
Delay time, RESET high to CLKOUT2 valid
Delay time, RESET low to high group invalid
Delay time, RESET high to high group valid
Delay time, RESET low to low group invalid
Delay time, RESET high to low group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
P
ns
ns
ns
ns
ns
ns
ns
ns
d(RSTL-CKO2IV)
d(RSTH-CKO2V)
d(RSTL-HIGHIV)
d(RSTH-HIGHV)
d(RSTL-LOWIV)
d(RSTH-LOWV)
d(RSTL-ZHZ)
P
P
P
4P
4P
4P
d(RSTH-ZV)
‡
||
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
High group consists of:
Low group consists of:
Z group consists of:
HOLDA
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1, XSP_CLK, XSP_DO, and XSP_CS
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, AD[31:0],
PCBE[3:0], PINTA, PREQ, PSERR, PPERR, PDEVSEL, PFRAME, PIRDY, PPAR, PSTOP, PTRDY, and PME
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
RESET TIMING (CONTINUED)
1
10
11
RESET
2
4
3
5
7
9
CLKOUT2
†
HIGH GROUP
6
8
†
LOW GROUP
†
Z GROUP
Boot Configuration
‡
ED[31:0]
†
‡
High group consists of:
Low group consists of:
Z group consists of:
HOLDA
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1, XSP_CLK, XSP_DO, and XSP_CS
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, AD[31:0],
PCBE[3:0], PINTA, PREQ, PSERR, PPERR, PDEVSEL, PFRAME, PIRDY, PPAR, PSTOP, PTRDY, and PME
ED[31:0] are the boot configuration pins during device reset.
Figure 28. Reset Timing
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles† (see Figure 29)
−200
MIN MAX
NO.
UNIT
2
3
t
t
Width of the interrupt pulse low
Width of the interrupt pulse high
2P
2P
ns
ns
w(ILOW)
w(IHIGH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions during interrupt response
cycles† (see Figure 29)
−200
NO.
PARAMETER
UNIT
MIN
9P
0
MAX
1
4
5
6
t
t
t
t
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
ns
ns
ns
ns
R(EINTH − IACKH)
d(CKO2L-IACKV)
d(CKO2L-INUMV)
d(CKO2L-INUMIV)
10
10
10
0
0
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
1
CLKOUT2
3
2
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
INUMx
Interrupt Number
Figure 29. Interrupt Timing
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
PCI I/O TIMINGS
timing requirements for PCI inputs (see Figure 30)
−200
MIN MAX
NO.
UNIT
5
6
t
t
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
7
0
ns
ns
su(IV-PCLKH)
h(IV-PCLKH)
switching characteristics over recommended operating conditions for PCI outputs (see Figure 30)
−200
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Delay time, PCLK high to output valid
11
ns
ns
ns
ns
d(PCLKH-OV)
d(PCLKH-OIV)
d(PCLKH-OLZ)
d(PCLKH-OHZ)
Delay time, PCLK high to output invalid
2
2
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
28
PCLK
1
2
Valid
PCI Output
PCI Input
3
4
Valid
5
6
Figure 30. PCI Intput/Output Timings
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
PCI RESET TIMING
timing requirements for PCI reset (see Figure 31)
−200
MIN MAX
NO.
UNIT
1
2
t
t
Pulse duration, PRST
1
ms
w(PRST)
Setup time, PCLK active before PRST high
100
µs
su(PCLKA-PRSTH)
PCLK
PRST
1
2
Figure 31. PCI Reset (PRST) Timings
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
PCI SERIAL EEPROM INTERFACE TIMING
timing requirements for serial EEPROM interface (see Figure 32)
−200
MIN MAX
NO.
UNIT
8
9
t
t
Setup time, XSP_DI valid before XSP_CLK high
Hold time, XSP_DI valid after XSP_CLK high
50
0
ns
ns
su(DIV-CLKH)
h(CLKH-DIV)
switching characteristics over recommended operating conditions for serial EEPROM interface†
(see Figure 32)
−200
NO.
PARAMETER
UNIT
MIN
NOM
2046P
0
MAX
1
2
3
4
5
6
7
t
t
t
t
t
t
t
Pulse duration, XSP_CS low
ns
ns
ns
ns
ns
ns
ns
w(CSL)
Delay time, XSP_CLK low to XSP_CS low
Delay time, XSP_CS high to XSP_CLK high
Pulse duration, XSP_CLK high
d(CLKL-CSL)
1023P
1023P
1023P
1023P
1023P
d(CSH-CLKH)
w(CLKH)
Pulse duration, XSP_CLK low
w(CLKL)
Output setup time, XSP_DO valid after XSP_CLK high
Output hold time, XSP_DO valid after XSP_CLK high
osu(DOV-CLKH)
oh(CLKH-DOV)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
2
1
XSP_CS
3
4
5
XSP_CLK
7
6
XSP_DO
9
8
XSP_DI
Figure 32. PCI Serial EEPROM Interface Timing
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 33)
−200
MIN MAX
NO.
UNIT
§
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P
ns
ns
c(CKRX)
¶
Pulse duration, CLKR/X high or CLKR/X low
P−1
9
w(CKRX)
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
2
6
3
8
7
0.5
4
8
Hold time, DR valid after CLKR low
3
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
2
6
3
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
¶
The minimum CLKR/X pulse duration is either (P−1) or 4 ns, whichever is larger. For example, when running parts at 200 MHz (P = 5 ns), use
4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P−1) = 9 ns as the minimum CLKR/X pulse
duration.
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 33)
−200
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal
CLKR/X generated from CLKS input
1
t
3
12
ns
d(CKSH-CKRXH)
§¶
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P−2
C − 2
−3
−3
3
ns
ns
ns
c(CKRX)
#
#
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C + 2
w(CKRX)
3
3
d(CKRH-FRV)
9
t
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
d(FXH-DXV)
9
−1
3
4
Disable time, DX high impedance following last data bit from
CLKX high
12
13
14
9
−1
2
4
Delay time, CLKX high to DX valid
12
5
−1
2
Delay time, FSX high to DX valid
ONLY applies when in data delay 0 (XDATDLY = 00b) mode.
FSX ext
12
†
‡
§
¶
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
The maximum bit rate for the C6205 devices is 100 Mbps or CPU/2 (the slower of the two). Care must be taken to ensure that the AC timings
specified in this data sheet are met. The maximum bit rate for McBSP-to-McBSP communications is 100 MHz; therefore, the minimum CLKR/X
clock cycle is either twice the CPU cycle time (2P), or 10 ns (100 MHz), whichever value is larger. For example, when running parts at 200 MHz
(P = 5 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running
parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP
communications applies when the serial port is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX,
CLKXM = FSXM = 1, and CLKRM = FSRM = 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP
communicates to is a slave.
#
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100-MHz limit.
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
13
(n-2)
14
13
Bit(n-1)
12
DX
Bit 0
(n-3)
Figure 33. McBSP Timings
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 34)
−200
MIN MAX
NO.
UNIT
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
4
4
ns
ns
su(FRH-CKSH)
h(CKSH-FRH)
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 34. FSR Timing When GSYNC = 1
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35)
−200
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 3P
ns
ns
su(DRV-CKXL)
6 + 6P
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 35)
−200
§
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
T + 5
L + 5
5
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T − 3
L − 4
−4
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
3P + 3 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L − 2
L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
P + 3
3P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36)
−200
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 3P
ns
ns
su(DRV-CKXH)
5 + 6P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 36)
−200
§
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
L + 3
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L − 2
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
T − 2 T + 3
−2
4
3P + 4 5P + 17
3P + 3 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
−2
4
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
H − 2 H + 4 2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37)
−200
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 3P
ns
ns
su(DRV-CKXH)
5 + 6P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 37)
−200
§
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T − 2 T + 3
H − 2 H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
−2
4
3P + 4 5P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
H − 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
P + 3
3P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38)
−200
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 3P
ns
ns
su(DRV-CKXL)
5 + 6P
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 38)
−200
§
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H − 2 H + 3
T − 2 T + 1
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
−2
4
3P + 4 5P + 17
3P + 3 5P + 17
2P + 2 4P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
−2
4
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
L − 2
L + 4
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics over recommended operating conditions for DMAC outputs†
(see Figure 39)
−200
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Pulse duration, DMAC high
2P−3
ns
w(DMACH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
1
DMAC[3:0]
Figure 39. DMAC Timing
timing requirements for timer inputs† (see Figure 40)
−200
NO.
UNIT
MIN
2P
MAX
1
2
t
t
Pulse duration, TINP high
Pulse duration, TINP low
ns
ns
w(TINPH)
2P
w(TINPL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for timer outputs†
(see Figure 40)
−200
NO.
PARAMETER
UNIT
MIN
2P−3
2P−3
MAX
3
4
t
t
Pulse duration, TOUT high
Pulse duration, TOUT low
ns
ns
w(TOUTH)
w(TOUTL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
2
1
TINPx
4
3
TOUTx
Figure 40. Timer Timing
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics over recommended operating conditions for power-down outputs†
(see Figure 41)
−200
NO.
PARAMETER
UNIT
MIN
MAX
1
t
Pulse duration, PD high
2P
ns
w(PDH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
1
PD
Figure 41. Power-Down Timing
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 42)
−200
MIN
NO.
UNIT
MAX
1
3
4
t
t
t
Cycle time, TCK
35
11
9
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 42)
−200
MIN
−4.5
NO.
PARAMETER
Delay time, TCK low to TDO valid
UNIT
MAX
2
t
12
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 42. JTAG Test-Port Timing
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
MECHANICAL DATA
GHK (S-PBGA-N288)
PLASTIC BALL GRID ARRAY
16,10
15,90
SQ
14,40 TYP
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19
10 12 14 16 18
2
4
6
8
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,12
0,08
M
∅ 0,08
0,45
0,35
4145273-4/C 12/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGAt configuration
thermal resistance characteristics (S-PBGA package)
†
NO
°C/W
9.5
Air Flow (m/s )
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
0.00
0.50
1.00
2.00
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
26.5
23.9
22.6
21.3
†
m/s = meters per second
MicroStar BGA is a trademark of Texas Instruments.
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E − OCTOBER 1999 − REVISED MARCH 2004
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPR106D device-specific data
sheet to make it an SPRS106E revision.
Scope: Applicable updates to the C62x device family, specifically relating to the C6205 device, have been incor-
porated.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
All
9
Updated the title for literature number SPRU190 to:
TMS320C6000 DSP Peripherals Overview Reference Guide
memory map summary:
Changed the document reference in the last sentence of the paragraph.
28
36
Added the power-down mode logic section and accompanying information.
switching characteristics over recommended operating conditions for CLKOUT2 table:
Removed NO. 1 (parameter t
) from the table.
c(CKO2)
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
BGA
BGA
BGA
BGA
BGA
Drawing
TMS320C6205DGHK200
TMS320C6205GHK200
TMS320C6205GHKA200
TMS32C6205DGHKA200
TMX320C6205GHK
ACTIVE
ACTIVE
GHK
288
288
288
288
288
90
90
90
90
None
None
None
None
None
SNPB
SNPB
SNPB
SNPB
Call TI
Level-3-220C-168HR
Level-3-220C-168HR
Level-3-220C-168HR
Level-3-220C-168HR
Call TI
GHK
ACTIVE
GHK
ACTIVE
GHK
OBSOLETE
GHK
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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www.ti.com/wireless
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Copyright 2005, Texas Instruments Incorporated
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