TMP320F2812PBKS [TI]
DIGITAL SIGNAL PROCESSORS; 数字信号处理器![TMP320F2812PBKS](http://pdffile.icpdf.com/pdf1/p00064/img/icpdf/TMP320F2812_334830_icpdf.jpg)
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描述: | DIGITAL SIGNAL PROCESSORS |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
D
D
High-Performance Static CMOS Technology
– 150 MHz (6.67-ns Cycle Time)
– Low-Power (1.8-V Core, 3.3-V I/O) Design
– 3.3-V Flash Programming Voltage
D
D
Three 32-Bit CPU-Timers
Serial Port Peripherals
– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces
(SCIs), Standard UART
– Enhanced Controller Area Network
(eCAN)
High-Performance CPU (C28x)
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Multichannel Buffered Serial Port
(McBSP) With SPI Mode
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– 4M Linear Program Address Reach
– 4G Linear Data Address Reach
– Code-Efficient (in C/C++ and Assembly)
– TMS320F24x/LF240x Processor Source
Code Compatible
D
12-Bit ADC, 16 Channels
– 2 x 8 Channel Input Multiplexer
– Two Sample-and-Hold
– Single Conversion Time: 200 ns
– Pipeline Conversion Time: 60 ns
D
D
D
Up to 56 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins
D
On-Chip Memory
– Up to 128K x 16 Flash
Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug via Hardware
(8 x 4K and 6 x 16K Sectors)
– 2K x 16 OTP ROM
– L0 and L1: 2 Blocks of 4K x 16
Single-Access RAM (SARAM)
– H0: 1 Block of 8K x 16 SARAM
– M0 and M1: 2 Blocks of 1K x 16 SARAM
Development Tools Include
– ANSI C/C++ Compiler/Assembler/Linker
– Supports TMS320C24x /240x
Instructions
– Code Composer Studio IDE
– DSP BIOS
D
D
Boot ROM (4K x 16)
– With Software Boot Modes
– Standard Math Tables
†
– JTAG Scan Controllers
External Interface (F2812)
– Up to 1.5M Total Memory
– Programmable Wait States
– Programmable Read/Write Strobe Timing
– Four Individual Chip Selects
(TI or Third-Party)
– Evaluation Modules
– Broad Third-Party Digital Motor Control
Support
D
D
Low-Power Modes and Power Savings
– IDLE, STANDBY, HALT Modes Supported
– Disable Individual Peripheral Clocks
D
Clock and System Control
– Dynamic PLL Ratio Changes Supported
– On-Chip Oscillator
Package Options
– 179-Pin MicroStar BGA With External
Interface (GHH) (F2812)
– Watchdog Timer Module
D
D
D
Three External Interrupts
Peripheral Interrupt Expansion (PIE) Block
That Supports 45 Peripheral Interrupts
– 176-Pin Low-Profile Quad Flatpack
(LQFP) With External Interface (PGF)
(F2812)
– 128-Pin LQFP Without External Interface
(PBK) (F2810)
128-Bit Security Key/Lock
– Protects Flash/OTP and L0/L1 SARAM
– Prevents Firmware Reverse Engineering
D
Temperature Options:
– A: –40°C to 85°C
– S: –40°C to 125°C
D
Motor Control Peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240x Devices
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C24x, Code Composer Studio, and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port
Copyright 2001, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
Table of Contents
Device Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Vector Table Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PIE Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PIE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PIE/CPU Interrupt Response . . . . . . . . . . . . . . . . . . . 41
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
OSC and PLL Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PLL-Based Clock Module . . . . . . . . . . . . . . . . . . . . . . . . 50
External Reference Oscillator Clock Option . . . . . . . . 50
Watchdog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Low-Power Modes Block . . . . . . . . . . . . . . . . . . . . . . . . 54
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
32-Bit CPU-Timers 0/1/2 . . . . . . . . . . . . . . . . . . . . . . . . 56
Event Manager Modules (EVA, EVB) . . . . . . . . . . . . . . 61
C28x CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Memory Bus (Harvard Bus Architecture) . . . . . . . . . 16
Peripheral Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Real-Time JTAG and Analysis . . . . . . . . . . . . . . . . . . 17
External Interface (XINTF) (F2812 Only) . . . . . . . . . 17
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M0, M1 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
L0, L1, H0 SARAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Peripheral Interrupt Expansion (PIE) Block . . . . . . . 19
External Interrupts (XINT1, 2, 13, XNMI) . . . . . . . . . 19
Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Peripheral Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Peripheral Frames 0, 1, 2 (PFn) . . . . . . . . . . . . . . . . . 20
General-Purpose Input/Output (GPIO) Multiplexer . 20
32-Bit CPU-Timers (0, 1, 2) . . . . . . . . . . . . . . . . . . . . . 20
Motor Control Peripherals . . . . . . . . . . . . . . . . . . . . . . 20
Serial Port Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Emulation Registers . . . . . . . . . . . . . . . . . . . . . . 24
External Interface, XINTF (F2812 only) . . . . . . . . . . . . 27
Enhanced Analog-to-Digital Converter
(ADC) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Enhanced Controller Area Network (eCAN) Module . 71
Multichannel Buffered Serial Port (McBSP) Module . . 75
Serial Communications Interface (SCI) Module . . . . . 79
Serial Peripheral Interface (SPI) Module . . . . . . . . . . . 82
GPIO Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . 97
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . 98
Recommended Operating Conditions . . . . . . . . . . . . . 98
Electrical Characteristics Over Recommended
Operating Free-Air Temperature Range . . . . . . . . 99
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
device summary
Note that throughout this data sheet, F2810 is used to denote TMS320F2810; F2812 is used to denote
TMS320F2812; and F28x is used to denote F2810 and F2812.
Table 1. Hardware Features of the F2810 and F2812 Devices
FEATURE
Instruction Cycle (at 150 MHz)
Single-Access RAM (SARAM) (16-bit word)
3.3-V On-Chip Flash (16-bit word)
Code Security for On-Chip Flash/SARAM
Boot ROM
F2810
F2812
6.67 ns
6.67 ns
18K
18K
64K
128K
Yes
Yes
Yes
Yes
OTP ROM
Yes
Yes
External Memory Interface
—
Yes
Event Managers A and B (EVA and EVB)
EVA, EVB
EVA, EVB
S
S
S
General-Purpose (GP) Timers
Compare (CMP)/PWM
4
4
16
16
Capture (CAP)/QEP Channels
6/2
6/2
Watchdog Timer
12-Bit ADC
Yes
Yes
Yes
Yes
S
Channels
16
16
32-bit CPU Timers
SPI
3
3
Yes
Yes
SCIA, SCIB
CAN
SCIA, SCIB
SCIA, SCIB
Yes
Yes
McBSP
Yes
Yes
Digital I/O Pins (Shared)
External Interrupts
Supply Voltage
56
56
3
3
1.8-V Core, 3.3-V I/O
1.8-V Core, 3.3-V I/O
179-pin GHH
176-pin PGF
Packaging
128-pin PBK
PP
Product Status:
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PP
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
functional block diagram
Memory Bus
CPU-TIMER 0
CPU-TIMER 1
CPU-TIMER 2
TINT0
Real-Time JTAG
External
TINT2
INT14
Control
PIE
Interface
Address(19)
†
(96 interrupts)
TINT1
‡
INT[12:1]
(XINTF)
Data(16)
INT13
NMI
XINT13
XNMI
External Interrupt
Control
(XINT1/2/13, XNMI)
G
P
I
M0 SARAM
1K x 16
M1 SARAM
1K x 16
SCIA/SCIB
SPI
FIFO
FIFO
FIFO
O
GPIO Pins
McBSP
C28x CPU
L0 SARAM
4K x 16
L1 SARAM
4K x 16
M
U
X
eCAN
EVA/EVB
Flash
128K x 16 (F2812)
64K x 16 (F2810)
12-Bit ADC
16 Channels
OTP
2K x 16
System Control
XRS
X1/XCLKIN
X2
RS
H0 SARAM
8K × 16
(Oscillator and PLL
CLKIN
+
Peripheral Clocking
+
Boot ROM
4K × 16
XPPLDIS
Low-Power
Modes
+
Memory Bus
WatchDog)
Peripheral
Bus
Protected by the Code Security Module.
†
‡
45 of the possible 96 interrupts are used on F2810/F2812.
XINTF is not available on the F2810.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
179-Pin GHH
(Ball Grid Array)
(TOP VIEW)
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
176-Pin PGF
(Low-Profile Quad Flatpack)
(TOP VIEW)
132
89
133
88
176
45
1
44
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
128-Pin PBK
(Low-Profile Quad Flatpack)
(TOP VIEW)
96
65
64
97
128
33
1
32
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
pin functions
Table 2 specifies the signals on the F2810 and F2812 devices. All digital inputs are TTL-compatible. All outputs
are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 20-µA resistor is used for pullup/down.
Table 2. Signal Descriptions
†
NAME
PIN NO.
I/O/Z
DRIVE
PU/PD
DESCRIPTION
XINTF SIGNALS (2812 ONLY)
XA[18:0]
XD[15:0]
XMP/MC
XHOLD
XHOLDA
XZCS0
O/Z
19-bit Address Bus
16-bit Data Bus
I/O/Z
I
PU
PU
Microprocessor/Microcomputer Mode Select
External DMA Hold Request
External DMA Hold Acknowledge
Zone 0 Chip Select Strobe
Zone 1 Chip Select Strobe
Zone 2 Chip Select Strobe
Zone 6 and 7 Chip Select Strobe
Write Enable
I
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
I
XZCS1
XZCS2
XZCS6AND7
XWE
XRD
Read Enable
XRNW
Read Not Write Select
XREADY
PU
Input Ready Signal
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN
X2
I
I
–
–
Oscillator Input Or Clock Generator Input
Oscillator Output
XPPLDIS
TESTSEL
XRS
I
PU
PU
PU
–
Disable PLL When High
I
Test Mode Select Signal
I/O
I/O
I/O
Device Reset (in) and Watchdog Reset (out)
Flash Test Signal 1
TEST1
TEST2
–
Flash Test Signal 2
JTAG
TRST
TCK
I
PD
JTAG Test-Logic Reset
JTAG Test clock
I
I
TMS
TDI
JTAG Test Mode Select
JTAG Test Data Input
I
TDO
EMU0
EMU1
O/Z
I/O/Z
I/O/Z
JTAG Test Data Output
Emulation/Test trigger channel 0
Emulation/Test trigger channel 1
PU
PU
†
PU = pin has internal pullup; PD = pin has internal pulldown
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
pin functions (continued)
Table 2. Signal Descriptions (Continued)
†
NAME
PIN NO.
I/O/Z
DRIVE
PU/PD
DESCRIPTION
ADC ANALOG INPUT SIGNALS
ADCIN0[7:0]
ADCIN1[7:0]
ADCREFP
I
8 Channel Analog Inputs
I
8 Channel Analog Inputs
ADC Reference Output
ADC Reference Output
ADC External Current Bias Resistor
Analog GND
O
ADCREFM
O
ADCRESEXT
AVSSREFBG
AVDDREFBG
ADCLO
O
I
I
Analog Power
I
Common Low Side Analog Input
Analog GND
AGND (2 pins)
AVDD (2 pins)
I
I
Analog 3.3-V Supply
POWER SIGNALS
V
V
3.3-V I/O Power Pins
I/O Ground Pins
DDO
SS
CV
CV
1.8-V CPU/Core Power Pins
CPU/Core Ground Pins
DD
SS
†
PU = pin has internal pullup; PD = pin has internal pulldown
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
pin functions (continued)
Table 2. Signal Descriptions (Continued)
†
GPIO
PERIPHERAL SIGNAL
PIN NO.
I/O/Z
DRIVE
PU/PD
DESCRIPTION
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOA0
PWM1 (O)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or PWM Output Pin #1
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
GPIOA12
GPIOA13
GPIOA14
GPIOA15
PWM2 (O)
GPIO or PWM Output Pin #2
GPIO or PWM Output Pin #3
GPIO or PWM Output Pin #4
GPIO or PWM Output Pin #5
GPIO or PWM Output Pin #6
GPIO or Timer 1 Output
PWM3 (O)
PWM4 (O)
PWM5 (O)
PWM6 (O)
T1PWM_T1CMP (I)
T2PWM_T2CMP (I)
CAP1_QEP1 (I)
CAP2_QEP2 (I)
CAP3_QEPI1 (I)
TDIRA (I)
GPIO or Timer 2 Output
GPIO or Capture Input #1
GPIO or Capture Input #2
GPIO or Capture Input #3
GPIO or Timer Direction
TCLKINA (I)
C1TRIP (I)
GPIO or Timer Clock Input
GPIO or Compare 1 Output Trip
GPIO or Compare 2 Output Trip
GPIO or Compare 3 Output Trip
C2TRIP (I)
C3TRIP (I)
GPIOB OR EVB SIGNALS
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOB8
GPIOB9
GPIOB10
GPIOB11
GPIOB12
GPIOB13
GPIOB14
GPIOB15
PWM7 (O)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or PWM Output Pin #7
GPIO or PWM Output Pin #8
GPIO or PWM Output Pin #9
GPIO or PWM Output Pin #10
GPIO or PWM Output Pin #11
GPIO or PWM Output Pin #12
GPIO or Timer 3 Output
PWM8 (O)
PWM9 (O)
PWM10 (O)
PWM11 (O)
PWM12 (O)
T3PWM_T3CMP (I)
T4PWM_T4CMP (I)
CAP4_QEP3 (I)
CAP5_QEP4 (I)
CAP6_QEPI2 (I)
TDIRB (I)
GPIO or Timer 4 Output
GPIO or Capture Input #4
GPIO or Capture Input #5
GPIO or Capture Input #6
GPIO or Timer Direction
TCLKINB (I)
C4TRIP (I)
GPIO or Timer Clock Input
GPIO or Compare 4 Output Trip
GPIO or Compare 5 Output Trip
GPIO or Compare 6 Output Trip
C5TRIP (I)
C6TRIP (I)
GPIOD OR EVA SIGNALS
GPIOD0
GPIOD1
T1CTRIP_PDPINTA (I)
T2CTRIP/EVASOC (I)
I/O/Z
I/O/Z
PU
PU
Timer 1 Compare Output Trip
Timer 2 Compare Output Trip or External ADC
Start-of-Conversion EV-A
†
PU = pin has internal pullup; PD = pin has internal pulldown
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
pin functions (continued)
Table 2. Signal Descriptions (Continued)
†
GPIO
PERIPHERAL SIGNAL
PIN NO.
I/O/Z
DRIVE
PU/PD
DESCRIPTION
GPIOD OR EVB SIGNALS
GPIOD5
T3CTRIP_PDPINTB (I)
T4CTRIP/EVBSOC (I)
I/O/Z
I/O/Z
PU
PU
Timer 3 Compare Output Trip
GPIOD6
Timer 4 Compare Output Trip or External ADC
Start-of-Conversion EV-B
GPIOE OR INTERRUPT SIGNALS
GPIOE0
GPIOE1
GPIOE2
XINT1_XBIO (I)
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
GPIO or XINT1 or XBIO core input
GPIO or XINT2 or ADC start of conversion
GPIO or XNMI or XINT13
XINT2_ADCSOC (I)
XNMI_XINT13 (I)
GPIOF OR SPI SIGNALS
GPIOF0
GPIOF1
GPIOF2
GPIOF3
SPISIMO (O)
SPISOMI (I)
SPICLK (I/O)
SPISTE (I/O)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
GPIO or SPI slave in, master out
GPIO or SPI slave out, master in
GPIO or SPI clock
GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIOF4
GPIOF5
SCITXDA (O)
SCIRXDA (I)
I/O/Z
I/O/Z
PU
PU
GPIO or SCI asynchronous serial port TX data
GPIO or SCI asynchronous serial port RX data
GPIOF OR CAN SIGNALS
GPIOF6
GPIOF7
CANTX (O)
CANRX (I)
I/O/Z
I/O/Z
PU
PU
GPIO or eCAN transmit data
GPIO or eCAN receive data
GPIOF OR MCBSP SIGNALS
GPIOF8
GPIOF9
GPIOF10
GPIOF11
GPIOF12
GPIOF13
MCLKX (I/O)
MCLKR (I/O)
MFSX (I/O)
MFSR (I/O)
MDX (O)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
GPIO or transmit clock
GPIO or receive clock
GPIO or transmit frame synch
GPIO or receive frame synch
GPIO or transmitted serial data
GPIO or received serial data
MDR (I)
GPIOG OR XF CPU OUTPUT SIGNAL
I/O/Z PU
GPIOG OR SCI-B SIGNALS
GPIOF14
XF(0)
GPIO or input clock
GPIOG4
GPIOG5
SCITXDB (O)
SCIRXDB (I)
I/O/Z
I/O/Z
PU
PU
GPIO or SCI asynchronous serial port transmit data
GPIO or SCI asynchronous serial port receive data
†
PU = pin has internal pullup; PD = pin has internal pulldown
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
memory map
Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x0000–0000
M0 Vector – RAM (32 × 32)
(enabled if VMAP = 0)
0x0000–0040
0x0000–0400
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
0x0000–0800
0x0000–0D00
Peripheral Frame 0
Reserved
(2K × 16)
PIE Vector - RAM
(256 × 16)
(enabled if VMAP = 0,
ENPIE = 1)
Reserved
0x0000–1000
0x0000–2000
Reserved
XINTF Zone 0 (8K × 16, XZCS0)
Reserved
0x0000–4000
XINTF Zone 1 (8K × 16, XZCS1) (Protected)
0x0000–6000
0x0000–7000
Peripheral Frame 2
(4K × 16, Protected)
Reserved
Peripheral Frame 1
(4K × 16, Protected)
Reserved
0x0000–8000
0x0000–9000
0x0000–A000
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
0x0008–0000
0x0010–0000
XINTF Zone 2 (0.5M × 16, XZCS2)
XINTF Zone 6 (1M × 16, XZCS6AND7)
Reserved
0x0020–0000
0x003D–7800
0x003D–8000
OTP (2K × 16, Secure Block)
Reserved
FLASH (128K × 16, Secure Block)
0x003F–0000
0x003F–7FF8
128-Bit Password
0x003F–8000
0x003F–A000
H0 SARAM (8K × 16)
Reserved
0x003F–C000
0x003F–F000
0x003F–FFC0
XINTF Zone 7 (16K × 16, XZCS6AND7)
Boot ROM (4K × 16)
(enabled if MP/MC = 0)
(enabled if MP/MC = 1)
XINTF Vector - RAM (32 × 32)
BROM Vector - ROM (32 × 32)
(enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
(enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected for spurious writes after configuration.
G. Zone 6 and Zone 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 1. F2812 Memory Map
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
memory map (continued)
Block
On-Chip Memory
Start Address
Data Space
Prog Space
0x0000–0000
M0 Vector – RAM (32 × 32)
(enabled if VMAP = 0)
0x0000–0040
0x0000–0400
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
0x0000–0800
0x0000–0D00
Peripheral Frame 0
(2K × 16)
PIE Vector - RAM
(256 × 16)
Reserved
(enabled if VMAP = 0,
ENPIE = 1)
0x0000–1000
0x0000–2000
Reserved
Reserved
0x0000–6000
0x0000–7000
Peripheral Frame 2
(4K × 16, Protected)
Reserved
Peripheral Frame 1
(4K × 16, Protected)
0x0000–8000
0x0000–9000
0x0000–A000
L0 SARAM (4K × 16, Secure Block)
L1 SARAM (4K × 16, Secure Block)
Reserved
0x003D–7800
0x003D–8000
0x003E–0000
OTP (2K × 16, Secure Block)
Reserved
FLASH (64K × 16, Secure Block)
0x003F–0000
0x003F–7FF8
128-Bit Password
0x003F–8000
0x003F–A000
H0 SARAM (8K × 16)
Reserved
0x003F–F000
0x003F–FFC0
Boot ROM (4K × 16)
(enabled if MP/MC = 0)
BROM Vector - ROM (32 × 32)
(enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps—M0 vector, PIE vector, BROM vector—should be enabled at a time.
NOTES: A. Memory blocks are not to scale. Flash location subject to change.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected for spurious writes after configuration.
G. Zone 6 and Zone 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 2. F2810 Memory Map
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
memory map (continued)
The “Low 64K” of the memory address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only
execute from the “High 64K” memory area. Hence, the top 32K of Flash and H0 SARAM block can be used to
run 24x/240x-compatible code (if MP/MC mode is low) or, on F2812, code can be executed from XINTF Zone 7
(if MP/MC mode is high).
The XINTF consists of five independent zones. Three zones have their own chip selects and two zones share
a single chip select. Each zone can be programmed with its own timing (wait states) and to either sample or
ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
Note: The chip selects of XINTF Zone 6 and Zone 7 are merged together into a single chip select (ZCS6AND7).
Refer to the ”External Interface – XINTF (F2812 only)” section of this data sheet for details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together so as to enable these blocks
to be “write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks
happen as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory
locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain
peripheral applications where the user expected the write to occur first (as written). The C28x CPU supports
a block protection mode where a region of memory can be protected so as to make sure that operations occur
as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by
default, it will protect the selected zones.
On the F2812, at reset, XINTF Zone 7 is enabled if the XMP/MC signal is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user
to either boot from on-chip memory or from off-chip memory. The state of the XMP/MC signal on reset is stored
in an MP/MC mode bit in the XINTCNF2 register. The user can change this mode in software and hence control
the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by XMP/MC.
I/O space is not supported on the F2812 XINTF.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
memory map (continued)
The wait states for the various spaces in the memory map area are listed in Table 3.
Table 3. Wait States
AREA
WAIT-STATES
0-wait
COMMENTS
M0 & M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
0-wait
Includes the Flash registers.
0-wait (writes)
2-wait (reads)
Cycles can be extended by peripheral generated ready.
Fixed. Cycles cannot be extended by the peripheral.
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
L0 & L1 SARAMs
OTP
0-wait
Programmable,
0-wait minimum
Programmed via the Flash registers.
Programmed via the Flash registers.
Flash
Programmable,
0-wait minmum
H0 SARAM
Boot-ROM
XINTF
0-wait
1-wait
Programmable,
1-wait minimum
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
description
The TMS320F2810 and TMS320F2812 devices, members of the TMS320C28x DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in subsequent paragraphs.
C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000 DSP platform. The C28x is source
codecompatibletothe24x/240xDSPdevices, henceexisting240xuserscanleveragetheirsignificantsoftware
investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop not only
their system control software in a high-level language, but also enables math algorithms to be developed using
C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by
microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x
32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle
higher numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a
device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute
at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
memory bus (Harvard bus architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached
to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses can be
summarized as follows:
†
Highest:
Data Writes
†
Program Writes
Data Reads
‡
Program Reads
‡
Lowest:
Fetches
peripheral bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F2810
and F2812 adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines
and 16 or 32 data lines and associated control signals. There are two versions of the peripheral bus supported
on the F2810 and F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains
compatibility with C240x compatible peripherals. The other version supports both 16- and 32-bit accesses
(called peripheral frame 1) and is used to connect peripherals requiring higher throughput.
TMS320C28x, C28x, and TMS320C2000 are trademarks of Texas Instruments.
†
‡
Simultaneous Data and Program writes cannot occur on the Memory Bus.
Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
real-time JTAG and analysis
TheC28ximplementsthestandardIEEE1149.1JTAGinterface. Additionally, theC28xsupportsreal-timemode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through
non-time critical code while enabling time-critical interrupts to be serviced without interference. The C28x
implements the real-time mode in hardware within the CPU. This is a unique feature to the C28x, no software
monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
external interface (XINTF) (F2812 only)
This asynchronous interface consists of 19 address lines, 16 data lines, and four chip-select lines. The
chip-select lines are mapped to five external zones, Zone 0, 1, 2, 6, and 7. Zones 6 and 7 share a single
chip-select. Each of the five zones can be programmed with different number of wait states, strobe signal setup
and hold timing and each zone can be programmed for extending wait states externally or not. The
programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external
memories and peripherals.
flash
The F2812 contains 128K x16 of embedded Flash memory and 2K x16 of OTP memory. The Flash memory
is segregated into eight 4K x16 sized sectors, and six 16K x16 sized sectors. The user can individually erase,
program and validate a sector while leaving other sectors untouched. Special memory pipelining is provided
to enable the Flash module to achieve higher performance. The Flash/OTP is mapped to both program and data
space hence can be used to execute code or store data information.
The F2810 has 64K x 16 of embedded Flash and 2K x 16 of OTP memory.
M0, M1 SARAMs
All C28x devices will contain these two blocks of single access memory, each 1Kx16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on C28x
devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program
and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is
performed within the linker. The C28x device presents a unified memory map to the programmer. This makes
for easier programming in high-level languages.
L0, L1, H0 SARAMs
The F2810 and the F2812 will contain an additional 16K x 16 of single-access RAM, divided into 3 blocks
(4K + 4K + 8K). Each block can be independently accessed hence minimizing pipeline stalls. Each block is
mapped to both program and data space.
boot ROM
The Boot ROM is factory programmed with boot loading software. Boot-mode signals are provided to tell the
boot loader software, programmed into the Boot ROM, what boot mode to use on power up. The user can select
to boot normally or to download new software from an external connection or to select boot software that is
programmed in the internal Flash. The Boot ROM will also contain standard tables, such as SIN/COS
waveforms, for use in math related algorithms.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
security
The F2810 and F2812 support high levels of security to protect the user firmware from being reversed
engineered. The security features a 128-bit password, which the user programs into the Flash. One code
security module (CSM) is used to protect the Flash/OTP and the L0/L1 SARAM blocks. The security feature
prevents unauthorized users from examining the memory contents via the JTAG port, executing code from
external memory or trying to boot-load some undesirable software that would export the secure memory
contents. To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which
matches the value stored in the password locations within the Flash.
Code Security Module Disclaimer
The Code Security Module (“CSM”) included on this device was designed to password
protect the data stored in the associated memory (either ROM or Flash) and is warranted
by Texas Instruments (TI), in accordance with its standard terms and conditions, to
conform to TI’s published specifications for the warranty period applicable for this device.
TIDOESNOT, HOWEVER, WARRANTORREPRESENTTHATTHECSMCANNOTBE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE
ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS.
MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR
REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE,
INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR
A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL,
INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING
INANYWAYOUTOFYOURUSEOFTHECSMORTHISDEVICE, WHETHERORNOT
TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED
DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF
GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER
ECONOMIC LOSS.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
peripheral interrupt expansion (PIE) block
ThePIEblockservestomultiplexnumerousinterruptsourcesintoasmallersetofinterruptinputs. ThePIEblock
can support up to 96 peripheral interrupts. On the F2810/F2812, 45 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into one of 12 CPU interrupt
lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block
that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.
It takes 9 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled/disabled within the PIE block.
external interrupts (XINT1, 2, 13, XNMI)
The F2810 and F2812 support three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one
non-masked external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can
be selected for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The
maskedinterruptsalsocontaina16-bitfreerunningupcounter, whichisresettozerowhenavalidinterruptedge
is detected. This counter can be used to accurately time stamp the interrupt.
oscillator and PLL
The F2810 and F2812 can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator
circuit. A PLL is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed
on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is
desired. The PLL block can be set in bypass mode.
watchdog
The F2810 and F2812 support a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can
be disabled if necessary.
peripheral clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports and the event managers, CAP and QEP
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from
increasing CPU clock speeds.
low-power modes
The F2810 and F2812 devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only
those peripherals that need to function during IDLE are left operating. An enabled interrupt
from an active peripheral will wake the processor from IDLE mode.
STANDBY:
HALT:
Turn off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional.
An external interrupt event will wake the processor and the peripherals. Execution begins on
the next valid cycle after detection of the interrupt event.
Turn off oscillator. This mode basically shuts down the device and places it in the lowest
possiblepowerconsumptionmode. OnlyaresetorXNMIwillwakethedevicefromthismode.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
peripheral frames 0, 1, 2 (PFn)
The F2810 and F2812 segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
PIE:
External Interface Configuration Registers
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
Flash:
Timers: CPU-Timers 0, 1, 2 Registers
CSM:
eCAN:
SYS:
GPIO:
EV:
Code Security Module KEY Registers
eCAN Mailbox and Control Registers
System Control Registers
PF1:
PF2:
GPIO Mux Configuration and Control Registers
Event Manager (EVA/EVB) Control Registers
McBSP: McBSP Control and TX/RX Registers
SCI:
SPI:
ADC:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Peripheral Interface (SPI) Control and RX/TX Registers
12-Bit ADC Registers
general-purpose input/output (GPIO) multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This enables the user
to use a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as
inputs. The user can then individually program each pin for GPIO mode or Peripheral Signal mode. For specific
inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.
32-bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter
reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timers 1 and 2 are reserved for
Real-Time OS (RTOS) applications. CPU-Timer 2 is connected to INT14 of the CPU. CPU-Timer 1 can be
connected to INT13 of the CPU. CPU-Timer 0 is for general use and is connected to the PIE block.
motor control peripherals
The F2810 and F2812 support the following peripherals which, are used for controlling motors:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units,
capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event
managers are provided which enable two three-phase motors to be driven or four two-phase
motors. The event managers on the F2810 and F2812 are compatible to the event managers
on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It will contain two
sample-and-hold units for simultaneous sampling.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial port peripherals
The F2810 and F2812 support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping
of messages, and is CAN 2.0B-compliant.
McBSP:
This is the multichannel buffered serial port that is used to connect to E1/T1 lines,
phone-quality codecs for modem applications or high-quality stereo-quality Audio DAC
devices. The McBSP receive and transmit registers are supported by a 16-level FIFO. This
significantly reduces the overhead for servicing this peripheral.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
DSP controller and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of the
SPI. On the F2810 and the F2812, the port supports a 16-level, receive and transmit FIFO
for reducing servicing overhead.
SCI:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. On the F2810 and the F2812, the port supports a 16-level, receive and
transmit FIFO for reducing servicing overhead.
register map
The F2810 device contains three peripheral register spaces. The spaces are categorized as follows:
D
D
D
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 4.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 5.
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 6.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
register map (continued)
Table 4. Peripheral Frame 0 Registers
†
NAME
CPU Emulation Register Space
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x0000 0800
0x0000 087F
128
EALLOW protected
0x0000 0880
0x0000 09FF
Device Emulation Registers
reserved
384
128
96
EALLOW protected
0x0000 0A00
0x0000 0B00
0x0000 0A80
0x0000 0ADF
EALLOW protected
CSM Protected
‡
FLASH Registers
0x0000 0AE0
0x0000 0AEF
Code Security Module Registers
reserved
16
EALLOW protected
0x0000 0AF0
0x0000 0B1F
48
0x0000 0B20
0x0000 0B3F
XINTF Registers
reserved
32
Not EALLOW protected
Not EALLOW protected
0x0000 0B40
0x0000 0BFF
192
64
0x0000 0C00
0x0000 0C3F
CPU-TIMER0/1/2 Registers
reserved
0x0000 0C40
0x0000 0CDF
160
32
0x0000 0CE0
0x0000 0CFF
PIE Registers
Not EALLOW protected
EALLOW protected
0x0000 0D00
0x0000 0DFF
PIE Vector Table
reserved
256
512
0x0000 0E00
0x0000 0FFF
†
‡
If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS instruction
disables writes. This prevents stray code or pointers from corrupting register contents.
The Flash Registers are also protected by the Code Security Module (CSM).
§
Table 5. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
User Accessible
0x0000 6000
0x0000 61FF
eCAN Registers
reserved
512
0x0000 6200
0x0000 6FFF
3584
§
Peripheral Frame 1 allows 16-bit and 32-bit accesses. All 32-bit accesses are aligned to even address boundaries.
22
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
register map (continued)
†
Table 6. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
0x0000 7000
0x0000 700F
reserved
16
0x0000 7010
0x0000 702F
System Control Registers
reserved
32
16
EALLOW Protected
0x0000 7030
0x0000 703F
0x0000 7040
0x0000 704F
SPI-A Registers
SCI-A Registers
reserved
16
Not EALLOW Protected
Not EALLOW Protected
0x0000 7050
0x0000 705F
16
0x0000 7060
0x0000 706F
16
0x0000 7070
0x0000 707F
External Interrupt Registers
reserved
16
Not EALLOW Protected
0x0000 7080
0x0000 70BF
64
0x0000 70C0
0x0000 70DF
GPIO Mux Registers
GPIO Data Registers
ADC Registers
reserved
32
EALLOW Protected
0x0000 70E0
0x0000 70FF
32
Not EALLOW Protected
Not EALLOW Protected
0x0000 7100
0x0000 711F
32
0x0000 7120
0x0000 73FF
736
64
0x0000 7400
0x0000 743F
EV-A Registers
reserved
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
0x0000 7440
0x0000 74FF
192
64
0x0000 7500
0x0000 753F
EV-B Registers
reserved
0x0000 7540
0x0000 774F
528
16
0x0000 7750
0x0000 775F
SCI Registers
reserved
0x0000 7760
0x0000 77FF
160
64
0x0000 7800
0x0000 783F
McBSP Registers
reserved
0x0000 7840
0x0000 7FFF
1984
†
Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
23
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
device emulation registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 7.
Table 7. Device Emulation Registers
NAME
ADDRESS RANGE
SIZE (x16)
DESCRIPTION
0x0000 0880
0x0000 0881
DEVICECNF
2
Device Configuration Register
Device ID Register
0x0000 0882
0x0000 0883
DEVICEID
2
PROTSTART
PROTRANGE
0x0000 0884
0x0000 0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
0x0000 0886
0x0000 09FF
reserved
378
Table 8. DEVICECNF Register Bit Definitions
BITS
1:0
2
NAME
TYPE
R/W
R =0
R
RESET
DECSRIPTION
reserved
reserved
VMAPS
reserved
XRS
1,1
0
For Test Only
3
0/1
0
VMAP Configure Status. This indicates the status of VMAP.
4
R = 0
R
5
0/1
1
Reset Input Signal Status. This is connected directly to the XRS input pin.
6
reserved
reserved
reserved
reserved
reserved
reserved
reserved
ENPROT
R = 1
R/W
R = 0
R/W
R = 1
R = 1
R = 1
R/W
7
0
14:8
15
16
17
18
19
0:0
0
For Test Only
1
1
1
1
Enable Write-Read Protection Mode Bit. This bit, when set to 1, will enable
write-read protection as specified by the PROTSTART and PROTRANGE
registers. This bit, when set to 0, disables this protection mode.
31:20
spares
R = 0
0
Table 9. DEVICEID Register Bit Definitions
BITS
NAME
TYPE
RESET
DECSRIPTION
15:0
PARTID
R
Dependent on
device
These 16 bits specify the part number of the device as follows:
0x0001: F2810 device
0x0002: F2812 device
31:16
REVID
R
0x0001
(for first silicon)
These 16 bits specify the silicon revision number for the particular
part. This number always starts with 0x0001 on the first revision of the
silicon and is incremented on any subsequent revisions.
24
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
device emulation registers (continued)
The PROTSTART and PROTRANGE registers set the memory address range for which CPU “write” followed
by“read”operationsareprotected(operationsoccurinsequenceratherthenintheirnaturalpipelineorder). This
is necessary protection for certain peripheral operations.
Example:
The following lines of code perform a write to register 1 (REG1) location and then the next
instruction performs a read from Register 2 (REG2) location. On the processor memory bus,
with block protection disabled, the read operation will be issued before the write as shown:
MOV
@REG1,AL
–––––+
–––––|––––> Read
+––––> Write
TBIT @REG2,#BIT_X
If block protection is enabled, then the read is stalled until the write occurs as shown:
MOV
@REG1,AL
–––––+
–––+ |
TBIT @REG2,#BIT_X
| +––––> Write
+––––––> Read
NOTE: The C28x CPU automatically protects writes followed by reads to the same memory
address. The protection mechanism described above is for cases where the address
is not the same, but within a given region in memory (as defined by the PROTSTART
and POROTRANGE registers).
Table 10. PROTSTART and PROTRANGE Registers
NAME
ADDRESS
SIZE
TYPE
RESET
DECSRIPTION
†
PROTSTART
0x0000 0884
16
R/W
0x0100
ThePROTSTARTregistersetsthestartingaddressrelativetothe16
most significant bits of the processors lower 22-bit address reach.
Hence, the smallest resolution is 64 words.
†
PROTRANGE
0x0000 0885
16
R/W
0x00FF
The PROTRANGE register sets the block size (from the starting
address), starting with 64 words and incrementing by binary
multiples (64, 128, 256, 512, 1K, 2K, 4K, 8K, 16K, ...., 2M).
†
The default values of these registers on reset are selected to cover the Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 areas of the
memory map (address range 0x0000 4000 to 0x0000 8000).
25
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
device emulation registers (continued)
†
Table 11. PROTSTART Valid Values
REGISTER BITS
START ADDRESS
0x0000 0000
0x0000 0040
0x0000 0080
0x0000 00C0
REGISTER VALUE
0x0000
15
0
14
0
13
0
12
0
11
0
10
0
9
0
0
0
0
8
0
0
0
0
7
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0x0001
0
0
0
0
0
0
0x0002
0
0
0
0
0
0
0x0003
0
0
0
0
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0x003F FF00
0x003F FF40
0x003F FF80
0x003F FFC0
0xFFFC
0xFFFD
0xFFFE
0xFFFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
†
The quickest way to calculate register value is to divide the desired block starting address by 64.
‡
Table 12. PROTRANGE Valid Values
REGISTER BITS
BLOCK SIZE
64
REGISTER VALUE
0x0000
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
12
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
11
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
10
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
9
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
8
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
2
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
128
0x0001
256
0x0003
512
0x0007
1K
0x000F
0x001F
0x003F
0x007F
0x00FF
0x01FF
0x03FF
0x07FF
0x0FFF
0x1FFF
0x3FFF
0x7FFF
0xFFFF
2K
4K
8K
16K
32K
64K
128K
256K
512K
1M
2M
4M
‡
Not all register values are valid. The PROTSTART address value must be a multiple of the range value. For example: if the block size is set to
4K, then the start address can only be at any 4K boundary.
26
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
external interface, XINTF (F2812 only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812 device.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the F2812 is mapped into five fixed zones shown in Figure 3.
Figure 3 shows the F2812 XINTF signals.
Data Space
Prog Space
0x0000–0000
XD(15:0)
XA(18:0)
0x0000–2000
0x0000–4000
XINTF Zone 0
XZCS0
XZCS1
(8K × 16)
XINTF Zone 1
(8K × 16)
0x0000–6000
0x0008–0000
XINTF Zone 2
(512K × 16)
XZCS2
0x0010–0000
XINTF Zone 6
(1M × 16)
XZCS6
XZCS7
XZCS6AND7
0x0020–0000
0x003F–C000
XINTF Zone 7
(16K × 16)
(mapped here if MP/MC =1)
0x0040–0000
XWE
XRD
XRNW
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT (see Note D)
NOTES: A. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2
register). Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip selects (XZCS0,
XZCS1, XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless
connection to many external memories and peripherals.
C. The chip selects for Zone 6 and 7 are ANDed internally together to form one chip select (XZCS6AND7). Any external memory
that is connected to XZCS6AND7 is dually mapped to both Zones 6 and Zone 7. This means that if Zone 7 is disabled (via the
MP/MC mode) then any external memory is still accessible via Zone 6 address space.
D. XCLKOUT is also pinned out on the F2810.
Figure 3. External Interface Block Diagram
27
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DIGITAL SIGNAL PROCESSORS
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external interface, XINTF (F2812 only) (continued)
The operation and timing of the external interface, can be controlled by the registers listed in Table 13.
Table 13. XINTF Configuration and Control Register Mappings
NAME
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XINTCNF2
XBANK
ADDRESS
SIZE (x16)
DESCRIPTION
0x0000–0B20
0x0000–0B22
0x0000–0B24
0x0000–0B2C
0x0000–0B2E
0x0000–0B34
0x0000–0B38
0x0000–0B3A
2
2
2
2
2
2
1
1
XINTF Timing Register, Zone 0
XINTF Timing Register, Zone 1
XINTF Timing Register, Zone 2
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XREVISION
timing registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The timing parameters can be
configured individually for each zone. This allows the programmer to maximize the efficiency of the bus, based
on the type of memory or peripheral that the user needs to access. All XINTF timing values are with respect to
XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in Figure 4.
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
SYSCLKOUT
C28x
CPU
XTIMCLK
1
0
/2
XCLKOUT
1
0
/2
XINTCNF2 (XTIMCLK)
XINTCNF2 (CLKMODE)
Default Value after reset
Figure 4. Relationship Between XTIMCLK and SYSCLKOUT
28
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
timing registers (continued)
The individual timing parameters can be programmed into the XTIMING registers as described in Table 14.
Table 14. XTIMING0/1/2/6/7 Register Bit Definitions
BIT
NAME
ACCESS
RESET
DESCRIPTION
1:0
XWRTRAIL
R/W
1,1
Two-bit field that defines the write cycle trail period, in XTIMCLK cycles, from
0,1,2,3 (if X2TIMING bit is 0) or 0,2,4,6 (if X2TIMING bit is 1).
4:2
XWRACTIVE
R/W
1,1,1
Three-bit field that defines the write cycle active wait-state period, in XTIMCLK
cycles, from 0,1,2,3,4,5,6,7 (if X2TIMING bit is 0) or 0,2,4,6,8,10,12,14 (if
X2TIMING bit is 1).
Notes: 1. If the USEREADY bit is set to 1 (using XREADY),
then XWRACTIVE must be ≥ 1.
2. The active period is by default 1 cycle. Hence the total active period
is 1 + XWRACTIVE value.
6:5
XWRLEAD
R/W
1,1
Two-bitfieldthatdefinesthewritecycleleadperiod, inXTIMCLKcycles, from1,2,3
(if X2TIMING bit is 0) or 2,4,6 (if X2TIMING bit is 1).
Note: XWRLEAD must be ≥ 1.
8:7
XRDTRAIL
R/W
R/W
1,1
Two-bit field that defines the read cycle trail period, in XTIMCLK cycles, from
0,1,2,3 (if X2TIMING bit is 0) or 0,2,4,6 (if X2TIMING bit is 1).
11:9
XRDACTIVE
1,1,1
Three-bit field that defines the read cycle active wait-state period, in XTIMCLK
cycles, from 0,1,2,3,4,5,6,7 (if X2TIMING bit is 0) or 0,2,4,6,8,10,12,14
(if X2TIMING bit is 1).
Notes: 1. If the USEREADY bit is set to 1 (using XREADY),
then XRDACTIVE must be ≥ 1.
2. The active period is by default 1 cycle. Hence the total active period
is 1 + XRDACTIVE value.
13:12
14
XRDLEAD
R/W
R/W
1,1
1
Two-bitfieldthatdefinesthereadcycleleadperiod, inXTIMCLKcycles, from1,2,3
(if X2TIMING bit is 0) or 2,4,6 (if X2TIMING bit is 1).
Note: XRDLEAD must be ≥ 1.
USEREADY
When set, the XREADY signal can be used to further extend the active portion of
the cycle past the minimum defined by the XRDACTIVE and XWRACTIVE fields.
When cleared XREADY is ignored.
15
READYMODE
Reserved
R/W
R/W
1
When set, the XREADY input is asynchronous. When cleared, the XREADY input
is synchronous.
17:16
1,1
Reserved.
Thesetwobitsmustalwaysbewrittentoas1,1. Anyothercombinationisreserved
and will result in incorrect XINTF behavior.
21:18
22
Reserved
R
0
1
Reserved
X2TIMING
R/W
This bit specifies the scaling factor of the LEAD, ACTIVE, TRAIL values in the
individual timing registers. If this bit is 0, the values are scaled 1:1. If this bit is 1,
the values are scaled 2:1 (doubled). The default mode of operation on power up
and reset is 2:1 scaling (doubled) mode.
31:23
Reserved
R
0
29
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
timing registers (continued)
The minimum timing settings for an XINTF access is as follows:
D
When the XREADY option is NOT used:
The minimum strobe setting is Lead = 1, Active = 0, Trail = 0
Hence: L = 0, A = 0,T = 0 settings are not allowed (L = 1, A = 0,T = 0 or L = 1, A = 1,T = 0 or L = 1, A = 0, T = 1 or
greater are allowed)
D
When the XREADY option is used:
The minimum strobe setting is Lead = 1, Active = 1, Trail = 0
Hence: L = 0, A = 0, T = 0 settings are not allowed (L = 1, A = 1, T = 0 or L = 1, A = 1, T = 1 or greater are
allowed).
No logic is included to detect illegal settings.
30
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
XINTCNF2 register
Table 15. XINTCNF2 Register Bit Definitions
BITS
TYPE
NAME
RESET
DESCRIPTION
1,0
R/W
Write
Buffer
Depth
0,0
The write buffer allows the processor to continue execution without waiting for
XINTFwriteaccessestocomplete. Thewritebufferdepthisselectableasfollows:
Depth
Action
00
No write buffering. The CPU will be stalled until the write
completes on the XINTF.
Note: Default mode on reset (XRS).
01
10
11
The XINTF will buffer one word. The CPU is stalled until the
write cycle begins on the XINTF (there could be a read cycle
currently active on the XINTF).
One write will be buffered without stalling the CPU. The CPU
is stalled if a second write follows. The CPU will be stalled
until the first write begins its cycle on the XINTF.
Two writes will be buffered without stalling the CPU. The CPU
is stalled if a third write follows. The CPU will be stalled until
the first write begins its cycle on the XINTF.
The buffered access can be 8, 16, or 32 bits in length. Order of execution is
preserved, e.g., writes are performed in the order they were accepted. The
processor is stalled on XINTF reads until all pending writes are done and the read
access completes. If the buffer is full, any pending reads or writes to the buffer
will stall the processor.
The “Write Buffer Depth” can be changed; however, it is recommended that the
write buffer depth be changed only when the buffer is empty (this can be checked
by reading the “Write Buffer Level” bits). Writing to these bits when the level is not
zero may have unpredictable results.
2
3
R/W
R/W
CLKMODE
Mode
1
0
XCLKOUT divide by 2 mode. If this bit is set to 1, XCLKOUT is a divide by 2 of
XTIMCLK. If this bit is set to 0, XCLKOUT is equal to XTIMCLK. All bus timings,
irrespectiveof which mode is enabled, will start from the rising edge of XCLKOUT.
The default mode of operation on power up and reset is /2 mode.
CLKOFF
Turn XCLKOUT off mode. When this bit is set to 1, the XCLKOUT signal is turned
off. This is done for power savings and noise reduction. This bit is set to 0 on a
reset.
4
5
R
R
Reserved
Reserved
1
0
Reserved
Reserved
31
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
XINTCNF2 register (continued)
Table 15. XINTCNF2 Register Bit Definitions (Continued)
BITS
TYPE
NAME
RESET
DESCRIPTION
7,6
R
WLEVEL
0,0
The current number of writes buffered are detectable as follows:
Level
Action
00
01
10
11
empty
1 value currently in the write buffer
2 values currently in the write buffer
3 values currently in the write buffer
The value in the write buffer may be 8-, 16-, or 32-bit data.
Note: There may be a few cycle delay from when a value enters the write buffer
to the buffer level depth being updated.
8
R/W
MP/MC
Mode
On reset, this bit reflects the state of the XMP/MC input signal sampled at XRS.
The user can modify the state of this bit by writing a 1 or a 0 to this location. This
willbereflectedontheXMP/MCoutputsignal. ThismodealsoaffectsZONE7and
Boot ROM mapping as follows:
MP/MC = 1, microprocessor state
(XINTF ZONE 7 enabled, Boot ROM disabled).
MP/MC = 0, microcomputer state
(XINTF ZONE 7 disabled, Boot ROM enabled).
Note: The XMP/MC input signal state is ignored after reset.
9
R/W
HOLD
0
This bit, when low, will automatically grant a request to an external device driving
the XHOLD input signal low (XHOLDA output signal is driven low when request
granted). This bit, when set high, will not automatically grant a request to an
external device driving the XHOLD input signal low (XHOLDA output signal stays
high).
If this bit is set, while XHOLD and XHOLDA are both low (external bus accesses
granted) then the XHOLDA signal is forced high (at the end of the current cycle)
and the exteranl interface is taken out of high-impedance mode.
On a reset XRS, this bit is set to zero. If on a reset the XHOLD signal is active-low,
then the bus and all signal strobes must be in high-impedance state and the
XHOLDA signal also driven active-low.
When HOLD mode is enabled and XHOLDA is active-low (external bus grant
active) then the core can still execute code from internal memory. If an access is
made to the external interface, then a not ready signal is generated and the core
is stalled until the XHOLD signal is removed.
10
11
R
R
HOLDS
XHOLD input
signal
This bit reflects the current state of the XHOLD input signal. It can be read by the
user to determine if an external device is requesting access to the external bus.
HOLDAS
XHOLDA input
signal
This bit reflects the current state of the XHOLDA output signal. It can be read by
the user to determine if the external interface is currently granting access to an
external device.
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
XINTCNF2 register (continued)
Table 15. XINTCNF2 Register Bit Definitions (Continued)
BITS
15:12
18:16
TYPE
X
NAME
RESET
0
DESCRIPTION
Reserved
XTIMCLK
Reserved
R/W
0,0,1
These bits select the fundamental clock for the timing of lead, active and trail
switching operations as defined by the XTIMING and XBANK registers:
Mode
Action
0,0,0
0,0,1
0,1,0
0,1,1
1,0,0
1,0,1
1,1,0
1,1,1
XTIMCLK = SYSCLKOUT/1
XTIMCLK = SYSCLKOUT/2
reserved
reserved
reserved
reserved
reserved
reserved
XBANK register
Table 16. XBANK Register Bit Defintions
BITS
TYPE
NAME
RESET
DESCRIPTION
2:0
R/W
BANK
1,1,1
These bits specify the XINTF zone for which bank switching is enabled, ZONE
0 to ZONE 7. At reset, XINTF Zone 7 is selected.
5:3
R/W
BCYC
1,1,1
These bits specify the number of XTIMCLK cycles to add between any
consecutive access that crosses into or out of the specified zone, be it a read or
write, program or data space. The number of XTIMCLK cycles can be 0 to 14.
On a reset (XRS) the value defaults to 14 cycles.
14:6
15
X
Reserved
Reserved
R/W
1
XREVISION register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the F2812, this register will be configured as described in Table 17.
Table 17. XREVISION Register Bit Defintions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
15–0
REVISION
R
0x0004
Current XINTF Revision. For internal use/reference. Test purposes only. Subject to
change.
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
interrupts
Figure 5 shows how the various interrupt sources are multiplexed within the F2810 and F2812 devices.
Peripherals (SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
Watchdog
WAKEINT
LPMINT
Low-Power Modes
XINT1
Interrupt Control
PIE
XINT1CR(15:0)
XINT1CTR(15:0)
INT1 to INT12
XINT2
Interrupt Control
XINT2CR(15:0)
C28x CPU
XINT2CTR(15:0)
GPIO
MUX
TINT0
TIMER 0
TINT2
TINT1
TIMER 2 (for RTOS)
TIMER 1 (for RTOS)
INT14
INT13
select
enable
NMI
XNMI_XINT13
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
†
Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 5. Interrupt Sources
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
interrupts (continued)
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the F2810/F2812, 45 of these are used by peripherals as shown
in Table 18.
IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
(Enable)
(Flag)
PIEIERx(7:1)
PIEIFRx(7:1)
Figure 6. Multiplexing of Interrupts Using the PIE Block
†
Table 18. PIE Peripheral Interrupts
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
PDPINTA
(EV-A)
PDPINTB
(EV-B)
ADCINT
(ADC)
TINT0
(TIMER 0)
WAKEINT
(LPM/WD)
INT1
INT2
INT3
INT4
INT5
INT6
reserved
XINT1
XINT2
CMP1INT
(EV-A)
CMP2INT
(EV-A)
CMP3INT
(EV-A)
T1PINT
(EV-A)
T1CINT
(EV-A)
T1UFINT
(EV-A)
T1OFINT
(EV-A)
reserved
reserved
reserved
reserved
reserved
T2PINT
(EV-A)
T2CINT
(EV-A)
T2UFINT
(EV-A)
T2OFINT
(EV-A)
CAPINT1
(EV-A)
CAPINT2
(EV-A)
CAPINT3
(EV-A)
CMP4INT
(EV-B)
CMP5INT
(EV-B)
CMP6INT
(EV-B)
T3PINT
(EV-B)
T3CINT
(EV-B)
T3UFINT
(EV-B)
T3OFINT
(EV-B)
T4PINT
(EV-B)
T4CINT
(EV-B)
T4UFINT
(EV-B)
T4OFINT
(EV-B)
CAPINT4
(EV-B)
CAPINT5
(EV-B)
CAPINT6
(EV-B)
SPIAINT
(SPI)
SPIATX
(SPI)
MRINT
(McBSP)
MXINT
(McBSP)
reserved
reserved
reserved
INT7
INT8
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
RXAINT
(SCI-A)
TXAINT
(SCI-A)
RXBINT
(SCI-B)
TXBINT
(SCI-B)
HECC0INT
(CAN)
HECC1INT
(CAN)
INT9
reserved
reserved
INT10
INT11
INT12
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
†
Out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. However, these
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
vector table mapping
The interrupt vector table can be mapped into the five distinct areas listed in Table 19.
†
Table 19. Interrupt Vector Table Mapping
VECTORS FETCHED
VECTOR MAPS
ADDRESS RANGE
VMAP
M0M1MAP
MP/MC
ENPIE
FROM
‡
M1 Vector
M1 SARAM Block
M0 SARAM Block
ROM Block
0x000000–0x00003F
0x000000–0x00003F
0x3FFFC0–0x3FFFFF
0x3FFFC0–0x3FFFFF
0x000D00–0x000DFF
0
0
1
1
1
0
1
X
X
0
X
X
0
0
1
M0 Vector
BROM Vector
X
X
X
§
XINTF Vector
XINTF Zone 7 Block
PIE Block
1
PIE Vector
X
†
‡
§
On the F2810 and F2812 devices, the VMAP and M0M1MAP modes are set to “1” on reset. The ENPIE mode is forced to “0” on reset.
Vector map M1 Vector is a reserved mode only.
Valid on F2812 only
After reset operation, the vector table will be located in the areas listed in Table 20.
†
Table 20. Vector Table Mapping After Reset Operation
RESET FETCHED
VECTOR MAPS
ADDRESS RANGE
VMAP
M0M1MAP
MP/MC
ENPIE
FROM
BROM Vector
ROM Block
0x3FFFC0–0x3FFFFF
0x3FFFC0–0x3FFFFF
1
1
1
1
0
1
0
0
§
XINTF Vector
XINTF Zone 7 Block
†
§
On the F2810 and F2812 devices, the VMAP and M0M1MAP modes are set to “1” on reset. The ENPIE mode is forced to “0” on reset.
Valid on F2812 only
The vector mapping is controlled by the following mode bits/signals:
VMAP:
This bit is found in Status Register 1 (bit 3). A device reset sets this bit to 1. The state of this
bit can be modified by writing to ST1 or by “SETC/CLRC VMAP” instructions.
M0M1MAP:
This bit is found in Status Register 1 (bit 11). A device reset sets this bit to 1. The state of this
bit can be modified by writing to ST1 or by “SETC/CLRC M0M1MAP” instructions. This bit
should remain set. M0M1MAP = 0 is reserved for TI testing.
MP/MC:
ENPIE:
This bit is found in XINTCNF2 Register (bit 8). On the F2812, the default value of this bit, on
reset, is set by the XMP/MC input device signal. On the F2810, XMP/MC is tied low internally.
The state of this bit can be modified by writing to the XINTCNF2 register (address 0x0000
0B34).
This bit is found in PIECTRL Register (bit 0). The default value of this bit, on reset, is set to “0”
(PIE disabled). The state of this bit can be modified by writing to the PIECTRL register
(address 0x0000 0CE0).
The external interrupts are configured using the registers listed in Table 27.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
vector table mapping (continued)
Used for Test Purposes Only
Recommended Flow for F2810/F2812 Applications
Reset
(Power-on Reset or
Warm Reset)
PIE Disabled (ENPIE = 0)
VMAP = 1
OBJMODE = 0
AMODE = 0
M0M1MAP = 1
(F2812 Only)
No
XMP/MC
input signal
Reset Vector Fetched
from XINTF Vector Map
†
= 0?
User Code Initializes:
Yes
Reset Vector Fetched
from Boot ROM
‡
OBJMODE and AMODE State
Using
Peripheral
Interrupts?
No
CPU IER Register and INTM
VMAP State
Branch into Bootloader
routines depending on
the state of GPIO Pins
¶
MP/MC Status Bit
Yes
User Code Initializes:
‡
OBJMODE and AMODE State
No
Vectors (except for reset) will be
fetched from M0 Vector Map
VMAP = 1?
§
PIE Enable (ENPIE = 1)
PIE Vector Table
PIEIERx Registers
CPU IER Register and INTM
Yes
(F2812 Only)
No
Vectors (except for reset)
will be
fetched from PIE Vector Map
MP/MC
status bit =
Vectors (except for reset) will be
¶
0?
§
§
fetched from XINTF Vector Map
Yes
Vectors (except for reset)
will be Fetched From
§
BROM Vector Map
†
‡
The XMP/MC input signal is tied low internally on the F2810.
The compatibility operating mode of the F2810 and F2812 is determined by a combination of the OBJMODE and AMODE bits in Status
Register 1 (ST1):
Operating Mode
OBJMODE
AMODE
C28x Mode
1
1
0
0
1
C2xLP Source-Compatible
C27x Object-Compatible
0
(Default at reset)
§
¶
The reset vector is always fetched from either the BROM or XINTF vector map depending on the XMP/MC input signal.
The state of the XMP/MC signal is latched into the MP/MC bit at reset, it can then be modified by software.
Figure 7. Reset Flow Diagram
37
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
PIE vector map
The PIE Vector Table (Table 21) consists of a 256 x 16 SARAM that can also be used as RAM if the PIE block
is not in use. The PIE vector table contents are undefined on reset. Interrupt priority for INT1 to INT12 is fixed
by the CPU. Priority for each group of 8 interrupts is, controlled by the PIE. For example: if INT1.1 should occur
simultaneously with INT8.1, both interrupts will be presented to the CPU simultaneously by the PIE block, and
the CPU will service INT1.1 first. If INT1.1 should occur simultaneously with INT1.8, then INT1.1 will be sent
to the CPU first and then INT1.8 will follow. Interrupt prioritization is performed during the vector fetch portion
of the interrupt processing. A “TRAP 1” to “TRAP 12” instruction or an “INTR INT1” to “INTR INT12” instruction
will always fetch the vector from the first location of each group (“INTR1.1” to “INT12.1”). Hence, it is
recommended that these instructions not be used when PIE is enabled. The “TRAP 0” operation will fetch the
vector from location 0x0000 0D00. The vector table is EALLOW protected.
Table 21. PIE Vector Table
SIZE
(x16)
PIE GROUP
PRIORITY
NAME
ADDRESS
DESCRIPTION
CORE PRIORITY
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
INT13
0x0000 0D00
0x0000 0D02
0x0000 0D04
0x0000 0D06
0x0000 0D08
0x0000 0D0A
0x0000 0D0C
0x0000 0D0E
0x0000 0D10
0x0000 0D12
0x0000 0D14
0x0000 0D16
0x0000 0D18
0x0000 0D1A
2
2
2
2
2
2
2
2
2
2
2
2
2
2
RESET never fetched here
INT1 remapped to INT1.1–INT1.8 below
INT2 remapped to INT2.1–INT2.8 below
INT3 remapped below
1 (highest)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
INT4 remapped below
–
INT5 remapped below
–
INT6 remapped below
–
INT7 remapped below
–
INT8 remapped below
–
INT9 remapped below
–
INT10 remapped below
INT11 remapped below
INT12 remapped below
–
–
–
External Interrupt 13 (XINT13) or
CPU-Timer 1 (for RTOS use)
17
INT14
DATALOG
RTOSINT
EMUINT
NMI
0x0000 0D1C
0x0000 0D1E
0x0000 0D20
0x0000 0D22
0x0000 0D24
0x0000 0D26
0x0000 0D28
.
2
2
2
2
2
2
2
.
CPU-Timer 2 (for RTOS use)
CPU Data Logging Interrupt
CPU Real-Time OS Interrupt
CPU Emulation Interrupt
External Non-Maskable Interrupt
Illegal Operation
18
–
19 (lowest)
–
4
2
3
–
–
.
–
–
–
ILLEGAL
USER0
.
–
User Defined Trap
–
.
.
USER11
INT1.1
.
0x0000 0D3E
0x0000 0D40
.
2
2
.
User Defined Trap
–
–
1 (highest)
.
Group 1 Interrupt Vectors
5
INT1.8
0x0000 0D4E
2
8 (lowest)
.
.
.
.
.
.
.
.
.
Group 2 Interrupt Vectors
to
Group 11 Interrupt Vectors
6
to
15
INT12.1
.
0x0000 0DF0
2
.
1 (highest)
.
.
Group 12 Interrupt Vectors
16
INT12.8
0x0000 0DFE
2
8 (lowest)
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
PIE registers
The registers controlling the functionality of the PIE block are listed in Table 22.
Table 22. PIE Configurations and Control Register Mappings
†
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
reserved
0x0000–0CE0
0x0000–0CE1
0x0000–0CE2
0x0000–0CE3
0x0000–0CE4
0x0000–0CE5
0x0000–0CE6
0x0000–0CE7
0x0000–0CE8
0x0000–0CE9
0x0000–0CEA
0x0000–0CEB
0x0000–0CEC
0x0000–0CED
0x0000–0CEE
0x0000–0CEF
0x0000–0CF0
0x0000–0CF1
0x0000–0CF2
0x0000–0CF3
0x0000–0CF4
0x0000–0CF5
0x0000–0CF6
0x0000–0CF7
0x0000–0CF8
0x0000–0CF9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
reserved
0x0000–0CFA
0x0000–0CFF
†
The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
PIE registers (continued)
Table 23. PIECTRL Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
Enable vector fetching from PIE block. When this bit is set to 1, all vectors are fetched from
0
ENPIE
R/W
0
the PIE vector table. If this bit is set to 0, the PIE block is disabled and vectors are fetched
as normal. All PIE block registers (PIEACK, PIEIFR, PIEIER) can be accessed even when
the PIE block is disabled.
15:1
PIEVECT
R
0
Vector fetch address. Displays the address of the vector that was fetched. The least
significant bit of the address is ignored and only bits 1 to 15 are shown. The vector address
can be used to determine which interrupt generated the fetch.
Table 24. PIEACK Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
11:0
PIEACK
R/W=1
0
Writinga 1 to the respective interrupt bit enables the PIE block to drive a pulse into the CPU
interrupts input, if an interrupt is pending on any of the group interrupts. Reading this
register indicates if an interrupt is pending in the respective group. Bit 0 refers to INT1 up
to Bit 11, which refers to INT12.
Note: Writes of 0 are ignored.
15:12
spares
R=0
0
†
Table 25. PIEIERx Register Bit Definitions
BIT(S)
NAME
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
spares
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R=0
RESET
DESCRIPTION
0
1
0
0
0
0
0
0
0
0
0
2
3
These register bits individually enable an interrupt within a group. They behave very much
like the CPU interrupt enable register. Setting a bit to 1 will enable the servicing of the
respective interrupt. Setting a bit to 0 will disable the servicing of the bit.
4
5
6
7
15:8
†
x = 1 to 12. INTx means CPU interrupts INT1 to INT12.
†
Table 26. PIEIFRx Register Bit Definitions
BIT(S)
NAME
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
INTx.6
INTx.7
INTx.8
spares
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R=0
RESET
DESCRIPTION
0
1
0
0
0
0
0
0
0
0
0
These register bits indicate if an interrupt is currently active. They behave very much like
the CPU interrupt flag register. When an interrupt is active, the respective register bit is set.
The bit is cleared when the interrupt is serviced or by writing a 0 to the register bit. This
register can also be read to determine which interrupts are active or pending.
2
3
4
5
Note: The PIEIFR register bit is cleared during the interrupt vector fetch portion of
the interrupt processing.
6
7
15:8
†
x = 1 to 12. INTx means CPU interrupts INT1 to INT12.
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
PIE/CPU interrupt response
Figure 8 shows the behavior of the PIE hardware under various PIEIFR and PIEIER register conditions. There
is one PIEACK bit for every CPU interrupt group (INT1 to INT12) and is referred to as PIEACK(x). There is a
corresponding PIEIFR and PIEIER register for each group and are referred to as the PIEIFRx and PIEIERx
registers. Figure 8 describes the operation of one PIE interrupt. This flow is common to all PIE interrupts.
Stage E
IFRx Bit Set 1
Start
No
No
Stage A
PIEIFRx.y = 1
Stage F
IERx Bit = 1
Wait for any
PIEIFRx.y = 1
Wait for
IERx = 1
Yes
Yes
No
No
Stage G
INTM Bit = 0
Stage B
PIEIERx.y = 1
Wait for INTM = 0
Wait for PIEIERx.y = 1
Yes
Yes
Stage H
CPU Responds
Branches to Vector Address at PIEIFRx.y
IFRx Bit Cleared
No
Vector Branch
Context Save
Wait for S/W
to Clear
PIEACKx Bit = 0
Stage C
PIEACKx = 0
IER = 0
INTM = 1
PIEIFRx.y Bit Cleared
Stage I
Interrupt Service Routine Responds
Write 1 to PIEACKx Bit to Clear to Enable
Other Interrupts in PIEIFRx Group
Re-enable Interrupts, INTM = 0
Return
Interrupt Service
Routine (ISR)
for PIEIFRx.y
Yes
Stage D
Interrupt Request Sent to
28x CPU on INTx
Interrupts to
CPU
End
PIE Interrupt
Control
CPU Interrupt
Control
Figure 8. Typical PIE/CPU Interrupt Response–INTx.y
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
external interrupts
Table 27. External Interrupts Registers
NAME
XINT1CR
ADDRESS RANGE
0x0000 7070
SIZE (x16)
DESCRIPTION
1
1
5
XINT1 configuration register
XINT2 configuration register
XINT2CR
reserved
0x0000 7071
0x0000 7072
0x0000 7076
XNMICR
0x0000 7077
0x0000 7078
0x0000 7079
1
1
1
5
XNMI configuration register
XINT1 counter register
XINT2 counter register
XINT1CTR
XINT2CTR
reserved
0x0000 707A
0x0000 707E
XNMICTR
0x0000 707F
1
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. The register
bits to control this are described in Table 28.
Table 28. XINT1/2CR Register Bit Definitions
BITS
NAME
TYPE
RESET
DESCRIPTION
0
ENABLE
R/W
0
0
1
Interrupt Disabled
Interrupt Enabled
1
2
reserved
R = 0
R/W
0
0
POLARITY
0
1
Interrupt is selected as negative edge triggered
Interrupt is selected as positive edge triggered
15:3
reserved
R = 0
0:0
Table 29 shows the bit definitions of the XNMICR register.
Table 29. XNMICR Register Bit Definitions
BITS
NAME
TYPE
RESET
DESCRIPTION
0
ENABLE
R/W
0
0
1
NMI Interrupt Disabled
NMI Interrupt Enabled
1
2
SELECT
POLARITY
reserved
R/W
R/W
0
0
0
1
Timer 1 Connected To INT13
XNMI Connected To INT13
0
1
Interrupt is selected as negative edge triggered
Interrupt is selected as positive edge triggered
15:3
R = 0
0:0
42
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
external interrupts (continued)
The masked interrupts, XINT1/2 and NMI, also contain a 16-bit up-counter register that is reset to 0x0000
whenever an interrupt edge is detected. This counter can be used to accurately time stamp the occurrence of
the interrupt. Table 30 shows the bit definitions of the XINT1/2CTR and XNMICTR registers.
Table 30. XINT1/2CTR and XNMICTR Registers Bit Definitions
BITS
NAME
TYPE
RESET
DESCRIPTION
15:0
INTCTR
R
0:0
This is a free running 16-bit up-counter that is clocked at the SYSCLKOUT rate. The
countervalue is reset to 0x0000 when a valid interrupt edge is detected and then continues
counting until the next valid interrupt edge is detected. The counter must only be reset by
the selected POLARITY edge as selected in the respective interrupt control register. When
the interrupt is disabled, the counter will stop. The counter is a free-running counter and
will wrap around to zero when the max value is reached. The counter is a read only register
and can only be reset to zero by a valid interrupt edge or by reset.
43
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
system control
This section describes the F2810 and F2812 oscillator, PLL and clocking mechanisms, the watchdog function
and the low power modes. Figure 9 shows the various clock and reset domains in the F2810 and F2812 devices
that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN
X1/XCLKIN
X2
C28x
CPU
PLL
OSC
Power
Modes
Control
XPLLDIS
Clock Enables
System
Control
Registers
Peripheral
Registers
eCAN
I/O
I/O
I/O
LSPCLK
Low-Speed Prescaler
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
GPIOs
GPIO
MUX
HSPCLK
High-Speed Prescaler
Peripheral
Registers
High-Speed Peripherals
EV-A/B
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
Figure 9. Clock and Reset Domains
44
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
system control (continued)
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 31.
†
Table 31. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
reserved
ADDRESS
SIZE (x16)
DESCRIPTION
0x0000–7010
0x0000–7017
8
reserved
reserved
HISPCP
LOSPCP
PCLKCR
reserved
LPMCR0
LPMCR1
reserved
PLLCR
0x0000–7018
0x0000–7019
0x0000–701A
0x0000–701B
0x0000–701C
0x0000–701D
0x0000–701E
0x0000–701F
0x0000–7020
0x0000–7021
0x0000–7022
0x0000–7023
0x0000–7024
0x0000–7025
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
High-Speed Peripheral Clock Prescaler Register for HSPCLK clock
Low-Speed Peripheral Clock Prescaler Register for HSPCLK clock
Peripheral Clock Control Register
Low Power Mode Control Register 0
Low Power Mode Control Register 1
‡
PLL Control Register
SCSR
System Control & Status Register
Watchdog Counter Register
WDCNTR
reserved
WDKEY
reserved
Watchdog Reset Key Register
Watchdog Control Register
0x0000–7026
0x0000–7028
WDCR
0x0000–7029
1
6
reserved
0x0000–702A
0x0000–702F
†
‡
All of the above registers can only be accessed, by executing the EALLOW instruction.
The PLL control register (PLLCR) is reset to a known state by the XRS signal only.
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system control (continued)
The PCLKCR1 and PCLKCR2 registers basically enable/disable clocks to the various peripheral modules in
the F2810 and F2812 devices. Table 32 lists the bit descriptions of the PCLKCR1 and PCLKCR2 registers.
†
Table 32. PCLKCR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
0
EVAENCLK
R/W
0
If this bit is set, it enables the high-speed clock (HSPCLK) within the EV-A
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
1
EVBENCLK
R/W
0
If this bit is set, it enables the high-speed clock (HSPCLK) within the EV-B
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
2
3
reserved
R=0
R/W
0
0
reserved
ADCENCLK
If this bit is set, it enables the high-speed clock (HSPCLK) within the ADC
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
7:4
8
reserved
R=0
R/W
0:0
0
SPIAENCLK
If this bit is set, it enables the low-speed clock (LSPCLK) within the SPI
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
9
reserved
R=0
R/W
0
0
reserved
10
SCIAENCLK
If this bit is set, it enables the low-speed clock (LSPCLK) within the SCI-A
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
11
12
SCIBENCLK
MAENCLK
R/W
R/W
0
0
If this bit is set, it enables the low-speed clock (LSPCLK) within the SCI-B
peripheral. For low power operation, this bit is set to zero by the user or
by reset.
If this bit is set, it enables the low-speed clock (LSPCLK) within the
McBSP peripheral. For low power operation, this bit is set to zero by the
user or by reset.
13
14
reserved
R=0
R/W
0
0
reserved
HECCAENCLK
If this bit is set, it enables the system clock within the CAN peripheral. For
low power operation, this bit is set to zero by the user or by reset.
15
reserved
R=0
0
reserved
†
If a peripheral block is not used, then the clock to that peripheral can be turned off to minimize power consumption.
46
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system control (continued)
The system control and status register contains the watchdog override bit and the watchdog interrupt
enable/disable bit. Table 33 describes the bit functions of the SCSR register.
Table 33. SCSR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
0
WDOVERRIDE
R/W=1
1
If this bit is set to 1, the user is allowed to change the state of the Watchdog
disable (WDDIS) bit in the Watchdog Control (WDCR) register (refer to
Watchdog Block section of this data sheet). If the WDOVERRIDE bit is
cleared, by writing a 1 the WDDIS bit cannot be modified by the user.
Writing a 0 will have no effect. If this bit is cleared, then it will remain in this
stateuntilaresetoccurs. Thecurrentstateofthisbitisreadablebytheuser.
1
WDENINT
reserved
R/W
R=0
0
If this bit is set to 1, the watchdog reset (WDRST) output signal is disabled
and the watchdog interrupt (WDINT) output signal is enabled. If this bit is
zero, then the WDRST output signal is enabled and the WDINT output
signal is disabled. This is the default state on reset (XRS).
15:2
0:0
The HISPCP and LOSPCP registers are used to configure the high- and low-speed peripheral clocks,
respectively. See Table 34 for the HISPCP bit definitions and Table 35 for the LOSPCP bit definitions.
Table 34. HISPCP Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
2:0
HSPCLK
R/W
0,0,1
These bits configure the high-speed peripheral clock (HSPCLK) rate
relative to SYSCLKOUT:
000
001
010
011
100
101
110
111
HSPCLK = SYSCLKOUT / 1
HSPCLK = SYSCLKOUT / 2
HSPCLK = SYSCLKOUT / 4
HSPCLK = SYSCLKOUT / 6
HSPCLK = SYSCLKOUT / 8
HSPCLK = SYSCLKOUT / 10
HSPCLK = SYSCLKOUT / 12
HSPCLK = SYSCLKOUT / 14
HSPCLK = SYSCLKOUT / (HSPCLK x 2)
SYSCLKOUT if HISPCP value is zero
=
15:3
reserved
R=0
0:0
47
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system control (continued)
Table 35. LOSPCP Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
2:0
LSPCLK
R/W
0,1,0
These bits configure the low-speed peripheral clock (LSPCLK) rate
relative to SYSCLKOUT:
000
001
010
011
100
101
110
111
LSPCLK = SYSCLKOUT / 1
LSPCLK = SYSCLKOUT / 2
LSPCLK = SYSCLKOUT / 4
LSPCLK = SYSCLKOUT / 6
LSPCLK = SYSCLKOUT / 8
LSPCLK = SYSCLKOUT / 10
LSPCLK = SYSCLKOUT / 12
LSPCLK = SYSCLKOUT / 14
LSPCLK = SYSCLKOUT / (LSPCLK x 2)
SYSCLKOUT if LOSPCP value is zero
=
15:3
reserved
R=0
0:0
Note: The HSPCLK is set to SYSCLKOUT/2 and LSPCLK is set to SYSCLKOUT/4 on reset.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
OSC and PLL block
The OSC and PLL block on the F2810 and F2812 will use a zero-pin Phase-Locked Loop (ZPLL). Figure 10
shows the implemented features and relevant signals.
XPLLDIS
OSCCLK
XTAL1/CLKIN
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
4-bit
PLL
XTAL2
PLL Select
Figure 10. OSC and PLL Block
The OSC circuit enables a crystal to be attached to the F2810 and F2812 devices using the X1 and X2 pins.
If a crystal is not used, then an external oscillator can be directly connected to the XCLKIN pin and the X2 pin
is left unconnected. The oscillator input range is 20 MHz to 35 MHz.
Table 36. PLLCR Register Bit Definitions
†
BIT(S)
NAME
TYPE
XRS RESET
DESCRIPTION
3:0
DIV
R/W
0,0,0,0
ThesebitssetthePLLclockingratio. Therangeofvaluesshouldbebetween
(x 1.0) to (x 10.0). The scale between these values should be as linear as
possible:
0000
0001
x 0.5
x 1.0
PLL bypassed but enabled
CLKIN = OSCCLK / 2
PLL connected
CLKIN (OSCCLK * 1.0) / 2
CLKIN = (OSCCLK * 2.0) / 2
CLKIN = (OSCCLK * 3.0) / 2
CLKIN = (OSCCLK * 4.0) / 2
CLKIN = (OSCCLK * 5.0) / 2
CLKIN = (OSCCLK * 6.0) / 2
CLKIN = (OSCCLK * 7.0) / 2
CLKIN = (OSCCLK * 8.0) / 2
CLKIN = (OSCCLK * 9.0) / 2
CLKIN = (OSCCLK * 10.0) / 2
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
x 2.0
x 3.0
x 4.0
x 5.0
x 6.0
x 7.0
x 8.0
x 9.0
x 10.0
spare
spare
spare
spare
spare
15:4
reserved
R=0
0:0
†
The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is not changed.
49
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DIGITAL SIGNAL PROCESSORS
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PLL-based clock module
The F2810 and F2812 have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
to select different CPU clock rates.
The PLL-based clock module provides two modes of operation:
D
D
Crystal-operation
This mode allows the use of an external crystal/resonator to provide the time base to the device.
External clock source operation
This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external
clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the
XTAL1/CLKIN pin.
external reference oscillator clock option
TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with
the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor
can also advise the customer regarding the proper tank component values that will ensure start-up and stability
over the entire operating range.
50
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watchdog block
The watchdog block on the F2810 and F2812 is identical to the one used on the 240x devices. The watchdog
module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up
counter has reached its maximum value. To prevent this, the user disables the counter or the software must
periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter.
Figure 11 shows the various functional blocks within the watchdog module.
WDCR (WDPS(2:0))
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
WDKEY(7:0)
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
O.C.
WDRST
SCSR (WDENINT)
WDCR (WDCHK(2:0))
XPPLDIS
1
0
1
NOTE A: The WDRST signal is driven low for 512 OSCCLK cycles (similarly for the WDINT signal if enabled).
Figure 11. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The WDINT signal is
fed to the LPM block so that it can wake the device from STANDBY (if enabled). Refer to ”Low-Power Modes
Block” section of this data sheet for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE
mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
51
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DIGITAL SIGNAL PROCESSORS
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watchdog block (continued)
Table 37. WDCNTR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
7:0
WDCNTR
R/W
0:0
These bits contain the current value of the WD counter. The 8-bit
counter continually increments at the WDCLK rate. If the counter
overflows, then the watchdog initiates a reset. If the WDKEY register
is written with a valid combination, then the counter is reset to zero.
15:8
reserved
R=0
0:0
Table 38. WDKEY Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
7:0
WDKEY
W/R=0
0:0
Writing 0x55 followed by 0xAA will cause the WDCNTR bits to be
cleared. Writing any other value will cause an immediate watchdog
reset to be generated.
15:8
reserved
R=0
0:0
Table 39. WDCR Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
2:0
WDPS(2:0)
R/W
0:0
Thesebitsconfigurethewatchdogcounterclock(WDCLK)raterelative
to OSCCLK/512:
000
001
010
011
100
101
110
111
WDCLK = OSCCLK/512/1
WDCLK = OSCCLK/512/1
WDCLK = OSCCLK/512/2
WDCLK = OSCCLK/512/4
WDCLK = OSCCLK/512/8
WDCLK = OSCCLK/512/16
WDCLK = OSCCLK/512/32
WDCLK = OSCCLK/512/64
5:3
6
WDCHK(2:0)
WDDIS
W/R=0
R/W
0:0
0
The user must ALWAYS write “1,0,1” to these bits whenever a write to
this register is performed. Writing any other value will cause an
immediate reset to the core (if WD enabled).
Writing a 1 to this bit will disable the watchdog module. Writing a 0 will
enable the module. This bit can only be modified if the WDOVERRIDE
bit in the SCSR2 register is set to 1. On reset, the watchdog module is
enabled.
7
WDFLAG
reserved
R/W=1
R=0
Watchdog reset status flag bit. This bit, if set, indicates a watchdog
reset (WDRST) generated the reset condition. If 0, then it was an
external device or power-up reset condition. This bit remains latched
untilthe user writes a 1 to clear the condition. Writes of 0 will be ignored.
15:8
0:0
52
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
watchdog block (continued)
When the XRS line is low, the WDFLAG bit is forced low. The WDFLAG bit will only be set if a rising edge on
WDRST signal is detected (after synch and a 4 cycle delay) and the XRS signal is high. If the XRS signal is low
when WDRST goes high, then the WDFLAG bit will remain at 0. In a typical application, the WDRST signal will
connect to the XRS input. Hence to distinguish between a watchdog reset and an external device reset, an
external reset must be longer in duration then the watchdog pulse.
Emulation Considerations
The watchdog module behaves as follows under various debug conditions:
CPU Suspended:
When the CPU is suspended, the watchdog clock (WDCLK) is
suspended.
Run-Free Mode:
When the CPU is placed in run-free mode, then the watchdog module
resumes operation as normal.
Real-Time Single-Step Mode:
When the CPU is in real-time single-step mode, the watchdog clock
(WDCLK) is suspended. The watchdog remains suspended even within
real-time interrupts.
Real-Time Run-Free Mode:
When the CPU is in real-time run-free mode, the watchdog operates as
normal.
53
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
low-power modes block
The low-power modes on the F2810 and F2812 are similar to the 240x devices. Table 40 summarizes the
various modes.
Table 40. F2810 and F2812 Low-Power Modes
†
MODE
Normal
IDLE
IDLES
low
LPM(1:0)
X,X
OSCCLK
CLKIN
on
SYSCLKOUT
EXIT
on
on
on
–
‡
on
high
0,0
on
XRS,
WDINT,
Any Enabled Interrupt,
XNMI
STANDBY
high
0,1
on
off
off
XRS,
WDINT,
(watchdog still
running)
XINT1,
XNMI,
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
§
Debugger
HALT
high
1,X
off
off
off
XRS,
XNMI,
§
(oscillator and
PLL turned
Debugger
off, watchdog
not functional)
†
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will exit the
low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the IDLE mode will
not be exited and the device will go back into the indicated low power mode.
‡
§
The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is still
functional while on the 24x/240x the clock is turned off.
On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is, exited by any enabled interrupt or an NMI that is recognized
by the processor. The LPM block performs no tasks during this mode as
long as the LPMCR(LPM) bits are set to 0,0.
HALT Mode:
Only the XRS and XNMI external signals can wake the device from HALT
mode. The XNMI input to the core has an enable/disable bit. Hence, it is
safe to use the XNMI signal for this function.
STANDBY Mode:
All other signals (including XNMI) will wake the device from STANDBY
mode if selected by the LPMCR1 register. The user will need to select
which signal(s) will wake the device. The selected signal(s) are also
qualified by the OSCCLK before waking the device. The number of
OSCCLKs is specified in the LPMCR0 register.
54
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
low-power modes block (continued)
The low-power modes are controlled by the LPMCR0 register (see Table 41) and the LPMCR1 register (see
Table 42).
Table 41. LPMCR0 Register Bit Definitions
†
BIT(S)
1,0
NAME
TYPE
R/W
RESET
DESCRIPTION
‡
LPM
QUALSTDBY
0,0
These bits set the low power mode for the device.
7:2
R/W
1:1
Select number of OSCCLK clock cycles to qualify the selected inputs when
waking the LPM from STANDBY mode:
000000 = 2 OSCCLKs
000001 = 3 OSCCLKs
.
111111 = 65 OSCCLKs
15:8
reserved
R=0
0:0
†
‡
These bits are cleared by a reset (XRS).
The low power mode bits (LPM) are only valid when the IDLE instruction is executed. Therefore, the user must set the LPM bits to the appropriate
mode before executing the IDLE instruction.
Table 42. LPMCR1 Register Bit Definitions
†
BIT(S)
0
NAME
XINT1
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
DESCRIPTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
XNMI
2
WDINT
T1CTRIP
T2CTRIP
T3CTRIP
T4CTRIP
C1TRIP
C2TRIP
C3TRIP
C4TRIP
C5TRIP
C6TRIP
SCIRXA
SCIRXB
CANRX
3
4
5
6
7
If the respective bit is set to 1, it will enable the selected signal to wake the
device from STANDBY mode. If the bit is cleared, the signal will have no effect.
8
9
10
11
12
13
14
15
†
These bits are cleared by a reset (XRS).
55
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
PERIPHERALS
TheintegratedperipheralsoftheTMS320F2810andTMS320F2812aredescribedinthefollowingsubsections:
D
D
D
D
D
D
D
D
D
D
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Controller area network (CAN) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
PLL-based clock module
Digital I/O and shared pin functions
External memory interfaces (TMS320F2812 only)
Watchdog (WD) timer module
32-bit CPU-Timers 0/1/2
This section describes the three 32-bit CPU-timers on the F2810 and F2812 devices (TIMER0/1/2).
†
CPU-Timers 1 and 2 are reserved for the Real-Time OS (such as DSP-BIOS). CPU-Timer 0 can be used in
user applications.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
SYSCLKOUT
PSCH:PSC
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
NOTE A: The CPU-Timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA, EVB).
Figure 12. CPU-Timers
†
If the application is not using BIOS, then CPU-Timers 1 and 2 can be used in the application.
56
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
32-bit CPU-Timers 0/1/2 (continued)
In the F2810 and F2812 devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown
in Figure 13.
INT1
to
TINT0
PIE
CPU-TIMER 0
INT12
C28x
TINT1
CPU-TIMER 1
(for RTOS use)
INT13
INT14
XINT13
TINT2
CPU-TIMER 2
(for RTOS use)
NOTES: A. The timer registers are connected to the Memory Bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 13. CPU-Timer Interrupts Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register, decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed
in Table 43 are used to configure the timers.
Table 43. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
reserved
ADDRESS
SIZE (x16)
DESCRIPTION
CPU-Timer 0, Counter Register
0x0000–0C00
0x0000–0C01
0x0000–0C02
0x0000–0C03
0x0000–0C04
0x0000–0C05
0x0000–0C06
0x0000–0C07
0x0000–0C08
0x0000–0C09
0x0000–0C0A
0x0000–0C0B
0x0000–0C0C
0x0000–0C0D
0x0000–0C0E
0x0000–0C0F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
57
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32-bit CPU-Timers 0/1/2 (continued)
Table 43. CPU-Timers 0, 1, 2 Configuration and Control Registers (Continued)
NAME
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
reserved
ADDRESS
SIZE (x16)
DESCRIPTION
CPU-Timer 2, Counter Register
0x0000–0C10
0x0000–0C11
0x0000–0C12
0x0000–0C13
0x0000–0C14
0x0000–0C15
0x0000–0C16
0x0000–0C17
1
1
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
1
1
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
1
1
TIMER2TPR
TIMER2TPRH
reserved
1
CPU-Timer 2, Prescale Register
1
CPU-Timer 2, Prescale Register High
0x0000–0C18
0x0000–0C3F
40
†
Table 44. TIMERxTIM Register Bit Definitions
BITS
NAME
TIM
R/W
RESET
DESCRIPTION
15:0
R/W
0xFFFF Timer Counter Registers (TIMH:TIM): The TIM register holds the low 16 bits of the current 32-bit
count of the timer. The TIMH register holds the high 16 bits of the current 32-bit count of the timer.
The TIMH:TIM decrements by one every (TDDRH:TDDR+1) clock cycles, where TDDRH:TDDR
is the timer prescale divide-down value. When the TIMH:TIM decrements to zero, the TIMH:TIM
registeris reloaded with the period value contained in the PRDH:PRD registers. The timer interrupt
(TINT) signal is generated.
†
x = 0, 1, or 2
†
Table 45. TIMERxTIMH Register Bit Definitions
BITS
NAME
R/W
RESET
DESCRIPTION
15:0
TIMH
R/W
0x0000
See description for TIMERxTIM.
†
x = 0, 1, or 2
†
Table 46. TIMERxPRD Register Bit Definitions
BITS
NAME
PRD
R/W
RESET
DESCRIPTION
15:0
R/W
0xFFFF Timer Period Registers (PRDH:PRD): The PRD register holds the low 16 bits of the 32-bit period.
The PRDH register holds the high 16 bits of the 32-bit period. When the TIMH:TIM decrements to
zero, the TIMH:TIM register is reloaded with the period value contained in the PRDH:PRD
registers, at the start of the next timer input clock cycle (the output of the prescaler). The
PRDH:PRD contents are also loaded into the TIMH:TIM when you set the timer reload bit (TRB)
in the Timer Control Register (TCR).
†
x = 0, 1, or 2
†
Table 47. TIMERxPRDH Register Bit Definitions
BITS
NAME
PRDH
R/W
RESET
DESCRIPTION
15:0
R/W
0x0000
See description for TIMERxPRD
†
x = 0, 1, or 2
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DIGITAL SIGNAL PROCESSORS
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32-bit CPU-Timers 0/1/2 (continued)
†
Table 48. TIMERxTCR Register Bit Definitions
BIT
NAME
R/W
RESET
DESCRIPTION
15
TIF
R/W=1
0
Timer Interrupt Flag. This flag gets set when the timer decrements to zero. This bit can be
cleared by software writing a 1, but it can only be set by the timer reaching zero. Writing a 1
to this bit will clear it, writing a zero has no effect.
14
TIE
R/W
0
TimerInterruptEnable. Ifthetimerdecrementstozero, andthisbitisset, thetimerwillassert
its interrupt request.
13:12
11
Reserved
FREE
R
0
0
Reserved
R/W
Timer Emulation Modes: These bits are special emulation bits that determine the state of
the timer when a breakpoint is encountered in the high-level language debugger. If the
FREE bit is set to 1, then, upon a software breakpoint, the timer continues to run (that is,
free runs). In this case, SOFT is a don’t care. But if FREE is 0, then SOFT takes effect. In
this case, if SOFT = 0, the timer halts the next time the TIMH:TIM decrements. If the SOFT
bit is 1, then the timer halts when the TIMH:TIM has decremented to zero.
FREE SOFT Timer Emulation Mode
10
SOFT
R/W
0
0
0
1
1
0
1
0
1
Stop after the next decrement of the TIMH:TIM (hard stop)
Stop after the TIMH:TIM decrements to 0 (soft stop)
Free run
Free run
Note: That in the SOFT STOP mode, the timer will generate an interrupt before
shutting down (since reaching 0 is the interrupt causing condition).
9:6
5
Reserved
TRB
R/W
0
0
Reserved
W/R=0
Timer Reload bit. When you write a 1 to TRB, the TIMH:TIM is loaded with the value in the
PRDH:PRD, and the prescaler counter (PSCH:PSC) is loaded with the value in the timer
divide-down register (TDDRH:TDDR). The TRB bit is always read as zero.
4
TSS
R/W
R/W
0
0
Timer stop status bit. TSS is a 1-bit flag that stops or starts the timer. To stop the timer, set
TSS to 1. To start or restart the timer, set TSS to 0. At reset, TSS is cleared to 0 and the timer
immediately starts.
3:0
Reserved
Reserved
†
x = 0, 1, or 2
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32-bit CPU-Timers 0/1/2 (continued)
†
Table 49. TIMERxTPR Register Bit Definitions
BITS
NAME
R/W
RESET
DESCRIPTION
7:0
TDDR
R/W
0x00
Timer Divide-Down. Every (TDDRH:TDDR + 1) timer clock source cycles, the timer counter
register (TIMH:TIM) decrements by one. At reset, the TDDRH:TDDR bits are cleared to 0. To
increase the overall timer count by an integer factor, write this factor minus one to the
TDDRH:TDDR bits. When the prescaler counter (PSCH:PSC) value is 0, one timer clock source
cycle later, the contents of the TDDRH:TDDR reload the PSCH:PSC, and the TIMH:TIM
decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit
(TRB) is set by software.
15:8
PSC
R
0x00
Timer Prescale Counter. These bits hold the current prescale count for the timer. For every timer
clock source cycle that the PSCH:PSC value is greater than 0, the PSCH:PSC decrements by one.
One timer clock (output of the timer prescaler) cycle after the PSCH:PSC reaches 0, the
PSCH:PSC is loaded with the contents of the TDDRH:TDDR, and the timer counter register
(TIMH:TIM) decrements by one. The PSCH:PSC is also reloaded whenever the timer reload bit
(TRB) is set by software. The PSCH:PSC can be checked by reading the register, but it cannot be
set directly. It must get its value from the timer divide-down register (TDDRH:TDDR). At reset, the
PSCH:PSC is set to 0.
†
x = 0, 1, or 2
†
Table 50. TIMERxTPRH Register Bit Definitions
BIT
7:0
NAME
R/W
R/W
R
RESET
DESCRIPTION
TDDRH
PSCH
0x00
0x00
See description of TIMERxTPR.
See description of TIMERxTPR.
15:8
†
x = 0, 1, or 2
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DIGITAL SIGNAL PROCESSORS
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event manager modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and
quadrature-encoder pulse (QEP) circuits. EVA’s and EVB’s timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 51 shows the module and signal names
used. Table 51 shows the features and functionality available for the event-manager modules and highlights
EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting
at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ.
Table 51. Module and Signal Names for EVA and EVB
EVA
EVB
EVENT MANAGER MODULES
MODULE
SIGNAL
MODULE
SIGNAL
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
GP Timers
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Compare Units
Capture Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
QEP1
QEP2
QEPI1
QEP3
QEP4
QEPI2
QEP1
QEP2
QEP3
QEP4
QEP Channels
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
External Clock Inputs
External Compare Inputs
External Trip Inputs
C1TRIP
C2TRIP
C3TRIP
C4TRIP
C5TRIP
C6TRIP
Compare
†
†
T1CTRIP_PDPINTA
T2CTRIP/EVASOC
T3CTRIP_PDPINTB
T4CTRIP/EVBSOC
†
In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as PDPINTB.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
event manager modules (EVA, EVB) (continued)
†
Table 52. EV-A Registers
SIZE
(x16)
NAME
ADDRESS RANGE
DESCRIPTION
GPTCONA
T1CNT
T1CMPR
T1PR
0x0000–7400
0x0000–7401
0x0000–7402
0x0000–7403
0x0000–7404
0x0000–7405
0x0000–7406
0x0000–7407
0x0000–7408
0x0000–7409
0x0000–7411
0x0000–7413
0x0000–7415
0x0000–7417
0x0000–7418
0x0000–7419
0x0000–7420
0x0000–7422
0x0000–7423
0x0000–7424
0x0000–7425
0x0000–7427
0x0000–7428
0x0000–7429
0x0000–742C
0x0000–742D
0x0000–742E
0x0000–742F
0x0000–7430
0x0000–7431
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GP Timer Control Register A
GP Timer 1 Counter Register
GP Timer 1 Compare Register
GP Timer 1 Period Register
GP Timer 1 Control Register
GP Timer 2 Counter Register
GP Timer 2 Compare Register
GP Timer 2 Period Register
GP Timer 2 Control Register
GP Extension Control Register A
Compare Control Register A
Compare Action Control Register A
Dead-Band Timer Control Register A
Compare Register 1
T1CON
T2CNT
T2CMPR
T2PR
T2CON
‡
EXTCONA
COMCONA
ACTRA
DBTCONA
CMPR1
CMPR2
Compare Register 2
CMPR3
Compare Register 3
CAPCONA
CAPFIFOA
CAP1FIFO
CAP2FIFO
CAP3FIFO
CAP1FBOT
CAP2FBOT
CAP2FBOT
EVAIMRA
EVAIMRB
EVAIMRC
EVAIFRA
EVAIFRB
EVAIFRC
Capture Control Register A
Capture FIFO Status Register A
Two-Level Deep Capture FIFO Stack 1
Two-Level Deep Capture FIFO Stack 2
Two-Level Deep Capture FIFO Stack 3
Bottom Register Of Capture FIFO Stack 1
Bottom Register Of Capture FIFO Stack 2
Bottom Register Of Capture FIFO Stack 3
Interrupt Mask Register A
Interrupt Mask Register B
Interrupt Mask Register C
Interrupt Flag Register A
Interrupt Flag Register B
Interrupt Flag Register C
†
‡
The EV-B register set is identical except the address range is from 0x0000–7500 to 0x0000–753F. The above registers are mapped to Zone 2.
This space allows only 16-bit accesses. 32-bit accesses produce undefined results.
New register compared to 24x/240x
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
event manager modules (EVA, EVB) (continued)
EXTCONA is an added control register to enable and disable the added/modified features. It is required for
compatibility with 24x EV. EXTCONA enables and disables the additions and modifications in features. All
additions and modifications are disabled by default to keep compatibility with 24x EV (see Table 53).
Table 53. EXTCONA Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
0
INDCOE
R/W
0
Independent Compare Output Enable Mode: This bit, when set to one, allows
compare outputs to be enabled and disabled independently.
0
1
Independent Compare Output Enable mode is disabled. Time 1 and 2
compare outputs are enabled and disabled at the same time by
GPTCONA(6). FullCompare1, 2, and3outputsareenabledanddisabled
at the same time by COMCONA(9). GPTCONA(12,11,5,4) and
COMCONA(7:5, 2:0) are reserved. EVIFRA(0) enables and disables all
the compare outputs at the same time. EVIMR(0) enables and disables
PDP interrupt and the direct path of PDPINT signal at the same time.
IndependentCompareOutputEnablemodeisenabled. Compareoutputs
are enabled and disabled respectively by GPTCONA(5,4) and
COMCONA(7:5). Compare trips are enabled and disabled respectively
by GPTCONA(12,11) and COMCONA(2:0). GPTCONA(6) and
COMCONA(9) are reserved. EVIFRA[0] is set to one when any trip input
is low and is also enabled. EVIMRA(0) functions only as interrupt enable
and disable.
1
QEPIQUAL
R/W
0
QEP/CAP3 Index Qualification Mode: This bit turns on and off QEP index
qualifier.
0
QEPI/CAP3 qualification mode is off. QEPI/CAP3 is allowed to pass the
qualifier unaffected.
1
QEPI/CAP3 qualification mode is on. A zero-to-one transition is allowed
to pass the qualifier only when both QEPA and QEPB are high. Otherwise
the output of the qualifier stays low.
2
3
QEPIE
R/W
R/W
0
0
QEP Index Enable: This bit enables and disables the QEPI input. The QEPI input
when enabled can cause Timer 2 to reset:
0
1
Disable QEPI. Transitions on QEPI don’t affect Timer 2.
Enable QEPI. Either a zero-to-one transition on QEPI alone (when
EXTCONA[1] = 0), or a zero-to-one transition plus QEPA and QEPB are
both high (when EXTCONA[1] = 1), causes Timer 2 to reset to zero.
EVSOCE
EV Start-of-Conversion Output Enable. This bit enables and disables the EV ADC
start-of-conversion output. When enabled, a negative (active-low) pulse of
32 x HSPCLK is generated on selected EV ADC start-of-conversion event. This
bit does not affect the EVTOADC signal routed to the ADC module as optional
SOC trigger.
0
Disable EVSOC output. EVSOC is in Hi-Z state.
1
Enable EVSOC output.
15:4
reserved
R = 0
0:0
63
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DIGITAL SIGNAL PROCESSORS
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event manager modules (EVA, EVB) (continued)
GPTCONA(12:4), CAPCONA(8), EXTCONA[0]
EVAENCLK
EVTOADCA
Control Logic
PDPINTA/T1CTRIP, T2CTRIP/EVASOC, C1TRIP, C2TRIP, C3TRIP
Output
T1PWM_T1CMP
Logic
Timer 1 Compare
T1CON(5,4)
GPTCONA(1,0)
Prescaler
TCLKINA
HSPCLK
T1CON(1)
clock
dir
QEPCLK
QEPDIR
GP Timer 1
T1CON(10:8)
TDIRA
T1CON(15:11,6,3,2)
PWM1
PWM2
PWM3
Full Compare 1
Full Compare 2
Full Compare 3
SVPWM
State
Output
Logic
Dead-
Band
Logic
PWM4
PWM5
PWM6
Machine
DBTCONA(15:0)
ACTRA(15:12),
COMCONA(15:5,2:0)
COMCONA(12),
T1CON(13:11)
ACTRA(11:0)
Output
Logic
Timer 2 Compare
T2CON(1)
T2PWM_T2CMP
T2CON(5,4)
GPTCONA(3,2)
TCLKINA
HSPCLK
clock
dir
Prescaler
GP Timer 2
QEPCLK
QEPDIR
reset
T2CON(10:8)
T2CON(15:11,7,6,3,2,0)
QEP
Logic
CAPCONA(10,9)
TDIRA
CAP1_QEP1
CAP2_QEP2
Capture Units
CAP3_QEPI1
Index Qual
CAPCONA(15:12,7:0)
EXTCONA(1:2)
NOTE A: The EVB module is similar to the EVA module.
Figure 14. Event Manager A Functional Block Diagram
64
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DIGITAL SIGNAL PROCESSORS
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general-purpose (GP) timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
D
D
D
D
D
D
D
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register,TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
D
A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time
base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1
for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare
registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as
needed.
full-compare units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband
values can be programmed into the compare register for the outputs of the three compare units. The deadband
generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit
produces two outputs (with or without deadband zone) for each compare unit output signal. The output states
of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTRx
register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
65
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DIGITAL SIGNAL PROCESSORS
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PWM characteristics
Characteristics of the PWMs are as follows:
D
D
D
D
D
D
16-bit registers
Wide range of programmable deadband for the PWM output pairs
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
D
Minimized CPU overhead using auto-reload of the compare and period registers
D
ThePWMpinsaredriventoahigh-impedancestatewhenthePDPINTxpinisdrivenlowandafterPDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
–
–
PDPINTA pin status is reflected in bit 8 of COMCONA register.
PDPINTB pin status is reflected in bit 8 of COMCONB register.
capture unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
D
Capture units include the following features:
–
–
–
–
–
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All
inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input
must hold at its current level to meet two rising edges of the device clock. The input pins CAP1/2 and
CAP4/5 can also be used as QEP inputs to the QEP circuit.]
–
–
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
quadrature-encoder pulse (QEP) circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip.
Direction or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented
by the rising and falling edges of the two input signals (four times the frequency of either input pulse).
external ADC start-of-conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin (ESOCA/B) for external ADC interface.
EVASOC and EVBSOC are muxed with T2CTRIP and T4CTRIP, respectively.
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 15. The ADC module consists of
a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
D
D
D
12-bit ADC core with built-in S/H
Analog input: 0 V to 2.5 V
Fast conversion time:
–
–
Single conversion time: 200 ns
Pipelined conversion time: 60 ns
D
D
16-channel, muxed inputs
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
D
D
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Input Analog Voltage * ADCLO
Digital Value + 4095
2.5
D
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
–
–
S/W – software immediate start
EVA – Event manager A (multiple event sources within EVA)
EVB – Event manager B (multiple event sources within EVB)
D
D
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
D
D
D
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
Calibration mode
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced analog-to-digital converter (ADC) module (continued)
The ADC module in the F2810 and F2812 has been enhanced to provide flexible interface to event managers
A and B. The ADC interface is built around a fast, 12-bit ADC module with a total minimum conversion time of
200 ns (S/H + conversion) per conversion. The ADC module has 16 channels, configurable as two independent
8-channel modules to service event managers A and B. The two independent 8-channel modules can be
cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there
is only one converter in the ADC module. Figure 15 shows the block diagram of the F2810 and F2812 ADC
module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the
choice of selecting any one of the respective eight channels available through an analog mux. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the
conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing
allows the system to convert the same channel multiple times, allowing the user to perform oversampling
algorithms. This gives increased resolution over traditional single-sampled conversion results.
SYSCLKOUT
Low-Power
Modes Block
System
Control Block
High-Speed
Prescaler
C28x
HALT
ADCENCLK
HSPCLK
Analog
MUX
Result Registers
70A8h
Result Reg 0
Result Reg 1
ADCIN00
ADCIN07
ADCIN08
ADCIN15
S/H
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
EVA
ADCSOC
S/W
EVB
SOC
SOC
Sequencer 2
Sequencer 1
Figure 15. Block Diagram of the F2810 and F2812 ADC Module
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced analog-to-digital converter (ADC) module (continued)
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (such as V
digital supply.
, V
, and V
) from the
CCA REFHI
SSA
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK:On reset, this signal will be low. While reset isactive-low(XRS)theclocktotheregisterwillstill
function. This is necessary to make sure all registers and modes go into their default reset state. The analog
module will however be in a low-power inactive state. As soon as reset goes high, then the clock to the
registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers
will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before
the ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. Ifhigh, theADCmodulegoesintolow-powermode. TheHALTmodewillstoptheclocktotheCPU,
which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced analog-to-digital converter (ADC) module (continued)
The ADC operation is configured, controlled, and monitored by the registers listed in Table 54.
†
Table 54. ADC Registers
ADDRESS
RANGE
SIZE
(x16)
NAME
DESCRIPTION
ADCTRL1
ADCTRL2
0x0000–7100
0x0000–7101
0x0000–7102
0x0000–7103
0x0000–7104
0x0000–7105
0x0000–7106
0x0000–7107
0x0000–7108
0x0000–7109
0x0000–710A
0x0000–710B
0x0000–710C
0x0000–710D
0x0000–710E
0x0000–710F
0x0000–7110
0x0000–7111
0x0000–7112
0x0000–7113
0x0000–7114
0x0000–7115
0x0000–7116
0x0000–7117
0x0000–7118
0x0000–7119
0x0000–711A
0x0000–711B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
ADC Control Register 1
ADC Control Register 2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCCALOFF0
ADCCALOFF1
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto–Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Calibration Offset Result 0
ADC Calibration Offset Result 1
ADC Control Register 3
ADCST
ADC Status Register
reserved
0x0000–711C
0x0000–711F
†
The above registers are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced controller area network (eCAN) module
The CAN module has the following features:
D
D
D
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
–
–
–
–
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
D
D
D
D
D
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
D
Self-test mode
–
Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced controller area network (eCAN) module (continued)
Address
Controls
Data
HECC0INT
HECC1INT
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 16. eCAN Block Diagram and Interface Circuit
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced controller area network (eCAN) module (continued)
eCAN Control and Status Registers
Mailbox Enable – CANME
Mailbox Direction – CANMD
Transmission Request Set – CANTRS
Transmission Request Reset – CANTRR
Transmission Acknowledge – CANTA
Abort Acknowledge – CANAA
Receive Message Pending – CANRMP
Receive Message Lost – CANRML
Remote Frame Pending – CANRFP
Reserved
eCAN Memory (512 Bytes)
6000h
Control and Status Registers
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Master Control – CANMC
Message Object Time Stamps (MOTS)
Bit-Timing Configuration – CANBTC
Error and Status – CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter – CANTEC
Receive Error Counter – CANREC
Global Interrupt Flag 0 – CANGIF0
Global Interrupt Mask – CANGIM
Global Interrupt Flag 1 – CANGIF1
Mailbox Interrupt Mask – CANMIM
Mailbox Interrupt Level – CANMIL
Overwrite Protection Control – CANOPC
TX I/O Control – CANTIOC
(32 × 32-Bit RAM)
eCAN Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6100h–6107h
6108h–610Fh
6110h–6117h
6118h–611Fh
6120h–6127h
RX I/O Control – CANRIOC
Local Network Time – CANLNT
Time-Out Control – CANTOC
Time-Out Status – CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
61E0h–61E7h
61E8h–61EFh
61F0h–61F7h
61F8h–61FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier – MID
Message Control – MCF
Message Data Low – MDL
Message Data High – MDH
61E8h–61E9h
61EAh–61EBh
61ECh–61EDh
61EEh–61EFh
Figure 17. eCAN Memory Map
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
enhanced controller area network (eCAN) module (continued)
The CAN registers listed in Table 55 are used by the CPU to configure and control the CAN controller and the
message objects.
†
Table 55. CAN Registers Map
REGISTER NAME
CANME
ADDRESS
0x00 6000
0x00 6002
0x00 6004
0x00 6006
0x00 6008
0x00 600A
0x00 600C
0x00 600E
0x00 6010
0x00 6012
0x00 6014
0x00 6016
0x00 6018
0x00 601A
0x00 601C
0x00 601E
0x00 6020
0x00 6022
0x00 6024
0x00 6026
0x00 6028
0x00 602A
0x00 602C
0x00 602E
0x00 6030
0x00 6032
DESCRIPTION
Mailbox enable
CANMD
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
Reserved
CANMC
Receive message pending
Receive message lost
Remote frame pending
Reserved
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
CANOPC
CANTIOC
CANRIOC
CANLNT
CANTOC
CANTOS
RX I/O control
Local network time (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
†
These registers are mapped to Peripheral Frame 1. This space allows 16-bit and 32-bit accesses.
74
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
multichannel buffered serial port (McBSP) module
The McBSP module has the following features:
D
D
D
D
D
D
D
D
D
D
D
Compatible to McBSP in TMS320C54x /TMS320C55x DSP devices
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
HIghly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
D
D
D
Works with SPI-compatible devices at 75 Mbps maximum for 150-MHz SYSCLKOUT
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
D
D
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
–
–
–
–
–
–
MVIP framers
H.100 framers
SCSA framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
TMS320C54x and TMS320C55x are trademarks of Texas Instruments.
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
multichannel buffered serial port (McBSP) module (continued)
Figure 18 shows the block diagram of the McBSP module with FIFO, interfaced to the F2810 and F2812 version
of Peripheral Frame 2.
Peripheral Write Bus
TX FIFO
Interrupt
TX FIFO _15
—
TX FIFO _15
—
MXINT
TX Interrupt Logic
To CPU
TX FIFO _1
TX FIFO _0
TX FIFO _1
TX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
16
DXR1 Transmit Buffer
16
DXR2 Transmit Buffer
16
LSPCLK
FSX
McBSP Registers and
Control Logic
CLKX
Compand Logic
XSR2
XSR1
DX
DR
RSR1
16
RSR2
16
CLKR
Expand Logic
FSR
RBR2 Register
16
RBR1 Register
16
McBSP
DRR2 Receive Buffer
16
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO _15
—
RX FIFO _15
—
RX FIFO
Interrupt
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
MRINT
To CPU
RX FIFO Registers
Peripheral Read Bus
Figure 18. McBSP Module With FIFO
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
multichannel buffered serial port (McBSP) module (continued)
Table 56 provides a summary of the McBSP registers.
Table 56. McBSP Register Summary
ADDRESS
0x000 xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
†
DATA REGISTERS, RECEIVE, TRANSMIT
–
–
–
–
–
–
–
–
–
0x0000
0x0000
0x0000
McBSP Receive Buffer Register
McBSP Receive Shift Register
McBSP Transmit Shift Register
McBSP Data Receive Register 2
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
–
Read First if the word size is greater than 16 bits,
else ignore DRR2
McBSP Data Receive Register 1
–
Read Second if the word size is greater than 16 bits,
else read DRR1 only
McBSP Data Transmit Register 2
–
W
W
Write First if the word size is greater than 16 bits,
else ignore DXR2
McBSP Data Transmit Register 1
–
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2
SPCR1
RCR2
04
05
06
07
08
09
0A
0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
MULTICHANNEL CONTROL REGISTERS
MCR2
MCR1
0C
0D
0E
0F
10
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR1
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
12
13
14
15
16
RCERC
RCERD
XCERC
XCERD
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
†
‡
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
multichannel buffered serial port (McBSP) module (continued)
Table 56. McBSP Register Summary (Continued)
ADDRESS
0x000 xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED)
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
17
18
19
1A
1B
1C
1D
1E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
FIFO MODE REGISTERS (applicable only in FIFO mode)
‡
FIFO Data Registers
McBSP Data Receive Register 2 – Top of receive FIFO
Read First FIFO pointers will not advance
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
–
McBSP Data Receive Register 1 – Top of receive FIFO
Read Second for FIFO pointers to advance
0x0000
0x0000
0x0000
–
McBSP Data Transmit Register 2 – Top of transmit FIFO
Write First FIFO pointers will not advance
W
W
–
McBSP Data Transmit Register 1 – Top of transmit FIFO
–
Write Second for FIFO pointers to advance
FIFO Control Registers
0xA000
MFFTX
MFFRX
MFFCT
MFFINT
MFFST
20
21
22
23
24
R/W
R/W
R/W
R/W
R/W
McBSP Transmit FIFO Register
McBSP Receive FIFO Register
McBSP FIFO Control Register
McBSP FIFO Interrupt Register
McBSP FIFO Status Register
0x201F
0x0000
0x0000
0x0000
†
‡
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial communications interface (SCI) module
The F2810 and F2812 devices include two serial communications interface (SCI) modules. The SCI modules
support digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own
separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex
mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing
errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of the SCI module include:
D
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
D
D
Baud rate programmable to 64K different rates
Up to 9.3 Mbps at 150-MHz SYSCLKOUT
Data-word format
–
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
D
D
D
D
D
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and
TX EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
D
D
D
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register
data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
D
D
Auto baud-detect hardware logic
16-level transmit/receive FIFO
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial communications interface (SCI) module (continued)
The SCI port operation is configured and controlled by the registers listed in Table 57 and Table 58.
†
Table 57. SCI-A Registers
NAME
ADDRESS RANGE
0x0000–7050
0x0000–7051
0x0000–7052
0x0000–7053
0x0000–7054
0x0000–7055
0x0000–7056
0x0000–7057
0x0000–7059
0x0000–705A
0x0000–705B
0x0000–705C
0x0000–705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCICCR
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
SCIFFTX
SCIFFRX
SCIFFCT
SCIPRI
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
†
Shaded registers are new registers for the FIFO mode.
†
Table 58. SCI-B Registers
NAME
ADDRESS RANGE
0x0000–7750
0x0000–7751
0x0000–7752
0x0000–7753
0x0000–7754
0x0000–7755
0x0000–7756
0x0000–7757
0x0000–7759
0x0000–775A
0x0000–775B
0x0000–775C
0x0000–775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCICCR
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
SCIFFTX
SCIFFRX
SCIFFCT
SCIPRI
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
†
Shaded registers are new registers for the FIFO mode.
Note:
The above registers are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit
accesses produce undefined results.
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial communications interface (SCI) module (continued)
Figure 19 shows the SCI module block diagram.
SCICTL1.1
SCITXD
SCITXD
Frame Format and Mode
TXSHF
TXENA
Register
8
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
Transmitter–Data
Buffer Register
SCICTL2.7
SCICTL2.0
TXWAKE
SCICTL1.3
1
8
TXINT
TX FIFO _0
TX FIFO Interrupt
TX Interrupt
Logic
TX FIFO _1
–––––
SCITXBUF.7–0
To CPU
TX FIFO _15
SCI TX Interrupt select logic
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 – 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
SCIRXST.1
LSPCLK
SCILBAUD. 7 – 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7–0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
BRKDT
RX–FI–FO–_1–5 –
SCIRXST.5
RX FIFO_1
RX FIFO _0
RXINT
RX Interrupt
Logic
RX FIFO Interrupt
SCIRXBUF.7–0
To CPU
RX FIFO registers
RXFFOVF
SCIRXST.7 SCIRXST.4 – 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt select logic
SCICTL1.6
Figure 19. Serial Communications Interface (SCI) Module Block Diagram
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial peripheral interface (SPI) module
The F2810 and F2812 devices include the four-pin serial peripheral interface (SPI) module. The SPI is a
high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen
bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical
applicationsincludeexternalI/Oorperipheralexpansionthroughdevicessuchasshiftregisters, displaydrivers,
and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
D
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
D
D
D
D
Two operational modes: master and slave
Baud rate: 125 different programmable rates/37.5 Mbps at 150-MHz SYSCLKOUT
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
D
D
D
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register
data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
D
D
16-level transmit/receive FIFO
Delayed transmit control
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial peripheral interface (SPI) module (continued)
The SPI port operation is configured and controlled by the registers listed in Table 59.
Table 59. SPI Registers
NAME
SPICCR
SPICTL
ADDRESS RANGE
0x0000–7040
0x0000–7041
0x0000–7042
0x0000–7044
0x0000–7046
0x0000–7047
0x0000–7048
0x0000–7049
0x0000–704A
0x0000–704B
0x0000–704C
0x0000–704F
SIZE (x16)
DESCRIPTION
SPI Configuration Control Register
1
1
1
1
1
1
1
1
1
1
1
1
SPI Operation Control Register
SPI Status Register
SPIST
SPIBRR
SPIEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI Baud Rate Register
SPI Emulation Buffer Register
SPI Serial Input Buffer Register
SPI Serial Output Buffer Register
SPI Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI FIFO Transmit Register
SPI FIFO Receive Register
SPI FIFO Control Register
SPI Priority Control Register
Note:
The above registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit
accesses produce undefined results.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
serial peripheral interface (SPI) module (continued)
Figure 20 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPISTS.7
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
SPIINT
RX FIFO Interrupt
–––––
RX Interrupt
Logic
RX FIFO _15
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
SPITX
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
–––––
TX FIFO _1
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 – 0
S
Talk
SPICTL.1
*
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 – 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 – 0
M
6
5
4
3
2
1
0
Figure 20. Serial Peripheral Interface Module Block Diagram
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux
The GPIO Mux registers, are used to select the operation of shared pins on the F2810 and F2812 devices. The
pins can be individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the
GPxMUX registers). If selected for “Digital I/O” mode, registers are provided to configure the pin direction (via
the GPxDIR registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers).
Table 60 lists the GPIO Mux Registers.
†‡§
Table 60. GPIO Mux Registers
NAME
GPAMUX
GPADIR
GPAQUAL
reserved
GPBMUX
GPBDIR
GPBQUAL
reserved
reserved
reserved
reserved
reserved
GPDMUX
GPDDIR
GPDQUAL
reserved
GPEMUX
GPEDIR
GPEQUAL
reserved
GPFMUX
GPFDIR
reserved
reserved
GPGMUX
GPGDIR
reserved
reserved
reserved
ADDRESS
SIZE (x16)
REGISTER DESCRIPTION
GPIO A Mux Control Register
0x0000–70C0
0x0000–70C1
0x0000–70C2
0x0000–70C3
0x0000–70C4
0x0000–70C5
0x0000–70C6
0x0000–70C7
0x0000–70C8
0x0000–70C9
0x0000–70CA
0x0000–70CB
0x0000–70CC
0x0000–70CD
0x0000–70CE
0x0000–70CF
0x0000–70D0
0x0000–70D1
0x0000–70D2
0x0000–70D3
0x0000–70D4
0x0000–70D5
0x0000–70D6
0x0000–70D7
0x0000–70D8
0x0000–70D9
0x0000–70DA
0x0000–70DB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
GPIO A Direction Control Register
GPIO A Input Qualification Control Register
GPIO B Mux Control Register
GPIO B Direction Control Register
GPIO B Input Qualification Control Register
GPIO D Mux Control Register
GPIO D Direction Control Register
GPIO D Input Qualification Control Register
GPIO E Mux Control Register
GPIO E Direction Control Register
GPIO E Input Qualification Control Register
GPIO F Mux Control Register
GPIO F Direction Control Register
GPIO F Mux Control Register
GPIO F Direction Control Register
0x0000–70DC
0x0000–70DF
†
‡
§
Registers that are not implemented will return undefined values and writes will be ignored.
Not all inputs will support input signal qualification.
These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
If configured for ”Digital I/O” mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 61 lists the GPIO Data Registers.
†‡
Table 61. GPIO Data Registers
NAME
GPADAT
ADDRESS
SIZE (x16)
REGISTER DESCRIPTION
0x0000–70E0
0x0000–70E1
0x0000–70E2
0x0000–70E3
0x0000–70E4
0x0000–70E5
0x0000–70E6
0x0000–70E7
0x0000–70E8
0x0000–70E9
0x0000–70EA
0x0000–70EB
0x0000–70EC
0x0000–70ED
0x0000–70EE
0x0000–70EF
0x0000–70F0
0x0000–70F1
0x0000–70F2
0x0000–70F3
0x0000–70F4
0x0000–70F5
0x0000–70F6
0x0000–70F7
0x0000–70F8
0x0000–70F9
0x0000–70FA
0x0000–70FB
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
GPIO A Data Register
GPIO A Set Register
GPASET
GPACLEAR
GPATOGGLE
GPBDAT
GPIO A Clear Register
GPIO A Toggle Register
GPIO B Data Register
GPIO B Set Register
GPIO B Clear Register
GPIO B Toggle Register
GPBSET
GPBCLEAR
GPBTOGGLE
reserved
reserved
reserved
reserved
GPDDAT
GPIO D Data Register
GPIO D Set Register
GPIO D Clear Register
GPIO D Toggle Register
GPIO E Data Register
GPIO E Set Register
GPIO E Clear Register
GPIO E Toggle Register
GPIO F Data Register
GPIO F Set Register
GPIO F Clear Register
GPIO F Toggle Register
GPIO G Data Register
GPIO G Set Register
GPIO G Clear Register
GPIO G Toggle Register
GPDSET
GPDCLEAR
GPDTOGGLE
GPEDAT
GPESET
GPECLEAR
GPETOGGLE
GPFDAT
GPFSET
GPFCLEAR
GPFTOGGLE
GPGDAT
GPGSET
GPGCLEAR
GPGTOGGLE
reserved
0x0000–70FC
0x0000–70FF
†
‡
Reserved locations will return undefined values and writes will be ignored.
These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Figure 21 shows how the various register bits select the various modes of operation.
GPxDAT/SET/CLEAR/TOGGLE
Digital I/O
Peripheral I/O
Register Bit(s)
High-
Impedance
Control
GPxQUAL
Register
GPxMUX
Register Bit Register Bit
GPxDIR
0
1
0
1
MUX
MUX
QUALxCLK
HSPCLK (High-Speed Peripheral Clock)
Input
Qualification
Pre-Scale
High-Impedance
Enable (1)
Boundary Off
XRS
Internal (Pullup or Pulldown)
PIN
Figure 21. Modes of Operation
Notes:
1. Via the GPxDAT register, the state of any PIN can be read, regardless of the operating mode.
2. Some selected input signals are, qualified by the QUALxCLK, which is a prescaled version of the
high-speed peripheral clock (HSPCLK). The GPxQUAL register specifies the qualification sampling period.
The sampling window is 6 samples wide and the output is only changed when all samples are the same
(all 0’s or all 1’s) as shown in Figure 22. This feature removes unwanted spikes from the input signal.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Input
to Qual
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
Sampling Window
QUALPRD
Output
from Qual
Figure 22. I/P Qualifier Clock Cycles
Table 62. GPAMUX, GPADIR Register Bit Definitions
GPIO NAME
(BIT = 0)
INPUT
QUAL
GPAMUX BIT
PERIPHERAL NAME (BIT = 1)
GPADIR BIT
TYPE
RESET
EV-A Peripheral
0
1
PWM1 (O)
PWM2 (O)
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
GPIOA12
GPIOA13
GPIOA14
GPIOA15
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
2
PWM3 (O)
2
3
PWM4 (O)
3
4
PWM5 (O)
4
5
PWM6 (O)
5
6
T1PWM_T1CMP (0)
T2PWM_T2CMP (0)
CAP1_QEP1 (I)
CAP2_QEP2 (I)
CAP3_QEPI1 (I)
TDIRA (I)
6
7
7
8
8
9
9
10
11
12
13
14
15
10
11
12
13
14
15
TCLKINA (I)
C1TRIP (I)
C2TRIP (I)
C3TRIP (I)
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Table 63. GPAQUAL Register Bit Definitions
BIT
NAME
TYPE
RESET
DESCRIPTION
Specifies the qualification sampling period:
7:0
QUALPRD
R/W
0:0
0x00
0x01
0x02
.
no qualification (just SYNC to SYSCLKOUT)
QUALPRD = SYSCLKOUT/2
QUALPRD = SYSCLKOUT/4
0xFF QUALPRD = SYSCLKOUT/510
15:8
reserved
R=0
0:0
Notes:
1. GPADIR bit = 0, configures corresponding GPIO pin as an input. GPADIR bit = 1, configures corresponding
GPIO pin as an output.
2. The GPADAT, GPASET, GPACLEAR, GPATOGGLE registers have the same bit to I/O signal mapping as
the GPAMUX and GPADIR registers.
3. The GPADAT register is a R/W register. Reading the register will reflect the current state of the input I/O
signal (after qualification). Writing to the register will set the corresponding state of any I/O signal configured
as an output.
4. The GPASET register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an I/O
signal will cause the I/O signal to go high. Writing a 0 will have no effect.
5. The GPACLEAR register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an
I/O signal will cause the I/O signal to go low. Writing a 0 will have no effect.
6. The GPATOGGLE register is a write only register (reads back 0). Writing a 1 to the corresponding bit of an
I/O signal will cause the I/O signal to toggle. Writing a 0 will have no effect.
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Table 64. GPBMUX, GPBDIR Register Bit Definitions
GPBMUX
BIT
GPIO NAME
(BIT = 0)
GPBDIR
BIT
PERIPHERAL NAME (BIT = 1)
TYPE
RESET
INPUT QUAL
EV-B Peripheral
0
1
PWM7 (O)
PWM8 (O)
GPIOB0
GPIOB1
GPIOB2
GPIOB3
GPIOB4
GPIOB5
GPIOB6
GPIOB7
GPIOB8
GPIOB9
GPIOB10
GPIOB11
GPIOB12
GPIOB13
GPIOB14
GPIOB15
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
2
PWM9 (O)
2
3
PWM10 (O)
3
4
PWM11 (O)
4
5
PWM12 (O)
5
6
T3PWM_T3CMP (0)
T4PWM_T4CMP (0)
CAP4_QEP3 (I)
CAP5_QEP4 (I)
CAP6_QEPI2 (I)
TDIRB (I)
6
7
7
8
8
9
9
10
11
12
13
14
15
10
11
12
13
14
15
TCLKINB (I)
C4TRIP (I)
C5TRIP (I)
C6TRIP (I)
Table 65. GPBQUAL Register Bit Definitions
BIT
NAME
TYPE
RESET
DESCRIPTION
Specifies the qualification sampling period:
7:0
QUALPRD
R/W
0:0
0x00
0x01
0x02
.
no qualification (just SYNC to SYSCLKOUT)
QUALPRD = SYSCLKOUT/2
QUALPRD = SYSCLKOUT/4
0xFF QUALPRD = SYSCLKOUT/510
15:8
reserved
R=0
0:0
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DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Table 66. GPDMUX, GPDDIR Register Bit Definitions
GPDMUX
GPIO NAME
(BIT = 0)
PERIPHERAL NAME (BIT = 1)
GPDDIR BIT
TYPE
RESET
INPUT QUAL
BIT
EV-A Peripheral:
0
T1CTRIP_PDPINTA (I)
T2CTRIP (I)
reserved
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
0
1
2
3
4
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
yes
yes
–
1
2
3
reserved
–
4
reserved
–
EV-B Peripheral:
5
6
T3CTRIP_PDPINTB (I)
T4CTRIP (I)
reserved
GPIOD5
GPIOD6
GPIOD7
GPIOD8
GPIOD9
GPIOD10
GPIOD11
GPIOD12
GPIOD13
GPIOD14
GPIOD15
5
6
R/W
R/W
R=0
R=0
R=0
R/W
R/W
R=0
R=0
R=0
R=0
0
0
0
0
0
0
0
0
0
0
0
yes
yes
–
7
7
8
reserved
8
–
9
reserved
9
–
10
11
12
13
14
15
reserved
10
11
12
13
14
15
–
reserved
–
reserved
–
reserved
–
reserved
–
reserved
–
Table 67. GPDQUAL Register Bit Definitions
BIT
NAME
TYPE
RESET
DESCRIPTION
Specifies the qualification sampling period:
7:0
QUALPRD
R/W
0:0
0x00
0x01
0x02
.
no qualification (just SYNC to SYSCLKOUT)
QUALPRD = SYSCLKOUT/2
QUALPRD = SYSCLKOUT/4
0xFF QUALPRD = SYSCLKOUT/510
15:8
reserved
R=0
0:0
91
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Table 68. GPEMUX, GPEDIR Register Bit Definitions
GPIO NAME
(BIT = 0)
INPUT
QUAL
GPEMUX BIT
PERIPHERAL NAME (BIT = 1)
GPEDIR BIT
TYPE
RESET
Interrupts:
0
1
XINT1_XBIO (I)
XINT2_ADCSOC (I)
XNMI_XINT13 (I)
reserved
GPIOE0
GPIOE1
GPIOE2
GPIOE3
GPIOE4
GPIOE5
GPIOE6
GPIOE7
GPIOE8
GPIOE9
GPIOE10
GPIOE11
GPIOE12
GPIOE13
GPIOE14
GPIOE15
0
1
R/W
R/W
R/W
R/W
R/W
R=0
R=0
R=0
R=0
R=0
R=0
R=0
R=0
R=0
R=0
R=0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
yes
yes
yes
–
2
2
3
3
4
reserved
4
–
5
reserved
5
–
6
reserved
6
–
7
reserved
7
–
8
reserved
8
–
9
reserved
9
–
10
11
12
13
14
15
reserved
10
11
12
13
14
15
–
reserved
–
reserved
–
reserved
–
reserved
–
reserved
–
Table 69. GPEQUAL Register Bit Definitions
BIT
NAME
TYPE
RESET
DESCRIPTION
Specifies the qualification sampling period:
7:0
QUALPRD
R/W
0:0
0x00
0x01
0x02
.
no qualification (just SYNC to SYSCLKOUT)
QUALPRD = SYSCLKOUT/2
QUALPRD = SYSCLKOUT/4
0xFF QUALPRD = SYSCLKOUT/510
15:8
reserved
R=0
0:0
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Table 70. GPFMUX, GPFDIR Register Bit Defintions
GPIO NAME
(BIT = 0)
INPUT
QUAL
GPFMUX BIT
PERIPHERAL NAME (BIT = 1)
GPFDIR BIT
TYPE
RESET
SPI Peripheral:
0
SPISIMO (O)
SPISOMI (I)
SPICLK (I/O)
SPISTE (I/O)
GPIOF0
GPIOF1
GPIOF2
GPIOF3
0
1
2
3
R/W
R/W
R/W
R/W
0
0
0
0
no
no
no
no
1
2
3
SCIA Peripheral:
4
SCITXDA (O)
SCIRXDA (I)
GPIOF4
GPIOF5
4
5
R/W
R/W
0
0
no
no
5
CAN Peripheral:
6
CANTX (O)
CANRX (I)
GPIOF6
GPIOF7
6
7
R/W
R/W
0
0
no
no
7
McBSP Peripheral:
8
MCLKX (I/O)
MCLKR (I/O)
MFSX (I/O)
MFSR (I/O)
MDX (O)
GPIOF8
GPIOF9
8
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
no
no
no
no
no
no
9
9
10
11
12
13
GPIOF10
GPIOF11
GPIOF12
GPIOF13
10
11
12
13
MDR (I)
XINT I/O Space Strobe & XF CPU Output Signal:
14 XF (0)
GPIOF14
14
R/W
0
no
93
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
GPIO mux (continued)
Table 71. GPGMUX, GPGDIR Register Bit Definitions
GPGMUX
BIT
GPIO NAME
(BIT = 0)
INPUT
QUAL
PERIPHERAL NAME (BIT = 1)
GPGDIR BIT
TYPE
RESET
0
1
2
3
reserved
reserved
reserved
reserved
GPIOG0
GPIOG1
GPIOG2
GPIOG3
0
1
2
3
R/W
R/W
R/W
R/W
0
0
0
0
–
–
–
–
SCI-B Peripheral:
4
5
SCITXDB (O)
SCIRXDB (I)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
GPIOG4
GPIOG5
GPIOG6
GPIOG7
GPIOG8
GPIOG9
GPIOG10
GPIOG11
GPIOG12
GPIOG13
GPIOG14
GPIOG15
4
5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
no
no
–
6
6
7
7
–
8
8
–
9
9
–
10
11
12
13
14
15
10
11
12
13
14
15
–
–
–
–
–
–
94
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
development support
Texas Instruments (TI) offers an extensive line of development tools for the C28x generation of DSPs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of F2810- and F2812-based applications:
Software Development Tools:
Assembler/linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/C++/Assembly debugger and code profiler
Hardware Development Tools:
Emulator XDS510 /XDS510PP (supports x24x/28x multiprocessor system debug)
SPI515 (third-party tool)
XDS510PP (third-party tool)
The TMS320 DSP Development Support Reference Guide (literature number SPRU011) contains information
about development support products for all TMS320 DSP family member devices, including documentation.
Refer to this document for further information about TMS320 DSPdocumentationoranyotherTMS320 DSP
support products from Texas Instruments. There is also an additional document, the TMS320 Third-Party
Support Reference Guide (literature number SPRU052), which contains information from other companies in
the industry regarding products related to the TMS320 DSPs . To receive copies of TMS320 DSP literature,
contact the Literature Response Center at 800-477-8924.
Development tools for the 28x are as follows:
D
Code Composer Studio Integrated Development Environment (IDE) Version 2.0
–
–
Code Composer Studio Version 2.0 Debugger
Code Generation Tools
–
–
–
Assembler/Linker
C/C++ Compiler
Cycle Accurate Simulator
D
D
D
D
JTAG-Based Emulator
Sample Applications Code
Universal 5-V DC Power Supply
Documentation and Cables
XDS510, XDS510PP, TMS320, and Code Composer Studio are trademarks of Texas Instruments.
95
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
device and development support tool nomenclature
To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part
numbers of all TMS320 DSP devices and support tools. Each TMS320 DSP member has one of three
prefixes: TMX, TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This
development flow is defined below.
Support tool development evolutionary flow:
TMDX
TMDS
Development support product that has not completed TI’s internal qualification testing
Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development support tools have been fully characterized, and the quality and reliability
of the device have been fully demonstrated. TI’s standard warranty applies.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PBK) and temperature range (for example, A). Figure 23 provides a legend for reading the
complete device name for any TMS320x28x family member. Refer to the timing section for specific options that
are available on F2810 and F2812 devices.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
A
TMS 320
F
2810
PBK
PREFIX
TEMPERATURE RANGE
TMX = experimental device
TMP = prototype device
TMS = qualified device
A
S
=
=
–40°C to 85°C
–40°C to 125°C
†
PACKAGE TYPE
GHH = 179-pin MicroStar BGA
DEVICE FAMILY
320 = TMS320 DSP Family
PGF = 176-pin LQFP
PBK = 128-pin LQFP
DEVICE
2810
2812
TECHNOLOGY
F
= Flash EEPROM (1.8-V Core/3.3-V I/O)
†
BGA
=
Ball Grid Array
LQFP = Low-Profile Quad Flatpack
Figure 23. TMS320x28x Device Nomenclature
96
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
documentation support
Extensive documentation supports all of the TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; and hardware and software applications. Useful reference
documentation includes:
D
Application Reports
3.3V DSP for Digital Motor Control (literature number SPRA550)
–
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320
DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this TMS320F2810/TMS320F2812 data sheet (literature number SPRS174), use
the comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
97
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
†
absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted)
Supply voltage range, V , PLLV
, V
, and V
(see Note 1) . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
DD
CCA DDO
CCA
Supply voltage range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 2 V
DD
V
range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 3.6 V
CCP
Input voltage range, V
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
IN
O
O
Output voltage range,V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V
Input clamp current, I (V < 0 or V > V
Output clamp current, I
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK IN
IN
CC
CC
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
OK
O
O
A
Operating free-air temperature ranges, T : A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
S version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
J
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
†
Clamp current stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
‡§
recommended operating conditions
MIN
NOM
3.3
1.8
0
MAX
3.6
1.95
0
UNIT
V
V
/V
Supply voltage
V
DDO
= V
± 0.3 V
DD
3
DD DDO
CV
Device supply voltage, CPU/core
Supply ground
1.65
0
V
DD
V
SS
PLLV
V
PLL supply voltage
3
3.3
3.3
3.3
3.6
3.6
3.6
150
V
CCA
¶
V
V
ADC supply voltage
3
V
CCA
Flash programming supply voltage
3
V
CCP
f
Device clock frequency (system clock)
High-level input voltage
2
MHz
CLKOUT
V
V
All inputs
All inputs
2
V
V
IH
Low-level input voltage
0.8
– 2
2
IL
I
High-level output source current, V
= 2.4 V
mA
mA
°C
OH
OL
OH
= V
I
Low-level output sink current, V
MAX
OL
OL
A version
S version
– 40
– 40
– 40
85
T
Free-air temperature
Junction temperature
A
125
150
°C
T
J
25
TBD
1
°C
N
N
Flash endurance for the array (Write/erase cycles)
OTP endurance for the array (Write cycles)
– 40°C to 85°C
– 40°C to 85°C
cycles
cycles
f
OTP
‡
§
¶
Refer to the mechanical data package page for thermal resistance values, Θ (junction-to-ambient) and Θ (junction-to-case).
The drive strength of the EVA PWM pins and the EVB PWM pins are not identical.
JA
JC
V
CCA
should not exceed V by 0.3 V.
DD
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
electrical characteristics over recommended operating free-air temperature ranges (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 3.0 V, I = I MAX
2.4
DD
OH OH
All outputs at 50 µA
= I MAX
V
V
High-level output voltage
V
OH
V
– 0.2
DDO
Low-level output voltage
Input current (low level)
I
0.4
V
OL
OL OL
With pullup
–16
I
IL
V
= 3.3 V, V = 0 V
IN
µA
DD
DD
With pulldown
With pullup
±2
±2
I
I
Input current (high level)
V
V
= 3.3 V, V = V
IN
µA
IH
DD
With pulldown
16
Output current, high-impedance state (off-state)
Input capacitance
= V or 0 V
DD
±2
µA
pF
pF
OZ
O
C
C
2
3
i
Output capacitance
o
99
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
MECHANICAL DATA
GHH (S-PBGA-N179)
PLASTIC BALL GRID ARRAY
12,10
SQ
10,40 TYP
11,90
0,80
0,40
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,12
M
0,08
0,45
0,35
0,45
0,08
4173504-3/B 02/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments.
100
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
MECHANICAL DATA
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
133
88
0,27
0,17
M
0,08
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
25,80
0,25
0,05 MIN
0°–ā7°
SQ
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
101
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B – APRIL 2001 – REVISED SEPTEMBER 2001
MECHANICAL DATA
PBK (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,40
96
M
0,07
64
0,13
65
97
128
33
0,13 NOM
1
32
Gage Plane
12,40 TYP
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–ā7°
15,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040279-3/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
102
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
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TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’sstandardwarranty. TestingandotherqualitycontroltechniquesareutilizedtotheextentTIdeemsnecessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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