TMP392A2DRLR [TI]
TMP392 双通道（过热和温热）、电阻器可编程温度开关 | DRL | 6 | -55 to 130;
| 型号： | TMP392A2DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMP392 双通道（过热和温热）、电阻器可编程温度开关 | DRL | 6 | -55 to 130 开关 电阻器 |
| 文件： | 总25页 (文件大小：855K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMP392
ZHCSKH3 –NOVEMBER 2019
TMP392 超小型、双通道（高低温跳变）、0.5µA 电阻器可编程温度开关
1 特性
3 说明
1
•
电阻器可编程的温度跳闸点和迟滞选项
TMP392 器件属于超低功耗、双通道、电阻器可编程
温度开关系列，可在 30°C 至 130°C 范围内对系统过
热事件进行保护和检测。TMP392 可提供双路过热
–
–
电阻器容差可实现零误差
迟滞选项：5°C、10°C 和 20°C
（热、温）检测。跳闸温度 (TTRIP) 和热迟滞 (THYST
)
•
适用于过热检测的双路输出
选项可由两个位于 SETA 和 SETB 引脚上的 E96 系列
电阻器（1% 容差）进行编程。通道 A 电阻器的阻值
范围为 1.05KΩ 至 909KΩ，具有 48 个不同阻值。通
道 B 电阻器的阻值范围为 10.5KΩ 至 909KΩ
–
通道 A（过热 - 热）：+30 至 +124°C，阶跃为
2°C
–
通道 B（过热 - 温）：+30 至 +105°C，阶跃为
5°C
•
精度级别选项（在 +30°C 至 +130°C 范围内达到最
大值）：
SETA 输入的接地电阻器值可设置通道 A 的 TTRIP 阈
值。SETB 输入的接地电阻器值可设置通道 B 的 TTRIP
阈值，两个通道的 THYST 选项可设置为 5°C 或 10°C，
以防止发生不需要的数字输出切换。当 SETB 输入接
地，通道 A 运行时具有 20°C 的迟滞。电阻器精度对
–
–
A2 级：±3.0°C（在 +30°C 至 +70°C 范围内为
±1.5°C）
A3 级：±3.5°C（在 +30°C 至 +70°C 范围内为
±2.0°C）
T
TRIP 精度没有影响。
•
•
•
•
•
超低功耗：25°C 时为 0.5µA（典型值）
电源电压：1.62 至 5.5V
开漏输出
为使客户能够进行电路板级制造， TMP392 可通过发
挥 SETA 或 SETB 引脚功能激活数字输出，从而支持
跳闸测试功能。
跳闸测试功能支持系统内测试
采用 SOT-563 (1.60mm × 1.20mm)、
6 引脚封装
器件信息(1)
器件型号
TMP392
封装
封装尺寸（标称值）
2 应用
SOT-563 (6)
1.60mm × 1.20mm
•
•
•
•
•
•
•
•
•
•
•
直流/交流逆变器
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
直流/直流转换器
温度变送器
器件比较
环境控制系统 (ECS)
电动工具
器件型号
TMP390
TMP392
功能
输出类型
热/冷
热/温
开漏
移动电源
照明控制
简化原理图
工业机器人
RSETA and RSETB select trip
thresholds and hysteresis options.
机器视觉
VDD or VDDIO
STB 和 DVR
WLAN/Wi-Fi 接入点
VDD
R
P
RP
SETA
OUTA
OUTB
Optional Trip
Test
TMP39x
SETB
RSETA
RSETB
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNIS216
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Applications Information.......................................... 11
8.2 Typical Applications ................................................ 11
Power Supply Recommendations...................... 17
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 7
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 18
11 器件和文档支持 ..................................................... 19
11.1 接收文档更新通知 ................................................. 19
11.2 支持资源................................................................ 19
11.3 商标....................................................................... 19
11.4 静电放电警告......................................................... 19
11.5 Glossary................................................................ 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2019 年 11 月
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
5 Pin Configuration and Functions
DRL Package
6-Pin SOT-563
Top View
SETA
SETB
GND
1
2
3
6
5
4
OUTA
VDD
OUTB
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Channel A temperature set point. Connect a standard E96, 1% resistance between SETA
and GND.
1
SETA
Input
Channel B temperature and Hysteresis set point. Connect a standard E96, 1% resistance
between SETB and GND.
2
3
4
5
6
SETB
GND
Input
Ground
Device ground.
Channel B logic open-drain active low output. If unused, the output can be left floating or
connected to GND.
OUTB
VDD
Logic Output
Supply
Power supply voltage (1.62 V – 5.5 V).
Channel A logic open-drain active low output. If unused, the output can be left floating or
connected to GND.
OUTA
Logic Output
Copyright © 2019, Texas Instruments Incorporated
3
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
-0.3
–0.3
–55
–60
MAX
UNIT
V
Supply voltage
VDD
6
6
Voltage at
OUTA, OUTB
SETA, SETB
V
Voltage at
VDD + 0.3
150
V
Junction temperature, TJ
Storage temperature, Tstg
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Powering the device when the operating junction temperature is outside the Recommended Operating Conditions, may affect the
functional operation of the device. The device must be power cycled after the system has returned to conditions as indicated under
Recommended Operating Conditions.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
NOM
MAX
5.5
UNIT
V
VDD
VOUTA
VOUTB
ISETA
ISETB
RPA
Supply voltage
1.62
3.3
Channel A output pull-up voltage (open-drain)
Channel B output pull-up voltage (open-drain)
SETA pin circuit leakage current
VDD + 0.3
VDD + 0.3
20
V
V
-20
-20
nA
nA
SETB pin circuit leakage current
20
Pullup resistor connected from OUTA to VDDIO(1)
Pullup resistor connected from OUTB to VDDIO(1)
Operating free-air temperature (specified performance)
1
10
kΩ
RPB
TA
–55
130
°C
(1) Where VDDIO is an independent power supply other than VDD, and shall not exceed (VDD + 0.3) V.
6.4 Thermal Information
TMP392
THERMAL METRIC(1)
DRL (SOT)
6 PINS
230
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
103.4
111.6
5.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
110.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor IC Package Thermal Metrics application report,
(SPRA953).
4
Copyright © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
6.5 Electrical Characteristics
Minimum and maximum specifications are over -55°C to 130°C and VDD = 1.62V - 5.5V (unless otherwise noted); typical
specifications are at TA = 25°C and VDD = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEMPERATURE TO DIGITAL CONVERTER
TEMPERATURE MEASUREMENT
30°C to 70°C, VDD = 2.5V
to 5.5V(1)
-1.5
-2.0
-2.5
-3.0
±0.5
±0.5
±0.5
1.5
2.0
2.5
3.0
30°C to 70°C, VDD =
1.62V to 2.5V(1)
TMP392A2
°C
30°C to 130°C, VDD =
2.5V to 5.5V(1)
Trip Point Accuracy
30°C to 130°C, VDD =
1.62V to 2.5V(1)
30°C to 70°C(1)
30°C to 130°C(1)
±0.5
±0.5
-2.0
-3.5
2.0
3.5
°C
°C
°C
°C
TMP392A3
表 2 selection column 2
表 2 selection column 3
5
10
THYST
Trip point hysteresis
Channel A only when SETB connected
to GND
20
°C
TRIP POINT RESISTOR PROGRAMMING
SETA resistor range
1.05
10.5
-1.0
909
909
1.0
kΩ
kΩ
%
SETB resistor range
SETA & SETB resistor tolerance
TA=25°C
SETA & SETB resistor
-100
-0.2
100 ppm/°C
temperature coefficient(2)
SETA & SETB resistor lifetime
drift(2)
0.2
50
%
DIGITAL INPUT/OUTPUT
Input capacitance for SETA &
SETB (includes PCB)
CIN
pF
RPD
VOL
Internal Pull down resistance
Output logic low level
SETA & SETB
IOL = -3 mA
125
kΩ
0
0.4
0.1
V
Leakage current on output high
level
ILKG
-0.1
µA
TCov
TS
Conversion duration
Sampling period
0.65
0.5
ms
s
POWER SUPPLY
IQ
Average Quiescent current
VDD = 1.62V to 3.3V
0.5
0.25
135
250
1.5
1
μA
IStandby
IConv
ISU
Standby current
Conversion current
μA
μA
V
Startup (Reset) peak current
Power-on-reset threshold voltage
Brownout detect
Reset Time interval only.
Supply going up
VPOR
Supply going down
1.1
V
Time required by device to reset after
power up
Power Reset Time
10
ms
(1) Trip point accuracy test conditions is from 30°C to 130°C, since for the TMP392 the trip points for both channels is from 30°C to 124°C
(2) Recommended Value
版权 © 2019, Texas Instruments Incorporated
5
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
6.6 Typical Characteristics
1.4
3
2.5
2
1.62 V
3.3 V
1.2
4.4 V
5.5 V
1
1.5
1
0.8
0.6
0.4
0.2
0
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
D002
30
40
50
60
70
80
90
100 110 120
Temperature (èC)
(VS = 1.62 V, 3.3 V, 4.4 V, 5.5 V)
D006
(VS = 3.3 V)
图 1. Average Supply Current vs Operating Temperature
图 2. Hot Trip Point Accuracy vs Operating Temperature
3
2.5
2
6
-55èC
5
25èC
4
130èC
1.5
1
3
2
1
0.5
0
0
-1
-2
-3
-4
-5
-6
-0.5
-1
-1.5
-2
-2.5
-3
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
30
40
50
60
70
80
90
100
D001
Temperature (èC)
D002
(VS = 3.3 V)
图 4. Sampling Period Variation vs Supply Voltage
图 3. Warm Trip Point Accuracy vs Operating Temperature
200
190
180
170
160
150
140
130
120
110
100
200
1.62 V
2.2 V
3.3 V
5.5 V
180
160
140
120
100
80
60
40
20
0
1.5
2
2.5
3
3.5
Supply Voltage (V)
4
4.5
5
5.5
6
0
1
2
3
4
Load Current (mA)
5
6
7
8
9
10
D005
D004
(TAMB = 25°C)
图 5. Conversion Current vs Supply Voltage
图 6. Output Voltage vs Load Current
6
版权 © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
7 Detailed Description
7.1 Overview
The TMP392 ultra-low power, dual channel, resistor programmable temperature switches enable detection and
protection of system thermal events over a wide temperature range. The TMP392 offers dual overtemperature
(hot and warm) detection. Channel A is referred to as the hot channel, and Channel B is referred to as the warm
channel. The trip temperatures and hysteresis options are programmed by two E96-series (1%) standard decade
value resistors on the SETA and SETB pins. The TMP392 can enable a customer board-level manufacturing test
through the trip test function that can force the SETA or SETB pins to logic high to activates the digital outputs.
7.2 Functional Block Diagram
RSETA and RSETB select trip
thresholds and hysteresis options.
VDD
VDD or VDDIO
RP
RP
SETA
SETB
OUTA
OUTB
C
TMP39x
R
SETA
R
SETB
图 7. Simplified Schematic
7.3 Feature Description
The TMP392 requires two resistors to set the two trip points and hysteresis, according to 表 1 and 表 2 for the
hot and warm channel device. The output of the TMP392 is open-drain and requires two pullup resistors. TI
recommends to use a pullup voltage supply that does not exceed VDD + 0.3 V. The pullup resistors used in
between the OUTA and OUTB pins and the pullup supply should be greater than 1 kΩ. The device powers on
when the supply voltage goes beyond 1.5 V, and starts sampling the input resistors to set the two trip points and
hysteresis value after power-on. These values will remain the same until the device goes through a power cycle.
After the device sets the trip points and hysteresis level, the device will update the output every half a second.
The conversion time is typically 0.65 ms when the temperature is checked against the trip points and the outputs
are updated. The device remains in standby mode between conversions. If either channel is not used, the output
can be grounded or left floating.
7.3.1 TMP392 Programming Tables
The temperature threshold and hysteresis options for the TMP392 device are programmed using two external
1% E96 standard resistors. The specific resistor value to ground on the SETA input sets the temperature
threshold of channel A. The specific resistor value to ground on the SETB input sets the temperature threshold of
channel B, as well as the hysteresis for both channel A and channel B.
表 1. TMP392 Channel A Threshold Setting
CHANNEL A (HOT)
TRIP TEMPERATURE
(°C)
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 5°C
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 10°C
CHANNEL A NOMINAL 1%
RESISTORS (KΩ)
30
32
1.05
1.21
25
27
20
22
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7
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
Feature Description (接下页)
表 1. TMP392 Channel A Threshold Setting (接下页)
CHANNEL A (HOT)
TRIP TEMPERATURE
(°C)
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 5°C
CHANNEL A (HOT) TRIP RESET
CHANNEL A NOMINAL 1%
TEMPERATURE (°C) FOR
HYSTERESIS = 10°C
RESISTORS (KΩ)
34
36
1.40
1.62
1.87
2.15
2.49
2.87
3.32
3.83
4.42
5.11
5.90
6.81
7.87
9.09
10.5
12.1
14.0
16.2
18.7
21.5
24.9
28.7
33.2
38.3
44.2
51.1
59.0
68.1
78.7
90.9
105
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
121
98
140
100
102
104
106
108
110
112
114
116
118
120
162
187
215
249
287
332
383
442
511
590
681
8
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TMP392
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ZHCSKH3 –NOVEMBER 2019
Feature Description (接下页)
表 1. TMP392 Channel A Threshold Setting (接下页)
CHANNEL A (HOT)
TRIP TEMPERATURE
(°C)
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 5°C
CHANNEL A (HOT) TRIP RESET
TEMPERATURE (°C) FOR
HYSTERESIS = 10°C
CHANNEL A NOMINAL 1%
RESISTORS (KΩ)
122
124
787
909
117
119
112
114
注
When the SETA pin is grounded or left floating during the device power up, the OUTA pin
always stays low. The Channel B functionality is not affected by the SETA channel.
表 2. TMP392 Channel B Threshold and Hysteresis Setting
CHANNEL B
(WARM) TRIP
TEMPERATURE (°C)
CHANNEL B NOMINAL 1% RESISTORS (KΩ)
CHANNEL B (WARM) TRIP RESET TEMPERATURE (°C)
HYSTERESIS = 5°C
HYSTERESIS = 10°C
HYSTERESIS = 5°C
HYSTERESIS = 10°C
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
90.9
78.7
68.1
59.0
51.1
44.2
38.3
33.2
28.7
24.9
21.5
18.7
16.2
14.0
12.1
10.5
105
121
140
162
187
215
249
287
332
383
442
511
590
681
787
909
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
注
When the SETB pin is grounded or left floating during the POR, the OUTB pin always
stays low and the Channel A hysteresis is set to 20°C.
7.3.2 Trip Test
The purpose of the trip test is in system manufacturing test without putting the TMP392 through costly
temperature verification of the assembly of TMP392 and pullup resistors. When the SETA or SETB pin is set to a
high logic level, the associated output goes low. When the input pin level goes low, the output goes to its
previous condition before the trip test. The trip test does not affect the current condition of the device. The trip
test signals should stay above 0.8 × VDD for logic high and below 0.2 × VDD for logic low.
The trip test operation is shown in 图 8. The trip test must be performed with a single toggle when the device is
operating at a temperature that will not cause the corresponding output to trip. The trip test is intended for
production testing after assembly, and must not be used as a functional feature.
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9
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
(Channel A)
Hot threshold
Hysteresis:
5°C, or 10°C
(Channel B)
Warm threshold
Time (s)
OUTA
OUTB
Trip test
asserts output
SETA
SETB
Time (s)
图 8. TMP392 Trip Test Operation
7.3.3 20°C Hysteresis
The 20°C hysteresis feature is only available on Channel A. To activate the feature, the SETB pin must be
connected to ground and SETA pin connected to the resistor to set the appropriate trip point on Channel A.
7.4 Device Functional Modes
The device has one mode of operation, as described above, that applies when operated within the
Recommended Operating Conditions.
10
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TMP392
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ZHCSKH3 –NOVEMBER 2019
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Applications Information
The TMP392 device is part of a family of ultra-low power, dual channel, resistor programmable temperature
switches that can enable detection and protection of system thermal events over a wide temperature range. The
trip temperatures (TTRIP) and hysteresis options are programmed by two E96-series (1%) standard decade value
resistors on the SETA and SETB pins. The thermal hysteresis (THYST) function is to prevent undesired digital
output switching due to small temperature changes.
8.2 Typical Applications
8.2.1 Simplified Application Schematic
Figure 9 shows the simplified schematic where RSETA and RSETB are used to set channel A trip point (SETA) and
channel B trip point and hysteresis for both channels (SETB). SETA and SETB can be programmed at a variety
of temperatures based on the device, as described in 表 1 for channel A trip point, and 表 2 for channel B trip
point and hysteresis for both channels. OUTA and OUTB outputs correspond to the temperature threshold
detection at SETA and SETB, respectively.
RSETA and RSETB select trip
thresholds and hysteresis options.
VDD or VDDIO
VDD
RP
RP
SETA
SETB
OUTA
OUTB
Optional Trip
Test
TMP39x
RSETA
RSETB
Figure 9. Simplified Schematic
8.2.1.1 Design Requirements
The TMP392 requires two resistors to set the high and low trip points and hysteresis, and two pullup resistors for
the open-drain device. TI also highly recommends to place a 0.1-µF, power-supply bypassing capacitor close to
the VDD supply pin. To minimize the internal power dissipation, use two pullup resistors greater than 1 kΩ from
the OUTA and OUTB pins to the VDD pin. A separate supply, VDDIO, may be used for the pullup voltage to set
the output voltage level to the level required by the MCU, as shown in Figure 9. The open-drain output gives
flexibility of pulling up to any voltage independent of VDD (VDDIO must be less than or equal to VDD + 0.3 V).
This allows for use of longer cables or different power supply options. If a separate voltage level is not required,
TI recommends to tie the pullup to the TMP392 VDD.
If the SETA or SETB connected resistor value is outside the legal range, the associated output goes to
permanent output zero stage and the channel cannot be used. The other channel still will be in operating
condition, and device can be used in one channel mode. If the SETB input is grounded or left floating, the
Channel B cannot be used and the hysteresis for Channel A will be 20°C. The SETA and SETB connected
resistors are measured during POR. If two consecutive measurements are not matching each other, then the
device sets the associated channel output to zero and repeats the resistor measurements until the
measurements match. When the measurements match, the channel output is released. Note that it is possible to
connect some device outputs together by shorting the OUTA or OUTB line.
Copyright © 2019, Texas Instruments Incorporated
11
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
The resistor to ground values on the SETA input sets the TTRIP threshold of Channel A. The resistor to ground
value on the SETB input sets the TTRIP threshold of Channel B—as well as the THYST 5°C and 10°C options. TI
recommends that the resistors at SETA and SETB have a 1% tolerance at room temperature. Each resistor can
range from 1.05 KΩ to 909 KΩ, representing one of 48 unique values. The exact temperature thresholds and trip
points are shown in 表 1 and 表 2. The pullup resistors should be at least 1 kΩ to minimize internal power
dissipation. To get the correct threshold for resistor values, take care to minimize the board level capacitance
and leakage at the SETA and SETB pins.
The waveform for the TMP392 output for hot/warm thresholds is shown in Figure 10. The hysteresis can be set
to 5°C, 10°C, or 20°C. When the temperature exceeds the hot trip point threshold, OUTA goes low until the
temperature drops below the hysteresis threshold. When the temperature exceeds the warm trip threshold,
OUTB goes low and returns high after the temperature drops below the hysteresis threshold. If the switch has
already tripped and the temperature is in the hysteresis band, a POR event will cause the output to go high after
the power is restored.
8.2.1.3 Application Curves
(Channel A)
Hot threshold
(Channel B)
Warm threshold
Time (s)
OUTA
OUTB
Time (s)
Figure 10. TMP392 Output With Hot/Warm Thresholds and Hysteresis
12
Copyright © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
Typical Applications (continued)
8.2.2 TMP392 With 10°C Hysteresis
Figure 11 shows an example circuit for dual overtemperature protection using the TMP392. In this example, the
trip points are set at +60°C and +90°C with 10°C hysteresis. This circuit is useful in cases where a lower
overtemperature detection may be used to warn the application of rising system temperature and take software
corrective actions such as lowering the performance, while the higher overtemperature detection may be used to
start a fan to cool the system to a lower temperature.
VDD = 3.0 V
0.1 µF
3.3 V
10 kΩ
VDD
TMP392
GND
VCC
Microprocessor
GND
OUTA
OUTB
SETA
SETB
78.7 kΩ
Channel A Trip Temp = +90°C
and Hysteresis = 10°C
10 kΩ
249 kΩ
Channel B Trip Temp = 60°C
and Hysteresis = 10°C
Figure 11. TMP392 Example Circuit at +90°C and +60°C Thresholds With 10°C Hysteresis
8.2.2.1 Design Requirements
In this example, VDD can be ≥ 3 V. The output pins may be tied to a switch to control a fan or other analog
circuitry. Figure 11 uses 10-kΩ pullup resistors at the OUTA and OUTB outputs. Place a 0.1-µF bypass capacitor
close to the TMP392 device to reduce noise coupled from the power supply. If needed, the output of multiple
parts can be connected together.
8.2.2.2 Detailed Design Procedure
SETA sets the +90°C threshold using 78.7 kΩ. SETB sets the +60°C trip point and 10°C hysteresis using 249
kΩ. These values were determined using 表 1 and 表 2. These resistors should have maximum of 1% tolerance
at room temperature and 100 ppm/°C or less over the desired temperature range. A summary of the resistor
settings used in this example is shown in Table 3. See 表 1 and 表 2 for additional trip points and hysteresis
configurations.
The switching output of the TMP392 can be visualized with the output diagram shown in Figure 12. It is key to
notice that hysteresis is subtracted from both Channel A and Channel B threshold values. OUTA remains high
until the sensor reaches +90°C where the output goes low, and returns high after the temperature drops back
down to +80°C. OUTB remains high until the sensor reaches +60°C where the output goes low, and returns high
after the temperature drops back down to +50°C.
Table 3. Example Resistor Settings and Trip Points
CHANNEL
SETA
RESISTOR SETTING (kΩ)
HYSTERESIS (°C)
TRIP TEMPERATURE (°C)
78.7
249
+90
+60
10
SETB
Copyright © 2019, Texas Instruments Incorporated
13
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
8.2.2.3 Application Curve
OUTB
VCC
OUTA
VCC
+50°C
Figure 12. TMP392 Output Response With Hysteresis
+60°C
TTRIP
+80°C
+90°C
TTRIP
14
Copyright © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
8.2.3 One Channel Operation for Hot Trip Point up to 124°C
Figure 13 shows the TMP392 configured for one channel operation, with a single resistor to set the hot trip point
and hysteresis. Table 4 shows the possible resistor values and hysteresis values that may be used for one
channel applications.
3.3 V
0.1 µF
10 kΩ
VDD
OUTA
SETA
33.2 kΩ
TMP39x
SETB
OUTB
GND
Figure 13. TMP392 One Channel (Hot) Operation Example Circuit With 78°C Trip Point and 5°C
Hysteresis
Table 4. Single Resistor One Channel Setting
CHANNEL A TRIP
TEMPERATURE (°C)
NOMINAL 1% RESISTOR (KΩ)
HYSTERESIS (°C)
10.5
12.1
14.0
16.2
18.7
21.5
24.9
28.7
33.2
38.3
44.2
51.1
59.0
68.1
78.7
90.0
105
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
10
10
10
10
10
121
140
162
187
Copyright © 2019, Texas Instruments Incorporated
15
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
Table 4. Single Resistor One Channel Setting (continued)
CHANNEL A TRIP
TEMPERATURE (°C)
NOMINAL 1% RESISTOR (KΩ)
HYSTERESIS (°C)
215
249
287
332
383
442
511
590
681
787
909
104
106
108
110
112
114
116
118
120
122
124
10
10
10
10
10
10
10
10
10
10
10
8.2.3.1 Application Curve
Hot threshold
Hysteresis
5°C
Time (s)
OUTA
VDD
When VDD supply voltage is zero, the pullup output voltage is still present
Time (s)
Figure 14. TMP392 One Channel (Hot) Operation Thresholds and Hysteresis
16
Copyright © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
8.2.4 One Channel Operation for Warm Trip Point from 30°C up to 105°C
Figure 15 shows the TMP392 configured for one channel operation, with a single resistor to set the warm trip
point and hysteresis. The resistor values for one channel warm trip point is same as described in 表 2.
3.3 V
0.1 µF
10 kΩ
VDD
OUTA
SETA
TMP392
215 kΩ
SETB
OUTB
GND
Figure 15. TMP392 One Channel (Warm) Operation Example Circuit With 55°C Trip Point and 10°C
Hysteresis
9 Power Supply Recommendations
The low supply current and wide supply range of the TMP392 allow the device to be powered from many
sources. VDDIO must always be lower than or equal to VDD + 0.3 V.
Power supply bypassing is strongly recommended by adding a 0.1-µF capacitor from VDD to GND. In noisy
environments, TI recommends to add a filter with 0.1-µF capacitor and 100-Ω resistor between external supply
and VDD to limit the power supply noise.
10 Layout
10.1 Layout Guidelines
The TMP392 is extremely simple to layout. Place the power supply bypass capacitor as close to the device as
possible, and connect the capacitor as shown in Figure 16. Place the RSETA and RSETB resistors as close to the
device as possible. Carefully consider the resistor placement to avoid additional leakage or parasitic capacitance,
as this may affect the actual resistor sense value for the trip thresholds and hysteresis. If there is a possibility of
moisture condensation on the SETA and SETB circuits, which may lead to additional leakage current, consider
adding a conformal coating to the circuits.
版权 © 2019, Texas Instruments Incorporated
17
TMP392
ZHCSKH3 –NOVEMBER 2019
www.ti.com.cn
10.2 Layout Example
VIA to ground plane
VIA to power plane
RSETA
SETA
SETB
GND
OUTA
VDD
0.1 …F
RSETB
OUTB
Figure 16. TMP392 Recommended Layout
18
版权 © 2019, Texas Instruments Incorporated
TMP392
www.ti.com.cn
ZHCSKH3 –NOVEMBER 2019
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP392A2DRLR
TMP392A2DRLT
TMP392A3DRLR
TMP392A3DRLT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
6
6
6
6
4000 RoHS & Green
250 RoHS & Green
4000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 130
-55 to 130
-55 to 130
-55 to 130
1CH
1CH
1CI
NIPDAU
NIPDAU
NIPDAU
1CI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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