TMP64_V02 [TI]
TMP64 ±1% 47-kΩ Linear Thermistor With 0402 Package;
| 型号： | TMP64_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMP64 ±1% 47-kΩ Linear Thermistor With 0402 Package |
| 文件： | 总28页 (文件大小：1358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMP64
SNIS212B –DECEMBER 2019–REVISED JUNE 2020
TMP64 ±1% 47-kΩ Linear Thermistor With 0402 Package
1 Features
3 Description
Get started today with the Thermistor Design Tool,
offering complete resistance vs temperature table (R-
T table) computation, other helpful methods to derive
temperature and example C-code.
1
•
Silicon-based thermistor with a
positive temperature coefficient (PTC)
•
•
Linear resistance change across temperature
47-kΩ nominal resistance at 25 °C (R25)
Linear thermistors offer linearity and consistent
sensitivity across temperature to enable simple and
accurate methods for temperature conversion. Low
–
±1% maximum (0 °C to 70 °C)
•
•
Wide operating temperature of –40 °C to +125 °C
Consistent sensitivity across temperature
power consumption and
a small thermal mass
minimize the impact of self-heating. With built-in
failsafe behavior at high temperatures and powerful
immunity to environmental variation, these devices
are designed for a long lifetime of high performance.
The small size of the TMP6 series also allows for
close placement to heat sources and quick response
times.
–
–
6400 ppm/°C TCR (25 °C)
0.2% typical TCR tolerance across
temperature range
•
•
Fast thermal response time of 0.6 s (DEC)
Long lifetime and robust performance
–
–
Built-in fail-safe in case of short-circuit failures
0.5% typical long term sensor drift
Take advantage of benefits over NTC thermistors
such as no extra linearization circuitry, minimized
calibration, less resistance tolerance variation, larger
sensitivity at high temperatures, and simplified
conversion methods to save time and memory in the
processor.
2 Applications
•
•
•
Temperature monitoring
–
–
HVAC and thermostats
The TMP64 is currently available in a 0402 footprint-
compatible X1SON package and a 0603 footprint-
compatible SOT-5X3 package.
Industrial control and appliances
Thermal compensation
–
–
Display backlights
Building automation
Device Information(1)
PART NUMBER
TMP64
PACKAGE
BODY SIZE (NOM)
0.60 mm × 1.00 mm
0.60 mm × 1.00 mm
Thermal threshold detection
X1SON
SOT-5X3(2)
–
–
Motor control
Chargers
TMP64
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) This package is in preview
Typical Implementation Circuits
Typical Resistances vs Ambient Temperature
90
VBias
RBias
IBias
75
60
45
30
RTMP64
RTMP64
VTemp
VTemp
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
64_F
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TMP64
SNIS212B –DECEMBER 2019–REVISED JUNE 2020
www.ti.com
Table of Contents
8.4 Feature Description................................................. 10
8.5 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application .................................................. 11
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 TMP64 R-T table..................................................... 10
9
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1 Receiving Notification of Documentation Updates 17
12.2 Support Resources ............................................... 17
12.3 Trademarks........................................................... 17
12.4 Electrostatic Discharge Caution............................ 17
12.5 Glossary................................................................ 17
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2019) to Revision B
Page
•
•
•
•
Added DYA (SOT-5X3) preview package .............................................................................................................................. 1
Updated Device Comparison table......................................................................................................................................... 3
Corrected view description in pin configurations and functions.............................................................................................. 4
Changed ISNS maximum from 400 µA to 100 µA in recommended operating conditions....................................................... 5
Changes from Revision Original (December 2019) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Changed data sheet status from: Advanced Information to: Production Data ....................................................................... 1
Updated Title .......................................................................................................................................................................... 1
Updated Features................................................................................................................................................................... 1
Updated Applications.............................................................................................................................................................. 1
Updated Description ............................................................................................................................................................... 1
Increased ESD CDM Rating from ±750 V to ± 1000 V .......................................................................................................... 5
Changed minimum 'Long Term Drift' spec for RH = 85 % from 0.1 % to -1 %...................................................................... 6
Added typical. 'Long Term Drift' spec for RH = 85 %............................................................................................................. 6
Changed maximum 'Long Term Drift' spec for RH = 85 % from 0.8 % to 1 % ...................................................................... 6
Changed minimum 'Long Term Drift' spec from 0.1 % to -1% ............................................................................................... 6
Added typical. 'Long Term Drift' spec..................................................................................................................................... 6
Changed maximum 'Long Term Drift' spec from 1 % to 1.8 % ............................................................................................. 6
Added 'Supply Dependence Resistance vs. Bias Current' graph........................................................................................... 7
Added 'Supply Dependence Resistance vs. Bias Voltage' graph .......................................................................................... 7
Added 'Step Response' graph................................................................................................................................................ 7
Added 'Thermal Response time' graphs................................................................................................................................. 7
Updated Thermistor Design Tool link ................................................................................................................................... 10
2
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SNIS212B –DECEMBER 2019–REVISED JUNE 2020
5 Device Comparison Table
PART
NUMBER
R25 TYP
R25 %TOL
RATING
TA
PACKAGE OPTIONS
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
TO-92S / LPG
–40 °C to 125 °C
–40 °C to 150 °C
–40 °C to 125 °C
–40 °C to 170 °C
–40 °C to 125 °C
TMP61
10k
1%
Catalog
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
TO-92S / LPG
Automotive Grade-1
Automotive Grade-0
Catalog
TMP61-Q1
10k
1%
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
TMP63
100k
100k
47k
1%
1%
1%
1%
TMP63-Q1
TMP64
Automotive Grade-1
Catalog
–40 °C to 125 °C
–40 °C to 125 °C
–40 °C to 125 °C
TMP64-Q1
47k
Automotive Grade-1
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6 Pin Configuration and Functions
DEC Package
2-Pin X1SON
Bottom View
œ
1
2
+
DYA Package
2-Pin SOT-5X3
Top View
ID Area
œ
1
2
+
(1) This package is in preview
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
1
–
+
Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +
terminal is at a higher voltage potential than the – terminal.
—
2
4
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SNIS212B –DECEMBER 2019–REVISED JUNE 2020
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
+6
UNIT
V
Voltage across pins 2 (+) and 1 (–)
Current through the device
Junction temperature (TJ)
+450
+150
+150
µA
°C
–65
–65
Storage temperature (Tstg
)
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.
7.2 ESD Ratings
VALUE
±2000
±1000
UNIT
(1)
Human-body model (HBM) per JESD22-A114
Charged-device model (CDM), per JEDEC specification JESD22-C101
V(ESD)
Electrostatic discharge
V
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX UNIT
VSns
ISns
TA
Voltage across pins 2 (+) and 1 (–)
5.5
100
125
V
Current passing through the device
0
µA
°C
Operating free-air temperature (specified performance) (X1SON/DEC Package)
–40
7.4 Thermal Information
TMP64
DEC (X1SON) DYA (SOT-5X3)
THERMAL METRIC
Units
2 PINS
443.4
195.7
254.6
19.9
2 PINS
742.9
315.8
506.2
109.3
500.4
–
RθJA
Junction-to-ambient thermal resistance(1)(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bot) thermal resistance
ΨJB
254.5
–
RθJC(bot)
(1) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
(2) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.
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7.5 Electrical Characteristics
TA = -40 °C - 125 °C, ISns = 42.553 μA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
46.53
–1
TYP
MAX
UNIT
R25
Thermistor Resistance at 25 °C
Resistance Tolerance
TA = 25 °C
TA = 25 °C
47
47.47
1
kΩ
RTOL
TA = 0 °C - 70 °C
–1
1
%
ppm/°C
%
TA = -40 °C - 125 °C
T1 = -40 °C, T2 = -30 °C
T1 = 20 °C, T2 = 30 °C
T1 = 80 °C, T2 = 90 °C
T1 = -40 °C, T2 = -30 °C
–1.5
1.5
TCR-35
TCR25
TCR85
TCR-35
TCR25
TCR85
+6220
+6400
+5910
±0.4
Temperature Coefficient of Resistance
%
%
Temperature Coefficient of Resistance Tolerance T1 = 20 °C, T2 = 30 °C
T1 = 80 °C, T2 = 90 °C
±0.2
%
±0.3
96 hours continuous operation at RH = 85% and
TA = 130 °C
VBias = 5.5 V, DEC Package
-1
-1
±0.1
0.5
1
ΔR
Sensor Long Term Drift (Reliability)
%
600 hours continuous operation at TA = 150 °C
VBias = 5.5V
1.8
tRES (stirred
T1 = 25 °C in Still Air to T2 = 125 °C in Stirred
Liquid
Thermal response to 63%
0.6
3.2
s
s
liquid)
tRES (still air) Thermal response to 63%
T1 = 25 °C to T2 = 70 °C in Still Air
6
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7.6 Typical Characteristics
at TA = 25 °C, (unless otherwise noted)
100
80
60
40
20
0
100
80
60
40
20
0
IBIAS = 2 mA
IBIAS = 10 mA
IBIAS = 20 mA
IBIAS = 42.6 mA
IBIAS = 100 mA
VBIAS = 1.8 V
VBIAS = 2.5 V
VBIAS = 3.3 V
VBIAS = 5 V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
64_R
64_R
RBias = 47 kΩ with ±0.01 % Tolerance
Figure 1. Resistance vs. Ambient Temperature Using
Multiple Bias Currents
Figure 2. Resistance vs. Ambient Temperature Using
Multiple Bias Voltages
6500
6500
6400
6300
6200
6100
6000
6400
6300
6200
6100
6000
0
10
20
30
40
50
60
70
80
90 100
1.5
2
2.5
3 3.5
Bias Voltage (V)
4
4.5
5
Bias Current (mA)
64_T
64_T
RBias = 47 kΩ with ±0.01% Tolerance
Figure 4. TCR as a Function of Sense Voltage, VSNS
Figure 3. TCR as a Function of Sense Current, ISNS
100
80
60
40
20
0
100
80
60
40
20
0
-40 èC
25 èC
50 èC
100 èC
125 èC
-40 èC
25 èC
50 èC
100 èC
125 èC
0
10
20
30
40
50
60
70
80
90 100
0
0.5
1
1.5
2
2.5
Bias Voltage (V)
3
3.5
4
4.5
5
5.5
Bias Current (mA)
64_s
64_s
RBias = 47 kΩ with ±0.01% Tolerance
Figure 5. Supply Dependence Resistance vs. Bias Current
Figure 6. Supply Dependence R vs. VBias
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Typical Characteristics (continued)
at TA = 25 °C, (unless otherwise noted)
2.5
85
80
75
70
65
60
55
50
45
2
1.5
1
0.5
0
VBias
VSNS
0
2
4
6
8
10
12
14
0
0.2
0.4
0.6
0.8
1
Time (ms)
Time (s)
64_s
64_r
TMP64: VSNS = 1 V
TMP64: Stirred Liquid. Temperature: 25 °C to 125 °C
Figure 7. Step Response
Figure 8. Thermal Response Time
64
62
60
58
56
54
52
50
48
46
0
2
4
6
8
Time (s)
10
12
14
16
64_r
TMP64: Still Air
Figure 9. Thermal Response Time
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SNIS212B –DECEMBER 2019–REVISED JUNE 2020
8 Detailed Description
8.1 Overview
The TMP64 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a uniform
and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI uses a
special silicon process where the the doping level and active region areas devices control the key characteristics
(the temperature coefficient resistance (TCR) and nominal resistance (R25)) . The device has an active area and
a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage potential. Connect
the negative terminal to the lowest voltage potential.
Unlike an NTC, which is a purely resistive device, the TMP64 resistance is affected by the current across the
device and the resistance changes when the temperature changes. In a voltage divider circuit, it is recommended
to maintain the top resistor value at 47 kΩ. Changing the top resistor value or the VBIAS value changes the
resistance vs temperature table (R-T table) of the TMP64, and subsequently the polynomials as described in the
Design Requirements section. Consult the TMP64 R-T table section for more information.
TCR (ppm/°C) = (RT2 – RT1) / ((T2 – T1) × R(T2+T1)/2
)
(1)
Below are the definitions of the key terms used throughout this document:
•
•
•
•
•
ISNS: Current flowing through the TMP64.
VSNS: Voltage across the two TMP64 terminals.
IBias: Current supplied by the biasing circuit.
VBias: Voltage supplied by the biasing circuit.
VTemp: Output voltage that corresponds to the measured temperature. Note that this is different from VSns. In
the use case of a voltage divider circuit with the TMP64 in the high side, VTemp is taken across RBias
.
8.2 Functional Block Diagram
VBias
RBias
IBias
RTMP64
RTMP64
VTemp
VTemp
Figure 10. Typical Implementation Circuits
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8.3 TMP64 R-T table
The TMP64 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current. TI
provides a Thermistor Design Tool to calculate the R-T table. The system designer should always validate the
calculations provided.
8.4 Feature Description
8.4.1 Linear resistance curve
The TMP64 has good linear behavior across the whole temperature range as shown in Figure 1. This range
allows a simpler resistance-to-temperature conversion method that reduces look-up table memory requirements.
The linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary with the
device.
The linear resistance across the entire temperature range allows the device to maintain sensitivity at higher
operating temperatures.
8.4.2 Positive Temperature Coefficient (PTC)
The TMP64 has a positive temperature coefficient. As temperature increases the device resistance increases
leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient system
increases power consumption with temperature as the resistance decreases.
The TMP64 benefits from the reduced power consumption of the bias circuit with less self-heating than a typical
NTC system.
8.5 Device Functional Modes
The device has one mode of operation that applies when operated within the Recommended Operating
Conditions.
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SNIS212B –DECEMBER 2019–REVISED JUNE 2020
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMP64 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves like a
temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on the
system-level requirements. The TMP64 has a nominal resistance at 25 °C (R25) of 47 kΩ, a maximum operating
voltage of 5.5 V (VSns), and maximum supply current of 100 µA (ISns). This device may be used in a variety of
applications to monitor temperature close to a heat source with the very small DEC package option compatible
with the typical 0402 (inch) footprint. Some of the factors that influence the total measurement error include the
ADC resolution (if applicable), the tolerance of the bias current or voltage, the tolerance of the bias resistance in
the case of a voltage divider configuration, and the location of the sensor with respect to the heat source.
9.2 Typical Application
9.2.1 Thermistor Biasing Circuits
Figure 11. Biasing Circuit Implementations With Linear Thermistor (Left) vs. Non-Linear Thermistor
(Right)
9.2.1.1 Design Requirements
Existing thermistors, in general, have a non-linear temperature vs. resistance curve. To linearize the thermistor
response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or a resistance
linearization circuit by adding another resistance in parallel with the thermistor, RP. The Thermistor Biasing
Circuits section highlights the two implementations where RT is the thermistor resistance. To generate an output
voltage across the thermistor, the engineer can use a voltage divider circuit with the thermistor placed at either
the high side (close to supply) or low side (close to ground), depending on the desired voltage response
(negative or positive). Alternatively, the thermistor can be biased directly using a precision current source
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Typical Application (continued)
(yielding the highest accuracy and voltage gain). It is common to use a voltage divider with thermistors because
of its simple implementation and lower cost. The TMP64, on the other hand, has a linear positive temperature
coefficient (PTC) of resistance such that the voltage measured across it increases linearly with temperature. As
such, the need for a linearization circuits is no longer a requirement, and a simple current source or a voltage
divider circuit can be used to generate the temperature voltage.
This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature
trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback
input for an active feedback control circuit.
The voltage across the TMP64, as described in Equation 2, can be translated to temperature using either a
lookup table method (LUT) or a fitting polynomial, V(T). The Thermistor Design Tool must be used to translate
Vtemp to Temperature. The temperature voltage must first be digitized using an ADC. The necessary resolution
of this ADC is dependent on the biasing method used. Additionally, for best accuracy, the bias voltage (VBIAS
)
should be tied to the reference voltage of the ADC to create a measurement where the difference in tolerance
between the bias voltage and the reference voltage cancels out. The engineer can also implement a low-pass
filter to reject system level noise, and the user should place the filter as close to the ADC input as possible.
9.2.1.2 Detailed Design Procedure
The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage
(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due to
the voltage supply is canceled and does not affect the temperature accuracy. This type of configuration is shown
in Figure 12. Equation 2 describes the output voltage (VTEMP) based on the variable resistance of the TMP64
(RTMP64) and bias resistor (RBIAS). The ADC code that corresponds to that output voltage, ADC full-scale range,
and ADC resolution is given in Equation 3.
VBias
RBias
RFilter
REF
IN
IN
ADC
CFilter
RTMP64
GND
Figure 12. TMP64 Voltage Divider With an ADC
≈
∆
«
’
RTMP64
VTEMP = VBIAS
ì
÷
RBIAS + RTMP64 ◊
(2)
(3)
V
≈
’
TEMP
ADC Code =
ì 2n
∆
÷
FSR
«
◊
where
•
•
FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF
)
n is the resolution of the ADC
Equation 4 shows whenever VREF = VBIAS, VBIAS cancels out.
≈
∆
∆
∆
’
÷
÷
÷
≈
∆
«
’
÷
RTMP64
V
ì
BIAS
RBIAS + RTMP64 ◊
VBIAS
≈
∆
«
’
÷
RTMP64
ADC Code =
ì 2n =
ì 2n
RBIAS + RTMP64 ◊
∆
∆
«
÷
÷
◊
(4)
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Typical Application (continued)
The engineer can use a polynomial equation or a LUT to extract the temperature reading based on the ADC
code read in the microcontroller. The Thermistor Design Tool should be used to translate the TMP64 resistance
to temperature.
The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the
output voltage of the divider circuit cannot increase much. Therefore, not all of the ADC codes are used due to
the small voltage output range compared to the FSR. This application is very common, however, and is simple to
implement.
The engineer can use a current source-based circuit, like the one shown in Figure 13, to have better control over
the sensitivity of the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I ×
R. For example, if a current source of 100 µA is used with the TMP64, the output voltage spans approximately
5.5 V and has a gain up to 40 mV/°C. Having control over the voltage range and sensitivity allows for full
utilization of the ADC codes and full-scale range. Similar to the ratiometric approach above, if the ADC has a
built-in current source that shares the same bias as the reference voltage of the ADC, the tolerance of the supply
current cancels out. In this case, a precision ADC is not required. This method yields the best accuracy, but can
increase the system implementation cost.
Precision
IBias
Current Source
RTMP64
VTemp
Figure 13. TMP64 Biasing Circuit With Current Source
In comparison to the non-linear NTC thermistor in a voltage divider, the TMP64 has an enhanced linear output
characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are shown in
Figure 14. Consider an example where VBIAS = 5 V, RBIAS = 47 kΩ, and a parallel resistor (RP) is used with the
NTC thermistor (RNTC) to linearize the output voltage with an additional 47-kΩ resistor. The TMP64 produces a
linear curve across the entire temperature range while the NTC curve is only linear across a small temperature
region. When the parallel resistor (RP) is added to the NTC circuit, the added resistor makes the curve much
more linear but greatly affects the output voltage range.
VBias
VBias
RBias
RBias
RTMP64
RNTC
RP
VTemp
VTemp
Figure 14. TMP64 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits
Copyright © 2019–2020, Texas Instruments Incorporated
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TMP64
SNIS212B –DECEMBER 2019–REVISED JUNE 2020
www.ti.com
Typical Application (continued)
9.2.1.2.1 Thermal Protection With Comparator
The engineer can use the TMP64, a voltage reference, and a comparator to program the thermal protection. As
shown in Figure 15, the output of the comparator remains low until the voltage of the thermistor divider, with
RBIAS and RTMP64, rises above the threshold voltage set by R1 and R2. When the output goes high, the
comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent
the output from continuously toggling around the temperature threshold when the output returns low. Either a
comparator with built-in hysteresis or feedback resistors may be used.
VBias
RBias
R1
VTrip
RTMP64
R2
Figure 15. Temperature Switch Using TMP64 Voltage Divider and a Comparator
9.2.1.2.2 Thermal Foldback
One application that uses the output voltage of the TMP64 in an active control circuit is thermal foldback. This is
performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures, the
LEDs begin to heat up due to environmental conditions and self heating. Thus, at a certain temperature threshold
based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs and prevent
thermal runaway. The TMP64 voltage output increases with temperature when the output is in the lower position
of the voltage divider and can provide a response used to fold back the current. Typically, the current is held at a
specified level until a high temperature is reached, known as the knee point, where the current must be rapidly
reduced. To better control the temperature/voltage sensitivity of the TMP64, a rail-to-rail operational amplifier is
used. In the example shown in Figure 16, the temperature “knee” where the foldback begins is set by the
reference voltage (2.5 V) at the positive input, and the feedback resistors set the response of the foldback curve.
The foldback knee point may be chosen based on the output of the voltage divider and the corresponding
temperature from Equation 5 (like 110 °C, for example). A buffer is used in-between the voltage divider with
RTMP64 and the input to the op amp to prevent loading and variations in VTEMP
.
14
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Product Folder Links: TMP64
TMP64
www.ti.com
SNIS212B –DECEMBER 2019–REVISED JUNE 2020
Typical Application (continued)
5 V
RFB
300 kꢀ
RBias
94 kꢀ
R2
200 kꢀ
R1
10 kꢀ
VTemp
VOut
VRef
RTMP64
R3
200 kꢀ
Figure 16. Thermal Foldback Using TMP64 Voltage Divider and a Rail-to-Rail Op Amp
The op amp remains high as long as the voltage output is below VRef. When the temperature goes above 110 °C,
then the output swings low to the 0-V rail of the op amp. The rate at which the foldback occurs is dependent on
the feedback network, RFB and R1, which varies the gain of the op amp, G, given by Equation 6. This in return
controls the voltage/temperature sensitivity of the circuit. This voltage output is fed into a LED driver IC that
adjusts output current accordingly. The final output voltage used for thermal foldback is VOUT, and is given in
Equation 7. In this example where the knee point is set at 110 °C, the output voltage curve is as shown in
Figure 17.
≈
∆
«
’
÷
RTMP64
VTEMP = VBIAS
ì
RBIAS + RTMP64 ◊
(5)
RFB
G =
R1
(6)
(7)
VOUT = -Gì VTEMP + 1+ G ì V
REF
6
5
4
3
2
1
0
0
25
50
75
100
125
150
Temperature (èC)
D014
Figure 17. Thermal Foldback Voltage Output Curve
Copyright © 2019–2020, Texas Instruments Incorporated
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TMP64
SNIS212B –DECEMBER 2019–REVISED JUNE 2020
www.ti.com
10 Power Supply Recommendations
The maximum recommended operating voltage of the TMP64 is 5.5 V (VSns), and the maximum current through
the device is 100 µA (ISns).
11 Layout
11.1 Layout Guidelines
The layout of the TMP64 is similar to that of a passive component. If the device is biased with a current source,
the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the circuit is
biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is connected
to ground, and V+ is connected to the output (VTEMP). If the device is placed on the upper side of the divider, V+
is connected to the voltage source and V– is connected to the output voltage (VTEMP). Figure 18 shows the
device layout.
11.2 Layout Example
Figure 18. Recommended Layout: DEC Package
16
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Product Folder Links: TMP64
TMP64
www.ti.com
SNIS212B –DECEMBER 2019–REVISED JUNE 2020
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2019–2020, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTMP6431DYAT
TMP6431DECR
ACTIVE
ACTIVE
SOT-5X3
X1SON
DYA
DEC
2
2
250
TBD
Call TI
Call TI
-40 to 125
-40 to 125
10000 Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
SN
Level-1-260C-UNLIM
HJ
TMP6431DECT
TMP6431DYAR
TMP6431DYAT
ACTIVE
PREVIEW
PREVIEW
X1SON
SOT-5X3
SOT-5X3
DEC
DYA
DYA
2
2
2
250
3000
250
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
HJ
Green (RoHS
& no Sb/Br)
1HH
1HH
Green (RoHS
& no Sb/Br)
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMP64 :
Automotive: TMP64-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP6431DECR
TMP6431DECT
X1SON
X1SON
DEC
DEC
2
2
10000
250
178.0
178.0
8.4
8.4
0.7
0.7
1.15
1.15
0.47
0.47
2.0
2.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMP6431DECR
TMP6431DECT
X1SON
X1SON
DEC
DEC
2
2
10000
250
205.0
205.0
200.0
200.0
33.0
33.0
Pack Materials-Page 2
PACKAGE OUTLINE
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
1.3
1.1
0.3
0.1
0.7
B
2X
TYP
0.5
0.77 MAX
C
SEATING PLANE
0.05 C
0.15
2X
0.08
SYMM
SYMM
0.35
0.25
2X
0.1
0.05
C A B
0.4
0.2
2X
4224978/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224978/A 04/2019
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DEC0002A
X1SON - 0.5 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
0.65
0.55
0.50
0.41
C
SEATING PLANE
0.05
0.00
0.03 C
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
PIN 1 ID
(45 X0.125)
SYMM
0.3
0.2
2X
0.1
C A B
4224506/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.25)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224506/A 08/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.05)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224506/A 08/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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