TMP708AQDBVRQ1 [TI]
具有引脚可选 10°C 和 30°C 迟滞的汽车级、±3°C 温度开关 | DBV | 5 | -40 to 125;
| 型号： | TMP708AQDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有引脚可选 10°C 和 30°C 迟滞的汽车级、±3°C 温度开关 | DBV | 5 | -40 to 125 开关 光电二极管 |
| 文件： | 总18页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMP708-Q1
ZHCSFW9 –DECEMBER 2016
TMP708-Q1 汽车类 采用 SOT 封装的电阻可编程温度开关
1 特性
3 说明
1
•
适用于汽车电子 应用
具有符合 AEC-Q100 标准的下列结果：
TMP708-Q1 是一款全集成式电阻可编程温度开关，其
温度阈值仅由一个外部电阻在整个运行范围内进行设
定。TMP708-Q1 提供一个低电平有效的开漏输出，可
由电压介于 2.7V 至 5.5V 范围内的电源供电。
•
–
–
–
器件温度等级 1：环境运行温度范围为 -40°C
至 125°C
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 3A
温度阈值精度通常为 ±0.5°C，最大值为 ±3.5°C（60°C
至 100°C）。静态消耗电流的典型值为 40μA。可通过
选择引脚来确定 10°C 或者 30°C 的温度滞后。
器件组件充电模式 (CDM) ESD 分类等级 C6
•
阈值精度：
TMP708-Q1 采用 5 引脚小外形尺寸晶体管 (SOT-23)
封装。
–
–
典型值 ±0.5°C
最大值 ±3.5°C（60°C 至 100°C）
•
•
•
•
•
•
•
由 1% 外部电阻设定的温度阈值
低静态电流：40μA（典型值）
开漏、低电平有效输出级
器件信息(1)
器件型号
TMP708-Q1
封装
SOT-23 (5)
封装尺寸（标称值）
2.90mm x 1.60mm
可通过引脚选择的 10°C 或者 30°C 温度滞后
VCC = 0.8 V 上指定的复位操作
电源范围：2.7V 至 5.5V
(1) 要了解所有可用封装，请见数据表末尾的封装选项附录。
封装：5 引脚小外形尺寸晶体管 (SOT)-23
2 应用
•
•
•
•
•
计算机（笔记本和台式机）
服务器
工业用和医疗用设备
存储区域网络
汽车用
典型应用
150 ꢀ
2.7 V to 5.5 V
0.1 …F
470 kꢀ
VCC
VCC
OT
TMP708
Microprocessor
GND
SET
GND
HYST
RSET
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS828
TMP708-Q1
ZHCSFW9 –DECEMBER 2016
www.ti.com.cn
目录
7.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 11
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
10 Layout................................................................... 11
10.1 Layout Guidelines ................................................. 11
10.2 Layout Example .................................................... 11
10.3 Thermal Considerations........................................ 11
11 器件和文档支持 ..................................................... 12
11.1 接收文档更新通知 ................................................. 12
11.2 社区资源................................................................ 12
11.3 商标....................................................................... 12
11.4 静电放电警告......................................................... 12
11.5 Glossary................................................................ 12
12 机械、封装和可订购信息....................................... 12
7
4 修订历史记录
日期
修订版本
注释
2016 年 12 月
*
最初发布。
2
Copyright © 2016, Texas Instruments Incorporated
TMP708-Q1
www.ti.com.cn
ZHCSFW9 –DECEMBER 2016
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
SET
GND
OT
1
2
3
5
4
VCC
HYST
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
GND
NO.
2
Analog power Device ground
HYST
OT
4
Digital input Hysteresis selection. For 10°C, HYST = VCC; for 30°C, HYST = GND.
Digital output Open-drain, active low output
3
SET
VCC
1
Analog input Temperature set point. Connect an external 1% resistor between SET and GND.
Analog power Power-supply voltage (2.7 V to 5.5 V)
5
Copyright © 2016, Texas Instruments Incorporated
3
TMP708-Q1
ZHCSFW9 –DECEMBER 2016
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
Supply, VCC
6
VCC + 0.3
6
Voltage
Input, SET and HYST
Output, OT
Input
V
20
Current
mA
°C
Output
20
Operating, TA
Junction, TJ
Storatge, Tstg
–40
–65
125
150
150
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±4000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
0
NOM
MAX
5.5
UNIT
V
VCC
TA
Supply voltage
Operating temperature
125
°C
6.4 Thermal Information
TMP708-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
217.9
86.3
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
44.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.4
ψJB
43.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2016, Texas Instruments Incorporated
TMP708-Q1
www.ti.com.cn
ZHCSFW9 –DECEMBER 2016
6.5 Electrical Characteristics
at TA = 0°C to 125°C and VCC = 2.7 V to 5.5 V (unless otherwise noted)
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 5 V
40
40
55
55
µA
µA
ICC
Supply current
VCC = 2.7 V
TEMPERATURE
TE
Temperature error
TA = 60°C to 100°C
±0.5
±3.5
°C
DIGITAL INPUT (HYST)
VIH
High-level input voltage
0.7 × VCC
V
V
VIL
Low-level input voltage
Input leakage current
Input capacitance
0.3 × VCC
Ilkg_in
CIN
1
µA
pF
10
ANALOG INPUT (SET)
VIN
Input voltage range
0
5
VCC
V
DIGITAL OPEN-DRAIN OUTPUT (OT)
I(OT_SINK)
Ilkg(OT)
Output sink current
VOT = 0.3 V
VOT = VCC
12
1
mA
µA
Output leakage current
Copyright © 2016, Texas Instruments Incorporated
5
TMP708-Q1
ZHCSFW9 –DECEMBER 2016
www.ti.com.cn
6.6 Typical Characteristics
at TA = 25°C and VCC = 2.7 V to 5.5 V (unless otherwise noted)
48
100
90
80
70
60
50
40
30
20
10
0
VCC = 5 V
46
44
42
40
38
36
34
VCC = 2.7 V
RSET = 0 W
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Temperature (°C)
Trip Temperature (°C)
Figure 1. Supply Current vs Temperature
Figure 2. RSET vs Trip Temperature
35
30
25
20
15
10
5
1.5
10°C Hysteresis
30°C Hysteresis
1
0.5
0
-0.5
-1
0
-1.5
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Trip Temperature (°C)
Trip Temperature (°C)
Figure 3. Hysteresis vs Trip Temperature
Figure 4. Temperature Error vs Trip Temperature
6
Copyright © 2016, Texas Instruments Incorporated
TMP708-Q1
www.ti.com.cn
ZHCSFW9 –DECEMBER 2016
7 Detailed Description
7.1 Overview
The TMP708-Q1 is a fully-integrated, resistor-programmable temperature switch that incorporates two
temperature-dependent voltage references and one comparator. One voltage reference exhibits a positive
temperature coefficient (tempco), and the other voltage reference exhibits a negative tempco. The temperature at
which both voltage references are equal determines the temperature trip point.
The Functional Block Diagram shows the comparator, the NFET open-drain device connected to the OT pin, the
positive tempco reference using the external RSET resistor, the negative tempco reference, and the hysteresis
control. The voltage of the positive tempco reference is controlled by external resistor RSET
.
7.2 Functional Block Diagram
2.7 V to 5.5 V
VCC
Hysteresis
Control
HYST
RPULLUP
Positive
SET
OT
Tempco
Reference
RSET
Negative
Tempco
Reference
TMP708
GND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
7
TMP708-Q1
ZHCSFW9 –DECEMBER 2016
www.ti.com.cn
7.3 Feature Description
7.3.1 Temperature Switch
The TMP708-Q1 temperature threshold is programmable from 0°C to 125°C and is set by an external 1%
resistor from the SET pin to the GND pin. The TMP708-Q1 has an open-drain, active-low output structure that
easily interfaces with a microprocessor.
The TMP708-Q1 reaches the temperature trip point when the voltage from the positive tempco reference
exceeds the voltage from the negative tempco reference. This difference causes the output of the comparator to
switch from logic 0 to logic 1. The comparator output drives the gate of the NFET open-drain device, and pulls
the voltage on the OT pin from logic 1 to logic 0 under these conditions; in other words, the output trips.
Furthermore, the logic 1 output from the comparator causes the hysteresis control to increase the voltage of the
positive tempco reference by an amount set by the logic setting on the HYST pin (10°C for logic 1 on the HYST
pin; 30°C for logic 0 on the HYST pin). Increase the voltage of the positive tempco reference after the TMP708-
Q1 trips to stop the TMP708-Q1 from untripping (voltage on the OT pin changing from logic 0 to logic 1) until the
local temperature reduces by the amount set by the HYST pin. After the local temperature reduces, and the
voltage from the positive tempco reference is less than the voltage from the negative tempco reference, the
output of the comparator switches from logic 1 to logic 0. This condition causes the voltage on the OT pin to
change from logic 0 to logic 1 (device untrips).
7.3.2 Hysteresis Input
The HYST pin is a digital input that allows the input hysteresis to be set at either 10°C (when HYST = VCC) or
30°C (when HYST = GND). The hysteresis function keeps the OT pin from oscillating when the temperature is
near the threshold. Thus, always connect the HYST pin to either VCC or GND. Other input voltages on this pin
can cause abnormal supply currents or a device malfunction.
7.3.3 Set-Point Resistor (RSET
)
Set the temperature threshold by connecting RSET from the SET pin to GND. The value of RSET is determined
using either Figure 2 or Equation 1:
RSET (kΩ) = 0.0012T2 – 0.9308T + 96.147
where
•
T = temperature threshold in degrees Celsius.
(1)
7.4 Device Functional Modes
The TMP708-Q1 device has a single functional mode. Normal operation for the TMP708-Q1 device occurs when
the power-supply voltage applied across the VCC and GND pins is within the specified operating range of 2.7 V
to 5.5 V.
8
Copyright © 2016, Texas Instruments Incorporated
TMP708-Q1
www.ti.com.cn
ZHCSFW9 –DECEMBER 2016
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP708-Q1 device is simple to configure. The only external components that the device requires are a
bypass capacitor and pullup resistor. Power-supply bypassing is strongly recommended. Use a 0.1-µF capacitor
placed as close as possible to the VCC supply pin. To minimize the internal power dissipation of the TMP708-Q1
family of devices, use a pullup resistor value greater than 10 kΩ from the OT pin to the VCC pin. See the
Hysteresis Input section for hysteresis configuration, and the Set-Point Resistor (RSET) section for configuring the
temperature threshold.
8.2 Typical Application
2.7 V to 5.5 V
150 ꢀ
0.1 …F
470 kꢀ
VCC HYST
OT
VCC
TMP708
Microprocessor
GND
SET
GND
RSET
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Overtemperature Protection for a 60°C Trip Point
8.2.1 Design Requirements
For this design example, a 2.7-V to 5.5-V power supply, 60°C trip point, and 10°C hysteresis are used.
Copyright © 2016, Texas Instruments Incorporated
9
TMP708-Q1
ZHCSFW9 –DECEMBER 2016
www.ti.com.cn
Typical Application (continued)
8.2.2 Detailed Design Procedure
Connect the HYST pin to VCC for 10°C hysteresis. For a 60°C temperature threshold, see the Set-Point Resistor
(RSET) section to compute an ideal RSET resistor value of 44.619 kΩ. Select the closest standard value resistor
available; in this case, 44.2 kΩ. Use a 10-kΩ pullup resistor from the OT pin to the VCC pin. To minimize power,
a larger-value pullup resistor can be used, but must not exceed 470 kΩ. Place a 0.1-μF bypass capacitor close to
the TMP708-Q1 device in order to reduce noise coupled from the power supply.
8.2.3 Application Curves
Figure 6 shows an example of the hysteresis feature. The HYST pin is connected to VCC, so the TMP708-Q1
device is configured for 10°C of hysteresis. The device is configured for a 60°C trip temperature by the RSET
resistor value; therefore, the OT output asserts low when the 60°C threshold is exceeded. The OT output
remains asserted low until the sensor reaches 50°C.
OUT
VS
T(TRIP)
50°C
60°C
Figure 6. TMP708-Q1 Hysteresis Function
10
Copyright © 2016, Texas Instruments Incorporated
TMP708-Q1
www.ti.com.cn
ZHCSFW9 –DECEMBER 2016
9 Power Supply Recommendations
The TMP708-Q1 low supply current and supply range allow this device to be powered from many sources. Any
significant noise on the VCC pin can result in a trip-point error. Minimize this noise by low-pass filtering the
device supply (VCC) using a 150-Ω resistor and a 0.1-μF capacitor.
10 Layout
10.1 Layout Guidelines
The TMP708-Q1 is extremely simple to lay out. Figure 7 shows the recommended board layout.
10.2 Layout Example
VIA to ground plane
VIA to power plane
RSET
150 ꢀ
SET
GND
OT
VCC
0.1 …F
HYST
Figure 7. Recommended Layout
10.3 Thermal Considerations
The TMP708-Q1 quiescent current is typically 40 μA. The device dissipates negligible power when the output
drives a high-impedance load. Thus, the die temperature is the same as the package temperature. In order to
maintain accurate temperature monitoring, provide a good thermal contact between the TMP708-Q1 package
and the device being monitored. The rise in die temperature as a result of self-heating is given by Equation 2:
ΔTJ = PDISS × θJA
where
•
•
PDISS = power dissipated by the device.
θJA = package thermal resistance. Typical thermal resistance for SOT-23 package is 217.9°C/W.
(2)
To limit the effects of self-heating, keep the output current at a minimum level.
版权 © 2016, Texas Instruments Incorporated
11
TMP708-Q1
ZHCSFW9 –DECEMBER 2016
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
12
版权 © 2016, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP708AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
708Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMP708-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2021
Catalog : TMP708
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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