TMP75C-Q1 [TI]
具有双线制接口和报警功能、精度为 1°C 的数字温度传感器;
| 型号： | TMP75C-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有双线制接口和报警功能、精度为 1°C 的数字温度传感器 温度传感 传感器 温度传感器 |
| 文件： | 总32页 (文件大小：829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMP75C-Q1
ZHCSFP0 –NOVEMBER 2016
TMP75C-Q1 具有两线制接口和报警功能的 1.8V 数字温度传感器
1 特性
3 说明
1
•
适用于汽车电子 应用
TMP75C-Q1 是一款集成数字温度传感器，此传感器具
有一个可由 1.8V 电源供电运行的 12 位模数转换器
(ADC)，并且与 NCT75 和 ADT75 引脚和寄存器兼
容。此器件采用 SOIC-8 和 VSSOP-8 两种封装，不需
要外部元件便可测温。TMP75C-Q1 能够以 0.0625°C
的分辨率读取温度，额定工作温度范围为 –40°C 至
+125°C。
•
具有符合 AEC-Q100 标准的下列结果：
–
–
–
器件温度 1 级：-40°C 至 125°C 的环境运行温
度范围
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
器件组件充电模式 (CDM) ESD 分类等级 C5
•
•
•
•
•
•
•
•
•
NCT75 和 ADT75 的低压替代产品
具有两线制接口的数字输出
多达 8 个引脚可编程总线地址
具有可编程触发值的过热 ALERT 引脚
用于节省电池电量的关断模式
单次转换模式
TMP75C-Q1 特有 系统管理总线 (SMBus) 和两线制接
口兼容性，并且可在同一总线上，借助 SMBus 过热报
警功能支持多达 8 个器件。利用可编程温度限值和
ALERT 引脚，传感器既可作为一个独立恒温器运行，
也作为一个针对节能或系统关断的过热警报器运行。
厂家校准温度精度和抗扰数字接口使得 TMP75C-Q1
成为其他传感器和电子元器件温度补偿的合适解决方
案，而且无需针对分布式温度感测的额外系统级校准或
复杂的电路板布局布线。
工作温度范围：-40°C 至 +125°C
工作电源范围：1.4V 至 3.6V
静态电流：
15μA 工作电流（典型值），0.3μA 关断电流（典
型值）
TMP75C-Q1 是多种消费类、计算机、通信、工业和环
境应用热管理和保护的理想 选择。
•
准确度：
–
–
–
0°C 至 +70°C 范围内为 ±0.25°C（典型值）
-20°C 至 +85°C 范围内为 ±0.5°C（典型值）
-40°C 至 +125°C 范围内为 ±1°C（典型值）
器件信息(1)
器件名称
TMP75C-Q1
封装
SOIC (8)
VSSOP (8)
封装尺寸（标称值）
4.90mm × 3.90mm
3.00mm × 3.00mm
•
•
分辨率：12 位 (0.0625°C)
封装：小外形尺寸集成电路 (SOIC)-8 和超薄小外
形尺寸封装 (VSSOP)-8
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
2 应用
•
•
•
服务器和计算机热管理
电信设备
办公机器、机顶盒、
恒温器控制
•
•
•
•
视频游戏控制台
电源和电池热保护
环境监测和供热通风与空气调节 (HVAC)
电机驱动器热保护
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS840
TMP75C-Q1
ZHCSFP0 –NOVEMBER 2016
www.ti.com.cn
温度精度（误差）与环境温度之间的关系
简化电路原理图
1.4 V to 3.6 V
3
2
0.01 mF
1
TMP75C-Q1
0
1
8
7
6
5
SDA
VS
A0
A1
A2
2
œ1
œ2
œ3
SCL
Two-Wire
Host Controller
Mean
3
ALERT
Mean - 61
Mean + 61
4
GND
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C005
2
版权 © 2016, Texas Instruments Incorporated
TMP75C-Q1
www.ti.com.cn
ZHCSFP0 –NOVEMBER 2016
目录
7.5 Programming........................................................... 17
7.6 Register Map........................................................... 17
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 16
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 22
11 器件和文档支持 ..................................................... 23
11.1 文档支持 ............................................................... 23
11.2 接收文档更新通知 ................................................. 23
11.3 社区资源................................................................ 23
11.4 商标....................................................................... 23
11.5 静电放电警告......................................................... 23
11.6 Glossary................................................................ 23
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
日期
修订版本
注释
2016 年 11 月
*
最初发布。
Copyright © 2016, Texas Instruments Incorporated
3
TMP75C-Q1
ZHCSFP0 –NOVEMBER 2016
www.ti.com.cn
5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and VSSOP
Top View
SDA
SCL
1
2
3
4
8
VS
A0
A1
A2
7
6
5
ALERT
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
7
A0
A1
A2
I
I
Address select. Connect to GND or VS.
Address select. Connect to GND or VS.
Address select. Connect to GND or VS.
6
5
I
ALERT
GND
SCL
SDA
VS
3
O
—
I
Overtemperature alert. Open-drain output; requires a pull-up resistor.
4
Ground.
2
Serial clock.
1
I/O
I
Serial data. Open-drain output; requires a pull-up resistor.
Supply voltage, 1.4 V to 3.6 V.
8
4
Copyright © 2016, Texas Instruments Incorporated
TMP75C-Q1
www.ti.com.cn
ZHCSFP0 –NOVEMBER 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
V
Supply voltage, VS
4
4
SDA, SCL, ALERT, A2, A1
–0.3
–0.3
V
Input voltage
A0
(VS) + 0.3
10
V
Sink current
SDA, ALERT
mA
°C
°C
Operating junction temperature
Storage temperature, Tstg
–40
–60
150
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.4
NOM
MAX
3.6
UNIT
V
Supply voltage
1.8
Operating free-air temperature, TA
–40
125
°C
6.4 Thermal Information
TMP75C-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
125.4
71.5
DGK (VSSOP)
8 PINS
188.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
79.1
65.8
109.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
21.1
15.3
ψJB
65.3
108
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2016, Texas Instruments Incorporated
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ZHCSFP0 –NOVEMBER 2016
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6.5 Electrical Characteristics
At TA = –40°C to +125°C and VS = +1.4 V to +3.6 V, unless otherwise noted. Typical values at TA = 25°C and VS = +1.8 V.
PARAMETER
TEMPERATURE INPUT
Temperature range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–40
125
°C
°C
Temperature resolution
0.0625
±0.25
±0.5
0°C to +70°C
±1
±2
±3
Temperature accuracy
(error)
–20°C to +85°C
°C
–40°C to +125°C
±1
DIGITAL INPUT/OUTPUT
VIH
VIL
IIN
High-level input voltage
Low-level input voltage
Input current
0.7(VS)
-0.3
VS
0.3(VS)
1
V
V
0 V < VIN < (VS) + 0.3 V
μA
V
S ≥ 2 V, IOUT = 3 mA
0.4
Low-level output
voltage
VOL
V
VS < 2 V, IOUT = 3 mA
0.2(VS)
ADC resolution
Conversion time
Update Rate
12
27
80
22
Bit
ms
ms
ms
One-shot mode
20
16
35
29
Bus timeout time
POWER SUPPLY
Operating supply range
1.4
3.6
37
V
Serial bus inactive
15
25
95
0.3
10
80
IQ
Quiescent current
Shutdown current
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 3.4 MHz
Serial bus inactive
µA
8
ISD
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 3.4 MHz
µA
6
Copyright © 2016, Texas Instruments Incorporated
TMP75C-Q1
www.ti.com.cn
ZHCSFP0 –NOVEMBER 2016
6.6 Typical Characteristics
At TA = 25°C and VS = +1.8 V (unless otherwise noted).
50
10
9
8
7
6
5
4
3
2
1
0
Vs = 1.4V
45
Vs = 1.4V
Vs = 1.8V
Vs = 3.6V
Vs = 1.8V
40
Vs = 3.6V
35
30
25
20
15
10
5
0
œ75 œ50 œ25
0
25
50
75
100 125 150
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
Temperature (°C)
C001
C002
Figure 1. Quiescent Current vs Temperature
Figure 2. Shutdown Current vs Temperature
30
29
28
27
26
25
24
23
22
21
20
200
175
150
125
100
75
Ta = -55˘C
Ta = 25˘C
Ta = 125˘C
50
Vs = 1.4V
Vs = 1.8V
Vs = 3.6V
25
0
œ75 œ50 œ25
0
25
50
75
100 125 150
10
100
1000
10000
Temperature (°C)
Bus Frequency (kHz)
C003
C004
Figure 3. Conversion Time vs Temperature
Figure 4. Quiescent Current vs Bus Frequency
3
2
1
0
œ1
œ2
œ3
Mean
Mean - 61
Mean + 61
œ75 œ50 œ25
0
25
50
75
100 125 150
Temperature (°C)
C005
Temperature Error (°C)
C006
Figure 6. Temperature Error at 25°C
Figure 5. Temperature Error vs Temperature
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7 Detailed Description
7.1 Overview
The TMP75C-Q1 is a digital temperature sensor optimal for thermal management and thermal protection
applications. The TMP75C-Q1 is two-wire and SMBus interface compatible, and is specified over a temperature
range of –40°C to +125°C.
The temperature sensing device for the TMP75C-Q1 is the chip itself. A bipolar junction transistor (BJT) inside
the chip is used in a band-gap configuration to produce a voltage proportional to the chip temperature. The
voltage is digitized and converted to a 12-bit temperature result in degrees Celsius, with resolution of 0.0625°C.
The package leads provide the primary thermal path because of the lower thermal resistance of the metal. Thus,
the temperature result is equivalent to the local temperature of the printed circuit board (PCB) where the sensor
is mounted.
7.2 Functional Block Diagram
ë{
Device
Voltage Regulator
Serial Interface
Register Bank
Oscillator
SDA
SCL
A0
Control Logic
N x I
I
ALERT
A1
A2
ADC
Thermal
BJT
GND
8
Copyright © 2016, Texas Instruments Incorporated
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7.3 Feature Description
7.3.1 Digital Temperature Output
The 12-bit digital output from each temperature measurement conversion is stored in the read-only temperature
register. Two bytes must be read to obtain the data, as shown in Figure 14. Note that byte 1 is the most
significant byte, followed by byte 2, the least significant byte. The temperature result is left-justified with the 12
most significant bits used to indicate the temperature. There is no need to read the second byte if resolution
below 1°C is not required. Table 1 summarizes the temperature data format. One LSB equals 0.0625°C.
Negative numbers are represented in binary twos complement format.
Table 1. Temperature Data Format(1)
DIGITAL OUTPUT
TEMPERATURE (°C)
BINARY
HEX
7FF
7FF
640
500
4B0
320
190
004
000
FFC
E70
D80
128
127.9375
100
80
0111 1111 1111
0111 1111 1111
0110 0100 0000
0101 0000 0000
0100 1011 0000
0011 0010 0000
0001 1001 0000
0000 0000 0100
0000 0000 0000
1111 1111 1100
1110 0111 0000
1101 1000 0000
75
50
25
0.25
0
–0.25
–25
–40
(1) The temperature sensor resolution is 0.0625°C/LSB.
Table 1 does not supply a full list of all temperatures. Use the following rules to obtain the digital data format for
a given temperature, and vice versa.
To convert positive temperatures to a digital data format:
Divide the temperature by the resolution. Then, convert the result to binary code with a 12-bit, left-justified
format, and MSB = 0 to denote a positive sign.
Example: (+50°C) / (0.0625°C / LSB) = 800 = 320h = 0011 0010 0000
To convert a positive digital data format to temperature:
Convert the 12-bit, left-justified binary temperature result, with the MSB = 0 to denote a positive sign, to a
decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature.
Example: 0011 0010 0000 = 320h = 800 × (0.0625°C / LSB) = +50°C
To convert negative temperatures to a digital data format:
Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a
12-bit, left-justified format. Then, generate the twos complement of the result by complementing the binary
number and adding one. Denote a negative number with MSB = 1.
Example: (|–25°C|) / (0.0625°C / LSB) = 400 = 190h = 0001 1001 0000
Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000
To convert a negative digital data format to temperature:
Generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with MSB
= 1, denoting negative temperature result) by complementing the binary number and adding one. Convert to
decimal number and multiply by the resolution to get the absolute temperature, then multiply by –1 for the
negative sign.
Example: 1110 0111 0000 has twos complement of 0001 1001 0000 = 0001 1000 1111 + 1
Convert to temperature: 0001 1001 0000 = 190h = 400; 400 × (0.0625°C / LSB) = 25°C = (|–25°C|);
(|–25°C|) × (–1) = –25°C
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7.3.2 Temperature Limits and Alert
The temperature limits are stored in the TLOW and THIGH registers (Table 7 and Table 8) in the same format as
the temperature result, and their values are compared to the temperature result on every conversion. The
outcome of the comparison drives the behavior of the ALERT pin, which can operate as a comparator output or
an interrupt, and is set by the TM bit in the Configuration register (Table 6).
In comparator mode (TM = 0, default), the ALERT pin becomes active when the temperature is equal to or
exceeds the value in THIGH (fault conditions) for a consecutive number of conversions as set by the FQ bits of the
configuration register. ALERT clears when the temperature falls below TLOW for the same consecutive number of
conversions. The difference between the two limits acts as a hysteresis on the comparator output, and a fault
counter prevents false alerts as a result of environmental noise.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value in
THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any
register occurs. After the ALERT pin is cleared, this pin becomes active again only when temperature falls below
TLOW for a consecutive number of fault conditions, and remains active until cleared by a read operation of any
register. The cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH
,
and so on. The ALERT pin is cleared also when the device is placed in shutdown mode (see Shutdown Mode for
shutdown mode description). This action also clears the fault counter memory.
The active state of the ALERT pin is set by the POL bit in the configuration register. When POL = 0 (default), the
ALERT pin is active low. When POL = 1, the ALERT pin is active high. The operation of the ALERT pin in the
various modes is illustrated in Figure 7.
THIGH
Measured
Temperature
TLOW
Device ALERT PIN
(Comparator Mode)
POL = 0
Device ALERT PIN
(Interrupt Mode)
POL = 0
Device ALERT PIN
(Comparator Mode)
POL = 1
Device ALERT PIN
(Interrupt Mode)
POL = 1
Read
Read
Time
Read
Figure 7. ALERT Pin Modes of Operation
10
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ZHCSFP0 –NOVEMBER 2016
7.3.3 Serial Interface
The TMP75C-Q1 operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are
made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression
filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP75C-Q1 supports the
transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3 MHz) modes. All data bytes
are transmitted MSB first.
7.3.3.1 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the start and stop conditions.
To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic
level while SCL is high. All slaves on the bus shift in the slave address byte; the last bit indicates whether a read
or write operation follows. During the ninth clock pulse, the slave being addressed responds to the master by
generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted
as a start or stop signal.
After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to
high, while SCL is high.
7.3.3.2 Serial Bus Address
To communicate with the TMP75C-Q1, the master must first communicate with slave devices using a slave
address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of
executing either a read or write operation. The TMP75C-Q1 features three address pins that allow up to eight
devices to be addressed on a single bus. The TMP75C-Q1 latches the status of the address pins at the start of a
communication. Table 2 describes the pin logic levels and the corresponding address values.
Table 2. Address Pin Connections and Slave Addresses
DEVICE TWO-WIRE ADDRESS
A2
GND
GND
GND
GND
VS
A1
GND
GND
VS
A0
GND
VS
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
GND
VS
VS
GND
GND
VS
GND
VS
VS
VS
GND
VS
VS
VS
7.3.3.3 Writing and Reading Operation
Accessing a particular register on the TMP75C-Q1 is accomplished by writing the appropriate value to the pointer
register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP75C-Q1 requires a value for the pointer register (see Figure 9).
When reading from the TMP75C-Q1, the last value stored in the pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the pointer register. This action is accomplished by issuing a slave address byte with the
R/W bit low, followed by the pointer register byte. No additional data are required. The master can then generate
a start condition and send the slave address byte with the R/W bit high to initiate the read command. See
Figure 10 for details of this sequence. If repeated reads from the same register are desired, there is no need to
continually send the pointer register bytes because the TMP75C-Q1 stores the pointer register value until it is
changed by the next write operation.
Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
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7.3.3.4 Slave Mode Operations
The TMP75C-Q1 can operate as a slave receiver or slave transmitter.
7.3.3.4.1 Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP75C-Q1 then
acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The
TMP75C-Q1 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the
register addressed by the pointer register. The TMP75C-Q1 acknowledges reception of each data byte. The
master can terminate data transfer by generating a start or stop condition.
7.3.3.4.2 Slave Transmitter Mode:
The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges
reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of
the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The
master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by
generating a start or stop condition.
7.3.3.5 High-Speed (Hs) Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus
Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed
operation. The TMP75C-Q1 does not acknowledge this byte, but does switch its input filters on SDA and SCL
and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3 MHz. After the Hs-mode master
code has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The
bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition,
the TMP75C-Q1 switches the input and output filters back to fast-mode operation.
7.3.3.6 Timeout Function
The TMP75C-Q1 resets the serial interface if SCL or SDA are held low for 22 ms (typ) between a start and stop
condition. If the TMP75C-Q1 is pulled low, it releases the bus and then waits for a start condition. To avoid
activating the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL
operating frequency.
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7.3.3.7 Two-Wire Timing
The TMP75C-Q1 is two-wire and SMBus compatible. Figure 8 to Figure 10 describe the various operations on
the TMP75C-Q1. Parameters for Figure 8 are defined in Table 3. Bus definitions are:
Bus Idle
Both SDA and SCL lines remain high.
Start Data Transfer A change in the state of the SDA line, from high to low, while the SCL line is high defines a
start condition. Each data transfer is initiated with a start condition.
Stop Data Transfer A change in the state of the SDA line from low to high while the SCL line is high defines a
stop condition. Each data transfer is terminated with a repeated start or stop condition.
Data Transfer The number of data bytes transferred between a start and a stop condition is not limited, and is
determined by the master device.
The receiver acknowledges the transfer of data. It is also possible to use the TMP75B for
single-byte updates. To update only the MS byte, terminate communication by issuing a start
or stop condition on the bus.
Acknowledge Each receiving device, when addressed, must generate an acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge clock
pulse. Setup and hold times must be taken into account. When a master receives data, the
termination of the data transfer can be signaled by the master generating a not-acknowledge
(1) on the last byte transmitted by the slave.
Table 3. Timing Diagram Requirements
FAST MODE
MIN
HIGH-SPEED MODE
MAX
0.4
MIN
0.001
0.001
160
MAX
UNIT
MHz
MHz
ns
V
S ≥ 1.8 V
VS < 1.8 V
S ≥ 1.8 V
VS < 1.8 V
0.001
3
f(SCL)
SCL operating frequency
0.001
0.4
2.5
V
1300
Bus free time between
stop and start conditions
t(BUF)
1300
260
ns
Hold time after repeated start condition.
After this period, the first clock is generated.
t(HDSTA)
600
160
ns
t(SUSTA)
t(SUSTO)
Repeated start condition setup time
Stop condition setup time
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
S ≥ 1.8 V
VS < 1.8 V
S ≥ 1.8 V
VS < 1.8 V
S ≥ 1.8 V
VS < 1.8 V
900
900
100
140
t(HDDAT)
t(SUDAT)
t(LOW)
Data hold time
0
0
V
100
100
1300
1300
600
10
Data setup time
SCL clock low period
20
V
190
240
60
t(HIGH)
SCL clock high period
Data rise and fall time
Clock rise and fall time
tR(SDA), tF(SDA)
tR(SCL), tF(SCL)
tR
300
300
80
40
Clock and data rise time for SCLK ≤ 100 kHz
1000
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7.3.3.8 Two-Wire Timing Diagrams
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH) t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 8. Two-Wire Timing Diagram
1
9
1
9
SCL
SDA
¼
A2(1) A1(1) A0(1)
1
0
0
1
R/W
0
0
0
0
0
P2
P1
P0
¼
Start By
Master
ACK By
ACK By
Device
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4 D3
D2 D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
(Continued)
ACK By
Device
ACK By
Stop By
Master
Device
Frame 3 Data Byte 1
Frame 4 Data Byte 2
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
Figure 9. Two-Wire Timing Diagram for Write Word Format
14
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1
9
1
9
¼
SCL
SDA
1
0
0
1
A2(1) A1(1) A0(1)
R/W
0
0
0
0
0
P2
P1
P0
Start By
Master
ACK By
ACK By
Stop By
Master
Device
Device
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
¼
(Continued)
SDA
A2(1) A1(1) A0(1)
¼
1
0
0
1
R/W
D7
D6
D5
D4 D3
D2
D1
D0
(Continued)
Start By
Master
ACK By
From
Device
ACK By
Master(2)
Device
Frame 3 Two-Wire Slave Address Byte
Frame 4 Data Byte 1 Read Register
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4
D3
D2
D1
D0
(Continued)
From
ACK By
Master(3)
Stop By
Master
Device
Frame 5 Data Byte 2 Read Register
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
(2) Master should leave SDA high to terminate a single-byte read operation.
(3) Master should leave SDA high to terminate a two-byte read operation.
Figure 10. Two-Wire Timing Diagram for Read Word Format
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7.4 Device Functional Modes
7.4.1 Continuous-Conversion Mode
The default mode of the TMP75C-Q1 is continuous conversion, where the ADC performs continuous temperature
conversions and stores each result to the Temperature register, overwriting the result from the previous
conversion. The typical conversion rate of TMP75C-Q1 is 12 Hz, with 80 ms between the start of each
consecutive conversion. The TMP75C-Q1 has a typical conversion time of 27 ms. To achieve its conversion
rates, the TMP75C-Q1 makes a conversion, and then powers down and waits for a delay 53 ms.
After power-up, the TMP75C-Q1 immediately starts a conversion, as shown in Figure 11. The first result is
available after 27 ms (typical). The active quiescent current during conversion is 45 μA (typical at +25°C). The
quiescent current during delay is 1 μA (typical at +25°C).
Delay(1)
Delay(1)
27 ms
27 ms
27 ms
Startup
Start of
Conversion
Start of
Conversion
(1) Delay is set to 53 ms (typ).
Figure 11. Conversion Start
7.4.2 Shutdown Mode
The shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface,
and reduces current consumption to typically less than 0.3 μA. Shutdown mode is enabled when the SD bit in the
configuration register is set to 1; the device shuts down and terminates a conversion if it is ongoing. When SD is
equal to 0, the device operates in continuous-conversion mode. When shutdown mode is enabled, the ALERT
pin and fault counter clear in both comparator and interrupt modes. The ALERT pin and the fault counter remain
clear until the SD bit is set.
7.4.3 One-Shot Mode
The TMP75C-Q1 features a one-shot temperature measurement mode. When the device is in continuous
conversion (SD = 0), writing a 1 to the OS bit enables shutdown mode, where any write to the one-shot register
triggers a single temperature conversion. The device returns to the shutdown state at the completion of the single
conversion, and a subsequent write to the one-shot register triggers another single conversion followed by a
return to shutdown state. This mode reduces power consumption in the TMP75C-Q1 when continuous
temperature monitoring is not required.
When the device is in complete shutdown (SD = 1), the one-shot mode is not active regardless of the state of the
OS bit, and a write to the one-shot register has no effect.
16
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7.5 Programming
Figure 12 shows the internal register structure of the TMP75C-Q1. Use the 8-bit pointer register to address a
given data register. The pointer register uses the three LSBs to identify which of the data registers respond to a
read or write command. Figure 13 identifies the bits of the pointer register byte.
Pointer
Register
Temperature
Register
Configuration
Register
SCL
I/O
Control
TLOW
Register
Interface
SDA
THIGH
Register
One-Shot
Register
Figure 12. Internal Register Structure
7.6 Register Map
Table 4 describes the registers available in the TMP75C-Q1 with their pointer addresses, followed by the
description of the bits in each register.
Table 4. Register Map and Pointer Addresses
P2
0
P1
0
P0
0
REGISTER
Temperature register (read only, default)
Configuration register (read/write)
TLOW register (read/write)
0
0
1
0
1
0
0
1
1
THIGH register (read/write)
1
0
0
One-Shot register (write only; write any value to start a
conversion)
Figure 13. Pointer Register (pointer = N/A) [reset = 00h]
7
6
5
4
3
2
1
0
Reserved
W-0h
P2
P1
P0
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
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Figure 14. Temperature Register (pointer = 0h) [reset = 0000h]
15
14
13
T9
12
T8
11
T7
10
T6
9
8
T11
T10
T5
T4
R-00h
7
6
5
4
3
2
1
0
T3
T2
T1
T0
Reserved
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. Temperature Register Description
Name
Description
T11 to T4
T3 to T0
The 8 MSBs of the temperature result (resolution of 1°C)
The 4 LSBs of the temperature result (resolution of 0.0625°C)
Figure 15. Configuration Register (pointer = 1h) [reset = 0000h]
15
7
14
6
13
OS
12
11
10
9
8
Reserved
R/W-0h
FQ
POL
TM
SD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
5
4
3
2
1
0
Reserved
R-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Configuration Register Description
Name
Description
Reserved
Reserved bits
Write 0 to these bits on configuration register update.
One-shot control
OS
SD = 0 and OS = 0: Continuous conversion mode (default)
SD = 0 and OS = 1: One-shot mode; the device is in shutdown mode but writing any value to the one-shot register
initiates a conversion. The device returns to shutdown mode at the end of the conversion.
SD = 1 and OS = x: The device is in shutdown mode and the status of the OS bit has no effect. Writing to the one-
shot register does not start a conversion.
FQ
Fault queue to trigger the ALERT pin
FQ = 0h: 1 fault (default)
FQ = 1h: 2 faults
FQ = 2h: 4 faults
FQ = 3h: 6 faults
POL
TM
ALERT polarity control
POL = 0: ALERT is active low (default)
POL = 1: ALERT is active high
ALERT thermostat mode control
TM = 0: ALERT is in comparator mode (default)
TM = 1: ALERT is in interrupt mode
Shutdown control bit
SD
SD = 0: Device is in continuous conversion mode (default)
SD = 1: Device is in shutdown mode
18
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Figure 16. TLOW - Temperature Low Limit Register (pointer = 2h) [reset = 4B00h](1)
15
14
13
L9
12
L8
11
L7
10
L6
9
8
L11
L10
L5
L4
R/W-4Bh
7
6
5
4
3
2
1
0
L3
L2
L1
L0
Reserved
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) 4B00h = 75°C.
Table 7. TLOW Register Description
Name
Description
The 8 MSBs of the temperature low limit (resolution of 1°C)
The 4 LSBs of the temperature low limit (resolution of 0.0625°C)
L11 to L4
L3 to L0
Figure 17. THIGH - Temperature High Limit Register (pointer = 3h) [reset = 5000h](1)
15
14
13
12
11
10
9
8
H11
H10
H9
H8
H7
H6
H5
H4
R/W-50h
7
6
5
4
3
2
1
0
H3
H2
H1
H0
Reserved
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) 5000h = 80°C.
Table 8. THIGH Register Description
Name
Description
The 8 MSBs of the temperature high limit (resolution of 1°C)
The 4 LSBs of the temperature high limit (resolution of 0.0625°C)
H11 to H4
H3 to H0
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8 Application and Implementation
8.1 Application Information
The TMP75C-Q1 is used to measure the PCB temperature of the location it is mounted. The programmable
address options allow up to eight locations on the board to be monitored on a single serial bus. Connecting the
ALERT pins together and programming the temperature limit registers to desired values allows for a temperature
watchdog operation of all devices, interrupting the host controller only if the temperature exceeds the limits.
8.2 Typical Application
1.4 V to 3.6 V
0.01 mF
TMP75C-Q1
1
2
3
4
8
7
6
5
SDA
VS
A0
A1
A2
Two-Wire
Host Controller
SCL
Connect to VS or
GND for up to 8
Address
ALERT
GND
Combinations
1.4 V to 3.6 V
TMP75C-Q1
0.01 mF
1
2
3
4
8
7
SDA
VS
A0
A1
A2
SCL
Connect to VS or
GND for up to 8
Address
6
5
ALERT
GND
Combinations
Copyright © 2016, Texas Instruments Incorporated
Additional
Sensor
Locations
Figure 18. Temperature Monitoring of Multiple Locations on a PCB
20
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Typical Application (continued)
8.2.1 Design Requirements
The TMP75C-Q1 only requires pull-up resistors on SDA and ALERT, although a pull-up resistor is typically
present on the SCL as well. A 0.01-μF bypass capacitor on the supply is recommended, as shown in Figure 18.
The SCL, SDA, and ALERT lines can be pulled up to a supply that is equal to or higher than VS through the pull-
up resistors. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either VS or
GND.
8.2.2 Detailed Design Procedure
The TMP75C-Q1 should be placed in close proximity to the heat source to be monitored, with a proper layout for
good thermal coupling. This ensures that temperature changes are captured within the shortest possible time
interval.
8.2.3 Application Curves
Figure 19 shows the step response of the TMP75C-Q1 to a submersion in an oil bath of 100°C from room
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 seconds.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
œ1 0
1
2
3
4
5
6
7
8
9 1011121314151617181920
Time (s)
C007
Figure 19. Temperature Step Response
9 Power Supply Recommendations
The TMP75C-Q1 operates with a power supply in the range of 1.4 V to 3.6 V. It is optimized for operation at 1.8-
V supply but can measure temperature accurately in the full supply range.
A power-supply bypass capacitor is required for stability; place this capacitor as close as possible to the supply
and ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy
or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
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10 Layout
10.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The recommended
value of this bypass capacitor is 0.01 μF. Additional decoupling capacitance can be added to compensate for
noisy or high-impedance power supplies.
Pull up the open-drain output pins (SDA and ALERT) to a supply voltage rail (VS or higher but up to 3.6 V)
through 10-kΩ pull-up resistors.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
VS
A0
A1
A2
SCL
ALERT
GND
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 20. Layout Example
22
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11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
《TMP75BEVM 和 TMP75CEVM 用户指南》（文献编号：SBOU141）
11.2 接收文档更新通知
如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册
后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
23
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Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP75CQDGKRQ1
TMP75CQDRQ1
ACTIVE
ACTIVE
VSSOP
SOIC
DGK
D
8
8
2500 RoHS & Green
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
T75CQ
T75CQ
NIPDAU-DCC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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