TMS27C128-12JE [TI]
131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY; 131 072 - BIT UV可擦除可编程只读存储器
| 型号： | TMS27C128-12JE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY |
| 文件： | 总14页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
J AND N PACKAGES
This Data Sheet is Applicable to All
(TOP VIEW)
TMS27C128s and TMS27PC128s Symbolized
with Code “B” as Described on Page 12.
V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
V
CC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PP
•
•
•
Organization . . . 16K × 8
PGM
A13
A8
A9
A11
G
2
Single 5-V Power Supply
3
4
Pin Compatible With Existing 128K MOS
ROMs, PROMs, and EPROMs
5
6
•
•
All Inputs/Outputs Fully TTL Compatible
7
A10
E
8
Max Access/Min Cycle Times
9
V
± 10%
CC
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
13
14
’27C128-12
120 ns
’27C/PC128-15 150 ns
’27C/PC128-20 200 ns
’27C/PC128-25 250 ns
•
•
•
•
Power Saving CMOS Technology
Very High-Speed SNAP! Pulse Programming
3-State Output Buffers
FM PACKAGE
(TOP VIEW)
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
4
5
3
2
1
32 31 30
29
•
•
Latchup Immunity of 250 mA on All Input
and Output Lines
A6
A5
A4
A3
A2
A8
A9
28
27
26
25
24
23
22
21
6
7
8
9
A11
NC
G
A10
E
Low Power Dissipation (V
= 5.25 V)
CC
– Active . . . 158 mW Worst Case
– Standby . . . 1.4 mW Worst Case
(CMOS Input Levels)
A1 10
A0 11
NC 12
•
•
PEP4 Version Available With 168-Hour
Burn-In and Choices of Operating
Temperature Ranges
DQ7
DQ6
DQ0
13
14 15 16 17 18 19 20
128K EPROM Available With MIL-STD-883C
Class B High-Reliability Processing
(SMJ27C128)
description
PIN NOMENCLATURE
The TMS27C128 series are 131 072-bit,
ultraviolet-light erasable, electrically
programmable read-only memories.
A0–A13
E
G
GND
NC
NU
Address Inputs
Chip Enable/Powerdown
Output Enable
Ground
No Connection
Make No External Connection
Program
The TMS27PC128 series are 131 072-bit, one
time electrically programmable read-only
memories.
PGM
DQ0–DQ7 Inputs (programming)/Outputs
V
CC
V
PP
5-V Power Supply
12-13 V Programming Power Supply
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C128 and the
TMS27PC128 are pin compatible with 28-pin 128K MOS ROMs, PROMs, and EPROMs.
The TMS27C128 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C128 is offered with two operating temperature
ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). The TMS27C128 is also offered with 168-hour
burn-in temperature ranges (JL4 and JE4 suffixes). (See table below).
TheTMS27PC128PROMisofferedinadual-in-lineplasticpackage(Nsuffix)designedforinsertioninmounting
hole rows on 15,2-mm (600-mil) centers. The TMS27PC128 is also supplied in a 32-lead plastic leaded chip
carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). The TMS27PC128 is also offered with two
operating temperature ranges of 0°C to 70°C (NL and FML suffixes) and –40°C to 85°C (NE and FME suffixes).
The TMS27PC128 is also offered with 168 hour burn-in temperature ranges (NL4, FML4, NE4, and FME4
suffixes). (See table below).
All package styles conform to JEDEC standards.
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
SUFFIX FOR OPERATING
TEMPERATURE RANGES WITH
PEP4 168 HR. BURN-IN
EPROM
AND
PROM
0°C TO 70°C
–40 °C TO 85°C
0°C TO 70°C
JL4
–40 °C TO 85°C
TMS27C128-XXX
TMS27PC128-XXX
TMS27PC128-XXX
JL
NL
JE
NE
JE4
NE4
NL4
FML
FME
FML4
FME4
These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in
microprocessor-based systems. One other 12-13-V supply is needed for programming . All programming
signals are TTL level. These devices are programmable by using the SNAP! Pulse programming algorithm.The
SNAP! Pulse programming algorithm uses a V of 13.0 V and a V
of 6.5 V for a nominal programming time
PP
CC
of two seconds. For programming outside the system, existing EPROM programmers can be used. Locations
may be programmed singly, in blocks, or at random.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
operation
The seven modes of operation are listed in the following table. Read mode requires a single 5-V supply. All
inputsareTTLlevelexceptforV duringprogramming(13VforSNAP!Pulse), and12VonA9forthesignature
PP
mode.
MODE
FUNCTION
OUTPUT
DISABLE
PROGRAM
INHIBIT
SIGNATURE
MODE
READ
STANDBY PROGRAMMING
VERIFY
E
G
V
V
V
V
V
V
V
V
V
V
IL
IL
IH
IH
IH
†
IL
IL
IH
IL
V
V
X
V
IH
X
X
IL
IL
IL
PGM
V
IH
X
V
IL
V
IH
V
IH
V
V
V
V
V
V
V
V
V
PP
CC
CC
CC
PP
PP
PP
CC
CC
V
CC
V
CC
X
V
CC
X
V
CC
X
V
CC
X
V
CC
X
V
CC
X
‡
V
H
A9
A0
V
H
X
X
X
X
X
X
V
IL
V
IH
CODE
Data Out
Data In
Data Out
DQ0–DQ7
HI-Z
HI-Z
HI-Z
MFG
97
DEVICE
83
†
X can be V or V
IL
H
.
IH
= 12 V ± 0.5 V.
V
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
read/output disable
When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup
without compromising performance or packing density.
power down
ActiveI supplycurrentcanbereducedfrom30mAto500µA(TTL-levelinputs)or250µA(CMOS-levelinputs)
CC
by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure (TMS27C128)
Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light
2
2
exposure dose (UV intensity × exposure time) is 15-W s/cm . A typical 12-mW/cm , filterless UV lamp will
erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS27C128, the window should be covered with an opaque label.
initializing (TMS27PC128)
The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows
are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.
SNAP! Pulse programming
The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm, illustrated
by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will
vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, PGM is
pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V
= 13 V, V
= 6.5 V, G = V , and E = V . More than
CC IH IL
PP
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with V
= V
= 5 V.
CC
PP
program inhibit
Programming may be inhibited by maintaining a high level input on the E or PGM pin.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
program verify
Programmed bits may be verified with V = 13 V when G = V , E = V , and PGM = V .
PP
IL
IL
IH
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by A0; i.e., A0 = V
IL
accesses the manufacturer code, which is output on DQ0–DQ7; A0 = V accesses the device code, which
IH
is output on DQ0–DQ7. All other addresses must be held at V . The manufacturer code for these devices
IL
is 97, and the device code is 83.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
Start
Address = First Location
Program
Mode
V
CC
= 6.5 V ± 0.25 V, V = 13 V ± 0.25 V
PP
Program One Pulse = t = 100 µs
Increment Address
w
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t = 100 µs
w
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
Device Failed
V
CC
= V
= 5 V ± 0.5 V
PP
Compare
All Bytes
To Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
†
logic symbol
EPROM 16 384 × 8
PROM 16 384 × 8
10
10
9
0
0
A0
A0
A1
A2
9
A1
8
8
7
A2
7
A3
A3
A4
A5
11
12
13
15
16
17
18
19
11
12
13
15
16
17
18
19
6
6
A
A
A
A
A
A
A
A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A
A
A
A
A
A
A
A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A4
A5
5
5
4
A6
4
0
0
A
A6
A7
A8
A
3
16 383
16 383
3
A7
A8
25
25
24
21
23
2
24
A9
A10
A9
A10
21
23
A11
A12
A11
A12
A13
E
2
26
26
20
13
13
A13
20
E
•
•
[PWR DWN]
[PWR DWN]
&
&
22
G
22
27
EN
EN
G
27
PGM
PGM
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are J and N packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V
CC
PP
Supply voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V
+ 1 V
CC
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V
Operating free-air temperature range (’27C128-_ _JL and JL4, ’27PC128-_ _NL, and NL4
+ 1 V
CC
FML, and FML4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Operating free-air temperature range (’27C128-_ _JE and JE4, ’27PC128-_ _NE, NE4,
FME, and FME4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
recommended operating conditions
MIN
4.5
NOM
5
MAX
5.5
UNIT
Read mode (see Note 2)
V
CC
Supply voltage
V
SNAP! Pulse programming algorithm
6.25
6.5
6.75
Read mode
V
– 0.6
V
+ 0.6
CC
12.75
CC
13.25
+1
V
Supply voltage
V
V
PP
IH
IL
SNAP! Pulse programming algorithm
13
TTL
2
V
CC
V
V
High-level dc input voltage
Low-level dc input voltage
CMOS
TTL
V
–0.2
V
+1
CC
CC
–0.5
0.8
0.2
V
V
CMOS
–0.5
’27C128-_ _JL,JL4
’27PC128_ _NL,NL4
T
Operating free-air temperature
Operating free-air temperature
0
70
70
°C
°C
A
FML, FML4
’27C128-_ _JE,JE4
’27PC128_ _NE,NE4
T
A
–40
FME, FME4
NOTES: 2. V
mustbeappliedbeforeoratthesametimeasV andremovedafteroratthesametimeasV .Thedevicemustnotbeinserted
PP PP
CC
into or removed from the board when V
or V
is applied.
PP
CC
electrical characteristics over full ranges of operating conditions
†
PARAMETER
TEST CONDITIONS
= –2.5 mA
= –20 µA
MIN
3.5
–0.1
TYP
MAX
UNIT
V
I
I
I
I
OH
OH
OL
OL
V
V
High-level dc output voltage
OH
V
V
CC
= 2.1 mA
0.4
0.1
±1
V
Low-level dc output voltage
OL
= 20 µA
V
I
I
I
I
Input current (leakage)
Output current (leakage)
V = 0 to 5.5 V
µA
µA
µA
mA
µA
µA
I
I
V
V
V
V
V
V
= 0 to V
±1
O
O
CC
V
V
supply current
= V
= 5.5 V
1
35
10
PP1
PP2
PP
PP
PP
CC
CC
CC
= 13 V
supply current (during program pulse)
50
PP
TTL-input level
CMOS-input level
= 5.5 V, E = V
= 5.5 V, E = V
= 5.5 V, E = V
250
100
500
250
IH
I
V
supply current (standby)
supply current (active)
CC1
CC2
CC
CC
CC
,
IL
CC
I
V
t
= minimum cycle time,
15
30
mA
cycle
outputs open
†
Typical values are at T = 25°C and nominal voltages.
A
capacitance over recommended ranges of supply voltage and operating free-air
‡
temperature, f = 1 MHz
†
PARAMETER
Input capacitance
Output capacitance
TEST CONDITIONS
V = 0, f = 1 MHz
MIN TYP
MAX
10
UNIT
pF
C
C
6
i
I
V
O
= 0, f = 1 MHz
10
14
pF
O
†
Typical values are at T = 25°C and nominal voltages.
Capacitance measurements are made on sample basis only.
A
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
switchingcharacteristicsoverfullrangesofrecommendedoperatingconditions(seeNotes3and 4)
’27C128-12
’27C/PC128-15
TEST CONDITIONS
UNIT
PARAMETER
(SEE NOTES 3 AND 4)
MIN
MAX
MIN
MAX
150
t
t
t
Access time from address
Access time from chip enable
Output enable time from G
120
120
55
ns
ns
ns
a(A)
150
a(E)
C
= 100 pF,
L
75
60
1 Series 74 TTL Load,
Input t ≤ 20 ns,
en(G)
r
†
Output disable time from G or E, whichever occurs first
0
0
45
0
0
ns
ns
t
dis
Input t ≤ 20 ns
f
Output data valid time after change of address,
E, or G, whichever occurs first
t
v(A)
†
’27C/PC128-20 ′27C/PC128-25
TEST CONDITIONS
UNIT
(SEE NOTES 3 AND 4)
MIN
MAX
200
200
75
MIN
MAX
250
250
100
t
t
t
Access time from address
Access time from chip enable
Output enable time from G
ns
ns
ns
ns
a(A)
a(E)
C
= 100 pF,
L
1 Series 74 TTL Load,
Input t ≤ 20 ns,
en(G)
r
†
Output disable time from Go r E, whichever occurs first
0
0
60
0
0
60
t
t
dis
Input t ≤ 20 ns
f
Output data valid time after change of address, E, or G,
ns
v(A)
†
whichever occurs first
†
Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switchingcharacteristicsforprogramming:V =6.5VandV =13V(SNAP!Pulse),T =25°C(see
CC
PP
CC
A
Note 3)
PARAMETER
MIN NOM MAX
UNIT
ns
t
t
Output disable time from G
Output enable time from G
0
130
150
dis(G)
ns
en(G)
recommended timing requirements for programming: V
Pulse), T = 25°C (see Note 3)
= 6.5 V and V
=13 V (SNAP!
PP
A
MIN NOM MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
Initial program pulse duration SNAP! Pulse programming algorithm
95
2
100
105
w(IPGM)
Address setup time
E setup time
µs
su(A)
2
µs
su(E)
G setup time
2
µs
su(G)
Data setup time
2
µs
su(D)
V
V
setup time
setup time
2
µs
su(VPP)
su(VCC)
h(A)
PP
2
µs
CC
Address hold time
Data hold time
0
µs
2
µs
h(D)
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low (reference page 10).
4. Common test conditions apply for t
except during programming.
dis
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
C
= 800 Ω
L
Output
Under Test
= 100 pF
L
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4 V
0.4 V
2 V
2 V
0.8 V
0.8 V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
V
IH
A0–A13
Addresses Valid
V
IL
t
a(A)
V
IH
E
G
V
IL
t
a(E)
V
IH
V
IL
t
dis
t
en(G)
t
v(A)
V
OH
DQ0–DQ7
HI-Z
Output Valid
HI-Z
V
OL
Figure 3. Read Cycle Timing
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Verify
Program
V
V
IH
Address
N + 1
A0–A13
Address Stable
IL
t
t
su(A)
h(A)
V
/V
IH OH
Data Out
Valid
DQ0–DQ7
Data In Stable
V
/V
IL OL
†
t
t
dis(G)
su(D)
V
V
PP
V
PP
CC
t
su(VPP)
su(VCC)
‡
V
V
CC
V
CC
CC
t
V
V
IH
E
IL
t
h(D)
t
su(E)
V
V
IH
PGM
G
IL
t
su(G)
t
†
w(IPGM)
t
en(G)
V
V
IH
IL
†
t
and t
are characteristics of the device but must be accommodated by the programmer.
dis(G)
13-V V
en(G)
and 6.5-V V
for SNAP! Pulse programming.
CC
PP
Figure 4. Program Cycle Timing
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
device symbolization
This data sheet is applicable to all TI TMS27C128 CMOS EPROMs and TMS27PC128 PROMs with the data
sheet revision code “B” as shown below.
TI FML
TMS27PC128
TMS
27C128
B
L
X
P
YY WW
B
L
X
P
YY WW
Data Sheet Revision Code
Wafer Fab Code
Die Revision Code
Assembly Site Code
Year of Manufacture
Month of Manufacture
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS128E–OCTOBER 1984–REVISED JANUARY 1993
TYPICAL TMS27C/PC128 CHARACTERISTICS
STANDBY SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
STANDBY SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1.50
1.25
1.00
1.50
1.25
1.00
V
= 5 V
CC
T = 25 °C
A
0.75
0.50
0.75
0.50
–75 –50 –25
0
25 50 75 100 125
4.25
4.5
4.75
5
5.25
5.5
5.75
T — Free-Air Temperature — °C
V
CC
— Supply Voltage — V
A
ACTIVE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
ACTIVE SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1.50
1.25
1.00
1.50
1.25
1.00
V
= 5 V
CC
T = 25 °C
f = Max
A
0.75
0.50
0.75
0.50
–75 –50 –25
0
25 50 75 100 125
4.25
4.5
4.75
5
5.25
5.5
5.75
T — Free-Air Temperature — °C
V
— Supply Voltage — V
CC
A
ACCESS TIME
vs
FREE-AIR TEMPERATURE
ACCESS TIME
vs
SUPPLY VOLTAGE
1.50
1.25
1.00
1.50
1.25
1.00
V
= 5 V
CC
T = 25 °C
A
0.75
0.50
0.75
0.50
–75 –50 –25
0
25 50 75 100 125
4.25
4.5
4.75
— Supply Voltage — V
CC
5
5.25
5.5
5.75
T — Free-Air Temperature — °C
V
A
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
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