TMS27C210A-25JE [TI]
64KX16 UVPROM, 250ns, CDIP40, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-40;
| 型号： | TMS27C210A-25JE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 64KX16 UVPROM, 250ns, CDIP40, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-40 可编程只读存储器 电动程控只读存储器 CD 内存集成电路 |
| 文件： | 总29页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
J PACKAGE
(TOP VIEW)
D Organization . . . 65536 by 16 Bits
D Single 5-V Power Supply
V
V
CC
PGM
1
40
39
38
37
36
35
PP
E
D Operationally Compatible With Existing
2
Megabit EPROMs
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
NC
3
D 40-Pin Dual-In-Line Package and 44-Lead
A15
A14
A13
4
Plastic Leaded Chip Carrier
5
6
D All Inputs/Outputs Fully TTL Compatible
7
34 A12
33 A11
D 10% V
Tolerance
CC
8
D Maximum Access/Minimum Cycle Time
9
32
31
30
29
28
27
26
25
24
23
22
21
A10
A9
10
11
12
13
14
15
16
17
18
19
20
DQ8
’27C/PC210A-10 100 ns
’27C/PC210A-12 120 ns
’27C/PC210A-15 150 ns
’27C/PC210A-20 200 ns
’27C/PC210A-25 250 ns
†
†
GND
GND
A8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
G
A7
A6
A5
A4
D 16-Bit Output For Use in
A3
Microprocessor-Based Systems
A2
D Very High-Speed SNAP! Pulse
A1
Programming
A0
D Power-Saving CMOS Technology
FN PACKAGE
(TOP VIEW)
D 3-State Output Buffers
D 400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D Latchup Immunity of 250 mA on All Input
6
5
4
3
2 1 44 43 42 41 40
and Output Pins
7
A13
A12
A11
A10
A9
DQ12
DQ11
DQ10
DQ9
39
38
37
36
35
34
33
32
31
30
29
D No Pullup Resistors Required
8
9
D Low Power Dissipation
10
11
12
13
14
15
16
17
− Active . . . 275 mW Worst Case
− Standby . . . 0.55 mW Worst Case
(CMOS-Input Levels)
DQ8
†
†
GND
NC
A8
GND
NC
DQ7
DQ6
DQ5
DQ4
D Temperature Range Options
A7
A6
PIN NOMENCLATURE
A5
A0−A15
DQ0−DQ15
E
Address Inputs
Inputs (programming)/Outputs
Chip Enable
18 19 20 21 22 23 24 25 26 27 28
G
Output Enable
GND
NC
PGM
Ground
No Internal Connection
Program
V
CC
V
PP
5-V Power Supply
13-V Power Supply
‡
†
‡
Pins 11 and 30 (J package) and pins 12 and 34 (FN
package) must be connected externally to ground.
Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1997, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
description
The TMS27C210A series are 65536 by 16-bit (1048576-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC210A series are 65536 by 16-bit (1048576-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is offered with two choices of
temperature ranges, 0°C to 70°C (JL suffix) and − 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC210A OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC210A is offered with two choices of temperature ranges,
0°C to 70°C (FNL suffix) and −40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE
RANGES
0°C to 70°C
− 40°C to 85°C
TMS27C210A-xx
TMS27PC210A-xx
JL
JE
FNL
FNE
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), they are ideal for use
in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation for the TMS27C210A and TMS27PC210A are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for V during programming (13 V), and 12 V on
PP
A9 for signature mode.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
Table 2. Operation Modes
†
MODE
FUNCTION
OUTPUT
DISABLE
PROGRAM
INHIBIT
READ
STANDBY
PROGRAMMING
VERIFY
SIGNATURE MODE
E
G
V
V
V
V
V
V
V
V
V
V
IL
IL
IH
IL
IL
IH
IL
V
IH
X
V
IH
X
X
IL
IL
IL
PGM
X
X
X
V
IL
V
IH
X
V
V
V
V
V
V
V
V
V
V
V
V
PP
CC
CC
CC
PP
PP
PP
CC
V
CC
V
CC
X
V
CC
X
V
CC
X
CC
X
CC
X
CC
X
CC
A9
A0
V ‡
V ‡
H
H
X
X
X
X
X
X
V
IL
V
IH
CODE
MFG
97
DEVICE
AB
DQ0−DQ15
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
†
‡
X can be V or V
IL IH
H
.
V
= 12 V 0.5 V.
read/output disable
When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, “Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family”, available through TI Sales Offices.
power down
Active I
supply current can be reduced from 50 mA to 500 µA by applying a high TTL input on E and to
CC
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C210A)
Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
2
2
exposure time) is 15-W•s/cm . A typical 12-mW/cm , filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the
window should be covered with an opaque label.
initializing (TMS27PC210A)
The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed
into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
SNAP! Pulse programming
The TMS27C210A and TMS27PC210A are programmed using the TI SNAP! Pulse programming algorithm
(shown in the flow chart in Figure 1), which can program in a nominal time of seven seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V = 13 V, V = 6.5 V, E = V , G = V . Data is presented in parallel
PP
CC
IL
IH
(16 bits) on pins DQ0 through DQ15. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
V
= V = 5 V 10%.
CC
PP
program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits can be verified with V = 13 V when G = V , E = V , and PGM = V
IH.
PP
IL
IL
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. DQ0−DQ7 contain the
valid codes. All other addresses must be held low. The signature code for these devices is 97AB. A0 low selects
the manufacturer’s code 97 (Hex), and A0 high selects the device code AB (Hex), as shown in Table 3.
Table 3. Signature Mode
PINS
†
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
97
Manufacturer Code
Device Code
V
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
1
IL
V
IH
AB
†
E = G = V , A9 = V , A1−A8 = V , A10−A15 = V , V
IL IL IL PP
= V , PGM = V or V .
CC IH IL
H
4
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
Start
Address = First Location
Program
Mode
V
CC
= 6.5 V 0.25 V, V = 13 V 0.25 V
PP
Program One Pulse = t = 100 µs
Increment Address
w
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t = 100 µs
w
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
Device Failed
V
CC
= V = 5 V 0.5 V
PP
Compare
All Bytes
to Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
†
logic symbol
EPROM 65 536 × 16
21
A0
A1
0
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
19
18
17
16
15
14
13
12
10
9
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A2
A3
A4
A5
A6
A7
0
A
A8
65 535
A9
A10
A11
A12
A13
A14
A15
8
7
6
5
4
15
3
2
E
[PWR DWN]
&
20
G
EN
†
This symbol is in accordance with ANSI/IEEE Std 91−1984 and IEC Publication 617−12.
6
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 14 V
CC
PP
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V
+ 1 V
CC
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V + 1 V
CC
Operating free-air temperature range (’27C210A-_ _JL, ’27PC210A-_ _FNL) . . . . . . . . . . . . . . 0° C to 70°C
Operating free-air temperature range (’27C210A-_ _JE, ’27PC210A-_ _FNE) . . . . . . . . . . . . − 40° C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
TMS27C/PC210A-10
TMS27C/PC210A-12
TMS27C/PC210A-15
TMS27C/PC210A-20
TMS27C/PC210A-25
UNIT
MIN
NOM
5
MAX
Read mode (see Note 2)
4.5
5.5
V
V
V
V
Supply voltage
V
V
V
CC
PP
IH
SNAP! Pulse programming algorithm
6.25
6.5
6.75
Read mode
V
−0.6
V
V
+0.6
CC
13.25
CC
CC
13
Supply voltage
SNAP! Pulse programming algorithm
12.75
2
TTL
V
+0.5
CC
High-level dc input voltage
CMOS
TTL
V
− 0.2
CC
− 0.5
V
+0.5
CC
0.8
Low-level dc input voltage
V
IL
CMOS
− 0.5
GND+0.2
’27C210A-_ _JL
’27PC210A-_ _FNL
T
Operating free-air temperature
Operating free-air temperature
0
70
°C
°C
A
’27C210A-_ _JE,
’27PC210A-_ _FNE
T
A
− 40
85
NOTE 2:
V
must be applied before or at the same time as V
PP
and removed after or at the same time as V . The device must not be inserted
PP
CC
into or removed from the board when V
or V
CC
is applied.
PP
7
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ꢌ
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ꢎ
ꢌ
ꢏ
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
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ꢒ
ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of operating conditions
PARAMETER
TEST CONDITIONS
= − 20 µA
MIN
− 0.2
MAX
UNIT
I
I
I
I
V
OH
OH
OL
OL
CC
2.4
V
V
High-level dc output voltage
V
OH
= − 2 mA
= 2.1 mA
0.4
0.1
1
Low-level dc output voltage
V
OL
= 20 µA
I
I
I
I
Input current (leakage)
Output current (leakage)
V = 0 V to 5.5 V
µA
µA
µA
mA
I
I
V
V
V
V
V
V
= 0 V to V
CC
1
O
O
V
V
supply current
= V
CC
= 13 V
= 5.5 V
10
50
500
100
PP1
PP2
PP
PP
PP
PP
CC
CC
supply current (during program pulse)
TTL-input level
= 5.5 V,
= 5.5 V,
= 5.5 V,
E = V
E = V
E = V
IH
I
V
supply current (standby)
supply current (active)
µA
CC1
CC2
CC
CC
CMOS-input level
CC
,
CC
IL
I
V
t
= minimum cycle time,
outputs open
50
mA
cycle
†
†
Minimum cycle time = maximum address access time.
capacitance over recommended ranges of supply voltage and operating free-air
‡
temperature, f = 1 MHz
§
PARAMETER
Input capacitance
Output capacitance
TEST CONDITIONS
V = 0 V, f = 1 MHz
MIN TYP
MAX
12
UNIT
pF
C
C
8
I
I
V
O
= 0 V, f = 1 MHz
12
15
pF
O
‡
§
Capacitance measurements are made on a sample basis only.
Typical values are at T = 25°C and nominal voltages.
A
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
’27C210A-10
’27C210A-12
’27C210A-15
’27C210A-20
’27C210A-25
TEST
CONDITIONS
’27PC210A-10 ’27PC210A-12 ’27PC210A-15 ’27PC210A-20 ’27PC210A-25
PARAMETER
UNIT
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time from
address
t
t
t
100
120
150
200
250
ns
ns
ns
a(A)
Access time from
chip enable
100
55
120
55
150
75
200
75
250
100
a(E)
Output enable
time from G
en(G)
CL = 100 pF,
1 Series 74
TTL load,
Output disable
time from G or E,
whichever occurs
Input t ≤ 20 ns,
t
0
0
50
0
0
50
0
0
60
0
0
60
0
0
60
ns
ns
r
dis
Input t ≤ 20 ns
f
¶
first
Output data valid
time after change
of address, E, or
G, whichever
t
v(A)
¶
occurs first
¶
Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for t
dis
except during programming.
8
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ꢓ
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ꢒ
ꢈ
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ꢏ
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
switching characteristics for programming: V
(see Note 3)
= 6.5 V and V = 13 V (SNAP! Pulse), T = 25°C
PP
CC
A
PARAMETER
MIN MAX
100
150
UNIT
ns
t
t
Output disable time from G
Output enable time from G
0
dis(G)
ns
en(G)
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).
timing requirements for programming
MIN NOM MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
Pulse duration, program
Setup time, address
Setup time, E
SNAP! Pulse programming algorithm
95
2
100
105
w(PGM)
µs
su(A)
2
µs
su(E)
Setup time, G
2
µs
su(G)
su(D)
Setup time, data
2
µs
Setup time, V
Setup time, V
2
µs
su(VPP)
su(VCC)
h(A)
PP
2
µs
CC
Hold time, address
Hold time, data
0
µs
2
µs
h(D)
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).
9
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
ꢑ
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ꢈ
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ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
C
= 800 Ω
L
L
Output
Under Test
= 100 pF
(see Note A)
2.4 V
0.4 V
2 V
2 V
0.8 V
0.8 V
NOTES: A.
C includes probe and fixture capacitance.
L
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.
Figure 2. The ac Testing Output Load Circuit and ac Waveform
V
V
IH
A0−A15
Addresses Valid
IL
V
V
IH
E
IL
t
a(E)
t
V
V
IH
G
IL
t
dis
en(G)
t
v(A)
t
a(A)
V
V
OH
DQ0−DQ15
Output Valid
Hi-Z
Hi-Z
OL
Figure 3. Read-Cycle Timing
10
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢆ
ꢈ
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ꢌ
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ꢏ
ꢒ
ꢀ
ꢃ
ꢆ
ꢊ
ꢊ
ꢎꢌ
ꢕ
ꢓ
ꢖ
ꢗ
ꢓ
ꢈ
ꢁ
ꢁ
ꢈ
ꢌ
ꢔ
ꢒ
ꢓ
ꢒ
ꢈ
ꢘ
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ꢁ
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ꢏ
ꢒꢂ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
PROGRAMMING INFORMATION
Verify
Program
V
V
IH
Address
N + 1
A0−A15
Address Stable
IL
t
t
su(A)
h(A)
V
/V
IH OH
Data-Out
Valid
DQ0−DQ15
Data-In Stable
V /V
IL OL
†
t
t
dis(G)
su(D)
‡
V
V
PP
V
PP
CC
t
t
su(VPP)
su(VCC)
‡
V
V
CC
V
CC
CC
V
V
IH
E
IL
t
h(D)
t
su(E)
V
V
IH
PGM
G
IL
t
su(G)
t
†
w(PGM)
t
en(G)
V
V
IH
IL
†
‡
t
and t
are characteristics of the device but must be accommodated by the programmer.
dis(G)
13-V V
en(G)
and 6.5-V V
CC
for SNAP! Pulse programming.
PP
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ
ꢎ
ꢌ
ꢏ
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
ꢑ
ꢒ
ꢓ
ꢈ
ꢂ
ꢈ
ꢌ
ꢂ
ꢔ
ꢒ
ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
0.350 (8,89)
MAX
MIN
MAX
0.395 (10,03)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
12
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ꢀ
ꢃ
ꢆ
ꢊ
ꢊ
ꢎꢌ
ꢕ
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ꢓ
ꢈ
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ꢁ
ꢈ
ꢌ
ꢔ
ꢒ
ꢓ
ꢒ
ꢈ
ꢘ
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ꢁ
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
A
0.140 (3,56)
0.018 (0,46) MIN
Seating Plane
0°−ā10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
PINS**
DIM
24
28
32
40
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
A
MIN
MAX
B
MIN
MAX
C
MIN
4040084/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
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ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
J PACKAGE
(TOP VIEW)
D Organization . . . 65536 by 16 Bits
D Single 5-V Power Supply
V
V
CC
PGM
1
40
39
38
37
36
35
PP
E
D Operationally Compatible With Existing
2
Megabit EPROMs
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
NC
3
D 40-Pin Dual-In-Line Package and 44-Lead
A15
A14
A13
4
Plastic Leaded Chip Carrier
5
6
D All Inputs/Outputs Fully TTL Compatible
7
34 A12
33 A11
D 10% V
Tolerance
CC
8
D Maximum Access/Minimum Cycle Time
9
32
31
30
29
28
27
26
25
24
23
22
21
A10
A9
10
11
12
13
14
15
16
17
18
19
20
DQ8
’27C/PC210A-10 100 ns
’27C/PC210A-12 120 ns
’27C/PC210A-15 150 ns
’27C/PC210A-20 200 ns
’27C/PC210A-25 250 ns
†
†
GND
GND
A8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
G
A7
A6
A5
A4
D 16-Bit Output For Use in
A3
Microprocessor-Based Systems
A2
D Very High-Speed SNAP! Pulse
A1
Programming
A0
D Power-Saving CMOS Technology
FN PACKAGE
(TOP VIEW)
D 3-State Output Buffers
D 400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D Latchup Immunity of 250 mA on All Input
6
5
4
3
2 1 44 43 42 41 40
and Output Pins
7
A13
A12
A11
A10
A9
DQ12
DQ11
DQ10
DQ9
39
38
37
36
35
34
33
32
31
30
29
D No Pullup Resistors Required
8
9
D Low Power Dissipation
10
11
12
13
14
15
16
17
− Active . . . 275 mW Worst Case
− Standby . . . 0.55 mW Worst Case
(CMOS-Input Levels)
DQ8
†
†
GND
NC
A8
GND
NC
DQ7
DQ6
DQ5
DQ4
D Temperature Range Options
A7
A6
PIN NOMENCLATURE
A5
A0−A15
DQ0−DQ15
E
Address Inputs
Inputs (programming)/Outputs
Chip Enable
18 19 20 21 22 23 24 25 26 27 28
G
Output Enable
GND
NC
PGM
Ground
No Internal Connection
Program
V
CC
V
PP
5-V Power Supply
13-V Power Supply
‡
†
‡
Pins 11 and 30 (J package) and pins 12 and 34 (FN
package) must be connected externally to ground.
Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1997, Texas Instruments Incorporated
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ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ
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15
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
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ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
description
The TMS27C210A series are 65536 by 16-bit (1048576-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC210A series are 65536 by 16-bit (1048576-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C210A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C210A is offered with two choices of
temperature ranges, 0°C to 70°C (JL suffix) and − 40°C to 85°C (JE suffix). See Table 1.
The TMS27PC210A OTP PROM is offered in a 44-pin plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC210A is offered with two choices of temperature ranges,
0°C to 70°C (FNL suffix) and −40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
EPROM
AND
OTP PROM
SUFFIX FOR OPERATING
FREE-AIR TEMPERATURE
RANGES
0°C to 70°C
− 40°C to 85°C
TMS27C210A-xx
TMS27PC210A-xx
JL
JE
FNL
FNE
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), they are ideal for use
in microprocessor based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation for the TMS27C210A and TMS27PC210A are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for V during programming (13 V), and 12 V on
PP
A9 for signature mode.
16
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
Table 2. Operation Modes
†
MODE
FUNCTION
OUTPUT
DISABLE
PROGRAM
INHIBIT
READ
STANDBY
PROGRAMMING
VERIFY
SIGNATURE MODE
E
G
V
V
V
V
V
V
V
V
V
V
IL
IL
IH
IL
IL
IH
IL
V
IH
X
V
IH
X
X
IL
IL
IL
PGM
X
X
X
V
IL
V
IH
X
V
V
V
V
V
V
V
V
V
V
V
V
PP
CC
CC
CC
PP
PP
PP
CC
V
CC
V
CC
X
V
CC
X
V
CC
X
CC
X
CC
X
CC
X
CC
A9
A0
V ‡
V ‡
H
H
X
X
X
X
X
X
V
IL
V
IH
CODE
MFG
97
DEVICE
AB
DQ0−DQ15
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
†
‡
X can be V or V
IL IH
H
.
V
= 12 V 0.5 V.
read/output disable
When the outputs of two or more TMS27C210As or TMS27PC210As are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit must have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C210A and TMS27PC210A is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
For more information see application report SMLA001, “Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family”, available through TI Sales Offices.
power down
Active I
supply current can be reduced from 50 mA to 500 µA by applying a high TTL input on E and to
CC
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C210A)
Before programming, the TMS27C210A is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
2
2
exposure time) is 15-W•s/cm . A typical 12-mW/cm , filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state.
Normal ambient light contains the correct wavelength for erasure; therefore, when using the TMS27C210A the
window should be covered with an opaque label.
initializing (TMS27PC210A)
The OTP TMS27PC210A PROM is provided with all bits in the logic high state then logic lows are programmed
into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
17
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
SNAP! Pulse programming
The TMS27C210A and TMS27PC210A are programmed using the TI SNAP! Pulse programming algorithm
(shown in the flow chart in Figure 1), which can program in a nominal time of seven seconds. Actual
programming time varies as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V = 13 V, V = 6.5 V, E = V , G = V . Data is presented in parallel
PP
CC
IL
IH
(16 bits) on pins DQ0 through DQ15. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
V
= V = 5 V 10%.
CC
PP
program inhibit
Programming can be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits can be verified with V = 13 V when G = V , E = V , and PGM = V
IH.
PP
IL
IL
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. DQ0−DQ7 contain the
valid codes. All other addresses must be held low. The signature code for these devices is 97AB. A0 low selects
the manufacturer’s code 97 (Hex), and A0 high selects the device code AB (Hex), as shown in Table 3.
Table 3. Signature Mode
PINS
†
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
97
Manufacturer Code
Device Code
V
1
1
0
0
0
1
1
0
0
1
1
0
1
1
1
1
IL
V
IH
AB
†
E = G = V , A9 = V , A1−A8 = V , A10−A15 = V , V
IL IL IL PP
= V , PGM = V or V .
CC IH IL
H
18
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
Start
Address = First Location
Program
Mode
V
CC
= 6.5 V 0.25 V, V = 13 V 0.25 V
PP
Program One Pulse = t = 100 µs
Increment Address
w
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t = 100 µs
w
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
Device Failed
V
CC
= V = 5 V 0.5 V
PP
Compare
All Bytes
to Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
19
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ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
†
logic symbol
EPROM 65 536 × 16
21
A0
A1
0
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
19
18
17
16
15
14
13
12
10
9
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A2
A3
A4
A5
A6
A7
0
A
A8
65 535
A9
A10
A11
A12
A13
A14
A15
8
7
6
5
4
15
3
2
E
[PWR DWN]
&
20
G
EN
†
This symbol is in accordance with ANSI/IEEE Std 91−1984 and IEC Publication 617−12.
20
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ꢊ
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 14 V
CC
PP
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V
+ 1 V
CC
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V + 1 V
CC
Operating free-air temperature range (’27C210A-_ _JL, ’27PC210A-_ _FNL) . . . . . . . . . . . . . . 0° C to 70°C
Operating free-air temperature range (’27C210A-_ _JE, ’27PC210A-_ _FNE) . . . . . . . . . . . . − 40° C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
TMS27C/PC210A-10
TMS27C/PC210A-12
TMS27C/PC210A-15
TMS27C/PC210A-20
TMS27C/PC210A-25
UNIT
MIN
NOM
5
MAX
Read mode (see Note 2)
4.5
5.5
V
V
V
V
Supply voltage
V
V
V
CC
PP
IH
SNAP! Pulse programming algorithm
6.25
6.5
6.75
Read mode
V
−0.6
V
V
+0.6
CC
13.25
CC
CC
13
Supply voltage
SNAP! Pulse programming algorithm
12.75
2
TTL
V
+0.5
CC
High-level dc input voltage
CMOS
TTL
V
− 0.2
CC
− 0.5
V
+0.5
CC
0.8
Low-level dc input voltage
V
IL
CMOS
− 0.5
GND+0.2
’27C210A-_ _JL
’27PC210A-_ _FNL
T
Operating free-air temperature
Operating free-air temperature
0
70
°C
°C
A
’27C210A-_ _JE,
’27PC210A-_ _FNE
T
A
− 40
85
NOTE 2:
V
must be applied before or at the same time as V
PP
and removed after or at the same time as V . The device must not be inserted
PP
CC
into or removed from the board when V
or V
CC
is applied.
PP
21
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
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ꢈ
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ꢒ
ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of operating conditions
PARAMETER
TEST CONDITIONS
= − 20 µA
MIN
− 0.2
MAX
UNIT
I
I
I
I
V
OH
OH
OL
OL
CC
2.4
V
V
High-level dc output voltage
V
OH
= − 2 mA
= 2.1 mA
0.4
0.1
1
Low-level dc output voltage
V
OL
= 20 µA
I
I
I
I
Input current (leakage)
Output current (leakage)
V = 0 V to 5.5 V
µA
µA
µA
mA
I
I
V
V
V
V
V
V
= 0 V to V
CC
1
O
O
V
V
supply current
= V
CC
= 13 V
= 5.5 V
10
50
500
100
PP1
PP2
PP
PP
PP
PP
CC
CC
supply current (during program pulse)
TTL-input level
= 5.5 V,
= 5.5 V,
= 5.5 V,
E = V
E = V
E = V
IH
I
V
supply current (standby)
supply current (active)
µA
CC1
CC2
CC
CC
CMOS-input level
CC
,
CC
IL
I
V
t
= minimum cycle time,
outputs open
50
mA
cycle
†
†
Minimum cycle time = maximum address access time.
capacitance over recommended ranges of supply voltage and operating free-air
‡
temperature, f = 1 MHz
§
PARAMETER
Input capacitance
Output capacitance
TEST CONDITIONS
V = 0 V, f = 1 MHz
MIN TYP
MAX
12
UNIT
pF
C
C
8
I
I
V
O
= 0 V, f = 1 MHz
12
15
pF
O
‡
§
Capacitance measurements are made on a sample basis only.
Typical values are at T = 25°C and nominal voltages.
A
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
’27C210A-10
’27C210A-12
’27C210A-15
’27C210A-20
’27C210A-25
TEST
CONDITIONS
’27PC210A-10 ’27PC210A-12 ’27PC210A-15 ’27PC210A-20 ’27PC210A-25
PARAMETER
UNIT
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time from
address
t
t
t
100
120
150
200
250
ns
ns
ns
a(A)
Access time from
chip enable
100
55
120
55
150
75
200
75
250
100
a(E)
Output enable
time from G
en(G)
CL = 100 pF,
1 Series 74
TTL load,
Output disable
time from G or E,
whichever occurs
Input t ≤ 20 ns,
t
0
0
50
0
0
50
0
0
60
0
0
60
0
0
60
ns
ns
r
dis
Input t ≤ 20 ns
f
¶
first
Output data valid
time after change
of address, E, or
G, whichever
t
v(A)
¶
occurs first
¶
Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for t
dis
except during programming.
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ꢏ
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ꢓ
ꢌ
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ꢍ
ꢂ
ꢆ
ꢈ
ꢉ
ꢌ
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ꢏ
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ꢀ
ꢃ
ꢆ
ꢊ
ꢊ
ꢎꢌ
ꢕ
ꢓ
ꢖ
ꢗ
ꢓ
ꢈ
ꢁ
ꢁ
ꢈ
ꢌ
ꢔ
ꢒ
ꢓ
ꢒ
ꢈ
ꢘ
ꢎ
ꢖ
ꢙ
ꢔꢍ
ꢁ
ꢒ
ꢁ
ꢖ
ꢓ
ꢏ
ꢒꢂ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
switching characteristics for programming: V
(see Note 3)
= 6.5 V and V = 13 V (SNAP! Pulse), T = 25°C
PP
CC
A
PARAMETER
MIN MAX
100
150
UNIT
ns
t
t
Output disable time from G
Output enable time from G
0
dis(G)
ns
en(G)
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).
timing requirements for programming
MIN NOM MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
Pulse duration, program
Setup time, address
Setup time, E
SNAP! Pulse programming algorithm
95
2
100
105
w(PGM)
µs
su(A)
2
µs
su(E)
Setup time, G
2
µs
su(G)
su(D)
Setup time, data
2
µs
Setup time, V
Setup time, V
2
µs
su(VPP)
su(VCC)
h(A)
PP
2
µs
CC
Hold time, address
Hold time, data
0
µs
2
µs
h(D)
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (See Figure 2).
23
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
ꢑ
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ꢈ
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ꢌ
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ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
C
= 800 Ω
L
L
Output
Under Test
= 100 pF
(see Note A)
2.4 V
0.4 V
2 V
2 V
0.8 V
0.8 V
NOTES: A.
C includes probe and fixture capacitance.
L
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.
Figure 2. The ac Testing Output Load Circuit and ac Waveform
V
V
IH
A0−A15
Addresses Valid
IL
V
V
IH
E
IL
t
a(E)
t
V
V
IH
G
IL
t
dis
en(G)
t
v(A)
t
a(A)
V
V
OH
DQ0−DQ15
Output Valid
Hi-Z
Hi-Z
OL
Figure 3. Read-Cycle Timing
24
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ꢆ
ꢈ
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ꢌ
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ꢀ
ꢃ
ꢆ
ꢊ
ꢊ
ꢎꢌ
ꢕ
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ꢖ
ꢗ
ꢓ
ꢈ
ꢁ
ꢁ
ꢈ
ꢌ
ꢔ
ꢒ
ꢓ
ꢒ
ꢈ
ꢘ
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ꢁ
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
PROGRAMMING INFORMATION
Verify
Program
V
V
IH
Address
N + 1
A0−A15
Address Stable
IL
t
t
su(A)
h(A)
V
/V
IH OH
Data-Out
Valid
DQ0−DQ15
Data-In Stable
V /V
IL OL
†
t
t
dis(G)
su(D)
‡
V
V
PP
V
PP
CC
t
t
su(VPP)
su(VCC)
‡
V
V
CC
V
CC
CC
V
V
IH
E
IL
t
h(D)
t
su(E)
V
V
IH
PGM
G
IL
t
su(G)
t
†
w(PGM)
t
en(G)
V
V
IH
IL
†
‡
t
and t
are characteristics of the device but must be accommodated by the programmer.
dis(G)
13-V V
en(G)
and 6.5-V V
CC
for SNAP! Pulse programming.
PP
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
25
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ꢉ
ꢎ
ꢌ
ꢏ
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
ꢑ
ꢒ
ꢓ
ꢈ
ꢂ
ꢈ
ꢌ
ꢂ
ꢔ
ꢒ
ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
0.350 (8,89)
MAX
MIN
MAX
0.395 (10,03)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
26
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ꢆ
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SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
A
0.140 (3,56)
0.018 (0,46) MIN
Seating Plane
0°−ā10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
PINS**
DIM
24
28
32
40
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
A
MIN
MAX
B
MIN
MAX
C
MIN
4040084/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
27
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ꢀ ꢁ ꢂ ꢃ ꢄꢕ ꢅꢃ ꢆꢇꢈ ꢉ ꢊ ꢊ ꢋ ꢉ ꢌꢍ ꢆ ꢉ ꢎꢌꢏ ꢀ
ꢐ
ꢑ
ꢒ
ꢓ
ꢈ
ꢂ
ꢈ
ꢌ
ꢂ
ꢔ
ꢒ
ꢕ ꢓꢖꢗꢓ ꢈ ꢁꢁ ꢈ ꢌꢔ ꢒ ꢓꢒ ꢈꢘ ꢎꢖꢙ ꢔꢍ ꢁꢒ ꢁꢖ ꢓꢏ ꢒ
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
28
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IMPORTANT NOTICE
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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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