TMS27C512-100JL4 [TI]

64KX8 UVPROM, 100ns, CDIP28, 0.600 INCH, WINDOWED, CERAMIC, DIP-28;


型号：	TMS27C512-100JL4
厂家：	TEXAS INSTRUMENTS
描述：	64KX8 UVPROM, 100ns, CDIP28, 0.600 INCH, WINDOWED, CERAMIC, DIP-28 可编程只读存储器电动程控只读存储器 CD 内存集成电路
文件：	总13页 (文件大小：182K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

J PACKAGE

(TOP VIEW)

Organization . . . 65536 by 8 Bits

Single 5-V Power Supply

Pin Compatible With Existing 512K MOS

ROMs, PROMs, and EPROMs

A15

A12

A14

A13

All Inputs/Outputs Fully TTL Compatible

Max Access/Min Cycle Time

± 10%

A11

G/V

A10

DQ7

DQ6

DQ5

DQ4

DQ3

’27C/PC512-10

’27C/PC512-12

’27C/PC512-15

’27C/PC512-20

’27C/PC512-25

100 ns

120 ns

150 ns

200 ns

250 ns

DQ0

DQ1

DQ2

GND

Power Saving CMOS Technology

Very High-Speed SNAP! Pulse

Programming

3-State Output Buffers

400-mV Minimum DC Noise Immunity With

Standard TTL Loads

FM PACKAGE

(TOP VIEW)

Latchup Immunity of 250 mA on All Input

and Output Lines

Low Power Dissipation ( V

= 5.25 V )

3 2 1 32 31 30

– Active . . . 158 mW Worst Case

– Standby . . . 1.4 mW Worst Case

(CMOS Input Levels)

DQ0

A11

Temperature Range Options

26 NC

512K EPROM Available With MIL-STD-883C

Class B High Reliability Processing

(SMJ27C512)

G/V

A10

DQ7

DQ6

description

14 15 16 17 18 19 20

The TMS27C512 series are 65536 by 8-bit

(524288-bit), ultraviolet (UV) light erasable,

electrically programmable read-only memories

(EPROMs).

PIN NOMENCLATURE

The TMS27PC512 series are 65536 by 8-bit

(524288-bit), one-time programmable (OTP)

electrically programmable read-only memories

(PROMs).

A0–A15

Address Inputs

Chip Enable/Power Down

DQ0–DQ7

Inputs (programming)/Outputs

13-V Programming Power Supply

Ground

G/V

GND

No Internal Connection

Make No External Connection

5-V Power Supply

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

description (continued)

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with

MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits

without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external

resistors.

The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C512 and the

TMS27PC512 are pin compatible with 28-pin 512K MOS ROMs, PROMs, and EPROMs.

The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in

mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is supplied in a 32-lead

plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).

The TMS27C512 and TMS27PC512 are offered with two choices of temperature ranges of 0°C to 70°C (JL and

FML suffix) and – 40°C to 85°C (JE and FME suffix). See Table 1.

All package styles conform to JEDEC standards.

Table 1. Temperature Range Suffixes

SUFFIX FOR OPERATING

FREE-AIR TEMPERATURE RANGES

EPROM

AND

OTP PROM

0°C TO 70°C

– 40°C TO 85°C

TMS27C512-xxx

TMS27PC512-xxx

FML

FME

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use

in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals

are TTL level. The device is programmed using the SNAP! Pulse programming algorithm. The SNAP! Pulse

programmingalgorithmusesaV of13VandaV of6.5Vforanominalprogrammingtimeofsevenseconds.

For programming outside the system, existing EPROM programmers can be used. Locations can be

programmed singly, in blocks, or at random.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

operation

The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are

TTL level except for V during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature mode.

Table 2. Operation Modes

†

MODE

FUNCTION

OUTPUT

DISABLE

PROGRAM

INHIBIT

SIGNATURE

MODE

READ

STANDBY PROGRAMMING

VERIFY

G/V

‡

CODE

DQ0–DQ7

Data Out

Hi-Z

Data In

Data Out

Hi-Z

MFG

DEVICE

†

‡

X can be V or V

= 12 V ± 0.5 V.

read/output disable

When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus,

the output of any particular device in the circuit can be read with no interference from the competing outputs

of the other devices. To read the output of a single device, a low-level signal is applied to the E and G/V pins.

All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these

pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs.

This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices

are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup

without compromising performance or packing density.

power down

Active I

supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level

inputs) by applying a high TTL/CMOS signal to the E pin. In this mode all outputs are in the high-impedance

state.

erasure (TMS27C512)

Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid

to a high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is

necessarytoassurethatallbitsareinthelogichighstate. Logiclowsareprogrammedintothedesiredlocations.

A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose

(UV intensity × exposure time) is 15-W s/cm . A typical 12-mW/cm , filterless UV lamp erases the device in

21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that

normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C512, the

window should be covered with an opaque label.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

initializing (TMS27PC512)

The one-time programmable TMS27PC512 PROM is provided with all bits in the logic high state, then logic lows

are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.

SNAP! Pulse programming

The 512K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm

illustrated by the flowchart in Figure 1, which programs in a nominal time of seven seconds. Actual programming

time varies as a function of the programmer used.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte

verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs

pulses per byte are provided before a failure is recognized.

The programming mode is achieved with G/V = 13 V, V

(eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.

= 6.5 V, and E = V . Data is presented in parallel

More than one device can be programmed when the devices are connected in parallel. Locations can be

programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with

= 5 V, G/V = V and E = V .

PP IL, IL

program inhibit

Programming can be inhibited by maintaining a high level input on the E pin.

program verify

Programmed bits can be verified when G/V and E = V .

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is

activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must

be held low. the signature code for these devices is 9785. A0 selects the manufacturer’s code 97 (Hex), and

A0 high selects the device code 85, as shown in Table 3.

Table 3. Signature Mode

PINS

†

IDENTIFIER

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

HEX

Manufacturer Code

Device Code

†

E = G = V , A9 = V , A1–A8 = V , A10–A15 = V , PGM = V or V

IL IL IL IH

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

Start

Address = First Location

Program

Mode

= 6.5 V ± 0.25 V, G/V = 13 V ± 0.25 V

Program One Pulse = t = 100 µs

Increment Address

Last

Address

Yes

Address = First Location

X = 0

Program One Pulse = t = 100 µs

Fail

Increment

Address

Verify

One Byte

X = X + 1

X = 10?

Interactive

Mode

Pass

Last

Address

Yes

Device Failed

= 5 V ± 0.5 V, G/V

= V

PP IL

Compare

All Bytes

To Original

Data

Fail

Final

Verification

Pass

Device Passed

Figure 1. SNAP! Pulse Programming Flow Chart

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

†

logic symbols

EPROM

65 536 × 8

OTP PROM

65 536 × 8

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

65 535

A10

A11

A12

A13

A14

A15

A10

A11

A12

A13

A14

A15

[PWR DWN]

G/V

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the J package.

‡

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V

+ 1 V

A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 13.5 V

Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V + 1 V

Operating free-air temperature range (’27C512-_ _JL, ’27PC512-_ _FML)T . . . . . . . . . . . . . . . 0°C to 70°C

Operating free-air temperature range (’27C512-_ _JE, ’27PC512-_ _FME)T . . . . . . . . . . . . –40°C to 85°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

recommended operating conditions

MIN

4.5

NOM

MAX

5.5

UNIT

Read mode (see Note 2)

Supply voltage

SNAP! Pulse programming algorithm

6.25

12.75

6.5

6.75

13.25

G/V

Supply voltage

SNAP! Pulse programming algorithm

TTL

High-level dc input voltage

CMOS

TTL

– 0.2

– 0.5

0.8

0.2

Low-level dc input voltage

CMOS

– 0.5

Operating free-air

temperature

TMS27C512-_ _JL

TMS27PC512-_ _FML

°C

Operating free-air

temperature

TMS27C512-_ _JE

TMS27PC512-_ _FME

– 40

NOTE 2:

must be applied before or at the same time as G/V

and removed after or at the same time as G/V . The device must not be

is applied.

inserted into or removed from the board when V

or V

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature

†

TYP

PARAMETER

TEST CONDITIONS

= – 2.5 mA

MIN

MAX

UNIT

3.5

High-level dc output voltage

= – 20 µA

– 0.1

= 2.1 mA

0.4

0.1

±1

Low-level dc output voltage

= 20 µA

Input current (leakage)

Output current (leakage)

V = 0 V to 5.5 V

µA

= 0 V to V

O CC

±1

G/V

supply current (during program pulse)

TTL-input level

G/V

= 13 V

250

100

= 5.5 V, . . . . . E = V

500

250

supply current (standby)

µA

CC1

CC2

CMOS-input level

= 5.5 V,

= minimum cycle time,

E = V ,

supply current (active)

cycle

outputs open

†

Typical values are at T = 25°C and nominal voltages.

capacitance over recommended ranges of supply voltage and operating free-air

†

temperature, f = 1 MHz

‡

PARAMETER

Input capacitance

Output capacitance

G/V input capacitance

TEST CONDITIONS

MIN TYP

MAX

UNIT

V = 0 V,

f = 1 MHz

= 0 V,

G/V

= 0 V, f = 1 MHz

G/VPP

†

‡

Capacitance measurements are made on a sample basis only.

Typical values are at T = 25°C and nominal voltages.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

switching characteristics over recommended ranges of operating conditions

’27C512-10

’27PC512-10

’27C512-12

’27PC512-12

TEST CONDITIONS

(SEE NOTES 3 AND 4)

PARAMETER

UNIT

MIN

MAX

100

MIN

MAX

120

Access time from address

Access time from chip enable

Output enable time from G/V

a(A)

a(E)

en(G)

dis

= 100 pF,

1 Series 74 TTL Load,

Input t ≤ 20 ns,

†

OutputdisabletimefromG/V orE, whicheveroccursfirst

Input t ≤ 20 ns

Output data valid time after change of address, E, or G/V

v(A)

†

whichever occurs first

’27C512-15

’27PC512-15

TEST CONDITIONS

(SEE NOTES 3 AND 4)

PARAMETER

UNIT

MIN

MAX

150

Access time from address

Access time from chip enable

Output enable time from G/V

a(A)

a(E)

en(G)

dis

= 100 pF,

1 Series 74 TTL Load,

Input t ≤ 20 ns,

†

Output disable time from G/V

or E, whichever occurs first

Input t ≤ 20 ns

Output data valid time after change of address, E, or G/V , whichever

v(A)

†

occurs first

’27C512-20

’27PC512-20

’27C512-25

’27PC512-25

TEST CONDITIONS

(SEE NOTES 3 AND 4)

PARAMETER

UNIT

MIN

MAX

200

MIN

MAX

250

100

Access time from address

Access time from chip enable

Output enable time from G/V

a(A)

a(E)

en(G)

dis

= 100 pF,

1 Series 74 TTL Load,

Input t ≤ 20 ns,

†

OutputdisabletimefromG/V orE, whicheveroccursfirst

Input t ≤ 20 ns

Output data valid time after change of address, E, or G/V

v(A)

†

whichever occurs first

†

Value calculated from 0.5 V delta to measured output level. This parameter is only sampled.

NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low (see Figure 2).

4. Common test conditions apply for t

except during programming.

dis

switching characteristics for programming: V

= 6.50 V and G/V

= 13 V (SNAP! Pulse),

T = 25°C (see Note 3)

PARAMETER

MIN

MAX UNIT

130 ns

Disable time, output from G/V

dis(G)

NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and

0.8 V for logic low.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

timing requirements for programming

MIN NOM

MAX

UNIT

µs

Pulse duration, initial program

Setup time, address

100

105

w(IPGM)

su(A)

Setup time, data

su(D)

Setup time, G/V

su(VPP

su(VCC)

h(A)

Setup time, V

Hold time, address

Hold time, data

h(D)

Hold time, G/V

h(VPP)

rec(PG)

EHD

Recovery time, G/V

Data valid from E low

Rise time, G/V

r(PG)G

PARAMETER MEASUREMENT INFORMATION

2.08 V

= 800 Ω

Output

Under Test

= 100 pF

(see Note A)

2.4 V

2 V

0.8 V

0.4 V

NOTES: A.

includes probe and fixture capacitance.

B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing

measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs

and outputs.

Figure 2. AC Testing Output Load Circuit

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

A0–A15

Addresses Valid

a(A)

a(E)

G/V

dis

en(G)

v(A)

DQ0–DQ7

Hi-Z

Output Valid

Hi-Z

Figure 3. Read-Cycle Timing

A0–A15

Address Stable

su(A)

h(A)

IH/ OH

DQ0–DQ7

Data-In Stable

Hi-Z

Data-Out Valid

IL/ OL

†

dis(G)

su(D)

h(D)

EHD

G/V

h(VPP)

su(VPP)

r(PG)G

rec(PG)

su(VCC)

w(IPGM)

‡

†

‡

is a characteristic of the device but must be accommodated by the programmer.

dis(G)

13-V G/V

and 6.5-V V

for SNAP! Pulse programming.

Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)

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TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

FM (R-PQCC-J32)

PLASTIC J-LEADED CHIP CARRIER

Seating Plane

0.004 (0,10)

0.140 (3,56)

0.132 (3,35)

0.129 (3,28)

0.495 (12,57)

0.485 (12,32)

0.123 (3,12)

0.453 (11,51)

0.447 (11,35)

0.049 (1,24)

0.043 (1,09)

0.008 (0,20) NOM

0.020 (0,51)

0.015 (0,38)

0.595 (15,11)

0.585 (14,86)

0.553 (14,05)

0.547 (13,89)

0.030 (0,76)

TYP

0.050 (1,27)

4040201-4/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-016

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G – NOVEMBER 1985 – REVISED SEPTEMBER 1997

J (R-CDIP-T**)

CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PIN SHOWN

Lens Protrusion

0.010 (0,25) MAX

0.065 (1,65)

0.045 (1,14)

0.090 (2,29)

0.060 (1,53)

0.175 (4,45)

0.140 (3,56)

0.018 (0,46) MIN

Seating Plane

0°–10°

0.125 (3,18) MIN

0.022 (0,56)

0.014 (0,36)

0.100 (2,54)

0.012 (0,30)

0.008 (0,20)

PINS**

DIM

NARR

WIDE

NARR

WIDE

NARR

WIDE

NARR

WIDE

0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)

0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)

1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)

1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)

0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)

0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)

MAX

MIN

MAX

MIN

MAX

MIN

4040084/B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

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TMS27C512-100JL4 [TI]

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