TMS28F002ZT90BDBJE [TI]

262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES; 262144 ×8位/ 131072 16位自动选择启动块闪存


型号：	TMS28F002ZT90BDBJE
厂家：	TEXAS INSTRUMENTS
描述：	262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES 262144 ×8位/ 131072 16位自动选择启动块闪存闪存
文件：	总79页 (文件大小：1110K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

DBJ PACKAGE

(TOP VIEW)

Organization . . . 262144 by 8 bits

131072 by 16 bits

Array-Blocking Architecture

44 RP

– One 16K-Byte Protected Boot Block

– Two 8K-Byte Parameter Blocks

– One 96K-Byte Main Block

– One 128K-Byte Main Block

– Top or Bottom Boot Locations

DU/WP

41 A9

40 A10

39 A11

38 A12

37 A13

36 A14

’28F200Axy Offers a User-Defined 8-Bit

(Byte) or 16-Bit (Word) Organization

A1 10

A0 11

A15

A16

BYTE

’28F002Axy Offers Only the 8-Bit (Byte)

Organization

Maximum Access/Minimum Cycle Time

– Commercial and Extended

31 DQ15/A

30 DQ7

29 DQ14

28 DQ6

–1

5-V V

10% or 3.3-V V

0.3 V

3.3 V

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

5 V

’28F002Axy/200Axy60 60 ns 110 ns

’28F002Axy/200Axy70 70 ns 130 ns

’28F002Axy/200Axy80 80 ns 150 ns

DQ13

26 DQ5

25 DQ12

24 DQ4

– Automotive

5-V V

10%

’28F200Axy70

’28F200Axy80

’28F200Axy90

70 ns

80 ns

90 ns

PIN NOMENCLATURE

A0–A16

A17

Address Inputs

(x = S, E, F, Z, or M Depending on V /V

Address Input (40-Pin Package Only)

Byte-Enable

CC PP

BYTE

Voltage Configuration)

DQ0–DQ14 Data In/Out

(y = T for Top or B for Bottom Boot-Block

Configuration)

DQ15/A

Data In/Out (Word-Wide Mode),

–1

Low-Order Address (Byte-Wide Mode)

Chip-Enable

100000- and 10000-Program/Erase-Cycle

Versions

Output-Enable

Three Temperature Ranges

No Internal Connection

Reset/Deep Power-Down

Power Supply

– Commercial . . . 0°C to 70°C

– Extended . . . – 40°C to 85°C

– Automotive . . . – 40°C to 125°C

Power Supply for Program/Erase

Ground

Industry Standard Packages Offered in

– 40-pin Thin Small-Outline Package

(TSOP)

Write-Enable

DU/WP

Do Not Use for AMy or AZy/Write-Protect

– 44-pin Plastic Small-Outline Package

(PSOP)

– 48-pin TSOP

Fully Automated On-Chip Erase and

Word/Byte Program Operations

Write-Protection for Boot Block

Low Power Dissipation (V

= 5.5 V)

Industry Standard Command-State Machine

(CSM)

– Erase Suspend/Resume

– Algorithm-Selection Identifier

– Active Read . . . 330 mW (Byte-Read)

– Active Write . . . 248 mW (Byte-Write)

– Active Read . . . 330 mW (Word-Read)

– Active Write . . . 248 mW (Word-Write)

– Block-Erase . . . 165 mW

Five Different Combinations of Supply

Voltages Offered

– Standby . . . 0.72 mW (CMOS-Input

Levels)

All Inputs/Outputs TTL-Compatible

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

40-PIN DCD PACKAGE

(TOP VIEW)

A16

A15

A14

A13

A12

A11

A17

A10

DQ7

DQ6

DQ5

DQ4

DU/WP

DQ3

DQ2

DQ1

DQ0

48-PIN DCD PACKAGE

(TOP VIEW)

A15

A16

BYTE

A14

A13

A12

A11

A10

DQ15/A

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

–1

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

DU/WP

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

Table of Contents

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

device symbol nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

block-memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

boot-block data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

parameter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

command-state machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . . . 8

operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

command definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

byte-wide or word-wide mode selection . . . . . . . . . . . . . . . . . . 11

command-state-machine operations . . . . . . . . . . . . . . . . . . . . 13

clear status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

programming operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

automatic power-saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . 15

reset/deep power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . 15

power supply detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

common electrical parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

TMS28F002ASy and TMS28F200ASy . . . . . . . . . . . . . . . . . . . . . . 22

TMS28F002AEy and TMS28F200AEy . . . . . . . . . . . . . . . . . . . . . . 32

TMS28F002AMy and TMS28F200AMy . . . . . . . . . . . . . . . . . . . . . 42

TMS28F002AFy and TMS28F200AFy . . . . . . . . . . . . . . . . . . . . . . 50

TMS28F002AZy and TMS28F200AZy . . . . . . . . . . . . . . . . . . . . . . 60

Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . 70

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NO TAG

description

The TMS28F200Axy is a 262144 by 8-bit /131072 by-16 bit (2097152-bit), boot-block flash memory that can

be electrically block-erased and reprogrammed. The TMS28F200Axy is organized in a blocked architecture

consisting of:

One 16K-byte protected boot block

Two 8K-byte parameter blocks

One 96K-byte main block

One 128K-byte main block

The device can beorderedinfivedifferentvoltageconfigurations(seeTable 1). Operation as a 256K-byte (8-bit)

or a 128K-word (16-bit) organization is user-definable.

The TMS28F002Axy is offered in a 256K-byte organization only. The operation for this device is the same as

the TMS28F200Axy and is offered in the same voltage configurations. TMS28F002Axy can be substituted for

the byte-wide TMS28F200Axy, with the latter being the generic name for this device family.

Embedded program and block-erase functions are fully automated by the on-chip write-state machine (WSM),

thereby simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM

status can be monitored by an on-chip status register to determine the progress of program/erase tasks. The

device features user-selectable block-erasure.

The configurations are as follow:

The TMS28F002ASy and the TMS28F200ASy configurations have the auto-select feature that allows

alternative read and program/erase voltages. Memory reads can be performed using 3.3-V V

for

optimum power consumption or at 5-V V , for device performance. Erasing or programming the device

can be accomplished with 5-V V , which eliminates having to use a 12-V source and/or in-system voltage

converters. Alternatively, 12-V V

operation exists for systems that already have a 12-V power supply,

which provides faster programming and erasing times. These configurations are offered in two different

temperature ranges: 0°C to 70°C and – 40°C to 85°C.

The TMS28F002AEy and the TMS28F200AEy configurations offer the auto-select feature of the

TMS28F200ASy with an extended V

to a low 2.7-V to 3.6-V range (3-V nominal). Memory reads can be

performed using a 3-V V , allowing for more efficient power consumption than the ’ASy device.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

The TMS28F002AMy and TMS28F200AMy configurations offer a 3-V or 5-V memory read with a 12-V

program and erase. These configurations are intended for low 3.3-V reads and the fast programming

offered with the12-V V

ranges: 0°C to 70°C and – 40°C to 85°C.

and 5-V V . These configurations are offered in two different temperature

The TMS28F002AFy and TMS28F200AFy configurations offer a 5-V memory read with a 5-V or 12-V

program and erase. These configurations are intended for systems using a single 5-V power supply. The

configurations are offered in three temperature ranges: 0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C.

TheTMS28F002AZyandTMS28F200AZyconfigurationsoffera5-Vmemoryreadwitha12-Vprogramand

a 12-V erase for fast programming and erasing times. These configurations are offered in three temperature

ranges: 0°C to 70°C,– 40°C to 85°C, and – 40°C to 125°C.

All configurations of the TMS28F200Axy are offered in the 44-pin plastic small-outline package (PSOP) and the

48-pinthinsmall-outlinepackage(TSOP). TheTMS28F002Axyisofferedina40-pinTSOPonly. Boththe40-pin

and 48-pin TSOP are offered for the 0°C to 70°C and – 40°C to 85°C temperature ranges only.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

device symbol nomenclature

TMS28F200AS

DBJ

Temperature Range Designator

0°C to 70°C

– 40°C to 85°C

Q = – 40°C to 125°C

Package Designator

DBJ = 44-Pin PSOP

DCD= 40-Pin TSOP (F002 only)

DCD= 48-Pin TSOP (F200 only)

Program/Erase Endurance

= 100000 Cycles

= 10000 Cycles

Speed Designator

60 = 60 ns

Boot-Block Location Indicator

T = Top Location

70 = 70 ns

80 = 80 ns

90 = 90 ns

B = Bottom Location

= (3.3V ± 0.3V or 5V ± 10%) V

and (5V ± 10% or 12V ± 5%) V

=(2.7 V to 3.6 V or 5 V ± 10%) V

and (5 V ± 10% or 12 V ± 5%) V

and 12V ± 5% V

M = (3.3V ± 0.3V or 5V ± 10%) V

and (5V ± 10% or 12V ± 5%) V

= 5V ± 10% V

and 12 V ± 5% V

Organization

200 = 128K x 16-bits or 256K x 8 bits

002 = 256K x 8 bits

†

Table 1. V -/V -Voltage Configurations

DEVICE

CONFIGURATION

PROGRAM/ERASE

OPERATING FREE-AIR

TEMPERATURE (T )

ACCESS SPEEDS

5 V (3.3 V) V

READ VOLTAGE (V

)

VOLTAGE (V

)

0°C to 70°C

– 40°C to 85°C

0°C to 70°C

60(110), 70(130), 80(150) ns

60, 70, 80 ns

3.3 V ± 0.3 V or

5 V ± 10 %

5 V ± 10% or

12 V ± 5 %

TMS28F200ASy

2.7 V to 3.6 V or

5 V ± 10 %

5 V ± 10% or

12 V ± 5 %

TMS28F200AEy

TMS28F200AMy

– 40°C to 85°C

0°C to 70°C

3.3 V ± 0.3 V or

5 V ± 10 %

12 V ± 5 %

– 40°C to 85°C

0°C to 70°C

5 V ± 10% or

12 V ± 5 %

TMS28F200AFy

TMS28F200AZy

5 V ± 10 %

– 40°C to 85°C

60, 70, 80 ns

‡

– 40°C to 125°C

0°C to 70°C

70, 80, 90 ns

60, 70, 80 ns

12 V ± 5 %

– 40°C to 85°C

– 40°C to 125°C

60, 70, 80 ns

70, 80, 90 ns

†

‡

All configurations are available in the TMS28F002Axy (8-bit only) and top or bottom boot.

Only the 44-pin PSOP is offered in the – 40°C to 125°C temperature range.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

functional block diagram

†

DQ8–DQ15/A

DQ0–DQ7

–1

DQ15/A

Input Buffer

Output

Buffer

Output

Buffer

Input

Buffer

Input

Buffer

–1

Data

†

BYTE

I/O Logic

Identification

Command-

State

Machine

Output

Multiplexer

Status

A0–

A16

Input

Buffer

Power-

Reduction

Control

Data

Comparator

Program/

Write-

State

Machine

Erase

Voltage

Switch

Address

Latch

Y Decoder

X Decoder

Y Gating/Sensing

16K-Byte

Boot

Block

8K-Byte

Parameter Parameter

Block Block

8K-Byte

96K-Byte 128K-Byte

Address

Counter

Main

Block

Main

Block

†

Not used on ’F002 model

architecture

The TMS28F200Axy uses a blocked architecture to allow independent erasure of selected memory blocks. The

block to be erased is selected by using any valid address within that block.

block-memory maps

The TMS28F200Axy is available with the block architecture mapped in either of two configurations: the boot

block located at the top or at the bottom of the memory array, as required by different microprocessors. The

TMS28F200AxB (bottom boot block) is mapped with the 16K-byte boot block located at the low-order address

range (00000h to 01FFFh). The TMS28F200AxT (top boot block) is inverted with respect to the

TMS28F200AxBwith the boot block located at the high-order address range (1E000h to 1FFFFh). Both of these

address ranges are for word-wide mode. The TMS28F002Axy is mapped as the 8-bit configuration of the

TMS28F200Axy, except that the least signficant bit (LSB) is A0 instead of A . Figure 1 and Figure 2 show the

–1

memory maps for these configurations.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

block memory maps (continued)

Address

Range

16-bit

Configuration

Address

Range

8-Bit Configuration

3FFFFh

1FFFFh

Boot Block

16K Addresses

8K Addresses

3C000h

3BFFFh

1E000h

1DFFFh

Parameter Block

8K Addresses

Parameter Block

4K Addresses

3A000h

39FFFh

1D000h

1CFFFh

Parameter Block

8K Addresses

Parameter Block

4K Addresses

38000h

37FFFh

1C000h

1BFFFh

Main Block

96K Addresses

48K Addresses

20000h

1FFFFh

10000h

0FFFFh

Main Block

128K Addresses

64K Addresses

00000h

DQ15/A Is LSB Address

–1

A0 Is LSB Address

NOTE A: The TMS28F002AxT is mapped the same way as the 8-bit configuration

of the TMS28F200AxT and the LSB is A0.

Figure 1. TMS28F200AxT (Top Boot Block) Memory Map (See Note A)

Address

Range

16-Bit

Configuration

Address

Range

8-Bit Configuration

3FFFFh

1FFFFh

Main Block

128K Addresses

64K Addresses

20000h

1FFFFh

10000h

0FFFFh

Main Block

96K Addresses

48K Addresses

08000h

07FFFh

04000h

03FFFh

Parameter Block

8K Addresses

Parameter Block

4K Addresses

06000h

05FFFh

03000h

02FFFh

Parameter Block

8K Addresses

Parameter Block

4K Addresses

04000h

03FFFh

02000h

01FFFh

Boot Block

16K Addresses

8K Addresses

00000h

DQ15/A Is LSB Address

–1

A0 Is LSB Address

NOTE A: The TMS28F002AxB is mapped the same way as the 8-bit

configuration of the TMS28F200AxB and the LSB is A0.

Figure 2. TMS28F200AxB (Bottom-Boot Block) Memory Map (See Note A)

boot-block data protection

The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data

in this block can be secured by using different combinations of the reset/deep power-down pin (RP), the

write-protect pin (WP), and V supply levels. Table 2 shows a listing of these combinations.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

parameter block

Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.

Alternatively, the parameter blocks can be used for additional boot-block or main-block data. If a parameter

block is used to store additional boot-block data, caution must be exercised because the parameter block does

not have the boot-block data-protection safety feature.

main block

Primary memory on the TMS28F200Axy is located in two main blocks. One of the blocks has storage capacity

for 128K bytes and the other block has storage capacity for 96K bytes.

data protection

Data is secured or unsecured by using different combinations of the reset/deep power-down pin (RP), the

write-protect pin (WP), and V supply levels. Table 2 shows a listing of these combinations.

There are two configurations to secure the entire memory against the inadvertent alteration of data. The V

supply pin can be held below the V lock-outvoltagelevel(V

)orthereset/deeppower-downpin(RP)can

PPLK

be pulled to a logic-low level. If RP is held low, the device resets—which means that it powers down, and

therefore, cannot be read. Typically this pin is tied to the system reset for additional protection during system

power up.

The boot-block sector has an additional security feature through the WP pin on the ’ASy, ’AEy, and ’AFy devices.

When the RP pin is at a logic-high level, the WP pin controls whether the boot-block sector is protected. When

WP is held at the logic-low level, the boot block is protected. When WP is held at the logic-high level, the boot

block is unprotected, along with the rest of the other sectors. Alternatively, the entire memory for all voltage

configurations can be unprotected by pulling the RP pin to V

(12 V).

Table 2. Data-Protection Combinations

’ASy, ’AEy, or ’AFy

†

’AMy or ’AZy

DATA-PROTECTION

PROVIDED

†

All blocks locked

All blocks locked (reset)

All blocks unlocked

> V

PPLK

Only boot block locked

†

For TMS28F200AZy and TMS28F200AMy (12-V V ) products, the WP pin is disabled and can be left floating. To unlock blocks, RP must

be at V

command-state machine (CSM)

Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface

between the external microprocessor and the internal write state machine (WSM). The available commands

are listed in Table 3 and the descriptions of these commands are listed in Table 4. When a program or erase

command is issued to the CSM, the WSM controls the internal sequences and the CSM only responds to status

reads. After the WSM completes its task, the write status bit (WSM) (SB7) is set to a logic-high level, allowing

the CSM to respond to the full command set again.

operation

Device operations are selected by entering standard JEDEC 8-bit command codes with conventional

microprocessor timing into an on-chip CSM through I/O pins DQ0–DQ7. When the device is powered up,

internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation

requires that a command code be entered into the CSM. Table 3 lists the CSM codes for all modes of operation.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

operation (continued)

The on-chip status register allows the progress of various operations to be monitored. The status register is

interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data

on I/O pins DQ0–DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.

Table 3. Command-State Machine Codes for Device Mode Selection

COMMAND

CODE ON

DQ0–DQ7

DEVICE MODE

Invalid/Reserved

Alternate Program Setup

Block-Erase Setup

Program Setup

Clear Status Register

Read Status Register

Algorithm Selection

Erase-Suspend

Erase-Resume/Block-Erase Confirm

Read Array

†

00h

10h

20h

40h

50h

70h

90h

B0h

D0h

FFh

†

DQ0 is the least significant bit. DQ8–DQ15 can be any valid 2-state level.

command definition

Once a specific command code has been entered, the WSM executes an internal algorithm generating the

necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and

data for each of the bus cycles.

Following the read-algorithm-selection-code command, two read cycles are required to access the

manufacturer-equivalent code and the device-equivalent code. The codes are shown in Table 6, Table 7, and

Table 8.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

command definition (continued)

Table 4. Command Definitions

FIRST BUS CYCLE

OPERATION ADDRESS

Read Operations

SECOND BUS CYCLE

BUS

CYCLES

REQUIRED

COMMAND

CSM

INPUT

DATA

OPERATION ADDRESS

IN/OUT

Read Array

Write

FFh

90h

70h

50h

Read

Data Out

M/D

Read Algorithm-Selection Code

Read Status Register

SRB

Clear Status Register

Program Mode

Program Setup/Program

(byte/word)

Write

40h or 10h

Write

Erase Operations

Block-Erase Setup/

Block-Erase Confirm

Write

BEA

20h

B0h

Write

BEA

D0h

Erase-Suspend/

Erase-Resume

Legend:

BEA

M/D

Block-erase address. Any address selected within a block selects that block for erase.

Manufacturer-equivalent/device-equivalent code

Address to be programmed

Data to be programmed at PA

SRB

Status-register data byte that can be found on DQ0–DQ7

Don’t care

status register

The status register allows determination of whether the state of a program/erase operation is pending or

complete. The status register is monitored by writing a read-status command to the CSM and reading the

resulting status code on I/O pins DQ0–DQ7. This is valid for operation in either the byte-wide or word-wide

mode. When writing to the CSM in word-wide mode, the high-order I/O pins (DQ8–DQ15) can be set to any

valid 2-state level. When reading the status bits during a word-wide read operation, the high-order I/Os

(DQ8–DQ15) are set to 00h internally, so the user needs to interpret only the low-order I/O pins (D0–DQ7).

After a read-status command has been given, the data appearing on DQ0–DQ7 remains as status register data

until a new command is issued to the CSM. To return the device to other modes of operation, a new command

must be issued to the CSM.

updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register

input change during a status-register read. To ensure that the status-register output contains updated status

data, E or G must be toggled for each subsequent status read.

The status register provides the internal state of the WSM to the external microprocessor. During periods when

the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the

status-register bits and their functions.

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262144 BY 8-BIT/131072 BY 16-BIT

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SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

status register (continued)

Table 5. Status-Register Bit Definitions and Functions

STATUS

FUNCTION

BIT

DATA

COMMENTS

If SB7 = 0 (busy), the WSM has not completed an erase or

programming operation. If SB7 = 1 (ready), other polling

operations can be performed. Until this occurs, the other status

bits are not valid. If the WSM status bit shows busy (0), the user

must toggle E or G periodically to determine when the WSM has

completed an operation (SB7 = 1) since SB7 is not automatically

updated at the completion of a WSM task.

Write-state-machine status

(WSMS)

1 = Ready

0 = Busy

SB7

When an erase-suspend command is issued, the WSM halts

execution and sets the ESS bit high (SB6 = 1), indicating that the

erase operation has been suspended. The WSM status bit also

is set high (SB7 = 1), indicating that the erase-suspend operation

has been completed successfully. The ESS bit remains at a

logic-high level until an erase-resume command is input to the

CSM (code D0h).

1 = Erase suspended

0 = Erase in progress or

completed

Erase-suspend status

(ESS)

SB6

SB5 = 0 indicates that a successful block-erasure has occurred.

SB5 = 1 indicates that an erase error has occurred. In this case,

the WSM has completed the maximum allowed erase pulses

determined by the internal algorithm, but this was insufficient to

completely erase the device.

Erase status

1 = Block-erase error

0 = Block-erase good

SB5

(ES)

SB4 = 0 indicates successful programming has occurred at the

addressed block location. SB4 = 1 indicates that the WSM was

unable to program the addressed block location correctly.

Program status

1 = Byte/word-program error

0 = Byte/word-program good

SB4

(PS)

SB3 provides information on the status of

during

1 = Program abort:

programming.If V is lower than V after a program or erase

command has been issued, SB3 is set to a 1, indicating that the

programming operation is aborted. If V is between V and

PPL

status

SB3

range error

good

(V S)

0 = V

PPH

V , SB3 is not set.

PPL

SB2–

SB0

Reserved

SB2–SB0 are masked out when reading the status register.

byte-wide or word-wide mode selection

The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8–DQ15, and

a lower-half that outputs data through DQ0–DQ7. Device operation in either byte-wide or word-wide mode is

user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device

is in the word-wide mode and data is written to or read from I/O pins DQ0–DQ15. When BYTE is at a logic-low

level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0–DQ7. In the byte-wide

mode, I/O pins DQ8–DQ14 are placed in the high-impedance state and DQ15/A becomes the low-order

–1

address pin and selects either the upper- or lower-half of the array. Array data from the upper half (DQ8–DQ15)

and the lower half (DQ0–DQ7) are multiplexed to appear on DQ0–DQ7. Table 6, Table 7, and Table 8

summarize operation modes.

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262144 BY 8-BIT/131072 BY 16-BIT

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SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

byte-wide or word-wide mode selection (continued)

Table 6. Operation Modes for Word-Wide Mode (BYTE = V ) (see Note 1)

MODE

DQ0–DQ15

Read

Data out

Manufacturer-equivalent code

0089h

Device-equivalent code

2274h

(top boot block)

Algorithm-selection mode

Device-equivalent code

2275h

(bottom boot block)

Output disable

Standby

Hi-Z

Reset/deep power-down

PPL

PPH

Write (see Note 2)

Data in

NOTES: 1. X = don’t care

2. When writing commands to the ’28F200Axy, V

must be in the appropriate V

voltage range (as shown in the recommended

operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the

combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).

Table 7. Operation Modes for Byte-Wide Mode (BYTE = V ) (see Note 1)

MODE

DQ15/A

DQ8–DQ14

DQ0–DQ7

Data out

–1

Read lower byte

Read upper byte

Hi-Z

Data out

Manufacturer-equivalent

code 89h

Hi-Z

Algorithm-selection

mode

Device-equivalent code

74h (top boot block)

Hi-Z

Device-equivalent code

75h (bottom boot block)

Output disable

Standby

Hi-Z

Reset/deep

power-down

Hi-Z

PPL

Write (see Note 2)

Hi-Z

Data in

PPH

NOTES: 1. X = don’t care

2. When writing commands to the ’28F200Axy, V

must be in the appropriate V

voltage range (as shown in the recommended

operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the

combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

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262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

byte-wide or word-wide mode selection (continued)

Table 8. Operation Modes for ’28F002Axy (see Note 1)

MODE

DQ0–DQ7

Read

Data out

Manufacturer-equivalent code

89h

Device-equivalent code 7Ch

(top boot block)

Algorithm-selection mode

Device-equivalent code 7Dh

(bottom boot block)

Output disable

Standby

Hi-Z

Reset/deep power-down

PPL

PPH

Write (see Note 3)

Data in

NOTES: 1. X = don’t care

3. When writing commands to the ’28F002Axy, V

must be in the appropriate V

voltage range (as shown in the recommended

operating conditions table for the product) for block-erase or program commands to be executed. Also, depending on the

combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).

command-state-machine operations

The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status

DQ0–DQ7 (see Table 3 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a

program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences

and the CSM responds only to status reads.

During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has

completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full

command set. The CSM stays in the current command state until the microprocessor issues another command.

The WSM successfully initiates an erase or program operation only when V is within its correct voltage range.

For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.

clear status register

The internal circuitry can set only the V status (SB3), the program status bit (SB4), and the erase status bit

(SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to

clear these status bits and synchronize to internal operations. When the status bits are cleared, the device

returns to the read-array mode.

read operations

There are three read operations available: read array, read algorithm-selection code, and read status register.

read array

The array level is read by entering the command code FFh on DQ0–DQ7. Control pins Eand G must be at a

logic-low level (V ) and W and RP must be at a logic-high level (V ) to read data from the array. Data is

available on DQ0–DQ15 (word-wide mode) or DQ0–DQ7 (byte-wide mode). Any valid address within any

of the blocks selects that block and allows data to be read from the block.

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SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

read operations (continued)

read algorithm-selection code

Algorithm-selection codes are read by entering command code 90h on DQ0–DQ7. Two bus cycles are

required for this operation: the first to enter the command code and a second to read the device-equivalent

code. Control pins E and G must be at a logic-low level (V ), and W and RP must be at a logic-high level

(V ). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on

DQ0–DQ7 with A0 at a logic-low level (V ). The device-equivalent code is obtained when A0 is set to a

logic-high level (V ). Alternatively, themanufacturer-anddevice-equivalentcodescanbereadbyapplying

(nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are

“don’t cares” (see Table 4, Table 6, Table 7, and Table 8).

read status register

The status register is read by entering the command code 70h on DQ0–DQ7. Control pins E and G must be

at a logic-low level (V ) and W and RP must be at a logic-high level (V ). Two bus cycles are required for

this operation: one to enter the command code and a second to read the status register. In a given read

cycle, status register contents are updated on the falling edge of E or G, whichever occurs last within the

cycle.

programming operations

There are two CSM commands for programming: program setup and alternate program setup

(see Table 3). After the desired command code is entered, the WSM takes over and correctly sequences the

device to complete the program operation. During this time, the CSM responds only to status reads until the

program operation has been completed, after which all commands to the CSM become valid again. Once a

program command has been issued, the WSM normally cannot be interrupted until the program algorithm is

completed (see Figure 3 and Figure 4).

Taking RP to V during programming aborts the program operation. During programming, V must remain in

the appropriate V voltage range, as shown in the recommended operating conditions table for the product.

Note that different combinations of RP, WP and V pin voltage levels ensure that data in certain blocks are

secure, and, therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and

compared during a program operation. If 1s are programmed, the memory cell contents do not change and no

error occurs.

A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)

during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.

When the SB7 is set to a logic-high level, signifying the nonprogram operation is terminated, all commands to

the CSM become valid again.

erase operations

There are two erase operations that can be performed by the TMS28F002Axy and TMS28F200Axy devices:

block-erase and erase-suspend/erase-resume. An erase operation must be used to initialize all bits in an array

block to 1s. After block-erase-confirm is issued, the CSM responds only to status reads or erase-suspend

commands until the WSM completes its task.

block erasure

Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is

accomplished only by blocks; data at single-address locations within the array cannot be erased

individually. The block to be erased is selected by using any valid address within that block. Note that

different combinations of RP, WP, and V pin voltage levels ensure that data in certain blocks are secure

and, therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a

command sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see

Figure 5). A two-command erase sequence protects against accidental erasure of memory contents.

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SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

erase operations (continued)

Erase-setup and erase-confirm commands are latched on the rising edge of E or W, whichever occurs first.

Block addresses are latched during the block-erase-confirm command on the rising edge of E or W (see

Figure 14 and Figure 15). When the block-erase-confirm command is complete, the WSM automatically

executes a sequence of events to complete the block erasure. During this sequence, the block is

programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is

performed to ensure that all bits are erased correctly. Monitoring of the erase operation is possible through

the status register (see the “read status register” paragraph in the “read operations” subsection).

erase-suspend/erase-resume

During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the

WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to

respond only to the read-array, read-status-register, and erase-resume commands. During the

erase-suspend operation, array data should be read from a block other than the one being erased. To

resume the erase operation, an erase-resume command (D0h) must be issued to cause the CSM to clear

the suspend state previously set (see Figure 5 and Figure 6).

automatic power-saving mode

Substantial power savings are realized during periods when the array is not being read and the device is in the

active mode. During this time, the device switches to the automatic power-saving (APS) mode. When the device

switches to this mode, I

is typically reduced from 40 mA to 1 mA (I

= 0 mA). The low level of power is

OUT

maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last

memory address read until a new address is read. This mode is entered automatically if no address or control

pins toggle within approximately a 200-ns time-out period. At least one transition on E must occur after power

up to activate this mode.

reset/deep power-down mode

Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device

circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, a much lower I

This is important in portable applications where extended battery life is of major concern.

value or power is achievable.

A recovery time is required when exiting from deep power-down mode. For a read-array operation, a

minimum of t

is required before data is valid, and a minimum of t

and t

in deep

d(RP)

rec(RPHE)

rec(RPHW)

power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM

is reset and the status register is cleared, effectively eliminating accidental programming to the array during

system reset. After restoration of power, the device does not recognize any operation command until RP is

returned to a V or V

level.

Should RP go low during a program or erase operation, the device powers down and, therefore, becomes

nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the

operation be performed again after power restoration.

power supply detection

RP must be connected to the system reset/power down signal to ensure that proper synchronization is

maintained between the CPU and the flash memory operating modes. The default state after power up and exit

from deep power-down mode is read array. RP also is used to indicate that the power supply is stable so that

the operating supply voltage can be established (3 V, 3.3 V, or 5 V). Figure 10 shows the proper power-up

sequence. To reset the operating supply voltage, the device must be completely powered off (V = 0 V) before

the new supply voltage is detected.

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TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

Start

BUS

COMMAND

COMMENTS

OPERATION

Issue Program-Setup

Command and Byte Address

Write

program

setup

Data

Addr

40h or 10h

Address of

byte to be

programmed

Issue Byte

Address/Data

Write

Write data

Data

Addr

Byte to be

programmed

Address of

byte to be

Read Status-Register

Bits

programmed

Read

Status-register data.

Toggle G or E to update

status register

SB7 = 1

Standby

Check SB7

1 = Ready, 0 = Busy

Yes

Repeat for subsequent bytes.

Write FFh after the last byte-programming operation to

reset the device to read-array mode.

Full Status-Register

See Note A

Check (optional)

Byte-Program Completed

FULL STATUS-REGISTER-CHECK FLOW

Read

Status-Register Bits

BUS

OPERATION

COMMAND

COMMENTS

Check SB3

SB3 = 0

Range Error

Standby

1 = Detect V

low

(see Note B)

Yes

Check SB4

1 = Byte-program error

(see Note C)

Byte-Program

Failed

Standby

SB4 = 0

Yes

Byte-Program Passed

NOTES: A. Full status-register check can be done after each byte or after a sequence of bytes.

B. SB3 must be cleared before attempting additional program/erase operations.

C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.

Figure 3. Automated Byte-Programming Flow Chart

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262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

BUS

OPERATION

Start

COMMAND

COMMENTS

Write

program

setup

Data

Addr

40h or 10h

Address of

word to be

programmed

Issue Program-Setup

Command and Word

Address

Write

Write data

Data

Addr

Word to be

programmed

Address of

word to be

Issue Word

Address/Data

programmed

Read

Status-register data.

Toggle G or E to update

status register.

Read Status-Register

Bits

Standby

Check SB7

1 = Ready, 0 = Busy

SB7 = 1

Repeat for subsequent words.

Write FFh after the last word-programming operation to

reset the device to read-array mode.

Yes

Full Status-Register

Check (optional)

See Note A

Word-Program

Completed

FULL STATUS-REGISTER-CHECK FLOW

Read Status-Register

Bits

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SB3

Detect V

SB3 = 0

low

V -Range Error

(see Note B)

Standby

Check SB4

Yes

Word-program

error

SB4 = 0

Word-Program

Failed

(see Note C)

Yes

Word-Program Passed

NOTES: A. Full status-register check can be done after each word or after a sequence of words.

B. SB3 must be cleared before attempting additional program/erase operations.

C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.

Figure 4. Automated Word-Programming Flow Chart

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262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

BUS

OPERATION

Start

COMMAND

COMMENTS

20h

Write

Write erase Data =

setup

Block Addr = Address

Issue Erase-Setup Command

and Block Address

within

block to

Issue Block-Erase-Confirm

Command and

erased

Write

Erase

Data

= D0h

Block Address

Block Addr = Address

within

block to

Erase-

Read Status-Register Bits

Suspend

erased

Loop

Read

Status-register data.

Toggle G or E to update

status register

Erase

Suspend

Yes

SB7 = 1

Standby

Check SB7

Yes

1 = Ready, 0 = Busy

Full Status-Register

Check (optional)

See Note A

Repeat for subsequent blocks.

WriteFFhafterthelastblock-eraseoperationtoresetthe

device to read-array mode

Block-Erase Completed

FULL STATUS-REGISTER-CHECK FLOW

Read Status-Register

Bits

BUS

OPERATION

COMMAND

COMMENTS

Standby

Check SB3

1 = Detect V

low

SB3 = 0

Range Error

(see Note B)

Standby

Check SB4 and SB5

1 = Block-erase

error

Yes

SB4 = 1,

SB5 = 1

Yes

Command Sequence

Error

Check SB5

1 = Block-erase error

(see Note C)

SB5 = 0

Block-Erase Failed

Yes

Block-Erase Passed

NOTES: A. Full status-register check can be done after each block or after a sequence of blocks.

B. SB3 must be cleared before attempting additional program/erase operations.

C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.

Figure 5. Automated Block-Erase Flow Chart

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262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

BUS

OPERATION

Start

COMMAND

COMMENTS

Data = B0h

Write

Erase-

suspend

Issue Erase-Suspend

Command

Read

Status-register data.

Toggle G or E to update

status register.

Standby

Write

Check SB7

1 = Ready

Read Status-Register

Bits

Check SB6

1 = Suspended

Read

memory

Data = FFh

SB7 = 1

Read

Read data from block

other than that being

erased.

Yes

SB6 = 1

Write

Erase-

resume

Data = D0h

Erase

Completed

Yes

Issue Memory-Read

Command

Finished

Reading

Yes

Issue Erase-Resume

Command

Erase Continued

See Note A

NOTE A: See block-erase flow chart for complete erasure procedure.

Figure 6. Erase-Suspend/Erase-Resume Flow Chart

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262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

common electrical parameter

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V

Supply voltage range, V (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V

Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to V

+ 1 V

RP, A9 (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V

Output voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to V + 1 V

Operating free-air temperature range, T , during read/erase/program: L suffix . . . . . . . . . . . . . . 0°C to 70°C

E suffix . . . . . . . . . . . . – 40°C to 85°C

Q suffix . . . . . . . . . . – 40°C to 125°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 4. All voltage values are with respect to V

5. The voltage on any input or output can undershoot to – 2 V for periods less than 20 ns. See Figure 8.

6. The voltage on any input or output can overshoot to 7 V for periods less than 20 ns. See Figure 9.

Output

Under

Test

VOLTAGE WAVEFORMS

(see Note A)

NOTES: A.

C includes probes and fixture capacitance

B. AC test conditions are driven at V and V . Timing measurements are made at V

and V levels on both inputs and

IH IL

outputs. See Table 9 for values based on V

operating range.

C. Each device should have a 0.1-µF ceramic capacitor connected to V

and V

as closely as possible to the device pins.

Figure 7. Load Circuit and Voltage Waveforms

20 ns

+0.8 V

–0.6 V

–2.0 V

20 ns

Figure 8. Maximum Negative Overshoot Waveform

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common electrical parameter (continued)

20 ns

7 V

+ 0.5 V

2.0 V

20 ns

Figure 9. Maximum Positive Overshoot Waveform

Table 9. AC Test Conditions

†

(V)

RANGE

(mA)

– 0.4

– 0.5

– 0.1

(V)

0.45

0.0

(V)

2.4

3.0

2.7

(pF)

100

(ns)

<10

(ns)

<10

5 V ± 10%

3.3 V ± 0.3 V

2.7 to 3.6 V

2.1

1.8

0.8

2.0

0.5

1.5

0.1

1.35

0.0

†

is the value to which an output at high impedance will float. V is calculated by the following equation: V = V

– I ).

– I

– V )/

OH OH OH

OH OL

capacitance over recommended ranges of supply voltage and operating free-air temperature

PARAMETER

TEST CONDITIONS

f = 1 MHz, V = 0V

MIN

MAX

UNIT

Input capacitance

Output capacitance

= 0 V, f = 1 MHz

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

TMS28F002ASy and TMS28F200ASy

The TMS28F002ASy and the TMS28F200ASy configurations have the auto-select feature that allows

alternative read and program/erase voltages. Memory reads can be performed using V

= 3.3 V for optimum

power consumption or at V

= 5 V, for device performance. Erasing or programming the device can be

accomplished with 5-V V , which eliminates having to use a 12-V source and/or in-system voltage converters.

Alternatively, 12-V V

operation exists for systems that already have a 12-V power supply, which provides

faster programming and erasing times. These configurations are offered in two different temperature ranges:

0°C to 70°C and – 40°C to 85°C.

recommended operating conditions for TMS28F002ASy and TMS28F200ASy

MIN

NOM

3.3

MAX

3.6

UNIT

3.3-V V

range

Supply voltage

During write/read/erase/erase suspend

5-V V

range

4.5

5.5

During read only (V

PPL

)

PPL

6.5

5-V V

range

4.5

11.4

5.5

During write/erase/erase suspend

12-V V

TTL

12.6

+ 0.5

3.3-V V

range

CMOS

TTL

– 0.2

+ 0.2

+ 0.3

+ 0.2

High-level dc

input voltage

5-V V

range

CMOS

TTL

– 0.2

– 0.5

0.8

+ 0.2

3.3-V V

range

CMOS

TTL

– 0.2

Low-level dc input

voltage

– 0.3

0.8

5-V V

range

CMOS

– 0.2

+ 0.2

lock-out voltage from write/erase (see Note 7)

LKO

RP unlock voltage

lock-out voltage from write/erase

11.4

1.5

PPLK

L suffix

E suffix

°C

Operating free-air temperature during read/erase/program

– 40

NOTE 7: Minimum value at T = 25°C.

word/byte typical write and block-erase performance for TMS28F002ASy and TMS28F200ASy

(see Notes 8 and 9)

5-V V

RANGE

12-V V

RANGE

3.3-V V

5-V V

3.3-V V

5-V V

PARAMETER

RANGE

TYP

2.4

RANGE

TYP

1.9

RANGE

TYP

1.3

RANGE

TYP

1.1

MIN

MAX

MIN

MAX MIN

MAX

MIN

MAX

Main block erase time

Main block byte-program time

Main block word-program time

Parameter/boot-block erase time

1.7

1.4

1.6

1.2

4.2

2.1

1.1

0.9

0.8

0.6

0.84

0.8

0.44

0.34

NOTES: 8. Typical values shown are at T = 25°C and nominal conditions

9. Excludes system-level overhead (all times in seconds)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of

supply voltage and operating free-air temperature using test conditions given in Table 9 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

TTL

= V

MIN,I

= – 2.5 mA

= – 100 µA

= 5.8 mA

2.4

High-level dc output voltage

CMOS

– 0.4

Low-level dc output voltage

A9 selection code voltage

0.45

12.6

During read algorithm-selection mode

= V MAX, V = 0 V to V MAX,

11.4

Input current (leakage), except for A9 when

RP = V

±1

µA

A9 = V (see Note 10)

A9 selection code current

RP boot-block unlock current

Output current (leakage)

A9 = V

500

±10

µA

RP = V

= V

MAX, V = 0 V to V

MAX

3.3-V V

range

standby current (standby)

≤ V

µA

PPS

PPL

PP1

5-V V

range

3.3-V V

5-V V

range

supply current (reset/deep

RP = V

± 0.2 V, V

≤ V

PP CC

power-down mode)

range

3.3-V V

range

200

supply current (active read)

≥ V

5-V V

range

range,

range

3.3-V V

5-V V

range,

range

supply current (active byte-write)

PP2

Programming in progress

(see Notes 11 and 12)

12-V V

range,

range

3.3-V V

range,

12-V V

5-V V

range

5-V V

3.3-V V

range,

range

5-V V

range,

range

supply current (active word-write)

(see Notes 11 and 12)

PP3

Programming in progress

12-V V

range,

range

3.3-V V

12-V V

5-V V

range,

range

NOTES: 10. DQ15/A is tested for output leakage only.

–1

11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

5-V V

range,

range

3.3-V V

5-V V

range,

range

supply current (block-erase)

PP4

Block-erase in progress

(see Notes 11 and 12)

12-V V

3.3-V V

range,

range

range,

12-V V

5-V V

range

5-V V

3.3-V V

range,

200

range

5-V V

range,

range

supply current (erase-suspend)

(see Notes 11 and 12)

PP5

Block-erase suspended

µA

12-V V

3.3-V V

range,

range

12-V V

5-V V

range,

range

3.3-V V

5-V V range

range

1.5

µA

= V

MAX,

TTL-input level

E = RP = V

supply current

(standby)

CCS

3.3-V V

5-V V

range

110

130

= V

MAX,

range

CMOS-input level

E = RP = V

0.2

µA

0°C to 70°C

supply current (reset/deep power-down

mode)

µA

RP = V

± 0.2 V

CCL

– 40°C to 85°C

E = V , G = V , I

= 0 mA,

range

IH OUT

f = 5 MHz, 3.3-V V

TTL-input level

E = V , G = V , I

= 0 mA,

range

IH OUT

f = 10 MHz, 5-V V

supply current

(active read)

CC1

E = V , G = V , I

= 0 mA,

range

CC OUT

f = 5 MHz, 3.3-V V

CMOS-input level

E = V , G = V , I

= 0 mA,

range

CC OUT

f = 10 MHz, 5-V V

5-V V

range,

range

3.3-V V

5-V V

range,

range

supply current (active byte-write)

= V MAX,

(see Notes 11 and 12)

Programming in progress

CC2

12-V V

range,

range

3.3-V V

12-V V

5-V V

range,

range

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

5-V V

range,

range

3.3-V V

5-V V

range,

range

supply current (active word-write)

= V MAX,

Programming in progress

CC3

(see Notes 11 and 12)

12-V V

3.3-V V

range,

range

range,

12-V V

5-V V

range

5-V V

3.3-V V

range,

range

5-V V

range,

range

supply current (block-erase)

= V MAX,

(see Notes 11 and 12)

Block-erase in progress

CC4

12-V V

3.3-V V

range,

range

12-V V

5-V V

range,

range

3.3-V V

range

supply current (erase-suspend)

= V

MAX, E = V ,

(see Notes 11 and 12)

CC5

Block-erase suspended

5-V V

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

power-up and reset switching characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply

voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7)

’28F002ASy60

’28F200ASy60

’28F002ASy70

’28F200ASy70

’28F002ASy80

’28F200ASy80

ALT.

SYMBOL

PARAMETER

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Setup time, RP low to V

PL5V

PL3V

4.5 V MIN (to V

at 3 V MIN or

su(VCC)

3.6 V MAX) (see Note 14)

Access time from address valid to data

110

800

130

800

150

800

a(DV)

AVQV

valid for V

= 5 V ± 10%

Setup time, RP high to data valid for

= 5 V ± 10%

450

su(DV)

PHQV

Hold time, V

high

at 4.5 V (MIN) to RP

µs

h(RP5)

5VPH

Hold time, V

at 3 V (MIN) to RP high

h(RP3)

3VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

switching characteristics for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage

(commercial and extended temperature ranges) (see Table 9 and Figure 7)

read operations

’28F002ASy60

’28F200ASy60

’28F002ASy70

’28F200ASy70

’28F002ASy80

’28F200ASy80

ALT.

SYMBOL

PARAMETER

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16

(see Note 15)

110

130

150

a(A)

AVQV

Access time from E

Access time from G

Cycle time, read

110

130

150

a(E)

a(G)

c(R)

ELQV

GLQV

110

130

150

AVAV

Delay time, E low to low-impedance

output

d(E)

ELQX

Delay time, G low to low-impedance

output

d(G)

GLQX

EHQZ

GHQZ

Disable time, E to high-impedance

output

dis(E)

dis(G)

h(D)

Disable time, G to high-impedance

output

Hold time, DQ valid from A0–A16, E, or

G, whichever occurs first (see Note 15)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Delay time, RP high to output

800

450

800

450

800

450

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15

in high-impedance state

FLQZ

Access time from BYTE going high

110

130

150

FHQV

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and

extended temperature ranges)

write/erase operations — W-controlled writes

’28F002ASy60

’28F200ASy60

’28F002ASy70

’28F200ASy70

’28F002ASy80

’28F200ASy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time, write

110

130

150

c(W)

AVAV

Cycle time, duration of programming

operation

0.3

0.6

0.3

0.6

0.3

0.6

µs

c(W)OP

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot

block)

0.3

0.6

0.3

0.6

0.3

0.6

c(W)ERB

c(W)ERP

c(W)ERM

Cycle time, erase operation

(parameter block)

Cycle time, erase operation (main

block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

200

100

200

100

200

100

d(RPR)

PHBR

h(A)

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status

h(VPP)

h(RP)

QVVL

QVPH

WHPL

Hold time, RP at V

status register bit

from valid

Hold time, WP from valid status

h(WP)

su(WP)

Setup time, WP before write

operation

105

120

ELPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

105

120

su(A)

AVWH

su(D)

DVWH

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and

extended temperature ranges) (continued)

write/erase operations — W-controlled writes (continued)

’28F002ASy60

’28F200ASy60

’28F002ASy70

’28F200ASy70

’28F002ASy80

’28F200ASy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Setup time, E before write operation

su(E)

ELWL

Setup time, RP at V

high

to W going

200

100

200

100

200

100

su(RP)

PHHWH

Setup time, V

to W going high

200

100

200

105

100

200

120

100

su(VPP)1

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(W)

w(WH)

Recovery time, RP high to W going

low

800

450

800

450

800

450

rec(RPHW)

PHWL

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and

extended temperature ranges)

write/erase operations — E-controlled writes

’28F002ASy60

’28F200ASy60

’28F002ASy70

’28F200ASy70

’28F002ASy80

’28F200ASy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time, write

110

130

150

c(E)

AVAV

Cycle time, duration of programming

operation

0.3

0.6

0.3

0.6

0.3

0.6

µs

c(E)OP

EHQV1

EHQV2

EHQV3

EHQV4

Cycle time, erase operation (boot

block)

0.3

0.6

0.3

0.6

0.3

0.6

c(E)ERB

c(E)ERP

c(E)ERM

Cycle time, erase operation

(parameter block)

Cycle time, erase operation (main

block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

200

100

200

100

200

100

d(RPR)

PHBR

h(A)

EHAX

h(D)

EHDX

Hold time, W

EHWH

h(W)

Hold time, V

status-register bit

from valid

h(VPP)

h(RP)

QVVL

QVPH

WHPL

Hold time, RP at V

status-register bit

from valid

Hold time, WP from valid status

h(WP)

su(WP)

Setup time, WP before write

operation

105

120

ELPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

105

120

su(A)

su(D)

su(W)

AVEH

DVEH

Setup time, W before write operation

WLEL

Setup time, RP at V

high

to E going

200

100

200

100

200

100

su(RP)

PHHEH

Setup time, V

to E going high

Pulse duration, E low

200

100

200

105

100

200

120

100

su(VPP)2

VPEH

w(E)

ELEH

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002ASy and TMS28F200ASy over recommended ranges of supply voltage (commercial and

extended temperature ranges) (continued)

write/erase operations — E-controlled writes (continued)

’28F002ASy60

’28F200ASy60

’28F002ASy70

’28F200ASy70

’28F002ASy80

’28F200ASy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Pulse duration, E high

w(EH)

EHEL

Recovery time, RP high to E going

low

800

450

800

450

800

450

rec(RPHE)

PHEL

NOTE 15: A – A16 for byte-wide

–1

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

TMS28F002AEy and TMS28F200AEy

The TMS28F002AEy and the TMS28F200AEy configurations offer the auto-select feature of the

TMS28F200ASy with an extended V

to a low 2.7-V to 3.6-V range (3-V nominal). Memory reads can be

performed using a V

= 3 V, allowing for more efficient power consumption than the AS device.

recommended operating conditions for TMS28F002AEy and TMS28F200AEy

MIN

2.7

4.5

NOM

MAX

3.6

UNIT

3-V V

5-V V

range

Supply voltage

During write/read/erase/erase-suspend

5.5

During read only (V

PPL

)

PPL

6.5

5-V V

range

4.5

11.4

5.5

During write/erase/erase-suspend

12-V V

TTL

range

12.6

+ 0.5

3-V V

5-V V

3-V V

5-V V

range

CMOS

TTL

– 0.2

+ 0.2

+ 0.3

+ 0.2

High-level dc input

voltage

CMOS

TTL

– 0.2

– 0.5

0.8

+ 0.2

CMOS

TTL

– 0.2

Low-level dc input

voltage

– 0.3

0.8

CMOS

– 0.2

+ 0.2

lock-out voltage from write/erase (see Note 7)

LKO

RP unlock voltage

lock-out voltage from write/erase

11.4

1.5

PPLK

L suffix

E suffix

°C

Operating free-air temperature during read/erase/program

– 40

NOTE 7: Minimum value at T = 25°C.

word/byte typical write and block-erase performance for TMS28F002AEy and TMS28F200AEy

(see Notes 8 and 9)

5-V V

RANGE

12-V V

RANGE

3-V V

5-V V

3-V V

RANGE

5-V V

PARAMETER

RANGE

TYP

2.4

RANGE

TYP

1.9

RANGE

TYP

1.1

MIN

MAX

MIN

MAX

MIN TYP

MAX

MIN

MAX

Main block erase time

1.3

1.6

Main block byte-program time

Main block word-program time

Parameter/boot block-erase time

1.7

1.4

1.2

4.2

2.1

1.1

0.9

0.8

0.6

0.84

0.8

0.44

0.34

NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.

9. Excludes system-level overhead (all times in seconds)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

TTL

= V

MIN,I

= – 2.5 mA

= – 100 µA

= 5.8 mA

2.4

High-level dc output voltage

CMOS

– 0.4

Low-level dc output voltage

A9 selection code voltage

0.45

12.6

During read algorithm-selection mode

11.4

Input current (leakage), except for A9 when

A9 = V (see Note 10)

= V

MAX,V = 0 V to V

MAX, RP = V

±1

µA

A9 selection code current

RP boot-block unlock current

Output current (leakage)

A9 = V

500

±10

µA

RP = V

= V

MAX,V = 0 V to V

MAX

3-V V

range

standby current (standby)

≤ V

µA

PPS

PPL

PP1

5-V V

3-V V

5-V V

3-V V

5-V V

range

supply current (reset/deep

RP = V

± 0.2 V, V

≤ V

PP CC

power-down mode)

200

supply current (active read)

≥ V

5-V V

3-V V

range,

range

5-V V

range,

range

supply current (active byte-write)

PP2

Programming in progress

(see Notes 11 and 12)

12-V V

3-V V

range,

range

12-V V

range,

range

5-V V

3-V V

range,

range

5-V V

range,

range

supply current (active word-write)

(see Notes 11 and 12)

PP3

Programming in progress

12-V V

3-V V

range,

range

12-V V

5-V V

range,

range

NOTES: 10. DQ15/A is tested for output leakage only.

–1

11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

5-V V

3-V V

range,

range

5-V V

range,

range

supply current (block-erase)

PP4

Block-erase in progress

(see Notes 11 and 12)

12-V V

3-V V

range,

range

12-V V

range,

range

5-V V

3-V V

range,

range

200

5-V V

range,

range

supply current (erase-suspend)

(see Notes 11 and 12)

PP5

Block-erase suspended

µA

12-V V

3-V V

range,

range

12-V V

range,

5-V V

3-V V

5-V V

3-V V

5-V V

range

1.5

µA

TTL-input level

supply current

= V MAX,

(standby)

E = RP = V

CCS

110

130

CMOS-input level

µA

0°C to 70°C

supply current (reset/deep power-down

mode)

µA

RP = V

± 0.2 V

CCL

– 40°C to 85°C

E = V

G = V , I

IH OUT

= 0 mA,

f = 5 MHz, 3-V V range

TTL-input level

E = V

, G = V , I

IH OUT

f = 10 MHz, 5-V V range

supply current

(active read)

CC1

E = V , G = V , I

f = 5 MHz, 3-V V

= 0 mA,

CC OUT

range

CMOS-input level

E = V , G = V , I

f = 10 MHz, 5-V V

CC OUT

range

5-V V

3-V V

range,

range

5-V V

range,

range

supply current (active byte-write)

= V MAX,

(see Notes 11 and 12)

Programming in progress

CC2

12-V V

3-V V

range,

range

12-V V

5-V V

range,

range

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

5-V V

3-V V

range,

range

5-V V

range,

range

supply current (active word-write)

= V MAX,

Programming in progress

CC3

(see Notes 11 and 12)

12-V V

3-V V

range,

range

12-V V

range,

range

5-V V

3-V V

range,

range

5-V V

range,

range

supply current (block-erase)

= V MAX,

(see Notes 11 and 12)

Block-erase in progress

CC4

12-V V

3-V V

range,

range

12-V V

range,

5-V V

3-V V

5-V V

range

supply current (erase-suspend)

= V

MAX, E = V ,

CC IH

(see Notes 11 and 12)

Block-erase suspended

CC5

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

power-up and reset switching characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply

voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7)

’28F002AEy60

’28F200AEy60

’28F002AEy70

’28F200AEy70

’28F002AEy80

’28F200AEy80

ALT.

SYMBOL

PARAMETER

3-V V

RANGE

5-V V

RANGE

3-V V

RANGE

5-V V

RANGE

3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Setup time, RP low to V

PL5V

PL3V

4.5 V MIN (to V

at 3 V MIN or

su(VCC)

3.6 V MAX) (see Note 14)

Access time from address valid to data

valid for V

= 5 V ± 10%

110

800

130

800

150

800

a(DV)

AVQV

(see Note 14)

Setup time, RP high to data valid for

= 5 V ± 10% (see Note 14)

450

su(DV)

PHQV

Hold time, V

high

at 4.5 V (MIN) to RP

µs

h(RP5)

5VPH

Hold time, V

at 3 V (MIN) to RP high

h(RP3)

3VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

switching characteristics for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage

(commercial and extended temperature ranges) (see Table 9 and Figure 7)

read operations

’28F002AEy60

’28F200AEy60

’28F002AEy70

’28F200AEy70

’28F002AEy80

’28F200AEy80

ALT.

SYMBOL

PARAMETER

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16

(see Note 15)

110

130

150

a(A)

AVQV

Access time from E

Access time from G

Cycle time, read

110

130

150

a(E)

a(G)

c(R)

ELQV

GLQV

110

130

150

AVAV

Delay time, E low to low-impedance

output

d(E)

ELQX

Delay time, G low to low-impedance

output

d(G)

GLQX

EHQZ

GHQZ

Disable time, E to high-impedance

output

dis(E)

dis(G)

h(D)

Disable time, G to high-impedance

output

Hold time, DQ valid from A0–A16, E, or

G, whichever occurs first (see Note 15)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Output delay time from RP high

800

450

800

450

800

450

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15

in high-impedance state

FLQZ

Access time from BYTE going high

110

130

150

FHQV

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and

extended temperature ranges)

write/erase operations — W-controlled writes

’28F002AEy60

’28F200AEy60

’28F002AEy70

’28F200AEy70

’28F002AEy80

’28F200AEy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time, write

110

130

150

c(W)

AVAV

Cycle time, duration of programming

operation

0.3

0.6

0.3

0.6

0.3

0.6

µs

c(W)OP

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot

block)

0.3

0.6

0.3

0.6

0.3

0.6

c(W)ERB

c(W)ERP

c(W)ERM

Cycle time, erase operation

(parameter block)

Cycle time, erase operation (main

block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

200

100

200

100

200

100

d(RPR)

PHBR

h(A)

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status

h(VPP)

h(RP)

QVVL

QVPH

WHPL

Hold time, RP at V

status register bit

from valid

Hold time, WP from valid status

h(WP)

su(WP)

Setup time, WP before write

operation

105

120

ELPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

105

120

su(A)

AVWH

su(D)

DVWH

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and

extended temperature ranges) (continued)

write/erase operations — W-controlled writes (continued)

’28F002AEy60

’28F200AEy60

’28F002AEy70

’28F200AEy70

’28F002AEy80

’28F200AEy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Setup time, E before write operation

su(E)

ELWL

Setup time, RP at V

high

to W going

200

100

200

100

200

100

su(RP)

PHHWH

Setup time, V

to W going high

200

100

200

105

100

200

120

100

su(VPP)1

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(W)

w(WH)

Recovery time, RP high to W going

low

800

450

800

450

800

450

rec(RPHW)

PHWL

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and

extended temperature ranges) (continued)

write/erase operations — E-controlled writes

’28F002AEy60

’28F200AEy60

’28F002AEy70

’28F200AEy70

’28F002AEy80

’28F200AEy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time, write

110

130

150

c(E)

AVAV

Cycle time, duration of programming

operation

0.3

0.6

0.3

0.6

0.3

0.6

µs

c(E)OP

EHQV1

EHQV2

EHQV3

EHQV4

Cycle time, erase operation

(boot block)

0.3

0.6

0.3

0.6

0.3

0.6

c(E)ERB

c(E)ERP

c(E)ERM

Cycle time, erase operation

(parameter block)

Cycle time, erase operation

(main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

200

100

200

100

200

100

d(RPR)

PHBR

h(A)

EHAX

h(D)

EHDX

Hold time, W

EHWH

h(W)

Hold time, V

status-register bit

from valid

h(VPP)

h(RP)

QVVL

QVPH

WHPL

Hold time, RP at V

status-register bit

from valid

Hold time, WP from valid status

h(WP)

su(WP)

Setup time, WP before write

operation

105

120

ELPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

105

120

su(A)

su(D)

su(W)

AVEH

DVEH

Setup time, W before write operation

WLEL

Setup time, RP at V

high

to E going

200

100

200

100

200

100

su(RP)

PHHEH

Setup time, V

to E going high

Pulse duration, E low

200

100

200

105

100

200

120

100

su(VPP)2

VPEH

w(E)

ELEH

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AEy and TMS28F200AEy over recommended ranges of supply voltage (commercial and

extended temperature ranges) (continued)

write/erase operations — E-controlled writes (continued)

’28F002AEy60

’28F200AEy60

’28F002AEy70

’28F200AEy70

’28F002AEy80

’28F200AEy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Pulse duration, E high

w(EH)

EHEL

Recovery time, RP high to E going

low

800

450

800

450

800

450

rec(RPHE)

PHEL

NOTE 15: A – A16 for byte-wide

–1

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

TMS28F002AMy and TMS28F200AMy

The TMS28F002AMy and TMS28F200AMy configurations offer a 3-V or 5-V memory read with a 12-V program

and erase. These configurations are intended for low 3.3-V reads and the fast programming offered with the

12-V V and 5-V V . The configurations are offered in two different temperature ranges: 0°C to 70°C and

– 40°C to 85°C.

recommended operating conditions for TMS28F002AMy and TMS28F200AMy

MIN

NOM

MAX

3.6

UNIT

3.3-V V

range

3.3

range

Supply voltage

During write/read/erase/erase-suspend

5-V V

4.5

5.5

During read only (V

PPL

)

PPL

6.5

During write/erase/erase-suspend

12-V V

TTL

range

11.4

12.6

+ 0.5

3.3-V V

range

CMOS

TTL

– 0.2

+ 0.2

+ 0.3

+ 0.2

High-level dc input

voltage

5-V V

range

CMOS

TTL

– 0.2

– 0.5

0.8

+ 0.2

3.3-V V

range

CMOS

TTL

– 0.2

Low-level dc input

voltage

– 0.3

0.8

5-V V

range

CMOS

– 0.2

+ 0.2

lock-out voltage from write/erase

LKO

RP unlock voltage

lock-out voltage from write/erase

11.4

1.5

PPLK

L suffix

E suffix

°C

Operating free-air temperature during read/erase/program

– 40

NOTE 7:. Minimum value at T = 25°C.

word/byte typical write and block-erase performance for TMS28F002AMy and TMS28F200AMy

(see Notes 8 and 9)

12-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

PARAMETER

MIN

TYP

1.3

MAX

TYP MAX

Main block erase time

1.1

1.2

4.2

2.1

Main block byte-program time

Main block word-program time

Parameter/boot block-erase time

1.6

0.8

0.6

0.44

0.34

NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.

9. Excludes system-level overhead (all times in seconds).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

TTL

= V MIN, I

= – 2.5 mA

= – 100 µA

= 5.8 mA

2.4

High-level dc output voltage

CMOS

= V MIN, I

– 0.4

Low-level dc output voltage

A9 selection code voltage

= V MIN, I

0.45

12.6

During read algorithm-selection mode

11.4

Input current (leakage), except for A9 when

A9 = V (see Note 10)

= V MAX,V = 0 V to V MAX, RP = V

CC CC

±1

µA

A9 selection code current

RP boot-block unlock current

Output current (leakage)

A9 = V

500

±10

µA

RP = V

= V MAX,V = 0 V to V MAX

3.3-V V

range

standby current (standby)

≤ V

µA

PPS

PPL

PP1

5-V V

range

3.3-V V

5-V V

range

supply current (reset/deep

RP = V

± 0.2 V, V

≤ V

PP CC

power-down mode)

range

3.3-V V

range

200

supply current (active read)

≥ V

5-V V

range

12-V V

range,

range

3.3-V V

supply current (active byte-write)

Programming in progress

PP2

PP3

(see Notes 11 and 12)

12-V V

5-V V

range,

range

12-V V

range,

range

3.3-V V

supply current (active word-write)

(see Notes 11 and 12)

12-V V

5-V V

range,

range

NOTES: 10. DQ15/A is tested for output leakage only.

–1

11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

12-V V

MIN

MAX

UNIT

range,

3.3-V V

range

supply current (block-erase)

(see Notes 11 and 12)

Block-erase in progress

PP4

PP5

12-V V

range,

range

200

5-V V

12-V V

range,

3.3-V V

range

supply current (erase-suspend)

(see Notes 11 and 12)

Block-erase suspended

µA

12-V V

range,

range

5-V V

3.3-V V

range

1.5

µA

range

TTL-input level

5-V V

supply current

= V max,

(standby)

E = RP = V

CCS

3.3-V V

range

110

130

CMOS-input level

5-V V

µA

0°C to 70°C

supply current (reset/deep power-down

mode)

µA

RP = V

± 0.2 V

CCL

– 40°C to 85°C

E = V

G = V , I = 0 mA,

IH OUT

f = 5 MHz, 3.3-V V range

TTL-input level

E = V

G = V , I

= 0 mA,

IH OUT

f = 10 MHz, 5-V V range

supply current

(active read)

CC1

E = V , G = V , I

f = 5 MHz, 3.3-V V

= 0 mA,

range

CC OUT

CMOS-input level

E = V , G = V , I

f = 10 MHz, 5-V V

= 0 mA,

range

CC OUT

12-V V

range,

3.3-V V

range

supply current (active byte-write)

= V MAX,

(see Notes 11 and 12)

Programming in progress

CC2

12-V V

5-V V

range,

range

12-V V

3.3-V V

range,

range

supply current (active word-write)

= V MAX,

(see Notes 11 and 12)

Programming in progress

CC3

12-V V

5-V V

range,

range

12-V V

3.3-V V

range,

range

supply current (block-erase)

= V MAX,

(see Notes 11 and 12)

Block-erase in progress

CC4

12-V V

5-V V

range,

range

3.3-V V

range

supply current (erase-suspend)

= V MAX,E = V

range

(see Notes 11 and 12)

Block-erase suspended

CC5

5-V V

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

power-up and reset switching characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of supply

voltage (commercial and extended temperature ranges) (see Notes 11, 12, and 13) (see Table 9 and Figure 7)

’28F002AMy60

’28F200AMy60

’28F002AMy70

’28F200AMy70

’28F002AMy80

’28F200AMy80

ALT.

SYMBOL

PARAMETER

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3 V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Setup time, RP low to V

PL5V

PL3V

4.5 V MIN (to V

at 3 V MIN or

su(VCC)

3.6 V MAX) (see Note 14)

Access time from address valid to data

110

800

130

800

150

800

a(DV)

AVQV

valid for V

= 5 V ± 10%

Setup time, RP high to data valid for

= 5 V ± 10%

450

su(DV)

PHQV

Hold time, V

high

at 4.5 V (MIN) to RP

µs

h(RP5)

5VPH

Hold time, V

at 3 V (MIN) to RP high

h(RP3)

3VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

switching characteristics for TMS28F002AMy and TMS28F200AMy over recommended ranges of supply voltage

(commercial and extended temperature ranges) (see Table 9 and Figure 7)

read operations

’28F002AMy60

’28F200AMy60

’28F002AMy70

’28F200AMy70

’28F002AMy80

’28F200AMy80

ALT.

SYMBOL

PARAMETER

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16

(see Note 15)

110

130

150

a(A)

AVQV

Access time from E

Access time from G

Cycle time, read

110

130

150

a(E)

a(G)

c(R)

ELQV

GLQV

110

130

150

AVAV

Delay time, E low to low-impedance

output

d(E)

ELQX

Delay time, G low to low-impedance

output

d(G)

GLQX

EHQZ

GHQZ

Disable time, E to high-impedance

output

dis(E)

dis(G)

h(D)

Disable time, G to high-impedance

output

Hold time, DQ valid from A0–A16, E, or

G, whichever occurs first (see Note 15)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Output delay time from RP high

800

450

800

450

800

450

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15

in high-impedance state

FLQZ

Access time from BYTE going high

110

130

150

FHQV

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AMy and TMS28F200AMy (commercial and extended temperature ranges)

write/erase operations — W-controlled writes

’28F002AMy60

’28F200AMy60

’28F002AMy70

’28F200AMy70

’28F002AMy80

’28F200AMy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time, write

110

130

150

c(W)

AVAV

Cycle time, duration of programming

operation

0.3

0.6

0.3

0.6

0.3

0.6

µs

c(W)OP

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot

block)

0.3

0.6

0.3

0.6

0.3

0.6

c(W)ERB

c(W)ERP

c(W)ERM

Cycle time, erase operation

(parameter block)

Cycle time, erase operation (main

block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

200

100

200

100

200

100

d(RPR)

PHBR

h(A)

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status

h(VPP)

h(RP)

QVVL

Hold time, RP at V

status register bit

from valid

QVPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

105

120

su(A)

su(D)

su(E)

AVWH

DVWH

Setup time, E before write operation

ELWL

Setup time, RP at V

high

to W going

200

100

200

100

200

100

su(RP)

PHHWH

Setup time, V

to W going high

200

100

200

105

100

200

120

100

su(VPP)1

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(W)

w(WH)

Recovery time, RP high to W going

low

800

450

800

450

800

450

rec(RPHW)

PHWL

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AMy and TMS28F200AMy (commercial and extended temperature ranges)

write/erase operations — E-controlled writes

’28F002AMy60

’28F200AMy60

’28F002AMy70

’28F200AMy70

’28F002AMy80

’28F200AMy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Cycle time, write

110

130

150

c(E)

AVAV

Cycle time, duration of programming

operation

0.3

0.6

0.3

0.6

0.3

0.6

µs

c(E)OP

EHQV1

EHQV2

EHQV3

EHQV4

Cycle time, erase operation (boot

block)

0.3

0.6

0.3

0.6

0.3

0.6

c(E)ERB

c(E)ERP

c(E)ERM

Cycle time, erase operation

(parameter block)

Cycle time, erase operation (main

block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

200

100

200

100

200

100

d(RPR)

PHBR

h(A)

EHAX

EHDX

h(D)

Hold time, W

EHWH

h(W)

Hold time, V

status-register bit

from valid

h(VPP)

h(RP)

QVVL

Hold time, RP at V

status-register bit

from valid

QVPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

105

120

su(A)

su(D)

su(W)

AVEH

DVEH

Setup time, W before write operation

WLEL

Setup time, RP at V

high

to E going

200

100

200

100

200

100

su(RP)

PHHEH

Setup time, V

to E going high

VPEH

su(VPP)2

NOTE 15: A – A16 for byte-wide

–1

timing requirements for TMS28F002AMy and TMS28F200AMy (commercial and extended temperature ranges) (continued)

write/erase operations — E-controlled writes

’28F002AMy60

’28F200AMy60

’28F002AMy70

’28F200AMy70

’28F002AMy80

’28F200AMy80

ALT.

SYMBOL

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

3.3-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

105

MAX

MIN

MAX

MIN

120

MAX

MIN

MAX

Pulse duration, E low

Pulse duration, E high

w(E)

ELEH

w(EH)

EHEL

Recovery time, RP high to E going

low

800

450

800

450

800

450

rec(RPHE)

PHEL

NOTE 15: A – A16 for byte-wide

–1

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

TMS28F002AFy and TMS28F200AFy

The TMS28F002AFy and TMS28F200AFy configurations offer a 5-V memory read with a 5-V or 12-V program

and erase. These configurations are intended for systems using a single 5-V power supply. The configurations

are offered in all three temperature ranges: 0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C.

recommended operating conditions for TMS28F002AFy and TMS28F200AFy

MIN

4.5

NOM

MAX

5.5

UNIT

Supply voltage

During write/read/erase/erase-suspend

During read only (V

5-V V

range

)

PPL

6.5

PPL

5-V V

range

4.5

11.4

5.5

During write/erase/erase-suspend

12-V V

TTL

range

12.6

+ 0.3

High-level dc input voltage

Low-level dc input voltage

CMOS

TTL

– 0.2

+ 0.2

0.8

– 0.3

– 0.2

CMOS

+ 0.2

lock-out voltage from write/erase (See Note 7)

11.4

LKO

RP unlock voltage

lock-out voltage from write/erase

1.5

PPLK

L suffix

E suffix

Q suffix

– 40

Operating free-air temperature during read/erase/program

°C

125

NOTE 7: Minimum value at T = 25°C.

word/byte typical write and block-erase performance for TMS28F002AFy and TMS28F200AFy

(see Notes 8 and 9)

5-V V

AND

12-V V

5-V V

AND

RANGES

PARAMETER

MIN

TYP

MAX

MIN

TYP

MAX

Main block erase time

1.9

1.4

0.9

0.8

1.1

1.2

Main block byte-program time

Main block word-program time

4.2

2.1

0.6

Parameter/boot-block erase time

0.34

NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.

9. Excludes system-level overhead (all times in seconds)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

TTL

= V MIN,

= – 2.5 mA

= – 100 µA

= 5.8 mA

2.4

High-level dc

output voltage

CMOS

= V MIN,

– 0.4

Low-level dc output voltage

= V MIN,

0.45

12.6

A9 selection code voltage

During read algorithm-selection mode

11.4

Input current (leakage), except for A9

when A9 = V (see Note 10)

= V MAX, V = 0 V to V MAX, RP = V

±1

µA

A9 selection code current

RP boot-block unlock current

Output current (leakage)

A9 = V

500

±10

µA

RP = V

= V MAX,

= 0 V to V MAX

standby current (standby)

≤ V

5-V V

range

PPS

± 0.2 V, V

supply current (reset/deep

RP = V

≤ V

5-V V

200

µA

PPL

PP1

≥ V

power-down mode)

supply current (active read)

5-V V

range,

range

supply current (active byte-write)

Programming in progress

Block-erase in progress

Block-erase suspended

µA

PP2

PP3

PP4

PP5

(see Notes 11 and 12)

12-V V

5-V V

range,

range

5-V V

range,

range

supply current (active word-write)

(see Notes 11 and 12)

12-V V

5-V V

range,

range

5-V V

range,

range

supply current (block-erase)

(see Notes 11 and 12)

12-V V

5-V V

range,

range

5-V V

range,

range

200

supply current (erase-suspend)

(see Notes 11 and 12)

12-V V

range,

5-V V

range

TTL-input level

130

supply current

(standby)

= V max, E = RP = V

CCS

CMOS-input level

µA

0°C to 70°C

supply current (reset/deep

power-down mode)

– 40°C to 85°C

– 40°C to 125°C

µA

RP = V

± 0.2 V

CCL

E = V

f = 10 MHz, 5-V V

G = V , I

IH OUT

= 0 mA,

TTL-input level

range

= 0 mA,

CC OUT

supply current

(active read)

CC1

E = V , G = V , I

f = 10 MHz, 5-V V

CMOS-input level

range

NOTES: 10. DQ15/A is tested for output leakage only.

–1

11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of

supply voltage and operating free-air temperature, using test conditions given in Table 9 (unless

otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

5-V V

MIN

MAX

UNIT

range,

range

5-V V

supply current (active byte-write)

(see Notes 11 and 12)

= V MAX,

CC CC

Programming in progress

CC2

CC3

12-V V

range,

range

5-V V

range,

range

supply current (active word-write)

(see Notes 11 and 12)

= V MAX,

CC CC

Programming in progress

12-V V

range,

range

5-V V

range,

range

= V MAX

supply current (block-erase)

(see Notes 11 and 12)

= 12 V or 5 V

CC4

12-V V

range,

range

Block-erase in progress

5-V V

supply current (erase-suspend)

(see Notes 11 and 12)

= V MAX,E = V ,

CC CC IH

Block-erase suspended

5-V V

range

CC5

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

power-up and reset switching characteristics for TMS28F002AFy and TMS28F200AFy over

recommended ranges of supply voltage (commercial and extended temperature ranges)

(see Notes 11, 12, and 13) (see Table 9 and Figure 7)

’28F002AFy60 ’28F002AFy70 ’28F002AFy80

’28F200AFy60 ’28F200AFy70 ’28F200AFy80

ALT.

PARAMETER

5 V V

RANGE

5 V V

RANGE

5 V V

RANGE

UNIT

SYMBOL

MIN MAX

Setup time, RP low to V

at 4.5 V MIN

at 3 V MIN or 3.6 V MAX) (see Note 14)

PL5V

PL3V

su(VCC)

(to V

Access time from address valid to data valid for

= 5 V ± 10%

a(DV)

AVQV

PHQV

Setup time, RP high to data valid for

= 5 V ± 10%

450

su(DV)

Hold time, V

at 4.5 V (MIN) to RP high

µs

h(RP5)

5VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

power-up and reset switching characteristics for TMS28F002AFy and TMS28F200AFy over

recommended ranges of supply voltage (automotive temperature range) (see Notes 11, 12, 13)

’28F002AFy70 ’28F002AFy80 ’28F002AFy90

’28F200AFy70 ’28F200AFy80 ’28F200AFy90

ALT.

PARAMETER

5 V V

UNIT

RANGE

SYMBOL

MIN MAX

Setup time, RP low to V

at 4.5 V MIN

at 3 V MIN or 3.6 V MAX) (see Note 14)

PL5V

PL3V

su(VCC)

(to V

Access time from address valid to data valid for

= 5 V ± 10%

a(DV)

AVQV

PHQV

Setup time, RP high to data valid for

= 5 V ± 10%

450

su(DV)

Hold time, V

at 4.5 V (MIN) to RP high

µs

h(RP5)

5VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

switching characteristics for TMS28F002AFy and TMS28F200AFy over recommended ranges of

supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7)

read operations

’28F002AFy60 ’28F002AFy70 ’28F002AFy80

’28F200AFy60 ’28F200AFy70 ’28F200AFy80

ALT.

PARAMETER

5-V V

UNIT

RANGE

SYMBOL

RANGE

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16 (see Note 15)

Access time from E

a(A)

AVQV

a(E)

ELQV

GLQV

Access time from G

a(G)

c(R)

Cycle time, read

AVAV

ELQX

GLQX

EHQZ

GHQZ

Delay time, E low to low-impedance output

Delay time, G low to low-impedance output

Disable time, E to high-impedance output

Disable time, G to high-impedance output

d(E)

d(G)

dis(E)

dis(G)

Hold time, DQ valid from A0–A16, E, or G,

whichever occurs first (see Note 15)

h(D)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Output delay time from RP high

450

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15 in the

high-impedance state

FLQZ

Access time from BYTE going high

FHQV

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

switching characteristics for TMS28F200AFy over recommended ranges of supply voltage

(automotive temperature range) (see Table 9 and Figure 7)

read operations

’28F002AFy70 ’28F002AFy80 ’28F002AFy90

’28F200AFy70 ’28F200AFy80 ’28F200AFy90

ALT.

PARAMETER

5-V V

UNIT

RANGE

SYMBOL

RANGE

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16 (see Note 15)

Access time from E

a(A)

AVQV

a(E)

ELQV

GLQV

Access time from G

a(G)

c(R)

Cycle time, read

AVAV

ELQX

GLQX

EHQZ

GHQZ

Delay time, E low to low-impedance output

Delay time, G low to low-impedance output

Disable time, E to high-impedance output

Disable time, G to high-impedance output

d(E)

d(G)

dis(E)

dis(G)

Hold time, DQ valid from A0–A16, E, or G,

whichever occurs first (see Note 15)

h(D)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Output delay time from RP high

300

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15 in the

high-impedance state

FLQZ

Access time from BYTE going high

FHQV

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F002AFy and TMS28F200AFy (commercial and extended

temperature ranges)

write/erase operations — W-controlled writes

’28F002AFy60 ’28F002AFy70

’28F200AFy60 ’28F200AFy70

’28F002AFy80

’28F200AFy80

ALT.

SYMBOL

5-V V

RANGE

5–V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(W)

AVAV

Cycle time, duration of programming

operation

c(W)OP

c(W)ERB

c(W)ERP

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot block)

0.3

0.6

0.3

0.6

0.3

0.6

Cycle time, erase operation (parameter

block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

c(W)ERM

d(RPR)

h(A)

100

PHBR

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

QVPH

WHPL

Hold time, RP at V

status-register bit

from valid

h(RP)

Hold time, WP from valid status-register bit

Setup time, WP before write operation

Setup time, A0–A16 (see Note 15)

Setup time, DQ

h(WP)

su(WP)

su(A)

ELPH

AVWH

DVWH

su(D)

Setup time, E before write operation

su(E)

ELWL

Setup time, RP at V

to W going high

PHHWH

100

su(RP)

su(VPP)1

w(W)

Setup time, V

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(WH)

rec(RPHW)

Recovery time, RP high to W going low

450

PHWL

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F200AFy (automotive temperature range)

write/erase operations — W-controlled writes

’28F002AFy70

’28F200AFy70

’28F002AFy80

’28F200AFy80

’28F002AFy90

’28F200AFy90

ALT.

SYMBOL

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(W)

AVAV

Cycle time, duration of programming

operation

c(W)OP

c(W)ERB

c(W)ERP

c(W)ERM

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot block)

0.3

0.6

0.3

0.6

0.4

0.7

Cycle time, erase operation (parameter

block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

100

d(RPR)

PHBR

h(A)

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

QVPH

WHPL

Hold time, RP at V

status-register bit

from valid

h(RP)

Hold time, WP from valid status-register bit

Setup time, WP before write operation

Setup time, A0–A16 (see Note 15)

Setup time, DQ

h(WP)

su(WP)

su(A)

ELPH

AVWH

DVWH

su(D)

Setup time, E before write operation

su(E)

ELWL

Setup time, RP at V

to W going high

PHHWH

100

su(RP)

su(VPP)1

w(W)

to W going high

Setup time, V

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(WH)

rec(RPHW)

Recovery time, RP high to W going low

220

PHWL

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F002AFy and TMS28F200AFy (commercial and extended

temperature ranges)

write/erase operations — E-controlled writes

’28F002AFy60

’28F200AFy60

’28F002AFy70

’28F200AFy70

’28F002AFy80

’28F200AFy80

ALT.

SYMBOL

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(E)

AVAV

Cycle time, duration of programming operation

Cycle time, erase operation (boot block)

Cycle time, erase operation (parameter block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

c(E)OP

c(E)ERB

c(E)ERP

c(E)ERM

d(RPR)

h(A)

EHQV1

EHQV2

EHQV3

EHQV4

0.3

0.6

0.3

0.6

0.3

0.6

100

PHBR

EHAX

EHDX

h(D)

Hold time, W

EHWH

h(W)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

QVPH

WHPL

Hold time, RP at V

bit

from valid status-register

h(RP)

Hold time, WP from valid status-register bit

Setup time, WP before write operation

Setup time, A0–A16 (see Note 15)

Setup time, DQ valid

h(WP)

su(WP)

su(A)

ELPH

AVEH

DVEH

su(D)

Setup time, W before write operation

su(W)

su(RP)

su(VPP)2

w(E)

WLEL

Setup time, RP at V

to E going high

100

PHHEH

Setup time, V

VPEH

Pulse duration, E low

ELEH

EHEL

PHEL

Pulse duration, E high

w(EH)

rec(RPHE)

Recovery time, RP high to E going low

450

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F200AFy (automotive temperature range)

write/erase operations — E-controlled writes

’28F002AFy70

’28F200AFy70

’28F002AFy80

’28F200AFy80

’28F002AFy90

’28F200AFy90

ALT.

SYMBOL

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(E)

AVAV

Cycle time, duration of programming

operation

c(E)OP

c(E)ERB

c(E)ERP

EHQV1

EHQV2

EHQV3

EHQV4

Cycle time, erase operation (boot block)

0.3

0.6

0.3

0.6

0.4

0.7

Cycle time, erase operation (parameter

block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

c(E)ERM

d(RPR)

h(A)

100

PHBR

EHAX

EHDX

EHEH

h(D)

Hold time, W

h(W)

Hold time, V

from valid status-register bit

QVVL

h(VPP)

Hold time, RP at

status-register bit

from valid

h(RP)

QVPH

Hold time, WP from valid status-register bit

Setup time, WP before write operation

Setup time, A0–A16 (see Note 15)

Setup time, DQ valid

h(WP)

WHPL

su(WP)

su(A)

ELPH

AVEH

DVEH

su(D)

Setup time, W before write operation

su(W)

su(RP)

su(VPP)2

w(E)

WLEL

Setup time, RP at V

to E going high

100

to E going high

PHHEH

Setup time, V

VPEH

Pulse duration, E low

ELEH

EHEL

PHEL

Pulse duration, E high

w(EH)

rec(RPHE)

Recovery time, RP high to E going low

300

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

TMS28F002AZy and TMS28F200AZy

The TMS28F002AZy and TMS28F200AZy configurations offer a 5-V memory read with a 12-V program and

a 12-V erase for fast programming and erasing times. These configurations are offered in three temperature

ranges: 0°C to 70°C,– 40°C to 85°C and – 40°C to 125°C.

recommended operating conditions for TMS28F002AZy and TMS28F200AZy

MIN

4.5

NOM

MAX

5.5

UNIT

Supply voltage

During write/read/erase/erase-suspend

During read only

5-V V

range

PPL

6.5

During write/erase/erase-suspend

12-V V

TTL

range

11.4

12.6

+ 0.3

High-level dc input voltage

Low-level dc input voltage

CMOS

TTL

– 0.2

+ 0.2

0.8

– 0.3

– 0.2

CMOS

+ 0.2

lock-out voltage from write/erase (see Note 7)

11.4

LKO

RP unlock voltage

lock-out voltage from write/erase

1.5

PPLK

L suffix

E suffix

Q suffix

– 40

Operating free-air temperature during read/erase/program

°C

125

NOTE 7:. Minimum value at T = 25°C.

word/byte typical write and block-erase performance for TMS28F002AZy and TMS28F200AZy

(see Notes 8 and 9)

12-V V

5-V V

AND

RANGES

PARAMETER

MIN

TYP

MAX

Main block-erase time

1.1

1.2

Main block-byte program time

Main block-word program time

Parameter/boot-block erase time

4.2

2.1

0.6

0.34

NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.

9. Excludes system-level overhead (all times in seconds)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

electrical characteristics for TMS28F002AZy and TMS28F200AZy over recommended ranges of

supply voltage and operating free-air temperature using test conditions given in Table 9 (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

= V MIN,

= – 2.5 mA

TTL

2.4

High-level dc

output voltage

= V MIN,

= – 100 µA

CMOS

– 0.4

= V MIN,

= 5.8 mA

Low-level dc output voltage

0.45

12.6

±1

During read algorithm-selection mode

V = V MAX,

A9 selection code voltage

11.4

Input current (leakage), except for A9

when A9 = V (see Note 10)

µA

V = 0 V to V MAX, RP = V

A9 selection code current

A9 = V

500

µA

RP boot-block unlock current

RP = V

= V MAX,

Output current (leakage)

±10

µA

= 0 V to V max

standby current (standby)

supply current (reset/deep

≤ V

5-V V

range

PPS

PPL

PP1

PP2

± 0.2 V, V

RP = V

≤ V

≥ V

power-down mode)

supply current (active read)

200

supply current (active byte-write)

12-V V

5-V V

range,

range

Programming in progress

Block-erase in progress

Block-erase suspended

(see Notes 11 and 12)

supply current (active word-write)

12-V V

5-V V

range,

range

(see Notes 11 and 12)

µA

PP3

PP4

PP5

supply current (block-erase)

12-V V

5-V V

range,

range

(see Notes 11 and 12)

supply current (erase-suspend)

12-V V

range,

range

(see Notes 11 and 12)

200

5-V V

TTL-input level

130

supply current

= V max,

(standby)

E = RP = V

5-V V

range

CCS

CCL

CMOS-input level

µA

0°C to 70°C

supply current (reset/deep

power-down mode)

– 40°C to 85°C

– 40°C to 125°C

µA

RP = V

± 0.2 V

E = V

f = 10 MHz, 5-V V

G = V

= 0 mA,

OUT

range

TTL-input level

supply current

(active read)

CC1

E = V , G = V

f = 10 MHz, 5-V V

CC, OUT

range

CMOS-input level

supply current (active byte-write)

= V MAX,

12-V V

5-V V

range,

(see Notes 11 and 12)

range

CC2

CC3

CC4

CC5

Programming in progress

supply current (active word-write)

= V MAX,

12-V V

5-V V

range,

range

(see Notes 11 and 12)

Programming in progress

supply current (block-erase)

= V MAX,

12-V V

range,

range

(see Notes 11 and 12)

Block erase in progress

= V MAX, E = V ,

5-V V

supply current (erase-suspend)

(see Notes 11 and 12)

5-V V

range

Block erase suspended

NOTES: 10. DQ15/A is tested for output leakage only.

–1

11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

power-up and reset switching characteristics for TMS28F002AZy and TMS28F200AZy over

recommended ranges of supply voltage (commercial and extended temperature ranges)

(see Notes 11, 12, and 13) (see Table 9 and Figure 7)

’28F002AZy60 ’28F002AZy70 ’28F002AZy80

’28F200AZy60 ’28F200AZy70 ’28F200AZy80

ALT.

PARAMETER

5-V V

UNIT

RANGE

SYMBOL

RANGE

MIN MAX

Setup time, RP low to V

at 4.5 V MIN

at 3 V MIN or 3.6 V MAX) (see Note 14)

PL5V

PL3V

µs

su(VCC)

(to V

Address valid to data valid for V

= 5 V ± 10%

a(DV)

Setup time, RP high to data valid for

= 5 V ± 10%

AVQV

450

su(DV)

h(RP5)

PHQV

Hold time, V

at 4.5 V (MIN) to RP high

5VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

power-up and reset switching characteristics for TMS28F002AZy and TMS28F200AZy over

recommended ranges of supply voltage (automotive temperature range) (see Notes 11, 12, and 13)

’28F002AZy70 ’28F002AZy80 ’28F002AZy90

’28F200AZy70 ’28F200AZy80 ’28F200AZy90

ALT.

PARAMETER

5-V V

UNIT

RANGE

SYMBOL

RANGE

MIN MAX

Setup time, RP low to V

at 4.5 V MIN

at 3 V MIN or 3.6 V MAX) (see Note 14)

PL5V

PL3V

µs

su(VCC)

(to V

Address valid to data valid for V

= 5 V ± 10%

a(DV)

Setup time, RP high to data valid for

= 5 V ± 10%

AVQV

450

su(DV)

h(RP5)

PHQV

Hold time, V

at 4.5 V (MIN) to RP high

5VPH

NOTES: 11. Characterization data available

12. All ac current values are RMS unless otherwise noted.

13. E and G are switched low after power up.

14. The power supply can switch low concurrently with RP going low.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

switching characteristics for TMS28F002AZy and TMS28F200AZy over recommended ranges of

supply voltage (commercial and extended temperature ranges) (see Table 9 and Figure 7)

read operations

’28F002AZy60 ’28F002AZy70 ’28F002AZy80

’28F200AZy60 ’28F200AZy70 ’28F200AZy80

ALT.

PARAMETER

5-V V

UNIT

RANGE

SYMBOL

RANGE

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16 (see Note 15)

Access time from E

a(A)

AVQV

a(E)

ELQV

GLQV

Access time from G

a(G)

c(R)

Cycle time, read

AVAV

ELQX

GLQX

EHQZ

GHQZ

Delay time, E low to low-impedance output

Delay time, G low to low-impedance output

Disable time, E to high-impedance output

Disable time, G to high-impedance output

d(E)

d(G)

dis(E)

dis(G)

Hold time, DQ valid from A0–A16, E, or G,

whichever occurs first (see Note 15)

h(D)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Output delay time from RP high

450

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15 in

high-impedance state

FLQZ

Access time from BYTE going high

FHQV

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

switching characteristics for TMS28F200AZy over recommended ranges of supply voltage

(automotive temperature range) (see Table 9 and Figure 7)

read operations

’28F002AZy70 ’28F002AZy80

’28F200AZy70 ’28F200AZy80

’28F002AZy90

’28F200AZy90

ALT.

SYMBOL

PARAMETER

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

Access time from A0–A16 (see Note 15)

Access time from E

a(A)

AVQV

a(E)

ELQV

GLQV

Access time from G

a(G)

c(R)

Cycle time, read

AVAV

ELQX

GLQX

EHQZ

GHQZ

Delay time, E low to low-impedance output

Delay time, G low to low-impedance output

Disable time, E to high-impedance output

Disable time, G to high-impedance output

d(E)

d(G)

dis(E)

dis(G)

Hold time, DQ valid from A0–A16, E, or G,

whichever occurs first (see Note 15)

h(D)

AXQX

ELFL

ELFH

Setup time, BYTE from E low

Output delay time from RP high

300

su(EB)

d(RP)

dis(BL)

a(BH)

PHQV

Disable time, BYTE low to DQ8–DQ15 in

high-impedance state

FLQZ

Access time from BYTE going high

FHQV

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F002AZy and TMS28F200AZy (commercial and extended

temperature ranges)

write/erase operations — W-controlled writes

’28F002AZy60 ’28F002AZy70

’28F200AZy60 ’28F200AZy70

’28F002AZy80

’28F200AZy80

ALT.

SYMBOL

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(W)

AVAV

Cycle time, duration of programming

operation

c(W)OP

c(W)ERB

c(W)ERP

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot block)

0.3

0.6

0.3

0.6

0.3

0.6

Cycle time, erase operation (parameter

block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

c(W)ERM

d(RPR)

h(A)

100

PHBR

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

Hold time, RP at V

status-register bit

from valid

h(RP)

QVPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

su(A)

AVWH

su(D)

DVWH

Setup time, E before write operation

su(E)

ELWL

Setup time, RP at V

to W going high

PHHWH

100

su(RP)

su(VPP)1

w(W)

to W going high

Setup time, V

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(WH)

rec(RPHW)

Recovery time, RP high to W going low

450

PHWL

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F200AZy (automotive temperature ranges)

write/erase operations — W-controlled writes

’28F002AZy70 ’28F002AZy80 ’28F002AZy90

’28F200AZy70 ’28F200AZy80 ’28F200AZy90

ALT.

SYMBOL

5-V V 5-V V 5-V V

UNIT

RANGE

CC CC

RANGE RANGE

MIN MAX

MIN MAX MIN MAX

Cycle time, write

µs

c(W)

AVAV

Cycle time, duration of programming

operation

c(W)OP

c(W)ERB

c(W)ERP

c(W)ERM

WHQV1

WHQV2

WHQV3

WHQV4

Cycle time, erase operation (boot block)

0.3

0.6

0.3

0.6

0.4

0.7

Cycle time, erase operation (parameter

block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

100

d(RPR)

PHBR

h(A)

WHAX

WHDX

WHEH

h(D)

Hold time, E

h(E)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

Hold time, RP at V

status-register bit

from valid

h(RP)

QVPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ

su(A)

AVWH

su(D)

DVWH

Setup time, E before write operation

su(E)

ELWL

Setup time, RP at V

to W going high

PHHWH

100

su(RP)

su(VPP)1

w(W)

to W going high

Setup time, V

VPWH

WLWH

WHWL

Pulse duration, W low

Pulse duration, W high

w(WH)

rec(RPHW)

Recovery time, RP high to W going low

220

PHWL

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F002AZy and TMS28F200AZy (commercial and extended

temperature ranges)

write/erase operations — E-controlled writes

’28F002AZy60 ’28F002AZy70

’28F200AZy60 ’28F200AZy70

’28F002AZy80

’28F200AZy80

ALT.

SYMBOL

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(E)

AVAV

Cycle time, duration of programming operation

Cycle time, erase operation (boot block)

Cycle time, erase operation (parameter block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

c(E)OP

c(E)ERB

c(E)ERP

c(E)ERM

d(RPR)

h(A)

EHQV1

EHQV2

EHQV3

EHQV4

0.3

0.6

0.3

0.6

0.3

0.6

100

PHBR

EHAX

EHDX

h(D)

Hold time, W

EHWH

h(W)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

Hold time, RP at V

bit

from valid status-register

h(RP)

QVPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ valid

su(A)

AVEH

su(D)

DVEH

Setup time, W before write operation

su(W)

su(RP)

su(VPP)2

w(E)

WLEL

Setup time, RP at V

to E going high

100

to E going high

PHHEH

Setup time, V

VPEH

Pulse duration, E low

ELEH

EHEL

PHEL

Pulse duration, E high

w(EH)

rec(RPHE)

Recovery time, RP high to E going low

450

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

timing requirements for TMS28F200AZy (automotive temperature range)

write/erase operations — E-controlled writes

’28F002AZy70

’28F200AZy70

’28F002AZy80

’28F200AZy80

’28F002AZy90

’28F200AZy90

ALT.

SYMBOL

5-V V

RANGE

5-V V

RANGE

5-V V

RANGE

UNIT

MIN MAX

Cycle time, write

µs

c(E)

AVAV

Cycle time, duration of programming

operation

c(E)OP

c(E)ERB

c(E)ERP

EHQV1

EHQV2

EHQV3

EHQV4

Cycle time, erase operation (boot block)

0.3

0.6

0.3

0.6

0.4

0.7

Cycle time, erase operation (parameter

block)

Cycle time, erase operation (main block)

Delay time, boot-block relock

Hold time, A0–A16 (see Note 15)

Hold time, DQ valid

c(E)ERM

d(RPR)

h(A)

100

PHBR

EHAX

h(D)

EHDX

Hold time, W

EHWH

h(W)

Hold time, V

from valid status-register bit

h(VPP)

QVVL

Hold time, RP at V

status-register bit

from valid

h(RP)

QVPH

Setup time, A0–A16 (see Note 15)

Setup time, DQ valid

su(A)

AVEH

su(D)

DVEH

Setup time, W before write operation

su(W)

su(RP)

su(VPP)2

w(E)

WLEL

Setup time, RP at V

to E going high

100

to E going high

PHHEH

Setup time, V

VPEH

Pulse duration, E low

ELEH

EHEL

PHEL

Pulse duration, E high

w(EH)

rec(RPHE)

Recovery time, RP high to E going low

300

NOTE 15: A –A16 for byte-wide

–1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

RP (P)

5.0 V

4.5 V

3.3 V

(3 V, 5 V)

3.0 V

h(RP3)

0 V

su(VCC)

h(RP5)

Address (A)

Data (D)

Valid

a(DV)

Valid 3.3 Outputs

Valid 5.0 Outputs

su(DV)

Figure 10. Power-Up Timing and Reset Switching

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

c(R)

Address Valid

a(A)

–A16 (byte-wide)

–1

A0–A16 (word-wide)

dis(E)

a(E)

dis(G)

a(G)

d(G)

h(D)

d(E)

DQ0–DQ7 (byte-wide)

DQ0–DQ15 (word-wide)

Hi-Z

d(RP)

Figure 11. Read-Cycle Timing

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

Power Up

and

Standby

–A16

Write

Program-Setup

Command

Write Valid

Address or

Data

Automated

Byte-/Word-

Programming

Write

Read-Array

Command

Read Status-

–1

(byte-wide)

A0–A16

(word-wide)

c(W)

su(A)

h(A)

su(E)

h(E)

c(W)OP

w(WH)

w(W)

su(D)

h(D)

Data

Valid SR

FFh

Hi-Z

DQ0– DQ7

(byte-wide)

DQ0– DQ15

(word-wide)

Hi-Z

40h or 10h

su(RP)

rec(RPHW)

h(RP)

su(WP)

h(WP)

h(VPP)

su(VPP)1

Figure 12. Write-Cycle Timing (W-Controlled Write)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

Power Up

and

Write

Program-Setup

Command

Write Valid

Address

And Data

Automated

Byte-/Word-

Programming

Write

Read-Array

Command

Read Status

Standby

–A16

–1

(byte-wide)

A0–A16

(word-wide)

c(E)

su(A)

h(A)

su(W)

h(W)

c(E)OP

w(EH)

w(E)

Data

su(D)

h(D)

Valid SR

FFh

Hi-Z

DQ0–DQ7

(byte-wide)

DQ0–DQ15

(word-wide)

Hi-Z

40h or 10h

rec(RPHE)

su(RP)

h(RP)

su(WP)

h(WP)

h(VPP)

su(VPP)2

Figure 13. Write-Cycle Timing (E-Controlled Write)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

Power

Up and

Standby

Write

Erase-Setup

Command

Write Erase-

Confirm

Command

Write

Read-Array

Command

Automated

Erase

Read Status-

–A16

–1

(byte-wide)

A0–A16

(word-wide)

c(W)

su(A)

h(A)

su(E)

h(E)

c(W)ERB

c(W)ERP

c(W)ERM

w(WH)

w(W)

D0h

su(D)

h(D)

Valid SR

DQ0–DQ7

(byte-wide)

DQ0–DQ15

(word-wide)

FFh

Hi-Z

20h

rec(RPHW)

su(RP)

h(RP)

su(WP)

h(WP)

h(VPP)

su(VPP)1

PPH

PPL

Figure 14. Erase-Cycle Timing (W-Controlled Write)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

Power Up

and

Standby

–A16

Write

Erase-Setup

Command

Write Erase-

Confirm

Command

Write

Read-Array

Command

Automated

Erase

Read Status-

–1

(byte-wide)

A0–A16

(word-wide)

c(E)

su(A)

h(A)

su(W)

h(W)

c(E)ERB

c(E)ERP

c(E)ERM

w(EH)

w(E)

D0h

su(D)

h(D)

Valid SR

DQ0–DQ7

(byte-wide)

DQ0–DQ15

(word-wide)

FFh

Hi-Z

20h

rec(RPHE)

su(RP)

h(RP)

su(WP)

h(WP)

h(VPP)

su(VPP)2

Figure 15. Erase-Cycle Timing (E-Controlled Write)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

–A16

–1

(byte-wide)

A0–A16

Address Valid

(word-wide)

c(R)

a(A)

a(E)

dis(E)

dis(G)

a(G)

BYTE

h(D)

su(EB)

Hi-Z

DQ0–DQ7

Byte DQ0–DQ7

Word DQ0–DQ7

d(G)

d(E)

DQ8–DQ14

Hi-Z

a(A)

dis(BL)

Word DQ8–DQ14

Hi-Z

DQ15/A

–1

Input

–1

Word DQ15

Figure 16. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

PARAMETER MEASUREMENT INFORMATION

–A16

–1

(byte-wide)

A0–A16

Address Valid

(word-wide)

c(R)

a(A)

a(E)

dis(E)

dis(G)

h(D)

a(G)

BYTE

su(EB)

Byte DQ0–DQ7

a(BH)

Hi-Z

DQ0–DQ7

d(G)

Word DQ0–DQ7

d(E)

DQ8–DQ14

Hi-Z

Word DQ8–DQ14

Word DQ15

DQ15/A

–1

Input

–1

Hi-Z

Figure 17. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

MECHANICAL DATA

DBJ (R-PDSO-G44)

PLASTIC SMALL-OUTLINE PACKAGE

0,45

0,35

1,27

0,16

13,40

13,20

16,10

15,90

0,15 NOM

28,30

28,10

Gage Plane

0,25

0°–8°

0,80

Seating Plane

0,10

2,625 MAX

0,50 MIN

4073325/A 10/94

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

MECHANICAL DATA

DCD (R-PDSO-G**)

PLASTIC DUAL SMALL-OUTLINE PACKAGE

40 PIN SHOWN

NO. OF

PINS**

MAX

MIN

0.402

(10,20) (9,80)

0.385

0.476

(12,10) (11,90)

0.469

0.020 (0,50)

0.012 (0,30)

0.004 (0,10)

0.008 (0,21)

0.728 (18,50)

0.720 (18,30)

0.795 (20,20)

0.780 (19,80)

0.041 (1,05)

0.037 (0,95)

0.047 (1,20) MAX

0.006 (0,15)

NOM

Seating Plane

0.004 (0,10)

0.028 (0,70)

0.020 (0,50)

0.010 (25,00) NOM

4073307/B 07/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

TMS28F002ZT90BDBJE [TI]

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