TMS28F010A-12C4NL4 [TI]
1048576-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY; 1048576位闪速电可擦可编程只读存储器
| 型号： | TMS28F010A-12C4NL4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1048576-BIT FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY |
| 文件： | 总22页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
N PACKAGE
•
•
Organization . . . 128K × 8-Bit Flash Memory
Pin Compatible With Existing 1-Megabit
EPROMs
(TOP VIEW)
V
V
CC
W
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PP
•
•
•
V
Tolerance ±10%
CC
A16
A15
A12
A7
2
All Inputs/Outputs TTL Compatible
Maximum Access/Minimum Cycle Time
NC
A14
A13
A8
3
4
’28F010A-10
’28F010A-12
’28F010A-15
’28F010A-17
100 ns
120 ns
150 ns
170 ns
5
A6
6
A5
A9
7
A4
A11
G
8
•
•
Industry-Standard Programming Algorithm
PEP4 Version Available With 168-Hour
Burn-In and Choice of Operating
Temperature Ranges
Chip Erase Before Reprogramming
10000 and 1000 Program/Erase-Cycle
Versions Available
A3
9
A2
A10
E
10
11
12
13
14
15
16
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
•
•
DQ0
DQ1
DQ2
•
Low Power Dissipation (V
– Active Write . . . 55 mW
– Active Read . . . 165 mW
= 5.5 V)
CC
V
SS
– Electrical Erase . . . 82.5 mW
– Standby . . . 0.55 mW
(CMOS-Input Levels)
FM PACKAGE
(TOP VIEW)
•
Automotive Temperature Range
– 40°C to 125°C
4
5
3
2
1
32 31 30
29
description
A7
A6
A14
A13
A8
6
28
27
26
25
24
23
22
21
The TMS28F010A is a 1048576-bit, program-
7
A5
mable read-only memory that can be electrically
bulk-erased and reprogrammed. It is available in
10000 and 1000 program/erase-endurance-
cycle versions.
8
A4
A9
9
A3
A11
G
10
11
12
13
A2
A1
A10
E
The TMS28F010A Flash EEPROM is offered in a
dual in-line plastic package (N suffix) designed for
insertion in mounting-hole rows on 15,2-mm
(600-mil) centers, a 32-lead plastic leaded
chip-carrier package using 1,25-mm (50-mil) lead
spacing (FM suffix), a 32-lead thin small-outline
package (DD suffix), and a reverse pinout TSOP
package (DU suffix).
A0
DQ0
DQ7
14 15 16 17 18 19 20
The TMS28F010A is characterized for operation
in temperature ranges of 0°C to 70°C (NL, FML,
DDL, andDULsuffixes), –40°Cto85°C(NE, FME,
DDE, and DUE suffixes), and –40°C to 125°C
(NQ, FMQ, DDQ, and DUQ suffixes). All package
types are offered with 168-hour burn-in (4 suffix).
PIN NOMENCLATURE
A0–A16
DQ0–DQ7
Address Inputs
Data In/Data Out
Chip Enable
E
G
NC
Output Enable
No Internal Connection
5-V Power Supply
12-V Power Supply
Ground
V
V
V
CC
PP
SS
W
Write Enable
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
DD PACKAGE
(TOP VIEW)
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
G
2
A10
E
A8
3
4
A13
A14
NC
W
DQ7
DQ6
DQ5
DQ4
DQ3
5
6
7
8
V
CC
9
V
V
SS
PP
10
11
12
13
14
15
16
A16
DQ2
DQ1
DQ0
A0
A15
A12
A7
A6
A1
A5
A2
A4
A3
DU PACKAGE
REVERSE PINOUT
(TOP VIEW)
G
A10
E
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
2
3
A8
4
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
NC
W
5
6
7
8
V
V
CC
PP
9
V
SS
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
A16
A15
A12
A7
A1
A6
A2
A5
A3
A4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
device symbol nomenclature
TMS28F010A
-12 C4 FM
L
4
PEP4 Burn-In
4 = 168-Hour Burn-In
(blank if no burn-in)
Temperature Range Designator
L
E
Q
=
=
=
0°C to 70°C
– 40°C to 85°C
– 40°C to 125°C
Package Designator
N = Plastic Dual In-Line Package
FM = Plastic Leaded Chip Carrier
DD = Thin Small-Outline Package
DU = Thin Small-Outline Package,
Reverse Pinout
Program/Erase Endurance
C4 = 10 000 Cycles
C3 = 1 000 Cycles
Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
†
logic symbol
FLASH
EEPROM
131 072 × 8
12
11
10
9
0
A0
A1
A2
A3
A4
A5
A6
8
7
6
5
A7
27
26
23
25
4
28
29
3
0
A8
A9
A
131 071
A10
A11
A12
A13
A14
A15
A16
2
16
22
E
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
24
31
G
W
13
DQ0
A, 3D
4
A, Z4
14
15
17
18
19
20
21
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the N package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
functional block diagram
DQ0–DQ7
8
Erase-Voltage Switch
V
PP
Input/Output Buffers
State Control
W
To Array
Program/Erase
Stop Timer
Program-Voltage
Switch
Command Register
STB
Data Latch
Chip-Enable and
E
Output-Enable
Logic
G
STB
A
d
d
r
e
s
s
Column Decoder
Row Decoder
Column Gating
A0–A16
17
1048576-Bit
Array Matrix
L
a
t
c
h
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
Table 1. Operation Modes
FUNCTION
†
V
PP
(1)
MODE
E
(22)
G
(24)
A0
(12)
A9
(26)
W
(31)
DQ0–DQ7
(13–15, 17–21)
Read
V
PPL
V
PPL
V
PPL
V
V
V
X
X
X
X
X
X
V
V
Data Out
IL
IL
IH
Output Disable
V
IH
HI-Z
IL
IH
Read
Standby and Write Inhibit
V
IH
X
X
HI-Z
V
Mfr Equivalent Code 89h
IL
Algorithm-Selection Mode
V
PPL
V
IL
V
IL
V
ID
V
IH
V
IH
Device Equivalent Code B4h
Read
V
PPH
V
PPH
V
PPH
V
PPH
V
V
V
V
X
X
V
V
Data Out
HI-Z
IL
IL
IH
Output Disable
Standby and Write Inhibit
Write
X
X
X
X
X
X
Read/
Write
IL
IH
IH
V
IH
X
X
HI-Z
V
IL
V
IH
Data In
V
IL
NOTE: X can be V or V
.
IL
IH
is the programming voltage specified for the device. For more details, refer to the recommended operating conditions.
†
V
PPL
≤ V
+ 2 V; V
CC PPH
operation
read/output disable
When the outputs of two or more TMS28F010As are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
read the output of the TMS28F010A, a low-level signal is applied to the E and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active I
current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 µA with a
CC
highCMOSlevelonE. In this mode, all outputs are in the high-impedance state. The TMS28F010A draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
agorithms. ThismodeisactivatedwhenA9(pin26)isforcedtoV . Twoidentifierbytesareaccessedbytoggling
ID
A0. All other addresses must be held low. A0 low selects the manufacturer equivalent code 89h, and A0 high
selects the device equivalent code B4h, as shown in the algorithm-selection mode table below:
PINS
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
89
Manufacturer Equivalent Code
Device Equivalent Code
V
1
1
0
0
0
1
0
1
1
0
0
1
0
0
1
0
IL
V
IH
B4
NOTE: E = G = V , A1–A8 = V , A9 = V , A10–A16 = V , V
IL IL ID IL PP
= V
.
PPL
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Afterwards, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
command register
The command register controls the program and erase functions of the TMS28F010A. The algorithm-selection
mode can be activated using the command register in addition to the above method. When V is high, the
PP
contents of the command register and the function being performed can be changed. The command register
is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse, while
the data is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation.
power supply considerations
Eachdeviceshouldhavea0.1-µFceramiccapacitorconnectedbetweenV andV tosuppresscircuitnoise.
CC
SS
Changes in current drain on V require it to have a bypass capacitor as well. Printed-circuit traces for both
PP
power supplies should be appropriate to handle the current demand.
Table 2. Command Definitions
REQUIRED
BUS
CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
†
†
OPERATION
ADDRESS
DATA
OPERATION
ADDRESS
DATA
Read
1
3
Write
X
00h
Read
RA
RD
0000
0001
89h
B4h
Algorithm-Selection Mode
Write
X
90h
Read
Set-Up-Erase/Erase
Erase Verify
2
2
2
2
2
Write
Write
Write
Write
Write
X
EA
X
20h
A0h
40h
C0h
FFh
Write
Read
Write
Read
Write
X
X
20h
EVD
PD
Set-Up-Program/Program
Program Verify
Reset
PA
X
X
PVD
FFh
X
X
†
Modes of operation are defined in Table 1.
Legend:
EA
RA
Address of memory location to be read during erase verify.
Address of memory location to be read.
PA
Address of memory location to be programmed. Address is latched on the falling edge of W.
Data read from location RA during the read operation.
Data read from location EA during erase verify.
Data to be programmed at location PA. Data is latched on the rising edge of W.
Data read from location PA during program verify.
RD
EVD
PD
PVD
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
command definitions
read command
Memory contents can be accessed while V is high or low. When V is high, writing 00h into the command
PP
PP
register invokes the read operation. When the device is powered up, the default contents of the command
register are 00h and the read operation is enabled. The read operation remains enabled until a different valid
command is written to the command register.
algorithm-selection mode command
The algorithm-selection mode is activated by writing 90h into the command register. The manufacturer
equivalent code (89h) is identified by the value read from address location 0000h, and the device equivalent
code (B4h) is identified by the value read from address location 0001h.
set-up-erase/erase commands
Theerase-algorithminitiateswithE=V ,W=V ,G=V ,V =V
,andV =5V.Toentertheerasemode,
CC
IL
IL
IH PP
PPH
write the set-up-erase command, 20h, into the command register. After the TMS28F010A is in the erase mode,
writing a second erase command, 20h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of W and ends on the rising edge of the next W. The erase operation requires
10 ms to complete before the erase-verify command, A0h, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a valid erase verify, read, or reset
command is received.
erase-verify command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, A0h, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a valid command is written to the
command register.
To determine whether or not all the bytes have been erased, the TMS28F010A applies a margin voltage to each
byte. If FFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation
continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation
needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing
the TMS28F010A.
set-up-program/program commands
The programming algorithm initiates with E = V , W = V , G = V , V = V
, and V
= 5 V. To enter the
IL
IL
IH PP
PPH
CC
programming mode, write the set-up-program command, 40h, into the command register. The programming
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W,
and data is latched internally on the rising edge of W. The programming operation begins on the rising edge of
W and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion before
the program-verify command, C0h, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a valid program-verify, read, or reset
command is received.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
program-verify command
The TMS28F010A can be programmed sequentially or randomly because it is programmed one byte at a time.
Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify
the most recently programmed byte. To invoke the program-verify operation, C0h must be written into the
command register. The program-verify operation ends on the rising edge of W.
While verifying a byte, the TMS28F010A applies an internal margin voltage to the designated byte. If the true
data and programmed data match, programming continues to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
reset command
To reset the TMS28F010A after set-up-erase command or set-up-program command operations without
changing the contents in memory, write FFh into the command register two consecutive times. After executing
the reset command, a valid command must be written into the command register to change to a new state.
Fastwrite algorithm
The TMS28F010A is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 1. This
algorithm programs in a nominal time of two seconds.
Fasterase algorithm
The TMS28F010A is erased using the Texas Instruments Fasterase algorithm shown in Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
To reduce total erase time, several devices can be erased in parallel. Since each Flash EEPROM can erase
at a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished (see Figure 3).
Examples of how to mask a device during parallel erase include driving the Epin high, writing the read command
(00h) to the device when the others receive a set-up-erase or erase command, or disconnecting it from all
electrical signals with relays or other types of switches.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
Bus
Operation
Start
Command
Comments
Initialize
Address
Address = 00h
Standby
Wait for V
to ramp to
PP
V
CC
= 5 V ± 10%, V
= 12 V ± 5%
PP
V
PPH
(see Note A)
Setup
X = 1
Initialize pulse count
Write Set-Up-Program Command
Write
Set-Up-
Program
Write
Data = 40h
Write Data
Increment
Address
Wait = 10 µs
X = X + 1
Write
Write Data Valid address/data
Write Program-Verify Command
Standby
Wait = 10 µs
Wait = 6 µs
No
Write
Program-
Verify
Data = C0h; ends
Program operation
Read
and Verify
Byte
Fail
X = 25?
Standby
Read
Wait = 6 µs
Yes
Pass
Read byte to verify
Programming; compare
output to expected output
Interactive
Mode
No
Last
Address
?
Yes
Write Read Command
Power
Down
Write
Read
Data = 00h; resets register
for read operations
Apply V
Apply V
PPL
PPL
Standby
Wait for V
to ramp to
PP
(see Note B)
V
PPL
Device Passed
Device Failed
NOTES: A. Refer to the recommended operating conditions for the value of V
B. Refer to the recommended operating conditions for the value of V
PPH.
PPL
.
Figure 1. Programming Flowchart: Fastwrite Algorithm
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
Bus
Operation
Start
Command
Comments
Preprogram
Entire memory must = 00h
before erasure
Program All
Bytes to 00h
No
All Bytes = 00h
?
Use Fastwrite
programming algorithm
Yes
Address = 00h
Initialize addresses
V
CC
= 5 V ± 10%, V
= 12 V ± 5%
PP
Standby
Wait for V
to ramp to
Setup
PP
(see Note A)
X = 1
V
PPH
Write Set-Up-Erase Command
Write-Erase Command
Initialize pulse count
Data = 20h
Write
Set-Up-
Erase
Wait = 10 ms
X = X + 1
Interactive
Mode
Write Erase-Verify Command
Write
Erase
Data = 20h
Standby
Wait = 10 ms
Wait = 6 µs
No
X = 1000?
Yes
Increment
Address
Read
and Verify
Byte
Write
Erase
Verify
Addr = Byte to verify;
Data = A0h; ends the erase
operation
Fail
Pass
Standby
Read
Wait = 6 µs
No
Last
Address?
Read byte to verify erasure;
compare output to FFh
Yes
Write Read Command
Write
Read
Data = 00h; resets register
for read operations
Power
Down
Apply V
Apply V
PPL
PPL
Standby
Wait for V
to ramp to
PP
(see Note B)
Device Passed
Device Failed
V
PPL
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
NOTES: A. Refer to the recommended operating conditions for the value of V
B. Refer to the recommended operating conditions for the value of V
PPH.
PPL
.
Figure 2. Flash-Erase Flowchart: Fasterase Algorithm
Start
Program All Devices to 00h
X = 1
Give Erase Command to All
Devices
D = 1
Yes
Is
Device #D
Erased
?
Mask Device #D
X = X+1
No
Give Erase
Command to
All Unmasked
Devices
No
D = n
?
D = D+1
Yes
No
Are
All Devices
Erased
?
No
X = 1000
?
Yes
Yes
Give Read
Command to
All Devices
Give Read
Command to
All Devices
All Devices Pass
Finished With Errors
NOTE: n = number of devices being erased.
Figure 3. Parallel-Erase Flow Diagram
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V
CC
PP
Input voltage range (see Note 2): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V
+ 1 V
CC
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V + 1 V
CC
Operating free-air temperature range during read/erase/program, T
A
NL, FML, DDL, DUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
NE, FME, DDE, DUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
NQ, FMQ, DDQ, DUQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40° C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to V
.
SS
2. The voltage on any input pin can undershoot to –2.0 V for periods less than 20 ns.
3. The voltage on any output pin can overshoot to 7.0 V for periods less than 20 ns.
recommended operating conditions
MIN
4.5
TYP
MAX
UNIT
V
Supply voltage
Supply voltage
During write/read/flash erase
During read only (V
5
5.5
V
V
V
CC
)
0
V
+ 2
PPL
During write/read/flash erase (V
CC
V
PP
)
11.4
2
12
12.6
+0.5
+0.5
0.8
PPH
TTL
V
CC
V
IH
High-level dc input voltage
V
CMOS
TTL
V
CC
– 0.5
–0.5
V
CC
V
V
Low-level dc input voltage
V
V
IL
CMOS
GND – 0.2
11.5
GND+0.2
13
Voltage level on A9 for algorithm-selection mode
ID
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
= – 2.5 mA
MIN
2.4
MAX
UNIT
I
I
I
I
OH
OH
OL
OL
V
V
High-level output voltage
V
OH
= – 100 µA
V
CC
– 0.4
= 5.8 mA
0.45
0.1
Low-level output voltage
V
OL
= 100 µA
I
I
I
I
A9 algorithm-selection-mode current
Input current (leakage)
A9 = V max
ID
200
±1
µA
µA
ID
All except A9
A9
V = 0 V to 5.5 V
I
V = 0 V to 13 V
I
I
± 200
±10
200
±10
30
Output current (leakage)
V
V
V
V
V
= 0 V to V
CC
µA
µA
O
O
= V
= V
= V
= V
,
Read mode
PP
PP
PP
PP
PPH
PPL
PPH
PPH
V
PP
supply current (read/standby)
PP1
µA
I
I
V
V
V
supply current (during program pulse) (see Note 4)
supply current (during flash erase) (see Note 4)
supply current (during program/erase verify)
mA
mA
PP2
PP
PP
PP
30
PP3
I
V
PP
= V
5.0
mA
PP4
PPH
(see Note 4)
TTL-input level
V
V
V
= 5.5 V,
E = V
E = V
E = V
1
mA
CC
IH
I
V
supply current (standby)
CCS
CC
CMOS-input level
5.5 V,
100
µA
CC =
CC
= 5.5 V
,
IL
CC
I
I
I
V
CC
V
CC
V
CC
V
CC
supply current (active read)
30
10
15
mA
mA
mA
CC1
CC2
CC3
f = 6 MHz,
Outputs open
V
CC
= 5.5 V,
E = V
,
,
,
IL
average supply current (active write) (see Note 4)
average supply current (flash erase) (see Note 4)
average supply current (program/erase verify)
Programming in progress
V
= 5.5 V,
E = V
CC
Erasure in progress
IL
IL
V
CC
V
PP
= 5.5 V,
E = V
I
= V
,
PPH
15
mA
CC4
(see Note 4)
Program/erase-verify in progress
NOTE 4: Not 100% tested; characterization data available.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
†
f = 1 MHz
PARAMETER
TEST CONDITIONS
V = 0 , f = 1 MHz
= 0, f = 1 MHz
MIN
MAX
6
UNIT
pF
C
C
Input capacitance
Output capacitance
i
I
V
O
12
pF
o
†
Capacitance measurements are made on sample basis only.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’28F010A-10
MIN MAX
’28F010A-12 ’28F010A-15 ’28F010A-17
TEST
CONDITIONS
ALTERNATE
SYMBOL
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
Access time from
address, A0–A16
t
t
t
100
100
120
150
170
ns
ns
a(A)
AVQV
Access time from
chip enable, E
t
120
150
170
a(E)
ELQV
Access time from
output enable, G
t
t
t
t
t
45
50
55
60
ns
ns
ns
en(G)
GLQV
Cycle time, read
t
100
0
120
0
150
0
170
0
c(R)
AVAV
Delay time, E low
to low-Z output
d(E)
ELQX
C
= 100 pF,
L
1 Series 74
TTL load,
Input t ≤ 20 ns,
Delay time, G low
to low-Z output
t
t
t
0
0
0
0
ns
ns
d(G)
GLQX
r
f
Chip disable time
to hi-Z output
Input t ≤ 20 ns
t
0
0
55
30
0
0
55
30
0
0
55
35
0
0
55
35
dis(E)
EHQZ
Output disable
time to hi-Z
output
t
t
ns
dis(G)
GHQZ
Hold time, data
valid from
address, E, or G
t
t
t
0
6
0
6
0
6
0
6
ns
h(D)
AXQX
†
Write recovery
time before read
t
µs
rec(W)
WHGL
†
Whichever occurs first.
15
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
timing requirements–write/erase/program operations
’28F010A-10
’28F010A-12
ALTERNATE
SYMBOL
PARAMETER
UNIT
MIN NOM
MAX
MIN NOM
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write using W
Cycle time, programming operation
Cycle time, erase operation
Hold time, address
t
100
10
120
10
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
c(W)
AVAV
t
t
c(W)PR
c(W)ER
h(A)
WHWH1
9.5
55
0
10
9.5
60
0
10
WHWH2
t
WLAX
Hold time, E
t
t
h(E)
WHEH
WHDX
Hold time, data valid after W high
Setup time, address
10
0
10
0
h(WHD)
su(A)
t
AVWL
Setup time, data
t
50
20
100
1.0
6
50
20
100
1.0
6
su(D)
DVWH
Setup time, E before W
t
su(E)
ELWL
t
EHVP
Setup time, E high to V
ramp
su(EHVPP)
su(VPPEL)
rec(W)
rec(R)
w(W)
PP
to E low
Setup time, V
PP
t
VPEL
WHGL
GHWL
WLWH
WHWL
Recovery time, W before read
Recovery time, read before W
Pulse duration, W (see Note 5)
Pulse duration, W high
t
t
0
0
t
60
20
1
60
20
1
t
w(WH)
r(VPP)
f(VPP)
Rise time, V
t
VPPR
PP
Fall time, V
t
1
1
PP
VPPF
’28F010A-15
’28F010A-17
ALTERNATE
SYMBOL
PARAMETER
UNIT
MIN NOM
MAX
MIN NOM
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write using W
Cycle time, programming operation
Cycle time, erase operation
Hold time, address
t
150
10
170
10
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
c(W)
AVAV
t
t
c(W)PR
c(W)ER
h(A)
WHWH1
WHWH2
9.5
60
0
10
9.5
70
0
10
t
WLAX
Hold time, E
t
t
h(E)
WHEH
WHDX
Hold time, data valid after W high
Setup time, address
10
0
10
0
h(WHD)
su(A)
t
AVWL
Setup time, data
t
50
20
100
1.0
6
50
20
100
1.0
6
su(D)
DVWH
Setup time, E before W
t
su(E)
ELWL
t
EHVP
Setup time, E high to V
ramp
su(EHVPP)
su(VPPEL)
rec(W)
rec(R)
w(W)
PP
to E low
Setup time, V
PP
t
VPEL
WHGL
GHWL
WLWH
WHWL
Recovery time, W before read
Recovery time, read before W
Pulse duration, W (see Note 5)
Pulse duration, W high
t
t
0
0
t
60
20
1
60
20
1
t
w(WH)
r(VPP)
f(VPP)
Rise time, V
t
VPPR
PP
Fall time, V
t
1
1
PP
VPPF
NOTE 5: Rise/fall time ≤ 10 ns.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
timing requirements — alternative E-controlled writes
’28F010A-10
’28F010A-12
’28F010A-15
’28F010A-17
ALTERNATE
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write using E
t
100
120
150
170
ns
c(W)
AVAV
Cycle time, programming op-
eration
t
10
10
10
10
µs
c(E)PR
EHEH
t
t
t
t
t
t
t
Hold time, address
Hold time, data
t
75
10
0
80
10
0
80
10
0
90
10
0
ns
ns
ns
ns
ns
ns
µs
h(EA)
ELAX
t
h(ED)
h(W)
EHDX
Hold time, W
t
EHWH
Setup time, address
Setup time, data
Setup time, W before E
t
0
0
0
0
su(A)
AVEL
t
50
0
50
0
50
0
50
0
su(D)
DVEH
t
su(W)
su(VPPEL)
WLEL
Setup time, V
PP
to E low
t
1.0
1.0
1.0
1.0
VPEL
Recovery time, write using E
before read
t
t
t
t
6
0
6
0
6
0
6
0
µs
µs
rec(E)R
rec(E)W
EHGL
Recovery time, read before
write using E
GHEL
t
t
Pulse duration, write using E
Pulse duration, write, E high
t
t
70
20
70
20
70
20
80
20
ns
ns
w(E)
ELEH
w(EH)
EHEL
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
= 800 Ω
L
Output
Under Test
C
= 100 pF
L
Figure 4. AC Test Output Load Circuit
AC testing input/output waveforms
2.4 V
2 V
2 V
0.8 V
0.8 V
0.45 V
AC testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic
capacitor connected between V
and V as close as possible to the device pins.
CC
SS
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
t
c(R)
A0–A16
Address Valid
t
a(A)
E
t
t
dis(E)
a(E)
G
W
t
rec(W)
t
en(G)
t
t
d(G)
dis(G)
t
d(E)
t
h(D)
DQ0–DQ7
HI-Z
Ouput Valid
HI-Z
Figure 5. Read Cycle Timing
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Address
and Data
Set-Up-
Program
Command
Program
Verify
Command
Power Up
and
Standby
Program
Verification
Standby/
Power Down
Programming
A0–A16
t
t
c(W)
c(W)
t
c(R)
t
c(W)
t
t
su(A)
h(A)
t
h(A)
t
su(A)
E
t
t
dis(E)
su(E)
t
su(E)
t
su(E)
t
h(E)
t
t
h(E)
h(E)
G
t
c(W)PR
t
t
w(WH)
rec(R)
t
t
dis(G)
rec(W)
W
t
h(D)
t
h(WHD)
t
h(WHD)
t
t
en(G)
h(WHD)
t
t
w(W)
w(W)
t
d(G)
t
w(W)
t
su(D)
t
t
su(D)
su(D)
HI-Z
DQ0–DQ7
Data In
Valid Data Out
t
d(E)
Data In = 40h
Data In = C0h
t
a(E)
5 V
V
CC
0 V
t
su(VPPEL)
V
PPH
V
PP
V
PPL
t
f(VPP)
t
r(VPP)
t
su(EHVPP)
Figure 6. Write Cycle Timing
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Address
and Data
Set-Up-
Program
Command
Program
Verify
Command
Power Up
and
Standby
Program
Verification
Standby/
Power Down
Programming
A0–A16
t
t
c(W)
c(W)
t
c(R)
t
c(W)
t
t
su(A)
h(EA)
t
h(EA)
t
su(A)
W
t
t
su(W)
t
t
su(W)
dis(G)
su(W)
t
t
t
h(W)
h(W)
h(W)
G
E
t
c(w)B
t
rec(E)W
t
t
dis(E)
rec(E)R
t
w(EH)
t
h(D)
t
h(ED)
t
h(ED)
t
t
en(G)
h(ED)
t
w(E)
t
w(E)
t
d(G)
t
w(E)
t
t
t
su(D)
su(D)
HI-Z
su(D)
DQ0–DQ7
Data In
Valid Data Out
t
d(E)
Data In = 40h
Data In = C0h
t
a(E)
5 V
V
V
CC
0 V
t
su(VPPEL)
V
PP
PPH
V
PPL
t
r(VPP)
t
f(VPP)
t
su(EHVPP)
Figure 7. Write Cycle (Alternative E-Controlled Writes) Timing
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F010A
1048576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS012 – DECEMBER 1992 – REVISED NOVEMBER 1993
PARAMETER MEASUREMENT INFORMATION
Set-Up-
Erase
Command
Erase-
Verify
Command
Power Up
and
Standby
Erase
Command
Erase
Verification
Standby/
Power Down
Erasing
A0–A16
t
t
c(W)
c(R)
t
c(W)
t
t
c(W)
h(A)
t
su(A)
E
t
su(E)
t
t
su(E)
su(E)
t
t
t
h(E)
dis(E)
h(E)
t
h(E)
G
t
w(WH)
t
t
rec(W)
t
rec(R)
t
c(E)B
t
dis(G)
W
t
h(D)
t
h(WHD)
t
en(G)
t
h(WHD)
h(WHD)
w(W)
t
w(W)
t
d(G)
t
t
w(W)
t
su(D)
t
su(D)
t
su(D)
HI-Z
DQ0–DQ7
Data In = 20h
Valid Data Out
t
d(E)
Data In = 20h
Data In = A0h
t
a(E)
5 V
V
CC
0 V
t
su(VPPEL)
V
PP
PPH
V
V
PPL
t
f(VPP)
t
r(VPP)
t
su(EHVPP)
Figure 8. Flash-Erase Cycle Timing
21
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