TMS28F200BZT90BDBJL [TI]
262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES; 262144 ×8位/ 131072 ×16位引导块闪存
| 型号： | TMS28F200BZT90BDBJL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES |
| 文件： | 总29页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
DBJ PACKAGE
(TOP VIEW)
Organization . . . 262144 by 8 bits
131072 by 16 bits
Array-Blocking Architecture
– Two 8K-Byte Parameter Blocks
– One 96K-Byte Main Block
– One 128K-Byte Main Block
– One 16K-Byte Protected Boot Block
– Top or Bottom Boot Locations
V
1
2
3
4
5
6
7
8
9
44 RP
PP
NC
NC
A7
A6
A5
A4
A3
A2
43
W
42
A8
41 A9
40 A10
39 A11
38 A12
All Inputs/Outputs TTL Compatible
37
A13
36 A14
Maximum Access/Minimum Cycle Time
35
34
33
32
A1 10
A0 11
A15
A16
BYTE
V
± 10%
CC
’28F200BZx70
’28F200BZx80
’28F200BZx90
70 ns
80 ns
90 ns
E
12
13
14
V
V
SS
G
SS
31 DQ15/A
30 DQ7
29 DQ14
28 DQ6
–1
(x = top (T) or bottom (B) boot-block
configurations ordered)
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
10000 Program/Erase-Cycles
27
DQ13
Three Temperature Ranges
26 DQ5
25 DQ12
24 DQ4
– Commercial . . . 0°C to 70°C
– Extended . . . – 40°C to 85°C
– Automotive . . . – 40°C to 125°C
23
V
CC
Low Power Dissipation (V
= 5.5 V)
CC
– Active Write . . . 330 mW (Byte-Write)
– Active Read . . . 330 mW (Byte-Read)
– Active Write . . . 358 mW (Word-Write)
– Active Read . . . 330 mW (Word-Read)
– Block-Erase . . . 165 mW
– Standby . . . 0.55 mW (CMOS-Input
Levels)
– Deep Power-Down Mode . . . 0.0066 mW
PIN NOMENCLATURE
A0–A16
BYTE
Address Inputs
Byte Enable
DQ0–DQ14 Data In/Out
DQ15/A
Data In/Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
–1
E
G
Output Enable
NC
RP
No Internal Connection
Reset/Deep Power-Down
5-V Power Supply
12-V Power Supply for Program/Erase
Ground
Fully Automated On-Chip Erase and
Word/Byte-Program Operations
V
CC
V
PP
V
SS
Write-Protection for Boot Block
Industry-Standard Command State Machine
(CSM)
W
Write Enable
– Erase-Suspend/Resume
– Algorithm-Selection Identifier
description
The TMS28F200BZx is a 262144 by 8-bit/131072 by 16-bit (2097152-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F200BZx is organized in a blocked architecture
consisting of one 16K-byte protected boot block, two 8K-byte parameter blocks, one 96K-byte main block, and
one 128K-byte main block. The device can be ordered with either a top or bottom boot-block configuration.
Operation as a 256K-by 8-bit or a 128K-by16-bit organization is user-definable.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
description (continued)
Embedded program and block-erase functions are fully automated by an on-chip write state machine (WSM),
simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM status
can be monitored by the on-chip status register to determine the progress of program/erase tasks. The device
features user-selectable block-erasure.
The TMS28F200BZx flash memory is offered in a 44-pin PSOP. It is available in two temperature ranges:
0°C to 70°C and – 40°C to 85°C.
device symbol nomenclature
TMS28F200BZT
70
B
DBJ
L
Temperature Range Designator
L
E
=
=
0°C to 70°C
– 40°C to 85°C
Package Designator
DBJ = Plastic Small-Outline Package
Program/Erase Endurance
= 10000 Cycles
B
Speed Designator
70 = 70 ns (±10%
80 = 80 ns (±10%
90 = 90 ns (±10%
V
CC
V
CC
V
CC
tolerance)
tolerance)
tolerance)
Boot-Block Location Indicator
T = Top Location
B = Bottom Location
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
functional block diagram
DQ8–DQ15/A
8
DQ0–DQ7
8
–1
8
DQ15/A
Input Buffer
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
–1
Data
Register
BYTE
I/O Logic
Identification
Register
E
Command
State
Machine
W
G
Output
Multiplexer
Status
Register
RP
17
A0–
A16
Input
Buffer
Power-
Reduction
Control
Data
Comparator
Program/
Write
State
Machine
Erase
Voltage
Switch
V
PP
Address
Latch
Y Decoder
X Decoder
Y Gating/Sensing
16K-Byte
Boot
Block
8K-Byte
Parameter Parameter
Block Block
8K-Byte
96K-Byte 128K-Byte
Address
Counter
Main
Block
Main
Block
architecture
The TMS28F200BZx uses a blocked architecture to allow independent erasure of selected memory blocks.The
block to be erased is selected by using any valid address within that block.
block memory maps
The TMS28F200BZx is available with the block architecture mapped in either of two configurations: the boot
block located at the top or at the bottom of the memory array, as required by different microprocessors. The
TMS28F200BZB (bottom boot block) is mapped with the 16K-byte boot block located at the low-order address
range (00000h to 01FFFh). The TMS28F200BZT (top boot block) is inverted with respect to the
TMS28F200BZBwiththebootblocklocatedatthehigh-orderaddressrange(1E000hto1FFFFh). Bothofthese
address ranges are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these
configurations.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
block memory maps (continued)
Address
Range
Address
Range
×8 Configuration
×16 Configuration
3FFFFh
1FFFFh
Boot Block
Boot Block
16K Addresses
8K Addresses
3C000h
3BFFFh
1E000h
1DFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
3A000h
39FFFh
1D000h
1CFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
38000h
37FFFh
1C000h
1BFFFh
Main Block
Main Block
96K Addresses
48K Addresses
20000h
1FFFFh
10000h
0FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
00000h
00000h
DQ15/A Is LSB Address
–1
A0 Is LSB Address
Figure 1. TMS28F200BZT (Top Boot Block) Memory Map
Address
Range
Address
Range
×8 Configuration
×16 Configuration
3FFFFh
1FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
20000h
1FFFFh
10000h
0FFFFh
Main Block
Main Block
96K Addresses
48K Addresses
08000h
07FFFh
04000h
03FFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
06000h
05FFFh
03000h
02FFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
04000h
03FFFh
02000h
01FFFh
Boot Block
Boot Block
16K Addresses
8K Addresses
00000h
00000h
DQ15/A Is LSB Address
–1
A0 Is LSB Address
Figure 2. TMS28F200BZB (Bottom Boot Block) Memory Map
boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. To
protect data within this memory sector, the RP pin can be used to provide a lockout to eliminate either accidental
erase or program operations. When RP is operated with normal TTL/CMOS logic levels, the contents of the
boot block cannot be erased or reprogrammed. Changes to the contents of the boot block can be made only
when RP is at V
(nominally 12 V) during normal write/erase operations.
HH
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution should be exercised because the parameter block does not
have the boot-block data-protection safety feature.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
main block
Primary memory on the TMS28F200BZx is located in two main blocks. One of the blocks has a storage capacity
for 128K bytes and the other block has a storage capacity for 96K bytes.
command state machine
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. The available commands are listed in Table 1 and
the description of these commands are shown in Table 2. When a program or erase command is issued to the
CSM, the WSM controls the internal sequences and the CSM only responds to status reads. After the WSM
completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the CSM to respond to the
full command set again.
operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0–DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires a command code to be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0–DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
Table 1. Command State Machine Codes for Device Mode Selection
COMMAND
CODE ON
DQ0–DQ7
DEVICE MODE
Invalid/Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
†
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
†
DQ0 is the least significant bit. DQ8–DQ15 can be any valid 2-state
level.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
command definition
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 2 for the CSM command definitions and
data for each of the bus cycles.
Following the read-algorithm-selection-code command, two read cycles are required to access the
manufacturer-equivalent code and the device-equivalent code. The codes are shown in Table 4 and Table 5.
Table 2. Command Definitions
FIRST BUS CYCLE
OPERATION ADDRESS
Read Operations
SECOND BUS CYCLE
BUS
CYCLES
REQUIRED
COMMAND
CSM
INPUT
DATA
OPERATION ADDRESS
IN/OUT
Read Array
1
3
2
1
Write
Write
Write
Write
X
X
X
X
FFh
90h
70h
50h
Read
Read
Read
X
A0
X
Data Out
M/D
Read Algorithm-Selection Code
Read Status Register
SRB
Clear Status Register
Program Mode
Program Setup/Program
(byte/word)
2
Write
PA
40h or 10h
Write
PA
PD
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
2
Write
Write
BEA
X
20h
B0h
Write
Write
BEA
X
D0h
D0h
Erase-Suspend/
Erase-Resume
Legend:
BEA
M/D
PA
Block-erase address. Any address selected within a block selects that block for erasure.
Manufacturer-equivalent/device-equivalent code (see Table 4 and Table 5 for these codes).
Address to be programmed
PD
Data to be programmed at PA
SRB
X
Status-register data byte that can be found on DQ0–DQ7
Don’t care
status register
The status register allows the user to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0–DQ7. This is valid for operation in either the byte- or word-wide mode.
When writing to the CSM in word-wide mode, the high order I/Os (DQ8–DQ15) can be set to any valid 2-state
level. When reading the status bits during word-wide read operation, the high order I/Os (DQ8–DQ15) are set
to 00h internally so the user only needs to interpret the low order I/Os (D0–DQ7).
After a read-status command has been given, the data appearing on DQ0–DQ7 remains as status-register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register
input change during a status-register read. To assure that the status-register output contains updated status
data, E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 3 defines the
status-register bits and their functions.
6
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
status register (continued)
Table 3. Status-Register Bit Definitions and Functions
STATUS
BIT
FUNCTION
DATA
COMMENTS
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling
operations can be performed. Until this occurs, the other status
bits are not valid. If the WSM status bit shows busy (0), the user
must periodically toggle E or G to determine when the WSM has
completed an operation (SB7=1) since SB7 is not automatically
updated at the completion of a WSM task.
1 = Ready
0 = Busy
SB7
SB6
Write-state-machine status
When an erase-suspend command is issued, the WSM halts
execution and sets the ESS bit high (SB6 = 1) indicating that the
erase operation has been suspended. The WSM bit is also set
high (SB7 = 1) indicating that the erase-suspend operation has
beensuccessfullycompleted.TheESSbitremainsatalogic-high
level until an erase-resume command is input to the CSM (code
D0h).
1 = Erase suspended
0 = Erase in progress or
completed
Erase-suspend status
(ESS)
SB5 = 0 indicates that a successful block-erasure has occurred.
SB5 = 1 indicates that an erase-error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
completely erase the device.
Erase status
(ES)
1 = Block-erase error
0 = Block-erase good
SB5
SB4
SB3
SB4 = 0 indicates successful programming has occurred at the
addressed block location. SB4 = 1 indicates that the WSM was
unable to correctly program the addressed block location.
Program status
(PS)
1 = Byte/word-program error
0 = Byte/word-program good
SB3 provides information on the status of
V
during
PP
1 = Program abort:
programming.If V is lower than V after a program or erase
PP
command has been issued, SB3 is set to a 1 to indicate that the
programming operation is aborted. If V is between V and
PPL
V
status
PP
(V
V
0 = V
range error
good
PP
PP
)
PPS
PP
PPH
V , SB3 will not be set.
PPL
SB2–
SB0
These bits should be masked out when reading the status
register.
Reserved
byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8–DQ15, and
a lower-half that outputs data through DQ0–DQ7. Device operation in either byte-wide or word-wide mode is
user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device
is in the word-wide mode and data is written to or read from I/O pins DQ0–DQ15. When BYTE is at a logic-low
level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0–DQ7. In the byte-wide
mode, I/O pins DQ8–DQ14 are placed in the high-impedance state and DQ15/A becomes the low-order
–1
address pin and selects either the upper- or lower-half of the array. Array data from the upper-half (DQ8–DQ15)
and the lower-half (DQ0–DQ7) are multiplexed in order to appear on DQ0–DQ7. Table 4 and Table 5
summarize operations for word-wide mode and byte-wide mode, respectively.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
byte-wide or word-wide mode selection (continued)
Table 4. Operation Modes for Word-Wide Mode (BYTE = V )
IH
MODE
E
G
RP
W
A9
A0
V
PP
DQ0–DQ15
Read
V
V
V
V
V
X
X
X
Data out
IL
IL
IH
IH
V
V
V
V
IL
V
V
V
V
ID
V
IL
X
X
Manufacturer-equivalent code 0089h
IL
IH
IH
Device-equivalent code 2274h
(top boot block)
Algorithm-selection mode
V
IL
V
IH
V
ID
V
IH
IL
IH
IH
Device-equivalent code 2275h
(bottom boot block)
Output disable
Standby
V
IH
V
V
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
IL
IH
V
IH
X
X
X
IH
Reset/deep power down
X
X
V
IL
V
V
or
V
or
IH
PPL
Write (see Note 1)
V
IL
V
IH
V
IL
X
X
Data in
V
PPH
HH
X = Don’t care
NOTE 1: When writing commands to the ’28F200BZx, V
must be V for block-erase or program commands to be executed and RP must
PPH
PP
be held at V
for the entire boot-block program or erase operation.
HH
Table 5. Operation Modes for Byte-Wide Mode (BYTE = V )
IL
MODE
E
G
RP
W
A9
X
A0
X
V
DQ15/A
DQ8–DQ14
Hi-Z
DQ0–DQ7
Data out
PP
–1
Read lower byte
Read upper byte
V
V
IL
V
V
IH
X
V
IL
IL
IL
IH
IH
V
V
IL
V
V
IH
X
X
X
V
IH
Hi-Z
Data out
Manufacturer-equivalent
code 89h
V
V
V
V
V
V
X
X
X
Hi-Z
Hi-Z
IL
IL
IH
IH
ID
IL
Algorithm-selection
mode
Device-equivalent code
74h (top boot block)
V
V
V
IL
V
IH
V
V
V
ID
V
IH
X
IL
IH
Device-equivalent code
75h (bottom boot block)
Output disable
Standby
V
IH
V
V
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IH
X
X
IH
Reset/deep power
down
X
X
V
IL
X
X
X
X
X
Hi-Z
Hi-Z
V
PPL
or
V
V
or
IH
Write (see Note 1)
X = Don’t care
V
IL
V
IH
V
IL
X
X
X
Hi-Z
Data in
HH
V
PPH
NOTE 1: When writing commands to the ’28F200BZx, V
must be V
for block-erase or program commands to be executed and RP must
for the entire boot-block program or erase operation.
PP
PPH
be held at V
HH
command state machine operations
The CSM decodes instructions for clear-status-register, read, read-algorithm-selection-code,
read-status-register, program, erase, erase-suspend, and erase-resume operations. The 8-bit command code
is input to the device on DQ0–DQ7 (see Table 1 for CSM codes). During a program or erase cycle, the CSM
informs the WSM that a program or erase cycle has been requested. During a program cycle, the WSM controls
the program sequences and the CSM responds only to status-reads.
8
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
command state machine operations (continued)
During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when V is within its correct voltage range
PP
(V
). For data protection, it is recommended that RP be held at a logic-low level during a CPU-reset.
PPH
clear status register
The internal circuitry can set only the V status bit (SB3), the program status bit (SB4), and the erase status
PP
bit (SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor
to clear these status bits and synchronize them to internal operations. When the status bits are cleared, the
device returns to the read-array mode.
read operations
There are three read operations available: read-array, read-algorithm-selection-code, and read-status-register.
Read array
The array is read by entering the command code FFh on DQ0–DQ7. Control pins E and G must be at a
logic-low level (V ) and W and RP must be at a logic-high level (V ) to read data from the array. Data is
IL
IH
available on DQ0–DQ15 (word-wide mode) or DQ0–DQ7 (byte-wide mode). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
Read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0–DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins E and G must be at a logic-low level (V ) and W and RP must be at a logic-high level
IL
(V ). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
IH
DQ0–DQ7 with A0 at a logic-low level (V ). The device-equivalent code is obtained when A0 is set to a
IL
logic-high level (V ). Alternatively, themanufacturer-anddevice-equivalentcodescanbereadbyapplying
IH
V
(nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
ID
in the “don’t care” category (see Table 2, Table 4, and Table 5).
Read status register
The status register is read by entering the command code 70h on DQ0–DQ7. Control pins E and G must be
at a logic-low level (V ) and W and RP must be at a logic-high level (V ). Two bus cycles are required for
IL
IH
this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status-register contents are updated on the falling edge of E or G, whichever occurs last within the
cycle.
boot-block programming/erasing
Should changes to the boot block be required, RP must be set to V
(12 V) and V
must be set to the
PP
HH
programmingvoltagelevel(V
RP at V , an error signal is generated on SB4 (program-status bit) or SB5 (erase-status bit).
).Ifanattemptismadetowrite,erase,orerase-suspendthebootblockwithout
PPH
HH
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to
status-reads. When the WSM status bit (SB7) is set to a logic-high level, signifying termination of the
nonprogram operation, all commands to the CSM become valid again.
9
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262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
normal programming
There are two CSM commands for programming: program-setup and alternate-program-setup (see Table 1).
After the desired command code is entered, the WSM takes over and correctly sequences the device to
complete the program operation. During this time, the CSM responds only to status-reads until the program
operation has been completed, after which all commands to the CSM become valid again. Once a program
command has been issued, the WSM cannot normally be interrupted until the program algorithm is completed
(see Figure 3 and Figure 4). Taking RP to V during programming aborts the program operation. During
IL
programming, V must remain at V
. Only 0s are written and compared during a program operation. If 1s
PP
PPH
are programmed, the memory-cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status-reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying that the nonprogram operation is
terminated, all commands to the CSM become valid again.
erase operations
There are two erase operations that can be performed by the TMS28F200BZx devices: block-erase and
erase-suspend/erase-resume. An erase operation must be used to initialize all bits in an array block to 1s. After
block-erase confirm is issued, the CSM responds only to status-reads or to erase-suspend commands until the
WSM completes its task.
Block-erasure
Block-erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single-address locations within the array cannot be individually
erased. The block to be erased is selected by using any valid address within that block. RP must be at V
HH
for changing the data content of the boot block. Block-erasure is initiated by a command sequence to the
CSM: block-erase-setup (20h), followed by block-erase-confirm (D0h) (see Figure 5). A two-command
erase sequence protects against accidental erasure of memory contents.
Erase-setup and erase-confirm commands are latched on the rising edge of E or W, whichever occurs first.
Block addresses are latched during the block-erase-confirm command on the rising edge of E or W (see
Figure 10 and Figure 11). When the block-erase-confirm command is complete, the WSM automatically
executes a sequence of events to complete the block-erasure. During this sequence, the block is
programmed with logic 0s, data is verified, all bits in the block are erased, and, finally, verification is
performed to assure that all bits are correctly erased. Monitoring of the erase operation is possible through
the status register (see the subsection, “read status register”).
Erase-suspend/erase-resume
During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data should be read from a block other than the one being erased. To
resume the erase operation, an erase-resume command (D0h) must be issued to cause the CSM to clear
the suspend state previously set (see Figure 5 and Figure 6).
automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read. During this time, the
device switches to the automatic power-saving (APS) mode. When the device switches to this mode, I is
CC
typically reduced from 40 mA to 1 mA (I
= 0 mA). The low level of power is maintained until another read
OUT
operation is initiated. In this mode, the I/O pins retain the data from the last memory-address read until a new
address is read. This mode is entered automatically if no address or control pins toggle within a 200-ns time-out
period. At least one transition on E must occur after power up to activate this mode.
10
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262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
reset/deep power-down mode
Very low levels of power consumption are attained by using a special pin, RP, to disable internal device circuitry.
When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, an I value on the order of 0.2 µA (or 1 µW of power)
CC
is achievable. This is important in portable applications where extended battery life is of major concern.
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a minimum
of t
is required before data is valid, and a minimum of t
and/or t
in deep
d(RP)
rec(RPHE)
rec(RPHW)
power-down mode is required before data-input to the CSM can be recognized. With RP at ground, the WSM
is reset and the status register is cleared, effectively eliminating accidental programming to the array during
system-reset. After restoration of power, the device does not recognize any operation command until RP is
returned to a V - or V -level.
IH
HH
Should RP go low during a program or erase operation, the device will power down and, therefore, will become
nonfunctional. Data being written or erased during the power down is invalid or indeterminate, requiring that the
operation be performed again after power restoration.
11
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
Start
BUS
COMMAND
COMMENTS
OPERATION
Issue Program-Setup Command and
Byte Address
Write
Write
program-
setup
Data
Addr
=
=
40h or 10h
Address of
byte to be
programmed
Issue Byte
Address/Data
Write
Write data
Data
Addr
=
=
Byte to be
programmed
Address of
byte to be
Read
Status-Register Bits
programmed
Read
Status-register data.
Toggle G or E to update
status register.
No
SB7 = 1
?
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Repeat for subsequent bytes.
Write FFh after the last byte-programming operation to
reset the device to read-array mode.
Full Status-Register
Check (optional)
See Note A
Byte-Program Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
OPERATION
COMMAND
COMMENTS
Check SB3
No
SB3 = 0
?
V
PP
Range Error
Standby
1 = Detect V
low
PP
(see Note B)
Yes
Check SB4
No
Byte-Program
Failed
Standby
1
= Byte-program error
(see Note C)
SB4 = 0
?
Yes
Byte-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flow Chart
12
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262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Write
Write
program-
setup
Data
Addr
=
=
40h or 10h
Address of
word to be
programmed
Issue Program-Setup Command
and Word Address
Write
Write data
Data
Addr
=
=
Word to be
programmed
Address of
word to be
Issue Word
Address/Data
programmed
Read
Status-register data.
Toggle G or E to update
status register.
Read Status-Register
Bits
Standby
Check SB7
1 = Ready, 0 = Busy
No
SB7 = 1
?
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Yes
Full Status-Register
Check (optional)
See Note A
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
COMMAND
COMMENTS
OPERATION
No
SB3 = 0
Standby
Check SB3
Detect V
V
PP
Range Error
?
1
=
low
PP
(see Note B)
Yes
Standby
Check SB4
1
=
Word-program
failed
(see Note C)
No
SB4 = 0
?
Word-Program
Failed
Yes
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flow Chart
13
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Data = 20h
Write
Write
Issue Erase-Setup Command
and Block Address
erase-setup Block Addr = Address
within
block to
be
Issue Block-Erase-Confirm
erased
Command and Block Address
Write
Erase
Data = D0h
Block Addr = Address
within
block to
be
Read Status-Register
Bits
Erase-
Suspend
Loop
erased
No
Read
Status-register data.
Toggle G or E to update
status register
No
Erase
Suspend
?
Yes
SB7 = 1
?
Yes
Standby
Check SB7
Full Status-Register
Check (optional)
1 = Ready, 0 = Busy
See Note A
Repeat for subsequent blocks.
WriteFFhafterthelastblock-eraseoperationtoresetthe
device to read-array mode.
Block-Erase Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
COMMAND
COMMENTS
OPERATION
No
Yes
No
SB3 = 0
?
Standby
Check SB3
1 = Detect V
V
Range Error
PP
low
PP
(see Note B)
Yes
SB4 = 1,
SB5 = 1
?
Command Sequence
Error
Standby
Standby
Check SB4 and SB5
1 = Block-erase
command error
No
SB5 = 0
?
Block-Erase Failed
Check SB5
1 = Block-erase failed
(see Note C)
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flow Chart
14
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Data = B0h
Write
Erase-
suspend
Issue Erase-Suspend
Command
Read
Status-register data.
Toggle G or E to update
status register.
Read Status-Register
Bits
Standby
Standby
Check SB7
1 = Ready
No
No
SB7 = 1
?
Yes
Check SB6
1 = Suspended
SB6 = 1
?
Erase Completed
Yes
Write
Read
Write
Read
memory
Data = FFh
Issue Memory-Read
Command
Read data from block
other than that being
erased.
No
Finished
Reading
?
Yes
Issue Erase-Resume
Command
Erase-
resume
Data = D0h
Erase Continued
See Note A
NOTE A: Refer to block-erase flow chart for complete erasure procedure.
Figure 6. Erase-Suspend/Resume Flow Chart
15
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262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
CC
PP
Supply voltage range, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to V
+ 1 V
CC
RP, A9 (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to V + 1 V
CC
Operating free-air temperature range, T , during read/erase/program: L suffix . . . . . . . . . . . . . . 0°C to 70°C
A
E suffix . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. All voltage values are with respect to V
.
SS
3. The voltage on any input can undershoot to – 2 V for periods less than 20 ns.
4. The voltage on any output can overshoot to 7 V for periods less than 20 ns.
recommended operating conditions
MIN
4.5
0
NOM
MAX
5.5
UNIT
V
V
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
5
CC
During read only (V
)
6.5
V
PPL
During write/erase/erase suspend (V
PP
)
11.4
2
12
12.6
V
PPH
TTL
V
V
+ 0.5
V
CC
V
V
High-level dc input voltage
Low-level dc input voltage
IH
CMOS
TTL
V
V
– 0.5
+ 0.5
0.8
V
CC
CC
– 0.5
– 0.2
V
IL
CMOS
V
+ 0.2
V
SS
SS
V
V
V
lock-out voltage from write/erase
2
V
LKO
CC
RP unlock voltage
11.5
12
13
V
HH
word/byte-write and block-erase performance (see Notes 5 and 6)
’28F200BZx70
’28F200BZx80
’28F200BZx90
PARAMETER
UNIT
MIN
TYP
2.2
3.2
1.6
.32
MAX
Main-block erase time
14
4.2
2.1
7
s
s
s
s
Main-block byte-program time
Main-block word-program time
Parameter/boot-block erase time
NOTES: 5. Excludes system-level overhead
6. Typical values shown are at T = 25°C, V
= 12 V
PP
A
16
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, using test conditions given in Table 6 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL
I
I
= – 2.5 mA,
= – 100 µA,
= 4.5 V,
V
V
= 4.5 V
= 4.5 V
2.4
OH
CC
V
High-level output voltage
V
OH
CMOS
V
– 0.4
OH
CC
CC
V
V
Low-level output voltage
A9 selection-code voltage
V
I = 5.8 mA
OL
0.45
13
V
V
OL
CC
11.5
ID
Input current (leakage), except for A9 when A9 = V
(see Note 7)
ID
I
I
V
CC
= 5.5 V,
V = 0 V to 5.5 V
I
±1
µA
I
I
I
I
I
I
A9 selection-code current
RP boot-block-unlock current
Output current (leakage)
A9 = V
500
500
±10
10
µA
µA
µA
µA
µA
µA
ID
ID
RP
O
V
V
= 5.5 V,
V
= 0 V to V
CC
CC
O
V
V
V
V
standby current (standby)
≤ V
PPS
PPL
PP1
PP
PP
PP
PP
PP
CC
± 0.2 V, V
supply current (reset/deep power-down mode)
supply current (active read)
RP = V
≤ V
CC
5
SS
> V
PP
V
200
PP
PP
CC
supply current (active byte-write)
V
= V
,
PPH
I
I
I
I
30
40
mA
mA
mA
µA
PP2
PP3
PP4
PP5
(see Notes 8 and 9)
Programming in progress
V
supply current (active word-write)
V
= V
,
PPH
PP
(see Notes 8 and 9)
PP
Programming in progress
V
= V
,
PPH
PP
Block-erase in progress
V
V
supply current (block-erase) (see Notes 8 and 9)
supply current (erase-suspend)
30
PP
V
= V
,
PPH
PP
PP
Block-erase suspended
200
(see Notes 8 and 9)
TTL-input level
V
V
= 5.5 V,
= 5.5 V,
E = RP = V
E = RP = V
1.5
100
1.2
1.2
mA
µA
µA
µA
CC
IH
IH
I
V
supply current (standby)
CCS
CCL
CC
CC
CMOS-input level
CC
0°C to 70°C
– 40°C to 85°C
E = V
I
V
supply current (reset/deep power-down mode)
RP = V
± 0.2 V
SS
V
= 5.5 V,
,
CC
f = 10 MHz,
IL
= 0 mA
TTL-input level
supply current (active read)
60
55
60
65
30
10
mA
mA
mA
mA
mA
mA
I
OUT
I
V
V
CC1
CC
V
= 5.5 V,
E = V
± 0.2 V,
SS
= 0 mA
CC
f = 10 MHz,
CMOS-input level
I
OUT
supply current (active byte-write)
V
= 5.5 V,
CC
CC
Programming in progress
I
I
I
I
CC2
CC3
CC4
CC5
(see Notes 8 and 9)
V
supply current (active word-write)
V
= 5.5 V,
CC
(see Notes 8 and 9)
CC
Programming in progress
V
= 5.5 V,
CC
Block-erase in progress
V
V
supply current (block-erase) (see Notes 8 and 9)
supply current (erase-suspend)
CC
V
= 5.5 V, E = V ,
IH
CC
CC
Block-erase suspended
(see Notes 8 and 9)
NOTES: 7. DQ15/A is tested for output leakage only.
–1
8. Characterization data available
9. All ac current values are RMS unless otherwise noted.
Table 6. AC Test Conditions
†
I
I
V
V
(V)
V
(V)
V
(V)
V
(V)
C
t
t
r
(ns)
OL
OH
Z
OL
OH
IL
IH
LOAD
(pF)
f
(mA)
(mA)
(V)
(ns)
2.1
– 0.4
1.5
0.8
2.0
0.45
2.4
100
<10
<10
†
V
Z
is the measured value used to detect high impedance.
17
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz, V = 0 V
I
PARAMETER
TEST CONDITIONS
MIN
MAX
8
UNIT
pF
C
C
Input capacitance
Output capacitance
i
V
O
= 0 V
12
pF
o
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
read operations
’28F200BZx70
’28F200BZx80
’28F200BZx90
ALT.
SYMBOL
PARAMETER
UNIT
MIN
MAX
70
MIN
MAX
80
MIN
MAX
90
t
t
t
t
t
t
t
t
Access time from A0–A16 (see Note 10)
Access time from E
t
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
70
80
90
a(E)
ELQV
Access time from G
t
t
35
40
45
a(G)
c(R)
GLQV
Cycle time, read
t
70
0
80
0
90
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, E low to low-impedance output
Delay time, G low to low-impedance output
Disable time, E to high-impedance output
Disable time, G to high-impedance output
d(E)
t
t
0
0
0
d(G)
dis(E)
dis(G)
25
25
30
30
35
35
t
Hold time, DQ valid from A0–A16, E, or G,
whichever occurs first (see Note 10)
t
t
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
300
25
5
300
30
5
300
35
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8–DQ15 in
high-impedance state
t
FLQV
Access time from BYTE switching high
t
70
80
90
FHQV
NOTE 10: A –A16 for byte-wide
–1
18
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BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
write/erase operations — W-controlled writes
’28F200BZx70
’28F200BZx80
’28F200BZx90
ALT.
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
Cycle time, write
t
70
80
90
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
0.3
0.3
0.6
6
0.3
0.3
0.6
7
0.4
0.4
0.7
c(W)OP
c(W)ERB
c(W)ERP
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter
block)
s
t
t
t
t
t
t
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A16 (see Note 10)
Hold time, DQ valid
s
c(W)ERM
d(RPR)
h(A)
t
100
100
100
ns
ns
ns
ns
ns
PHBR
t
10
0
10
0
10
0
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
10
0
10
0
10
0
h(E)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
Hold time, RP at V
status-register bit
from valid
HH
t
t
0
0
0
ns
h(RP)
QVPH
t
t
t
t
t
t
t
t
Setup time, A0–A16 (see Note 10)
Setup time, DQ
t
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
su(A)
AVWH
t
su(D)
DVWH
Setup time, E before write operation
t
0
0
0
su(E)
ELWL
Setup time, RP at V
to W going high
t
PHHWH
100
100
60
100
100
60
100
100
60
su(RP)
su(VPP)1
w(W)
HH
to W going high
Setup time, V
t
PP
VPWH
t
WLWH
Pulse duration, W low
Pulse duration, W high
t
10
20
30
w(WH)
rec(RPHW)
WLWL
Recovery time, RP high to W going low
t
215
215
215
PHWL
NOTE 10: A –A16 for byte-wide
–1
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
write/erase operations — E-controlled writes
’28F200BZx70
’28F200BZx80
’28F200BZx90
ALT.
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write using E
t
70
80
90
ns
c(W)
AVAV
Cycle time, duration of programming
operation using E
t
t
t
t
6
0.3
0.3
0.6
6
0.3
0.3
0.6
7
0.4
0.4
0.7
µs
c(E)OP
EHQV1
EHQV2
EHQV3
EHQV4
Cycle time, erase operation using E
(boot block)
t
t
t
s
s
s
c(E)ERB
c(E)ERP
c(E)ERM
Cycle time, erase operation using E
(parameter block)
Cycle time, erase operation using E
(main block)
t
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A16 (see Note 10)
Hold time, DQ valid
t
100
100
100
ns
ns
ns
ns
ns
d(RPR)
PHBR
t
10
0
10
0
10
0
h(A)
EHAX
EHDX
t
h(D)
Hold time, W
t
10
0
10
0
10
0
h(W)
h(VPP)
EHWH
Hold time, V
PP
from valid status-register bit
fromvalidstatus-register
t
QVVL
Holdtime, RPatV
bit
HH
t
t
0
0
0
ns
h(RP)
QVPH
t
t
t
t
t
t
t
t
Setup time, A0–A16 (see Note 10)
Setup time, DQ valid
t
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
su(A)
AVEH
t
su(D)
DVEH
Setup time, W before E
t
0
0
0
su(W)
su(RP)
su(VPP)2
w(E)
WLEL
Setup time, RP at V
to E going high
t
100
100
50
100
100
50
100
100
50
HH
to E going high
PHHEH
Setup time, V
t
VPEH
PP
Pulse duration, E low, write using E
Pulse duration, E high, write using E
Recovery time, RP high to E going low
t
t
t
ELEH
EHEL
PHEL
20
30
40
w(EH)
215
215
215
rec(RPHE)
NOTE 10: A –A16 for byte-wide
–1
20
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
t
c(R)
Address Valid
a(A)
A
–A16 ( byte-wide)
–1
A0–A16 (word-wide)
t
E
t
dis(E)
t
a(E)
G
t
dis(G)
t
a(G)
W
t
d(G)
t
h(D)
t
d(E)
DQ0–DQ7 (byte-wide)
DQ0–DQ15 (word-wide)
Hi-Z
Hi-Z
V
CC
t
d(RP)
RP
Figure 7. Read-Cycle Timing
21
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte/Word-
Programming
Write
Read-Array
Command
Read Status-
Register Bits
A
–A16
–1
(byte-wide)
A0–A16
(word-wide)
t
c(W)
t
t
su(A)
h(A)
E
G
t
su(E)
t
h(E)
t
c(W)OP
t
w(WH)
W
t
w(W)
su(D)
h(D)
Data
t
t
Valid SR
FFh
Hi-Z
DQ0–DQ7
(byte-wide)
DQ0–DQ15
(word-wide)
Hi-Z
Hi-Z
40h or 10h
t
su(RP)
t
rec(RPHW)
t
h(RP)
RP
t
h(VPP)
t
su(VPP)1
V
PP
Figure 8. Write-Cycle Timing (W-Controlled Write)
22
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
–A16
Write
Program-Setup
Command
Write Valid
Address
And Data
Automated
Byte/Word-
Programming
Write
Read-Array
Command
Read Status
Register Bits
A
–1
(byte-wide)
A0–A16
(word-wide)
t
c(W)
t
t
su(A)
h(A)
W
G
E
t
su(W)
t
h(W)
t
c(E)OP
t
w(EH)
t
w(E)
Data
t
t
su(D)
h(D)
Valid SR
FFh
Hi-Z
DQ0–DQ7
(byte-wide)
DQ0–DQ15
(word-wide)
Hi-Z
Hi-Z
40h or 10h
rec(RPHE)
t
su(RP)
t
h(RP)
t
RP
t
h(VPP)
t
su(VPP)2
V
PP
Figure 9. Write-Cycle Timing (E-Controlled Write)
23
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power
Up and
Standby
Write
Erase-Setup
Command
Write Erase-
Confirm
Command
Write
Read-Array
Command
Automated
Erase
Read Status-
Register Bits
A
–A16
–1
(byte-wide)
A0–A16
(word-wide)
t
c(W)
t
t
su(A)
h(A)
E
G
t
su(E)
t
h(E)
t
c(W)ERB
t
t
c(W)ERP
c(W)ERM
t
w(WH)
W
t
w(W)
D0h
t
t
su(D)
h(D)
DQ0–DQ7
(byte-wide)
DQ0–DQ15
(word-wide)
Valid SR
FFh
Hi-Z
Hi-Z
Hi-Z
20h
t
rec(RPHW)
t
su(RP)
t
h(RP)
V
V
HH
IH
RP
t
h(VPP)
t
su(VPP)1
V
V
PPH
V
PP
PPL
Figure 10. Erase-Cycle Timing (W-Controlled Write)
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
–A16
Standby
Write
Erase-Setup
Command
Write Erase-
Confirm
Command
Write
Read-Array
Command
Automated
Erase
Read Status-
Register Bits
A
–1
(byte-wide)
A0–A16
(word-wide)
t
c(W)
t
t
su(A)
h(A)
W
G
E
t
su(W)
t
h(W)
t
t
t
c(E)ERB
c(E)ERP
c(E)ERM
t
w(EH)
t
w(E)
D0h
t
su(D)
h(D)
Valid SR
DQ0– DQ7
(byte-wide)
DQ0– DQ15
(word-wide)
t
FFh
Hi-Z
Hi-Z
Hi-Z
20h
rec(RPHE)
t
t
su(RP)
t
h(RP)
RP
t
h(VPP)
t
su(VPP)2
V
PP
Figure 11. Erase-Cycle Timing (E-Controlled Write)
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
A0–A16
Address Valid
t
c(R)
t
a(A)
E
t
a(E)
t
t
dis(E)
G
dis(G)
t
a(G)
BYTE
t
h(D)
t
su(EB)
Hi-Z
Hi-Z
DQ0–DQ7
Byte DQ0–DQ7
Word DQ0–DQ7
t
d(G)
t
d(E)
DQ8–DQ14
Hi-Z
Hi-Z
t
a(A)
t
dis(BL)
Word DQ8–DQ14
Hi-Z
Hi-Z
DQ15/A
–1
A
Input
–1
Word DQ15
Figure 12. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
26
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TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
A0–A16
Address Valid
t
c(R)
t
a(A)
E
t
a(E)
t
t
t
dis(E)
dis(G)
h(D)
G
t
a(G)
BYTE
t
su(EB)
Byte DQ0–DQ7
t
a(BH)
Hi-Z
Hi-Z
DQ0–DQ7
t
t
d(G)
Word DQ0–DQ7
d(E)
DQ8–DQ14
Hi-Z
Hi-Z
Word DQ8–DQ14
Word DQ15
DQ15/A
–1
A
Input
–1
Hi-Z
Hi-Z
Figure 13. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
MECHANICAL DATA
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
M
1,27
0,16
0,35
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°–8°
0,80
Seating Plane
0,10
2,625 MAX
0,50 MIN
4073325/A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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