TMS28F210-10C4FNL [TI]
64KX16 FLASH 12V PROM, 100ns, PQCC44, 1.25 MM PITCH, PLASTIC, LCC-44;
| 型号： | TMS28F210-10C4FNL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 64KX16 FLASH 12V PROM, 100ns, PQCC44, 1.25 MM PITCH, PLASTIC, LCC-44 可编程只读存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
FN PACKAGE
(TOP VIEW)
Organization . . . 65536 by 16-Bits
Pin Compatible With Existing 1-Megabit
EPROMs
All Inputs/Outputs TTL Compatible
6
5
4
3
2 1 44 43 42 41 40
V
Tolerance ±10%
CC
7
DQ12
DQ11
DQ10
DQ9
39 A13
38 A12
37 A11
36 A10
35 A9
Maximum Access/Minimum Cycle Time
’28F210-10 100 ns
8
9
10
11
12
13
14
15
16
17
’28F210-12 120 ns
’28F210-15 150 ns
’28F210-17 170 ns
DQ8
V
SS
34
V
SS
NC
DQ7
DQ6
DQ5
DQ4
33 NC
32 A8
31 A7
30 A6
Industry-Standard Programming Algorithm
PEP4 Version Available With 168-Hour
Burn-In and Choice of Operating
Temperature Ranges
29
A5
18 19 20 21 22 23 24 25 26 27 28
10000 and 1000 Program/Erase Cycles
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation (V
– Active Write . . . 55 mW
= 5.5 V)
CC
– Active Read . . . 165 mW
– Electrical Erase . . . 82.5 mW
– Standby . . . 0.55 mW
(CMOS-Input Levels)
Automotive Temperature Range
– 40°C to 125°C
description
The TMS28F210 is a 65536 by 16-bit (1048 576-bit), programmable read-only memory that can be electrically
bulk-erased and reprogrammed. It is available in 10000- and 1000-program/erase-endurance-cycle versions.
The TMS28F210 flash memory is offered in a 44-lead plastic leaded chip carrier package using 1,25 mm
(50-mil) lead spacing (FN suffix), and a 40-lead thin small-outline package (DBW suffix).
The TMS28F210 is characterized for operation in temperature ranges of 0°C to 70°C, –40°C to 85°C, and
–40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
DBW PACKAGE
(TOP VIEW)
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A9
A10
A11
A12
A13
A14
A15
NC
V
SS
2
A8
A7
A6
A5
A4
A3
A2
A1
A0
G
3
4
5
6
7
8
9
W
10
11
12
13
14
15
16
17
18
19
20
V
CC
V
PP
E
D0
D1
D2
D3
D4
D5
D6
D7
D15
D14
D13
D12
D11
D10
D9
D8
V
SS
PIN NOMENCLATURE
A0–A15
Address Inputs
E
Chip Enable
G
Output Enable
Ground
No Connection
Program
V
NC
SS
W
DQ0–DQ15
Inputs (programming)/Outputs
V
CC
V
PP
5-V Supply
12-V Power Supply
†
†
Only in program mode
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
device symbol nomenclature
TMS28F210
-12 C4 FN
L
Temperature Range Designator
L
E
=
=
0°C to 70°C
– 40°C to 85°C
Q = – 40°C to 125°C
Package Designator
DBW = Thin Small-Outline Package
FN = Plastic Leaded Chip Carrier
Package
Program/Erase Endurance
C4 = 10 000 Cycles
C3 = 1 000 Cycles
Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
†
logic symbol
FLASH
EEPROM
65536 × 16
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
41
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
0
A
65535
A9
A10
A11
A12
A13
A14
A15
15
3
E
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
22
43
G
W
21
DQ0
A, 3D
4
A, Z4
20
19
18
17
16
15
14
11
10
9
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
8
7
6
5
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the FN package.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
†
logic symbol (continued)
FLASH
EEPROM
65536 × 16
31
32
33
34
35
36
37
38
39
1
2
3
4
5
6
7
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
0
A
65535
A9
A10
A11
A12
A13
A14
A15
15
12
E
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
30
9
G
W
29
DQ0
A, 3D
4
A, Z4
28
27
26
25
24
23
22
20
19
18
17
16
15
14
13
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBW package.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
functional block diagram
DQ0–DQ15
16
V
PP
Erase-Voltage Switch
Input/Output Buffers
State Control
W
To Array
Program/Erase
Stop Timer
Program-Voltage
Switch
Command Register
STB
Data Latch
Chip-Enable and
E
Output-Enable
Logic
G
STB
A
d
d
r
e
s
s
Column Decoder
Row Decoder
Column Gating
16
A0–A15
1048576-Bit
Array Matrix
L
a
t
c
h
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
operation
Modes of operation are defined in Table 1.
Table 1. Operation Modes
†‡
FUNCTION
§
V
E
12
3
G
A0
31
24
X
A9
W
9
DQ0–DQ15
PP
11
DBW
PACKAGE
MODE
30
22
1
35
X
13–20, 22–29
FN PACKAGE
2
43
4–11, 14–21
Read
Output Disable
V
V
V
V
IL
V
IL
V
IH
Data Out
PPL
PPL
PPL
V
IL
V
IH
X
X
V
IH
Hi-Z
Read Standby and Write Inhibit
Algorithm-Selection Mode
Read
V
IH
X
X
X
X
Hi-Z
V
IL
Mfr. Equivalent Code 0097h
V
V
IL
V
IL
V
ID
V
IH
PPL
V
IH
Device Equivalent Code 00E5h
V
V
V
V
V
V
V
V
X
X
X
X
X
X
X
X
V
V
Data Out
Hi-Z
PPH
PPH
PPH
PPH
IL
IL
IH
Output Disable
Standby and Write Inhibit
Write
Read/
Write
IL
IH
X
IH
V
IH
X
Hi-Z
V
IL
V
IH
V
IL
Data In
†
‡
§
See the recommended operating conditions table.
X can be V or V
.
IL
IH
+ 2 V; V
V
PPL
≤ V
is the programming voltage specified for the device.
PPH
CC
read/output disable
When the outputs of two or more TMS28F210s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices. To
readtheoutputoftheTMS28F210, alow-levelsignalisappliedtotheEandGpins. Allotherdevicesinthecircuit
should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active I
current can be reduced from 50 mA to 1 mA by applying a high TTL level on E or reduced to 100 µA
CC
with a high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F210 draws
active current when it is deselected during programming, erasure, or program/erase verification. It continues
to draw active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code that identifies the correct programming and
erase algorithms. This mode is activated when A9 is forced to V . Two identifier bytes are accessed by toggling
ID
A0. All other addresses must be held low. A0 low selects the manufacturer-equivalent code 0097h, and A0 high
selects the device-equivalent code 00E5h, as shown in Table 2.
¶
Table 2. Algorithm-Selection Modes
#
PINS
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
0097
00E5
Manufacturer-Equivalent Code
Device-Equivalent Code
V
1
1
0
1
0
1
1
0
0
0
1
1
1
0
1
1
IL
V
IH
¶
#
E = G = A1–A8 = A10–A15 = V , A = V , V
IL ID PP
= V
9
PPL
D8–D15 are not shown in the table because the upper eight data bits read 0.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Afterwards, the entire chip is erased. At this point, the bits, now logic 1s, can be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
command register
The command register controls the program and erase functions of the TMS28F210. The algorithm-selection
mode can be activated using the command register in addition to the above method. When V
is high, the
PP
contents of the command register and the function being performed can be changed. The command register
is written to when E is low and W is pulsed low. The address is latched on the leading edge of the pulse, while
the data is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation. The command register is inhibited when V is below
CC
the erase/write lockout voltage, V
.
LKO
power supply considerations
Eachdeviceshouldhavea0.1-µFceramiccapacitorconnectedbetweenV andV tosuppresscircuitnoise.
CC
SS
Changes in current drain on V requires it to have a bypass capacitor as well. Printed circuit traces for both
PP
power supplies should be appropriate to handle the current demand.
command definitions
See Table 3 for command definitions.
Table 3. Command Definitions
REQUIRED
BUS
CYCLES
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
†
†
OPERATION
ADDRESS
DATA
OPERATION
ADDRESS
DATA
Read
1
3
Write
X
0000h
Read
RA
RD
0000
0001
0097h
00E5h
Algorithm-Selection Mode
Write
X
0090h
Read
Set-Up-Erase/Erase
Erase Verify
2
2
2
2
2
Write
Write
Write
Write
Write
X
EA
X
0020h
00A0h
0040h
00C0h
00FFh
Write
Read
Write
Read
Write
X
X
20h
EVD
PD
Set-Up-Program/Program
Program Verify
Reset
PA
X
X
PVD
00FFh
X
X
†
Modes of operation are defined in Table 1.
Legend:
EA
RA
PA
RD
EVD
PD
PVD
X
Address of memory location to be read during erase verify
Address of memory location to be read
Address of memory location to be programmed. Address is latched on the falling edge of W.
Data read from location RA during the read operation
Data read from location EA during erase verify
Data to be programmed at location PA. Data is latched on the rising edge of W.
Data read from location PA during program verify
Don’t care.
read command
Memory contents can be accessed while V is high or low. When V is high, writing 0000h into the command
PP
PP
register invokes the read operation. When the device is powered up, the default contents of the command
register are 0000h and the read operation is enabled. The read operation remains enabled until a different valid
command is written to the command register.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
algorithm-selection-mode command
The algorithm-selection mode is activated by writing 0090h into the command register. The manufacturer
equivalent code (0097h) is identified by the value read from address location 0000h, and the device equivalent
code (00E5h) is identified by the value read from address location 0001h.
set-up-program/program commands
The programming algorithm initiates with E = V , W = V , G = V , V = V
, and V
= 5 V. To enter the
CC
IL
IL
IH PP
PPH
programming mode, write the set-up-program command, 0040h, into the command register. The programming
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W,
and data is latched internally on the rising edge of W. The programming operation begins on the rising edge
of W and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion
before the program-verify command, 00C0h, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a command is received.
program-verify command
The TMS28F210 can be programmed sequentially or randomly because it is programmed one word at a time.
Each word must be verified after it is programmed. The program-verify operation prepares the device to verify
the most recently programmed word. To invoke the program-verify operation, 00C0h must be written into the
command register. The program-verify operation ends on the rising edge of W.
While verifying a word, the TMS28F210 applies an internal margin voltage to the designated word. If the true
data and programmed data match, programming continues to the next designated word location; otherwise, the
word must be reprogrammed. Figure 1 shows how commands and bus operations are combined for word
programming.
set-up-erase/erase commands
TheerasealgorithminitiateswithE=V ,W=V , G=V ,V =V
, andV =5V. Toentertheerasemode,
CC
IL
IL
IH PP
PPH
write the set-up-erase command, 0020h, into the command register. After the TMS28F210 is in the erase mode,
writing a second erase command, 0020h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of W and ends on the rising edge of the nextW. The erase operation requires
10 ms to complete before the erase-verify command, 00A0h, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a command is received.
erase-verify command
All words must be verified following an erase operation. After the erase operation is complete, an erased word
can be verified by writing the erase-verify command, 00A0h, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the word to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a command is written to the command
register.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
Bus
Operation
Start
Command
Comments
Initialize
Address
Address = 00h
Standby
Write
Wait for V
to ramp to
PP
V
CC
= 5 V ± 10%, V
= 12 V ± 5%
PP
V
PPH
(see Note A)
Setup
X = 1
Initialize pulse count
Write Set-Up-Program
Command
Set-Up-Pr Data = 0040h
ogram
Write
Write Data Valid address/data
Write Data
Increment
Address
Wait = 10 µs
X = X + 1
No
Standby
Wait = 10 µs
Write Program-Verify Command
Write
Program-
Verify
Data = 00C0h; ends
program operation
Wait = 6 µs
Standby
Wait = 6 µs
Read
and Verify
Word
Fail
X = 25?
Read
Read word to verify
programming; compare
output to expected output
Yes
Pass
Interactive
Mode
No
Last
Address
?
Yes
Write Read Command
Power
Down
Write
Read
Data = 0000h; resets
register for read operations
Apply V
Apply V
PPL
PPL
Standby
Wait for V
to ramp to
PP
(see Note B)
V
PPL
Device Passed
Device Failed
NOTES: A. Refer to the recommended operating conditions for the value of V
B. Refer to the recommended operating conditions for the value of V
PPH
PPL
Figure 1. Programming Flowchart: Fastwrite Algorithm
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
erase-verify command (continued)
To determine whether or not all the words have been erased, the TMS28F210 applies a margin voltage to each
word. If FFFFh is read from the word, all bits in the designated word have been erased. The erase-verify
operationcontinuesuntilallofthewordshavebeenverified. IfFFFFhisnotreadfromaword, anadditionalerase
operation needs to be executed. Figure 2 shows the combination of commands and bus operations for
electrically erasing the TMS28F210.
reset command
To reset the TMS28F210 after a set-up-erase operation or a set-up-program operation without changing the
contents in memory, write 00FFh into the command register two consecutive times. After executing the reset
command, the device defaults to the read mode.
Fastwrite algorithm
The TMS28F210 is programmed using the Texas Instruments fastwrite algorithm previously shown in Figure
1. This algorithm programs in a nominal time of two seconds.
Fasterase algorithm
The TMS28F210 is erased using the Texas Instruments fasterase algorithm shown in Figure 2. The memory
array needs to be programmed completely (using the fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
To reduce total erase time, several devices can be erased in parallel. Since each flash memory can erase at
a different rate, every device must be verified separately after each erase pulse. After a given device has been
erased successfully, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished shown in Figure 3.
Examplesof how to mask a device during parallel erase include driving the E pin high, writing the read command
(0000h) to the device when the others receive a set-up-erase or erase command, or disconnecting it from all
electrical signals with relays or other types of switches.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
Bus
Operation
Start
Command
Comments
Entire memory must = 0000h
before erasure
Preprogram
All
Words =
0000h
Program All
Words to
0000h
No
Use Fastwrite
programming algorithm
?
Yes
Initialize addresses
Address = 00h
Standby
Wait for V
to ramp to
PP
(see Note A)
V
CC
= 5 V ± 10%, V
= 12 V ± 5%
PP
V
PPH
Setup
X = 1
Initialize pulse count
Data = 0020h
Write Set-Up-Erase Command
Write Erase Command
Write
Write
Set-Up-
Erase
Erase
Data = 0020h
Wait = 10 ms
Wait = 10 ms
Write Erase-Verify Command
Wait = 6 µs
X = X + 1
Standby
Write
Interactive
Mode
Erase
Verify
Addr = Word to verify;
data = 00A0h; ends the erase
operation
Standby
Read
Wait = 6 µs
No
X = 1000?
Yes
Increment
Address
Read
and Verify
Word
Fail
Read word to verify erasure;
compare output to FFFFh
Pass
No
Last
Address?
Yes
Write Read Command
Write
Read
Data = 0000h; resets register
for read operations
Power
Down
Apply V
Apply V
PPL
PPL
Standby
Wait for V
to ramp to
PP
(see Note B)
V
PPL
Device Passed
Device Failed
NOTES: A. Refer to the recommended operating conditions for the value of V
B. Refer to the recommended operating conditions for the value of V
PPH
PPL
Figure 2. Flash-Erase Flowchart: Fasterase Algorithm
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
Start
Program All Devices to 0000h
X = 1
Give Erase Command To All
Devices
D = 1
Yes
Is
Device #D
Erased
?
Mask Device #D
X = X + 1
No
Give Erase
Command To
All Unmasked
Devices
No
D = n
?
D = D + 1
Yes
No
Are
No
All Devices
Erased
?
X = 1000
?
Yes
Yes
Give Read
Command To
All Devices
Give Read
Command To
All Devices
All Devices Pass
Finished With Errors
NOTE: n = number of devices being erased
Figure 3. Parallel-Erase Flow Diagram
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Programming supply voltage range, V
Input voltage range (see Note 2): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V
PP
+ 1 V
CC
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V + 1 V
CC
Operating free-air temperature range during read/erase/program, T
A
L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to V
.
SS
2. The voltage on any input can undershoot to –2 V for periods less than 20 ns.
3. The voltage on any output can overshoot to 7 V for periods less than 20 ns.
recommended operating conditions
MIN
4.5
0
NOM
MAX
UNIT
V
V
V
V
Supply voltage
During write/read/flash erase
5
5.5
V
V
V
V
CC
PP
ID
During read only (V
)
V
CC
+2
PPL
During write/read/flash erase (V
Programming supply voltage
)
11.4
11.5
2
12
12.6
PPH
Voltage level on A9 for algorithm-selection mode
13
TTL
V
V
+0.5
CC
High-level dc input voltage
V
V
IH
CMOS
TTL
CMOS
L
V
– 0.5
CC
–0.5
+0.5
CC
0.8
V
IL
Low-level dc input voltage
GND – 0.2
GND+0.2
0
– 40
– 40
70
85
T
A
Operating free-air temperature
E
°C
Q
125
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
= – 2.5 mA
MIN
MAX
UNIT
TTL
I
I
I
I
2.4
OH
OH
OL
OL
V
V
High-level output voltage
V
OH
CMOS
TTL
= – 100 µA
V
– 0.4
CC
= 5.8 mA
0.45
0.1
Low-level output voltage
Input current (leakage)
V
OL
CMOS
All except A9
A9
= 100 µA
V = 0 V to 5.5 V
±1
I
I
I
µA
V = 0 V to 13 V
± 200
±10
I
I
I
Output current (leakage)
V
= 0 V to V
O CC
µA
µA
µA
µA
O
A9 algorithm-selection-mode current
A9 = V max
ID
± 200
200
ID
V
= V
= V
,
Read mode
PP
PP
PPH
PPL
I
V
supply current (read/standby)
PP1
PP
PP
V
±10
V
supply current (during program pulse)
I
I
I
V
V
V
= V
= V
= V
50
50
5
mA
mA
mA
PP2
PP3
PP4
PP
PP
PP
PPH
PPH
PPH
(see Note 4)
V
supply current (during flash erase)
PP
(see Note 4)
V
supply current (during program/erase verify)
PP
(see Note 4)
TTL-input level
V
V
V
= 5.5 V,
E = V
E = V
E = V
1
mA
CC
IH
I
V
supply current (standby)
CCS
CC
CMOS-input level
5.5 V,
100
µA
CC =
CC
= 5.5 V,
= 0 mA,
,
IL
CC
I
I
I
V
V
supply current (active read)
50
10
15
mA
mA
mA
CC1
CC2
CC3
CC
I
f = 6 MHz
OUT
average supply current (active write)
V
CC
= 5.5 V,
E = V
,
IL
,
IL
,
IL
CC
(see Note 4)
Programming in progress
V
average supply current (flash erase)
V
= 5.5 V,
E = V
CC
(see Note 4)
CC
Erasure in progress
V
CC
V
PP
= 5.5 V,
E = V
V
average supply current (program/erase verify)
CC
(see Note 4)
I
= V
,
PPH
15
mA
CC4
Program/erase verify in progress
NOTE 4: Characterization data available
capacitance over recommended ranges of supply voltage and operating free-air temperature,
†
f = 1 MHz
PARAMETER
TEST CONDITIONS
MIN
MAX
6
UNIT
pF
C
C
Input capacitance
Output capacitance
V = 0 V,
f = 1 MHz
f = 1 MHz
i
I
V
O
= 0 V,
12
pF
o
†
Capacitance measurements are made on sample basis only.
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’28F210-10
’28F210-12
’28F210-15
’28F210-17
TEST
CONDITIONS
ALTERNATE
SYMBOL
PARAMETERS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time
from address
t
t
t
t
t
100
100
45
120
120
50
150
150
55
170
170
60
ns
ns
ns
ns
a(A)
AVQV
Access time
from E
t
a(E)
ELQV
GLQV
Access time
from G
t
en(G)
c(R)
Cycle time,
read
t
100
0
120
0
150
0
170
0
AVAV
Delay time, chip
enable low to
low-Z output
t
t
ns
d(E)
ELQX
C
= 100 pF,
L
1 Series 74
TTL load,
Input t ≤ 20 ns,
Delay time, G
low to low-Z
output
t
t
t
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
d(G)
GLQX
EHQZ
GHQZ
r
f
Input t ≤ 20 ns
Chip disable to
hi-Z output
55
30
55
30
55
35
55
35
dis(E)
dis(G)
Disable time,
output enable to
hi-Z output
t
Hold time, data
valid from
t
t
0
6
0
6
0
6
0
6
ns
h(D)
AXQX
address, E, or
†
G
Write recovery
time before
read
t
t
µs
rec(W)
WHGL
†
Whichever occurs first
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
timing requirements—write/erase/program operations
’28F210-10
’28F210-12
ALTERNATE
SYMBOL
UNIT
MIN NOM
MAX
MIN NOM
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write using W
Cycle time, programming operation
Cycle time, erase operation
Hold time, address
t
100
10
120
10
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
c(W)
AVAV
t
t
c(W)PR
c(W)ER
h(A)
WHWH1
9.5
55
0
10
9.5
60
0
10
WHWH2
t
WLAX
Hold time, E
t
t
h(E)
WHEH
WHDX
Hold time, data valid after W high
Setup time, address
10
0
10
0
h(WHD)
su(A)
t
AVWL
Setup time, data
t
50
20
100
1
50
20
100
1
su(D)
DVWH
Setup time, E before W
t
su(E)
ELWL
t
EHVP
Setup time, E high to V
ramp
su(EHVPP)
su(VPPEL)
rec(W)
rec(R)
w(W)
PP
to E low
Setup time, V
PP
t
VPEL
WHGL
GHWL
WLWH
WHWL
Recovery time, W before read
Recovery time, read before W
Pulse duration, W
t
t
6
6
0
0
t
60
20
1
60
20
1
Pulse duration, W high
t
w(WH)
r(VPP)
f(VPP)
Rise time, V
t
VPPR
PP
Fall time, V
t
1
1
PP
VPPF
’28F210-15
MIN NOM
150
’28F210-17
MIN NOM
170
ALTERNATE
SYMBOL
UNIT
MAX
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write using W
Cycle time, programming operation
Cycle time, erase operation
Hold time, address
t
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
c(W)
AVAV
t
t
10
10
c(W)PR
c(W)ER
h(A)
WHWH1
9.5
60
0
10
9.5
70
0
10
WHWH2
t
WLAX
Hold time, E
t
t
h(E)
WHEH
Hold time, data valid after W high
Setup time, address
10
0
10
0
h(WHD)
su(A)
WHDX
t
AVWL
Setup time, data
t
50
20
100
1
50
20
100
1
su(D)
DVWH
Setup time, E before W
t
su(E)
ELWL
t
EHVP
Setup time, E high to V
ramp
su(EHVPP)
su(VPPEL)
rec(W)
rec(R)
w(W)
PP
to E low
Setup time, V
PP
t
VPEL
WHGL
GHWL
WLWH
WHWL
Recovery time, W before read
Recovery time, read before W
Pulse duration, W
t
t
6
6
0
0
t
60
20
1
60
20
1
Pulse duration, W high
t
w(WH)
r(VPP)
f(VPP)
Rise time, V
t
VPPR
PP
Fall time, V
t
1
1
PP
VPPF
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
timing requirements—alternative E-controlled writes
’28F210-10
’28F210-12
’28F210-15
’28F210-17
ALTERNATE
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write using E
t
100
120
150
170
ns
c(W)
AVAV
Cycle time, programming
operation
t
10
10
10
10
µs
c(E)PR
EHEH
t
t
t
t
t
t
t
Hold time, address
Hold time, data
t
75
10
0
80
10
0
80
10
0
90
10
0
ns
ns
ns
ns
ns
ns
µs
h(EA)
ELAX
t
h(ED)
h(W)
EHDX
Hold time, W
t
EHWH
Setup time, address
Setup time, data
Setup time, W before E
t
0
0
0
0
su(A)
AVEL
t
50
0
50
0
50
0
50
0
su(D)
DVEH
t
su(W)
su(VPPEL)
WLEL
Setup time, V
PP
to E low
t
1
1
1
1
VPEL
Recovery time, write using E
before read
t
t
t
t
6
0
6
0
6
0
6
0
µs
µs
rec(E)R
rec(E)W
EHGL
Recovery time, read before
write using E
GHEL
t
t
Pulse duration, write using E
Pulse duration, write, E high
t
t
70
20
70
20
70
20
80
20
ns
ns
w(E)
ELEH
w(EH)
EHEL
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
= 800 Ω
L
Output
Under Test
C
= 100 pF
L
(see Note A)
LOAD CIRCUIT
2.4 V
2 V
0.8 V
2 V
0.8 V
0.45 V
VOLTAGE WAVEFORMS
NOTES: A.
C
L
includes probe and fixture capacitance.
B. AC testing inputs are driven at 2.4 V for logic high
and 0.45 V for logic low. Timing measurements
are made at
2
V
for logic high and
0.8 V for logic low on both inputs and outputs.
Each device should have a 0.1-µF ceramic
capacitor connected between V
close as possible to the device pins.
and V as
CC
SS
Figure 4. Load Circuit and Voltage Waveforms
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
t
c(R)
A0–A15
Address Valid
t
a(A)
E
t
t
dis(E)
a(E)
G
W
t
rec(W)
t
en(G)
t
dis(G)
t
d(G)
t
h(D)
t
d(E)
DQ0–DQ15
Hi-Z
Output Valid
Hi-Z
Figure 5. Read-Cycle Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Address
and Data
Set-Up-
Program
Command
Program-
Verify
Command
Programming
Power Up
and
Standby
Program
Standby/
Verification
Power Down
A0–A15
t
t
c(W)
c(W)
t
c(R)
t
c(W)
t
t
su(A)
h(A)
t
h(A)
t
su(A)
E
t
t
dis(E)
su(E)
t
su(E)
t
su(E)
t
t
h(E)
h(E)
t
h(E)
G
t
c(W)PR
t
t
w(WH)
rec(R)
t
t
dis(G)
rec(W)
W
t
h(D)
t
h(D)
t
h(D)
t
en(G)
t
h(D)
t
t
w(W)
w(W)
t
d(G)
t
w(W)
t
su(D)
t
su(D)
t
su(D)
Hi-Z
DQ0–
DQ15
Data In
Valid Data Out
t
d(E)
Data In = 0040h
Data In = 00C0h
t
a(E)
5 V
V
CC
0 V
t
su(VPPEL)
V
PPH
V
PP
V
PPL
t
f(VPP)
t
r(VPP)
Figure 6. Write-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Address
and Data
Set-Up-
Program
Command
Program-
Verify
Command
Programming
Power Up
and
Standby
Program
Standby/
Verification
Power Down
A0–A15
t
t
c(W)
c(W)
t
c(R)
t
c(W)
t
t
su(A)
h(A)
t
h(A)
t
su(A)
W
t
t
t
su(W)
dis(G)
su(W)
t
su(W)
t
t
h(W)
h(W)
t
h(W)
G
E
t
c(E)PR
t
rec(E)W
t
t
dis(E)
rec(E)R
t
w(EH)
t
h(D)
t
h(D)
t
h(D)
t
en(G)
t
d(G)
t
h(D)
t
w(E)
t
w(E)
t
w(E)
t
t
t
su(D)
su(D)
Hi-Z
su(D)
DQ0–
DQ15
Data In
Valid Data Out
t
d(E)
Data In = 0040h
Data In =00C0h
t
a(E)
5 V
CC
V
0 V
t
su(VPPEL)
V
PPH
V
PP
V
PPL
t
f(VPP)
t
r(VPP)
Figure 7. Write-Cycle (Alternative E-Controlled Writes) Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Set-Up
Erase
Erase
Verify
Power-Up
and
Erase
Erase
Standby/
Command
Verification
Command
Command
Power-Down
Standby
Erasing
A0–A15
t
c(W)
t
c(R)
t
c(W)
t
t
c(W)
h(A)
t
su(A)
E
t
su(E)
t
t
su(E)
su(E)
t
t
t
h(E)
dis(E)
h(E)
t
h(E)
G
t
w(WH)
t
rec(W)
t
rec(R)
t
c(W)ER
t
dis(G)
W
t
h(D)
t
h(D)
t
en(G)
t
t
h(D)
h(D)
t
w(W)
t
t
w(W)
d(G)
t
w(W)
t
t
su(D)
t
su(D)
su(D)
DQ0–
DQ15
Hi-Z
Data In = 0020h
Valid Data Out
t
d(E)
Data In = 0020h
su(VPPEL)
Data In = 00A0h
t
a(E)
5 V
V
CC
0 V
t
V
PP
PPH
V
V
PPL
t
f(VPP)
t
r(VPP)
Figure 8. Flash-Erase-Cycle Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
0.050 (1,27)
9
13
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F210
65536 BY 16-BIT
FLASH MEMORY
SMJS210D – DECEMBER 1992 – REVISED AUGUST 1997
MECHANICAL DATA
DBW (R-PDSO-G40)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
1
40
0.020 (0,50)
0.386 (9,80)
0.402 (10,20)
0.010 (0,25)
0.006 (0,15)
0.007 (0,18)
M
21
20
0.484 (12,30)
0.492 (12,50)
0.024 (0,60)
0.016 (0,40)
0.047 (1,20) MAX
Seating Plane
0.004 (0,10)
0.005 (0,13) MIN
0.006 (0,15)
NOM
0.559 (14,20)
0.543 (13,80)
4073304/A 09/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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