TMS28F400AMT60CDCDE [TI]
256KX16 FLASH 12V PROM, 110ns, PDSO48, TSOP-48;型号: | TMS28F400AMT60CDCDE |
厂家: | TEXAS INSTRUMENTS |
描述: | 256KX16 FLASH 12V PROM, 110ns, PDSO48, TSOP-48 可编程只读存储器 光电二极管 内存集成电路 |
文件: | 总80页 (文件大小:1128K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
DBJ PACKAGE
(TOP VIEW)
Organization . . . 524288 By 8 Bits
262144 By 16 Bits
Array-Blocking Architecture
V
1
2
3
4
5
6
7
8
9
44 RP
43
42 A8
PP
DU/WP
A17
A7
W
– One 16K-Byte Protected Boot Block
– Two 8K-Byte Parameter Blocks
– One 96K-Byte Main Block
– Three 128K-Byte Main Blocks
– Top or Bottom Boot Locations
41 A9
A6
A5
A4
A3
A2
A1 10
A0 11
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
’28F400Axy Offers a User-Defined 8-Bit
(Byte) or 16-Bit (Word) Organization
’28F004Axy Offers Only the 8-Bit
Organization
34
33 BYTE
32
A16
E
12
13
14
Maximum Access/Minimum Cycle Time
– Commercial and Extended
V
V
SS
SS
G
31 DQ15/A
30 DQ7
29 DQ14
–1
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
5-V V
± 10%
3.3-V V
± 0.3 V
CC
CC
’28F400Axy60 60 ns 110 ns
’28F400Axy70 70 ns 130ns
’28F400Axy80 80 ns 150 ns
28
DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
– Automotive (offered for only 5-V V
voltage configurations)
CC
23
V
CC
5-V V
± 10%
CC
’28F400Axy70 70 ns
’28F400Axy80 80 ns
’28F400Axy90 90 ns
PIN NOMENCLATURE
A0–A17
BYTE
Address Inputs
Byte Enable
(x = S, E, F, M, or Z Depending on V /V
Configuration)
(y = T or B for Top or Bottom Boot-Block
Configuration)
CC PP
DQ0–DQ14 Data In/Out
DQ15/A
Data In/Out (word-wide mode),
–1
Low-Order Address (byte-wide mode)
Chip Enable
E
G
Output Enable
100000 and 10000 Program/Erase Cycle
Versions
NC
RP
No Internal Connection
Reset/Deep Power-Down
Power Supply
Three Temperature Ranges
V
CC
V
PP
V
SS
– Commercial . . . 0°C to 70°C
– Extended . . . – 40°C to 85°C
– Automotive . . . – 40°C to 125°C
Power Supply for Program/Erase
Ground
W
Write Enable
Industry Standard Packages Offered in
– 40-Pin TSOP (DCD Suffix)
– 44-Pin PSOP (DBJ Suffix)
DU/WP
Do Not Use for ’AMy or ’AZy /Write Protect
Fully Automated On-Chip Erase and
Word/Byte Program Operations
– 48-Pin TSOP (DCD Suffix)
Low Power Dissipation (V
= 5.5 V)
CC
Write Protection for Boot Block
– Active Write . . . 248 mW (Byte Write)
– Active Read . . . 330 mW (Byte Read)
– Active Write . . . 248 mW (Word Write)
– Active Read . . . 330 mW (Word Read)
– Block Erase . . . 165 mW
Industry Standard Command-State Machine
(CSM)
– Erase Suspend/Resume
– Algorithm-Selection Identifier
Three Different Combinations of Supply
Voltages Offered
– Standby . . . 0.72 mW (CMOS-Input
Levels)
All Inputs/Outputs TTL Compatible
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
DCD PACKAGE-40 PIN
(TOP VIEW)
A16
A15
A14
A13
A12
A11
A9
A17
GND
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
3
NC
4
A10
DQ7
DQ6
DQ5
DQ4
5
6
7
A8
8
W
9
RP
V
10
11
12
13
14
15
16
17
18
19
20
CC
V
V
PP
CC
DU/WP
A18
A7
NC
DQ3
DQ2
DQ1
DQ0
G
A6
A5
A4
A3
GND
E
A2
A1
A0
DCD PACKAGE-48 PIN
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A16
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE
GND
DQ15/A
DQ7
2
3
4
–1
5
DQ14
DQ6
6
7
A8
8
DQ13
DQ5
NC
NC
W
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
RP
V
CC
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
PP
DU/WP
NC
NC
A17
A7
A6
A5
A4
A3
GND
E
A2
A1
A0
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
device symbol nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
block memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
boot-block data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
parameter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
command-state machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . 8
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
byte-wide or word-wide mode selection . . . . . . . . . . . . . . . . 11
command-state machine (CSM) operations . . . . . . . . . . . 13
clear status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
programming operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
automatic power-saving mode . . . . . . . . . . . . . . . . . . . . . . . 15
reset/deep power-down mode . . . . . . . . . . . . . . . . . . . . . . 15
power-supply detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TMS28F004ASy and TMS28F400ASy . . . . . . . . . . . . . . . . . . . 23
TMS28F004AEy and TMS28F400AEy . . . . . . . . . . . . . . . . . . . 33
TMS28F004AMy and TMS28F400AMy . . . . . . . . . . . . . . . . . . 44
TMS28F004AFy and TMS28F400AFy . . . . . . . . . . . . . . . . . . . 52
TMS28F004AZy and TMS28F400AZy . . . . . . . . . . . . . . . . . . . 62
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . 71
mechanical data – DBJ (R-PDSO-G44) . . . . . . . . . . . . . . . . . 78
mechanical data – DCD (R-PDSO-G**) . . . . . . . . . . . . . . . . . 79
description
The TMS28F400Axy is a 524288 by 8 bits/262144 by 16 bits (4194304-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F400Axy is organized in a blocked architecture
consisting of:
One 16K-byte protected boot block
Two 8K-byte parameter blocks
One 96K-byte main block
Three 128K-byte main blocks
Table 1 lists the five different voltage configurations available for ordering. Operation as a 512K-byte (8-bit) or
a 256K-word (16-bit) organization is user-definable.
Table 1. V /V Voltage Configurations, Temperature, and Speeds Matrix
CC PP
DEVICE CONFIGURATION
TEMPERATURE
DEVICE
READ (V
)
PROGRAM/ERASE (V
ACCESS SPEEDS – 5-V(3.3-V) V
CC
CC
PP)
(T )
A
0°C to 70°C
–40°C to 85°C
0°C to 70°C
60(110), 70(130), 80(150) ns
60(110), 70(130), 80(150) ns
60(110), 70(130), 80(150) ns
60(110), 70(130), 80(150) ns
60(110), 70(130), 80(150) ns
60(110), 70(130), 80(150) ns
60, 70, 80 ns
TMS28F400ASy
3.3 V± 0.3 V or 5 V±10%
2.7 to 3.6 V or 5 V±10%
5 V±10% or 12 V±5%
5 V±10% or 12 V±5%
12 V±10%
TMS28F400AEy
–40°C to 85°C
0°C to 70°C
TMS28F400AMy 3.3 V± 0.3 V or 5 V±10%
–40°C to 85°C
0°C to 70°C
TMS28F400AFy
TMS28F400AZy
5 V±10%
5 V±10%
5 V±10% or 12 V±5%
12 V±10%
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
60, 70, 80 ns
†
†
70, 80, 90 ns
60, 70, 80 ns
–40°C to 85°C
–40°C to 125°C
60, 70, 80 ns
70, 80, 90 ns
†
Only the 44-pin PSOP is offered in the –40°C to 125°C temperature range.
NOTE 1: All configurations are available in the TMS28F004Axy (8 bit configuration only) and top or bottom boot.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
description (continued)
The TMS28F004Axy is offered in a 512K-byte organization only. The operation for this device is the same as
the TMS28F400Axy and is offered in the same voltage configurations. TMS28F004Axy can be substituted for
the byte-wide TMS28F400Axy with the latter being the generic name for this device family.
Embedded program and block-erase functions are fully automated by the on-chip write state machine (WSM),
simplifying these operations and relieving the system microcontroller of secondary tasks. WSM status can be
monitored by an on-chip status register to determine progress of program/erase tasks. The device features
user-selectable block erasure.
The configurations are as follows:
The TMS28F400ASy configuration has the auto-select feature that allows the user alternative read and
program/erase voltages. Memory reads can be performed using 3.3-V V
for optimum power
CC
consumption or 5-V V for device performance. Erasing or programming the device can be accomplished
CC
with 5-V V , which eliminates having to use a 12-V source and/or in-system voltage converters.
PP
Alternatively,12-V V operation exists for systems that already have a 12-V power supply, which provides
PP
faster programming and erasing times. This configuration is offered in two temperature ranges: 0°C to 70°C
and –40°C to 85°C.
The TMS28F400AEy configuration offers the auto-select feature of the TMS28F400ASy with an extended
V
rangeof2.7-Vto3.6-V(3-Vnominal).Memoryreadscanbeperformedusing3-VV ,formoreefficient
CC
CC
power consumption than the ’ASy device.
The TMS28F400AMy configuration offers a 3-V or 5-V memory read with a 12-V program and erase. This
configuration is intended for low 3.3-V reads and the fast programming offered with the 12-V V and 5-V
PP
V
. This configuration is offered in two temperature ranges: 0°C to 70°C and – 40°C to 85°C.
CC
The TMS28F400AFy configuration offers a 5-V memory read with a 5-V or 12-V program and erase. This
configuration is intended for systems using a single 5-V power supply. This configuration is offered in three
temperature ranges: 0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C.
The TMS28F400AZy configuration offers a 5-V memory read with a 12-V program and erase for fast
programming and erasing times. This configuration is offered in three temperature ranges: 0°C to 70°C,
– 40°C to 85°C, and – 40°C to 125°C.
The y in the device name represents a T for top or B for bottom boot-block configuration.
All configurations of the TMS28F400Axy are offered in a 44-pin plastic small-outline package (PSOP) and a
48-pinthinsmall-outlinepackage(TSOP). TheTMS28F004Axyisofferedina40-pinTSOPonly. Boththe40-pin
and 48-pin TSOP are offered for the 0°C to 70°C and – 40°C to 85°C temperature ranges only.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
device symbol nomenclature
TMS28F400AS
T
60
C
DBJ
L
Temperature Range Designator
L
E
=
=
0°C to 70°C
– 40°C to 85°C
Q = – 40°C to 125°C
Package Designator
DBJ = 44 Lead PSOP
DCD= 40 Lead TSOP
DCD= 48 Lead TSOP
Program/Erase Endurance
C
B
= 100000 Cycles
= 10000 Cycles
Speed Designator
60 = 60 ns
Boot-Block Location Indicator
T = Top Location
70 = 70 ns
80 = 80 ns
90 = 90 ns
B = Bottom Location
S
E
= (3.3V ± 0.3V or 5V ± 10%) V
and (5V ± 10% or 12V ± 5%) V
CC
= (2.7 V to 3.6 V or 5 V ± 10%) V
PP
PP
and (5V ± 10% or 12V ± 5%) V
CC
and (12V ± 5%) V
M = (3.3V ± 0.3V or 5V ± 10%) V
F
Z
CC
and (5V ± 10% or 12V ± 5%) V
PP
= 5V ± 10% V
= 5V ± 10% V
CC
CC
PP
and 12V ± 5% V
PP
Configuration
400= 256K 16-bit or 512K 8-bit
004= 512K 8-bit
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
functional block diagram
DQ8–DQ15/A
8
DQ0–DQ7
8
–1
8
DQ15/A
Input Buffer
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
–1
Data
Register
BYTE
I/O Logic
Identification
Register
E
W
G
Output
Multiplexer
Command
State
Machine
Status
Register
RP
WP
17
A0–
A17
Input
Buffer
Power-
Reduction
Control
Data
Comparator
Program/
Write
State
Machine
Erase
Voltage
Switch
V
PP
Address
Latch
Y Decoder
X Decoder
Y Gating/Sensing
16K-Byte
Boot
Block
8K-Byte
Parameter Parameter
Block Block
8K-Byte
96K-Byte 128K-Byte 128K-Byte 128K-Byte
Address
Counter
Main
Block
Main
Block
Main
Block
Main
Block
architecture
The TMS28F400Axy uses a blocked architecture to allow independent erasure of selected memory blocks. The
block to be erased is selected by using any valid address within that block.
block memory maps
The TMS28F400Axy is available with the block architecture mapped in either of two configurations: the boot
block located at the top or at the bottom of the memory array, as required by different microprocessors. The
TMS28F400AxB (bottom boot block) is mapped with the 16K-byte boot block located at the low-order address
range(00000hto01FFFh). TheTMS28F400AxT(topbootblock)isinvertedwithrespecttotheTMS28F400AxB
with the boot block located at the high-order address range (3E000h to 3FFFFh). Both of these address ranges
are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these configurations. The
TMS28F004Axy is mapped as the 8-bit configuration of the TMS28F400Axy, except that the least significant
bit (LSB) is A0 instead of A
.
–1
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
block memory maps (continued)
Address
Range
16-Bit
Configuration
Address
Range
8-Bit Configuration
7FFFFh
3FFFFh
Boot Block
Boot Block
16K Addresses
8K Addresses
7C000h
7BFFFh
3E000h
3DFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
7A000h
79FFFh
3D000h
3CFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
78000h
77FFFh
3C000h
3BFFFh
Main Block
Main Block
96K Addresses
48K Addresses
60000h
5FFFFh
30000h
2FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
40000h
3FFFFh
20000h
1FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
20000h
1FFFFh
10000h
0FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
00000h
00000h
DQ15/A Is LSB Address
–1
A0 Is LSB Address
NOTE A: The TMS28F004AxT is mapped the same as the 8-bit configuration of the TMS28F400AxT except that the LSB is A0.
Figure 1. TMS28F400AxT (Top Boot Block) Memory Map (See Note A)
Address
Range
Address
Range
16-Bit
Configuration
8-Bit Configuration
7FFFFh
3FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
60000h
5FFFFh
30000h
2FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
40000h
3FFFFh
20000h
1FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
20000h
1FFFFh
10000h
0FFFFh
Main Block
Main Block
96K Addresses
48K Addresses
08000h
07FFFh
04000h
03FFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
06000h
05FFFh
03000h
02FFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
04000h
03FFFh
02000h
01FFFh
Boot Block
Boot Block
16K Addresses
8K Addresses
00000h
00000h
DQ15/A Is LSB Address
–1
A0 Is LSB Address
NOTE A: The TMS28F004AxB is mapped the same as the 8-bit configuration of the TMS28F400AxB except that the LSB is A0.
Figure 2. TMS28F400AxB (Bottom Boot Block) Memory Map (See Note A)
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data
in this block can be secured by using different combinations of the reset/power-down pin (RP), the write protect
pin (WP) and V supply levels. Table 2 provides a list of these combinations.
PP
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution must be exercised because the parameter block does not have
the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F400Axy is located in four main blocks. Three of the blocks have storage
capacity for 128K bytes and the fourth block has storage capacity for 96K bytes.
data protection
Data is secured or unsecured by using different combinations of the reset/power-down pin (RP), the write
protect pin (WP), and V supply levels. Table 2 provides a list of these combinations.
PP
There are two configurations to secure the entire memory against inadvertant alteration of data. The V supply
PP
pin can be held below the V lock-out voltage level (V
) or the reset/deep power-down pin (RP) can be
PP
PPLK
pulled to a logic-low level. Note if RP is held low, the device resets which means it powers down and, therefore,
cannot be read. Typically this pin tied to the system reset for additional protection during system power up.
The boot block sector has an additional security feature through the WP pin (’ASy, ’AEy, and ’AFy device
configurations only). When the RP pin is at a logic-high level, the WP pin controls whether the boot block sector
is protected. When WP is held at the logic-low level, the boot block is protected. When WP is held at the
logic-high level, the boot block is unprotected along with the rest of the other sectors. Alternatively, the entire
memory for all voltage configurations can be unprotected by pulling the RP pin to V
(12 V).
HH
Table 2. Data-Protection Combinations
’ASy, ’AEy, OR ’AFy
’AMy OR ’AZy
†
†
DATA PROTECTION PROVIDED
All blocks locked
V
RP
WP
V
RP
WP
PP
PP
V
X
X
V
X
X
IL
IL
All blocks locked (reset)
All blocks unlocked
X
V
X
X
V
X
IL
IL
>V
>V
>V
V
HH
X
V
V
V
HH
X
PPLK
PPLK
PPLK
HH
V
V
IH
IH
IH
Only boot block locked
V
V
IL
V
IH
X
HH
†
For the TMS28F400AZy and TMS28F400AMy 12-V V -only products, the WP pin is disabled and can be left
PP
floating. To unlock blocks, RP must be at V
.
HH
command-state machine (CSM)
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. The available commands are listed in Table 3 and
the descriptions of these commands are shown in Table 4. When a program or erase command is issued to the
CSM, the WSM controls the internal sequences and the CSM responds only to status reads. After the WSM
completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the CSM to respond to the
full command set again.
8
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operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0–DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires a command code to be entered into the CSM. Table 3 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0–DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
Table 3. CSM Codes for Device Mode Selection
COMMAND
CODE ON
DQ0–DQ7
DEVICE MODE
Invalid/Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
†
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
†
DQ0 is the least significant bit. DQ8–DQ15 can be any valid 2-state
level.
command definitions
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and
data for each of the bus cycles. Table 5 lists the status register bits and definitions.
Following the read-algorithm-selection-code command, two read cycles are required to access the
manufacturer-equivalent code and the device-equivalent code. Table 6, Table 7, and Table 8 list the code.
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command definitions (continued)
Table 4. Command Definitions
FIRST BUS CYCLE
OPERATION ADDRESS
Read Operations
SECOND BUS CYCLE
BUS
CYCLES
REQUIRED
COMMAND
CSM
INPUT
DATA
OPERATION ADDRESS
IN/OUT
Read Array
1
2
2
1
Write
Write
Write
Write
X
X
X
X
FFh
90h
70h
50h
Read
Read
Read
X
A0
X
Data Out
M/D
Read Algorithm-Selection Code
Read-Status Register
SRB
Clear-Status Register
Program Mode
Program Setup/Program
(byte/word)
2
Write
PA
40h or 10h
Write
PA
PD
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
2
Write
Write
BEA
X
20h
B0h
Write
Write
BEA
X
D0h
D0h
Erase Suspend/
Erase Resume
Legend:
BEA
M/D
PA
Block-erase address. Any address selected within a block selects that block for erase.
Manufacturer-equivalent/device-equivalent code
Address to be programmed
PD
Data to be programmed at PA
SRB
X
Status-register data byte that can be found on DQ0–DQ7
Don’t care
status register
The status register allows the user to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0–DQ7. This is valid for operation in either the byte- or word-wide mode.
WhenwritingtotheCSMinword-widemode, thehighorderI/Opins(DQ8–DQ15)canbesettoanyvalid2-state
level. When reading the status bits during a word-wide read operation, the high order I/Os (DQ8–DQ15) are
set to 00h internally, so the user needs to interpret only the low order I/O pins (D0–DQ7).
After a read-status command has been given, the data appearing on DQ0–DQ7 remains as status register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of G or E. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring if the register input
change during a status-register read. To ensure that the status-register output contains updated status data,
E or G must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the status
register bits and their functions.
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status register (continued)
Table 5. Status-Register Bit Definitions and Functions
STATUS
FUNCTION
BIT
DATA
COMMENTS
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling
operations can be performed. Until this occurs, the other status
bits are not valid. If the WSM status bit shows busy (0), the user
must toggle E or G periodically to determine when the WSM has
completed an operation (SB7 = 1) since SB7 is not updated
automatically at the completion of a WSM task.
1 = Ready
0 = Busy
SB7
SB6
Write-state-machine status
Erase-suspend status (ESS)
When an erase-suspend command is issued, the WSM halts
execution and sets the ESS bit high (SB6 = 1) indicating that the
erase operation has been suspended. The WSM status bit also
is set high (SB7 = 1) indicating that the erase-suspend operation
has been completed successfully. The ESS bit remains at a
logic-high level until an erase-resume command is input to the
CSM (code D0h).
1 = Erase suspended
0 = Erase in progress or
completed
SB5 = 0 indicates that a successful block erasure has occurred.
SB5 = 1 indicates that an erase error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
erase the device completely.
1 = Block erase error
0 = Block erase good
SB5
SB4
SB3
Erase status (ES)
SB4 = 0 indicates successful programming has occurred at the
addressed block location. SB4 = 1 indicates that the WSM was
unable to program the addressed block location correctly.
1 = Byte/word program error
0 = Byte/word program good
Program status (PS)
SB3 provides information on the status of
V
during
PP
1 = Program abort:
programming.If V is lower than V after a program or erase
PP
command has been issued, SB3 is set to a 1 indicating that the
programming operation is aborted. If V is between V and
PPL
V
PP
status (V
)
PPS
V
0 = V
range error
good
PP
PP
PP
PPH
V , SB3 is not set.
PPL
SB2–
SB0
Reserved
These bits must be masked out when reading the status register.
byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8–DQ15, and
a lower-half that outputs data through DQ0–DQ7. Device operation in either byte-wide or word-wide mode is
user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device
is in the word-wide mode and data is written to, or read from, I/O pins DQ0–DQ15. When BYTE is at a logic-low
level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0–DQ7. In the byte-wide
mode, I/O pins DQ8–DQ14 are placed in the high-impedance state and DQ15/A becomes the low-order
–1
address pin and selects either the upper or lower half of the array. Array data from the upper half (DQ8–DQ15)
and the lower half (DQ0–DQ7) are multiplexed to appear on DQ0–DQ7. Table 6, Table 7, and Table 8
summarize operational modes.
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byte-wide or word-wide mode selection (continued)
Table 6. Operation Modes for Word-Wide Mode (BYTE = V ) (see Note 2)
IH
MODE
WP
E
G
RP
W
A9
A0
V
PP
DQ0–DQ15
Read
X
V
V
V
V
X
X
X
Data out
IL
IL
IH
IH
IH
Manufacturer-equivalent code
0089h
X
X
V
IL
V
V
V
V
IH
V
ID
V
IL
X
X
IL
Device-equivalent code 4470h
(top boot block)
Algorithm-selection mode
V
V
V
IH
V
V
V
ID
V
IH
IL
IL
IH
Device-equivalent code 4471h
(bottom boot block)
Output disable
Standby
X
X
X
V
IH
V
V
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IH
X
X
X
IH
Reset/deep power down
X
X
V
IL
V
or
V
or
V
IL
IH
PPL
or
Write (see Note 3)
V
IL
V
IH
V
IL
X
X
Data in
V
IH
V
HH
V
PPH
NOTES: 2. X = don’t care
3. When writing commands to the ’28F400Axy, V
must be in the appropriate V
voltage range (as shown in the recommended
PP
PP
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).
Table 7. Operation Modes for Byte-Wide Mode (BYTE = V ) (see Note 2)
IL
MODE
WP
X
E
G
RP
W
A9
X
A0
X
V
DQ15/A
DQ8–DQ14
Hi-Z
DQ0–DQ7
Data out
PP
X
–1
Read lower byte
Read upper byte
V
IL
V
IL
V
V
V
IH
V
IL
IH
X
V
IL
V
IL
V
IH
X
X
X
V
IH
Hi-Z
Data out
IH
Manufacturer-equivalent
code 89h
X
X
V
V
V
V
V
V
X
X
X
X
Hi-Z
Hi-Z
IL
IL
IL
IH
IH
ID
IL
Algorithm-selection
mode
Device-equivalent code
70h (top boot block)
V
V
IL
V
IH
V
V
V
ID
V
IH
IH
Device-equivalent code
71h (bottom boot block)
Output disable
Standby
X
X
V
IL
V
IH
V
V
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IH
IH
V
IH
X
X
X
X
IH
Reset/deep power
down
X
X
X
V
IL
X
X
X
X
X
Hi-Z
Hi-Z
V
V
or
V
IL
or
IH
PPL
or
Write (see Note 3)
V
IL
V
IH
V
IL
X
X
X
Hi-Z
Data in
V
V
HH
V
PPH
IH
NOTES: 2. X = don’t care
3. When writing commands to the ’28F400Axy, V
must be in the appropriate V
PP
voltage range (as shown in the recommended
PP
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for the combinations).
12
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byte-wide or word-wide mode selection (continued)
Table 8. Operation Modes for TMS28F004Axy
MODE
WP
E
G
RP
W
A9
A0
V
DQ0–DQ7
PP
X
Read
X
X
V
V
V
V
V
V
V
V
X
X
Data out
IL
IL
IH
IH
V
ID
V
IL
X
Manufacturer-equivalent code 89h
IL
IL
IH
IH
Device-equivalent code 78h (top boot block)
Algorithm-selection mode
X
V
V
V
V
V
V
V
V
X
IL
IL
IH
IH
ID
IH
Device-equivalent code 79h (bottom boot
block)
Output disable
Standby
X
X
X
V
IH
V
V
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IH
X
X
X
X
X
X
IH
Reset/deep power down
X
X
V
X
IL
V
V
or
V
IL
or
IH
PPL
or
Write (see Note 3)
V
IL
V
IH
V
IL
X
X
Data in
V
V
HH
V
PPH
IH
NOTES: 2. X = don’t care
3. When writing commands to the ’28F004Axy, V
must be in the appropriate V voltage range (as shown in the recommended
PP
PP
operating conditions table) for block-erase or program commands to be executed. Also, depending on the combination of RP and
WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for a list of the combinations).
command-state machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read status register, clear status
register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on
DQ0–DQ7 (see Table 3 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when V is within its correct voltage range.
PP
For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the V status (SB3), the program status bit (SB4), and the erase status bit
PP
(SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read array mode.
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read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
read array
The array level is read by entering the command code FFh on DQ0–DQ7. Control pins Eand G must be at a
logic-low level (V ) and W and RP must be at a logic-high level (V ) to read data from the array. Data is
IL
IH
available on DQ0–DQ15 (word-wide mode) or DQ0–DQ7 (byte-wide mode). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0–DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins E and G must be at a logic-low level (V ) and W and RP must be at a logic-high level
IL
(V ). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
IH
DQ0–DQ7 with A0 at a logic-low level (V ). The device-equivalent code is obtained when A0 is set to a
IL
logic-high level (V ). Alternatively, themanufacturer-anddevice-equivalentcodescanbereadbyapplying
IH
V
(nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
ID
“don’t cares” (see Table 4, Table 6, Table 7, Table 8).
read status register
The status register is read by entering the command code 70h on DQ0–DQ7. Control pins E and G must be
at a logic-low level (V ) and W and RP must be at a logic-high level (V ). Two bus cycles are required for
IL
IH
this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status register contents are updated on the falling edge of E or G, whichever occurs last within the
cycle.
programming operations
There are two CSM commands for programming: program setup and alternate program setup
(see Table 3). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM normally cannot be interrupted until the program algorithm is
completed (see Figure 3 and Figure 4).
Taking RP to V during programming aborts the program operation. During programming, V must remain in
IL
PP
the appropriate V
voltage range, as shown in the recommended operating conditions table. Different
PP
combinationsofRP, WP, andV pinvoltagelevelsensurethatdataincertainblocksaresecure, and, therefore,
PP
cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared during a
program operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.
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erase operations
There are two erase operations that can be performed by the TMS28F004Axy and TMS28F400Axy devices:
block erase and erase suspend/erase resume. An erase operation must be used to initialize all bits in an array
block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend
commands until the WSM completes its task.
block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplishedonlybyblocks;dataatsingleaddresslocationswithinthearraycannotbeerasedindividually.
The block to be erased is selected by using any valid address within that block. Note that different
combinations of RP, WP and V
pin voltage levels ensure that data in certain blocks are secure and,
PP
therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command
sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A
two-command erase sequence protects against accidental erasure of memory contents.
Erase setup and confirm commands are latched on the rising edge of E or W, whichever occurs first. Block
addresses are latched during the block-erase-confirm command on the rising edge of Eor W (see Figure 14
and Figure 15). When the block-erase-confirm command is complete, the WSM automatically executes a
sequence of events to complete the block erasure. During this sequence, the block is programmed with
logic 0s, data is verified, all bits in the block are erased, and finally, verification is performed to ensure that all
bits are correctly erased. Monitoring of the erase operation is possible through the status register (see the
subsection, “read status register”).
erase suspend/erase resume
During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data must be read from a block other than the one being erased. To resume
the erase operation, an erase-resume command (D0h) must be issued to cause the CSM to clear the
suspend state previously set (see Figure 5 and Figure 6).
automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read and the device is in the
active mode. During this time, the device switches to the automatic power-saving (APS) mode. When the device
switches to this mode, I
is typically reduced from 40 mA to 1 mA (I
= 0 mA). The low level of power is
CC
OUT
maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last
memory address read until a new address is read. This mode is entered automatically if no address or control
pins toggle within approximately a 200-ns time-out period. At least one transition on E must occur after power
up to activate this mode.
reset/deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V ± 0.2 V, a much lower I
This is important in portable applications where extended battery life is of major concern.
value or power is achievable.
CC
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a
minimum of t
is required before data is valid, and a minimum of t
and t
in deep
d(RP)
rec(RPHE)
rec(RPHW)
power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM
is reset and the status register is cleared, effectively eliminating accidental programming to the array during
system reset. After restoration of power, the device does not recognize any operation command until RP is
returned to a V or V
level.
IH
HH
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reset/deep power-down mode (continued)
If RP goes low during a program or erase operation, the device powers down and, therefore, becomes
nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the
operation be performed again after power restoration.
power-supply detection
RP must be connected to the system reset/power good signal to ensure that proper synchronization is
maintained between the CPU and the flash memory operating modes. The default state after power up and exit
from deep power-down mode is read array. RP also is used to indicate that the power supply is stable so that
the operating supply voltage can be established (3 V, 3.3 V or 5 V). Figure 10 shows the proper power-up
sequence. To reset the operating supply voltage, the device must be completely powered off (V = 0 V) before
CC
the new supply voltage is detected.
16
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SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
Start
BUS
COMMAND
COMMENTS
OPERATION
Issue Program-Setup
Command and Byte Address
Write
Write
program
setup
Data
Addr
=
=
40h or 10h
Address of
byte to be
programmed
Issue Byte
Address/Data
Write
Write data
Data
Addr
=
=
Byte to be
programmed
Address of
byte to be
Read Status-Register
Bits
programmed
Read
Status-register data.
Toggle G or E to update
status register.
No
SB7 = 1
?
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Repeat for subsequent bytes
Write FFh after the last byte-programming operation to
reset the device to read-array mode.
Full Status-Register
Check (optional)
See Note A
Byte-Program Completed
FULL STATUS-REGISTER-CHECK FLOW
Read
Status-Register Bits
BUS
OPERATION
COMMAND
COMMENTS
Check SB3
No
SB3 = 0
?
V
PP
Range Error
Standby
1 = Detect V
low
PP
(see Note B)
Yes
Check SB4
1 = Byte-program error
(see Note C)
No
Byte-Program
Failed
Standby
SB4 = 0
?
Yes
Byte-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flow Chart
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SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
BUS
OPERATION
Start
COMMAND
COMMENTS
Write
Write
program
setup
Data
Addr
=
=
40h or 10h
Address of
word to be
programmed
Issue Program-Setup
Command and Word
Address
Write
Write data
Data
Addr
=
=
Word to be
programmed
Address of
word to be
Issue Word
Address/Data
programmed
Read
Status-register data.
Toggle G or E to update
status register.
Read Status-Register
Bits
Standby
Check SB7
1 = Ready, 0 = Busy
No
SB7 = 1
?
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Yes
Full Status-Register
See Note A
Check (optional)
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
OPERATION
COMMAND
COMMENTS
No
SB3 = 0
Standby
Check SB3
Detect V
V
PP
Range Error
?
1
=
low
PP
(see Note B)
Yes
Standby
Check SB4
1
=
Word-program
error
(see Note C)
No
SB4 = 0
?
Word-Program
Failed
Yes
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flow Chart
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
BUS
OPERATION
Start
COMMAND
COMMENTS
20h
Write
Write erase Data
=
setup
Block Addr = Address
Issue Erase-Setup Command
and Block Address
within
block to
be
Issue Block-Erase-Confirm
Command and
erased
Write
Erase
Data = D0h
Block Addr = Address
Block Address
within
block to
be
Erase-
Suspend
Loop
Read Status-Register Bits
erased
No
Erase
Suspend
?
Read
Status-register data.
Toggle G or E to update
status register
No
Yes
SB7 = 1
?
Standby
Check SB7
Yes
1 = Ready, 0 = Busy
Full Status-Register
Check (optional)
See Note A
Repeat for subsequent blocks
WriteFFhafterthelastblock-eraseoperationtoresetthe
device to read-array mode.
Block-Erase Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
OPERATION
COMMAND
COMMENTS
Standby
Check SB3
1 = Detect V
No
low
SB3 = 0
PP
V
PP
Range Error
(see Note B)
?
Standby
Standby
Check SB4 and SB5
1 = Block-erase
error
Yes
SB4 = 1,
SB5 = 1
?
Yes
No
Command Sequence
Error
Check SB5
1 = Block-erase error
(see Note C)
No
SB5 = 0
?
Block-Erase Failed
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flow Chart
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
BUS
OPERATION
Start
COMMAND
COMMENTS
Data = B0h
Write
Erase
suspend
Issue Erase-Suspend
Command
Read
Status-register data.
Toggle G or E to update
status register.
Standby
Standby
Write
Check SB7
1 = Ready
Read Status-Register
Bits
Check SB6
1 = Suspended
No
Read
Data = FFh
SB7 = 1
memory
?
Read
Read data from block
other than that being
erased.
Yes
No
SB6 = 1
Write
Erase
resume
Data = D0h
?
Erase
Yes
Completed
Issue Memory-Read
Command
No
Finished
Reading
?
Yes
Issue Erase-Resume
Command
Erase Continued
See Note A
NOTE A: See block-erase flowchart for complete erasure procedure.
Figure 6. Erase-Suspend/Resume Flow Chart
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 7 V
CC
PP
Supply voltage range, V (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 14 V
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to V
+ 1 V
CC
RP, A9 (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to 13.5 V
Output voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.6 V to V + 1 V
CC
Operating free-air temperature range, T , during read/erase/program: L suffix . . . . . . . . . . . . . . 0°C to 70°C
A
E suffix . . . . . . . . . . . . – 40°C to 85°C
Q suffix . . . . . . . . . . – 40°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to V
.
SS
5. The voltage on any input or output can undershoot to – 2 V for periods less than 20 ns. See Figure 8.
6. The voltage on any input or output can overshoot to 7 V for periods less than 20 ns. See Figure 9.
I
OL
V
IH
V
V
Output
Under
Test
OH
OL
V
Z
V
IL
VOLTAGE WAVEFORMS
C
L
(see Note A)
I
OH
C includes probe and fixture capacitance.
L
NOTES: A.
B. AC test conditions are driven at V and V , Timing measurements are made at V
and V
levels on both inputs and outputs.
OL
IH
See Table 9 for values based on V
IL
OH
operating range..
CC
C. Each device must have a 0.1 F ceramic capacitor connected to V
CC
and V
SS
as close as possible to the device pins.
Figure 7. Load Circuit and Voltage Waveforms
Table 9. AC Test Conditions
†
V
RANGE
I
I
V
V
V
V
V
C
L
tf
tr
CC
5 V ± 10%
OL
OH
Z
OL
OH
IL
IH
2.1
0.5
0.1
–0.4
–0.5
–0.1
1.5
1.5
0.8
1.5
2.0
1.5
0.45
0.0
2.4
3.0
2.7
100
50
< 10
< 10
< 10
< 10
< 10
< 10
3.3 ± 0.3 V
2.7 to 3.6 V
1.35
1.35
1.35
0.0
50
†
V
Z
is the measured value used to detect high impedance.
5 ns
5 ns
+0.8 V
–0.6 V
– 2.0 V
20 ns
Figure 8. Maximum Negative Overshoot Waveform
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
20 ns
7 V
V
CC
+ 0.5 V
2.0 V
5 ns
5 ns
Figure 9. Maximum Positive Overshoot Waveform
capacitance over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
MIN
MAX
8
UNIT
pF
Ci
Input capacitance
Output capacitance
C
V
O
= 0 V
12
pF
o
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
TMS28F004ASy and TMS28F400ASy
The TMS28F004ASy and the TMS28F400ASy configurations have the auto-select feature that allows
alternative read and program/erase voltages. Memory reads can be performed using V = 3.3 V for optimal
CC
power consumption or at V
= 5 V for device performance. Erasing or programming the device can be
CC
accomplished with V
= 5 V, which eliminates having to use a 12-V source and/or in-system voltage
converters. Alternatively, the 12-V V operation exists for systems that already have a 12-V power supply that
PP
PP
provides faster programming and erasing times. This configuration is offered in two temperature ranges (0°C
to 70°C and –40°C to 85°C).
recommended operating conditions for TMS28F004ASy and TMS28F400ASy
MIN
3
NOM
3.3
5
MAX
3.6
UNIT
3.3-V V
range
range
CC
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
V
CC
PP
5-V V
4.5
0
5.5
CC
During read only (V
PPL
)
V
PPL
6.5
V
5-V V
range
range
4.5
11.4
2
5
5.5
V
V
PP
During write/erase/erase suspend
12-V V
TTL
12
12.6
PP
V
V
V
V
+ 0.5
CC
CC
CC
CC
3.3-V V
range
CC
CMOS
TTL
V
– 0.2
CC
+ 0.2
+ 0.3
+ 0.2
High-level dc input
voltage
V
IH
IL
2
5-V V
range
CC
CMOS
TTL
V
– 0.2
CC
– 0.5
0.8
+ 0.2
3.3-V V
range
CC
CMOS
TTL
V
– 0.2
V
Low-level dc input
voltage
SS
SS
V
V
– 0.3
0.8
5-V V
CC
range
CMOS
V
– 0.2
2
V
+ 0.2
SS
SS
V
V
V
V
lock-out voltage from write/erase (see Note 7)
V
V
V
LKO
CC
RP unlock voltage
lock-out voltage from write/erase
11.4
12
13
HH
V
PP
0
0
1.5
70
85
PPLK
L Suffix
E Suffix
T
A
Operating free-air temperature
°C
– 40
NOTE 7: Mimimum value at T = 25°C.
A
word/byte typical write and block-erase performance for TMS28F004ASy and TMS28F400ASy
(see Notes 8 and 9)
5-V V
RANGE
12-V V
RANGE
PP
PP
3.3-V V
5-V V
CC
3.3-V V
RANGE
5-V V
CC
CC
CC
PARAMETER
RANGE
TYP
2.4
RANGE
TYP
1.9
RANGE
TYP
1.1
MIN
MAX
MIN
MAX
MIN TYP
MAX
MIN
MAX
14
Main block-erase time
1.3
1.6
Main block-byte program time
Main block-word program time
Parameter/boot-block erase time
1.7
1.4
1.2
4.2
2.1
7
1.1
0.9
0.8
0.6
0.84
0.8
0.44
0.34
NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.
A
9. Excludes system-level overhead (all times in seconds)
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of
supply voltage and operating free-air temperature, using test conditions listed in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL
V
V
V
= V
= V
= V
MIN,I
MIN,I
MIN,I
= – 2.5 mA
= – 100 µA
= 5.8 mA
2.4
CC
CC
CC
CC
CC
CC
OH
OH
OL
V
High-level dc output voltage
V
OH
CMOS
V
– 0.4
CC
V
V
Low-level dc output voltage
A9 selection code voltage
0.45
12.6
V
V
OL
During read algorithm-selection mode
= V MAX, V = 0 V to V MAX,
11.4
ID
Input current (leakage), except for A9 when
V
CC
RP = V
CC
HH
I
CC
I
I
±1
µA
A9 = V (see Note 10)
ID
I
I
I
A9 selection code current
RP boot-block unlock current
Output current (leakage)
A9 = V
500
500
±10
15
µA
µA
µA
ID
RP
O
ID
RP = V
HH
V
= V
MAX, V = 0 V to V
MAX
3.3-V V
CC
PP
CC
O
CC
range
CC
CC
CC
I
I
I
V
standby current (standby)
V
≤ V
µA
µA
µA
PPS
PPL
PP1
PP
PP
CC
5-V V
range
10
CC
3.3-V V
5-V V
range
5
V
supply current (reset/deep
RP = V
± 0.2 V, V
≤ V
PP CC
SS
power-down mode)
range
5
CC
3.3-V V
range
200
200
V
PP
supply current (active read)
V
PP
≥ V
CC
5-V V
5-V V
range
CC
range,
range
PP
CC
30
25
25
20
30
25
25
20
30
20
25
15
3.3-V V
5-V V
5-V V
range,
range
PP
CC
V
supply current (active byte-write)
PP
I
I
I
Programming in progress
Programming in progress
Block-erase in progress
mA
mA
mA
PP2
PP3
PP4
(see Notes 11 and 12)
12-V V
range,
range
PP
3.3-V V
CC
range,
12-V V
5-V V
PP
range
CC
5-V V
3.3-V V
range,
range
PP
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (active word-write)
PP
(see Notes 11 and 12)
12-V V
range,
range
PP
3.3-V V
CC
range,
12-V V
5-V V
PP
range
CC
5-V V
3.3-V V
range,
range
PP
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (block-erase
PP
(see Notes 11 and 12)
12-V V
range,
range
PP
3.3-V V
CC
12-V V
5-V V
CC
range,
PP
range
NOTES: 10. DQ15/A is tested for output leakage only.
–1
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of
supply voltage and operating free-air temperature, (as on the previous page) using test conditions
listed in Table 9 (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
5-V V
PP
range,
range
200
3.3-V V
CC
5-V V
5-V V
range,
range
PP
CC
200
200
200
V
supply current (erase-suspend)
PP
I
Block-erase suspended
µA
PP5
(see Notes 11 and 12)
12-V V
PP
3.3-V V
range,
range
CC
12-V V
5-V V
CC
range,
PP
range
3.3-V V
CC
5-V V range
CC
range
1.5
2
mA
mA
µA
V
= V
MAX,
CC
CC
IH
TTL-input level
E = RP =V
V
supply current
CC
(standby)
I
I
CCS
3.3-V V
5-V V
range
110
130
8
V
CC
= V
MAX,
CC
CC
CC
range
CMOS-input level
E = RP= V ± 0.2 V
µA
CC
0°C to 70°C
V
supply current (reset/deep
CC
power-down mode)
µA
RP = V
± 0.2 V; V
= V
MAX
CC
CCL
SS
CC
– 40°C to 85°C
8
E = V , I
IL OUT
= 0 mA, f = 5 MHz,
= 0 mA, f = 10 MHz,
= 0 mA, f = 5 MHz,
= 0 mA, f = 10 MHz,
3.3-V V
range
30
65
30
60
CC
CC
G = V
IH
TTL-input level
mA
E = V , I
IL OUT
G = V
5-V V
range
CC
V
CC
supply
IH
I
current (active
read)
CC1
E = V , I
IL OUT
G = V
3.3-V V
range
CC
CMOS-input level
mA
mA
E = V , I
IL OUT
G = V
5-V V
5-V V
range
CC
CC
range,
range
PP
CC
30
50
25
45
30
50
25
45
3.3-V V
5-V V
5-V V
range,
range
PP
CC
V
supply current (active byte write)
CC
(see Notes 11 and 12)
V
= V MAX,
CC
CC
Programming in progress
I
CC2
12-V V
range,
range
PP
3.3-V V
CC
range,
12-V V
5-V V
PP
range
CC
5-V V
3.3-V V
CC
range,
range
PP
5-V V
5-V V
range,
range
PP
CC
V
supply current (active word-write)
V
= V MAX,
CC
CC
(see Notes 11 and 12)
CC
Programming in progress
I
CC3
mA
12-V V
range,
range
PP
3.3-V V
CC
12-V V
5-V V
CC
range,
PP
range
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of
supply voltage and operating free-air temperature, (as on the previous page) using test conditions
listed in Table 9 (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
5-V V
range,
range
PP
3.3-V V
30
CC
5-V V
5-V V
range,
range
PP
CC
35
25
30
V
supply current (block-erase)
V
= V MAX,
CC
CC
CC
Block-erase in progress
I
mA
CC4
(see Notes 11 and 12)
12-V V
PP
3.3-V V
range,
range
CC
range,
12-V V
PP
range
5-V V
CC
3.3-V V
range
range
8
V
supply current (erase suspend)
V
= V
MAX, E = V ,
CC IH
CC
CC
(see Notes 11 and 12)
CC
Block erase suspended
I
mA
CC5
5-V V
CC
10
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
power-up and reset switching characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of supply
voltage (commercial and extended temperature ranges)(see Notes 11, 12, and 13)
’28F004ASy60
’28F400ASy60
’28F004ASy70
’28F400ASy70
’28F004ASy80
’28F400ASy80
ALT.
SYMBOL
PARAMETER
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, RP low to V
at
CC
t
t
PL5V
PL3V
t
4.5 V MIN (to V
CC
at 3 V MIN or
0
0
0
0
0
0
ns
su(VCC)
3.6 V MAX) (see Note 14)
Address valid to data valid
Setup time, RP high to data valid
t
t
t
110
800
60
130
800
70
150
800
80
ns
ns
a(DV)
AVQV
t
450
450
450
su(DV)
PHQV
Hold time, V
high
at 4.5 V (MIN) to RP
CC
t
t
2
2
2
2
2
2
2
2
2
2
2
2
µs
µs
h(RP5)
h(RP3)
5VPH
t
Hold time, V
at 3 V (MIN) to RP high
t
CC
3VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
switching characteristics for TMS28F004ASy and TMS28F400ASy over recommended ranges of supply voltage
(commercial and extended temperature ranges)
read operations
’28F004ASy60
’28F400ASy60
’28F004ASy70
’28F400ASy70
’28F004ASy80
’28F400ASy80
ALT.
SYMBOL
PARAMETER
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time from A0–A17
(see Note 15)
t
t
110
60
130
70
150
80
ns
a(A)
AVQV
t
t
t
Access time from E
Access time from G
Cycle time, read
t
110
65
60
35
130
80
70
40
150
90
80
40
ns
ns
ns
a(E)
a(G)
c(R)
ELQV
t
t
GLQV
t
110
0
60
0
130
0
70
0
150
0
80
0
AVAV
Delay time, E low to low-impedance
output
t
t
t
t
ns
ns
ns
ns
d(E)
ELQX
Delay time, G low to low-impedance
output
t
t
0
0
0
0
0
0
d(G)
GLQX
EHQZ
GHQZ
Disable time, E to high-impedance
output
55
45
25
25
70
55
30
30
80
60
30
30
dis(E)
dis(G)
Disable time, G to high-impedance
output
t
Hold time, DQ valid from A0–A17, E, or
G, whichever occurs first
(see Note 15)
t
t
0
0
0
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
800
45
5
450
25
5
800
55
5
450
30
5
800
60
5
450
30
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8–DQ15
in high-impedance state
t
FLQZ
FHQV
Access time from BYTE going high
t
110
60
130
70
150
80
NOTE 15: A –A17 for byte-wide
–1
timing requirements for TMS28F004ASy and TMS28F400ASy
write/erase operations — W-controlled writes
’28F004ASy60
’28F004ASy70
’28F400ASy70
’28F004ASy80
’28F400ASy80
’28F400ASy60
ALT.
3.3-V V
CC
RANGE
5-V V
CC
RANGE
3.3-V V
CC
RANGE
5-V V
3.3-V V
CC
RANGE
5-V V
UNIT
CC
CC
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
110
60
6
130
70
150
80
ns
c(W)
AVAV
Cycle time, duration of
programming operation
t
t
t
t
6
6
0.3
0.3
0.6
6
6
0.3
0.3
0.6
6
µs
c(W)OP
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation
(boot block)
t
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
c(W)ERB
c(W)ERP
Cycle time, erase operation
(parameter block)
t
Cycle time, erase operation
(main block)
t
t
t
s
c(W)ERM
d(RPR)
h(A)
Delay time, boot-block relock
t
200
100
200
100
200
100
ns
ns
PHBR
Hold time, A0–A17
(see Note 15)
t
0
0
0
0
0
0
WHAX
t
t
Hold time, DQ valid
Hold time, E
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
h(D)
WHDX
h(E)
WHEH
Hold time, V
PP
from valid
status register bit
t
t
t
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
h(VPP)
QVVL
QVPH
WHPL
Hold time, RP at V
valid status register bit
from
HH
t
h(RP)
Hold time, WP from valid status
register bit
t
0
0
0
0
0
0
h(WP)
su(WP)
Setup time, WP before write
operation
t
90
50
105
50
120
50
ELPH
Setup time, A0–A17
(see Note 15)
t
t
t
t
90
90
0
50
50
0
105
105
0
50
50
0
120
120
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(E)
AVWH
Setup time, DQ
t
DVWH
Setup time, E before write
operation
t
ELWL
NOTE 15: A –A17 for byte-wide
–1
timing requirements for TMS28F004ASy and TMS28F400ASy (continued)
write/erase operations — W-controlled writes
’28F004ASy60
’28F400ASy60
’28F004ASy70
’28F400ASy70
’28F004ASy80
’28F400ASy80
ALT.
SYMBOL
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V 5-V V
3.3-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
RANGE
CC
CC
RANGE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, RP at V
going high
to W
HH
t
t
t
200
100
100
200
100
100
200
100
100
ns
ns
su(RP)
PHHWH
Setup time, V
high
to W going
PP
t
200
200
200
su(VPP)1
VPWH
t
t
Pulse duration, W low
Pulse duration, W high
t
90
20
50
10
105
25
50
20
120
30
50
30
ns
ns
w(W)
WLWH
t
w(WH)
WHWL
Recovery time, RP high to W
going low
t
t
800
450
800
450
800
450
ns
rec(RPHW)
PHWL
timing requirements for TMS28F004ASy and TMS28F400ASy
write/erase operations — E-controlled writes
’28F004ASy60
’28F004ASy70
’28F400ASy70
’28F004ASy80
’28F400ASy80
’28F400ASy60
ALT.
3.3-V V
CC
RANGE
5-V V
CC
RANGE
3.3-V V
CC
RANGE
5-V V
3.3-V V
CC
RANGE
5-V V
UNIT
CC
CC
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
110
60
6
130
70
150
80
ns
c(E)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
6
0.3
0.3
0.6
6
6
0.3
0.3
0.6
6
µs
c(E)OP
EHQV1
EHQV2
EHQV3
EHQV4
Cycle time, erase operation (boot
block)
t
t
t
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
s
c(E)ERB
c(E)ERP
c(E)ERM
Cycle time, erase operation
(parameter block)
Cycle time, erase operation (main
block)
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
200
100
200
100
200
100
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
EHAX
EHDX
t
h(D)
Hold time, W
t
EHWH
h(W)
Hold time, V
status-register bit
from valid
PP
t
t
t
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
status-register bit
from valid
HH
t
Hold time, WP from valid status
register bit
t
0
0
0
0
0
0
h(WP)
su(WP)
Setup time, WP before write
operation
t
90
50
105
50
120
50
ELPH
t
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
90
90
0
50
50
0
105
105
0
50
50
0
120
120
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(W)
AVEH
t
DVEH
t
Setup time, W before write operation
WLEL
NOTE 15: A –A17 for byte-wide
–1
timing requirements for TMS28F004ASy and TMS28F400ASy (continued)
write/erase operations — E-controlled writes
’28F004ASy60
’28F004ASy70
’28F400ASy70
’28F004ASy80
’28F400ASy80
’28F400ASy60
ALT.
3.3-V V
CC
RANGE
5-V V
CC
RANGE
3.3-V V
CC
RANGE
5-V V
3.3-V V
CC
RANGE
5-V V
UNIT
CC
CC
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, RP at V
high
to E going
HH
t
t
200
100
200
100
200
100
ns
su(RP)
PHHEH
t
t
t
Setup time, V
PP
to E going high
t
200
90
100
50
200
105
25
100
50
200
120
30
100
50
ns
ns
ns
su(VPP)2
VPEH
Pulse duration, E low
Pulse duration, E high
t
w(E)
ELEH
EHEL
t
20
10
20
30
w(EH)
Recovery time, RP high to E going
low
t
t
800
450
800
450
800
450
ns
rec(RPHE)
PHEL
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
TMS28F004AEy and TMS28F400AEy
The TMS28F004AEy and the TMS28F400AEy configurations offer the auto-select feature of the
TMS28F400ASy with an extended V from a low 2.7-V to 3.6-V range (3-V nominal). Memory reads can be
CC
performed using a V
= 3 V, allowing for more efficient power consumption than the ’ASy device.
CC
recommended operating conditions for TMS28F004AEy and TMS28F400AEy
MIN
2.7
4.5
0
NOM
MAX
3.6
UNIT
3-V V
5-V V
range
range
3
5
CC
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
V
CC
PP
5.5
CC
During read only (V
PPL
)
V
PPL
6.5
V
5-V V
range
4.5
11.4
2
5
5.5
V
V
PP
During write/erase/erase suspend
12-V V
TTL
range
12
12.6
PP
V
V
V
V
+ 0.5
CC
CC
CC
CC
3-V V
5-V V
3-V V
5-V V
range
range
range
range
CC
CC
CC
CC
CMOS
TTL
V
– 0.2
CC
+ 0.2
+ 0.3
+ 0.2
High-level dc input
voltage
V
IH
IL
2
CMOS
TTL
V
– 0.2
CC
– 0.5
0.8
+ 0.2
CMOS
TTL
V
– 0.2
V
Low-level dc input
voltage
SS
SS
V
V
– 0.3
0.8
CMOS
V
– 0.2
2
V
+ 0.2
SS
SS
V
V
V
V
lock-out voltage from write/erase (see Note 7)
V
V
V
LKO
CC
RP unlock voltage
lock-out voltage from write/erase
11.4
12
13
HH
V
PP
0
0
1.5
70
85
PPLK
L Suffix
E Suffix
T
A
Operating free-air temperature
°C
– 40
NOTE 7: Mimimum value at T = 25°C.
A
word/byte typical write and block-erase performance for TMS28F004AEy and TMS28F400AEy
(see Notes 8 and 9)
5-V V
RANGE
5-V V
MIN
12-V V
RANGE
5-V V
MIN
PP
PP
PARAMETER
3-V V
MIN
RANGE
RANGE
3-V V
CC
RANGE
RANGE
CC
CC
TYP
CC
TYP
TYP
MAX
MAX
MIN TYP
MAX
MAX
Main block-erase time
2.4
1.7
1.1
1.9
1.4
0.9
0.8
1.3
1.6
1.1
1.2
0.6
14
4.2
2.1
7
Main block-byte program time
Main block-word program time
Parameter/boot-block erase time
0.8
0.84
0.44
0.34
NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.
A
9. Excludes system-level overhead (all times in seconds)
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage and operating free-air temperature using test conditions listed in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL
V
V
V
= V
= V
= V
MIN,I
MIN,I
MIN,I
= – 2.5 mA
= – 100 µA
= 5.8 mA
2.4
CC
CC
CC
CC
CC
CC
OH
OH
OL
V
High-level dc output voltage
V
OH
CMOS
V
– 0.4
CC
V
V
Low-level dc output voltage
A9 selection code voltage
0.45
12.6
V
V
OL
During read algorithm-selection mode
11.4
ID
Input current (leakage), except for A9 when
A9 = V (see Note 10)
ID
I
I
V
CC
= V
MAX,V = 0 V to V
CC
MAX, RP = V
HH
±1
µA
CC
I
I
I
I
A9 selection code current
RP boot-block unlock current
Output current (leakage)
A9 = V
500
500
±10
15
µA
µA
µA
ID
RP
O
ID
RP = V
HH
V
= V
MAX,V = 0 V to V
MAX
3-V V
CC
PP
CC
O
CC
range
CC
CC
CC
CC
CC
CC
I
I
I
V
standby current (standby)
V
≤ V
µA
µA
µA
PPS
PPL
PP1
PP
PP
CC
5-V V
3-V V
5-V V
3-V V
5-V V
range
range
range
range
range
10
5
V
supply current (reset/deep
RP = V
± 0.2 V, V
≤ V
PP CC
SS
power-down mode)
5
200
200
V
PP
supply current (active read)
V
PP
≥ V
CC
5-V V
3-V V
range,
range
PP
CC
30
25
25
20
30
25
25
20
5-V V
5-V V
range,
range
PP
CC
V
supply current (active byte-write)
PP
I
PP2
Programming in progress
mA
(see Notes 11 and 12)
12-V V
3-V V
CC
range,
PP
range
12-V V
range,
range
PP
5-V V
CC
5-V V
3-V V
range,
range
PP
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (active word-write)
PP
(see Notes 11 and 12)
I
PP3
Programming in progress
mA
12-V V
3-V V
CC
range,
PP
range
12-V V
5-V V
CC
range,
PP
range
NOTES: 10. DQ15/A is tested for output leakage only.
–1
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
5-V V
3-V V
range,
range
PP
CC
30
mA
5-V V
5-V V
range,
range
PP
CC
20
25
V
supply current (block-erase)
PP
I
PP4
Block-erase in progress
(see Notes 11 and 12)
12-V V
3-V V
CC
range,
PP
range
mA
µA
µA
12-V V
range,
range
PP
15
5-V V
CC
5-V V
3-V V
range,
range
PP
CC
200
200
200
200
5-V V
5-V V
range,
range
PP
CC
V
supply current (erase-suspend)
PP
(see Notes 11 and 12)
I
PP5
Block-erase suspended
12-V V
3-V V
CC
range,
PP
range
12-V V
range,
PP
5-V V
3-V V
5-V V
3-V V
5-V V
range
range
range
range
range
CC
CC
CC
CC
CC
1.5
2
V
= V
MAX
CC
CC
IH
TTL-input level
mA
µA
µA
E = RP =V
V
supply current
CC
(standby)
I
I
CCS
110
130
8
V
= V
MAX,
CC
CC
E = RP = WP = V
CMOS-input level
± 0.2 V
CC
0°C to 70°C
V
supply current (reset/deep
CC
power-down mode)
RP = V
± 0.2 V; V
= V
MAX
CC
CCL
SS
CC
– 40°C to 85°C
8
E = V , I
= 0 mA, f = 5 MHz,
= 0 mA, f = 10 MHz,
= 0 mA, f = 5 MHz,
= 0 mA, f = 10 MHz,
3.3-V V
range
30
65
30
60
CC
CC
G = V
IH
TTL-input level
mA
mA
E = V , I
IL OUT
G = V
5-V V
range
CC
V
CC
supply
IH
I
CC1
current (active
read)
E = V , I
IL OUT
G = V
3.3-V V
range
CC
CMOS-input level
E = V , I
IL OUT
G = V
5-V V
range
CC
CC
5-V V
3-V V
range,
range
PP
CC
30
50
25
45
5-V V
5-V V
range,
range
PP
CC
V
supply current (active byte-write)
V
= V MAX,
CC
CC
(see Notes 11 and 12)
CC
Programming in progress
I
CC2
mA
12-V V
3-V V
CC
range,
PP
range
12-V V
5-V V
CC
range,
PP
range
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
5-V V
3-V V
range,
range
PP
CC
30
5-V V
3-V V
range,
range
PP
CC
50
25
45
30
35
25
30
V
supply current (active word-write)
V
= V MAX,
CC
CC
CC
Programming in progress
I
mA
CC3
(see Notes 11 and 12)
12-V V
3-V V
CC
range,
PP
range
12-V V
range,
range
PP
5-V V
CC
5-V V
3-V V
range,
range
PP
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (block-erase)
V
= V MAX,
CC
CC
(see Notes 11 and 12)
CC
Block-erase in progress
I
I
mA
mA
CC4
12-V V
3-V V
CC
range,
PP
range
12-V V
range,
range
PP
5-V V
CC
3-V V
range
CC
V
supply current (erase-suspend)
V
CC
= V
MAX, E = V ,
IH
CC
CC
3.3-V V
range
CC
range
8
CC5
Block-erase suspended
5-V V
CC
10
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
power-up and reset switching characteristics for TMS28F004AEy and TMS28F400AEy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 11, 12, and 13)
’28F004AEy60
’28F400AEy60
ALT.
PARAMETER
3-V V
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
MIN MAX
MIN MAX
Setup time, RP low to V
2.7 V MIN or 3.6 V MAX) (see Note 14)
at 4.5 V MIN (to V
at
t
t
CC
CC
PL5V
PL3V
t
0
0
ns
su(VCC)
t
t
t
t
Address valid to data valid
t
110
800
60
ns
ns
µs
µs
a(DV)
AVQV
Setup time, RP high to data valid
t
450
su(DV)
h(RP5)
h(RP3)
PHQV
Hold time, V
at 4.5 V (MIN) to RP high
at 2.7 V (MIN) to RP high
t
2
2
2
2
CC
CC
5VPH
Hold time, V
t
3VPH
’28F004AEy70
’28F400AEy70
’28F004AEy80
’28F400AEy80
ALT.
SYMBOL
PARAMETER
3-V V
5-V V
3-V V
CC
5-V V
CC
RANGE
UNIT
CC
CC
RANGE
RANGE
RANGE
MIN
MAX
MIN
MAX
MIN MAX
MIN MAX
Setup time, RP low to V
at 4.5 V
CC
t
MIN (to V
at
PL5V
CC
t
0
0
0
0
ns
su(VCC)
t
2.7 V MIN or 3.6 V MAX)
(see Note 14)
PL3V
t
t
Address valid to data valid
t
150
800
70
150
800
80
ns
ns
a(DV)
AVQV
Setup time, RP high to data valid
t
450
450
su(DV)
PHQV
Hold time, V
high
at 4.5 V (MIN) to RP
CC
t
t
2
2
2
2
2
2
2
2
µs
µs
h(RP5)
h(RP3)
5VPH
Hold time, V
high
at 2.7 V (MIN) to RP
CC
t
t
3VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
switching characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
’28F004AEy60
’28F400AEy60
’28F004AEy70
’28F400AEy70
ALT.
SYMBOL
PARAMETER
3-V V
RANGE
5-V V
RANGE
3-V V
RANGE
5-V V
RANGE
UNIT
CC
CC
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time from A0–A17
(see Note 15)
t
t
110
60
130
70
ns
a(A)
AVQV
t
t
t
Access time from E
Access time from G
Cycle time, read
t
110
65
60
35
130
80
70
40
ns
ns
ns
a(E)
a(G)
c(R)
ELQV
t
t
GLQV
t
110
0
60
0
130
0
70
0
AVAV
Delay time, E low to low-impedance
output
t
t
t
t
ns
ns
ns
ns
d(E)
ELQX
Delay time, G low to low-impedance
output
t
t
0
0
0
0
d(G)
GLQX
EHQZ
GHQZ
Disable time, E to high-impedance
output
55
45
25
25
70
55
30
30
dis(E)
dis(G)
Disable time, G to high-impedance
output
t
Hold time, DQ valid from A0–A17, E,
or G, whichever occurs first
(see Note 15)
t
t
0
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
5
5
5
ns
ns
su(EB)
t
800
450
800
450
d(RP)
PHQV
Disable time, BYTE low to
DQ8–DQ15 in the high-impedance
state
t
t
45
25
60
55
30
70
ns
ns
dis(BL)
a(BH)
FLQZ
FHQV
t
Access time from BYTE going high
t
110
130
NOTE 15: A –A17 for byte-wide
–1
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
switching characteristics for TMS28F004AEy and TMS28F400AEy over recommended ranges of
supply voltage (commercial and extended temperature ranges) (continued)
’28F004AEy80
’28F400AEy80
ALT.
PARAMETER
3-V V
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
Access time from A0–A17 (see Note 15)
Access time from E
t
150
150
90
80
80
40
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
a(E)
ELQV
Access time from G
t
t
a(G)
c(R)
GLQV
Cycle time, read
t
150
0
80
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, E low to low-impedance output
Delay time, G low to low-impedance output
Disable time, E to high-impedance output
Disable time, G to high-impedance output
d(E)
t
t
0
0
d(G)
dis(E)
dis(G)
80
60
30
30
t
Hold time, DQ valid from A0–A17, E, or G, whichever occurs first
(see Note 15)
t
t
t
0
0
ns
ns
h(D)
AXQX
t
t
ELFL
ELFH
Setup time, BYTE from E low
5
5
su(EB)
t
t
t
Output delay time from RP high
t
t
800
60
450
30
ns
ns
ns
d(RP)
dis(BL)
a(BH)
PHQV
Disable time, BYTE low to DQ8–DQ15 in the high-impedance state
Access time from BYTE going high
t
FLQZ
150
80
FHQV
NOTE 15: A –A17 for byte-wide
–1
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy
write/erase operations — W-controlled writes
’28F004AEy60
’28F400AEy60
ALT.
SYMBOL
3-V V
RANGE
5-V V
RANGE
UNIT
CC
CC
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
110
6
60
6
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
t
t
t
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
d(RPR)
h(A)
WHQV1
WHQV2
WHQV3
WHQV4
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHBR
t
0
0
0
0
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
0
0
h(E)
Hold time, V
from valid status register bit
Hold time, RP at V from valid status register bit
t
0
0
h(VPP)
h(RP)
PP
QVVL
QVPH
WHPL
t
0
0
HH
Hold time, WP from valid status register bit
Setup time, WP before write operation
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
0
0
h(WP)
t
90
90
90
0
50
50
50
0
su(WP)
su(A)
ELPH
AVWH
DVWH
t
t
su(D)
Setup time, E before write operation
t
ELWL
su(E)
Setup time, RP at V
to W going high
t
PHHWH
200
200
90
20
800
100
100
50
10
450
su(RP)
su(VPP)1
w(W)
HH
to W going high
Setup time, V
t
PP
VPWH
WLWH
WHWL
Pulse duration, W low
t
Pulse duration, W high
t
w(WH)
rec(RPHW)
Recovery time, RP high to W going low
t
PHWL
NOTE 15: A –A17 for byte-wide
–1
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy (continued)
write/erase operations — W-controlled writes
’28F004AEy70
’28F400AEy70
’28F004AEy80
’28F400AEy80
ALT.
SYMBOL
3.0-V V
CC
RANGE
5-V V
RANGE
3.0-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
130
70
150
80
ns
c(W)
AVAV
Cycle time, duration of
programming operation
t
t
t
t
6
0.3
0.3
0.6
6
6
0.3
0.3
0.6
6
µs
c(W)OP
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation (boot
block)
t
t
t
0.3
0.3
0.6
0.3
0.3
0.6
s
s
s
c(W)ERB
c(W)ERP
c(W)ERM
Cycle time, erase operation
(parameter block)
Cycle time, erase operation
(main block)
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
200
100
200
100
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
h(E)
Hold time, V
register bit
from valid status
PP
t
t
t
t
t
0
0
0
0
0
0
0
0
ns
ns
ns
ns
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
status register bit
from valid
HH
t
Hold time, WP from valid status
register bit
t
0
0
0
0
h(WP)
su(WP)
Setup time, WP before write
operation
t
105
50
120
50
ELPH
Setup time, A0–A17
(see Note 15)
t
t
t
t
105
105
0
50
50
0
120
120
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(E)
AVWH
Setup time, DQ
t
DVWH
Setup time, E before write
operation
t
ELWL
Setup time, RP at V
going high
to W
HH
t
t
200
100
200
100
ns
su(RP)
PHHWH
t
t
t
Setup time, V
PP
to W going high
t
200
105
25
100
50
200
120
30
100
50
ns
ns
ns
su(VPP)1
VPWH
t
WLWH
Pulse duration, W low
Pulse duration, W high
w(W)
t
20
30
w(WH)
WLWL
Recovery time, RP high to W
going low
t
t
800
450
800
450
ns
rec(RPHW)
PHWL
NOTE 15: A –A17 for byte-wide
–1
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy
write/erase operations — E-controlled writes
’28F004AEy60
’28F400AEy60
ALT.
SYMBOL
3-V V
RANGE
5-V V
RANGE
UNIT
CC
CC
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
110
6
60
6
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
t
t
t
c(E)OP
c(E)ERB
c(E)ERP
c(E)ERM
d(RPR)
h(A)
EHQV1
EHQV2
EHQV3
EHQV4
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
200
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHBR
t
0
0
0
0
EHAX
EHDX
t
h(D)
Hold time, W
t
0
0
h(W)
EHWH
Hold time, V
from valid status-register bit
Hold time, RP at V from valid status-register bit
t
0
0
h(VPP)
h(RP)
PP
QVVL
QVPH
WHPL
t
0
0
HH
Hold time, WP from valid status register bit
Setup time, WP before write operation
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
0
0
h(WP)
su(WP)
su(A)
t
90
90
90
0
50
50
50
0
ELPH
AVEH
DVEH
t
t
su(D)
Setup time, W before write operation
t
WLEL
su(W)
su(RP)
su(VPP)2
w(E)
Setup time, RP at V
to E going high
t
200
200
90
20
800
100
100
50
10
450
HH
to E going high
PHHEH
Setup time, V
t
VPEH
PP
Pulse duration, E low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, E high
w(EH)
rec(RPHE)
Recovery time, RP high to E going low
NOTE 15: A –A17 for byte-wide
–1
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F004AEy and TMS28F400AEy (continued)
write/erase operations — E-controlled writes
’28F004AEy70
’28F400AEy70
’28F004AEy80
’28F400AEy80
ALT.
SYMBOL
3-V V
RANGE
5-V V
RANGE
3-V V
RANGE
5-V V
RANGE
UNIT
CC
CC
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
130
70
150
80
ns
c(E)
AVAV
Cycle time, duration of
programming operation
t
t
t
t
6
6
6
6
µs
c(E)OP
EHQV1
Cycle time, erase operation (boot
block)
t
t
t
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
s
c(E)ERB
c(E)ERP
c(E)ERM
EHQV2
EHQV3
EHQV4
Cycle time, erase operation
(parameter block)
Cycle time, erase operation (main
block)
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
200
100
200
100
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
EHAX
EHDX
t
h(D)
Hold time, W
t
EHWH
h(W)
Hold time, V
status-register bit
from valid
PP
t
t
t
t
t
0
0
0
0
0
0
0
0
ns
ns
ns
ns
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
status-register bit
from valid
HH
t
Hold time, WP from valid status
register bit
t
0
0
0
0
h(WP)
su(WP)
Setup time, WP before write
operation
t
105
50
120
50
ELPH
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
105
105
50
50
120
120
50
50
ns
ns
su(A)
AVEH
t
su(D)
DVEH
Setup time, W before write
operation
t
t
t
0
0
0
0
ns
ns
su(W)
WLEL
Setup time, RP at V
high
to E going
HH
t
200
100
200
100
su(RP)
PHHEH
t
t
t
Setup time, V
PP
to E going high
t
200
105
25
100
50
200
120
30
100
50
ns
ns
ns
su(VPP)2
VPEH
Pulse duration, E low
Pulse duration, E high
t
w(E)
ELEH
EHEL
t
20
30
w(EH)
Recovery time, RP high to E going
low
t
t
800
450
800
450
ns
rec(RPHE)
PHEL
NOTE 15: A –A17 for byte-wide
–1
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
TMS28F004AMy and TMS28F400AMy
The TMS28F004AMy and the TMS28F400AMy configurations offer a 3-V or 5-V memory read with a 12-V
program and erase. This configuration is intended for low 3.3-V reads and the fast programming offered with
the 12-V V = 12 V and 5-V V . This configuration is offered in two different temperature ranges: 0°C to 70°C
PP
CC
and – 40°C to 85°C.
recommended operating conditions for TMS28F004AMy and TMS28F400AMy
MIN
3
NOM
MAX
3.6
UNIT
3.3-V V
range
3.3
5
CC
range
V
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
V
CC
5-V V
CC
4.5
0
5.5
During read only (V
PPL
)
V
PPL
6.5
V
V
PP
During write/erase/erase suspend
12-V V
TTL
range
11.4
2
12
12.6
PP
V
V
V
V
+ 0.5
CC
CC
CC
CC
3.3 V V
range
CC
CMOS
TTL
V
– 0.2
CC
+ 0.2
+ 0.3
+ 0.2
High-level dc
input voltage
V
IH
IL
2
5 V V
range
CC
CMOS
TTL
V
– 0.2
CC
– 0.5
0.8
+ 0.2
3.3 V V
range
CC
CMOS
TTL
V
– 0.2
V
Low-level dc input
voltage
SS
SS
V
V
– 0.3
0.8
5 V V
range
CC
CMOS
V
– 0.2
2
V
+ 0.2
SS
SS
V
V
V
V
lock-out voltage from write/erase (see Note 7)
V
V
V
LKO
CC
RP unlock voltage
lock-out voltage from write/erase
11.4
12
13
HH
V
PP
0
0
1.5
PPLK
L Suffix
E Suffix
70
85
T
A
Operating free-air temperature
°C
– 40
NOTE 7: Mimimum value at T = 25°C.
A
word/byte typical write and block-erase performance for TMS28F004AMy and TMS28F400AMy
(see Notes 8 and 9)
12-V V
PP
RANGE
5-V V
MIN
3.3-V V
CC
RANGE
PARAMETER
CC
RANGE
TYP
1.3
MIN
MAX
TYP
MAX
Main block-erase time
1.1
1.2
0.6
14
4.2
2.1
7
Main block-byte program time
Main block-word program time
Parameter/boot-block erase time
1.6
0.8
0.44
0.34
NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.
A
9. Excludes system-level overhead (all times in seconds)
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL
V
V
V
= V
= V
= V
MIN,I
MIN,I
MIN,I
= – 2.5 mA
= – 100 µA
= 5.8 mA
2.4
CC
CC
CC
CC
CC
CC
OH
OH
OL
V
High-level dc output voltage
V
OH
CMOS
V
– 0.4
CC
V
V
Low-level dc output voltage
A9 selection code voltage
0.45
12.6
V
V
OL
During read algorithm-selection mode
11.4
ID
Input current (leakage), except for A9
when A9 = V (see Note 10)
ID
I
I
V
CC
= V
MAX, V = 0 V to V MAX, RP = V
CC
±1
µA
CC
I
HH
I
I
I
A9 selection code current
RP boot-block unlock current
Output current (leakage)
A9 = V
500
500
±10
15
µA
µA
µA
ID
RP
O
ID
RP = V
HH
V
= V MAX,V = 0 V to V MAX
CC
PP
CC
O
CC
3.3-V V
range
CC
CC
CC
I
I
I
V
standby current (standby)
V
≤ V
µA
µA
µA
PPS
PPL
PP1
PP
PP
CC
5-V V
range
10
CC
3.3-V V
5-V V
range
5
V
supply current (reset/deep
RP = V
± 0.2 V, V
≤ V
PP CC
SS
power-down mode)
range
5
CC
3.3-V V
range
200
200
V
PP
supply current (active read)
V
PP
≥ V
CC
5-V V
range
CC
12-V V
range,
range
PP
3.3-V V
25
20
CC
V
supply current (active byte-write)
PP
I
I
I
I
Programming in progress
Programming in progress
Block-erase in progress
Block-erase suspended
mA
mA
mA
µA
PP2
PP3
PP4
PP5
(see Notes 11 and 12)
12-V V
5-V V
CC
range,
PP
range
12-V V
range,
range
PP
3.3-V V
25
CC
V
supply current (active word-write)
PP
(see Notes 11 and 12)
12-V V
5-V V
CC
range,
PP
range
20
12-V V
range,
range
PP
3.3-V V
25
CC
V
supply current (block-erase)
PP
(see Notes 11 and 12)
12-V V
5-V V
CC
range,
PP
range
15
12-V V
range,
range
PP
3.3-V V
200
200
CC
V
supply current (erase-suspend)
PP
(see Notes 11 and 12)
12-V V
5-V V
CC
range,
PP
range
TTL-
input
level
3.3-V V
5-V V
range
1.5
2
mA
mA
µA
CC
V
= V
MAX,
CC
CC
IH
E = RP =V
range
CC
I
I
V
V
supply current (standby)
CCS
CC
CMOS-
input
level
3.3-V V
5-V V
range
110
130
CC
V
CC
= V
MAX,
C C
CC
E = RP = V ± 0.2 V
range
µA
CC
0°C to 70°C
8
8
supply current (reset/deep
RP = V
MAX
± 0.2 V; V
= V
CC
µA
CCL
power-down mode)
– 40°C to 85°C
NOTES: 10. DQ15/A is tested for output leakage only.
–1
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
= 0 mA, f = 5 MHz,
MIN
MAX
UNIT
E = V , I
IL OUT
3.3-V V
range
30
CC
G = V
IH
TTL-input level
mA
E = V , I
= 0 mA, f = 10 MHz,
= 0 mA, f = 5 MHz,
= 0 mA, f = 10 MHz,
IL OUT
G = V
5-V V
range
65
30
60
CC
V
supply
CC
IH
I
current (active
read)
CC1
E = V , I
G = V
3.3-V V
range
CC
CC
CMOS-input level
mA
E = V , I
IL OUT
G = V
5-V V
range
CC
CC
12-V V
range,
PP
3.3-V V
25
45
25
45
25
30
range
CC
V
supply current (active byte-write)
V
= V MAX,
CC
CC
(see Notes 11 and 12)
CC
Programming in progress
I
I
mA
mA
CC2
12-V V
5-V V
CC
range,
PP
range
12-V V
PP
3.3-V V
range,
range
CC
V
supply current (active word-write)
V
= V MAX,
CC
CC
(see Notes 11 and 12)
CC
Programming in progress
CC3
12-V V
5-V V
CC
range,
PP
range
12-V V
PP
3.3-V V
range,
range
CC
V
supply current (block-erase)
V
= V MAX,
CC
CC
(see Notes 11 and 12)
CC
Block-erase in progress
I
I
mA
mA
CC4
12-V V
5-V V
CC
range,
PP
range
3.3-V V
range
8
V
supply current (erase-suspend)
V
= V
MAX, E = V ,
CC
range
CC
(see Notes 11 and 12)
CC5
Block-erase suspended
5-V V
CC
10
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
power-up and reset switching characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of supply
voltage (commercial and extended temperature ranges)(see Notes 11, 12, and 13)
’28F004AMy60
’28F400AMy60
’28F004AMy70
’28F400AMy70
’28F004AMy80
’28F400AMy80
ALT.
SYMBOL
PARAMETER
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, RP low to V
at
CC
t
t
PL5V
PL3V
t
4.5 V MIN (to V
CC
at 3 V MIN or
0
0
0
0
0
0
ns
su(VCC)
3.6 V MAX) (see Note 14)
Address valid to data valid
Setup time, RP high to data valid
t
t
t
110
800
60
130
800
70
150
800
80
ns
ns
a(DV)
AVQV
t
450
450
450
su(DV)
PHQV
Hold time, V
high
at 4.5 V (MIN) to RP
CC
t
t
2
2
2
2
2
2
2
2
2
2
2
2
µs
µs
h(RP5)
h(RP3)
5VPH
t
Hold time, V
at 3 V (MIN) to RP high
t
CC
3VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13 E and G are switched low after power up.
14 The power supply can switch low concurrently with RP going low.
switching characteristics for TMS28F004AMy and TMS28F400AMy over recommended ranges of supply voltage
(commercial and extended temperature ranges)
read operations
’28F004AMy60
’28F400AMy60
’28F004AMy70
’28F400AMy70
28F004AMy80
’28F400AMy80
ALT.
SYMBOL
PARAMETER
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
CC
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time from A0–A17
(see Note 15)
t
t
110
60
130
70
150
80
ns
a(A)
AVQV
t
t
t
Access time from E
Access time from G
Cycle time, read
t
110
65
60
35
130
80
70
40
150
90
80
40
ns
ns
ns
a(E)
a(G)
c(R)
ELQV
t
t
GLQV
t
110
0
60
0
130
0
70
0
150
0
80
0
AVAV
Delay time, E low to low-impedance
output
t
t
t
t
ns
ns
ns
ns
d(E)
ELQX
Delay time, G low to low-impedance
output
t
t
0
0
0
0
0
0
d(G)
GLQX
EHQZ
GHQZ
Disable time, E to high-impedance
output
55
45
25
25
70
55
30
30
80
60
30
30
dis(E)
dis(G)
Disable time, G to high-impedance
output
t
Hold time, DQ valid from A0–A17, E, or
G, whichever occurs first
(see Note 15)
t
t
0
0
0
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
800
45
5
450
25
5
800
55
5
450
30
5
800
60
5
450
30
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8–DQ15
in high-impedance state
t
FLQZ
FHQV
Access time from BYTE going high
t
110
60
130
70
150
80
NOTE 15: A –A17 for byte-wide
–1
timing requirements for TMS28F004AMy and TMS28F400AMy
write/erase operations — W-controlled writes
’28F004AMy60
’28F004AMy70
’28F400AMy70
28F004AMy80
’28F400AMy80
’28F400AMy60
ALT.
3.3-V V
CC
RANGE
5-V V
CC
RANGE
3.3-V V
CC
RANGE
5-V V
3.3-V V
CC
RANGE
5-V V
UNIT
CC
CC
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
110
60
6
130
70
150
80
ns
c(W)
AVAV
Cycle time, duration of
programming operation
t
t
t
t
6
6
0.3
0.3
0.6
6
6
0.3
0.3
0.6
6
µs
c(W)OP
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation
(boot block)
t
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
c(W)ERB
c(W)ERP
Cycle time, erase operation
(parameter block)
t
Cycle time, erase operation
(main block)
t
t
t
s
c(W)ERM
d(RPR)
h(A)
Delay time, boot-block relock
t
200
100
200
100
200
100
ns
ns
PHBR
Hold time, A0–A17
(see Note 15)
t
0
0
0
0
0
0
WHAX
t
t
Hold time, DQ valid
Hold time, E
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
h(D)
WHDX
h(E)
WHEH
Hold time, V
PP
from valid
status register bit
t
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
h(VPP)
QVVL
Hold time, RP at V
valid status register bit
from
HH
t
h(RP)
QVPH
Setup time, A0–A17
(see Note 15)
t
t
t
t
90
90
0
50
50
0
105
105
0
50
50
0
120
120
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(E)
AVWH
Setup time, DQ
t
DVWH
Setup time, E before write
operation
t
ELWL
NOTE 15: A –A17 for byte-wide
–1
timing requirements for TMS28F004AMy and TMS28F400AMy (continued)
write/erase operations — W-controlled writes
’28F004AMy60
’28F400AMy60
’28F004AMy70
’28F400AMy70
28F004AMy80
’28F400AMy80
ALT.
SYMBOL
3.3-V V
CC
RANGE
5-V V
RANGE
3.3-V V 5-V V
3.3-V V
CC
RANGE
5-V V
RANGE
UNIT
CC
CC
RANGE
CC
CC
RANGE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, RP at V
going high
to W
HH
t
t
t
200
100
100
200
100
100
200
100
100
ns
ns
su(RP)
PHHWH
Setup time, V
high
to W going
PP
t
200
200
200
su(VPP)1
VPWH
t
t
Pulse duration, W low
Pulse duration, W high
t
90
20
50
10
105
25
50
20
120
30
50
30
ns
ns
w(W)
WLWH
t
w(WH)
WHWL
Recovery time, RP high to W
going low
t
t
800
450
800
450
800
450
ns
rec(RPHW)
PHWL
NOTE 15: A –A17 for byte-wide
–1
timing requirements for TMS28F004AMy and TMS28F400AMy
write/erase operations — E-controlled writes
’28F004AMy60
’28F004AMy70
’28F400AMy70
28F004AMy80
’28F400AMy80
’28F400AMy60
ALT.
3.3-V V
CC
RANGE
5-V V
CC
RANGE
3.3-V V
CC
RANGE
5-V V
3.3-V V
CC
RANGE
5-V V
UNIT
CC
CC
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
110
60
6
130
70
150
80
ns
c(E)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
6
0.3
0.3
0.6
6
6
0.3
0.3
0.6
6
µs
c(E)OP
EHQV1
EHQV2
EHQV3
EHQV4
Cycle time, erase operation (boot
block)
t
t
t
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
s
c(E)ERB
c(E)ERP
c(E)ERM
Cycle time, erase operation
(parameter block)
Cycle time, erase operation (main
block)
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
200
100
200
100
200
100
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
EHAX
EHDX
t
h(D)
Hold time, W
t
EHWH
h(W)
Hold time, V
status-register bit
from valid
PP
t
t
t
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
h(VPP)
h(RP)
QVVL
Hold time, RP at V
status-register bit
from valid
HH
t
QVPH
t
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
90
90
0
50
50
0
105
105
0
50
50
0
120
120
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(W)
AVEH
t
DVEH
Setup time, W before write operation
t
WLEL
Setup time, RP at V
high
to E going
HH
t
t
200
100
200
100
200
100
ns
su(RP)
PHHEH
t
t
t
Setup time, V
PP
to E going high
t
200
90
100
50
200
105
25
100
50
200
120
30
100
50
ns
ns
ns
su(VPP)2
VPEH
Pulse duration, E low
Pulse duration, E high
t
w(E)
ELEH
EHEL
t
20
10
20
30
w(EH)
Recovery time, RP high to E going
low
t
t
800
450
800
450
800
450
ns
rec(RPHE)
PHEL
NOTE 15: A –A17 for byte-wide
–1
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
TMS28F004AFy and TMS28F400AFy
The TMS28F004AFy and the TMS28F400AFy configurations offer a 5-V memory read with a 5-V or 12-V
program and erase. This configuration is intended for systems using a single 5-V power supply and it is offered
in three temperature ranges: 0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C.
recommended operating conditions for TMS28F004AFy and TMS28F400AFy
MIN
4.5
0
NOM
MAX
5.5
UNIT
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
During read only (V
5-V V
range
5
V
CC
PP
CC
)
V
PPL
6.5
PPL
V
5-V V
range
4.5
11.4
2
5
5.5
V
PP
During write/erase/erase suspend
12-V V
TTL
range
12
12.6
PP
V
V
+ 0.3
CC
V
V
High-level dc input voltage
Low-level dc input voltage
V
V
IH
CMOS
TTL
V
V
– 0.2
+ 0.2
0.8
CC
CC
– 0.3
– 0.2
IL
CMOS
V
+ 0.2
SS
SS
V
V
V
V
lock-out voltage from write/erase (see Note 7)
2
11.4
0
V
V
V
LKO
CC
RP unlock voltage
lock-out voltage from write/erase
12
13
HH
V
PP
1.5
PPLK
L Suffix
E Suffix
Q Suffix
0
– 40
– 40
70
85
°C
°C
T
A
Operating free-air temperature
125
NOTE 7: Mimimum value at T = 25°C.
A
word/byte typical write and block-erase performance for TMS28F004AFy and TMS28F400AFy
(see Notes 8 and 9)
5-V V
5-V V
CC
AND
12-V V
5-V V
CC
AND
PP
RANGES
PP
RANGES
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
14
Main block erase time
1.9
1.4
0.9
0.8
1.1
1.2
Main block byte-program time
Main block word-program time
Parameter/boot-block erase time
4.2
2.1
7
0.6
0.34
NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.
A
9. Excludes system-level overhead (all times in seconds)
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AFy and TMS28F400AFy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL
V
V
V
= V
= V
= V
MIN,I
MIN,I
MIN,I
= – 2.5 mA
= – 100 µA
= 5.8 mA
2.4
High-level dc
output voltage
CC
CC
CC
CC
CC
CC
OH
OH
OL
V
V
OH
CMOS
V
– 0.4
CC
V
V
Low-level dc output voltage
0.45
12.6
V
V
OL
A9 selection code voltage
During read algorithm-selection mode
11.4
ID
Input current (leakage), except for A9
when A9 = V (see Note 10)
ID
I
I
V
CC
= V
MAX, V = 0 V to V
CC
MAX, RP = V
±1
µA
CC
I
HH
I
I
I
I
A9 selection code current
RP boot-block unlock current
Output current (leakage)
A9 = V
500
500
±10
10
µA
µA
µA
µA
ID
ID
RP = V
RP
O
HH
V
= V
MAX, V = 0 V to V
CC
MAX
CC
PP
CC
CC
O
V
standby current (standby)
V
≤ V
5-V V
range
range
range
PPS
PP
PP
CC
CC
CC
V
supply current (reset/deep
I
RP = V
± 0.2 V, V
≤ V
CC
5-V V
5-V V
5
200
25
µA
µA
PPL
PP1
SS
PP
power-down mode)
I
V
PP
supply current (active read)
V
PP
≥ V
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (active byte-write)
PP
I
I
I
I
Programming in progress
Programming in progress
Block-erase in progress
Block-erase suspended
mA
mA
mA
µA
PP2
PP3
PP4
PP5
(see Notes 11 and 12)
12-V V
5-V V
range,
range
PP
20
25
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (active word-write)
PP
(see Notes 11 and 12)
12-V V
5-V V
range,
range
PP
20
CC
5-V V
5-V V
range,
range
PP
CC
20
V
supply current (block-erase)
PP
(see Notes 11 and 12)
12-V V
5-V V
range,
range
PP
15
CC
5-V V
5-V V
range,
range
PP
CC
200
200
V
supply current (erase-suspend)
PP
(see Notes 11 and 12)
12-V V
range,
PP
5-V V
5-V V
5-V V
range
range
range
CC
CC
CC
TTL-input level
2
130
8
mA
V
supply current
CC
(standby)
I
I
V
CC
= V
MAX, E = RP = V
CC IH
CCS
CMOS-input level
µA
0°C to 70°C
V
supply current (reset/deep
CC
power-down mode)
– 40°C to 85°C
– 40°C to 125°C
8
µA
RP = V
± 0.2 V
CCL
SS
40
E = V
,
I
= 0 mA,
IL OUT
f = 10 MHz, G = V
TTL-input level
65
60
mA
mA
5-V V
range
range
CC
CC
V
supply current
IH
= 0 mA,
CC
(active read)
I
CC1
E = V , I
SS OUT
f = 10 MHz, G = V
CMOS-input level
5-V V
CC
NOTES: 10. DQ15/A is tested for output leakage only.
–1
11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AFy and TMS28F400AFy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
5-V V
MIN
MAX
UNIT
range,
range
PP
CC
50
5-V V
V
supply current (active byte-write)
(see Notes 11 and 12)
V
= V MAX,
CC CC
Programming in progress
CC
I
mA
CC2
CC3
12-V V
range,
range
PP
45
50
45
35
30
10
5-V V
CC
5-V V
5-V V
range,
range
PP
CC
V
supply current (active word-write)
CC
(see Notes 11 and 12)
V
= V MAX,
CC CC
Programming in progress
I
mA
12-V V
range,
range
PP
5-V V
CC
5–V V
5-V V
range,
range
PP
CC
V
CC
V
PP
= V
MAX
CC
= 12 V or 5 V
V
supply current (block-erase)
CC
(see Notes 11 and 12)
I
I
mA
mA
CC4
12-V V
range,
range
PP
Block-erase in progress
5-V V
CC
V
supply current (erase-suspend)
CC
(see Notes 11 and 12)
V
= V
MAX, E = V ,
CC CC IH
Block-erase suspended
5-V V
range
CC5
CC
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
power-up and reset switching characteristics for TMS28F004AFy and TMS28F400AFy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 11, 12, and 13)
’28F004AFy60 ’28F004AFy70 ’28F004AFy80
’28F400AFy60 ’28F400AFy70 ’28F400AFy80
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN MAX
Setup time, RP low to V
Note 14)
at 4.5 V MIN (see
t
t
CC
PL5V
PL3V
t
0
2
0
2
0
2
ns
su(VCC)
t
t
t
Address valid to data valid
Setup time, RP high to data valid
Hold time, V at 4.5 V (MIN) to RP high
t
60
70
80
ns
ns
µs
a(DV)
AVQV
t
450
450
450
su(DV)
h(RP5)
PHQV
t
CC
5VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
power-up and reset switching characteristics for TMS28F400AFy over recommended ranges of
supply voltage (automotive temperature range) (see Notes 11, 12, 13)
’28F004AFy70 ’28F004AFy80 ’28F004AFy90
’28F400AFy70 ’28F400AFy80 ’28F400AFy90
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN MAX
Setup time, RP low to V
(see Note 14)
at 4.5 V MIN
t
t
CC
PL5V
PL3V
t
0
2
0
2
0
2
ns
su(VCC)
t
t
t
Address valid to data valid
Setup time, RP high to data valid
Hold time, V at 4.5 V (MIN) to RP high
t
70
80
90
ns
ns
µs
a(DV)
AVQV
t
450
450
450
su(DV)
h(RP5)
PHQV
t
CC
5VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
switching characteristics for TMS28F004AFy and TMS28F400AFy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
’28F004AFy60 ’28F004AFy70 ’28F004AFy80
’28F400AFy60 ’28F400AFy70 ’28F400AFy80
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
Access time from A0–A17 (see Note 15)
Access time from E
t
60
60
35
70
70
40
80
80
40
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
a(E)
ELQV
GLQV
Access time from G
t
t
a(G)
c(R)
Cycle time, read
t
60
0
70
0
80
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, E low to low-impedance output
Delay time, G low to low-impedance output
Disable time, E to high-impedance output
Disable time, G to high-impedance output
d(E)
t
t
0
0
0
d(G)
dis(E)
dis(G)
25
25
30
30
30
30
t
Hold time, DQ valid from A0–A17, E, or G,
whichever occurs first (see Note 15)
t
t
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
450
25
5
450
30
5
450
30
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8–DQ15 in
high-impedance state
t
FLQZ
Access time from BYTE going high
t
60
70
80
FHQV
NOTE 15: A –A17 for byte-wide
–1
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
switching characteristics for TMS28F400AFy over recommended ranges of supply voltage
(automotive temperature range)
read operations
’28F400AFy70 ’28F400AFy80 ’28F004AFy90
’28F400AFy70 ’28F400AFy80 ’28F400AFy90
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
Access time from A0–A17 (see Note 15)
Access time from E
t
70
70
35
80
80
40
90
90
45
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
a(E)
ELQV
GLQV
Access time from G
t
t
a(G)
c(R)
Cycle time, read
t
70
0
80
0
90
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, E low to low-impedance output
Delay time, G low to low-impedance output
Disable time, E to high-impedance output
Disable time, G to high-impedance output
d(E)
t
t
0
0
0
d(G)
dis(E)
dis(G)
25
25
30
30
35
35
t
Hold time, DQ valid from A0–A17, E, or G,
whichever occurs first (see Note 15)
t
t
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
300
30
5
300
30
5
300
35
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8–DQ15 in
high-impedance state
t
FLQZ
Access time from BYTE going high
t
70
80
90
FHQV
NOTE 15: A –A17 for byte-wide
–1
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F400AFy (commercial and extended temperature ranges)
write/erase operations — W-controlled writes
’28F004AFy60 ’28F004AFy70 ’28F004AFy80
’28F400AFy60
’28F400AFy70
’28F400AFy80
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
Cycle time, write
t
60
70
80
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
6
6
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation (boot block)
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
Cycle time, erase operation (parameter
block)
s
Cycle time, erase operation (main block)
s
t
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
100
100
100
ns
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
h(E)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
QVPH
WHPL
Hold time, RP at V
status-register bit
from valid
HH
t
t
0
0
0
ns
h(RP)
t
t
t
t
t
t
t
t
t
t
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
0
50
0
50
0
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(WP)
t
su(WP)
su(A)
ELPH
AVWH
DVWH
t
50
50
50
t
50
50
50
su(D)
Setup time, E before write operation
t
0
0
0
su(E)
ELWL
Setup time, RP at V
to W going high
t
PHHWH
100
100
50
100
100
50
100
100
50
su(RP)
su(VPP)1
w(W)
HH
to W going high
Setup time, V
t
PP
VPWH
WLWH
WHWL
Pulse duration, W low
t
Pulse duration, W high
t
10
20
30
w(WH)
rec(RPHW)
Recovery time, RP high to W going low
t
450
450
450
PHWL
NOTE 15: A –A17 for byte-wide
–1
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F400AFy (automotive temperature range)
write/erase operations — W-controlled writes (continued)
’28F004AFy70
’28F400AFy70
’28F004AFy80
’28F400AFy80
’28F004AFy90
’28F400AFy90
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
Cycle time, write
t
70
80
6
90
7
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation (boot block)
0.3
0.3
0.6
0.3
0.3
0.6
0.4
0.4
0.4
Cycle time, erase operation (parameter
block)
s
Cycle time, erase operation (main block)
s
t
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
100
100
100
ns
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
h(E)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
QVPH
WHPL
Hold time, RP at V
status-register bit
from valid
HH
t
t
0
0
0
ns
h(RP)
t
t
t
t
t
t
t
t
t
t
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
0
50
0
50
0
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(WP)
t
su(WP)
su(A)
ELPH
AVWH
DVWH
t
50
50
50
t
50
50
50
su(D)
Setup time, E before write operation
t
0
0
0
su(E)
ELWL
Setup time, RP at V
to W switching high
t
PHHWH
100
100
60
100
100
60
100
100
60
su(RP)
su(VPP)1
w(W)
HH
to W switching high
Setup time, V
PP
t
VPWH
WLWH
WHWL
Pulse duration, W low
t
Pulse duration, W high
t
20
30
40
w(WH)
rec(RPHW)
Recovery time, RP high to W going low
t
220
220
220
PHWL
NOTE 15: A –A17 for byte-wide
–1
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F400AFy (commercial and extended temperature ranges)
write/erase operations — E-controlled writes
’28F004AFy60
’28F400AFy60
’28F004AFy70
’28F400AFy70
’28F004AFy80
’28F400AFy80
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
60
6
70
6
80
6
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
t
t
t
c(E)OP
c(E)ERB
c(E)ERP
c(E)ERM
d(RPR)
h(A)
EHQV1
EHQV2
EHQV3
EHQV4
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
100
100
100
ns
ns
ns
ns
ns
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
EHAX
EHDX
t
h(D)
Hold time, W
t
EHWH
h(W)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
QVPH
WHPL
Hold time, RP at V
bit
from valid status-register
HH
t
t
0
0
0
ns
h(RP)
t
t
t
t
t
t
t
t
t
t
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
0
50
0
50
0
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(WP)
t
su(WP)
su(A)
ELPH
AVEH
DVEH
t
50
50
50
t
50
50
50
su(D)
Setup time, W before write operation
t
0
0
0
su(W)
su(RP)
su(VPP)2
w(E)
WLEL
Setup time, RP at V
to E going high
HH
to E going high
t
100
100
50
100
100
50
100
100
50
PHHEH
Setup time, V
t
VPEH
PP
Pulse duration, E low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, E high
10
20
30
w(EH)
rec(RPHE)
Recovery time, RP high to E going low
450
450
450
NOTE 15: A –A17 for byte-wide
–1
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F400AFy (automotive temperature range)
write/erase operations — E-controlled writes (continued)
’28F004AFy70
’28F400AFy70
’28F004AFy80
’28F400AFy80
’28F004AFy90
’28F400AFy90
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
Cycle time, write
t
70
80
6
90
7
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
c(E)OP
c(E)ERB
c(E)ERP
EHQV1
EHQV2
EHQV3
EHQV4
Cycle time, erase operation (boot block)
0.3
0.3
0.6
0.3
0.3
0.6
0.4
0.4
0.7
Cycle time, erase operation (parameter
block)
s
t
t
t
t
t
t
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
s
c(E)ERM
d(RPR)
h(A)
t
100
100
100
ns
ns
ns
ns
ns
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
EHAX
t
h(D)
EHDX
Hold time, W
t
EHWH
h(W)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
QVPH
WHPL
Hold time, RP at
status-register bit
V
from valid
HH
t
t
0
0
0
ns
h(RP)
t
t
t
t
t
t
t
t
t
t
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0–A17 (see Note 15)
Setup time, DQ valid
t
0
50
0
50
0
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(WP)
t
su(WP)
su(A)
ELPH
AVEH
DVEH
t
50
50
t
50
50
su(D)
Setup time, W before write operation
t
0
0
su(W)
su(RP)
su(VPP)2
w(E)
WLEL
Setup time, RP at V
to E going high
HH
to E going high
t
100
100
60
100
100
60
50
50
60
40
300
PHHEH
Setup time, V
t
VPEH
PP
Pulse duration, E low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, E high
20
30
w(EH)
rec(RPHE)
Recovery time, RP high to E going low
300
300
NOTE 15: A –A17 for byte-wide
–1
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
TMS28F004AZy and TMS28F400AZy
The TMS28F004AZy and the TMS28F400AZy configurations offer a 5-V memory read with a 12-V program and
a 12-V erase for fast programming and erasing times. This configuration is offered in three temperature ranges:
0°C to 70°C, – 40°C to 85°C, and – 40°C to 125°C.
recommended operating conditions for TMS28F004AZy and TMS28F400AZy
MIN
4.5
0
NOM
MAX
5.5
UNIT
V
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
During read only
5-V V
CC
range
5
V
CC
V
PPL
6.5
V
V
V
PP
During write/erase/erase suspend
12-V V
TTL
range
11.4
2
12
12.6
PP
V
V
+ 0.3
CC
V
V
High-level dc input voltage
Low-level dc input voltage
IH
CMOS
TTL
V
V
– 0.2
+ 0.2
0.8
CC
CC
– 0.3
– 0.2
IL
CMOS
V
+ 0.2
SS
SS
V
V
V
V
lock-out voltage from write/erase (see Note 7)
2
11.4
0
V
V
V
LKO
CC
RP unlock voltage
lock-out voltage from write/erase
12
13
HH
V
PP
1.5
PPLK
L Suffix
E Suffix
Q Suffix
0
– 40
– 40
70
85
°C
°C
T
A
Operating free-air temperature
125
NOTE 7: Mimimum value at T = 25°C.
A
word/byte typical write and block-erase performance for TMS28F400AZy and TMS28F400AZy
(see Notes 8 and 9)
12-V V
5-V V
CC
AND
PP
RANGES
PARAMETER
MIN
TYP
MAX
14
Main block-erase time
1.1
1.2
Main block-byte program time
Main block-word program time
Parameter/boot-block erase time
4.2
2.1
7
0.6
0.34
NOTES: 8. Typical values shown are at T = 25°C and nominal conditions.
A
9. Excludes system-level overhead (all times in seconds)
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
electrical characteristics for TMS28F004AZy and TMS28F400AZy over recommended ranges of
supply voltage and operating free-air temperature using test conditions given in Table 9 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL
V
V
V
= V
= V
= V
MIN,I
MIN,I
MIN,I
= – 2.5 mA
= – 100 µA
= 5.8 mA
2.4
High-level dc
output voltage
CC
CC
CC
CC
CC
CC
OH
OH
OL
V
V
OH
CMOS
V
– 0.4
CC
V
V
Low-level dc output voltage
0.45
12.6
V
V
OL
A9 selection code voltage
During read algorithm-selection mode
V = V MAX,
CC
11.4
ID
Input current (leakage), except for A9
when A9 = V (see Note 10)
ID
CC
I
I
±1
µA
V = 0 V to V MAX, RP = V
I
CC
HH
I
I
A9 selection code current
A9 = V
500
500
µA
µA
ID
ID
RP boot-block unlock current
RP = V
RP
HH
= V
V
CC
V
CC
MAX, V = 0 V to
O
CC
MAX
I
I
I
I
I
Output current (leakage)
±10
10
5
µA
µA
µA
µA
mA
O
V
V
standby current (standby)
supply current (reset/deep
V
PP
≤ V
5-V V
5-V V
5-V V
range
range
range
PPS
PPL
PP1
PP2
PP
CC
± 0.2 V, V
CC
CC
CC
PP
RP = V
≤ V
CC
SS
≥ V
PP
power-down mode)
V
V
supply current (active read)
V
PP
200
20
PP
CC
supply current (active byte write)
12-V V
5-V V
CC
range,
PP
range
PP
Programming in progress
Programming in progress
Block erase in progress
Block erase suspended
(see Notes 11 and 12)
V
supply current (active word write)
12-V V
5-V V
CC
range,
PP
range
PP
(see Notes 11 and 12)
I
I
I
20
15
mA
mA
µA
PP3
PP4
PP5
V
supply current (block erase)
12-V V
5-V V
CC
range,
PP
range
PP
(see Notes 11 and 12)
V
supply current (erase suspend)
12-V V
range,
PP
range
PP
(see Notes 11 and 12)
200
5-V V
CC
TTL-input level
2
130
8
mA
V
supply current
CC
(standby)
I
5-V V
range
V
= V
MAX, E = RP = V
CC IH
CCS
CCL
CC
CC
CMOS-input level
µA
0°C to 70°C
V
supply current (reset/deep
CC
power-down mode)
I
– 40°C to 85°C
– 40°C to 125°C
8
µA
RP = V
± 0.2 V
SS
40
E = V
,
I
= 0 mA,
IL OUT
f = 10 MHz, G = V
TTL-input level
65
60
50
45
45
10
mA
mA
mA
mA
mA
mA
5-V V
range
range
CC
CC
IH
= 0 mA,
V
supply current
CC
(active read)
I
CC1
E = V , I
SS OUT
f = 10 MHz, G = V
CMOS-input level
5-V V
CC
MAX,
V
supply current (active byte write)
V
CC
= V
12-V V
5-V V
CC
range,
PP
range
CC
(see Notes 11 and 12)
CC
I
I
I
I
CC2
CC3
CC4
CC5
Programming in progress
V
supply current (active word write)
V
= V MAX,
12-V V
5-V V
CC
range,
PP
range
CC
(see Notes 11 and 12)
CC
CC
Programming in progress
V
supply current (block erase)
V
= V MAX,
12-V V
range,
PP
range
CC
(see Notes 11 and 12)
CC
CC
Block erase in progress
5-V V
CC
V
supply current (erase suspend)
V
= V MAX, E = V ,
IH
CC
(see Notes 11 and 12)
CC
CC
5-V V
range
CC
Block erase suspended
NOTES: 10. DQ15/A is tested for output leakage only.
–1
11. Not 100% tested; characterization data available
12. All ac current values are RMS unless otherwise noted.
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
power-up and reset switching characteristics for TMS28F004AZy and TMS28F400AZy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 11, 12, and 13)
’28F004AZy60 ’28F004AZy70 ’28F004AZy80
’28F400AZy60 ’28F400AZy70 ’28F400AZy80
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN MAX
Setup time, RP low to V
(see Note 14)
at 4.5 V MIN
t
t
CC
PL5V
PL3V
t
0
2
0
2
0
2
ns
su(VCC)
t
t
t
Address valid to data valid
Setup time, RP high to data valid
Hold time, V at 4.5 V (MIN) to RP high
t
60
70
80
ns
ns
µs
a(DV)
AVQV
t
450
450
450
su(DV)
h(RP5)
PHQV
t
CC
5VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
power-up and reset switching characteristics for TMS28F400AZy over recommended ranges of
supply voltage (automotive temperature range)
’28F004AZy70 ’28F004AZy80 ’28F004AZy90
’28F400AZy70 ’28F400AZy80 ’28F400AZy90
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN MAX
MIN MAX
MIN MAX
Setup time, RP low to V
(see Note 14)
at 4.5 V MIN
t
t
CC
PL5V
PL3V
t
0
2
0
2
0
2
ns
su(VCC)
t
t
t
Address valid to data valid
Setup time, RP high to data valid
Hold time, V at 4.5 V (MIN) to RP high
t
70
80
90
ns
ns
µs
a(DV)
AVQV
t
450
450
450
su(DV)
h(RP5)
PHQV
t
CC
5VPH
NOTES: 11. Characterization data available
12. All ac current values are RMS unless otherwise noted.
13. E and G are switched low after power up.
14. The power supply can switch low concurrently with RP going low.
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
switching characteristics for TMS28F004AZy and TMS28F400AZy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
’28F004AZy60 ’28F004AZy70 ’28F004AZy80
’28F400AZy60 ’28F400AZy70 ’28F400AZy80
ALT.
PARAMETER
5-V V
5-V V
CC
5-V V
CC
UNIT
CC
RANGE
SYMBOL
RANGE
RANGE
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
Access time from A0–A17 (see Note 15)
Access time from E
t
60
60
35
70
70
40
80
80
40
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
a(E)
ELQV
GLQV
Access time from G
t
t
a(G)
c(R)
Cycle time, read
t
60
0
70
0
80
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, E low to low-impedance output
Delay time, G low to low-impedance output
Disable time, E to high-impedance output
Disable time, G to high-impedance output
d(E)
t
t
0
0
0
d(G)
dis(E)
dis(G)
25
25
30
30
30
30
t
Hold time, DQ valid from A0–A17, E, or G,
whichever occurs first (see Note 15)
t
t
0
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from E low
Output delay time from RP high
5
450
25
5
450
30
5
450
30
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8–DQ15 in
high-impedance state
t
FLQZ
Access time from BYTE going high
t
60
70
80
FHQV
NOTE 15: A –A17 for byte-wide
–1
switching characteristics for TMS28F400AZy over recommended ranges of supply voltage
(automotive temperature range)
read operations
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
’28F004AZy90
’28F400AZy90
ALT.
SYMBOL
PARAMETER
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
Access time from A0–A17 (see Note 15)
Access time from E
t
70
70
35
80
80
40
90
90
45
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
a(E)
ELQV
Access time from G
t
t
a(G)
c(R)
GLQV
Cycle time, read
t
70
0
80
0
90
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, E low to low-impedance output
Delay time, G low to low-impedance output
Disable time, E to high-impedance output
Disable time, G to high-impedance output
d(E)
t
t
0
0
0
d(G)
dis(E)
dis(G)
25
25
30
30
35
35
t
Hold time, DQ valid from A0–A17, E, or G,
whichever occurs first (see Note 15)
t
t
0
0
0
ns
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
Setup time, BYTE from E low
5
5
5
su(EB)
NOTE 15: A –A17 for byte-wide
–1
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
switching characteristics for TMS28F400AZy over recommended ranges of supply voltage
(automotive temperature range) (continued)
read operations
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
’28F004AZy90
’28F400AZy90
ALT.
SYMBOL
PARAMETER
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
Output delay time from RP high
t
t
300
300
30
300
35
ns
ns
ns
d(RP)
dis(BL)
a(BH)
PHQV
Disable time, BYTE low to DQ8–DQ15 in
high-impedance state
t
30
FLQZ
Access time from BYTE going high
70
80
90
FHQV
timing requirements for TMS28F004AZy and TMS28F400AZy (commercial and extended
temperature ranges)
write/erase operations — W-controlled writes
’28F004AZy60
’28F400AZy60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
Cycle time, write
t
60
70
6
80
6
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation (boot block)
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
Cycle time, erase operation (parameter
block)
s
Cycle time, erase operation (main block)
s
t
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
100
100
100
ns
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
h(E)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
Hold time, RP at V
status-register bit
from valid
HH
t
t
0
0
0
ns
h(RP)
QVPH
t
t
t
t
t
t
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
su(A)
AVWH
t
su(D)
DVWH
Setup time, E before write operation
t
0
0
0
su(E)
ELWL
Setup time, RP at V
to W going high
t
PHHWH
100
100
50
100
100
50
100
100
50
su(RP)
su(VPP)1
w(W)
HH
to W going high
Setup time, V
t
PP
VPWH
WLWH
WHWL
Pulse duration, W low
t
Pulse duration, W high
t
10
20
30
w(WH)
rec(RPHW)
Recovery time, RP high to W going low
t
450
450
450
PHWL
NOTE 15: A –A17 for byte-wide
–1
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F400AZy (automotive temperature range)
write/erase operations — W-controlled writes (continued)
’28F004AZy60
’28F400AZy60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
Cycle time, write
t
70
80
6
90
7
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
WHQV1
WHQV2
WHQV3
WHQV4
Cycle time, erase operation (boot block)
0.3
0.3
0.6
0.3
0.3
0.6
.4
.4
.7
Cycle time, erase operation (parameter
block)
s
Cycle time, erase operation (main block)
s
t
t
t
t
t
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
100
100
100
ns
ns
ns
ns
ns
d(RPR)
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
h(A)
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, E
h(E)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
Hold time, RP at V
status-register bit
from valid
HH
t
t
0
0
0
ns
h(RP)
QVPH
t
t
t
t
t
t
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
su(A)
AVWH
t
su(D)
DVWH
Setup time, E before write operation
t
0
0
0
su(E)
ELWL
Setup time, RP at V
to W going high
t
PHHWH
100
100
60
100
100
60
100
100
60
su(RP)
su(VPP)1
w(W)
HH
to W going high
Setup time, V
t
PP
VPWH
WLWH
WHWL
Pulse duration, W low
t
Pulse duration, W high
t
20
30
40
w(WH)
rec(RPHW)
Recovery time, RP high to W going low
t
220
220
220
PHWL
NOTE 15: A –A17 for byte-wide
–1
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F004AZy and TMS28F400AZy (commercial and extended
temperature ranges)
write/erase operations — E-controlled writes
’28F004AZy60
’28F400AZy60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
60
6
70
6
80
6
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
t
t
t
t
c(E)OP
c(E)ERB
c(E)ERP
c(E)ERM
d(RPR)
h(A)
EHQV1
EHQV2
EHQV3
EHQV4
0.3
0.3
0.6
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
100
100
100
ns
ns
ns
ns
ns
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
EHAX
EHDX
t
h(D)
Hold time, W
t
EHWH
h(W)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
Hold time, RP at V
bit
from valid status-register
HH
t
t
0
0
0
ns
h(RP)
QVPH
t
t
t
t
t
t
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ
t
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
su(A)
AVEH
t
su(D)
DVEH
Setup time, W before write operation
t
0
0
0
su(W)
su(RP)
su(VPP)2
w(E)
WLEL
Setup time, RP at V
to E going high
t
100
100
50
100
100
50
100
100
50
HH
to E going high
PHHEH
Setup time, V
t
VPEH
PP
Pulse duration, E low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, E high
10
20
30
w(EH)
rec(RPHE)
Recovery time, RP high to E going low
450
450
450
NOTE 15: A –A17 for byte-wide
–1
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
timing requirements for TMS28F400AZy (automotive temperature range)
write/erase operations — E-controlled writes (continued)
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
’28F004AZy90
’28F400AZy90
ALT.
SYMBOL
5-V V
CC
RANGE
5-V V
CC
RANGE
5-V V
CC
RANGE
UNIT
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
Cycle time, write
t
70
80
6
90
7
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming
operation
t
t
t
t
6
c(E)OP
c(E)ERB
c(E)ERP
EHQV1
EHQV2
EHQV3
EHQV4
Cycle time, erase operation (boot block)
0.3
0.3
0.6
0.3
0.3
0.6
0.4
0.4
0.7
Cycle time, erase operation (parameter
block)
s
t
t
t
t
t
t
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0–A17 (see Note 15)
Hold time, DQ valid
s
c(E)ERM
d(RPR)
h(A)
t
100
100
100
ns
ns
ns
ns
ns
PHBR
t
0
0
0
0
0
0
0
0
0
0
0
0
EHAX
t
h(D)
EHDX
Hold time, W
t
EHWH
h(W)
Hold time, V
PP
from valid status-register bit
t
h(VPP)
QVVL
Hold time, RP at V
status-register bit
from valid
HH
t
t
0
0
0
ns
h(RP)
QVPH
t
t
t
t
t
t
t
t
Setup time, A0–A17 (see Note 15)
Setup time, DQ valid
t
50
50
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
su(A)
AVEH
t
su(D)
DVEH
Setup time, W before write operation
t
0
0
0
su(W)
su(RP)
su(VPP)2
w(E)
WLEL
Setup time, RP at V
to E going high
t
100
100
60
100
100
60
100
100
60
HH
to E going high
PHHEH
Setup time, V
t
VPEH
PP
Pulse duration, E low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, E high
20
30
40
w(EH)
rec(RPHE)
Recovery time, RP high to E going low
300
300
300
NOTE 15: A –A17 for byte-wide
–1
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RP (P)
5.0 V
4.5 V
3.3 V
V
CC
(3 V, 5 V)
3.0 V
t
h(RP3)
0 V
t
su(VCC)
t
h(RP5)
Address (A)
Data (D)
Valid
Valid
t
a(DV)
t
t
a(DV)
Valid 3.3 Outputs
Valid 5.0 Outputs
t
su(DV)
su(DV)
Figure 10. Power-Up Timing and Reset Switching
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
t
c(R)
Address Valid
a(A)
A
–A17 (byte-wide)
–1
A0–A17 (word-wide)
t
E
t
dis(E)
t
a(E)
G
t
dis(G)
t
a(G)
W
t
d(G)
t
h(D)
t
d(E)
DQ0–DQ7 (byte-wide)
DQ0–DQ15 (word-wide)
Hi-Z
Hi-Z
V
CC
t
d(RP)
RP
Figure 11. Read-Cycle Timing
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
–A17
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte/Word
Programming
Write
Read-Array
Command
Read Status-
Register Bits
A
–1
(byte-wide)
A0–A17
(word-wide)
t
c(W)
t
t
su(A)
h(A)
E
G
t
su(E)
t
h(E)
t
c(W)OP
t
w(WH)
W
t
w(W)
su(D)
h(D)
Data
t
t
Valid SR
FFh
Hi-Z
DQ0– DQ7
(byte-wide)
DQ0– DQ15
(word-wide)
Hi-Z
Hi-Z
40h or 10h
t
su(RP)
t
rec(RPHW)
t
h(RP)
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)1
V
PP
Figure 12. Write-Cycle Timing (W-Controlled Write)
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
Write
Program-Setup
Command
Write Valid
Address
And Data
Automated
Byte/Word
Programming
Write
Read-Array
Command
Read Status
Register Bits
A
–A17
–1
(byte-wide)
A0–A17
(word-wide)
t
c(W)
t
t
su(A)
h(A)
W
G
E
t
su(W)
t
h(W)
t
c(E)OP
t
w(EH)
t
w(E)
DQ0–
DQ7
Data
t
t
su(D)
h(D)
Valid SR
(byte-
wide)
DQ0–
DQ15
(word-
wide)
FFh
Hi-Z
Hi-Z
Hi-Z
40h or 10h
rec(RPHE)
t
su(RP)
t
h(RP)
t
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)2
V
PP
Figure 13. Write-Cycle Timing (E-Controlled Write)
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power
Up and
Standby
Write
Erase-Setup
Command
Write Erase-
Confirm
Command
Write
Read-Array
Command
Automated
Erase
Read Status-
Register Bits
A
–A17
–1
(byte-wide)
A0–A17
(word-wide)
t
c(W)
t
t
su(A)
h(A)
E
G
t
su(E)
t
h(E)
t
c(W)ERB
t
t
c(W)ERP
c(W)ERM
t
w(WH)
W
t
DQ0–
DQ7
w(W)
D0h
t
t
su(D)
h(D)
Valid SR
FFh
Hi-Z
(byte-
wide)
DQ0–
DQ15
(word-
wide)
Hi-Z
Hi-Z
20h
t
rec(RPHW)
t
su(RP)
t
h(RP)
V
V
HH
IH
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)1
V
V
PPH
V
PP
PPL
Figure 14. Erase Cycle Timing (W-Controlled Write)
74
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
–A17
Write
Erase-Setup
Command
Write Erase-
Confirm
Command
Write
Read-Array
Command
Automated
Erase
Read Status-
Register Bits
A
–1
(byte-wide)
A0–A17
(word-wide)
t
c(W)
t
t
su(A)
h(A)
W
G
E
t
su(W)
t
h(W)
t
t
t
c(E)ERB
c(E)ERP
c(E)ERM
t
w(EH)
t
w(E)
D0h
t
su(D)
h(D)
Valid SR
DQ0–DQ7
(byte-wide)
DQ0–DQ15
(word-wide)
t
FFh
Hi-Z
Hi-Z
Hi-Z
20h
rec(RPHE)
t
t
su(RP)
t
h(RP)
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)2
V
PP
Figure 15. Erase-Cycle Timing (E-Controlled Write)
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
A
–A17
–1
(byte-wide)
A0–A17
Address Valid
(word-wide)
t
c(R)
t
a(A)
E
t
a(E)
t
t
dis(E)
G
dis(G)
t
a(G)
BYTE
t
h(D)
t
su(EB)
Hi-Z
Hi-Z
DQ0–DQ7
Byte DQ0–DQ7
Word DQ0–DQ7
t
d(G)
t
d(E)
DQ8–DQ14
Hi-Z
Hi-Z
t
a(A)
t
dis(BL)
Word DQ8–DQ14
Hi-Z
Hi-Z
DQ15/A
–1
A
Input
–1
Word DQ15
Figure 16. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
PARAMETER MEASUREMENT INFORMATION
A
–A17
–1
(byte-wide)
A0–A17
Address Valid
(word-wide)
t
c(R)
t
a(A)
E
t
a(E)
t
t
t
dis(E)
dis(G)
h(D)
G
t
a(G)
BYTE
t
su(EB)
Byte DQ0–DQ7
t
a(BH)
Hi-Z
Hi-Z
DQ0–DQ7
t
t
d(G)
Word DQ0–DQ7
d(E)
DQ8–DQ14
Hi-Z
Hi-Z
Word DQ8–DQ14
Word DQ15
DQ15/A
–1
A
Input
–1
Hi-Z
Hi-Z
Figure 17. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
MECHANICAL DATA
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,35
M
1,27
0,16
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°–8°
0,80
Seating Plane
0,10
2,625 MAX
0,50 MIN
4073325/A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/262144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
MECHANICAL DATA
DCD (R-PDSO-G**)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
40 PIN SHOWN
A
NO. OF
PINS**
MAX
MIN
1
40
0.402
(10,20) (9,80)
0.385
40
48
0.476
(12,10) (11,90)
0.469
0.020 (0,50)
A
0.012 (0,30)
0.004 (0,10)
0.008 (0,21)
M
21
20
0.728 (18,50)
0.720 (18,30)
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.047 (1,20) MAX
0.006 (0,15)
NOM
Seating Plane
0.004 (0,10)
0.028 (0,70)
0.020 (0,50)
0.010 (25,00) NOM
4073307/B 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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