TMS28F800ASYB70CDBJE [TI]
IC 1M X 8 FLASH 3V PROM, 70 ns, PDSO44, PLASTIC, SOP-44, Programmable ROM;
| 型号： | TMS28F800ASYB70CDBJE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC 1M X 8 FLASH 3V PROM, 70 ns, PDSO44, PLASTIC, SOP-44, Programmable ROM 可编程只读存储器 光电二极管 |
| 文件： | 总52页 (文件大小：690K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
D
D
Organization . . . 1048576 By 8 Bits
524288 By 16 Bits
D
D
Package Options
− 44-Pin Plastic Small-Outline Package
(PSOP) (DBJ Suffix)
− 40-Pin Thin Small-Outline Package
(TSOP) (DCD Suffix)
Array-Blocking Architecture
− Two 8K-Byte/4K-Word Parameter Blocks
− One 96K-Byte/48K-Word Main Block
− Seven 128K-Byte/64K-Word Main Blocks
− One 16K-Byte/8K-Word Protected Boot
Block
− 48-Pin TSOP (DCD Suffix)
− 48-Ball Micro Ball Grid Array
(µBGAt) available
− Top or Bottom Boot Locations
Low Power Dissipation (V
= 5.5 V)
CC
− Active Write . . . 330 mW (Byte Write)
− Active Read . . . 220 mW (Byte Read)
− Active Write . . . 330 mW (Word Write)
− Active Read . . . 275 mW (Word Read)
− Block Erase . . . 330 mW
− Standby . . . 0.55 mW (CMOS-Input
Levels)
− Deep Power-Down Mode . . . 0.044 mW
D
D
All Inputs/Outputs TTL-Compatible
Maximum Access/Minimum Cycle Time
5-V V
’28F008Axy70 70 ns
’28F008Axy80 80 ns
’28F800Axy70 70 ns
’28F800Axy80 80 ns
3-V V
CC
CC
100 ns
120 ns
100 ns
120 ns
(See Table 1 for V /V Voltage
CC PP
D
D
Write-Protection for Boot Block
Configuration)
Industry Standard Command-State Machine
(CSM)
− Erase Suspend/Resume
− Algorithm-Selection Identifier
D
D
100000- and 10000-Program/Erase Cycle
Versions
Three Temperature Ranges
− Commercial . . . 0°C to 70°C
− Extended . . . − 40°C to 85°C
− Automotive . . . − 40°C to 125°C
D
Flexible V /Supply Voltage Combination
PP
D
Embedded Program/Erase Algorithms
− Automated Byte Programming
− Automated Word Programming
− Automated Block Erase
PIN NOMENCLATURE
A0−A18
A0−A19
BYTE
Address Inputs
Address Inputs (for 40-pin TSOP only)
Byte Enable
− Erase Suspend/Erase Resume
DQ0−DQ14 Data In/Out
D
D
Automatic Power-Saving Mode
DQ15/A
Data In/Out (word-wide mode),
Low-Order Address (byte-wide mode)
Chip Enable
−1
JEDEC Standards Compatible
− Compatible With JEDEC Byte/Word
Pinouts
− Compatible With JEDEC EEPROM
Command Set
CE
OE
NC
RP
Output Enable
No Internal Connection
Reset/Deep Power Down
Power Supply
V
CC
V
PP
V
SS
D
Fully Automated On-Chip Erase and
Byte/Word Program Operations
Power Supply for Program/Erase
Ground
WE
Write Enable
WP
Write Protect (for 40-pin and 48-pin
TSOP only)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
µBGA is a trademark of Tessera, Inc.
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Copyright 1998, Texas Instruments Incorporated
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
Table of Contents
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
device symbol nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
logic symbol for TMS28F008Axy 40-pin package . . . . . . . . . . . 6
logic symbol for TMS28F800Axy 44-pin package . . . . . . . . . . . 7
logic symbol for TMS28F800Axy 48-pin package . . . . . . . . . . . 8
functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
block memory maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
boot-block data protection . . . . . . . . . . . . . . . . . . . . . . . . . . 12
parameter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
main block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
command-state machine (CSM) . . . . . . . . . . . . . . . . . . . . . 13
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
command definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
byte-wide or word-wide mode selection . . . . . . . . . . . . . . . 16
command-state machine (CSM) operations . . . . . . . . . . . 18
clear status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
programming operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
automatic power-saving mode . . . . . . . . . . . . . . . . . . . . . . . 20
reset/deep power-down mode. . . . . . . . . . . . . . . . . . . . . . . 20
absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
recommended operating conditions . . . . . . . . . . . . . . . . . . . . . 27
word/byte typical write and block-erase performance . . . . . . 27
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
power-up and reset switching characteristics for
TMS28F008ASy or ’AEy and
TMS28F800ASy or ’AEy . . . . . . . . . . . . . . . . . . . . . . . . . . 30
power-up and reset switching characteristics for
TMS28F008AVy or ’ALy and
TMS28F800AVy or ’ALy . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
power-up and reset switching characteristics for
TMS28F008AZy and TMS28F800AZy . . . . . . . . . . . . . . 37
Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . 40
mechanical data DBJ (R-PDSO-G44) . . . . . . . . . . . . . 48
mechanical data DCD (R-PDSO-G**) . . . . . . . . . . . . . . 49
description
The TMS28F800Axy is a 8388608-bit, boot-block flash memory that can be electrically block-erased and
reprogrammed. The TMS28F800Axy is organized in a blocked architecture consisting of:
D
D
D
D
One 16K-byte/8K-word protected boot block
Two 8K-byte/4K-word parameter blocks
One 96K-byte/48K-word main block
Seven 128K-byte/64K-word main blocks
The device can be ordered in four different voltage configurations (see Table 1). Operation as a 1024K-byte
(8-bit) or a 512K-word (16-bit) organization is user-definable.
Embedded program and block-erase functions are fully automated by the on-chip write-state machine (WSM),
simplifying these operations and relieving the system microcontroller of these secondary tasks. WSM status
can be monitored by an on-chip status register to determine progress of program/erase tasks. The device
features user-selectable block erasure.
The TMS28F800AEy configuration allows the user to perform memory reads using 2.7−3.6-V V
for optimum power consumption. Erasing or programming the device can be accomplished with V
and 5-V V
CC
CC
= 3 V,
PP
5 V, or 12-V. This configuration is offered in the commercial temperature range (0°C to 70°C) and the extended
temperature range (−40°C to 85°C). Also, TMS28F800ASy offers V = 3 − 3.6 V and V = 5 V for optimum
CC
CC
power consumption. The TMS28F800ALy configuration allows performance of memory reads using
= 3.0 − 3.6 V for optimum power consumption. The TMS28F800AVy configuration allows performance of
V
CC
memory reads using V
= 2.7−3.6 V for optimum power consumption.
CC
The TMS28F800AZy configuration offers a 5-V memory read with a 3-V/5-V/12-V program and erase. This
configuration is offered in three temperature ranges: 0°C to 70°C, − 40°C to 85°C, − 40°C to 125°C.
The TMS28F800Axy is offered in a 44-pin plastic small-outline package (PSOP) and a 48-pin thin small-outline
package (TSOP) organized as 16-bit or 8-bit.
The TMS28F008 is functionally equivalent to the ’F800 except that it is organized only as a 8-bit configuration,
and it is offered only in a 40-pin TSOP.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
TMS28F800Axy
44-PIN PSOP (DBJ)
(TOP VIEW)
V
1
2
3
4
5
6
7
8
9
44 RP
43 WE
42 A8
PP
A18
A17
A7
A6
A5
A4
A3
A2
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
A1 10
A0 11
CE 12
V
13
32
V
SS
SS
OE 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
31 DQ15/A
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
−1
23
V
CC
TMS28F800Axy
48-PIN TSOP (DCD)
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A16
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE
2
V
3
SS
DQ15/A
DQ7
4
−1
5
DQ14
DQ6
6
7
A8
8
DQ13
DQ5
NC
NC
WE
RP
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
V
CC
V
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
PP
WP
NC
A18
A17
A7
A6
A5
A4
A3
V
SS
A2
CE
A0
A1
3
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
TMS28F008Axy
40-PIN TSOP (DCD)
(TOP VIEW)
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A16
A15
A14
A13
A12
A11
A9
A17
2
V
SS
3
NC
4
A19
A10
DQ7
DQ6
DQ5
DQ4
5
6
7
8
A8
9
WE
RP
10
11
12
13
14
15
16
17
18
19
20
V
V
CC
CC
V
PP
WP
A18
A7
NC
DQ3
DQ2
DQ1
DQ0
OE
A6
A5
A4
A3
GND
CE
A2
A1
A0
TMS28F800Axy
48-BALL µBGA
(TOP VIEW)
1
2
3
4
5
6
7
8
A
B
C
D
E
F
A13 A11 A8
A14 A10
NC A7 A4
V
WP
PP
A18 A17 A5 A2
A15 A12 A9 NC NC A6 A3 A1
A16 D14 D5 D11 D2 D8 A0
D15 D6 D12 D3 D9 D0
WE RP
CE
V
SS
BYTE
D7 D13 D4
D10 D1
V
SS
V
CC
OE
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
device symbol nomenclature
TMS28FXXXA
X
T
70
C
DBJ
L
Temperature Range Designator
L
E
= Commercial (0°C to 70°C)
= Extended (− 40°C to 85°C)
Q = Automotive (− 40°C to 125°C)
Package Designator
DBJ = Plastic Small-Outline Package (44-Pin)
DCD = Plastic Dual Small-Outline Package (48-Pin)
DCD = Plastic Dual Small-Outline Package (40-Pin)
Program/Erase Endurance
C
B
= 100000 Cycles
= 10000 Cycles
Speed Designator
70 = 70 ns
80 = 80 ns
10 = 100 ns
12 = 120 ns
Boot-Block Location Indicator
T = Top Location
B = Bottom Location
E = 2.7 − 3.6-V/5-V V
CC
and 3-V/5-V/12-V V
PP
L = 3.0 − 3.6-V V
and 3-V/5-V/12-V V
CC
PP
S = 3.0 − 3.6-V/5-V V
and 3-V/5-V/12-V V
PP
CC
V = 2.7−3.6 V
and 3-V/5-V/12-V V
CC
PP
Z = 4.5-V−5.5-V V
(See Note A)
and 3-V/5-V/12-V V
PP
CC
008
800
NOTE A: V
CC
and V
are nominal unless otherwise stated.
PP
Table 1. V /V Voltage Configurations
CC PP
DEVICE CONFIGURATION
TMS28F800AEy
TMS28F800AZy
TMS28F008AEy
TMS28F008AZy
TMS28F800ASy
TMS28F008ASy
TMS28F800AVy
TMS28F008AVy
TMS28F800ALy
TMS28F008ALy
READ VOLTAGE (V
CC
)
PROGRAM/ERASE VOLTAGE (V
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V 5 %
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
3 V/5 V 10% or 12 V " 5%
)
PP
2.7 V to 3.6 V/5 V 10 %
5 V 10 %
2.7 V to 3.6 V/5 V 10 %
5 V 10 %
3.3 V/5 V 10 %
3.3 V/5 V 10 %
2.7 V to 3.6 V
2.7 V to 3.6 V
3.3 V 10 %
3.3 V 10 %
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
†
logic symbol for the TMS28F008Axy 40-pin package
21
FLASH
MEMORY
1048576 × 8
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
0
A
A9
1048575
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
19
10
12
22
RP
WP
CE
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
24
9
OE
WE
A, 3D
∇ 4
A, Z4
25
26
27
28
32
33
34
35
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇ
ꢖ
ꢀꢗ
ꢓ
ꢂ
ꢘ
ꢙ
ꢘ
ꢚ
ꢀ
ꢑ
ꢗ
ꢗ
ꢀꢓ
ꢑ
ꢙ
ꢗ
ꢚ
ꢛ
ꢅ
ꢙ
ꢇ
ꢂ
ꢜ
ꢁ
ꢘ
ꢁ
ꢗ
ꢝ
ꢔ
ꢘ
ꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
†
logic symbol for TMS28F800Axy 44-pin package
11
10
9
8
7
6
5
4
FLASH
MEMORY
524288 × 16
0
A0
A1
A2
A3
A4
A5
A6
A7
42
41
40
39
38
37
36
35
34
3
A8
A9
0
A
524287
A10
A11
A12
A13
A14
A15
A16
A17
A18
2
18
44
33
12
RP
BYTE
CE
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
14
43
OE
WE
A, 3D
∇ 4
A, Z4
15
17
19
21
24
26
28
30
16
18
20
22
25
27
29
31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBJ package.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
†
logic symbol for TMS28F800Axy 48-pin package
25
FLASH
MEMORY
524288 × 16
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
24
23
22
21
20
19
18
8
7
6
0
A9
A
524287
A10
A11
A12
A13
A14
A15
A16
A17
A18
5
4
3
2
1
48
17
16
18
12
47
14
26
RP
BYTE
WP
CE
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
28
11
OE
WE
A, 3D
A, Z4
∇ 4
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
functional block diagram
DQ8−DQ15/A
8
DQ0−DQ7
8
−1
8
DQ15/A
Input Buffer
Output
Buffer
Output
Buffer
Input
Buffer
Input
Buffer
−1
Data
Register
BYTE
I/O Logic
Identification
Register
CE
WE
OE
RP
WP
Output
Multiplexer
Command
State
Machine
Status
Register
19
A0−
A18
Input
Buffer
Power-
Reduction
Control
Data
Comparator
Program/
Write
State
Machine
Erase
Voltage
Switch
V
PP
Address
Latch
Y Decoder
X Decoder
Y Gating/Sensing
16K-
Byte
8K-
Byte
8K-
Byte
Para.
96K-
Byte
Main
128K- 128K- 128K- 128K- 128K- 128K- 128K-
Address
Counter
Byte
Main
Byte
Main
Byte
Main
Byte
Main
Byte
Main
Byte
Main
Byte
Main
Boot Para.
Block Block
Block Block Block Block Block Block Block Block Block
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
architecture
The TMS28F008Axy and TMS28F800Axy use a blocked architecture to allow independent erasure of selected
memory blocks. The block to be erased is selected by using any valid address within that block.
block memory maps (’28F800Axy 16-bit configuration)
The TMS28F800Axy is available with the block architecture mapped in either of two configurations: the boot
block located at the top or at the bottom of the memory array, as required by different microprocessors. The
TMS28F800AxB (bottom boot block) is mapped with the 8K-word boot block located at the low-order address
range (00000h to 01FFFh). The TMS28F800AxT (top boot block) is inverted with respect to the TMS28F800AxB
with the boot block located at the high-order address range (7E000h to 7FFFFh). Both of these address ranges
are for word-wide mode. Figure 1 and Figure 2 show the memory maps for these configurations.
block memory maps (’28F008Axy and ’28F800Axy 8-bit configuration)
The TMS28F008Axy and TMS28F800Axy are available with the block architecture mapped in either of two
configurations: the boot block located at the top (e.g., TMS28F008AxT) or at the bottom (e.g., TMS28F008AxB)
of the memory array, as required by different microprocessors. The ’28F008AxB and ’28F800AxB (8-bit) are
mapped with 16K-byte boot block located at the low-order address range (00000h to 03FFFh). The
TMS28F008AxT and TMS28F800AxT (8-bit) are inverted with respect to the TMS28F008AxB models with the
boot block located at the higher-order address range (FC000h to FFFFFh).
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
block memory maps (continued)
Address
Range
Address
Range
8-bit Configuration
16-bit Configuration
FFFFFh
7FFFFh
Boot Block
Boot Block
16K Addresses
8K Addresses
FC000h
FBFFFh
7E000h
7DFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
FA000h
F9FFFh
7D000h
7CFFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
F8000h
F7FFFh
7C000h
7BFFFh
Main Block
Main Block
96K Addresses
48K Addresses
E0000h
DFFFFh
70000h
6FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
C0000h
BFFFFh
60000h
5FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
A0000h
9FFFFh
50000h
4FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
80000h
7FFFFh
40000h
3FFFFh
Main Block
64K Addresses
Main Block
128K Addresses
60000h
5FFFFh
30000h
2FFFFh
Main Block
Main Block
64K Addresses
128K Addresses
40000h
3FFFFh
20000h
1FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
20000h
1FFFFh
10000h
0FFFFh
Main Block
128K Addresses
Main Block
64K Addresses
00000h
00000h
DQ15/A
Is LSB Address
A0 Is LSB Address
−1
NOTE A: ’28F008Axy is offered in a 40-pin TSOP package, 8-bit configuration only, and A0 is the LSB address.
Figure 1. TMS28F008AxT and TMS28F800AxT (Top Boot Block) Memory Map
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
block memory maps (continued)
Address
Range
Address
Range
8-bit Configuration
16-bit Configuration
FFFFFh
7FFFFh
Main Block
Main Block
128K Addresses
64K Addresses
E0000h
DFFFFh
70000h
6FFFFh
Main Block
64K Addresses
Main Block
128K Addresses
C0000h
BFFFFh
60000h
5FFFFh
Main Block
Main Block
64K Addresses
128K Addresses
A0000h
9FFFFh
50000h
4FFFFh
Main Block
Main Block
64K Addresses
128K Addresses
80000h
7FFFFh
40000h
3FFFFh
Main Block
64K Addresses
Main Block
128K Addresses
60000h
5FFFFh
30000h
2FFFFh
Main Block
Main Block
64K Addresses
128K Addresses
40000h
3FFFFh
20000h
1FFFFh
Main Block
Main Block
64K Addresses
128K Addresses
20000h
1FFFFh
10000h
0FFFFh
Main Block
Main Block
96K Addresses
48K Addresses
08000h
7FFFh
04000h
03FFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
06000h
5FFFh
03000h
02FFFh
Parameter Block
8K Addresses
Parameter Block
4K Addresses
04000h
3FFFh
02000h
01FFFh
Boot Block
Boot Block
8K Addresses
16K Addresses
00000h
00000h
DQ15/A
Is LSB Address
A0 Is LSB Address
−1
NOTE A: ’28F008Axy is offered in a 40-pin TSOP package, 8-bit configuration only, and A0 is LSB adddress.
Figure 2. TMS28F008AxB and TMS28F800AxB (Bottom Boot Block) Memory Map
boot-block data protection
The 16K-byte boot block can be used to store key system data that is seldom changed in normal operation. Data
in this block can be secured by using different combinations of the reset/deep power-down pin (RP), the write
protect pin (WP) and V supply levels. Table 2 provides a list of these combinations.
PP
parameter block
Two parameter blocks of 8K bytes each can be used like a scratch pad to store frequently updated data.
Alternatively, the parameter blocks can be used for additional boot- or main-block data. If a parameter block is
used to store additional boot-block data, caution must be exercised because the parameter block does not have
the boot-block data-protection safety feature.
main block
Primary memory on the TMS28F800Axy is located in eight main blocks. Seven of the blocks have storage
capacity for 128K bytes and the eighth block has storage capacity for 96K bytes.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
data protection
Data is secured or unsecured by using different combinations of the reset/deep power-down pin (RP), the write
protect pin (WP) and V supply levels. See to Table 2 for a listing of these combinations.
PP
There are two configurations to secure the entire memory against inadvertant alteration of data. The V supply
PP
pin can be held below the V lock-out voltage level (V
) or the RP can be pulled to a logic-low level. If RP
PP
PPLK
is held low, the device resets, which means it powers down and, therefore, cannot be read. Typically, this pin
is tied to the system reset for additional protection during system power up.
The boot-block sector has an additional security feature through the WP pin. When the RP pin is at a logic-high
level, the WP pin controls whether the boot-block sector is protected. When WP is held at the logic-low level,
the boot block is protected. When WP is held at the logic-high level, the boot block is unprotected along with
the rest of the other sectors. Alternatively, the entire memory can be unprotected by pulling the RP pin to
V
(12 V).
HH
Table 2. Data-Protection Combinations (see Note 1)
DATA PROTECTION PROVIDED
All blocks locked
V
RP
WP
X
PP
≤ V
≥ V
≥ V
≥ V
≥ V
X
PPLK
PPLK
PPLK
PPLK
PPLK
All blocks locked (reset)
All blocks unlocked
V
IL
X
V
HH
X
Only boot block locked
All blocks unlocked
V
V
IL
IH
IH
V
V
IH
NOTE 1: For TMS28F008AZy and TMS28F800AZy (12-V V ) products, the WP pin is
PP
disabled and can be left floating. To unlock blocks, RP must be at V
.
HH
command-state machine (CSM)
Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface
between the external microprocessor and the internal WSM. Table 1 lists the CSM codes and device modes,
and Table 4 lists the data for the bus cycle. When a program or erase command is issued to the CSM, the WSM
controls the internal sequences and the CSM responds only to status reads. After the WSM completes its task,
the WSM status bit (SB7) is set to a 1, allowing the CSM to respond to the full command set again.
operation
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional
microprocessor timing into an on-chip CSM through I/O pins DQ0−DQ7. When the device is powered up,
internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation
requires that a command code be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.
The on-chip status register allows the progress of various operations to be monitored. The status register is
interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data
on I/O pins DQ0−DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
operation (continued)
Table 3. CSM Codes for Device-Mode Selection
COMMAND
CODE ON
DQ0−DQ7
DEVICE MODE
†
00h
10h
20h
40h
50h
70h
90h
B0h
D0h
FFh
Invalid/Reserved
Alternate Program Setup
Block-Erase Setup
Program Setup
Clear Status Register
Read Status Register
Algorithm Selection
Erase-Suspend
Erase-Resume/Block-Erase Confirm
Read Array
†
DQ0 is the least significant bit. DQ8−DQ15 can be any valid 2-state
level.
command definition
Once a specific command code has been entered, the WSM executes an internal algorithm generating the
necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and
data for each of the bus cycles.
Table 4. Command Definitions
FIRST BUS CYCLE
OPERATION ADDRESS
Read Operations
SECOND BUS CYCLE
BUS
CYCLES
REQUIRED
COMMAND
DATA
INPUT
DATA
OPERATION ADDRESS
IN/OUT
Read Array
1
3
2
1
Write
Write
Write
Write
X
X
X
X
FFh
90h
70h
50h
Read
Read
Read
X
A0
X
Data Out
M/D
Read Algorithm-Selection Code
Read Status Register
SRB
Clear Status Register
Program Mode
Program Setup/Program
(byte/word)
2
Write
PA
40h or 10h
Write
PA
PD
Erase Operations
Block-Erase Setup/
Block-Erase Confirm
2
2
Write
Write
BEA
X
20h
B0h
Write
Write
BEA
X
D0h
D0h
Erase Suspend/
Erase Resume
Legend:
BEA
M/D
PA
Block-erase address. Any address selected within a block selects that block for erase.
Manufacturer-equivalent/device-equivalent code
Address to be programmed
PD
Data to be programmed at PA
SRB
X
Status-register data byte that can be found on DQ0−DQ7
Don’t care
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
status register
The status register can be used to determine whether the state of a program/erase operation is pending or
complete. The status register is monitored by writing a read-status command to the CSM and reading the
resulting status code on I/O pins DQ0−DQ7. This is valid for operations in either the byte-wide or word-wide
mode. When writing to the CSM in word-wide mode, the high-order I/O pins (DQ8−DQ15) can be set to any valid
2-state level. When reading the status bits during a word-wide read operation, the high-order I/O pins
(DQ8−DQ15) are set to 00h internally, so the user needs to interpret only the low-order I/O pins (D0−DQ7).
After a read-status command has been given, the data appearing on DQ0−DQ7 remains as status register data
until a new command is issued to the CSM. To return the device to other modes of operation, a new command
must be issued to the CSM.
Register data is updated on the falling edge of OE or CE. The latest falling edge of either of these two signals
updates the latch within a given read cycle. Latching the data prevents errors from occurring should the register
input change during a status-register read. To ensure that the status-register output contains updated status
data, CE or OE must be toggled for each subsequent status read.
The status register provides the internal state of the WSM to the external microprocessor. During periods when
the WSM is active, the status register can be polled to determine the WSM status. Table 5 defines the
status-register bits and their functions.
Table 5. Status-Register Bit Definitions and Functions
STATUS
BIT
FUNCTION
DATA
COMMENTS
If SB7 = 0 (busy), the WSM has not completed an erase or
programming operation. If SB7 = 1 (ready), other polling operations
can be performed. Until this occurs, the other status bits are not
valid. If the WSM status bit shows busy (0), the user must toggle
CE or OE periodically to determine when the WSM has completed
an operation (SB7 = 1) since SB7 is not updated automatically at
the completion of a WSM task.
Write-state-machine status
(WSMS)
1 = Ready
0 = Busy
SB7
SB6
When an erase-suspend command is issued, the WSM halts
execution and sets the ESS bit high (SB6 = 1), indicating that the
erase operation has been suspended. The WSMS bit also is set
high (SB7 = 1), indicating that the erase-suspend operation has
been completed successfully. The ESS bit remains at a logic-high
level until an erase-resume command is input to the CSM
(code D0h).
1 = Erase suspended
0 = Erase in progress or
completed
Erase-suspend status
(ESS)
SB5 = 0 indicates that a successful block erasure has occurred.
SB5 = 1 indicates that an erase error has occurred. In this case,
the WSM has completed the maximum allowed erase pulses
determined by the internal algorithm, but this was insufficient to
erase the device completely.
1 = Block-erase error
0 = Block-erase good
SB5
SB4
SB3
Erase status (ES)
SB4 = 0 indicates successful programming has occurred at the
addressed block location. SB4 = 1 indicates that the WSM was
unable to program the addressed block location correctly.
1 = Byte/word-program error
0 = Byte/word-program good
Program status (PS)
SB3 provides information on the status of
V
during
PP
1 = Program abort:
programming. If V is lower than V after a program or erase
PP PPL
command has been issued, SB3 is set to a 1, indicating that the
programming operation is aborted. If V is between V and
V
PP
status (VPPS)
V
0 = V
range error
good
PP
PP
PP PPH
V , SB3 is not set.
PPL
SB2−
SB0
Reserved
These bits must be masked out when reading the status register.
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
byte-wide or word-wide mode selection
The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8−DQ15, and
a lower-half that outputs data through DQ0−DQ7. Device operation in either byte-wide or word-wide mode is
user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device
is in the word-wide mode and data is written to, or read from, I/O pins DQ0−DQ15. When BYTE is at a logic-low
level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0−DQ7. In the byte-wide
mode, I/O pins DQ8−DQ14 are placed in the high-impedance state and DQ15/A becomes the low-order
−1
address pin and selects either the upper- or lower-half of the array. Array data from the upper half (DQ8−DQ15)
and the lower half (DQ0−DQ7) are multiplexed to appear on DQ0−DQ7. Table 6 and Table 7 summarize
operations for word-wide mode and byte-wide mode, respectively. Table 8 summarizes the operation for
’28F008Axy.
Table 6. Operation Modes for Word-Wide Mode (BYTE = V ) (’28F800Axy) (see Note 2)
IH
MODE
WP
CE
OE
RP
WE
A9
A0
V
PP
DQ0−DQ15
Read
X
V
V
V
V
X
X
X
Data out
IL
IL
IL
IL
IH
IH
IH
IH
Manufacturer-equivalent code
0089h
X
X
V
V
V
V
V
ID
V
IL
X
X
Device-equivalent code 889Ch
(top boot block)
Algorithm-selection mode
V
V
V
IL
V
IH
V
V
V
ID
V
IH
IL
IH
Device-equivalent code 889Dh
(bottom boot block)
Output disable
Standby
X
X
X
V
IH
V
V
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IH
X
X
X
IH
Reset/deep power down
X
X
V
IL
or
V
or
V
V
V
or
IL
IH
HH
PPL
V
PPH
Write (see Note 3)
V
IL
V
IH
V
IL
X
X
Data in
V
IH
Table 7. Operation Modes for Byte-Wide Mode (BYTE = V ) (’28F800Axy) (see Note 2)
IL
MODE
WP
X
CE
OE
RP
WE
A9
X
A0
X
V
DQ15/A
−1
DQ8−DQ14
Hi-Z
DQ0−DQ7
Data out
PP
Read lower byte
Read upper byte
V
V
V
V
X
V
IL
IL
IL
IL
IL
IH
IH
IH
IH
X
V
V
V
V
X
X
X
V
IH
Hi-Z
Data out
Manufacturer-equivalent
code 89h
X
X
V
V
V
V
V
V
X
X
X
Hi-Z
Hi-Z
IL
IL
IH
IH
ID
IL
Algorithm-selection
mode
Device-equivalent code
9Ch (top boot block)
V
V
V
IL
V
IH
V
V
V
ID
V
IH
X
IL
IH
Device-equivalent code
9Dh (bottom boot block)
Output disable
Standby
X
X
V
IH
V
V
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IH
X
X
X
X
IH
Reset/deep power
down
X
X
X
V
IL
X
X
X
X
X
Hi-Z
Hi-Z
V
V
or
V
IL
or
IH
PPL
or
Write (see Note 3)
V
IL
V
IH
V
IL
X
X
X
Hi-Z
Data in
V
V
HH
V
PPH
IH
NOTES: 2. X = don’t care
3. When writing commands to the ’28F008Axy and the ’28F800Axy, V
must be in the appropriate V
PP
voltage range (as shown in
PP
the recommended operating conditions table for a specific product) for block-erase or program commands to be executed. Also,
depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for
a list of the combinations).
16
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ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
byte-wide or word-wide mode selection (continued)
Table 8. Operation Modes for Byte-Wide Mode (’28F008Axy) (see Note 2)
MODE
WP
CE
OE
RP
WE
A9
A0
V
PP
DQ0−DQ7
Read
X
V
V
V
V
X
X
X
Data out
IL
IL
IL
IL
IH
IH
IH
IH
Manufacturer-equivalent code
89h
X
X
V
V
V
V
V
ID
V
IL
X
X
Device-equivalent code 98
(top boot block)
Algorithm-selection mode
V
V
V
IL
V
IH
V
V
V
ID
V
IH
IL
IH
Device-equivalent code 99
(bottom boot block)
Output disable
Standby
X
X
X
V
IH
V
V
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
IL
IH
IH
V
IH
X
X
X
IH
Reset/deep power down
X
X
V
IL
or
V
or
V
V
V
or
IL
IH
HH
PPL
V
PPH
Write (see Note 3)
V
IL
V
IH
V
IL
X
X
Data in
V
IH
NOTES: 2. X = don’t care
3. When writing commands to the ’28F008Axy and the ’28F800Axy, V
must be in the appropriate V voltage range (as shown in
PP
PP
the recommended operating conditions table for a specific product) for block-erase or program commands to be executed. Also,
depending on the combination of RP and WP, the boot block can be secured and, therefore, is not programmable (see Table 2 for
a list of the combinations).
17
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ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
command-state machine (CSM) operations
The CSM decodes instructions for read, read algorithm-selection code, read-status register, clear-status
register, program, erase, erase-suspend, and erase-resume. The 8-bit command code is input to the device on
DQ0−DQ7 (see Table 1 for CSM codes). During a program or erase cycle, the CSM informs the WSM that a
program or erase cycle has been requested. During a program cycle, the WSM controls the program sequences
and the CSM responds only to status reads.
During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has
completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when V is within its correct voltage range.
PP
For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the V status bit (SB3), the program status bit (SB4), and the erase status
PP
bit (SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor
to clear these status bits and synchronize to internal operations. When the status bits are cleared, the device
returns to the read-array mode.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
D
read array
The array level is read by entering the command code FFh on DQ0−DQ7. Control pins CE and OE must be
at a logic-low level (V ) and WE and RP must be at a logic-high level (V ) to read data from the array. Data is
IL
IH
available on DQ0−DQ15 (word-wide mode) or DQ0−DQ7 (byte-wide mode). Any valid address within any of
the blocks selects that block and allows data to be read from the block.
D
read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0−DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins CE and OE must be at a logic-low level (V ) and WE and RP must be at a logic-high level
IL
(V ). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
IH
DQ0−DQ7 with A0 at a logic-low level (V ). The device-equivalent code is obtained when A0 is set to a
IL
logic-high level (V ). Alternatively, the manufacturer- and device-equivalent codes can be read by applying
IH
V
(nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
ID
“don’t cares” (see Table 4, Table 6, and Table 7).
D
read status register
The status register is read by entering the command code 70h on DQ0−DQ7. Control pins CE and OE must
be at a logic-low level (V ) and WE and RP must be at a logic-high level (V ). Two bus cycles are required
IL
IH
for this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status register contents are updated on the falling edge of CE or OE, whichever occurs last within the
cycle.
18
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ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
programming operations
There are two CSM commands for programming: program setup and alternate program setup
(see Table 1). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM normally cannot be interrupted until the program algorithm is
completed (see Figure 3 and Figure 4).
Taking RP to V during programming aborts the program operation. During programming, V must remain in
IL
PP
the appropriate V
voltage range as shown in the recommended operating conditions table. Different
PP
combinations of RP, WP, and V
pin voltage levels ensure that data in certain blocks are secured, and,
PP
therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and compared
during a program operation. If 1s are programmed, the memory cell contents do not change and no error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the WSM status bit (SB7) is set to a logic-high level, signifying the nonprogram operation is terminated,
all commands to the CSM become valid again.
erase operations
There are two erase operations that can be performed by the TMS28F008Axy and TMS28F800Axy devices:
block erase and erase suspend/erase resume. An erase operation must be used to initialize all bits in an array
block to 1s. After block-erase confirm is issued, the CSM responds only to status reads or erase-suspend
commands until the WSM completes its task.
D
block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single address locations within the array cannot be erased individually.
The block to be erased is selected by using any valid address within that block. Note that different
combinations of RP, WP and V
pin voltage levels ensure that data in certain blocks are secure and,
PP
therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a command
sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see Figure 5). A
two-command erase sequence protects against accidental erasure of memory contents.
Erase-setup and erase-confirm commands are latched on the rising edge of CE or WE, whichever occurs
first. Block addresses are latched during the block-erase-confirm command on the rising edge of CE or WE
(see Figure 15 and Figure 16). When the block-erase-confirm command is complete, the WSM
automatically executes a sequence of events to complete the block erasure. During this sequence, the block
is programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is
performed to ensure that all bits are erased correctly. Monitoring of the erase operation is possible through
the status register (see “read status register” in the subsection “read operations”).
D
erase suspend/erase resume
During the execution of an erase operation, the erase-suspend command (B0h) can be entered to direct the
WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to
respond only to the read-array, read-status-register, and erase-resume commands. During the
erase-suspend operation, array data should be read from a block other than the one being erased. To
resume the erase operation, an erase-resume command (D0h) must be issued to cause the CSM to clear
the suspend state previously set (see Figure 5 and Figure 6).
19
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ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
automatic power-saving mode
Substantial power savings are realized during periods when the array is not being read. During this time, the
device switches to the automatic power-saving (APS) mode. When the device switches to this mode, I
CC
reduces by an order of magnitude. For example, for a 5 V port, I
typically reduces from 40 mA to 1 mA. The
CC
low level of power is maintained until another read operation is initiated. In this mode, the I/O pins retain the data
from the last memory address read until a new address is read. This mode is entered automatically if no new
address is accessed within a 200-ns time-out period.
reset/deep power-down mode
Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device
circuitry. When RP is at a CMOS logic-low level of 0.0 V 0.2 V, a much lower I
This is important in portable applications where extended battery life is of major concern.
value or power is achievable.
CC
A recovery time is required when exiting from deep power-down mode. For a read-array operation, a
minimum of t
is required before data is valid, and a minimum of t
and t
in deep
d(RP)
rec(RPHE)
rec(RPHW)
power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM
is reset and the status register is cleared, effectively eliminating accidental programming to the array during
system reset. After restoration of power, the device does not recognize any operation command until RP is
returned to a V or V
level.
IH
HH
Should RP go low during a program or erase operation, the device powers down and, therefore, becomes
nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the
operation be performed again after power restoration.
20
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ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
Start
BUS
COMMAND
COMMENTS
OPERATION
Issue Program-Setup
Command and Byte Address
Write
Write
program
setup
Data
Addr
=
=
40h or 10h
Address of
byte to be
programmed
Issue Byte
Address/Data
Write
Write data
Data
Addr
=
=
Byte to be
programmed
Address of
byte to be
Read Status-Register
Bits
programmed
Read
Status-register data.
Toggle OE or CE to up-
date status register
No
SB7 = 1
?
Standby
Check SB7
1 = Ready, 0 = Busy
Yes
Repeat for subsequent bytes.
Write FFh after the last byte-programming operation to
reset the device to read-array mode
Full Status-Register
Check (optional)
See Note A
Byte-Program Completed
FULL STATUS-REGISTER-CHECK FLOW
Read
Status-Register Bits
BUS
OPERATION
COMMAND
COMMENTS
No
SB3 = 0
?
V
PP
Range Error
Standby
Check SB3
1 = Detect V
low
PP
(see Note B)
Yes
Check SB4
No
Byte-Program
Failed
Standby
1 = Byte-program error
(see Note C)
SB4 = 0
?
Yes
Byte-Program Passed
NOTES: A. Full status-register check can be done after each byte or after a sequence of bytes.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 3. Automated Byte-Programming Flow Chart
21
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ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Write
Write
program
setup
Data
Addr
=
=
40h or 10h
Address of
word to be
programmed
Issue Program-Setup
Command and Word
Address
Write
Write data
Data
Addr
=
=
Word to be
programmed
Address of
word to be
Issue Word
Address/Data
programmed
Read
Status-register data.
Toggle OE or CE to
update status register.
Read Status-Register
Bits
Standby
Check SB7
1 = Ready, 0 = Busy
No
SB7 = 1
?
Repeat for subsequent words.
Write FFh after the last word-programming operation to
reset the device to read-array mode.
Yes
Full Status-Register
Check (optional)
See Note A
Word-Program
Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
COMMAND
COMMENTS
Check SB3
OPERATION
No
Standby
SB3 = 0
?
V
PP
Range Error
1
=
Detect V
low
PP
(see Note B)
Yes
Standby
Check SB4
1
=
Word-program
error
(see Note C)
No
SB4 = 0
?
Word-Program
Failed
Yes
Word-Program Passed
NOTES: A. Full status-register check can be done after each word or after a sequence of words.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB4 is cleared only by the clear-status-register command, but it does not prevent additional program operation attempts.
Figure 4. Automated Word-Programming Flow Chart
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
20h
Write
Write erase Data =
setup
Block Addr = Address
Issue Erase-Setup Command
and Block Address
within
block to
be
Issue Block-Erase-Confirm
Command and
erased
Write
Erase
Data = D0h
Block Addr = Address
Block Address
within
block to
be
Erase-
Suspend
Loop
Read Status-Register Bits
erased
No
Erase
Suspend
?
Read
Status-register data.
Toggle OE or CE to
update status register
No
Yes
SB7 = 1
?
Yes
Standby
Check SB7
Full Status-Register
Check (optional)
1 = Ready, 0 = Busy
See Note A
Repeat for subsequent blocks.
Write FFh after the last block-erase operation to reset the
device to read-array mode
Block-Erase Completed
FULL STATUS-REGISTER-CHECK FLOW
Read Status-Register
Bits
BUS
COMMAND
COMMENTS
OPERATION
No
Standby
Check SB3
1 = Detect V
SB3 = 0
V
PP
Range Error
low
?
PP
(see Note B)
Yes
SB4 = 1,
SB5 = 1
?
Yes
No
Command Sequence
Error
Standby
Standby
Check SB4 and SB5
1 = Block-erase
error
No
SB5 = 0
?
Block-Erase Failed
Check SB5
1 = Block-erase error
(see Note C)
Yes
Block-Erase Passed
NOTES: A. Full status-register check can be done after each block or after a sequence of blocks.
B. SB3 must be cleared before attempting additional program/erase operations.
C. SB5 is cleared only by the clear-status-register command in cases where multiple blocks are erased before full status is checked.
Figure 5. Automated Block-Erase Flow Chart
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
BUS
OPERATION
Start
COMMAND
COMMENTS
Data = B0h
Write
Erase
suspend
Issue Erase-Suspend
Command
Read
Status-register data.
Toggle OE or CE to
update status register
Read Status-Register
Bits
Standby
Standby
Check SB7
1 = Ready
No
SB7 = 1
?
Yes
Check SB6
1 = Suspended
No
SB6 = 1
?
Erase
Completed
Yes
Write
Read
Write
Read
memory
Data = FFh
Issue Memory-Read
Command
Read data from block
other than that being
erased.
No
Finished
Reading
?
Yes
Issue Erase-Resume
Command
Erase
resume
Data = D0h
Erase Continued
See Note A
NOTE A: See block-erase flow chart for complete erasure procedure
Figure 6. Erase-Suspend/Erase-Resume Flow Chart
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to 7 V
CC
Supply voltage range, V (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to 14 V
PP
Input voltage range: All inputs except A9, RP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to V
+ 1 V
CC
RP, A9 (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to 13.5 V
Output voltage range (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.6 V to V + 1 V
CC
Ambient temperature range, T , during read/erase/program:
L suffix . . . . . . . . . . . . . . 0°C to 70°C
E suffix . . . . . . . . . . . . − 40°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
A
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to V
.
SS
5. The voltage on any input or output can undershoot to − 2 V for periods of less than 20 ns. See Figure 7.
6. The voltage on any input or output can overshoot to 2 V for periods of less than 20 ns. See Figure 8.
5 ns
5 ns
+0.8 V
−0.5 V
V
CC
−2.0 V
20 ns
Figure 7. Maximum Negative Overshoot Waveform
20 ns
V
CC
+ 2.0 V
V
CC
+ 0.5 V
2.0 V
5 ns
5 ns
Figure 8. Maximum Positive Overshoot Waveform
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢌ ꢆꢍ ꢄꢌ ꢎ ꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃ ꢍꢌ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
PARAMETER MEASUREMENT INFORMATION
I
0.1 mA
OL
Output
Under
Test
1.35 V
C
L
(see Note A)
I
−0.1 mA
OH
2.7 V
0.0 V
1.35 V
1.35 V
VOLTAGE WAVEFORMS FOR -100, -120
Conditions: V = 2.7 V
IH
V
= 0 V
= 30 pF
IL
C
L
Measurements taken at: 1.35 V for logic high
1.35 V for logic low
Input rise and fall = <5 ns
NOTES: A.
C includes probe and fixture capacitance.
L
B. Each device should have a 0.1-µF ceramic capacitor connected between V
and V , as closely as possible to the device pins.
SS
CC
Figure 9. 3-V Testing Load Circuit and Voltage Waveform
I
0.5 mA
OL
Output
Under
Test
1.40 V
C
L
(see Note A)
I
−0.5 mA
OH
2.4 V
2 V
0.8 V
0.45 V
VOLTAGE WAVEFORMS FOR -70, -80
Conditions: V = 2.45 V
IH
V
= 0.45 V
= 100 pF
IL
C
L
Measurements taken at: 2.0 V for logic high
0.8 V for logic low
Input rise and fall = <20 ns
NOTES: A.
C includes probe and fixture capacitance.
L
B. Each device should have a 0.1-µF ceramic capacitor connected between V
and V , as closely as possible to the device pins.
SS
CC
Figure 10. 5-V Testing Load Circuit and Voltage Waveform
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢌꢆ ꢍ ꢄ ꢌ ꢎ ꢏꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢌꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇ
ꢖ
ꢀꢗ
ꢓ
ꢂ
ꢘ
ꢙ
ꢘ
ꢚ
ꢀ
ꢑ
ꢗ
ꢗ
ꢀꢓ
ꢑ
ꢙ
ꢗ
ꢚ
ꢛ
ꢅ
ꢙ
ꢇ
ꢂ
ꢜ
ꢁ
ꢘ
ꢁ
ꢗ
ꢝ
ꢔ
ꢘ
ꢂ
SMJS851A − NOVEMBER 1997 − REVISED MARCH 1998
recommended operating conditions
MIN
2.7
3
NOM
3
MAX
3.6
UNIT
3 V
CC
3.3 V
CC
3.3
5
3.6
V
V
Supply voltage
Supply voltage
During write/read/erase/erase suspend
V
V
CC
5 V
4.5
0
5.5
CC
During read only (V
)
6.5
PPL
3 V
5 V
3.0
4.5
11.4
2
3.3
5
3.6
PP
During write/erase/erase suspend, V
as MIN or NOM
can have V
CC
PP
PP
5.5
V
PP
12 V
PP
12
12.6
TTL
V
V
+ 0.5
CC
V
V
High-level dc input voltage
Low-level dc input voltage
V
V
IH
CMOS
TTL
V
V
− 0.2
+ 0.2
0.8
CC
CC
− 0.5
− 0.2
IL
CMOS
V
+ 0.2
SS
1.2
SS
V
V
V
V
lock-out voltage from write/erase (see Note 7)
V
V
LKO
CC
RP unlock voltage
lock-out voltage from write/erase (see Note 7)
11.4
0
12
13
HH
V
PP
1.5
70
85
V
PPLK
L Suffix
E Suffix
0
°C
°C
T
A
Ambient temperature during read/erase/program:
−40
NOTE 7: Typical values shown are at T = 25°C.
A
word/byte typical write and block-erase performance (see Notes 7 and 8)
MIN
TYP
2.4
MAX
UNIT
Main-block erase time
s
s
s
s
Main-block byte-program time
Main-block word-program time
Parameter/boot-block erase time
1.7
1.1
0.84
NOTES: 7. Typical values shown are at T = 25°C.
A
8. Excludes system-level overhead (all times in seconds)
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Template Release Date: 7−11−94
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢆꢄ ꢇꢈ ꢉꢊ ꢵ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢆ ꢇꢈ ꢉ
ꢋꢵ ꢆꢍꢄ ꢵ ꢎ ꢏꢐ ꢵ ꢑ ꢒꢵ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎꢃ ꢍ ꢵ ꢃ ꢄ ꢄꢵ ꢑ ꢒꢵ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇꢖ ꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢵ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛꢵ ꢅꢙ ꢇꢂ ꢜ ꢵ ꢁꢘꢁ ꢗꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVVISED FEBRUARY 1998
28
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢵ ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢵꢆ ꢍ ꢄ ꢵ ꢎ ꢏꢐ ꢵ ꢑꢒꢵꢄ ꢓꢑ ꢔꢀ ꢕꢎ ꢃ ꢍ ꢵ ꢃ ꢄꢄ ꢵꢑ ꢒꢵ ꢋꢐ ꢓꢑ ꢔꢀ
ꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀꢵ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛꢵ ꢅꢙ ꢇꢂ ꢜꢵꢁ ꢘ ꢁꢗ ꢝ ꢔꢘ ꢂ
ꢇ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
•
29
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
power-up and reset switching characteristics for TMS28F008ASy or ’AEy and TMS28F800ASy or
’AEy over recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 10, 11, and 12)
’28F008AEy70
’28F800AEy70
’28F008ASy70
’28F800ASy70
’28F008AEy80
’28F800AEy80
’28F008ASy80
’28F800ASy80
ALT.
SYMBOL
PARAMETER
UNIT
3 V/3.3-V V
CC
5-V V
RANGE
3 V/3.3-V V
CC
5-V V
CC
RANGE
CC
RANGE
RANGE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, RP low to V
3 V MIN or 3.6 V MAX)
(see Note 13)
at
CC
t
t
PL5V
PL3V
t
0
0
0
0
ns
su(VCC)
t
t
Address valid to data valid
t
100
800
70
120
800
80
ns
ns
a(DV)
AVQV
Setup time, RP high to data
valid
t
450
450
su(DV)
PHQV
Hold time, V
to RP high
at 4.5 V (MIN)
CC
t
t
2
2
2
2
2
2
2
2
µs
µs
h(RP5)
5VPH
Hold time, V
RP high
at 3 V (MIN) to
CC
t
t
h(RP3)
3VPH
NOTES: 10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
12. E and G are switched low after power up.
13. The power supply can switch low concurrently with RP going low.
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
switching characteristics for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
read operations
’28F008ASy70
’28F800ASy70
’28F008AEy70
’28F800AEy70
’28F008ASy80
’28F800ASy80
’28F008AEy80
’28F800AEy80
ALT.
PARAMETER
UNIT
3 V
5 V
3 V
5 V
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time, from A0−A18
(see Note 14)
t
t
100
70
120
80
ns
a(A)
AVQV
t
t
t
Access time, from CE
Access time, from OE
Cycle time, read
t
100
65
70
35
120
65
80
40
ns
ns
ns
a(E)
a(G)
c(R)
ELQV
t
t
GLQV
t
100
0
70
0
120
0
80
0
AVAV
Delay time, CE low to
low-impedance output
t
t
t
t
ns
ns
ns
ns
d(E)
ELQX
Delay time, OE low to
low-impedance output
t
t
0
0
0
0
d(G)
GLQX
EHQZ
GHQZ
Disable time, CE to
high-impedance output
55
45
25
25
55
45
30
30
dis(E)
dis(G)
Disable time, OE to
high-impedance output
t
Hold time, DQ valid from
A0−A17, CE, or OE,
whichever occurs first
(see Note 14)
t
t
0
0
0
0
ns
h(D)
AXQX
Setup time, BYTE from CE
low
t
t
ELFL
ELFH
t
t
7
5
5
5
ns
ns
su(EB)
Delay time, output from RP
high
t
800
450
800
450
d(RP)
PHQV
Disable time, BYTE low to
DQ8−DQ15 in the
high-impedance state
t
t
100
100
70
70
120
120
80
80
ns
ns
dis(BL)
a(BH)
FLQZ
Access time, from BYTE
going high
t
t
FHQV
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
timing requirements for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy (commercial and
extended temperature ranges)
write/erase operations — WE-controlled writes
’28F008ASy70
’28F800ASy70
’28F008AEy70
’28F800AEy70
’28F008ASy80
’28F800ASy80
’28F008AEy80
’28F800AEy80
ALT.
UNIT
3 V
5 V
3 V
5 V
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
100
70
120
80
ns
c(W)
AVAV
Cycle time, duration of
programming operation
t
t
6
6
6
6
µs
c(W)OP
WHQV1
WHQV2
Cycle time, erase
operation (boot block)
t
t
t
0.3
0.3
0.3
0.3
s
s
s
c(W)ERB
c(W)ERP
c(W)ERM
Cycle time, erase
operation (parameter
block)
t
0.3
0.6
0.3
0.6
0.3
0.6
0.3
0.6
WHQV3
WHQV4
Cycle time, erase
operation (main block)
t
Delay time, boot-block
relock
t
t
t
200
100
200
100
ns
ns
d(RPR)
PHBR
Hold time, A0−A18
(see Note 14)
t
0
0
0
0
h(A)
WHAX
t
t
Hold time, DQ valid
Hold time, CE
t
t
0
0
0
0
0
0
0
0
ns
ns
h(D)
WHDX
h(E)
WHEH
Hold time, V
PP
from
t
t
0
0
0
0
ns
h(VPP)
h(RP)
QVVL
QVPH
WHPL
valid status-register bit
Hold time, RP at V
from valid status-register
bit
HH
t
t
0
0
0
0
ns
Hold time, WP from valid
status-register bit
t
t
t
0
0
0
0
ns
ns
h(WP)
Setup time, WP before
write operation
t
90
50
100
50
su(WP)
ELPH
Setup time, A0−A17
(see Note 14)
t
t
t
t
90
90
0
50
50
0
100
100
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(E)
AVWH
Setup time, DQ
t
DVWH
Setup time, CE before
write operation
t
ELWL
Setup time, RP at V
WE going high
to
HH
t
t
t
200
200
100
100
100
100
100
100
ns
ns
su(RP)
PHHWH
Setup time, V
going high
to WE
PP
t
su(VPP)1
VPWH
t
t
Pulse duration, WE low
Pulse duration, WE high
t
90
20
50
10
100
30
50
30
ns
ns
w(W)
WLWH
t
w(WH)
WLWL
Recovery time, RP high
to WE going low
t
t
1.5
450
1.5
450
µs
rec(RPHW)
PHWL
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
timing requirements for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy (commercial and
extended temperature ranges)
write/erase operations — CE-controlled writes
’28F008ASy70
’28F800ASy70
’28F008AEy70
’28F800AEy70
’28F008ASy80
’28F800ASy80
’28F008AEy80
’28F800AEy80
ALT.
SYMBOL
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
t
t
Cycle time, write
t
100
70
120
80
ns
c(E)
AVAV
Cycle time, duration of
programming operation
t
t
6
6
6
6
µs
c(E)OP
EHQV1
EHQV2
Cycle time, erase
operation (boot block)
t
0.3
0.3
0.3
0.3
s
s
c(E)ERB
c(E)ERP
Cycle time, erase
operation (parameter
block)
t
t
0.3
0.6
0.3
0.6
0.3
0.6
0.3
0.6
EHQV3
EHQV4
Cycle time, erase
operation (main block)
t
t
t
t
s
c(E)ERM
d(RPR)
h(A)
Delay time, boot-block
relock
t
200
100
200
100
ns
ns
PHBR
Hold time, A0−A18
(see Note 14)
t
0
0
0
0
EHAX
t
t
Hold time, DQ valid
Hold time, WE
t
0
0
0
0
0
0
0
0
ns
ns
h(D)
EHDX
t
h(W)
EHWH
Hold time, V
PP
from valid
status-register bit
t
t
t
t
t
0
0
0
0
0
0
0
0
ns
ns
ns
ns
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
valid status-register bit
from
HH
t
Hold time, WP from valid
status-register bit
t
0
0
0
0
h(WP)
su(WP)
Setup time, WP before
write operation
t
90
50
100
50
ELPH
Setup time, A0−A18
(see Note 14)
t
t
t
t
90
90
0
50
50
0
100
100
0
50
50
0
ns
ns
ns
su(A)
su(D)
su(W)
AVEH
Setup time, DQ
t
DVEH
Setup time, WE before
write operation
t
WLEL
Setup time, RP at V
CE going high
to
HH
t
t
t
200
200
100
100
100
100
100
100
ns
ns
su(RP)
PHHEH
Setup time, V
going high
to CE
PP
t
su(VPP)2
VPEH
t
t
Pulse duration, CE low
Pulse duration, CE high
t
t
90
20
50
10
100
30
50
30
ns
ns
w(E)
ELEH
w(EH)
EHEL
Recovery time, RP high to
CE going low
t
t
1.5
450
1.5
450
µs
rec(RPHE)
PHEL
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
power-up and reset switching characteristics for TMS28F008AVy or ’ALy and TMS28F800AVy or
’ALy over recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 10, 11, and 12)
’28F008AVy100 ’28F008AVy120
’28F800AVy100 ’28F800AVy120
’28F008ALy100 ’28F008ALy120
ALT.
’28F800ALy100 ’28F800ALy120
PARAMETER
UNIT
SYMBOL
3.3-V V 3.3-V V
CC CC
RANGE RANGE
MIN MAX MIN MAX
Setup time, RP low to V
CC
at 3 V MIN or 3.6 V MAX
t
t
PL5V
PL3V
t
0
2
0
2
ns
su(VCC)
(see Note 13)
t
t
t
Access time, address valid to data valid
Setup time, RP high before data valid
t
100
800
120
800
ns
ns
µs
a(DV)
AVQV
t
su(DV)
h(RP3)
PHQV
Hold time, V
CC
at 3 V (MIN) to RP high
t
3VPH
NOTES: 10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
12. E and G are switched low after power up.
13. The power supply can switch low concurrently with RP going low.
switching characteristics for TMS28F008AVy or ’ALy and TMS28F800AV or ’ALy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
read operations
’28F008AVy100 ’28F008AVy120
’28F800AVy100 ’28F800AVy120
’28F008ALy100 ’28F008ALy120
’28F800ALy100 ’28F800ALy120
ALT.
SYMBOL
PARAMETER
UNIT
3 V
MIN
3 V
MIN
MAX
100
100
65
MAX
120
120
65
t
t
t
t
t
t
t
t
Access time, from A0−A18 (see Note 14)
Access time, from CE
t
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
a(E)
ELQV
GLQV
Access time, from OE
t
t
a(G)
c(R)
Cycle time, read
t
100
0
120
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, CE low to low-impedance output
Delay time, OE low to low-impedance output
Disable time, CE to high-impedance output
Disable time, OE to high-impedance output
d(E)
t
t
0
0
d(G)
dis(E)
dis(G)
55
45
55
45
t
Hold time, DQ valid from A0−A17, CE, or OE, whichever occurs
first (see Note 14)
t
t
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from CE low
Delay time, output from RP high
7
800
100
100
5
800
120
120
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8−DQ15 in the high-impedance
state
t
FLQZ
Access time, from BYTE going high
t
FHQV
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
timing requirements for TMS28F008AVy or ’ALy and TMS28F800AVy or ’ALy (commercial and
extended temperature ranges)
write/erase operations — WE-controlled writes
’28F008AVy100 ’28F008AVy120
’28F800AVy100 ’28F800AVy120
’28F008ALy100 ’28F008ALy120
’28F800ALy100 ’28F800ALy120
ALT.
SYMBOL
UNIT
3 V
MIN
3 V
MIN
MAX
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
100
6
120
6
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0−A18 (see Note 14)
Hold time, DQ valid
t
t
t
t
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
d(RPR)
h(A)
WHQV1
WHQV2
WHQV3
WHQV4
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
PHBR
t
0
0
0
0
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, CE
0
0
h(E)
Hold time, V
PP
from valid status-register bit
from valid status-register bit
t
0
0
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
HH
t
0
0
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0−A17 (see Note 14)
Setup time, DQ
t
0
0
h(WP)
t
90
90
90
0
100
100
100
0
su(WP)
su(A)
ELPH
AVWH
DVWH
t
t
su(D)
Setup time, CE before write operation
t
ELWL
su(E)
Setup time, RP at V
to WE going high
to WE going high
t
200
200
90
20
1.5
100
100
100
30
1.5
su(RP)
su(VPP)1
w(W)
HH
PHHWH
Setup time, V
PP
t
VPWH
t
WLWH
Pulse duration, WE low
Pulse duration, WE high
t
WLWL
w(WH)
rec(RPHW)
Recovery time, RP high to WE going low
t
PHWL
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
timing requirements for TMS28F008AVy or ’ALy and TMS28F800AVy or ’ALy (commercial and
extended temperature ranges) (continued)
write/erase operations — CE-controlled writes
’28F008AVy100 ’28F008AVy80
’28F800AVy100 ’28F800AVy80
ALT.
SYMBOL
’28F008ALy100
’28F800ALy100
’28F008ALy80
’28F800ALy80
UNIT
MIN
100
6
MAX
MIN
120
6
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0−A18 (see Note 14)
Hold time, DQ valid
t
t
t
t
c(E)OP
c(E)ERB
c(E)ERP
c(E)ERM
d(RPR)
h(A)
EHQV1
EHQV2
EHQV3
EHQV4
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
200
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
PHBR
t
0
0
0
0
EHAX
t
h(D)
EHDX
Hold time, WE
t
0
0
h(W)
EHWH
Hold time, V
PP
from valid status-register bit
from valid status-register bit
t
0
0
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
HH
t
0
0
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0−A18 (see Note 14)
Setup time, DQ
t
0
0
h(WP)
su(WP)
su(A)
t
90
90
90
0
100
100
100
0
ELPH
AVEH
DVEH
t
t
su(D)
Setup time, WE before write operation
t
WLEL
su(W)
su(RP)
su(VPP)2
w(E)
Setup time, RP at V
to CE going high
to CE going high
t
200
200
90
20
1.5
100
100
100
30
1.5
HH
PHHEH
Setup time, V
PP
t
VPEH
Pulse duration, CE low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, CE high
w(EH)
rec(RPHE)
Recovery time, RP high to CE going low
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
power-up and reset switching characteristics for TMS28F008AZy and TMS28F800AZy over
recommended ranges of supply voltage (commercial and extended temperature ranges)
(see Notes 10, 11, and 12)
’28F008AZy70 ’28F008AZy80
’28F800AZy70 ’28F800AZy80
ALT.
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Setup time, RP low to V
CC
(see Note 13)
at 4.5 V MIN or 5.5 V MAX)
t
t
0
0
ns
su(VCC)
PL5V
t
t
t
Address valid to data valid
t
70
80
ns
ns
µs
a(DV)
AVQV
Setup time, RP high to data valid
t
450
450
su(DV)
h(RP5)
PHQV
Hold time, V
CC
at 4.5 V (MIN) to RP high
t
2
2
5VPH
NOTES: 10. Characterization data available
11. All ac current values are RMS unless otherwise noted.
12. E and G are switched low after power up.
13. The power supply can switch low concurrently with RP going low.
switching characteristics for TMS28F008AZy and TMS28F800AZy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
’28F008AZy70
’28F800AZy70
’28F008AZy80
’28F800AZy80
ALT.
SYMBOL
PARAMETER
UNIT
MIN
MAX
70
MIN
MAX
80
t
t
t
t
t
t
t
t
Access time, from A0−A18 (see Note 14)
Access time, from CE
t
ns
ns
ns
ns
ns
ns
ns
ns
a(A)
AVQV
t
70
80
a(E)
ELQV
GLQV
Access time, from OE
t
t
35
40
a(G)
c(R)
Cycle time, read
t
70
0
80
0
AVAV
ELQX
GLQX
EHQZ
GHQZ
Delay time, CE low to low-impedance output
Delay time, OE low to low-impedance output
Disable time, CE to high-impedance output
Disable time, OE to high-impedance output
d(E)
t
t
0
0
d(G)
dis(E)
dis(G)
25
25
30
30
t
Hold time, DQ valid from A0−A17, CE, or OE, whichever occurs
first (see Note 14)
t
t
0
0
ns
h(D)
AXQX
t
t
ELFL
ELFH
t
t
t
t
Setup time, BYTE from CE low
Delay time, output from RP high
5
450
70
5
450
80
ns
ns
ns
ns
su(EB)
d(RP)
dis(BL)
a(BH)
t
PHQV
Disable time, BYTE low to DQ8−DQ15 in the high-impedance
state
t
FLQZ
Access time, from BYTE going high
t
70
80
FHQV
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
timing requirements for TMS28F008AZy and TMS28F800AZy (commercial and extended
temperature ranges)
write/erase operations — WE-controlled writes
’28F008AZy70
’28F800AZy70
’28F008AZy80
’28F800AZy80
ALT.
UNIT
5 V
5 V
SYMBOL
MIN
70
MAX
MIN
80
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
ns
µs
s
c(W)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0−A18 (see Note 14)
Hold time, DQ valid
t
t
t
t
6
6
c(W)OP
c(W)ERB
c(W)ERP
c(W)ERM
d(RPR)
h(A)
WHQV1
WHQV2
WHQV3
WHQV4
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
PHBR
t
0
0
0
0
WHAX
WHDX
WHEH
t
t
h(D)
Hold time, CE
0
0
h(E)
Hold time, V
PP
from valid status-register bit
from valid status-register bit
t
0
0
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
HH
t
0
0
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0−A17 (see Note 14)
Setup time, DQ
t
0
0
h(WP)
t
50
50
50
0
50
50
50
0
su(WP)
su(A)
ELPH
AVWH
DVWH
t
t
su(D)
Setup time, CE before write operation
t
ELWL
su(E)
Setup time, RP at V
to WE going high
to WE going high
t
100
100
50
10
450
100
100
50
30
450
su(RP)
su(VPP)1
w(W)
HH
PHHWH
Setup time, V
PP
t
VPWH
t
WLWH
Pulse duration, WE low
Pulse duration, WE high
t
WLWL
w(WH)
rec(RPHW)
Recovery time, RP high to WE going low
t
PHWL
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
timing requirements for TMS28F008AZy and TMS28F800AZy (commercial and extended
temperature ranges)
write/erase operations — CE-controlled writes
’28F008AZy70
’28F800AZy70
’28F008AZy80
’28F800AZy80
ALT.
SYMBOL
UNIT
MIN
70
MAX
MIN
80
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
ns
µs
s
c(E)
AVAV
Cycle time, duration of programming operation
Cycle time, erase operation (boot block)
Cycle time, erase operation (parameter block)
Cycle time, erase operation (main block)
Delay time, boot-block relock
Hold time, A0−A18 (see Note 14)
Hold time, DQ valid
t
t
t
t
6
6
c(E)OP
c(E)ERB
c(E)ERP
c(E)ERM
d(RPR)
h(A)
EHQV1
EHQV2
EHQV3
EHQV4
0.3
0.3
0.6
0.3
0.3
0.6
s
s
t
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
PHBR
t
0
0
0
0
EHAX
EHDX
t
h(D)
Hold time, WE
t
0
0
h(W)
EHWH
Hold time, V
PP
from valid status-register bit
from valid status-register bit
t
0
0
h(VPP)
h(RP)
QVVL
QVPH
WHPL
Hold time, RP at V
HH
t
0
0
Hold time, WP from valid status-register bit
Setup time, WP before write operation
Setup time, A0−A18 (see Note 14)
Setup time, DQ
t
0
0
h(WP)
su(WP)
su(A)
t
50
50
50
0
50
50
50
0
ELPH
AVEH
DVEH
t
t
su(D)
Setup time, WE before write operation
t
WLEL
su(W)
su(RP)
su(VPP)2
w(E)
Setup time, RP at V
to CE going high
to CE going high
t
100
100
50
10
450
100
100
50
30
450
HH
PHHEH
Setup time, V
PP
t
VPEH
Pulse duration, CE low
t
t
t
ELEH
EHEL
PHEL
Pulse duration, CE high
w(EH)
rec(RPHE)
Recovery time, RP high to CE going low
NOTE 14: For 28F800 (8-bit configuration) A , A −A18 with A as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB
−1 −1 −1
address.
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Template Release Date: 7−11−94
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ ꢆꢄ ꢇꢈ ꢉꢊ ꢵ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢄꢆ ꢆ ꢇꢈ ꢉ
ꢋꢵ ꢆꢍꢄ ꢵ ꢎ ꢏꢐ ꢵ ꢑ ꢒꢵ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎꢃ ꢍ ꢵ ꢃ ꢄ ꢄꢵ ꢑ ꢒꢵ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇꢖ ꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢵ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛꢵ ꢅꢙ ꢇꢂ ꢜ ꢵ ꢁꢘꢁ ꢗꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVVISED FEBRUARY 1998
40
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
t
c(R)
Address Valid
a(A)
A
−A18
−1
(Byte-Wide)
A0−A18
(Word-Wide)
t
CE
OE
WE
t
dis(E)
t
a(E)
t
dis(G)
t
a(G)
t
d(G)
t
h(D)
t
d(E)
DQ0−DQ7
(Byte-Wide)
DQ0−DQ15
(Word-Wide)
Hi-Z
Hi-Z
V
CC
t
d(RP)
RP
Figure 12. Read-Cycle Timing
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
−A18
Write
Program-Setup
Command
Write Valid
Address or
Data
Automated
Byte/Word-
Programming
Write
Read-Array
Command
Read Status-
Register Bits
A
−1
(Byte-Wide)
A0−A18
(Word-Wide)
t
c(W)
t
t
su(A)
h(A)
CE
OE
WE
t
su(E)
t
h(E)
t
c(W)OP
t
w(WH)
t
w(W)
su(D)
h(D)
Data
t
t
Valid SR
FFh
Hi-Z
DQ0− DQ7
(Byte-Wide)
DQ0− DQ15
(Word-Wide)
Hi-Z
Hi-Z
40h or 10h
rec(RPHW)
t
su(RP)
t
t
h(RP)
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)1
V
PP
Figure 13. Write-Cycle Timing (WE-Controlled Write)
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Write
Program-Setup
Command
Write Valid
Address
And Data
Automated
Byte/Word-
Programming
Write
Read-Array
Command
Read Status
Register Bits
Standby
A
−A18
−1
(Byte-Wide)
A0−A18
(Word-Wide)
t
c(W)
t
t
su(A)
h(A)
WE
OE
CE
t
su(W)
t
h(W)
t
c(E)OP
t
w(EH)
t
w(E)
Data
t
t
su(D)
h(D)
Valid SR
FFh
Hi-Z
DQ0−DQ7
(Byte-Wide)
DQ0−DQ15
(Word-Wide)
Hi-Z
Hi-Z
40h or 10h
rec(RPHE)
t
su(RP)
t
h(RP)
t
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)2
V
PP
Figure 14. Write-Cycle Timing (CE-Controlled Write)
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power
Up and
Standby
Write
Erase-Setup
Command
Write Erase-
Confirm
Command
Write
Read-Array
Command
Automated
Erase
Read Status-
Register Bits
A
−A18
−1
(Byte-Wide)
A0−A18
(Word-Wide)
t
c(W)
t
t
su(A)
h(A)
CE
OE
WE
t
su(E)
t
h(E)
t
c(W)ERB
c(W)ERP
t
t
t
w(WH)
c(W)ERM
t
t
t
w(W)
su(D)
h(D)
D0h
Valid SR
DQ0−DQ7
(Byte-Wide)
DQ0−DQ15
(Word-Wide)
FFh
Hi-Z
Hi-Z
Hi-Z
20h
t
rec(RPHW)
t
su(RP)
t
h(RP)
V
V
HH
IH
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)1
V
V
PPH
V
PP
PPL
Figure 15. Erase-Cycle Timing (WE-Controlled Write)
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
Power Up
and
Standby
−A18
Write
Erase-Setup
Command
Write Erase-
Confirm
Command
Write
Read-Array
Command
Automated
Erase
Read Status-
Register Bits
A
−1
(Byte-Wide)
A0−A18
(Word-Wide)
t
c(W)
t
t
su(A)
h(A)
WE
OE
CE
t
su(W)
t
h(W)
t
t
t
c(E)ERB
c(E)ERP
c(E)ERM
t
w(EH)
t
w(E)
D0h
t
t
su(D)
h(D)
Valid SR
DQ0−DQ7
(Byte-Wide)
DQ0−DQ15
(Word-Wide)
FFh
Hi-Z
Hi-Z
Hi-Z
20h
rec(RPHE)
t
t
su(RP)
t
h(RP)
RP
t
su(WP)
t
h(WP)
WP
t
h(VPP)
t
su(VPP)2
V
PP
Figure 16. Erase-Cycle Timing (CE-Controlled Write)
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
A
−A18
−1
(Byte-Wide)
A0−A18
Address Valid
(Word-Wide)
t
c(R)
t
a(A)
CE
t
a(E)
t
t
dis(E)
dis(G)
OE
t
a(G)
BYTE
t
h(D)
t
su(EB)
Hi-Z
Hi-Z
DQ0−DQ7
Byte DQ0−DQ7
Word DQ0−DQ7
t
d(G)
t
d(E)
DQ8−DQ14
Hi-Z
Hi-Z
t
a(A)
t
dis(BL)
Word DQ8−DQ14
Hi-Z
Hi-Z
DQ15/A
−1
A
Input
−1
Word DQ15
Figure 17. BYTE Timing, Changing From Word-Wide to Byte-Wide Mode
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
PARAMETER MEASUREMENT INFORMATION
A
−A18
−1
(Byte-Wide)
A0−A18
Address Valid
(Word-Wide)
t
c(R)
t
a(A)
CE
t
a(E)
t
t
t
dis(E)
dis(G)
h(D)
OE
t
a(G)
BYTE
t
su(EB)
Byte DQ0−DQ7
t
a(BH)
Hi-Z
Hi-Z
DQ0−DQ7
t
t
d(G)
d(E)
Word DQ0−DQ7
DQ8−DQ14
Hi-Z
Hi-Z
Word DQ8−DQ14
Word DQ15
DQ15/A
−1
A
Input
−1
Hi-Z
Hi-Z
Figure 18. BYTE Timing, Changing From Byte-Wide to Word-Wide Mode
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢆ ꢄꢇ ꢈꢉꢊ ꢀꢁ ꢂꢃ ꢄ ꢅꢄ ꢆ ꢆ ꢇꢈ ꢉ
ꢋꢶꢆ ꢍ ꢶ ꢎꢏ ꢐ ꢑ ꢒ ꢄ ꢓꢑꢔ ꢀ ꢕ ꢎ ꢃꢍ ꢶ ꢃ ꢄ ꢄ ꢑꢒ ꢋ ꢐ ꢓꢑꢔ ꢀ
ꢇ ꢖꢀꢗꢓꢂꢘ ꢙ ꢘꢚ ꢀ ꢑꢗ ꢗꢀꢓꢑꢙ ꢗꢚ ꢛ ꢅꢙ ꢇꢂ ꢜ ꢁꢘꢁ ꢗ ꢝꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
MECHANICAL DATA
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
M
1,27
0,16
0,35
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°−ā8°
0,80
Seating Plane
0,10
2,625 MAX
0,50 MIN
4073325/A 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢉꢊꢀ ꢁ ꢂꢃ ꢄ ꢅꢄꢆ ꢆꢇ ꢈꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓꢑꢔ ꢀꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋꢐ ꢓꢑ ꢔ ꢀ
ꢇꢖꢀꢗ ꢓꢂꢘꢙ ꢘꢚ ꢀ ꢑꢗ ꢗ ꢀꢓꢑꢙ ꢗ ꢚꢛ ꢅ ꢙꢇ ꢂꢜ ꢁꢘ ꢁ ꢗ ꢝꢔ ꢘ ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
MECHANICAL DATA
DCD (R-PDSO-G**)
PLASTIC DUAL SMALL-OUTLINE PACKAGE
40 PIN SHOWN
A
NO. OF
PINS**
MAX
MIN
1
40
0.402
(10,20) (9,80)
0.385
40
48
0.476
(12,10) (11,90)
0.469
0.020 (0,5)
A
0.012 (0,30)
0.004 (0,10)
0.008 (0,21)
M
21
20
0.728 (18,50)
0.720 (18,30)
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.047 (1,20) MAX
0.006 (0,15)
NOM
Seating Plane
0.004 (0,10)
0.028 (0,70)
0.020 (0,50)
0.010 (0,25) NOM
4073307/B 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁ
ꢂ
ꢃ
ꢄꢅ
ꢆ
ꢆ
ꢄ
ꢇ
ꢈ
ꢊ
ꢀ
ꢁ
ꢂꢃ
ꢄ
ꢅꢄ
ꢆ
ꢆ
ꢇ
ꢈ
ꢉ
ꢋ
ꢶ
ꢍ
ꢶ
ꢏ
ꢐ
ꢑ
ꢒ
ꢄ
ꢓ
ꢑ
ꢔ
ꢀ
ꢕ
ꢎ
ꢃ
ꢍ
ꢶ
ꢃ
ꢄ
ꢄ
ꢑ
ꢒ
ꢋ
ꢐ
ꢓ
ꢑ
ꢔ
ꢀ
ꢇ
ꢖ
ꢀ
ꢗ
ꢓ
ꢂ
ꢘ
ꢙ
ꢘ
ꢚ
ꢀ
ꢑ
ꢗ
ꢗ
ꢀ
ꢓ
ꢑ
ꢙ
ꢗ
ꢚ
ꢛ
ꢅ
ꢙ
ꢇ
ꢂ
ꢜ
ꢁ
ꢘ
ꢁ
ꢗꢝ
ꢔ
ꢘ
ꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
Operation Modes for Word-Wide
Mode 17
A
E
absolute maximum ratings 26
access times 1
algorithms 1
electrical characteristics 29
Erase-Cycle Timing (CE-Controlled
Write) 46
organization 1
Erase-Cycle Timing (WE-Controlled
Write) 45
erase operations 20
Erase-Suspend-/Erase-Resume
Flow Chart 25
erase suspend/erase resume 20
architecture 1, 4, 11
Automated Block-Erase Flow Chart
24
Automated Byte-Programming Flow
Chart 22
Automated Word-Programming
Flow Chart 23
P
packaging 1
44-pin TSOP 2
48-pin TSOP 2
parameter block 13
pinout
40-pin TSOP 3
44-pin TSOP 2
48-ball micro ball grid array 3
48-pin TSOP 2
automatic power-saving mode 21
F
flow chart
B
automated block-erase 24
automated byte-programming
22
automated word-programming
23
erase-suspend/erase-resume 25
functional block diagram 10
powe-up and reset switching
characteristics, ’AZy 38
power-up and reset switching,
’AEy and ’ASy 31
power-up and reset switching
characteristics, ’AVy 35
programming operations 20
block-erase functions 4
block erasure 20
block memory maps 11
boot-block data protection 13
BYTE Timing, Changing From
Byte-Wide to Word-Wide Mode
48
BYTE Timing, Changing From
Word-Wide to
L
R
Byte-Wide Mode 47
byte-wide or word-wide mode
selection 16
logic symbol for the
TMS28F008Axy,
40-pin package 6
logic symbol for TMS28F800Axy,
44-pin package 7
read algorithm-selection code 19
read array 19
Read-Cycle Timing 42
read operations 19
’ASy and ’AEy 32
read status register 19
logic symbol for TMS28LF800Axy,
48-pin package 8
C
clear status register 19
command definition 15
recommended operating conditions
28
reset/deep power-down mode 21
command-state machine (CSM)
14
M
Maximum Positive Overshoot Wa-
veform 26
command-state machine (CSM) op-
erations 19
S
memory map
bottom boot block 13
top boot block 12
CSM codes for device-mode selec-
tion 15
cycle times 1
status register 16
Status-Register Bit Definitions and
Functions 16
switching characteristics for ’ASy,
’AEy,
O
D
read operations 32
operation 14
Operation Modes for Byte-Wide
Mode 17, 18
switching characteristics for ’AVy,
read operations 35
data protection 14
Data-Protection Combinations 14
description 4
device symbol nomenclature 5
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢆ ꢆ ꢄ ꢇꢈ ꢊꢀ ꢁ ꢂꢃ ꢄꢅꢄ ꢆꢆ ꢇꢈ ꢉ
ꢋ ꢶ ꢆ ꢍꢄ ꢶ ꢎ ꢏ ꢐ ꢑꢒ ꢄ ꢓ ꢑ ꢔ ꢀ ꢕ ꢎ ꢃ ꢍ ꢶ ꢃ ꢄ ꢄ ꢑ ꢒ ꢋ ꢐ ꢓ ꢑ ꢔ ꢀ
ꢇ ꢖ ꢀꢗ ꢓ ꢂ ꢘ ꢙ ꢘ ꢚ ꢀ ꢑ ꢗ ꢗ ꢀꢓ ꢑ ꢙ ꢗ ꢚ ꢛ ꢅ ꢙꢇ ꢂꢜ ꢁ ꢘꢁ ꢗ ꢝ ꢔ ꢘꢂ
SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998
switching characteristics for ’AZy,
read operations 38
temperature ranges 1
timing requirements for ’ASy, ’AEy,
write/erase
TMS28F800AZy 1
operations 33, 34
V
timing requirements for ’AVy, write/
erase
operations 36, 37
timing requirements for ’AZy, write/
erase
T
VCC/VPP Voltage Configurations
5
voltage configurations 4
table, data-protection combinations
14
table
absolute maximum ratings 26
command definitions 15
CSM codes for device-mode
selection 15
operation modes for byte-wide
mode 18
operation modes for word-wide
mode 17
recommended operating condi-
tions 28
status-register bit definitions 16
VCC/VPP voltage configura-
tions 5
word/byte typical write and block-
erase 28
operations 39, 40
TMS28F008AEy 1
TMS28F008ASy 1
TMS28F008AVy 1
TMS28F008AxB and
TMS28F800AxB
Memory Map 13
TMS28F008AxT and
TMS28F800AxT
W
word/byte typical write and block-
erase performance (see Notes
7 and 8) 28
Write-Cycle Timing (WE-Controlled
Write) 43
Write-Cycle Timing (CE-Controlled
Write) 44
write-state machine (WSM) 4
write/erase operations − CE-con-
trolled writes 34
write/erase operations −WE-con-
trolled writes 33
Memory Map 12
TMS28F008AZy 1
TMS28F800AEy 1, 4
TMS28F800ASy 1, 4
TMS28F800AVy 1, 4
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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