TMS29F800T-90CDBJL [TI]
1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES; 1048576 ×8位/ 524288 ×16位闪存
| 型号： | TMS29F800T-90CDBJL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1048576 BY 8-BIT/ 524288 BY 16-BIT FLASH MEMORIES |
| 文件： | 总51页 (文件大小：684K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
Single Power Supply Supports 5 V 10%
Read/Write Operation
Erase Suspend/Resume
– Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
Organization . . . 1048576 By 8 Bits
524288 By 16 Bits
Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
Array-Blocking Architecture
– One 16K-Byte/One 8K-Word Boot Sector
– Two 8K-Byte/4K-Word Parameter Sectors
– One 32K-Byte/16K-Word Sector
– Fifteen 64K-Byte/32K-Word Sectors
– Any Combination of Sectors Can Be
Erased. Supports Full-Chip Erase
– Any Combination of Sectors Can Be
Marked as Read-Only
Package Options
– 44-Pin Plastic Small-Outline Package
(PSOP) (DBJ Suffix)
– 48-Pin Thin Small-Outline Package
(TSOP) (DCD Suffix)
Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector
– Hardware Method for Detection of
Program/Erase Cycle Completion
Sector Protection
Through Ready/Busy (RY/BY) Output Pin
– Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
High-Speed Data Access at 5-V V
at Three Temperature Ranges
10%
CC
– 80 ns
– 90 ns
– 100 ns
– 120 ns
Commercial . . . 0°C to 70°C
Commercial . . . 0°C to 70°C
Extended . . . –40°C to 85°C
Automotive . . . –40°C to 125°C
Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases
Any Sector
– Automatically Programs and Verifies the
Program Data at Specified Address
PIN NOMENCLATURE
JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM
Command Set
A[0:18]
BYTE
Address Inputs
Byte/Word Enable
Data In/Data out
DQ[0:14]
DQ15/A
–1
Data In/Out (Word-Wide Mode)
Low-Order Address (Byte-Wide Mode)
Chip Enable
Fully Automated On-Chip Erase and
Program Operations
CE
100 000 Program/Erase Cycles
OE
Output Enable
Low Power Dissipation
NC
No Internal Connection
Reset/Deep Power Down
Ready/Busy Output
Power Supply
– 40-mA Typical Active Read for Byte Mode
– 50-mA Typical Active Read for Word
Mode
– 60-mA Typical Program/Erase Current
– Less Than 100-µA Standby Current
– 5 µA in Deep Power-Down Mode
RESET
RY/BY
V
V
CC
Ground
SS
WE
Write Enable
All Inputs/Outputs TTL-Compatible
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
44-PIN PSOP
DBJ PACKAGE
(TOP VIEW)
RY/BY
A18
A17
A7
RESET
WE
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
A8
3
A9
4
A6
A10
A11
A12
A13
A14
A15
A16
BYTE
5
A5
6
A4
7
A3
8
A2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A1
A0
CE
V
V
SS
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ15/A
DQ7
–1
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
description
The TMS29F800T/B is an 1048576 by 8-bit/524288 by 16-bit (8388608-bit), 5-V single-supply, programmable
read-only memory device that can be electrically erased and reprogrammed. This device is organized as
1048576 by 8 bits or 524288 by 16 bits, divided into 19 sectors:
–
–
–
–
One 16K-byte/8K-word boot sector
Two 8K-byte/4K-word sectors
One 32K-byte/16K-word sector
Fifteen 64K-byte/32K-word sectors
Any combination of sectors can be marked as read-only or erased. Full-chip erasure is also supported.
Sector data protection is afforded by methods that can disable any combination of sectors from write or read
operations using standard programming equipment. An on-chip state machine provides an on-board algorithm
that automatically pre-programs and erases any sector before it automatically programs and verifies program
data at any specified address. The command set is compatible with that of the Joint Electronic Device
Engineering Council (JEDEC) standards and is compatible with the JEDEC 8M-bit electrically erasable,
programmable read-only memory (EEPROM) command set. A suspend/resume feature allows access to
unaltered memory blocks during a section-erase operation. All outputs of this device are TTL-compatible.
Additionally, an erase/suspend/resume feature supports reading data from, or programming data to, a sector
that is not being erased.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
48-PIN TSOP
DCD PACKAGE
(TOP VIEW)
A15
A14
A13
A12
A11
A10
A9
A16
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE
2
V
3
SS
DQ15/A
DQ7
4
–1
5
DQ14
DQ6
6
7
A8
8
DQ13
DQ5
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
DQ12
DQ4
WE
RESET
NC
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
V
SS
A2
CE
A0
A1
description (continued)
Device operations are selected by writing JEDEC-standard commands into the command register using
standard microprocessor write timings. The command register acts as an input to an internal-state machine
which interprets the commands, controls the erase and programming operations, outputs the status of the
device, outputs the data stored in the device, and outputs the device algorithm-selection code. On initial power
up, the device defaults to the read mode. A hardware-reset pin initializes the internal-state machine to the read
operation.
The device has low power dissipation with a 40-mA active read for the byte mode, 50-mA active read for the
word mode, 60-mA typical program/erase current mode, and less than 100- A standby current with a 5- A
deep-power-down mode. These devices are offered with 80-, 90-, 100-, and 120-ns access times. Table 1 and
Table 2 show the sector-address ranges. The TMS29F800T/B is offered in a 44-pin plastic small-outline
package (PSOP) (DBJ suffix) and a 48-pin thin small-outline package (TSOP) (DCD suffix).
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
device symbol nomenclature
TMS29F800
T
–90
C
DCD
L
Temperature Range
L = Commercial (0°C to 70°C)
E = Extended (–40°C to 85°C)
Q = Automotive (–40°C to 125°C)
Package Designator
DCD
DBJ
=
=
48-Pin Plastic Dual Small-Outline Package
44-Pin Plastic Small-Outline Package
Program/Erase Endurance
C = 100000 Cycles
B = 10000 Cycles
Speed Option
80 = 80 ns
90 = 90 ns
100 = 100 ns
120 = 120 ns
Boot Code Selection Architecture
T = Top Sector
B = Bottom Sector
Device Number/Description
8M Bits
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
†
logic symbol for 44-pin package
11
10
9
8
7
6
5
4
42
41
40
39
38
37
36
35
34
3
FLASH
MEMORY
524288 × 16
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
0
A
524287
2
18
1
RY/BY
RESET
BYTE
CE
44
33
22
G1
[PWR DWN]
G2 1, 2 EN (READ)
1C3 (WRITE)
14
43
OE
WE
A, 3D
A, Z4
4
15
17
19
21
24
26
28
30
16
18
20
22
25
27
29
31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A
–1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DBJ package.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
†
logic symbol for 48-pin package
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
FLASH
MEMORY
524288 × 16
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
0
A
524287
48
17
16
A16
A17
A18
18
15
12
47
26
RY/BY
RESET
BYTE
CE
G1
[PWR DWN]
G2 1, 2 EN (READ)
1C3 (WRITE)
28
11
OE
WE
A, 3D
A, Z4
4
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A
–1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DCD package.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
block diagram
DQ0–DQ15
RY/BY
Buffer
RY/BY
V
CC
Erase Voltage
Generator
V
SS
Input/Output Buffers
WE
State Control
BYTE
RESET
PGM Voltage
Generator
Command Registers
STB
Data Latch
CE
OE
Chip-Enable
Output-Enable
Logic
Y-Decoder
X-Decoder
Y-Gating
V
CC
Detector
Timer
A
d
d
r
e
s
s
STB
A0–A18
Cell Matrix
L
a
t
c
h
A
–1
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
operation
See Table 1 and Table 2 for the sector-address ranges of the TMS29F800T/B.
†
Table 1. Top-Boot Sector-Address Ranges
A18
1
A17
1
A16
1
A15
1
A14
1
A13
1
A12
X
1
SECTOR SIZE
16K-Byte
8K-Byte
(x8) ADDRESS RANGE
FC000H–FFFFFH
FA000H–FBFFFH
F8000H–F9FFFH
F0000H–F7FFFH
E0000H–EFFFFH
D0000H–DFFFFH
C0000H–CFFFFH
B0000H–BFFFFH
A0000H–AFFFFH
90000H–9FFFFH
80000H–8FFFFH
70000H–7FFFFH
60000H–6FFFFH
50000H–5FFFFH
40000H–4FFFFH
30000H–3FFFFH
20000H–2FFFFH
10000H–1FFFFH
00000H–0FFFFH
(x16) ADDRESS RANGE
7E000H–7FFFFH
7D000H–7DFFFH
7C000H–7CFFFH
78000H–7BFFFH
70000H–77FFFH
68000H–6FFFFH
60000H–67FFFH
58000H–5FFFFH
50000H–57FFFH
48000H–4FFFFH
40000H–47FFFH
38000H–3FFFFH
30000H–37FFFH
28000H–2FFFFH
20000H–27FFFH
18000H–1FFFFH
10000H–17FFFH
08000H–0FFFFH
00000H–07FFFH
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
1
1
1
1
1
0
1
1
1
1
1
0
0
8K-Byte
1
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
1
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
SA8
1
0
0
0
SA7
0
1
1
1
SA6
0
1
1
0
SA5
0
1
0
1
SA4
0
1
0
0
SA3
0
0
1
1
SA2
0
0
1
0
SA1
0
0
0
1
SA0
0
0
0
0
†
The address range is A –A18 in byte mode.
–1
The address range is A0–A18 in word mode.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
operation (continued)
†
Table 2. Bottom-Boot Sector-Address Ranges
A18 A17 A16
A15
1
A14
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
A13
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
A12
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
SECTOR SIZE
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
64K-Byte
32K-Byte
8K-Byte
(x8) ADDRESS RANGE
F0000H–FFFFFH
E0000H–EFFFFH
D0000H–DFFFFH
C0000H–CFFFFH
B0000H–BFFFFH
A0000H–AFFFFH
90000H–9FFFFH
80000H–8FFFFH
70000H–7FFFFH
60000H–6FFFFH
50000H–5FFFFH
40000H–4FFFFH
30000H–3FFFFH
20000H–2FFFFH
10000H–1FFFFH
08000H–0FFFFH
06000H–07FFFH
04000H–05FFFH
00000H–03FFFH
(x16) ADDRESS RANGE
78000H–7FFFFH
70000H–77FFFH
68000H–6FFFFH
60000H–67FFFH
58000H–5FFFFH
50000H–57FFFH
48000H–4FFFFH
40000H–47FFFH
38000H–3FFFFH
30000H–37FFFH
28000H–2FFFFH
20000H–27FFFH
18000H–1FFFFH
10000H–17FFFH
08000H–0FFFFH
04000H–07FFFH
03000H–03FFFH
02000H–02FFFH
00000H–01FFFH
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
SA8
1
SA7
0
SA6
1
SA5
0
SA4
1
SA3
0
SA2
0
0
SA1
0
0
1
0
8K-Byte
SA0
0
0
0
X
16K-Byte
†
The address range is A –A18 in byte mode.
–1
The address range is A0–A18 in word mode.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
operation (continued)
See Table 3 and Table 4 for the operation modes of the TMS29F800T/B.
Table 3. Byte-Operation Mode (BYTE = V )
IL
†
FUNCTIONS
MODE
DQ0–DQ7
CE
OE
WE
A0 A1
A6
A9
RESET
Manufacturer-Equivalent Code 01h
(TMS29F800T/B – Byte)
Algorithm-selection mode
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IL
IH
IH
IH
IL
IH
IH
IL
IL
IL
IL
IL
IL
ID
ID
ID
IH
IH
IH
Device-Equivalent Code D6h
(TMS29F800T – Byte)
V
V
V
V
3-V power supply
Device-Equivalent Code 58h
(TMS29F800B – Byte)
V
V
Read
V
V
V
V
A0
X
A1
X
A6
X
A9
X
V
IH
V
IH
V
IH
V
IH
V
ID
V
IH
Data out
Hi-Z
IL
IL
IH
Output disable
Standby and write inhibit
V
IH
IL
IH
V
IH
X
X
X
X
X
X
Hi-Z
‡
Write
V
IL
V
IH
X
V
IL
A0
X
A1
X
A6
X
A9
X
Data in
X
Temporary sector unprotect
Verify sector protect
Hardware reset
X
X
V
IL
V
IL
V
IH
X
V
IL
V
IH
X
V
IL
V
ID
X
Data out
Hi-Z
X
X
X
X
V
IL
Legend:
V
V
V
†
= Logic 0
= Logic 1
= 12.0 ± 0.5 V
X can be V or V
IL IH
See Table 6 for valid address and data during write.
IL
IH
ID
.
‡
Table 4. Word-Operation Mode (BYTE =V )
IH
†
FUNCTIONS
MODE
DQ0–DQ15
CE
OE
WE
A0 A1
A6
A9
RESET
Manufacturer-Equivalent Code 01h
(TMS29F800T/B – Word)
Algorithm-selection mode
3-V power supply
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IL
IH
IH
IH
IL
IH
IH
IL
IL
IL
IL
IL
IL
ID
ID
ID
IH
IH
IH
Device-Equivalent Code 22D6h
(TMS29F800T – Word)
V
V
V
V
V
Device-Equivalent Code 2258h
(TMS29F800B – Word)
V
V
Read
V
V
V
V
A0
X
A1
X
A6
X
A9
X
V
IH
V
IH
V
IH
V
IH
V
ID
V
IH
Data out
Hi-Z
IL
IL
IH
Output disable
Standby and write inhibit
V
IH
IL
IH
V
IH
X
X
X
X
X
X
Hi-Z
‡
Write
V
IL
V
IH
X
V
IL
A0
X
A1
X
A6
X
A9
X
Data in
X
Temporary sector unprotect
Verify sector protect
Hardware reset
X
X
V
IL
V
IL
V
IH
X
V
IL
V
IH
X
V
IL
V
ID
X
Data out
Hi-Z
X
X
X
X
V
IL
Legend:
V
V
V
†
= Logic 0
= Logic 1
= 12.0 ± 0.5 V
X can be V or V
IL IH
See Table 6 for valid address and data during write.
IL
IH
ID
.
‡
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
read mode
A logic-low signal applied to the CE and OE pins allows the output of the TMS29F800T/B to be read. When two
or more ’29F800T/B devices are connected in parallel, the output of any one device can be read without
interference. The CE pin is for power control and must be used for device selection. The OE pin is for output
control and is used to gate the data output onto the bus from the selected device.
The address-access time (t
) is the delay from stable address to valid output data. The chip-enable (CE)
AVQV
access time (t
) is the delay from CE low and stable addresses to valid output data. The output-enable
) is the delay from OE low to valid output data when CE equals logic low and addresses are
ELQV
access time (t
GLQV
stable for at least the duration of t
–t
.
AVQV GLQV
standby mode
supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In
I
CC
the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on
CE and RESET reduces the current to 100 µA. Applying a TTL logic-high level on CE and RESET reduces the
current to 1 mA. If the ’29F800T/B is deselected during erasure or programming, the device continues to draw
active current until the operation is complete.
output disable
When OE equals V or CE equals V , output from the device is disabled and the output pins (DQ0–DQ15) are
IH
IH
placed in the high-impedance state.
automatic-sleep mode
The ’29F800 has a built-in feature called automatic-sleep mode to minimize device energy consumption which
is independent of CE, WE, and OE, and is enabled when addresses remain stable for 300 ns. Typical
sleep-mode current is 100 µA. Sleep mode does not affect output data, which remains latched and available
to the system.
algorithm selection
The algorithm-selection mode provides access to a binary code that matches the device with its proper
programming and erase command operations. This mode is activated when V (11.5 V to 12.5 V) is placed on
ID
address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address
pin A0 from V to V . Address pins other than A0, A1, and A6 can be at logic low or at logic high.
IL
IH
The algorithm-selection mode can also be read by using the command register, which is useful when V is not
ID
available to be placed on address pin A9. Table 5 shows the binary algorithm-selection codes.
†
Table 5. Algorithm-Selection Codes (5-V Single Power Supply)
CODE DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacturer-
equivalent code
01H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
TMS29F800T–Byte
TMS29F800B–Byte
TMS29F800T
D6H
58H
A
Hi-Z
Hi-Z
0
Hi-Z
Hi-Z
1
Hi-Z
Hi-Z
0
Hi-Z
Hi-Z
0
Hi-Z
Hi-Z
0
Hi-Z
Hi-Z
1
Hi-Z
Hi-Z
0
1
0
1
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
0
0
0
0
1
–1
A
–1
22D6H
2258H
01H
0
0
0
TMS29F800B
0
1
0
0
0
1
0
Sector protection
0
0
0
0
0
0
0
†
A1 = V , A6 = V , CE = V OE = V
IL IL IL,
IL
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erasure and programming
Erasureandprogrammingofthe’29F800areaccomplishedbywritingasequenceofcommandsusingstandard
microprocessor write timing. The commands are written to a command register and input to the command-state
machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume
operations as instructed. The CSM acts as the interface between the write-state machine (WSM) and
external-chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and
verification of memory contents. Program and block-/chip-erase functions are fully automatic. Once the end of
a program or erase operation has been reached, the device resets internally to the read mode. If V
drops
CC
below the low-voltage-detect level (V
), any programming or erase operation is aborted and subsequent
LKO
writes are ignored until the V
level is greater than V
. The control pins must be logically correct to prevent
CC
LKO
unintentional command writes or programming or erasing.
command definitions
Device operating modes are selected by writing specific address and data sequences into the command
register. Table 6 defines the valid command sequences. Writing incorrect address and data values or writing
them in the incorrect sequence causes the device to reset to the read mode. The command register does not
occupy an addressable memory location. The register is used to store the command sequence, along with the
address and data needed by the memory array. Commands are written by setting CE = V , OE = V , and
IL
IH
bringing WE from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched
on the rising edge of WE. Holding WE = V and toggling CE is an alternative method. See the switching
IL
characteristics of the write/erase/program-operations section for specific timing information.
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command definitions (continued)
Table 6. Command Definitions
1ST CYCLE
2ND CYCLE
3RD CYCLE
4TH CYCLE
ADDR DATA
5TH CYCLE
6TH CYCLE
BUS
CYCLES
COMMAND
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
Read/reset
(word)
1
1
3
3
xxxxH
xxx
xxF0H
Read/reset
(byte)
F0H
xxAAH
AAH
Read/reset
(word)
555H
2AAH
2AAH
555H
xx55H
55H
555H
2AAH
xxF0H
F0H
RA
RA
RD
RD
Read/reset
(byte)
22D6H
T
Algorithm
selection (word)
3
3
555H
2AAH
xxAAH
AAH
2AAH
555H
xx55H
55H
555H
2AAH
xx90H
90H
01H
01H
2258H
B
D6H
T
Algorithm
selection (byte)
58H
B
Program (word)
Program (byte)
4
4
555H
2AAH
xxAAH
AAH
2AAH
555H
xx55H
55H
555H
2AAH
xxA0H
A0H
PA
PA
PD
PD
Chip erase
(word)
6
6
6
6
1
1
1
1
555H
2AAH
555H
2AAH
xxAAH
AAH
2AAH
555H
2AAH
555H
xx55H
55H
555H
2AAH
555H
2AAH
xx80H
80H
555H
2AAH
555H
2AAH
xxAAH
AAH
2AAH
555H
2AAH
555H
xx55H
55H
555H
2AAH
SA
xx10H
10H
Chip erase
(byte)
Sector erase
(word)
xxAAH
AAH
xx55H
55H
xx80H
80H
xxAAH
AAH
xx55H
55H
xx30H
30H
Sector erase
(byte)
SA
Sector-erase
suspend (word)
XXXXH xxB0H Erase suspend valid during sector-erase operation
XXX B0H Erase suspend valid during sector-erase operation
XXXXH xx30H Erase resume valid only after erase-suspend operation
XXX 30H Erase resume valid only after erase-suspend operation
Sector-erase
suspend (byte)
Sector-erase
resume (word)
Sector-erase
resume (byte)
LEGEND:
RA
PA
SA
=
=
=
Address of the location to be read
Address of the location to be programmed
Address of the sector to be erased
Addresses A12–A18 select 1 to 19 sectors.
Data to be read at selected address location
Data to be programmed at selected address location
RD
PD
=
=
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read/reset command
The read or reset mode is activated by writing either of the two read/reset command sequences into the
command register. The device remains in this mode until another valid command sequence is input in the
command register. Memory data is available in the read mode and can be read with standard microprocessor
read-cycle timing.
On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and
memory data is available.
algorithm-selection command
The algorithm-selection command allows access to a binary code that matches the device with the proper
programming and erase command operations. After writing the three-bus-cycle command sequence, the first
byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read
fromaddressXX01h(seeTable 6). This mode remains in effectuntilanothervalidcommandsequenceiswritten
to the device.
program command
Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the
program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the
device. The addresses are latched on the falling edge of WE while the data is latched on the rising edge of WE
in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming
function automatically provides needed voltage and timing to program and verify the cell margin. Any further
commands written to the device during the program operation are ignored.
Programming can be performed at any address location in any sequence. When erased, all bits are in a
logic-high state. Logic lows are programmed into the device. Only an erase operation can change bits from logic
lows to logic highs. Attempting to program a 1 into a bit that has been programmed previously to a 0 causes
the internal-pulse counter to exceed the pulse-count limit, which sets the exceed-time-limit indicator (DQ5) to
a logic-high state. The automatic-programming operation is complete when the data on DQ7 is equivalent to
the data written to bit DQ5, at which time the device returns to the read mode and addresses are no longer
latched. Figure 9 shows a flowchart of the typical device-programming operation.
chip-erase command
Chip erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the erase-setup
state. The next two bus cycles unlock the erase mode. The sixth bus cycle loads the chip-erase command. This
command sequence is required to ensure that the memory contents are not erased accidentally. The rising edge
of WE starts the chip-erase operation. Any further commands written to the device during the chip-erase
operation are ignored.
The embedded chip-erase function automatically provides voltage and timing needed to program and to verify
all the memory cells prior to electrical erase. It then erases and verifies the cell margin automatically without
programming the memory cells prior to erase.
Figure 12 shows a flowchart of the typical chip-erase operation.
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sector-erase command
Sector-erase is a six-bus-cycle command sequence. The first three bus cycles put the device into the
erase-setup state. The next two bus cycles unlock the erase mode and then the sixth bus cycle loads the
sector-erase command and the sector-address location to be erased. Any address location within the desired
sector can be used. The addresses are latched on the falling edge of WE and the sector-erase command (30h)
is latched on the rising edge of WE in the sixth bus cycle. After a delay of 80 µs from the rising edge of WE, the
sector-erase operation begins on the selected sector(s).
Additional sectors can be selected to be erased concurrently during the sector-erase command sequence. For
each additional sector to be selected for erase, another bus cycle is issued. The bus cycle loads the next
sector-address location and the sector-erase command. The time between the end of the previous bus cycle
and the start of the next bus cycle must be less than 100 µs; otherwise, the new sector location is not loaded.
A time delay of 100 µs from the rising edge of the last WE starts the sector-erase operation. If there is a falling
edge of WE within the 100 µs time delay, the timer is reset.
One to nineteen sector-address locations can be loaded in any sequence. The state of the delay timer can be
monitored using the sector-erase delay indicator (DQ3). If DQ3 is at logic low, the time delay has not expired.
See the operation status section for a description.
Any command other than erase suspend (B0h) or sector erase (30h) written to the device during the
sector-erase operation causes the device to exit the sector-erase mode and the contents of the sector(s)
selected for erase are no longer valid. To complete the sector-erase operation, re-issue the sector-erase
command sequence.
Theembeddedsector-erasefunctionautomaticallyprovidesneededvoltageandtimingtoprogramandtoverify
all of the memory cells prior to electrical erase and then erases and verifies the cell margin automatically.
Programming the memory cells prior to erase is not required.
See the operation status section for a full description. Figure 14 shows a flowchart of the typical sector-erase
operation.
erase-suspend command
The erase-suspend command (B0h) allows interruption of a sector-erase operation to read data from unaltered
sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be V or V and the
IL
IH
erase-suspend command (B0h) is latched on the rising edge of WE. Once the sector-erase operation is in
progress, the erase-suspend command requests the internal write-state machine to halt operation at
predetermined breakpoints. The erase-suspend command is valid only during the sector-erase operation and
is invalid during programming and chip-erase operations. The sector-erase delay timer expires immediately if
the erase-suspend command is issued while the delay is active.
After the erase-suspend command is issued, the device takes between 0.1 µs and 15 µs to suspend the
operation. The toggle bit must be monitored to determine when the suspend has been executed. When the
toggle bit stops toggling, data can be read from sectors that are not selected for erase. Reading from a sector
selected for erase can result in invalid data. See the operation status section for a full description.
Once the sector-erase operation is suspended, reading from or programming to a sector that is not being erased
can be performed. This command is applicable only during sector-erase operation. Any other command written
during erase-suspend mode to the suspended sector is ignored.
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erase-resume command
The erase-resume command (30h) restarts a suspended sector-erase operation from the point where it was
halted. Erase resume is a one-bus-cycle command. The addresses can be V or V and the erase-resume
IL
IH
command (30h) is latched on the rising edge of WE. When an erase-suspend/erase-resume command
combination is written, the internal-pulse counter (exceed timing limit) is reset. The erase-resume command
is valid only in the erase-suspend state. After the erase-resume command is executed, the device returns to
the valid sector-erase state and further writes of the erase-resume command are ignored. After the device has
resumed the sector-erase operation, another erase-suspend command can be issued to the device.
operation status
The status of the device during an automatic-programming algorithm, chip-erase, or automatic-erase algorithm
can be determined in three ways:
DQ7: Data polling
DQ6: Toggle bit
RY/BY: Ready/busy bit
status-bit definitions
During operation of the automatic embedded program and erase functions, the status of the device can be
determined by reading the data state of designated outputs. The data-polling bit (DQ7) and toggle bit (DQ6)
require multiple successive reads to observe a change in the state of the designated output. Table 7 defines
the values of the status flags.
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status-bit definitions (continued)
†
Table 7. Operation Status Flags
‡
DEVICE OPERATION
DQ7
DQ7
0
DQ6
DQ5
0
DQ3
0
DQ2
RY/BY
Programming
T
No Tog
§
0
0
1
1
0
0
0
0
1
1
Program/erase in auto-erase
T
0
1
In progress
Erase-sector address
1
No Tog
0
0
T
Erase-suspend mode
Non-erase sector address
D
D
T
T
T
T
D
1
D
0
D
0
D
¶
§
1
Program in erase suspend
Programming
DQ7
DQ7
0
1
0
No Tog
#
Exceeded time limits
Program/erase in auto erase
Program in erase suspend
Programming complete
Sector-/chip-erase complete
1
1
DQ7
D
1
0
No Tog
D
1
D
1
D
1
Successful operation
complete
1
†
T= toggle, D= data, No Tog= No toggle
‡
§
DQ4, DQ1, DQ0 are reserved for future use.
DQ2 can be toggled when the sector address applied is an erasing sector. DQ2 cannot be toggled when the sector address applied is a
non-erasing sector. DQ2 is used to determine which sectors are erasing and which are not.
¶
#
Status flags apply when outputs are read from the address of a non-erase-suspend operation.
If DQ5 is high (exceeded timing limits), successive reads from a problem sector causes DQ2 to toggle.
data-polling (DQ7)
The data-polling-status function outputs the complement of the data latched into the DQ7 data register while
the write-state machine (WSM) is engaged in a program or erase operation. Data bit DQ7 changes from
complement to true to indicate the end of an operation. Data-polling is available only during programming,
chip-erase, sector-erase, and sector-erase-timing delay. Data-polling is valid after the rising edge of WE in the
last bus cycle of the command sequence loaded into the command register. Figure 16 shows a flowchart for
data-polling.
During a program operation, reading DQ7 outputs the complement of the DQ7 data to be programmed at the
selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the
program-data register. During the erase operations, reading DQ7 outputs a logic low. Upon completion, reading
DQ7 outputs a logic high. Also, data-polling must be performed at a sector address that is within a sector that
is being erased. Otherwise, the status is invalid. When using data-polling, the address should remain stable
throughout the operation.
During a data-polling read, while OE is logic low, data bit DQ7 can change asynchronously. Depending on the
read timing, the system can read valid data on DQ7, while other DQ pins are still invalid. A subsequent read
of the device is valid. See Figure 17 for the data-polling timing diagram.
toggle bit (DQ6)
The toggle-bit status function outputs data on DQ6, which toggles between logic high and logic low while the
WSM is engaged in a program or erase operation. When DQ6 stops toggling after two consecutive reads to the
sameaddress, theoperationiscomplete. Thetogglebitisavailableonlyduringprogramming, chiperase, sector
erase, and sector-erase-timing delay. Toggle-bit data is valid after the rising edge of WE in the last bus cycle
of the command sequence loaded into the command register. Figure 18 shows a flowchart of the toggle-bit
status-read algorithm. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid
and a subsequent read of the device is valid. See Figure 19 for the toggle-bit timing diagram.
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exceed time limit (DQ5)
Program and erase operations use an internal-pulse counter to limit the number of pulses applied. If the
pulse-count limit is exceeded, DQ5 is set to a logic-high data state. This indicates that the program or erase
operation has failed. DQ7 does not change from complemented data to true data and DQ6 does not stop
toggling when read. To continue operation, the device must be reset.
The exceed-time-limit condition occurs when attempting to program a logic-high state into a bit that has been
programmed previously to a logic low. Only an erase operation can change bits from logic low to logic high. After
reset, the device is functional and can be erased and reprogrammed.
sector-load-timer (DQ3)
The sector-load-timer status bit, DQ3, is used to determine whether the time to load additional sector addresses
has expired. After completion of a sector-erase command sequence, DQ3 remains at a logic low for 100 µs.
This indicates that another sector-erase command sequence can be issued. If DQ3 is at a logic high, it indicates
that the delay has expired and attempts to issue additional sector-erase commands are ignored. See the
sector-erase command section for a description.
The data-polling and toggle bit are valid during the 100-µs time delay and can be used to determine if a valid
sector-erase command has been issued. To ensure additional sector-erase commands have been accepted,
the status of DQ3 should be read before and after each additional sector-erase command. If DQ3 is at a logic
low on both reads, the additional sector-erase command was accepted.
toggle bit 2 (DQ2)
The state of DQ2 determines whether the device is in algorithmic-erase mode or erase-suspend mode. DQ2
toggles if successive reads are issued to the erasing or erase-suspended sector, assuming in case of the latter
that the device is in erase-suspend-read mode. It also toggles when DQ5 becomes a logic high due to the
timer-exceed limit, and reads are issued to the failed sector. DQ2 does not toggle in any other sector due to DQ5
failure. When the device is in erase-suspend-program mode, successive reads from the non-erase-suspended
sector causes a logic high on DQ2.
ready/busy bit (RY/BY)
The RY/BY bit indicates when the device can accept new commands after performing algorithmic operations.
If the RY/BY (open-drain output) bit is low, the device is busy with either a program or erase operation and does
not accept any other commands except for erase suspend. While it is in the erase-suspend mode, RY/BY
remains high. In program mode, the RY/BY bit is valid (logic low) after the fourth WE pulse. In erase mode, it
is valid after the sixth WE pulse. After a delay period, t
waveform.
, RY/BY becomes valid. See Figure 28 for the timing
busy
Since the RY/BY bit is an open-drain output, several such bits can be combined in parallel with a pullup resistor
to V
.
CC
hardware-reset bit (RESET)
When the RESET pin is driven to a logic low, it forces the device out of the currently active mode and into a reset
state. It also avoids bus contention by placing the outputs into the high-impedance state for the duration of the
RESET pulse.
During program or erase operation, if RESET is asserted to logic low, the RY/BY bit remains at logic low until
the reset operation is complete. Since this can take from 1 µs to 20 µs, the RY/BY bit can be used to sense reset
completion or the user can allow a maximum of 20 µs. If RESET is asserted during read mode, then the reset
operation is complete within 500 ns. See Figure 1 and Figure 2 for timing specifications.
The RESET pin also can be used to drive the device into deep power-down (standby) mode by applying
V
± 0.3 V to it. I
reads <1 µA typical, and 5 µA maximum for CMOS inputs. Standby mode can be entered
SS
CC4
anytime, regardless of the condition of CE.
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hardware-reset bit (RESET) (continued)
Asserting RESET during program or erase can leave erroneous data in the address locations. These locations
need to be updated after the device resumes normal operations. A minimum of 50 ns must be allowed after
RESET goes high before a valid read can take place.
t
= 500 ns
RL
RESET
RY/BY
20 µs max
Figure 1. Device Reset During a Program or Erase Operation
t
= 500 ns
RL
RESET
RY/BY
0 V
Figure 2. Device Reset During Read Mode
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word-/byte-mode configuration
The BYTE pin is used to set the device configuration. If BYTE is at a logic 1, the device is in word mode with
all data outputs valid and the DQ15/A output representing DQ15. Similarly, if BYTE is at a logic 0, the device
–1
is in byte mode with only DQ0–DQ7 valid. The remaining outputs are in high-impedance mode and DQ15/A
–1
is used as an input for the least significant bit (A1) address function. See Figure 3 and Figure 4 for timing
specifications.
CE
OE
t
ELFH
BYTE
DQ8–DQ14
DQ8–DQ14
DQ8–DQ14
t
FHQV
DQ15/A–1
A–1
DQ15
Figure 3. Word-Mode Configuration
CE
OE
t
ELFL
BYTE
DQ8–DQ14
DQ15/A–1
DQ8–DQ14
DQ8–DQ14
A–1
t
FLQV
DQ15
Figure 4. Byte-Mode Configuration
temporary hardware-sector unprotect feature
Thisfeaturetemporarilyenablesbothprogramminganderaseoperationsonanycombinationofonetonineteen
sectors that were previously protected. The unprotect feature is enabled using high voltage V (11.5 V to
ID
12.5 V) on the RESET pin, using standard command sequences.
Normally, the device is delivered with all sectors unprotected.
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sector-protect programming
The sector-protect programming mode is activated when A6, A0, and CE are at V , and address pin A9 and
IL
control pin OE are forced to V . Address pin A1 is set to V .The sector-select address pins A12–A18 are used
ID
IH
to select the sector to be protected. Address pins A0–A11 and I/O pins must be stable and can be either V or
IL
V . Once the addresses are stable, WE is pulsed low for 100 µs, causing programming to begin on the falling
IH
edge of WE and to terminate on the rising edge of WE. Figure 20 is a flowchart of the sector-protect algorithm
and Figure 21 shows a timing diagram of the sector-protect operation.
Commands to program or erase a protected sector do not change the data contained in the sector. Attempts
to program and erase a protected sector cause the data-polling bit (DQ7) and the toggle bit (DQ6) to operate
from 2 s to 100 s and then return to valid data.
sector-protect verify
Verification of the sector-protection programming is activated when WE = V , OE = V , CE = V , and address
IH
IL
IL
pin A9 = V . Address pins A0 and A6 are set to V , and A1 is set to V . The sector-address pins A12–A18
ID
IL
IH
select the sector that is to be verified. The other addresses can be V or V . If the sector that was selected
IH
IL
is protected, the DQs output 01h. If the sector is not protected, the DQs output 00h.
Sector-protect verify can also be read using the algorithm-selection command. After issuing the three-bus-cycle
command sequence, the sector-protection status can be read on DQ0. Set address pins
A0 = V , A1 = V , and A6 = V , and then the sector address pins A12–A18 select the sector to be verified.
IL
IH
IL
The remaining addresses are set to V . If the sector selected is protected, DQ0 outputs a logic-high state. If
IL
the sector selected is not protected, DQ0 outputs a logic-low state. This mode remains in effect until another
valid command sequence is written to the device. Figure 20 is a flowchart of the sector-protect algorithm and
Figure 21 shows a timing diagram of the sector-protect operation.
sector unprotect
Prior to sector unprotect, all sectors must be protected using the sector-protect programming mode. The sector
unprotect is activated when address pin A9 and control pin OE are forced to V . Address pins A1 and A6 are
ID
set to V while CE and A0 are set to V . The sector-select address pins A12–A18 can be V or V . All sectors
IH
IL
IL
IH
are unprotected in parallel and once the inputs are stable, WE is pulsed low for 10 ms, causing the unprotect
operation to begin on the falling edge of WE and to terminate on the rising edge of WE. Figure 22 is a flowchart
of the sector-unprotect algorithm and Figure 23 shows a timing diagram of the sector-unprotect operation.
sector-unprotect verify
Verification of the sector unprotect is accomplished when WE = V , OE = V , CE =V , and address pin
IH
IL
IL
A9 = V , and then select the sector to be verified. Address pins A1 and A6 are set to V , and A0 is set to V .
ID
IH
IL
The other addresses can be V or V . If the sector selected is protected, the DQs output 01h. If the sector is
IH
IL
not protected, the DQs output 00h. Sector unprotect can also be read using the algorithm-selection command.
low V write lockout
CC
Duringpower-upandpower-downoperations,writecyclesarelockedoutforV lessthanV
.IfV <V
,
CC
LKO
CC
LKO
the command input is disabled and the device is reset to the read mode. On power up, if CE = V , WE = V ,
IL
IL
andOE=V , thedevicedoesnotacceptcommandsontherisingedgeofWE. Thedeviceautomaticallypowers
IH
up in the read mode.
glitching
Pulses of less than 5 ns (typical) on OE, WE, or CE do not issue a write cycle.
power supply considerations
Eachdeviceshouldhavea0.1-µFceramiccapacitorconnectedbetweenV andV tosuppresscircuitnoise.
CC
SS
Printed circuit traces to V
should be appropriate to handle the current demand and minimize inductance.
CC
21
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 7 V
CC
Input voltage range: All inputs except A9, CE, OE (see Note 2) . . . . . . . . . . . . . . . . . . . . –0.6 V to V
+ 1 V
CC
A9, CE, OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 13.5 V
Output voltage range (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to V + 1 V
CC
Ambient temperature range during read/erase/program, T
A
(L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
(E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
(Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to V
.
SS
2. The voltage on any input pin can undershoot to –2 V for periods less than 20 ns (see Figure 6).
3. The voltage on any input and output pin can overshoot to 7 V for periods less than 20 ns (see Figure 7).
recommended operating conditions
MIN
MAX
UNIT
V
V
Supply voltage
4.5
2
5.5
V
CC
TTL
V
+0.5
CC
High-level dc input voltage
V
V
IH
CMOS
TTL
0.7 V
* CC
V
+0.5
CC
–0.5
–0.5
11.5
3.2
0.8
V
IL
Low-level dc input voltage
CMOS
0.8
12.5
4.2
V
V
Algorithm-selection and sector-protect input voltage
V
V
ID
Low V
lock-out voltage
CC
LKO
L version
E version
Q version
0
–40
–40
70
85
T
A
Ambient temperature
°C
125
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
electrical characteristics over recommended ranges of supply voltage and ambient temperature
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
TTL-input level
V
V
V
V
V
V
= V
= V
= V
= V
= V
MIN,
MIN,
MIN,
MIN,
MAX,
I
I
I
I
= –2.5 mA
= – 100 µA
= – 2.5 mA
= 5.8 mA
2.4 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
OH
OH
OH
OL
V
V
High-level output voltage
CMOS-input level
CMOS-input level
V
–0.4
V
OH
CC
0.85*V
CC
Low-level output voltage
Input current (leakage)
0.45
±1
±1
35
1
V
OL
I
I
I
V
= V to V
SS CC
µA
µA
µA
mA
µA
I
IN
Output current (leakage)
High-voltage current (standby)
= V
to V , CE = V
CC IH
O
O
SS
A9 or CE or OE = V MAX
ID
ID
TTL-input level
CE = V , V
IH CC
= V
MAX
CC
I
V
supply current (standby)
CC1
CC2
CC
CC
CMOS-input level CE = V
± 0.2,
V
CC
= V MAX
CC
100
40
50
60
CC
Byte
V
supply current
I
mA
CE = V , OE = V
IL
IH
(see Note 4 and Note 7)
Word
I
I
I
V
supply current (see Note 5)
CE = V , OE = V
IL
mA
µA
µA
CC3
CC4
CC5
CC
CC
IH
V
= V
MAX,
± 0.3 V
CC
CC
SS
± 0.3 V, V = V ± 0.3 V
SS
V
supply current (standby during reset)
5
RESET = V
Automatic sleep mode (see Note 6 and Note 7)
V
IH
= V
100
CC
IL
NOTES: 4. I
current in the read mode, switching at 6 MHz
current while erase or program operation is in progress
CC
CC
5.
I
6. Automatic sleep mode is entered when addresses remain stable for 300 ns.
7. = 0 mA
I
OUT
capacitance over recommended ranges of supply voltage and ambient temperature
PARAMETER
Input capacitance (All inputs except A9, CE, OE)
Input capacitance (A9, CE, OE)
Output capacitance
TEST CONDITIONS
MIN
MAX
UNIT
pF
C
C
C
V = 0 V,
f = 1 MHz
f = 1 MHz
f = 1 MHz
7.5
9
i1
i2
o
I
V = 0 V,
pF
I
V
= 0 V,
12
pF
O
23
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TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
I
OL
0.5 mA
Output
Under
Test
1.5 V
C
= 30 pF
L
(see Note A and Note B)
I
– 0.5 mA
OH
2.4 V
2 V
0.8 V
0.45 V
NOTES: A.
C includes probe and fixture capacitance.
L
B. The ac testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements are made
at 2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-µF ceramic
capacitor connected between V
CC
and V
as closely as possible to the device pins.
SS
Figure 5. AC Test Output Load Circuit
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 6. Maximum Negative Overshoot Waveform
20 ns
V
CC
+ 2.0 V
V
CC
+ 0.5 V
2.0 V
20 ns
20 ns
Figure 7. Maximum Positive Overshoot Waveform
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
switching characteristics over recommended ranges of supply voltage and ambient temperature,
read-only operation
’29F800-80
’29F800-90
’29F800-100
’29F800-120
ALTERNATE
SYMBOL
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
Cycle time, read
t
80
80
80
40
30
30
0
90
90
90
45
30
30
0
100
100
100
50
30
30
0
120
120
120
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
c(R)
AVAV
Access time, address
t
AVQV
a(A)
Access time, CE
t
a(E)
ELQV
GLQV
EHQZ
GHQZ
Access time, OE
t
t
a(G)
Disable time, CE to high impedance
Disable time, OE to high impedance
Enable time, CE to low impedance
Enable time, OE to low impedance
dis(E)
dis(G)
en(E)
en(G)
t
t
ELQX
t
0
0
0
0
GLQX
Hold time, output from address CE
or OE change
t
t
0
0
0
0
ns
h(D)
AXQX
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PRODUCT PREVIEW
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE
’29F800-80
’29F800-90
’29F800-100
’29F800-120
ALT
SYMBOL
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP MAX
MIN
TYP
MAX
MIN
TYP MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
80
0
90
0
100
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
c(W)
AVAV
Setup time, address
t
su(A)
h(A)
AVWL
Hold time, address
t
45
45
0
50
50
0
50
50
0
65
65
0
WLAX
Setup time, data
t
t
su(D)
h(D)
DVWH
Hold time, data valid after WE high
Setup time, CE
WHDX
t
0
0
0
0
su(E)
h(E)
ELWL
Hold time, CE
t
0
0
0
0
WHEH
Pulse duration, WE low
Pulse duration, WE high
Recovery time, read before write
Hold time, OE read
t
45
20
0
50
30
0
50
30
0
65
35
0
w(WL)
w(WH)
rec(R)
WLWH1
t
WHWL
t
GHWL
t
0
0
0
0
WHGL1
WHGL2
Hold time, OE toggle, data
t
10
50
10
50
10
50
10
50
Setup time, V
CC
t
VCEL
Transition time, V
(see Note 8 and Note 9)
ID
t
4
4
4
4
µs
HVT
Pulse duration, WE low (see Note 8)
Pulse duration, WE low (see Note 9)
t
t
100
10
100
10
100
10
100
10
µs
WLWH2
ms
WLWH3
Setup time, CE VID to WE
(see Note 9)
t
4
4
4
4
4
4
4
4
µs
µs
EHVWL
Setup time, OE V to WE
ID
(see Notes 8 and 9)
t
GHVWL
Byte
8
8
8
8
µs
µs
ns
ns
ns
µs
µs
ns
ns
Cycle time, programming
operation
t
t
WHWH1
c(W)PR
Word
14
14
14
14
Write recovery time from RY/BY
RESET low time
t
0
500
50
20
5
0
500
50
20
5
0
500
50
20
5
0
500
50
20
5
RB
t
RL
RESET high time before read
RESET to power-down time
RESET to CE/WE low
t
RH
t
t
RPD
RPD
Program/erase valid to RY/BY delay
CE to BYTE switching low or high
t
90
5
90
5
90
5
90
5
BUSY
/t
t
ELFL ELFH
NOTES: 8. Sector-protect timing
9. Sector-unprotect timing
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by WE
(continued)
’29F800-80
MIN TYP MAX
’29F800-90
MIN TYP MAX
’29F800-100
MIN TYP MAX
’29F800-120
MIN TYP MAX
ALT
SYMBOL
PARAMETER
UNIT
BYTE switching low to output 3-state
BYTE switching high to output active
Cycle time, sector-erase operation
Cycle time, chip-erase operation
t
30
80
30
90
40
40
ns
ns
s
FLQZ
t
100
120
FHQV
t
t
t
1
6
1
6
1
6
1
6
c(W)ER
WHWH2
50
50
50
50
s
WHWH3
PRODUCT PREVIEW
PRODUCT PREVIEW
switching characteristics over recommended ranges of supply voltage and ambient temperature, controlled by CE
’29F800-80
’29F800-90
’29F800-100
’29F800-120
ALTERNATE
SYMBOL
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP
MAX
t
t
t
t
t
t
t
t
t
t
Cycle time, write
t
80
0
90
0
100
0
120
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
s
c(W)
AVAV
Setup time, address
Hold time, address
Setup time, data
t
t
su(A)
h(A)
AVE
L
45
45
0
50
50
0
50
50
0
65
65
0
ELAX
t
t
su(D)
h(D)
DVEH
EHDX
Hold time, data
Setup time, WE
t
0
0
0
0
su(W)
h(W)
w(EL)
w(EH)
rec(R)
WLEL
Hold time, WE
t
0
0
0
0
EHWH
Pulse duration, CE low
Pulse duration, CE high
Recovery time, read before write
Setup time, OE
t
45
20
0
50
30
0
50
30
0
65
35
0
ELEH1
t
EHEL
t
GHEL
t
0
0
0
0
GLEL
t
Hold time, OE read
Hold time, OE toggle, data
t
t
0
0
0
0
h(C)
EHGL1
10
10
10
10
EHGL2
Byte
Word
8
14
1
8
14
1
8
14
1
8
14
1
Programming operation
t
EHEH1
Cycle time, sector-erase operation
Cycle time, chip-erase operation
BYTE switching low to output 3-state
t
t
EHEH2
6
50
30
6
50
30
6
50
40
6
50
40
s
EHEH3
t
ns
FLQZ
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
†
erase and program performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Excludes 00H programming prior to
erasure
‡
1
§
15
Sector-erase time
s
Program word time
Program byte time
Excludes system-level overhead
Excludes system-level overhead
Excludes system-level overhead
9
9
11
9
5200
µs
µs
§
§
3600
‡
6
Chip-programming time
Erase/program cycles
50
s
100000 1000000
cycles
†
The internal algorithms allow for 2.5-ms byte-program time. DQ5 = 1 only after a byte takes the theoretical maximum time to program. A minimal
number of bytes can require signficantly more programming pulses than the typical byte. The majority of the bytes program within one or two
pulses. This is demonstrated by the typical and maximum programming time listed above.
‡
§
25°C, 5-V V , 100000 cycles, typical pattern
Under worst-case conditions: 90°C, 5-V V , 100000 cycles
CC
CC
latchup characteristics (see Note 10)
PARAMETER
MIN
– 1
MAX
UNIT
V
Input voltage with respect to V
Input voltage with respect to V
Current
on all pins except I/O pins (including A9 and OE)
on all I/O pins
13
SS
– 1
V
CC
+ 1
V
SS
– 100
100
mA
NOTE 10: Includes all pins except V
CC
test conditions: V
=5 V, one pin at a time
CC
pin capacitance, all packages (see Note 11)
PARAMETER
TEST CONDITIONS
= 0
TYP
6
MAX
UNIT
pF
C
C
C
Input capacitance
V
V
V
7.5
12
10
IN
IN
Output capacitance
Control pin capacitance
= 0
8.5
8
pF
OUT
IN2
OUT
pF
IN = 0
NOTE 11: Test conditions: T = 25°C, f = 1 MHz
A
data retention
PARAMETER
TEST CONDITIONS
MIN
10
MAX
UNIT
150°C
125°C
Minimum pattern data retention time
Years
20
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
read operation
t
AVAV
Valid Addresses
Addresses
t
AVQV
CE
OE
t
EHQZ
t
ELQV
t
GHQZ
t
GLQV
t
WE
DQ
GLQX
t
AXQX
t
ELQX
Valid Data
Figure 8. AC Waveform for Read Operation
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
write operation
Start
Write Bus Cycle
2AAH/AAH or
555H/XXAAH
Write Bus Cycle
555H/55H or
2AAH/XX55H
Write Bus Cycle
2AAH/A0H or
555H/XXA0H
Write Bus Cycle
Program Address/Program Data
Poll Device Status
No
Operation
Complete
?
Yes
Last
Address
?
No
Next Address
Yes
End
Figure 9. Program Algorithm
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
write operation (continued)
t
AVAV
555H
2AAH
555H
PA
PA
Addresses
t
WLAX
t
AVWL
CE
OE
t
ELWL
t
WHEH
t
WHDX
t
GHWL
t
WHWL
t
WLWH1
WE
DQ
t
WHWH1
t
DVWH
xxAAH
xx55H
xxA0H
PD
DQ7
DOUT
NOTES: A. PA = Address to be programmed
B. PD = Data to be programmed
C. DQ7 = Complement of data written to DQ7
D. Timing diagram shown is for word-mode operation.
Figure 10. AC Waveform for Program Operation
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
write operation (continued)
t
AVAV
555H
2AAH
555H
PA
PA
Addresses
t
AVEL
t
ELAX
t
ELEH
CE
OE
WE
DQ
t
t
EHEL
GHEL
t
DVEH
t
WLEL
t
EHWH
t
WHWH1
t
EHDX
xxAAH
xx55H
xxA0H
PD
DQ7
DOUT
NOTES: A. PA=Address to be programmed
B. PD Data to be programmed
C. DQ7= Complement of data written to DQ7
D. Timing diagram shown is for word-mode operation.
=
Figure 11. Alternate CE-Controlled Write Operation
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
chip-erase operation
Start
Write Bus Cycle
2AAH/AAH or
555H/XXAAH
Write Bus Cycle
555H/55H or
2AAH/XX55H
Write Bus Cycle
2AAH/80H or
555H/XX80H
Write Bus Cycle
2AAH/AAH or
555H/XXAAH
Write Bus Cycle
555H/55H or
2AAH/XX55H
Write Bus Cycle
2AAH/10H or
555H/XX10H
Poll Device Status
No
Operation
Complete
?
Yes
End
Figure 12. Chip-Erase Algorithm
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
chip-erase operation (continued)
t
AVAV
555H
555H
2AAH
WLAX
555H
VA
Addresses
t
t
AVWL
CE
OE
WE
DQ
t
ELWL
t
WHEH
t
WHDX
t
GHWL
t
WHWL
t
WLWH1
t
WHWH3
t
DVWH
xx80H
xxAAH
xx55H
xx10H
DQ7=0
DOUT=FFH
NOTES: A. VA = any valid address
B. Figure details the last four bus cycles in a six-bus-cycle operation.
C. Timing diagram shown is for word-mode operation.
Figure 13. AC Waveform for Chip-Erase Operation
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-erase operation
Start
Write Bus Cycle
2AAH/AAH or
555H/XXAAH
Write Bus Cycle
555H/55H or
2AAH/XX55H
Write Bus Cycle
2AAH/80H or
555H/XX80H
Write Bus Cycle
2AAH/AAH or
555H/XXAAH
Write Bus Cycle
555H/55H or
2AAH/XX55H
Write Bus Cycle
Sector Address/
30H (Byte)/xx30H (Word)
No
DQ3 = 0
?
Yes
Load
Additional
Sectors
?
Yes
No
Poll Device Status
Operation
Complete
?
No
Yes
End
Figure 14. Sector-Erase Algorithm
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-erase operation (continued)
t
AVAV
555H
555H
2AAH
SA
SA
Addresses
t
WLAX
t
AVWL
CE
OE
t
ELWL
t
WHEH
t
WHDX
t
GHWL
t
WHWL
t
WLWH1
WE
DQ
t
WHWH2
t
DVWH
xx80H
xxAAH
xx55H
xx30H
DQ7=0
DOUT=FFH
NOTES: A. SA = Sector address to be erased
B. Figure details the last four bus cycles in a six-bus-cycle operation.
C. Timing diagram shown is for word-mode operation.
Figure 15. AC Waveform for Sector-Erase Operation
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
data-polling operation
Start
Read DQ0–DQ7
Addr = VA
Yes
DQ7 =
Data
?
No
No
DQ5 = 1
?
Yes
Read DQ0–DQ7
Addr = VA
DQ7 =
Data
?
Yes
No
Fail
Pass
NOTES: A. Pollingstatus bits DQ7 and DQ5 may change asynchronously.
Read DQ7 after DQ5 changes states.
B. VA
=
=
=
Program address for byte-programming
Selected sector address for sector erase
Any valid address for chip erase
Figure 16. Data-Polling Algorithm
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
data-polling operation (continued)
Addresses
AIN
AIN
AIN
t
AVQV
t
AVQV
t
t
ELQV
t
AXQX
ELQV
CE
OE
t
GLQV
t
GLQV
t
GHQZ
t
WHGL1
WE
t
GHQX
t
WHWH1, 2, or 3
DQ
DIN
DQ7
DQ7
DQ7
DOUT
NOTES: A. DIN
B. DQ7
=
=
=
=
Last command data written to the device
Complement of data written to DQ7
Valid data output
C. DOUT
D. AIN
Valid address for byte-program, sector-erase, or chip-erase operation
Figure 17. AC Waveform for Data-Polling Operation
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
toggle-bit operation
Start
Read DQ0–DQ7
Addr = VA
Read DQ0–DQ7
Addr = VA
No
DQ6 =
Toggle
?
Yes
No
DQ5 = 1
?
Yes
Read DQ0–DQ7
DQ6 =
Toggle
?
No
Yes
Fail
Pass
NOTE A: Polling status bits DQ6 and DQ5 can change
asynchronously. Read DQ6 after DQ5 changes
states.
Figure 18. Toggle-Bit Algorithm
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
toggle-bit operation (continued)
Addresses
AIN
t
t
AVQV
t
ELQV
ELQV
CE
t
GLQV
t
GLQV
OE
t
WHGL2
WE
DQ
t
WHWH1, 2 or 3
DIN
DOUT
DQ6 = STOP
TOGGLE
DQ6 = TOGGLE
DQ6 = TOGGLE
DQ6 = TOGGLE
NOTES: A. DIN
B. DQ6
=
=
=
=
Last command data written to the device
Toggle bit output
Valid data output
C. DOUT
D. AIN
Valid address for byte-program, sector-erase, or chip-erase operation
Figure 19. AC Waveforms for Toggle-Bit Operation
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-protect operation
Start
Select Sector Address
A12–A18
X = 1
OE and A9 = V
CE, A0, and A6 = V
,
IL
ID
,
A1 = V
IH
Apply One 100-µs
Pulse
CE, OE, A0, A6 = V
,
IL
A1 = V
A9 = V
,
IH
X = X+1
ID
Read Data
No
No
X = 25
?
Data = 01H
?
Yes
Yes
Yes
Sector Protect
Failed
Protect
Additional
Sectors
?
No
A9 = V or V
IH
IL
Write Reset Command
End
Figure 20. Sector-Protect Algorithm
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-protect operation (continued)
Sector Address
Sector Address
A18–A12
V
ID
A9
A6
t
AVQV
t
HVT
A1
A0
CE
OE
WE
DQ
V
ID
t
GHVWL
t
HVT
t
HVT
t
WLWH2
t
GLQV
DOUT
NOTE A: DOUT
=
00H if selected sector is not protected,
01H if the sector is protected
Figure 21. AC Waveform for Sector-Protect Operation
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-unprotect operation
Start
Protect All Sectors
X = 1
OE, A9 = V
CE and A0 = V
A6 and A1 = V
,
IL
IH
ID
,
Apply One
10-ms Pulse
CE, OE, A0 = V
,
,
IL
A6 and A1 = V
IH
A9 = V
ID
Select Sector Address
Read Data
X = X+1
No
No
X=1000
?
Next Sector
Address
Data = 00H
?
Yes
Yes
No
Sector Unprotect
Failed
Last
Sector
?
Yes
A9 = V or V
IH
IL
Write Reset Command
End
Figure 22. Sector-Unprotect Algorithm
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
sector-unprotect operation (continued)
Sector Address
A18–A12
V
ID
t
AVQV
A9
A6
t
HVT
A1
A0
CE
OE
WE
DQ
V
ID
t
GHVWL
t
HVT
t
HVT
t
WLWH3
t
GLQV
DOUT
NOTE A: DOUT
=
00H if selected sector is not protected,
01H if the sector is protected
Figure 23. AC Waveform for Sector-Unprotect Operation
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
temporary sector-unprotect operation
Start
RESET = V
(see Note A)
ID
Perform Erase or
Program Operations
RESET = V
IH
Temporary Sector-
Group-Unprotect
Completed (see Note B)
NOTES: A. All protected sectors unprotected
B. All previously protected sectors are protected once again
Figure 24. Temporary Sector-Unprotect Algorithm
12 V
5 V
RESET
CE
WE
Program or Erase Command Sequence
t
VLHT
RY/BY
Figure 25. Temporary Sector-Unprotect Timing Diagram
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
CE
OE
BYTE
t
t
,
ELFL
ELFH
Data Output
(DQ0–DQ7)
Data Output (DQ0–DQ14)
DQ0–DQ14
DQ15 Output
Address Input
DQ15/A
–1
t
FLQZ
Figure 26. BYTE Timing Diagram for Read Operation
CE
The Falling Edge of the Last WE Signal
WE
BYTE
t
SET
(t
)
AS
t
HOLD
(t
)
AH
Figure 27. BYTE Timing Diagram for Write Operation
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
CE
The Rising Edge of the Last WE Signal
WE
Entire Programming or Erase Operations
RY/BY
t
BUSY
Figure 28. RY/BY Timing Diagram During Program/Erase Operations
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
DBJ (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0,45
0,35
M
1,27
0,16
44
23
13,40
13,20
16,10
15,90
0,15 NOM
1
22
28,30
28,10
Gage Plane
0,25
0°–8°
0,95
0,65
Seating Plane
0,10
2,63 MAX
0,50 MIN
4073325/C 09/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS29F800T, TMS29F800B
1048576 BY 8-BIT/524288 BY 16-BIT
FLASH MEMORIES
SMJS835B – MAY 1997 – REVISED OCTOBER 1997
DCD (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
1
48
0.050 (1,27)
A
0.012 (0,30)
0.004 (0,10)
0.008 (0,21)
M
25
24
0.728 (18,50)
0.720 (18,30)
0.795 (20,20)
0.780 (19,80)
0.041 (1,05)
0.037 (0,95)
0.047 (1,20) MAX
0.006 (0,15)
NOM
Seating Plane
0.028 (0,70)
0.020 (0,50)
0.004 (0,10)
0.010 (0,25) NOM
PINS**
40
48
56
DIM
0.402
0.476
0.555
A MAX
A MIN
(10,20) (12,10) (14,10)
0.386
(9,80)
0.469
(11,90) (13,10)
0.516
4073307/B 11/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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