TMS320BC51PQ [TI]
DIGITAL SIGNAL PROCESSORS; 数字信号处理器
| 型号： | TMS320BC51PQ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DIGITAL SIGNAL PROCESSORS |
| 文件： | 总91页 (文件大小：1303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Powerful 16-Bit TMS320C5x CPU
Multiple Phase-Locked Loop (PLL)
Clocking Options (×1, ×2, ×3, ×4, ×5, ×9
Depending on Device)
20-, 25-, 35-, and 50-ns Single-Cycle
Instruction Execution Time for 5-V
Operation
Block Moves for Data/Program
Management
25-, 40-, and 50-ns Single-Cycle Instruction
Execution Time for 3-V Operation
On-Chip Scan-Based Emulation Logic
Boundary Scan
Single-Cycle 16 × 16-Bit Multiply/Add
224K × 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K I/O, and 32K Global)
Five Packaging Options
– 100-Pin Quad Flat Package (PJ Suffix)
– 100-Pin Thin Quad Flat Package
(PZ Suffix)
– 128-Pin Thin Quad Flat Package
(PBK Suffix)
– 132-Pin Quad Flat Package (PQ Suffix)
– 144-Pin Thin Quad Flat Package
(PGE Suffix)
2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access
On-Chip Program ROM
1K, 3K, 6K, 9K × 16-Bit Single-Access
On-Chip Program/Data RAM (SARAM)
1K Dual-Access On-Chip Program/Data
RAM (DARAM)
Low Power Dissipation and Power-Down
Modes:
– 47 mA (2.35 mA/MIP) at 5 V, 40-MHz
Clock (Average)
Full-Duplex Synchronous Serial Port for
Coder/Decoder Interface
Time-Division-Multiplexed (TDM) Serial Port
– 23 mA (1.15 mA/MIP) at 3 V, 40-MHz
Clock (Average)
– 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode)
– 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode)
– 5 µA at 5 V, Clocks Off (IDLE2 Mode)
Hardware or Software Wait-State
Generation Capability
On-Chip Timer for Control Operations
Repeat Instructions for Efficient Use of
Program Space
High-Performance Static CMOS Technology
Buffered Serial Port
Host Port Interface
†
IEEE Standard 1149.1 Test-Access Port
(JTAG)
description
The TMS320C5x generation of the Texas Instruments (TI ) TMS320 digital signal processors (DSPs) is
fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an
earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
‡
the ’C5x devices. They execute up to 50 million instructions per second (MIPS).
The ’C5x devices offer these advantages:
Enhanced TMS320 architectural design for increased performance and versatility
Modular architectural design for fast development of spin-off devices
Advanced integrated-circuit processing technology for increased performance
Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.)
Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation
New static-design techniques for minimizing power consumption and maximizing radiation tolerance
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
†
‡
IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
description (continued)
Table 1 provides a comparison of the devices in the ’C5x generation. It shows the capacity of on-chip RAM and
ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of
package with total pin count.
Table 1. Characteristics of the ’C5x Processors
ON-CHIP MEMORY (16-BIT WORDS)
I/O PORTS
POWER
SUPPLY
(V)
CYCLE
TIME
(ns)
PACKAGE
TYPE
QFP
TMS320
DEVICES
DARAM
SARAM
ROM
DATA +
DATA +
PROG
‡
†
DATA
PROG
SERIAL
PARALLEL
PROG
512
512
512
512
512
512
512
512
512
512
512
512
512
512
§
§
§
§
§
§
TMS320C50
TMS320LC50
TMS320C51
TMS320LC51
TMS320C52
TMS320LC52
TMS320C53
TMS320LC53
TMS320C53S
TMS320LC53S
TMS320LC56
TMS320LC57
TMS320C57S
TMS320LC57S
544
544
544
544
544
544
544
544
544
544
544
544
544
544
9K
9K
1K
1K
–
2K
2K
8K
8K
4K
4K
2
2
2
2
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
64K
5
3.3
5
50/35/25
50/40/25
132 pin
132 pin
50/35/25/20 100/132 pin
3.3
5
50/40/25
50/35/25/20
50/40/25
50/35/25
50/40/25
50/35/25
50/40/25
35/25
100/132 pin
100 pin
100 pin
132 pin
132 pin
100 pin
100 pin
100 pin
128 pin
144 pin
144 pin
¶
1
1
¶
–
3.3
5
§
§
§
§
3K
3K
3K
3K
6K
6K
6K
6K
16K
16K
16K
16K
2
2
3.3
5
¶
2
2
2
2
2
2
¶
#
#
#
#
3.3
3.3
3.3
5
32K
32K
||
64K + HPI
64K + HPI
64K + HPI
35/25
§
||
||
2K
2K
50/35/25
50/35
§
3.3
†
Sixteen of the 64K parallel I/O ports are memory mapped.
QFP = Quad flatpack
ROM boot loader available
TDM serial port not available
Includes auto-buffered serial port (BSP) but TDM serial port not available
HPI = Host port interface
‡
§
¶
#
||
Pinouts for each package are device-specific.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
TMS320C50, TMS320LC50, TMS320C51, TMS320LC51, TMS320C53, TMS320LC53
PQ PACKAGE
(TOP VIEW)
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
NC
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
V
SSD
V
V
DDI
SSD
NC
DDI
IACK
D7
D6
D5
D4
D3
D2
D1
D0
NC
CLKOUT1
XF
HOLDA
TDX
DX
TFSX/TFRM
FSX
TMS
CLKMD2
V
V
DDD
V
V
SSI
DDD
TCK
SSI
TDO
V
V
SSD
V
V
DDC
98
SSD
NC
DDC
97
X1
INT1
INT2
INT3
INT4
NMI
96
X2/CLKIN
CLKIN2
BR
95
94
93
STRB
R/W
PS
92
DR
91
TDR
FSR
CLKR
90
IS
89
DS
88
NC
V
87
V
DDA
SSC
V
86
V
DDA
NC
NC
SSC
85
NC
NC
84
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NOTE: NC = No connect (These pins are reserved.)
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for Devices in the PQ Package
SIGNAL
TYPE
DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15
I/O/Z
I/O/Z
O/Z
16-bit external address bus (MSB: A15, LSB: A0)
16-bit external data bus (MSB: D15, LSB: D0)
Program, data, and I/O space select outputs, respectively
Timing strobe for external cycles and external DMA
Read/write select for external cycles and external DMA
Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input
D0–D15
PS, DS, IS
STRB
I/O/Z
I/O/Z
O/Z
R/W
RD, WE
READY
BR
I
I/O/Z
Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero
Microprocessor/microcomputer mode select. Enables internal ROM
Puts parallel I/F bus in high-impedance state after current cycle
Hold acknowledge. Indicates external bus in hold state
External flag output. Set/cleared through software
I/O branch input. Implements conditional branches
Timer output signal. Indicates output of internal timer
Instruction acquisition signal
RS
I
MP/MC
HOLD
HOLDA
XF
I
I
O/Z
O/Z
I
BIO
TOUT
IAQ
O/Z
O/Z
O/Z
I
IACK
INT1–INT4
NMI
Interrupt acknowledge signal
External interrupt inputs
I
Nonmaskable external interrupt
SERIAL PORT INTERFACE (SPI)
DR
I
O/Z
I
Serial receive-data input
DX
Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
CLKR
CLKX
FSR
FSX
I/O/Z
I
Serial transmit-data clock. Internal or external source
Serial receive-frame-synchronization input
I/O/Z
Serial transmit-frame-synchronization signal. Internal or external source
TDM SERIAL-PORT INTERFACE
TDR
I
O/Z
I
TDM serial receive-data input
TDX
TDM serial transmit-data output. In high-impedance state when not transmitting
TDM serial receive-data clock input
TCLKR
TCLKX
I/O/Z
TDM serial transmit-data clock. Internal or external source
TDM serial receive-frame-synchronization input. In the TDM mode, TFSR/TADD is used to output/
input the address of the port.
TFSR / TADD
I/O/Z
I
TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
TFSX/TFRM becomes TFRM, the TDM frame synchronization.
TFSX /TFRM
LEGEND:
I
= Input
O = Output
Z = High impedance
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for Devices in the PQ Package (Continued)
EMULATION/IEEE STANDARD 1149.1 TEST ACCESS PORT (TAP)
TAP scan data input
TDI
I
TDO
O/Z
TAP scan data output
TMS
I
TAP mode select input
TCK
I
TAP clock input
TRST
EMU0
EMU1/OFF
I
TAP reset (with pulldown resistor). Disables TAP when low
Emulation control 0. Reserved for emulation use
Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL
Oscillator output
I/O/Z
I/O/Z
X1
O
X2/CLKIN
CLKIN2
I
Clock/oscillator input
I
I
Clock input
CLKMD1, CLKMD2
CLKOUT1
Clock-mode select inputs
O/Z
Device system-clock output
POWER SUPPLY CONNECTIONS
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
V
V
V
V
V
V
V
V
S
S
S
S
S
S
S
S
DDA
DDD
DDC
DDI
SSA
SSD
SSC
SSI
LEGEND:
Input
I
=
O = Output
S = Supply
Z = High impedance
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
TMS320LC57
PBK PACKAGE
( TOP VIEW )
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
1
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
HINT
WE
2
HD1
RD
EMU0
3
EMU1/OFF
V
4
HD0
HRDY
SSC
V
5
SSC
6
V
TOUT
BCLKX
CLKX
DDA
7
A15
8
A14
9
V
A13
DDC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A12
BFSR
BCLKR
RS
A11
A10
CLKMD1
READY
HOLD
BIO
V
V
SSA
SSA
V
DDC
TDI
HDS1
HDS2
V
DDC
IAQ
V
TRST
DDI
V
V
V
SSI
SSI
DDI
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
V
MP/MC
D15
D14
D13
D12
D11
D10
D9
D8
V
SSA
DDD
HCS
V
DDD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for the TMS320LC57 in the PBK Package
SIGNAL
TYPE
DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15
I/O/Z
I/O/Z
O/Z
16-bit external address bus (MSB: A15, LSB: A0)
16-bit external data bus (MSB: D15, LSB: D0)
D0–D15
PS, DS, IS
STRB
Program, data, and I/O space select outputs, respectively
Timing strobe for external cycles and external DMA
Read/write select for external cycles and external DMA
Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input
Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero
Microprocessor/microcomputer mode select. Enables internal ROM
Puts parallel I/F bus in high-impedance state after current cycle
Hold acknowledge. Indicates external bus in hold state
External flag output. Set/cleared through software
I/O branch input. Implements conditional branches
Timer output signal. Indicates output of internal timer
Instruction acquisition signal
I/O/Z
I/O/Z
O/Z
R/W
RD, WE
READY
BR
I
I/O/Z
RS
I
MP/MC
HOLD
HOLDA
XF
I
I
O/Z
O/Z
I
BIO
TOUT
IAQ
O/Z
O/Z
I
INT1–INT4
NMI
External interrupt inputs
I
Nonmaskable external interrupt
SERIAL PORT INTERFACE
DR
I
O/Z
I
Serial receive-data input
DX
Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
CLKR
CLKX
FSR
FSX
I/O/Z
I
Serial transmit-data clock. Internal or external source
Serial receive-frame-synchronization input
Serial transmit-frame-synchronization signal. Internal or external source
HOST PORT INTERFACE (HPI)
I/O/Z
HCNTL0
HCNTL1
HINT
I
HPI mode control 1
I
HPI mode control 2
O/Z
Host interrupt
HDS1
I
HPI data strobe 1
HDS2
I
HPI data strobe 2
HR/W
HAS
I
HPI read/write strobe
I
HPI address strobe
HRDY
HCS
O/Z
HPI ready signal
I
HPI chip select
HBIL
I
HPI byte identification input
HD0–HD7
LEGEND:
I/O/Z
HPI data bus
I
= Input
O = Output
Z = High impedance
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for the TMS320LC57 in the PBK Package (Continued)
SIGNAL
TYPE
DESCRIPTION
BUFFERED SERIAL PORT
BSP receive data input
BDR
BDX
I
O/Z
I
BSP transmit data output; in high-impedance state when not transmitting
BSP receive-data clock input
BCLKR
BCLKX
BFSR
I/O/Z
I
BSP transmit-data clock; internal or external source
BSP receive frame-synchronization input
BSP transmit frame-synchronization signal; internal or external source
EMULATION/JTAG INTERFACE
BFSX
I/O/Z
TDI
I
JTAG-test-port scan data input
TDO
O/Z
JTAG-test-port scan data output
TMS
I
JTAG-test-port mode select input
TCK
I
JTAG-port clock input
TRST
EMU0
EMU1/OFF
I
JTAG-port reset (with pull-down resistor). Disables JTAG when low
Emulation control 0. Reserved for emulation use
Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL
Oscillator output
I/O/Z
I/O/Z
X1
O
I
X2/CLKIN
Clock input
CLKMD1, CLKMD2,
CLKMD3
I
Clock-mode select inputs
CLKOUT1
O/Z
Device system-clock output
POWER SUPPLY CONNECTIONS
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
V
V
V
V
V
V
V
V
S
S
S
S
S
S
S
S
DDA
DDD
DDC
DDI
SSA
SSD
SSC
SSI
LEGEND:
Input
I
=
O = Output
S = Supply
Z = High impedance
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
TMS320C51, TMS320LC51, TMS320C52, TMS320LC52, TMS320C53S, TMS320LC53S, TMS320LC56
PZ PACKAGE
(TOP VIEW)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
EMU0
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
WE
RD
V
A15
A14
A13
A12
A11
A10
EMU1/OFF
V
DDA
SSC
TOUT
†
†
†
†
9
RS
READY
HOLD
BIO
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLKMD1
V
SSA
V
SSA
TDI
TRST
V
V
V
DDI
SSI
SSI
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
MP/MC
D15
D14
D13
D12
D11
D10
D9
D8
V
V
SSA
DDD
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTE: NC = No connect (These pins are reserved.)
†
See Table 2 for device-specific pinouts.
Table 2. Device-Specific Pinouts for the PZ Package
‡
’LC56
PIN
’C51, ’LC51
TCLKX
’C52, ’LC52
’C53S, ’LC53S
CLKX2
CLKX1
FSR2
5
V
BCLKX
CLKX
BFSR
BCLKR
DR
SSI
CLKX
§
6
CLKX
7
TFSR/TADD
TCLKR
DR
V
V
SSI
8
CLKR2
DR1
SSI
DR
§
46
47
TDR
V
SSI
DR2
BDR
§
48
49
FSR
FSR
FSR1
FSR
§
CLKR
CLKIN2
FSX
CLKR
CLKIN2
FSX
CLKR1
CLKIN2
FSX1
CLKR
CLKMD3
FSX
83
§
91
92
TFSX/TFRM
DX
V
FSX2
BFSX
DX
SSI
§
93
94
DX
NC
DX1
TDX
DX2
BDX
‡
§
Pin names beginning with “B” indicate signals on the buffered serial port (BSP).
No functional change
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for Devices in the PZ Package
SIGNAL
TYPE
DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15
I/O/Z
I/O/Z
O/Z
16-bit external address bus (MSB: A15, LSB: A0)
16-bit external data bus (MSB: D15, LSB: D0)
Program, data, and I/O space select outputs, respectively
Timing strobe for external cycles and external DMA
Read/write select for external cycles and external DMA
Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input
D0–D15
PS, DS, IS
STRB
I/O/Z
I/O/Z
O/Z
R/W
RD, WE
READY
BR
I
I/O/Z
Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero
RS
I
MP/MC
HOLD
HOLDA
XF
I
Microprocessor/microcomputer mode select. Enables internal ROM
Puts parallel I/F bus in high-impedance state after current cycle
Hold acknowledge. Indicates external bus in hold state
External flag output. Set/cleared through software
I/O branch input. Implements conditional branches
Timer output signal. Indicates output of internal timer
External interrupt inputs
I
O/Z
O/Z
BIO
I
TOUT
INT1–INT4
NMI
O/Z
I
I
Nonmaskable external interrupt
SERIAL PORT INTERFACE
DR, DR1, DR2
I
O/Z
I
Serial receive-data input
DX, DX1, DX2
Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
CLKR, CLKR1, CLKR2
CLKX, CLKX1, CLKX2
FSR, FSR1, FSR2
FSX, FSX1, FSX2
I/O/Z
I
Serial transmit-data clock. Internal or external source
Serial receive-frame-synchronization input
I/O/Z
Serial transmit-frame-synchronization signal. Internal or external source
BUFFERED SERIAL PORT (BSP) (SEE NOTE 1)
BSP receive data input
BDR
I
O/Z
I
BDX
BSP transmit data output; in high-impedance state when not transmitting
BSP receive-data clock input
BCLKR
BCLKX
BFSR
I/O/Z
I
BSP transmit-data clock; internal or external source
BSP receive frame-synchronization input
BFSX
I/O/Z
BSP transmit frame-synchronization signal; internal or external source
LEGEND:
I
= Input
O = Output
Z = High impedance
NOTE 1: ’LC56 devices only
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for Devices in the PZ Package (Continued)
SIGNAL
TYPE
DESCRIPTION
TDM SERIAL PORT INTERFACE
TDM serial receive-data input
TDR
TDX
I
O/Z
I
TDM serial transmit-data output. In high-impedance state when not transmitting
TDM serial receive-data clock input
TCLKR
TCLKX
I/O/Z
TDM serial transmit-data clock. Internal or external source
TDM serial receive-frame-synchronization input. In the TDM mode, TFSR/TADD is used to output/
input the address of the port
TFSR / TADD
TFSX /TFRM
I/O/Z
I
TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
TFSX/TFRM becomes TFRM, the TDM frame sync.
EMULATION/JTAG INTERFACE
JTAG-test-port scan data input
TDI
I
TDO
O/Z
JTAG-test-port scan data output
TMS
I
JTAG-test-port mode select input
TCK
I
JTAG-port clock input
TRST
EMU0
EMU1/OFF
I
JTAG-port reset (with pull-down resistor). Disables JTAG when low
Emulation control 0. Reserved for emulation use
Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL (SEE NOTE 2)
Oscillator output
I/O/Z
I/O/Z
X1
O
I
X2/CLKIN
CLKIN2
Clock/oscillator input (PLL clock input for ’C56)
Clock input (PLL clock input for ’C50, ’C51, ’C52, ’C53, ’C53S)
I
CLKMD1, CLKMD2,
CLKMD3
I
Clock-mode select inputs
CLKOUT1
O/Z
Device system-clock output
POWER SUPPLY CONNECTIONS
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
V
V
V
V
V
V
V
V
S
S
S
S
S
S
S
S
DDA
DDD
DDC
DDI
SSA
SSD
SSC
SSI
LEGEND:
Input
I
=
O = Output
S = Supply
Z = High impedance
NOTE 2: CLKIN2 pin is replaced by CLKMD3 pin on ’LC56 devices.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
TMS320C52, TMS320LC52
PJ PACKAGE
(TOP VIEW)
83 82 81
100 99
97 96 95 94 93 92 91 90 89 88 87 86 85 84
98
D8
1
EMU1/OFF
EMU0
80
V
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDD
V
V
3
SSD
DDC
V
V
4
SSD
D7
DDC
V
5
DDI
D6
D5
D4
D3
D2
D1
D0
V
6
DDI
CLKOUT1
7
XF
8
HOLDA
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DX
V
SSI
TMS
DDD
FSX
V
V
CLKMD2
V
DDD
TCK
SSI
V
SSI
V
V
TDO
SSD
V
SSD
DDC
INT1
INT2
INT3
INT4
NMI
DR
X1
X2/CLKIN
CLKIN2
BR
STRB
R/W
PS
V
SSI
FSR
IS
CLKR
DS
V
V
DDA
SSC
V
WE
SSA
A0
RD
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTE: NC = No connect (These pins are reserved.)
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package
SIGNAL
TYPE
DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15
I/O/Z
I/O/Z
O/Z
16-bit external address bus (MSB: A15, LSB: A0)
16-bit external data bus (MSB: D15, LSB: D0)
D0–D15
PS, DS, IS
STRB
Program, data, and I/O space select outputs, respectively
Timing strobe for external cycles and external DMA
Read/write select for external cycles and external DMA
Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input
I/O/Z
I/O/Z
O/Z
R/W
RD, WE
READY
BR
I
I/O/Z
Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero
Microprocessor/microcomputer mode select. Enables internal ROM
Puts parallel I/F bus in high-impedance state after current cycle
Hold acknowledge. Indicates external bus in hold state
External flag output. Set/cleared through software
I/O branch input. Implements conditional branches
Timer output signal. Indicates output of internal timer
External interrupt inputs
RS
I
MP/MC
HOLD
HOLDA
XF
I
I
O/Z
O/Z
BIO
I
TOUT
INT1–INT4
NMI
O/Z
I
I
Nonmaskable external interrupt
SERIAL PORT INTERFACE
DR
I
O/Z
I
Serial receive-data input
DX
Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
CLKR
CLKX
FSR
FSX
I/O/Z
I
Serial transmit-data clock. Internal or external source
Serial receive-frame-synchronization input
I/O/Z
Serial transmit-frame-synchronization signal. Internal or external source
EMULATION/JTAG INTERFACE
TDI
I
JTAG-test-port scan data input
TDO
O/Z
JTAG-test-port scan data output
TMS
I
JTAG-test-port mode select input
TCK
I
JTAG-port clock input
TRST
I
JTAG-port reset (with pulldown resistor). Disables JTAG when low
Emulation control 0. Reserved for emulation use
Emulation control 1. Puts outputs in high-impedance state when low
EMU0
EMU1/OFF
LEGEND:
I/O/Z
I/O/Z
I
= Input
O = Output
Z = High impedance
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package (Continued)
SIGNAL
TYPE
DESCRIPTION
CLOCK GENERATION AND CONTROL
Oscillator output
Clock/oscillator input
X1
O
X2/CLKIN
I
CLKIN2
I
I
Clock input (PLL clock input for ’C52, ’LC52)
Clock-mode select inputs
CLKMD1, CLKMD2
CLKOUT1
O/Z
Device system-clock output
POWER SUPPLY CONNECTIONS
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
V
V
V
V
V
V
V
V
S
S
S
S
S
S
S
S
DDA
DDD
DDC
DDI
SSA
SSD
SSC
SSI
LEGEND:
Input
I
=
O = Output
S = Supply
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
TMS320C57S, TMS320LC57S
PGE PACKAGE
(TOP VIEW)
HINT
EMU0
NC
1
WE
HD1
RD
HD0
HRDY
108
107
106
105
104
103
102
101
100
99
2
3
EMU1/OFF
4
V
5
SSC
V
V
6
SSC
DDA
TOUT
BCLKX
CLKX
A15
NC
A14
A13
A12
NC
7
8
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DDC
98
BFSR
BCLKR
RS
97
96
A11
A10
CLKMD1
95
READY
HOLD
NC
94
93
V
SSA
92
BIO
V
SSA
91
V
TDI
DDC
90
V
HDS1
HDS2
DDC
89
IAQ
88
TRST
V
DDI
87
V
V
SSI
DDI
86
V
A9
A8
A7
NC
A6
A5
A4
A3
NC
A2
A1
A0
SSI
85
MP/MC
D15
D14
D13
NC
84
83
82
81
80
D12
D11
D10
D9
NC
D8
79
78
77
76
75
74
V
V
HCS
DDD
SSA
73
V
DDD
NOTE: NC = No connect (These pins are reserved.)
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package
SIGNAL
TYPE
DESCRIPTION
PARALLEL INTERFACE BUS
A0–A15
I/O/Z
I/O/Z
O/Z
16-bit external address bus (MSB: A15, LSB: A0)
16-bit external data bus (MSB: D15, LSB: D0)
Program, data, and I/O space select outputs, respectively
Timing strobe for external cycles and external DMA
Read/write select for external cycles and external DMA
Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input
Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero
Microprocessor/microcomputer mode select. Enables internal ROM
Puts parallel I/F bus in high-impedance state after current cycle
Hold acknowledge. Indicates external bus in hold state
External flag output. Set/cleared through software
I/O branch input. Implements conditional branches
Timer output signal. Indicates output of internal timer
Instruction acquisition signal
D0–D15
PS, DS, IS
STRB
I/O/Z
I/O/Z
O/Z
R/W
RD, WE
READY
BR
I
I/O/Z
RS
I
MP/MC
HOLD
HOLDA
XF
I
I
O/Z
O/Z
I
BIO
TOUT
IAQ
O/Z
O/Z
I
INT1–INT4
NMI
External interrupt inputs
I
Nonmaskable external interrupt
SERIAL PORT INTERFACE (SPI)
DR
I
O/Z
I
Serial receive-data input
DX
Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
CLKR
CLKX
FSR
FSX
I/O/Z
I
Serial transmit-data clock. Internal or external source
Serial receive-frame-synchronization input
Serial transmit-frame-synchronization signal. Internal or external source
HOST PORT INTERFACE (HPI)
I/O/Z
HCNTL0
HCNTL1
HINT
I
HPI mode control 1
I
HPI mode control 2
O/Z
Host interrupt
HDS1
I
HPI data strobe 1
HDS2
I
HPI data strobe 2
HR/W
HAS
I
HPI read/write strobe
I
HPI address strobe
HRDY
HCS
O/Z
HPI ready signal
I
HPI chip select
HBIL
I
HPI byte identification input
HD0–HD7
LEGEND:
I/O/Z
HPI data bus
I
= Input
O = Output
Z = High impedance
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Pin Functions for the TMS320C57S, TMS320LC57S in the PGE Package (Continued)
SIGNAL
TYPE
DESCRIPTION
BUFFERED SERIAL PORT
BSP receive data input
BDR
BDX
I
O/Z
I
BSP transmit data output; in high-impedance state when not transmitting
BSP receive-data clock input
BCLKR
BCLKX
BFSR
I/O/Z
I
BSP transmit-data clock; internal or external source
BSP receive frame-synchronization input
BSP transmit frame-synchronization signal; internal or external source
EMULATION/JTAG INTERFACE
BFSX
I/O/Z
TDI
I
JTAG-test-port scan data input
TDO
O/Z
JTAG-test-port scan data output
TMS
I
JTAG-test-port mode select input
TCK
I
JTAG-port clock input
TRST
EMU0
EMU1/OFF
I
JTAG-port reset (with pulldown resistor). Disables JTAG when low
Emulation control 0. Reserved for emulation use
Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL
Oscillator output
I/O/Z
I/O/Z
X1
O
I
X2/CLKIN
PLL clock input
CLKMD1, CLKMD2,
CLKMD3
I
Clock-mode select inputs
CLKOUT1
O/Z
Device system-clock output
POWER SUPPLY CONNECTIONS
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
Supply connection, address-bus output
Supply connection, data-bus output
Supply connection, control output
Supply connection, internal logic
V
V
V
V
V
V
V
V
S
S
S
S
S
S
S
S
DDA
DDD
DDC
DDI
SSA
SSD
SSC
SSI
LEGEND:
Input
I
=
O = Output
S = Supply
Z = High impedance
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
architecture
The ’C5x’s advanced Harvard-type architecture maximizes the processing power by maintaining two separate
memorybusstructures, programanddata, forfull-speedexecution. Instructionssupportdatatransfersbetween
the two spaces. This architecture permits coefficients stored in program memory to be read into the RAM,
eliminating the need for a separate coefficient ROM. The ’C5x architecture also makes available immediate
instructions and subroutines based on computed values. Increased throughput on the ’C5x for many DSP
applications is accomplished using single-cycle multiply/accumulate instructions with a data-move option, up
to eight auxiliary registers with a dedicated arithmetic unit, a parallel logic unit, and faster I/O necessary for
data-intensive signal processing. The architectural design emphasizes overall speed, communication, and
flexibility in processor configuration. Control signals and instructions provide floating-point support,
block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations
as shown in the functional block diagram.
Table 3 explains the symbols that are used in the functional block diagram.
Table 3. Symbols Used in Functional Block Diagram
SYMBOL
ABU
DESCRIPTION
Auto-buffering unit
SYMBOL
IFR
DESCRIPTION
Interrupt-flag register
Interrupt-mask register
ACCB
ACCH
ACCL
ALU
Accumulator buffer
IMR
Accumulator high
INDX
IR
Indirect-addressing-index register
Instruction register
Accumulator low
Arithmetic logic unit
MCS
Microcall stack
ARAU
ARB
Auxiliary-register arithmetic unit
Auxiliary-register pointer buffer
Auxiliary-register compare register
Auxiliary-register pointer
MUX
Multiplexer
PAER
PASR
PC
Block-repeat-address end register
Block-repeat-address start register
Program counter
ARCR
ARP
ARR
Address-receive register (ABU)
Auxiliary registers
PFC
Prefetch counter
AR0–AR7
AXR
PLU
Parallel logic unit
Address-transmit register (ABU)
Receive-buffer-size register (ABU)
Transmit-buffer-size register (ABU)
Block-move-address register
Block-repeat-counter register
Buffered serial port
PMST
PRD
Processor-mode-status register
Timer-period register
BKR
BKX
PREG
RPTC
SARAM
SFL
Product register
BMAR
BRCR
BSP
Repeat-counter register
Single-access RAM
Left shifter
C
Carry bit
SFR
Right shifter
CBER1
CBER2
CBSR1
CBSR2
DARAM
DBMR
DP
Circular buffer 1 end address
Circular buffer 2 end address
Circular buffer 1 start address
Circular buffer 2 start address
Dual-access RAM
SPC
Serial-port interface-control register
Status registers
ST0,ST1
TCSR
TCR
TDM channel-select register
Timer-control register
TDM
Time-division-multiplexed serial port
TDM data transmit register
Timer-count register
Dynamic bit manipulation register
Data memory page pointer
Serial-port data receive register
Serial-port data transmit register
Global memory allocation register
Host port interface
TDXR
TIM
DRR
TRAD
TRCV
TREG0
TREG1
TREG2
TRTA
TSPC
TDM received-address register
TDM data-receive register
Temporary register for multiplication
Temporary register for dynamic shift count
Temporary register used as bit pointer in dynamic-bit test
TDM receive-/transmit-address register
TDM serial-port-control register
DXR
GREG
HPI
HPIAH
HPIAL
HPICH
HPICL
HPI-address register (high bytes)
HPI-address register (low bytes)
HPI-control register (high bytes)
HPI-control register (low bytes)
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
functional block diagram
Program Bus
CLKMD1
CLKMD2
IS
Serial Port 1
DX
SPC
CLKX
DS
16
PFC(16)
FSX
PS
DXR
DR
16
RW
STRB
READY
BR
X1
FSR
DRR
PAER(16)
16
CLKOUT1
X2/CLKIN
CLKIN2/CLKMD3
CLKR
16
16
MUX
†
Serial Port 2
XF
16
16
Compare
DX2
HOLD
HOLDA
IAQ
16
16
16
16
SPC
16
CLKX2
IR(16)
FSX2
MCS(16)
PC(16)
16
PASR(16)
16
BMAR(16)
ST0(16)
DXR
DRR
DR2
BO
RD
FSR2
CLKR2
RS
WE
NMI
IACK
ST1(16)
Address
Stack
PMST(16)
RPTC(16)
IMR(16)
MP/MC
†
TDM
INT(1–4)
Program
’C50
ROM
2K
(8x16)
4
TSPC
’C51
8K
IFR(16)
’C52
4K
TDXR
TRCV
TDX
’C53
16K
32K
32K
GREG(16)
BRCR(16)
TREG1(5)
TREG2(4)
TFRM
TCLKX
TDR
16
16
’C56
16
A15–A0
’C57
16
TCSR(8)
TRTA
TADD
TCLKR
Instruction
16
16
RBIT
Program Bus
TRAD(16)
D15–D0
16
†
BSP
DXR
16
Data Bus
16
16
AXR(11)
BKX(11)
DRR
BDX
16
DFSX
BCLKX
BDR
3
9
7 LSB
16
16 16
16
16
from IR
AR0(16)
AR1(16)
DP(9)
BFSR
BCLKR
DBMR(16)
MUX
AR2(16)
ARR(11)
BKR(11)
16
16
16
ARP(3)
3
AR3(16)
3
9
AR4(16)
16
AR5(16)
MUX
TREG0(16)
Multiplier
ARB(3)
Timer
TCR
AR6(16)
AR7(16)
16
CBSR1(16)
CBSR2(16)
CBER1(16)
CBER2(16)
3
TOUT
SFL(0–16)
MUX
PREG(32)
32
PRD
TIM
16
PLU (16)
SFL (–6, 0, 1, 4)
32
MUX
HD0
32
INDX(16)
†
32
HPI
HD7
ARCR(16)
HCNTL1
HCNTL0
HBIL
SFR(0–16)
HPICL
HPIAL
HPICH
HPIAH
16
MUX
32
HCS
HDS(1–1)
HAS
ARAU(16)
MUX
MUX
HR/W
HRDY
HINT
ALU(32)
16
32
32
Data/Prog
SARAM
32
MUX
’C50
’C51
’C53
’C56
’C57
9K
1K
3K
6K
6K
Data/Prog
DARAM
B0 (512x16)
Data
C
ACCH(16)
ACCL(16)
32
ACCB(32)
DARAM
B2 (32x16)
B1 (512x16)
16
Shifter(0–7)
16
MUX
16
MUX
16
16
16
†
Not available on all devices (see Table 1).
NOTES: A. Signals in shaded text are not available on
100-pin QFP packages.
B. Symbol descriptions appear in Table 3.
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
32-bit ALU/accumulator
The 32-bit ALU and accumulator implement a wide range of arithmetic and logical functions, the majority of
which execute in a single cycle. The ALU is a general-purpose arithmetic/logic unit that operates on 16-bit words
taken from data memory or derived from immediate instructions. In addition to the usual arithmetic instructions,
the ALU can perform Boolean operations, facilitating the bit manipulation ability required of a high-speed
controller. One input to the ALU always is supplied by the accumulator, and the other input can be furnished
from the product register (PREG) of the multiplier, the accumulator buffer (ACCB), or the output of the scaling
shifter [which has been read from data memory or from the accumulator (ACC)]. After the ALU performs the
arithmetic or logical operation, the result is stored in the ACC where additional operations, such as shifting, can
be performed. Data input to the ALU can be scaled by the scaling shifter. The 32-bit ACC is split into two 16-bit
segments for storage in data memory. Shifters at the output of the ACC provide a left shift of 0 to 7 places. This
shift is performed while the data is being transferred to the data bus for storage. The contents of the ACC remain
unchanged. When the postscaling shifter is used on the high word of the ACC (bits 31–16), the most significant
bits (MSBs) are lost and the least significant bits (LSBs) are filled with bits shifted in from the low word (bits
15–0). When the postscaling shifter is used on the low word, the LSBs are filled with zeros.
The ’C5x supports floating-point operations for applications requiring a large dynamic range. By performing left
shifts, the normalization instruction (NORM) is used to normalize fixed-point numbers contained in the ACC.
The four bits of the TREG1 define a variable shift through the scaling shifter for the ADDT/LACT/SUBT
instructions (add to/load to/subtract from ACC with shift specified by TREG1). These instructions are useful
in denormalizing a number (converting from floating point to fixed point). They are also useful for executing an
automatic gain control (AGC) going into a filter.
The single-cycle 1-bit to 16-bit right shift of the ACC efficiently aligns the ACC’s contents. This, coupled with
the32-bittemporarybufferontheACC, enhancestheeffectivenessoftheALUinextended-precisionarithmetic.
The ACCB provides a temporary storage place for a fast save of the ACC. The ACCB also can be used as an
input to the ALU. The minimum or maximum value in a string of numbers is found by comparing the contents
of the ACCB with the contents of the ACC. The minimum or maximum value is placed in both registers, and,
if the condition is met, the carry bit (C) is set to 1. The minimum and maximum functions are executed by the
CRLT and CRGT instructions, respectively.
scaling shifters
The ’C5x provides a scaling shifter that has a 16-bit input connected to the data bus and a 32-bit output
connected to the ALU. This scaling shifter produces a left shift of 0 to 16 bits on the input data. The shift count
is specified by a constant embedded in the instruction word or by the value in TREG1. The LSBs of the output
are filled with zeros; the MSBs may be either filled with zeros or sign extended, depending upon the value of
the sign-extension mode (SXM) bit of status register ST1.
The ’C5x also contains several other shifters that allow it to perform numerical scaling, bit extraction,
extended-precision arithmetic, and overflow prevention. These shifters are connected to the output of the
product register and the ACC.
parallel logic unit
The parallel logic unit (PLU) is a second logic unit, additional to the main ALU, that executes logic operations
on data without affecting the contents of the ACC. The PLU provides the bit-manipulation ability required of a
high-speed controller and simplifies control/status register operations. The PLU provides a direct logic
operation path to data memory space and can set, clear, test, or toggle multiple bits directly in a data memory
location, a control/status register, or any register that is mapped into data memory space.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
16 × 16-bit parallel multiplier
The ’C5x uses a 16 × 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit
product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction,
perform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as
2s-complement numbers, and the result is a 32-bit 2s-complement number.
There are two registers associated with the multiplier: TREG0, a 16-bit temporary register that holds one of the
operands for the multiplier, and PREG, the 32-bit product register that holds the product. Four product shift
modes (PM) are available at the PREG’s output. These shift modes are useful for performing
multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products. The PM field
of status register ST1 specifies the PM shift mode.
The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY). A 4-bit shift is used in conjunction with the MPY instruction with a short
immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by
a 13-bit number. Finally, the output of PREG can, instead, be right-shifted 6 bits to enable the execution of up
to 128 consecutive multiply/accumulates without the possibility of overflow.
The load-TREG0 (LT) instruction normally loads TREG0 to provide one operand (from the data bus), and the
MPY instruction provides the second operand (also from the data bus). A multiplication also can be performed
with a short or long immediate operand by using the MPY instruction with an immediate operand. A product is
obtained every two cycles except when a long immediate operand is used.
Four multiply/accumulate instructions (MAC, MACD, MADD, and MADS as defined in Table 7) fully utilize the
computational bandwidth of the multiplier, allowing both operands to be processed simultaneously. The data
for these operations is transferred to the multiplier during each cycle through the program and data buses. This
facilitates single-cycle multiply/accumulates when used with repeat (RPT and RPTZ) instructions. In these
instructions, the coefficient addresses are generated by the PC, while the data addresses are generated by the
ARAU. This allows the repeated instruction to access the values sequentially from the coefficient table and step
through the data in any of the indirect addressing modes. The RPTZ instruction also clears the accumulator and
the product register to initialize the multiply/accumulate operation.
The MACD and MADD instructions, when repeated, support filter constructs (weighted running averages) so
that as the sum-of-products is executed, the sample data is shifted in memory to make room for the next sample
and to eliminate the oldest sample. Circular addressing with MAC and MADS instructions also can be used to
support filter implementation.
auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The’C5xprovidesaregisterfilecontainingeightauxiliaryregisters(AR0–AR7). Theauxiliaryregistersareused
for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register addressing
allowsplacementofthedatamemoryaddressofaninstructionoperandintooneoftheauxiliaryregisters. These
registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through
7, designated AR0 through AR7, respectively. The auxiliary registers and the ARP can be loaded from data
memory, the ACC, the product register, or by an immediate operand defined in the instruction. The contents of
these registers can be stored in data memory or used as inputs to the central arithmetic logic unit (CALU). These
registers are accessible as memory-mapped locations within the ’C5x data-memory space.
The auxiliary register file (AR0–AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data memory location is being addressed. Indexing can
be performed either by ±1 or by the contents of the INDX register. As a result, accessing tables of information
does not require the CALU for address manipulation; thus, the CALU is free for other operations in parallel.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
memory
The ’C5x implements three separate address spaces for program memory, data memory, and I/O. Each space
accommodates a total of 64K 16-bit words (see Figures 1 through 7). Within the 64K words of data space, the
256 to 32K words at the top of the address range can be defined to be external global memory in increments
of powers of two, as specified by the contents of the global memory allocation register (GREG). Access to global
memory is arbitrated using the global memory bus request (BR) signal.
The ’C5x devices include a considerable amount of on-chip memory to aid in system performance and
integration including ROM, single-access RAM (SARAM), and dual-access RAM (DARAM). The amount and
types of memory available on each device are shown in Table 1.
On the ’C5x, the first 96 (0–5Fh) data-memory locations are allocated for memory-mapped registers. This
memory-mapped register space contains various control and status registers including those for the CPU, serial
port, timer, and software wait-state generators. Additionally, the first 16 I/O port locations are mapped into this
data-memory space, allowing them to be accessed either as data memory using single-word instructions or as
I/O locations with two-word instructions. Two-word instructions allow access to the full 64K words of I/O space.
The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM
programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state
of the MP/MC control input upon resetting the device or by manipulating the MP/MC bit in the PMST status
register after reset. The ROM occupies the lowest block of program memory when enabled. When disabled,
these addresses are located in the device’s external program-memory space.
The ’C5x also has a mask-programmable option that provides security protection for the contents of on-chip
ROM. When this internal option bit is programmed, no externally-originating instruction can access the on-chip
ROM. This feature can be used to provide security for proprietary algorithms.
An optional boot loader is available in the device’s on-chip ROM. This boot loader can be used to transfer a
program automatically from data memory or the serial port to anywhere in program memory. In data memory,
theprogramcanbelocatedonany1K-wordboundaryandcanbeineitherbyte-wideor16-bitwordformat. Once
the code is transferred, the boot loader releases control to the program for execution.
The ’C5x devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM).
The single-access RAM requires a full machine cycle to perform a read or a write; however, this is not one large
RAMblockinwhichonlyoneaccesspercycleisallowed. Itismadeupof2K-wordsize-independentRAMblocks
and each one allows one CPU access per cycle. The CPU can read or write one block while accessing another
block at the same time. All ’C5x processors support multiple accesses to its SARAM in one cycle as long as they
go to different RAM blocks. If the total SARAM size is not a multiple of two, one block is made smaller than 2K
words. With an understanding of this structure, programmers can arrange code and data appropriately to
improve code performance. Table 4 shows the sizes of available SARAM on the applicable ’C5x devices.
Table 4. SARAM Block Sizes
DEVICE
’C50/’LC50
NUMBER OF SARAM BLOCKS
Four 2K blocks and one 1K block
One 1K block
’C51/’LC51
’C53/’C53S /’LC53
’LC56
One 2K block and one 1K block
Three 2K blocks
’C57S/’LC57/’LC57S Three 2K blocks
memory (continued)
The ’C5x dual-access RAM (DARAM) allows writes to, and reads from, the RAM in the same cycle without the
address restrictions of the SARAM. The dual-access RAM is configured in three blocks: block 0 (B0), block 1
(B1), and block 2 (B2). Block 1 is 512 words in data memory and block 2 is 32 words in data memory. Block 0
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
is a 512-word block which can be configured as data or program memory. The CLRC CNF (configure B0 as data
memory) and SETC CNF (configure B0 as program memory) instructions allow dynamic configuration of the
memory maps through software. When using block 0 as program memory, instructions can be downloaded from
external program memory into on-chip RAM and then executed.
When using on-chip RAM, ROM, or high-speed external memory, the ’C5x runs at full speed with no wait states.
The ability of the DARAM to allow two accesses to be performed in one cycle, coupled with the parallel nature
ofthe’C5xarchitecture, enablesthedevicetoperformthreeconcurrentmemoryaccessesinanygivenmachine
cycle. Externally, the READY line can be used to interface the ’C5x to slower, less expensive external memory.
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.
Program
Program
Data
Hex
Hex
Hex
0000
0000
0000
Memory-Mapped
Registers
Interrupts and
Reserved
(external)
Interrupts and
Reserved
(on-chip)
005F
0060
003F
0040
003F
0040
On-Chip
DARAM B2
On-Chip
ROM
External
007F
0080
07FF
0800
07FF
0800
Reserved
00FF
0100
On-Chip DARAM B0
(CNF = 0)
Reserved (CNF = 1)
On-Chip SARAM
(RAM = 1)
On-Chip SARAM
(RAM = 1)
02FF
0300
External
(RAM = 0)
External
(RAM = 0)
On-Chip
DARAM B1
04FF
0500
2BFF
2C00
2BFF
2C00
Reserved
07FF
0800
On-Chip SARAM
(OVLY = 1)
External
External
External (OVLY = 0)
2BFF
2C00
FDFF
FE00
FDFF
FE00 On-Chip DARAM B0
(CNF = 1)
On-Chip DARAM B0
(CNF = 1)
External (CNF = 0)
External
External (CNF = 0)
FFFF
FFFF
FFFF
MP/MC = 1
(microprocessor mode)
MP/MC = 0
(microcomputer mode)
Figure 1. TMS320C50 and TMS320LC50 Memory Map
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Program
Program
Data
Hex
Hex
Hex
0000
0000
0000
Memory-Mapped
Registers
Interrupts and
Reserved
Interrupts and
Reserved
005F
0060
(external)
(on-chip)
003F
0040
003F
0040
On-Chip
DARAM B2
On-Chip
ROM
007F
0080
External
1FFF
2000
1FFF
2000
Reserved
00FF
0100
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
On-Chip SARAM
(RAM = 1)
On-Chip SARAM
(RAM = 1)
02FF
0300
External
(RAM = 0)
External
(RAM = 0)
On-Chip
DARAM B1
04FF
0500
23FF
2400
23FF
2400
Reserved
07FF
0800
On-Chip SARAM
(OVLY = 1)
External
External
External (OVLY = 0)
0BFF
0C00
FDFF
FE00
FDFF
FE00
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
External
FFFF
FFFF
FFFF
MP/MC = 1
(microprocessor mode)
MP/MC = 0
(microcomputer mode)
Figure 2. TMS320C51 and TMS320LC51 Memory Map
Program
Program
Data
Hex
Hex
Hex
0000
0000
0000
Memory-Mapped
Registers
Interrupts and
Reserved
(external)
Interrupts and
Reserved
(on-chip)
005F
0060
003F
0040
003F
0040
On-Chip
DARAM B2
On-Chip
ROM
007F
0080
0FFF
1000
Reserved
00FF
0100
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
02FF
0300
External
On-Chip
DARAM B1
External
04FF
0500
Reserved
External
07FF
0800
FDFF
FE00
FDFF
FE00
On-Chip DARAM
B0 (CNF = 1)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
External (CNF = 0)
FFFF
FFFF
FFFF
MP/MC = 1
(microprocessor mode)
MP/MC = 0
(microcomputer mode)
Figure 3. TMS320C52 and TMS320LC52 Memory Map
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Hex
0000
Program
Hex
0000
Program
Hex
0000
Data
Memory-Mapped
Registers
Interrupts and
Reserved
(external)
Interrupts and
Reserved
(on-chip)
005F
0060
003F
0040
003F
0040
On-Chip
DARAM B2
On-Chip
ROM
External
007F
0080
3FFF
4000
3FFF
4000
Reserved
00FF
0100
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
On-Chip SARAM
(RAM = 1)
On-Chip SARAM
(RAM = 1)
02FF
0300
External
(RAM = 0)
External
(RAM = 0)
On-Chip
DARAM B1
04FF
0500
4BFF
4C00
4BFF
4C00
Reserved
07FF
0800
On-Chip SARAM
(OVLY = 1)
External
External
External (OVLY = 0)
13FF
1400
FDFF
FE00
FDFF
FE00
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
On-Chip DARAM
B0 (CNF = 1)
External (CNF = 0)
External
FFFF
FFFF
FFFF
MP/MC = 1
(microprocessor mode)
MP/MC = 0
(microcomputer mode)
Figure 4. TMS320C53, TMS320C53S, TMS320LC53, and TMS320LC53S Memory Map
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Program
Program
Data
Hex
Hex
0000
Hex
0000
0000
Memory-Mapped
Registers
Interrupts and Reservrd
(external)
Interrupts and Reserved
(on-chip)
005F
0060
007F
0080
On-Chip DARAM B2
Reserved
003F
0040
003F
0040
00FF
0100
External
On-Chip ROM
On-Chip DARAM B0 (CNF = 0)
Reserved (CNF = 1)
7FFF
8000
7FFF
8000
02FF
0300
On-Chip DARAM B1
Reserved
On-Chip SARAM Blk0
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk0
(RAM = 1)
External (RAM = 0)
04FF
0500
87FF
8800
87FF
8800
07FF
0800
On-Chip SARAM Blk0
BSP Block (OVLY = 1)
External (OVLY = 0)
On-Chip SARAM Blk1
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk1
(RAM = 1)
External (RAM = 0)
0FFF
1000
8FFF
9000
8FFF
9000
On-Chip SARAM Blk1
(OVLY = 1)
External (OVLY = 0)
On-Chip SARAM Blk2
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk2
(RAM = 1)
External (RAM = 0)
17FF
1800
On-Chip SARAM Blk2
(OVLY = 1)
External (OVLY = 0)
97FF
9800
97FF
9800
1FFF
2000
External
External
External
FDFF
FE00
FDFF
FE00
On-Chip DARAM B0
(CNF = 1)
On-Chip DARAM B0
(CNF = 1)
External (CNF = 0)
External (CNF = 0)
FFFF
FFFF
FFFF
MP/MC = 1
MP/MC = 0
Figure 5. TMS320LC56 Memory Map
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Program
Program
Data
Hex
0000
Hex
0000
Hex
0000
Memory-Mapped
Registers
Interrupts and Reservrd
(external)
Interrupts and Reserved
(on-chip)
005F
0060
007F
0080
On-Chip DARAM B2
Reserved
003F
0040
003F
0040
00FF
0100
External
On-Chip ROM
On-Chip DARAM (CNF = 0)
Reserved (CNF = 1)
7FFF
8000
7FFF
8000
02FF
0300
On-Chip DARAM B1
On-Chip SARAM Blk0
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk0
(RAM = 1)
External (RAM = 0)
04FF
0500
HPI Control Register
Reserved
0501
07FF
0800
87FF
8800
87FF
8800
On-Chip SARAM Blk0
BSP Block (OVLY = 1)
External (OVLY = 0)
On-Chip SARAM Blk1
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk1
(RAM = 1)
External (RAM = 0)
0FFF
1000
8FFF
9000
8FFF
9000
On-Chip SARAM Blk1
HPI Block (OVLY = 1)
External (OVLY = 0)
On-Chip SARAM Blk2
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk2
(RAM = 1)
External (RAM = 0)
17FF
1800
On-Chip SARAM Blk2
(OVLY = 1)
External (OVLY = 0)
97FF
9800
97FF
9800
1FFF
2000
External
External
External
FDFF
FE00
FDFF
FE00
On-Chip DARAM B0
(CNF = 1)
On-Chip DARAM B0
(CNF = 1)
External (CNF = 0)
External (CNF = 0)
FFFF
FFFF
FFFF
MP/MC = 1
MP/MC = 0
Figure 6. TMS320LC57 Memory Map
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
Program
Program
Data
Hex
0000
Hex
0000
Hex
0000
Memory-Mapped
Registers
Interrupts and Reservrd
(external)
Interrupts and Reserved
(on-chip)
005F
0060
007F
0080
On-Chip DARAM B2
Reserved
003F
0040
003F
0040
07FF
0800
On-Chip ROM
External
00FF
0100
External
On-Chip DARAM (CNF = 0)
Reserved (CNF = 1)
7FFF
8000
7FFF
8000
02FF
0300
On-Chip DARAM B1
HPI Control Register
On-Chip SARAM Blk0
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk0
(RAM = 1)
External (RAM = 0)
04FF
0500
0501
Reserved
87FF
8800
87FF
8800
07FF
0800
On-Chip SARAM Blk0
BSP Block (OVLY = 1)
External (OVLY = 0)
On-Chip SARAM Blk1
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk1
(RAM = 1)
External (RAM = 0)
0FFF
1000
8FFF
9000
8FFF
9000
On-Chip SARAM Blk1
HPI Block (OVLY = 1)
External (OVLY = 0)
On-Chip SARAM Blk2
(RAM = 1)
External (RAM = 0)
On-Chip SARAM Blk2
(RAM = 1)
External (RAM = 0)
17FF
1800
On-Chip SARAM Blk2
(OVLY = 1)
External (OVLY = 0)
97FF
9800
97FF
9800
1FFF
2000
External
External
External
FDFF
FE00
FDFF
FE00
On-Chip DARAM B0
(CNF = 1)
On-Chip DARAM B0
(CNF = 1)
External (CNF = 0)
External (CNF = 0)
FFFF
FFFF
FFFF
MP/MC = 1
MP/MC = 0
Figure 7. TMS320C57S Memory Map
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
interrupts and subroutines
The ’C5x implements four general-purpose interrupts, INT4–INT1, along with reset (RS) and the nonmaskable
interrupt (NMI) which are available for external devices to request the attention of the processor. Internal
interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), and by the software-interrupt
(TRAP, INTR, and NMI) instructions. Interrupts are prioritized with RS having the highest priority, followed by
NMI, and INT4 having the lowest priority. Additionally, any interrupt except RS and NMI can be masked
individually with a dedicated bit in the interrupt mask register (IMR) and can be cleared, set, or tested using its
own dedicated bit in the interrupt flag register (IFR). The reset and NMI functions are not maskable.
All interrupt vector locations are on two-word boundaries so that branch instructions can be accommodated in
those locations. While normally located at program memory address 0, the interrupt vectors can be remapped
to the beginning of any 2K-word page in program memory by modifying the contents of the interrupt vector
pointer (IPTR) located in the PMST status register.
A built-in mechanism protects multicycle instructions from interrupts. If an interrupt occurs during a multicycle
instruction, the interrupt is not processed until the instruction completes execution. This mechanism applies to
instructions that are repeated (using the RPT instruction) and to instructions that become multicycle because
of wait states.
Each time an interrupt is serviced or a subroutine is entered, the PC is pushed onto an internal hardware stack,
providing a mechanism for returning to the previous context. The stack contains eight locations, allowing
interrupts or subroutines to be nested up to eight levels deep.
In addition to the eight-level hardware PC stack, eleven key CPU registers are equipped with an associated
single-level stack or shadow register into which the registers’ contents are saved upon servicing an interrupt.
The contents are restored into their particular CPU registers once a return-from-interrupt instruction (RETE or
RETI) is executed. The registers that have the shadow-register feature include the ACC and buffer, product
register, status registers, and several other key CPU registers. The shadow-register feature allows
sophisticated context save and restore operations to be handled automatically in cases where nested interrupts
are not required or if interrupt servicing is performed serially.
power-down modes
The ’C5x implements several power-down modes in which the ’C5x core enters a dormant state and dissipates
considerably less power. A power-down mode is invoked either by executing the IDLE/IDLE2 instructions or
by driving the HOLD input low. When the HOLD signal initiates the power-down mode, on-chip peripherals
continue to operate; this power-down mode is terminated when HOLD goes inactive.
While the ’C5x is in a power-down mode, all internal contents are maintained; this allows operation to continue
unaltered when the power-down mode is terminated. All CPU activities are halted when the IDLE instruction
is executed, but the CLKOUT1 pin remains active. The peripheral circuits continue to operate, allowing
peripherals such as serial ports and timers to take the CPU out of its powered-down state. A power-down mode,
when initiated by an IDLE instruction, is terminated upon receipt of an interrupt.
The IDLE2 instruction is used for a complete shutdown of the core CPU as well as all on-chip peripherals. In
IDLE2, the power is reduced significantly because the entire device is stopped. The power-down mode is
terminated by activating any of the external interrupt pins (RS, NMI, INT1, INT2, INT3, and INT4) for at least
five machine cycles.
bus-keeper circuitry (TMS320LC56/’C57S/’LC57)
The TMS320LC56/’C57S/’LC57 devices provide built-in bus keeper circuitry which holds the last state driven
on the data bus by either the DSP or an external device after the bus is no longer being driven. This capability
prevents excess power consumption caused by a floating bus, thus allowing optimization of power consumption
without the need for external pullup resistors.
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
external interface
The ’C5x supports a wide range of system interfacing requirements. Program, data, and I/O address spaces
provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along
with the PS, DS, and IS space select signals, allow addressing of 64K 16-bit words in each of the three spaces.
I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O
address space using the processor’s external address and data buses in the same manner as memory-mapped
devices.
The ’C5x external parallel interface provides various control signals to facilitate interfacing to the device. The
R/W output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles. For convenience, the device also provides the RD and the
WE output signals, which indicate a read and a write cycle, respectively, along with timing information for those
cycles. The availability of these signals minimizes external gating necessary for interfacing external devices to
the ’C5x.
Interface to memory and I/O devices of varying speeds is accomplished by using the READY line. When
transactionsaremadewithslowerdevices, the’C5xprocessorwaitsuntiltheotherdevicecompletesitsfunction
and signals the processor via the READY line. Once a ready indication is provided back to the ’C5x from the
external device, execution continues.
The bus request (BR) signal is used in conjunction with the other ’C5x interface signals to arbitrate external
global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted
at the beginning of the access. When an external global-memory device receives the the bus request, the
external device responds by asserting the READY signal after the global memory access is arbitrated and the
global access is completed.
external direct-memory access (DMA) capability
All ’C5x devices with single-access RAM offer a unique feature allowing another processor to read and write
to the ’C5x internal memory. To initiate a read or write operation to the ’C5x single-access RAM, the host or
master processor requests a hold state on the DSP’s external bus. When acknowledged with HOLDA, the host
can request access to the internal bus by pulling the BR signal low. Unlike the hold mode, which allows the
current operation to complete and allows CPU operation to continue (if status bit HM=0), a BR-requested DMA
always halts the operation currently being executed by the CPU. Access to the internal bus always is granted
on the third clock cycle after the BR signal is received. In the PQ package, the IAQ pin also indicates when bus
access has been granted. In the PZ package, this pin is not present so the host is required to wait two clock
cycles after driving the bus request low before beginning DMA transfer.
host port interface (HPI) (TMS320C57S, TMS320LC57, TMS320LC57S only)
The HPI is an 8-bit parallel port used to interface a host processor to the ’C57S/’LC57. The host port is
connected to a 2k word on-chip buffer through a dedicated internal bus. The dedicated bus allows the CPU to
work uninterrupted while the host processor accesses the host port. The HPI memory buffer is a single-access
RAM block which is accessible by both the CPU and the host. The HPI memory also can be used as
general-purpose data or program memory. Both the CPU and the host have access to the HPI control register
(HPIC) and the host can address the HPI memory through the HPI address register (HPIA).
Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin, HBIL, indicating whether
the high or low byte is being transmitted. Two control pins, HCNTL1 and HCNTL0, control host access to the
HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the
’C57S/’LC57 by writing to HPIC. The ’C57S/’LC57 can interrupt the host with a dedicated HINT pin that the host
acknowledges and clears.
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
host port interface (continued)
The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the
normal mode of operation, both the ’C57S/’LC57 and the host can access HPI memory. In this mode,
asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority
and the ’C57S/’LC57S waits one cycle. Host and CPU accesses to the HPI memory can be resychronized
through polling of a command word or through interrupts to prevent stalling the CPU for one cycle. The HOM
capability allows the host to access HPI memory while the ’C57S/’LC57 is in IDLE2 mode (all internal clocks
stopped) or in reset mode. The external ’C57S/’LC57S clock even can be stopped. The host can, therefore,
access the HPI RAM while the ’C57S/’LC57 is in its optimum configuration in terms of power consumption.
The HPI control register has two data strobes, HDS1 and HDS2, a read/write strobe HR/W, and an address
strobe HAS, to enable a glueless interface to a variety of industry-standard host devices. The HPI is easily
interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe, and
a read/write strobe, or two separate strobes for read and write. An HPI-ready pin, HRDY, is provided to specify
wait states for hosts that support an asynchronous input. When the ’C57S/’LC57 operating frequency is
variable, or when the host is capable of accessing at a faster rate than the maximum shared-access mode
access rate, the HRDY pin provides a convenient way to adjust the host access rate automatically (no software
handshake needed) to a change in the ’C57S/’LC57 clock rate or an HPI-mode switch.
The HPI supports high-speed back-to-back accesses. In the shared-access mode, the HPI can handle one byte
every five ’C57S/’LC57 periods (that is, 64 Mb/s with a 40-MHz ’C57S/’LC57). The HPI is designed so that the
host can take advantage of this high bandwidth and run at frequencies up to (f n) ÷ 5, where n is the number
of host cycles for an external access and f is the ’C57S/’LC57 frequency. In host-only mode, the HPI supports
even higher speed back-to-back host accesses: 1 byte every 50 ns (that is, 160 Mb/s) independently of the
’C57S/’LC57 clock rate.
serial ports
The ’C5x provides high-speed full-duplex serial ports that allow direct interface to other ’C5x devices, codecs,
and other devices in a system. There is a general-purpose serial port, a time-division-multiplexed (TDM) serial
port, and an auto-buffered serial port (BSP).
The general-purpose serial port uses two memory-mapped registers for data transfer: the data-transmit register
(DXR) and the data-receive register (DRR). Both registers can be accessed in the same manner as any other
memory location. The transmit and receive sections of the serial port each have associated clocks,
frame-synchronization pulses, and serial shift registers, and serial data can be transferred either in bytes or in
16-bit words. Serial port receive and transmit operations can generate their own maskable transmit and receive
interrupts (XINT and RINT), allowing serial port transfers to be managed by way of software. The ’C5x serial
ports are double-buffered and fully static.
The TDM port allows the device to communicate through time-division multiplexing with up to seven other ’C5x
devices with TDM ports. Time-division multiplexing is the division of time intervals into a number of subintervals
with each subinterval representing a prespecified communications channel. The TDM port serially transmits
16-bit words on a single data line (TDAT) and destination addresses on a single address line (TADD). Each
device can transmit data on a single channel and receive data from one or more of the eight channels providing
a simple and efficient interface for multiprocessing applications. A frame synchronization pulse occurs once
every 128 clock cycles corresponding to transmission of one 16-bit word on each of the eight channels. Like
the general-purpose serial port, the TDM port is double-buffered on both input and output data. The TDM port
also can be configured in software to operate as a general-purpose serial port as described above. Both types
of ports are capable of operating at up to one-fourth the machine cycle rate (CLKOUT1).
The buffered serial port (BSP) consists of a full-duplex double-buffered serial port interface (SPI) and an
auto-buffering unit (ABU). The SPI block of the BSP is an enhanced version of the general-purpose serial port.
The auto-buffering unit allows the SPI to read/write directly to ’C5x internal memory using a dedicated bus
independently of the CPU. This results in minimum overhead for SPI transactions and faster data rates.
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
serial ports (continued)
When auto-buffering capability is disabled (standard mode), transfers with SPI are performed under software
control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and
WRINT) provided by the SPI are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT).
When auto buffering is enabled, word transfers are done directly between the SPI and the ’C5x internal memory,
using ABU-embedded address generators.
The ABU has its own set of circular addressing registers with corresponding address-generation units. Memory
for the buffers resides in 2K words of ’C5x internal memory. The length and starting addresses of the buffers
are user-programmable. A buffer-empty/-full interrupt can be posted to the CPU. Buffering is halted easily
because of an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and
receive sections. When auto-buffering is disabled, operation is similar to the general-purpose serial port.
The SPI allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a
frame-synchronization pulse for every packet. In continuous mode, the frame-synchronization pulse occurs
when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency
and polarity programmable. The SPI is fully static and operates at arbitrarily low clock frequencies. The
maximum operating frequency is CLKOUT1 (28.6 Mb/s at 35 ns, 40 Mb/s at 25 ns). The SPI transmit section
also includes a pulse-coded modulation (PCM) mode that allows easy interface with a PCM line.
Most ’C5x devices provide one general-purpose serial port and one TDM port. The ’C52 provides one
general-purpose serial port and no TDM port. The ’C53SX provides two general-purpose serial ports and no
TDMport. The’LC56, ’C57S, and’LC57devicesprovideonegeneral-purposeserialportandonebufferedserial
port.
software wait-state generators
Software wait-state generation is incorporated in the ’C5x without any external hardware for interfacing with
slower off-chip memory and I/O devices. The circuitry consists of 16 wait-state generating circuits and is
user-programmable to operate with 0, 1, 2, 3, or 7 wait states. For off-chip memory accesses, these wait-state
generators are mapped on 16K-word boundaries in program memory, data memory, and the I/O ports.
The ’C53S/’C57S and ’LC56/57 devices have software-programmable wait-state generators that are controlled
by one 16-bit wait-state register PDWSR at address 0x28. The programmed number of wait states (0 through
7) applies to all external addresses at the corresponding address space (program, data, I/O) regardless of
address value.
timer
The ’C5x features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one
thirty-second the machine rate of the device itself, depending on the programmable timer’s divide-down ratio.
This timer can be stopped, restarted, reset, or disabled by specific status bits.
The timer can be used to generate CPU interrupts periodically. The timer is decremented by one at every
CLKOUT1 cycle. A timer interrupt (TINT) and a pulse equal to the duration of a CLKOUT1 cycle on the external
TOUT pin are generated each time the counter decrements to zero. The timer provides a convenient means
of performing periodic I/O or other functions. When the timer is stopped, the internal clocks to the timer are shut
off, allowing the device to run in a low-power mode of operation.
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DIGITAL SIGNAL PROCESSORS
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IEEE 1149.1 boundary scan interface
The IEEE 1149.1 boundary-scan interface is used for emulation and test purposes. The IEEE 1149.1 scanning
logic provides the boundary-scan path to and from the interfacing devices. Also, it can be used to test pin-to-pin
continuity as well as to perform operational tests on those peripheral devices that surround the ’C5x. On ’C5x
devices which do not provide boundary-scan capability, the IEEE 1149.1 interface is used for emulation
purposes only. It is interfaced to other internal scanning logic circuitry, which has access to all of the on-chip
resources. Thus, the ’C5x can perform on-board emulation by means of IEEE 1149.1 serial pins and the
emulation-dedicated pins (see IEEE Standard 1149.1 for more details). Table 5 shows IEEE 1149.1 and
boundary-scan functions supported by the ’C5x family of devices.
Table 5. IEEE 1149.1 Interface/Boundary Scan/On-Chip Analysis Block Configurations
on the ’C5x/’LC5x Device Family
DEVICE TYPE
’C50/’LC50
IEEE 1149.1 INTERFACE
BOUNDARY-SCAN CAPABILITY
ON-CHIP ANALYSIS BLOCK
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Full
Full
’C51/’LC51
’C52/’LC52
’C53/’LC53
’C53S/’LC53S
’LC56
Full
Yes
No
Full
Reduced
Full
No
’C57S
Yes
No
Full
’LC57
Full
on-chip analysis block
The on-chip analysis block, in conjunction with the ’C5x EVM, provides the capability to perform a variety of
debugging and performance evaluation functions in a target system. The full analysis block provides capability
for message passing by a combination of monitor mode and scan, flexible breakpoint setup based on events,
counting of events, and a PC discontinuity trace buffer. Breakpoints can be triggered based on the following
events: program fetches/reads/writes, EMU0/1 pin activity (used in multiprocessing), data reads/writes, CPU
events(calls, returns, interrupts/traps, branches, pipelineclock), andevent-counteroverflow. Theeventcounter
is a 16-bit counter which can be used for performance analysis. The event counter can be incremented based
on the occurrence of the following events: CPU clocks (performance monitoring), pipeline advances, instruction
fetches (used to count instructions for an algorithm), branches, calls, returns, interrupts/traps, program
reads/writes, or data reads/writes. The PC discontinuity-trace buffer provides a method to monitor program
counter flow.
These analysis functions are available on all ’C5x devices except the ’C53S and ’LC53S which have a reduced
analysis block (see Table 5). The reduced analysis block provides capability for message passing and
breakpoints based on program fetches/reads/writes and EMU0/1 pin activity.
multiprocessing
The flexibility of the ’C5x allows configurations to satisfy a wide range of system requirements; the device can
be used in a variety of system configurations, including, but not limited to, the following:
A standalone processor
A multiprocessor with devices in parallel
A slave/host multiprocessor with global-memory space
A peripheral processor interfaced via processor-controlled signals to another device
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
multiprocessing (continued)
For multiprocessing applications, the ’C5x is capable of allocating global-memory space and communicating
with that space via the BR and ready control signals. Global memory is data memory shared by more than one
device. Globalmemoryaccessmustbearbitrated. The8-bitmemory-mappedglobalmemoryallocationregister
(GREG) specifies part of the ’C5x’s data memory as global external memory. The contents of the register
determine the size of the global memory space. If the current instruction addresses an operand within that
space, BR is asserted to request control of the bus. The length of the memory cycle is controlled by the READY
line.
The ’C5x supports direct memory access (DMA) to its external program, data, and I/O spaces using the HOLD
and HOLDA signals. Another device can take complete control of the ’C5x’s external memory interface by
asserting HOLD low. This causes the ’C5x to to place its address, data, and control lines in the high-impedance
state and assert HOLDA. While external memory is being accessed, program execution from on-chip memory
can proceed concurrently when the device is in hold mode.
Multiple ’C5x devices can be interconnected through their serial ports. This form of interconnection allows
information to be transferred at high speed while using a minimum number of signal connections. A complete
full-duplex serial-port interconnection between multiple processors can be accomplished with as few as four
signal lines.
instruction set
The ’C5x microprocessor implements a comprehensive instruction set that supports both numeric-intensive
signal processing operations and general-purpose applications, such as multiprocessing and high-speed
control. Source code for the ’C1x and ’C2x DSPs is upward compatible with the ’C5x.
For maximum throughput, the next instruction is prefetched while the current one is being executed. Because
the same data lines are used to communicate to external data, program, or I/O space, the number of cycles an
instruction requires to execute varies, depending on whether the next data operand fetch is from internal or
external memory. Highest throughput is achieved by maintaining data memory on chip and using either internal
or fast external program memory.
addressing modes
The ’C5x instruction set provides six basic memory-addressing modes: direct, indirect, immediate, register,
memory mapped, and circular addressing.
In direct addressing, the instruction word contains the lowest seven bits of the data-memory address. This field
is concatenated with the nine bits of the data-memory page pointer (DP) to form the 16-bit data-memory
address. Therefore, in the direct-addressing mode, data memory is paged effectively with a total of 512 pages,
each of which contains 128 words.
Indirect addressing accesses data memory through the auxiliary registers. In indirect addressing mode, the
address of the instruction operand is contained in the currently selected auxiliary register. Eight auxiliary
registers (AR0–AR7) provide flexible and powerful indirect addressing. To select a specific auxiliary register,
the auxiliary register pointer (ARP) is loaded with a value from 0 to 7 for AR0 through AR7, respectively.
There are seven types of indirect addressing: autoincrement or autodecrement, postindexing by either adding
or subtracting the contents of AR0, single-indirect addressing with no increment or decrement, and bit-reversed
addressing (used in FFTs) with increment or decrement. All operations are performed on the current auxiliary
register in the same cycle as the original instruction, following which the current auxiliary register and ARP can
be modified.
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
addressing modes (continued)
In immediate addressing, the actual operand data is provided in a portion of the instruction word or words. There
are two types of immediate addressing: long and short. In short-immediate addressing, the data is contained
in a portion of the bits in a single-word instruction. In long-immediate addressing, the data is contained in the
second word of a two-word instruction. The immediate-addressing mode is useful for data that does not need
to be stored or used more than once during the course of program execution, such as initialization values,
constants, etc.
The register-addressing mode uses operands in CPU registers either explicitly, such as with a direct reference
to a specific register, or implicitly, with instructions that intrinsically reference certain registers. In either case,
operand reference is simplified because 16-bit values can be used without specifying a full 16-bit operand
address or immediate value.
Memory-mapped addressing provides the convenience of easy access to memory-mapped registers located
on page zero of data memory. The flexibility of memory-mapped addressing results because accesses are
made independently of actual DP value and without having to provide a complete address of the memory
location being accessed. Commonly used on-board registers can be accessed with a simplified addressing
scheme.
Circular addressing is the most sophisticated ’C5x addressing mode. This addressing mode allows specified
buffers in memory to be accessed sequentially with a pointer that automatically wraps around to the beginning
of the buffer when the last location is accessed. A total of two independent circular buffers can be allocated at
any given time.
Five dedicated registers are allocated for implementation of circular addressing: a beginning-of-buffer and an
end-of-buffer register for each of the two independent circular buffers and a control register. Additionally, one
of the auxiliary registers is used as the pointer into the circular buffer. All registers used in circular addressing
must be initialized properly prior to performing any circular buffer access.
The circular-addressing mode allows implementation of circular buffers, which facilitate data structures used
in FIR filters, convolution and correlation algorithms, and waveform generators. Having the capability to access
circular buffers automatically with no overhead allows these types of data structures to be implemented most
efficiently.
repeat feature
The repeat function can be used withinstructionssuchasmultiply/accumulates(MACandMACD), blockmoves
(BLDD and BLPD), I/O transfers (IN/OUT), and table read/writes (TBLR/TBLW). These instructions, although
normally multicycle, are pipelined when the repeat feature is used, and they effectively become single-cycle
instructions. For example, the table-read instruction may take three or more cycles to execute, but when the
instruction is repeated, a table location can be read every cycle.
The repeat counter (RPTC) is a 16-bit register that, when loaded with a number N, causes the next single
instruction to be executed N + 1 times. The RPTC register is loaded by either the RPT or the RPTZ instruction,
resulting in a maximum of 65,536 executions of a given instruction. RPTC is cleared by reset. The RPTZ
instruction clears both ACC and PREG before the next instruction starts repeating. Once a repeat instruction
(RPT or RPTZ) is decoded, all interrupts including NMI (except reset) are masked until the completion of the
repeat loop. However, the device responds to the HOLD signal while executing an RPT/RPTZ loop.
repeat feature (continued)
The ’C5x implements a block-repeat feature that provides zero-overhead looping for implementation of FOR
and DO loops. The function is controlled by three registers (PASR, PAER, and BRCR) and the BRAF bit in the
PMST register. The block-repeat counter register (BRCR) is loaded with a loop count of 0 to 65,535. Then,
execution of the RPTB (repeat block) instruction loads the program-address-start register (PASR) with the
address of the instruction following the RPTB instruction and loads the program-address-end register (PAER)
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
with its long-immediate operand. The long-immediate operand is the address of the instruction following the last
instruction in the loop minus one. (The repeat block must contain at least three instruction words.) Execution
of the RPTB instruction automatically sets active the BRAF bit. With each PC update, the PAER contents are
compared to the PC. If they are equal, the BRCR contents are compared to zero. If the BRCR contents are
greater than zero, BRCR is decremented and the PASR is loaded into the PC, repeating the loop. If not, the
BRAF bit is set low and the processor resumes execution past the end of the code’s loop.
The equivalent of a WHILE loop can be implemented by setting the BRAF bit to zero if the exit condition is met.
The program then completes the current pass through the loop but does not go back to the top. To exit, the bit
must be reset at least four instruction words before the end of the loop. It is possible to exit block-repeat loops
and return to them without stopping and restarting the loop. Branches, calls, and interrupts do not necessarily
affect the loop. When program control is returned to the loop, loop execution is resumed.
instruction set summary
This section summarizes the operational codes (opcodes) of the instruction set for the ’C5x digital signal
processors. The instruction set is a super set of the ’C1x and ’C2x instruction sets. The instructions are arranged
according to function and are alphabetized by mnemonic within each category. The symbols in Table 6 are used
in the instruction set opcode table (Table 7). The Texas Instruments ’C5x assembler accepts ’C2x instructions
as well as ’C5x instructions.
The number of words that an instruction occupies in program memory is specified in column 4 of Table 7. In
these cases, different forms of the instruction occupy a different number of words. For example, the ADD
instruction occupies one word when the operand is a short immediate value or two words if the operand is a
long immediate value.
The number of cycles that an instruction requires to execute is listed in column 5 of Table 7. All instructions are
assumed to be executed from internal program memory and internal data dual-access memory. The cycle
timings are for single-instruction execution, not for repeat mode.
A read or write access to any peripheral memory-mapped register in data memory locations 20h–4Fh adds one
cycle to the cycle time shown because all peripherals perform these accesses over the internal peripheral bus.
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
instruction set summary (continued)
Table 6. Opcode Symbols
SYMBOL
DESCRIPTION
A
Address
ACC
ACCB
ARX
Accumulator
Accumulator buffer
Auxiliary register value (0–7)
BITX
BMAR
DBMR
I
4-bit field specifies which bit to test for the BIT instruction
Block-move address register
Dynamic bit-manipulation register
Addressing-mode bit
II...II
Immediate operand value
INTM
INTR#
N
Interrupt-mode flag bit
Interrupt vector number
Field for the XC instruction, indicating the number of instructions (one or two) to execute conditionally
PREG
PROG
RPTC
SHF, SHFT
TC
Product register
Program memory
Repeat counter
3/4 bit shift value
Test-control bit
Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO
T P Meaning
0 0
0 1
1 0
1 1
BIO low
TC=1
TC=0
T P
None of the above conditions
TREGn
Temporary register n (n = 0, 1, or 2)
4-bit field representing the following conditions:
Z:
L:
V:
C:
ACC = 0
ACC < 0
Overflow
Carry
A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the
corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4–7) indicates the state of
the conditions designated by the mask bits as being tested. For example, to test for ACC ≥ 0, the Z and L fields are set while
the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate
testing the condition ACC = 0, and the L field is reset to indicate testing the condition ACC ≥ 0. The conditions possible with
these 8 bits are shown in the BCND, CC, and XC instructions. To determine if the conditions are met, the 4-LSB bit mask
is ANDed with the conditions. If any bits are set, the conditions are met.
Z L V C
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS
INSTRUCTION
Absolute value of ACC
Add ACCB to ACC with carry
Add to ACC with shift
Add to low ACC short immediate
Add to ACC long immediate with shift
Add to ACC with shift of 16
MNEMONIC
OPCODE
WORDS
CYCLES
ABS
ADCB
ADD
ADD
ADD
1011 1110 0000 0000
1011 1110 0001 0001
0010 SHFT IAAA AAAA
1011 1000 IIII IIII
1011 1111 1001 SHFT
0110 0001 IAAA AAAA
1011 1110 0001 0000
0110 0000 IAAA AAAA
0110 0010 IAAA AAAA
0110 0011 IAAA AAAA
0110 1110 IAAA AAAA
1011 1111 1011 SHFT
1011 1110 1000 0001
1011 1110 0001 0010
1011 1111 1110 SHFT
1011 1110 0000 0001
1011 1110 0001 1011
1011 1110 0001 1100
1011 1110 0001 1101
1011 1110 0001 1111
0001 SHFT IAAA AAAA
1011 1111 1000 SHFT
0110 1010 IAAA AAAA
1011 1001 IIII IIII
0110 1001 IAAA AAAA
0110 1011 IAAA AAAA
0000 1000 IAAA AAAA
1011 1110 0000 0010
1010 0000 IAAA AAAA
0110 1101 IAAA AAAA
1011 1111 1100 SHFT
1011 1110 1000 0010
1011 1110 0001 0011
1011 1110 0000 1100
1011 1110 0001 0100
1011 1110 0000 1101
1011 1110 0001 0101
1011 1110 0001 1110
1001 1SHF IAAA AAAA
1001 0SHF IAAA AAAA
1000 1000 IAAA AAAA
1011 1110 0101 1010
1011 1110 0101 1011
1011 1110 0001 1000
1011 1110 0001 1001
1011 1110 0000 1001
1011 1110 0001 0110
1011 1110 0000 1010
1011 1110 0001 0111
0011 SHFT IAAA AAAA
0110 0101 IAAA AAAA
1011 1010 IIII IIII
1011 1111 1010 SHFT
1
1
1
1
2
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
2
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
1
1
1
ADD
Add ACCB to ACC
Add to ACC with carry
ADDB
ADDC
ADDS
ADDT
AND
Add to low ACC with sign extension suppressed
Add to ACC with shift specified by TREG1 [3–0]
AND ACC with data value
AND with ACC long immediate with shift
AND with ACC long immediate with shift of 16
AND ACCB with ACC
Barrel shift ACC right
Complement ACC
Store ACC in ACCB if ACC > ACCB
Store ACC in ACCB if ACC< ACCB
Exchange ACCB with ACC
Load ACC with ACCB
Load ACC with shift
Load ACC long immediate with shift
Load ACC with shift of 16
Load low word of ACC with immediate
Load low word of ACC
Load ACC with shift specified by TREG1 [3–0]
Load ACCL with memory-mapped register
Negate ACC
Normalize ACC
OR ACC with data value
OR with ACC long immediate with shift
OR with ACC long immediate with shift of 16
OR ACCB with ACC
Rotate ACC 1 bit left
Rotate ACCB and ACC left
Rotate ACC 1 bit right
Rotate ACCB and ACC right
Store ACC in ACCB
Store high ACC with shift
Store low ACC with shift
Store ACCL to memory-mapped register
Shift ACC 16 bits right if TREG1 [4] = 0
Shift ACC0–ACC15 right as specified by TREG1 [3–0]
Subtract ACCB from ACC
Subtract ACCB from ACC with borrow
Shift ACC 1 bit left
Shift ACCB and ACC left
Shift ACC 1 bit right
Shift ACCB and ACC right
AND
AND
ANDB
BSAR
CMPL
CRGT
CRLT
EXAR
LACB
LACC
LACC
LACC
LACL
LACL
LACT
LAMM
NEG
1
1 or 2
1
1
1
2
2
1
1
1
1
1
1
1
NORM
OR
OR
OR
ORB
ROL
ROLB
ROR
RORB
SACB
SACH
SACL
SAMM
SATH
SATL
SBB
SBBB
SFL
SFLB
SFR
SFRB
SUB
SUB
1
1 or 2
1
1
1
1
1
1
1
1
1
1
1
2
Subtract from ACC with shift
Subtract from ACC with shift of 16
Subtract from ACC short immediate
Subtract from ACC long immediate with shift
SUB
SUB
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes (Continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS (CONTINUED)
INSTRUCTION
MNEMONIC
OPCODE
WORDS
CYCLES
Subtract from ACC with borrow
Conditional subtract
SUBB
SUBC
SUBS
SUBT
XOR
XOR
XOR
XORB
ZALR
ZAP
0110 0100 IAAA AAAA
0000 1010 IAAA AAAA
0110 0110 IAAA AAAA
0110 0111 IAAA AAAA
0110 1100 IAAA AAAA
1011 1111 1101 SHFT
1011 1110 1000 0011
1011 1110 0001 1010
0110 1000 IAAA AAAA
1011 1110 0101 1001
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
2
1
1
1
Subtract from ACC with sign extension suppressed
Subtract from ACC, shift specified by TREG1 [3–0]
XOR ACC with data value
XOR with ACC long immediate with shift
XOR with ACC long immediate with shift of 16
XOR ACCB with ACC
Zero ACC, load high ACC with rounding
Zero ACC and product register
AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
INSTRUCTION
MNEMONIC
OPCODE
WORDS
CYCLES
Add to AR short immediate
Compare AR with CMPR
Load AR from addressed data
Load AR short immediate
Load AR long immediate
Load data page pointer with addressed data
Load data page immediate
Modify auxiliary register
Store AR to addressed data
Subtract from AR short immediate
ADRK
CMPR
LAR
LAR
LAR
LDP
LDP
MAR
SAR
SBRK
0111 1000 IIII IIII
1011 1111 0100 01CM
0000 0ARX IAAA AAAA
1011 0ARX IIII IIII
1011 1111 0000 1ARX
0000 1101 IAAA AAAA
1011 110I IIII IIII
1000 1011 IAAA AAAA
1000 0ARX IAAA AAAA
0111 1100 IIII IIII
1
1
1
1
2
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
BRANCH INSTRUCTIONS
MNEMONIC
INSTRUCTION
OPCODE
WORDS
CYCLES
Branch unconditional with AR update
Branch addressed by ACC
Branch addressed by ACC delayed
Branch AR ≠ 0 with AR update
Branch AR ≠ 0 with AR update delayed
Branch conditional
Branch conditional delayed
Branch unconditional with AR update delayed
Call subroutine addressed by ACC
Call subroutine addressed by ACC delayed
Call unconditional with AR update
Call unconditional with AR update delayed
Call conditional
Call conditional delayed
Software interrupt
Nonmaskable interrupt
Return
Return conditional
Return conditionally, delayed
Return, delayed
Return from interrupt with enable
Return from interrupt
Trap
B
0111 1001 1AAA AAAA
1011 1110 0010 0000
1011 1110 0010 0001
0111 1011 1AAA AAAA
0111 1111 1AAA AAAA
1110 00TP ZLVC ZLVC
1111 00TP ZLVC ZLVC
0111 1101 1AAA AAAA
1011 1110 0011 0000
1011 1110 0011 1101
0111 1010 1AAA AAAA
0111 1110 1AAA AAAA
1110 10TP ZLVC ZLVC
1111 10TP ZLVC ZLVC
1011 1110 011I NTR#
1011 1110 0101 0010
1110 1111 0000 0000
1110 11TP ZLVC ZLVC
1111 11TP ZLVC ZLVC
1111 1111 0000 0000
1011 1110 0011 1010
1011 1110 0011 1000
1011 1110 0101 0001
111N 01TP ZLVC ZLVC
2
1
1
2
2
2
2
2
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
4
4
2
BACC
BACCD
BANZ
BANZD
BCND
BCNDD
BD
CALA
CALAD
CALL
CALLD
CC
2 or 4
2
2 or 4
2
2
4
2
4
2
2 or 4
2
4
4
CCD
INTR
NMI
RET
4
RETC
RETCD
RETD
RETE
RETI
TRAP
XC
2 or 4
2
2
4
4
4
1
Execute next one or two INST on condition
instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes (Continued)
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
I/O AND DATA MEMORY OPERATIONS
INSTRUCTION
MNEMONIC
OPCODE
WORDS
CYCLES
Block move from data to data memory
Block move data to data DEST long immediate
Block move data to data with source in BMAR
Block move data to data with DEST in BMAR
Block move data to PROG with DEST in BMAR
Block move from program to data memory
Block move PROG to data with source in BMAR
Data move in data memory
Input external access
Load memory-mapped register
Out external access
Store memory-mapped register
Table read
Table write
BLDD
BLDD
BLDD
BLDD
BLDP
BLPD
BLPD
DMOV
IN
LMMR
OUT
SMMR
TBLR
TBLW
1010 1000 IAAA AAAA
1010 1001 IAAA AAAA
1010 1100 IAAA AAAA
1010 1101 IAAA AAAA
0101 0111 IAAA AAAA
1010 0101 IAAA AAAA
1010 0100 IAAA AAAA
0111 0111 IAAA AAAA
1010 1111 IAAA AAAA
1000 1001 IAAA AAAA
0000 1100 IAAA AAAA
0000 1001 IAAA AAAA
1010 0110 IAAA AAAA
1010 0111 IAAA AAAA
2
2
1
1
1
2
1
1
2
2
2
2
1
1
3
3
2
2
2
3
2
1
2
2 or 3
3
2 or 3
3
3
PARALLEL LOGIC UNIT INSTRUCTIONS
INSTRUCTION
MNEMONIC
OPCODE
WORDS
CYCLES
AND DBMR with data value
APL
APL
CPL
CPL
OPL
OPL
SPLK
XPL
XPL
0101 1010 IAAA AAAA
0101 1110 IAAA AAAA
0101 1011 IAAA AAAA
0101 1111 IAAA AAAA
0101 1001 IAAA AAAA
0101 1101 IAAA AAAA
1010 1110 IAAA AAAA
0101 1000 IAAA AAAA
0101 1100 IAAA AAAA
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
2
1
2
AND long immediate with data value
Compare DBMR to data value
Compare data with long immediate
OR DBMR to data value
OR long immediate with data value
Store long immediate to data
XOR DBMR to data value
XOR long immediate with data value
T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
INSTRUCTION
MNEMONIC
OPCODE
WORDS
CYCLES
Add PREG to ACC
Load high PREG
Load TREG0
Load TREG0 and accumulate previous product
Load TREG0, accumulate previous product, and move
data
Load TREG0 and load ACC with PREG
Load TREG0 and subtract previous product
Multiply/accumulate
Multiply/accumulate with data shift
Mult/ACC w/source ADRS in BMAR and DMOV
Mult/ACC with source address in BMAR
Multiply data value times TREG0
Multiply TREG0 by 13-bit immediate
Multiply TREG0 by long immediate
Multiply TREG0 by data, add previous product
Multiply TREG0 by data, ACC – PREG
Multiply unsigned data value times TREG0
Load ACC with product register
APAC
LPH
LT
LTA
LTD
1011 1110 0000 0100
0111 0101 IAAA AAAA
0111 0011 IAAA AAAA
0111 0000 IAAA AAAA
0111 0010 IAAA AAAA
1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
3
3
3
1
1
2
1
1
1
1
1
1
1
1
1
1
1
LTP
LTS
0111 0001 IAAA AAAA
0111 0100 IAAA AAAA
1010 0010 IAAA AAAA
1010 0011 IAAA AAAA
1010 1011 IAAA AAAA
1010 1010 IAAA AAAA
0101 0100 IAAA AAAA
110I IIII IIII IIII
1011 1110 1000 0000
0101 0000 IAAA AAAA
0101 0001 IAAA AAAA
0101 0101 IAAA AAAA
1011 1110 0000 0011
1011 1110 0000 0101
1000 1101 IAAA AAAA
1000 1100 IAAA AAAA
1011 1111 0000 00PM
0101 0010 IAAA AAAA
0101 0011 IAAA AAAA
1011 1110 0101 1000
MAC
MACD
MADD
MADS
MPY
MPY
MPY
MPYA
MPYS
MPYU
PAC
SPAC
SPH
SPL
SPM
SQRA
SQRS
ZPR
Subtract product from ACC
Store high product register
Store low product register
Set PREG shift count
Data to TREG0, square it, add PREG to ACC
Data to TREG0, square it, ACC – PREG
Zero product register
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes (Continued)
CONTROL INSTRUCTIONS
MNEMONIC
INSTRUCTION
Test bit specified immediate
OPCODE
WORDS
CYCLES
BIT
0100 BITX IAAA AAAA
0110 1111 IAAA AAAA
1011 1110 0100 0010
1011 1110 0100 0110
1011 1110 0100 1000
1011 1110 0100 1010
1011 1110 0100 1110
1011 1110 0100 0100
1011 1110 0100 0000
1011 1110 0100 1100
1011 1110 0010 0010
1011 1110 0010 0011
0000 1110 IAAA AAAA
0000 1111 IAAA AAAA
1000 1011 0000 0000
1011 1110 0011 0010
1000 1010 IAAA AAAA
0111 0110 IAAA AAAA
1011 1110 0011 1100
0000 1011 IAAA AAAA
1011 1110 1100 0100
1011 1011 IIII IIII
1011 1110 1100 0110
1011 1110 1100 0101
1011 1110 0100 0011
1011 1110 0100 0111
1011 1110 0100 1001
1011 1110 0100 1011
1011 1110 0100 1111
1011 1110 0100 1101
1011 1110 0100 0101
1011 1110 0100 0001
1000 1110 IAAA AAAA
1000 1111 IAAA AAAA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
Test bit in data value as specified by TREG2 [3–0]
Reset overflow mode
Reset sign extension mode
Reset hold mode
Reset TC bit
Reset carry
Reset CNF bit
Reset INTM bit
Reset XF pin
Idle
Idle until interrupt — low-power mode
Load status register 0
Load status register 1
No operation
Pop PC stack to low ACC
Pop stack to data memory
Push data memory value onto PC stack
Push low ACC to PC stack
Repeat instruction as specified by data
Repeat next INST specified by long immediate
Repeat INST specified by short immediate
Block repeat
Clear ACC/PREG and repeat next INST long immediate
Set overflow mode
Set sign extension mode
Set hold mode
Set TC bit
Set carry
BITT
CLRC
CLRC
CLRC
CLRC
CLRC
CLRC
CLRC
CLRC
IDLE
IDLE2
LST
LST
NOP
POP
POPD
PSHD
PUSH
RPT
RPT
RPT
RPTB
RPTZ
SETC
SETC
SETC
SETC
SETC
SETC
SETC
SETC
SST
Set XF pin high
Set CNF bit
Set INTM bit
Store status register 0
Store status register 1
SST
development support
Texas Instruments offers an extensive line of development tools for the ’C5x generation of DSPs, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of ’C5x-based applications:
Software Development Tools:
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
development support (continued)
Hardware Development Tools:
Extended development set (XDS ) emulator (supports ’C5x multiprocessor system debug)
’C5x EVM (Evaluation Module)
’C5x DSK (DSP Starter Kit)
The TMS320 Family Development Support Reference Guide (SPRU011) contains information about
development support products for all TMS320 family member devices, including documentation. Refer to this
document for further information about TMS320 documentation or any other TMS320 support products from
Texas Instruments. There is an additional document, the TMS320 Third Party Support Reference Guide
(SPRU052), which contains information about TMS320-related products from other companies in the industry.
To receive copies of TMS320 literature, contact the Literature Response Center at 800/477-8924.
See Table 8 for complete listings of development support tools for the ’C5x. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Table 8. TMS320C5x, TMS320LC5x Development Support Tools
DEVELOPMENT TOOL
PLATFORM
Software
PART NUMBER
Compiler/Assembler/Linker
PC-DOS , OS/2
SPARC , HP
PC-DOS, OS/2
PC-DOS, WIN
SPARC
TMDS3242855-02
TMDS3242555-08
TMDS3242850-02
TMDS3245851-02
TMDS3245551-09
DFDP
Compiler/Assembler/Linker
Assembler/Linker
Simulator
Simulator
Digital Filter Design Package
Debugger/Emulation Software
Debugger/Emulation Software
PC-DOS
PC-DOS, OS/2, WIN
SPARC
TMDS3240150
TMDS3240650
Hardware
XDS-510 XL Emulator
XDS-510 WS Emulator
EVM Evaluation Module
DSK DSP Starter Kit
PC-DOS, OS/2
SPARC
TMD000510
TMDS000510WS
TMDS3260050
TMDS3200051
PC-DOS, WIN
PC-DOS
device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas
Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)
through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below.
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
PC-DOS and OS/2 are trademarks of International Business Machines Corp.
SPARC is a trademark of SPARC International, Inc.
WIN is a trademark of Microsoft Corporation.
HP is a trademark of Hewlett-Packard Company.
XDS is a trademark of Texas Instruments Incorporated.
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
device and development support tool nomenclature (continued)
TMS Fully-qualified production device
Support tool development evolutionary flow:
TMDX
Development support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development support product
TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability
of the device has been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, N, FN, or GB) and temperature range (for example, L). Figure 8 provides a legend for reading the
complete device name for any TMS320 family member.
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
TMS 320 (L)
(B)
C
52
PJ (L)
PREFIX
TEMPERATURE RANGE (DEFAULT: 0 TO 70°C)
H = 0 to 50°C
TMX= experimental device
TMP= prototype device
TMS= qualified device
SMJ = MIL-STD-883C
L
=
=
0 to 70°C
S
–55 to 100°C
M = –55 to 125°C
SM = High Rel (non-883C)
A
=
–40 to 85°C
PACKAGE TYPE
DEVICE FAMILY
320 = TMS320 Family
N
=
=
=
=
=
=
=
=
=
=
plastic DIP
ceramic CER-DIP
J
JD
GB
FZ
FN
FD
PJ
PQ
PZ
ceramic DIP side-brazed
ceramic PGA
LOW VOLTAGE OPTION (3.3V)
BOOT LOADER OPTION
ceramic CER-QUAD
plastic leaded CC
ceramic leadless CC
100-pin plastic EIAJ QFP
132-pin plastic bumpered QFP
100-pin plastic TQFP
TECHNOLOGY
C = CMOS
E
= CMOS EPROM
PBK = 128-pin plastic TQFP
PGE= 144-pin plastic TQFP
DEVICE
’C1x DSP:
’C3x DSP:
10
14
15
16
17
30
31
32
’C4x DSP:
’C5x DSP:
40
44
’C2x DSP:
25
26
50
51
52
53
56
57
’C2xx DSP:
203
209
Figure 8. TMS320 Device Nomenclature
documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include data sheets, such as this
document, with design specifications, complete user’s guides for all devices, development support tools, and
three volumes of the publication Digital Signal Processing Applications with the TMS320 Family (literature
numbers SPRA012, SPRA016, and SPRA017).
The application book series describes hardware and software applications, including algorithms, for fixed and
floating point TMS320 family devices. The TMS320C5x User’s Guide (literature number SPRU056), which
describes in detail the fifth-generation TMS320 products, is currently available.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board
service (BBS) provides access to information pertaining to the TMS320 family, including documentation, source
code and object code for many DSP algorithms and utilities. The BBS can be reached at 713/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http:/www.ti.com uniform
resource locator (URL).
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
absolute maximum ratings over operating ambient-air temperature range (unless otherwise noted)
†
(’320C5x only)
Supply voltage range, V
(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
I
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
O
Operating ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Operating case temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, T
A
C
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 3: All voltage values are with respect to V
.
SS
recommended operating conditions (’320C5x only)
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
Supply voltage
4.75
5
0
5.25
DD
V
SS
X2/CLKIN, CLKIN2
3
2.5
V
DD
V
DD
V
DD
+0.3
+0.3
+0.3
0.7
V
IH
High-level input voltage
CLKX, CLKR, TCLKX, TCLKR
All other inputs
V
2
X2/CLKIN, CLKIN2, CLKX, CLKR, TCLKX, TCLKR
All other inputs
– 0.3
– 0.3
V
IL
Low-level input voltage
V
0.8
‡
I
I
High-level output current (see Note 4)
Low-level output current
– 300
µA
mA
°C
OH
2
OL
T
Operating case temperature
0
85
85
C
T
Operating ambient temperature
–40
°C
A
‡
This I
can be exceeded when using a 1-kΩ pulldown resistor on the TDM serial port TADD output; however, this output still meets V
OH
OH
specifications under these conditions.
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
electrical characteristics over recommended ranges of supply voltage and operating ambient-air
temperature (unless otherwise noted) (’320C5x only)
‡
PARAMETER
TEST CONDITIONS
= 300 µA
MIN TYP
MAX
UNIT
V
V
V
High-level output voltage (see Note 4)
Low-level output voltage (see Note 4)
I
I
2.4
3
OH
OH
= 2 mA
0.3
0.6
20
V
OL
OL
BR (with internal pullup)
All other 3-state outputs
TRST (with internal pulldown)
TMS, TCK, TDI (with internal pullups)
X2/CLKIN
– 500
– 20
– 10
– 500
– 50
– 10
I
High-impedance output current (V
= 5.25 V)
DD
µA
µA
OZ
20
800
10
I
I
Input current (V = V
to V
)
DD
I
SS
50
All other inputs
10
f = 40 MHz,
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 5.25 V
= 5.25 V
= 5.25 V
= 5.25 V
= 5.25 V
= 5.25 V
= 5.25 V
= 5.25 V
60
67
x
f = 57 MHz,
x
I
Supply current, core CPU
mA
DD(core)
f = 80 MHz,
x
94
f = 100 MHz,
x
110
40
f = 40 MHz,
x
f = 57 MHz,
x
45
I
I
Supply current, pins
mA
DD(pins)
f = 80 MHz,
x
63
f = 100 MHz,
x
75
IDLE2, divide-by-two clock mode, clocks
shut off
Supply current, standby
5
µA
DD(standby)
C
C
Input capacitance
Output capacitance
15
15
pF
pF
i
o
†
Typical values are at V
DD
= 5 V, T = 25°C, unless otherwise specified.
A
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
absolute maximum ratings over specified temperature range (unless otherwise noted) (’320LC5x
†
only)
Supply voltage range, V
(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
I
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5 V
O
Operating ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40° to 85°C
A
Operating case temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55° to 150°C
C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 3: All voltage values are with respect to V
.
SS
recommended operating conditions (’320LC5x only)
MIN
NOM
3.3
0
MAX
3.47
UNIT
V
3.13
V
V
Supply voltage
Supply voltage
DD
V
SS
X2/CLKIN, CLKIN2
2.5
2.0
1.8
V
DD
V
DD
V
DD
+ 0.3
+ 0.3
+ 0.3
CLKX, CLKR, TCLKX, TCLKR
All other inputs
V
V
High-level input voltage
Low-level input voltage
IH
X2/CLKIN, CLKIN2, CLKX,
CLKR, TCLKX, TCLKR
–0.3
–0.3
0.5
0.6
V
V
All other inputs
V
‡
– 300
µA
mA
°C
°C
I
I
High-level output current
Low-level output current
OH
2
OL
0
85
85
T
Operating case temperature
Operating ambient temperature
C
–40
T
A
‡
This I
may be exceeded when using a 1-kΩ pulldown resistor on the TDM serial port TADD output; however, this output still meets V
OH
OH
specifications under these conditions.
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (’320LC5x only)
†
PARAMETER
TEST CONDITIONS
= 300 µA
MIN
TYP
MAX
UNIT
I
I
I
I
2.0
High-level output voltage
(see Note 4)
OH
OH
OL
OL
V
V
V
OH
‡
= 20 µA
= 2 mA
= 20 µA
V
– 0.3
DD
0.4
20
Low-level output voltage
(see Note 4)
V
OL
‡
0.3
BR (with internal pullup)
–500
High-impedance output current
I
µA
OZ
(V
DD
= 3.47 V)
All other 3-state outputs
–20
–10
20
800
10
TRST(with internal pulldown)
TMS, TCK, TDI pins (with internal pullups)
–500
–50
X2/CLKIN (oscillator enabled)
X2/CLKIN (oscillator disabled)
All other inputs
50
10
10
I
I
Input current (V = V
to V )
DD
µA
I
SS
–10
–10
f = 40 MHz,
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3.47 V
= 3.47 V
= 3.47 V
= 3.47 V
= 3.47 V
= 3.47 V
26
33
53
18
22
35
x
I
Supply current, core CPU
f = 50 MHz,
x
mA
DD(core)
f = 80 MHz,
x
f = 40 MHz,
x
I
I
Supply current, pins
f = 50 MHz,
x
mA
DD(pins)
f = 80 MHz,
x
IDLE2, divide-by-two clock mode, clocks
shut off
Supply current, standby
5
µA
DD(standby)
C
C
Input capacitance
Output capacitance
15
15
pF
pF
i
o
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
DD
Values derived from characterization data and not tested
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
I
OL
Output
Under
Test
50 Ω
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
V
=
=
=
=
2 mA (all outputs) minimum
300 µA (all outputs) minimum
1.5 V
OL
OH
LOAD
T
C
80-pF typical load circuit capacitance
Figure 9. Test Load Circuit
signal transition levels
The data in this section is shown for both the 5-V version (’C5x) and the 3.3-V version (’LC5x). In each case,
the 5-V data is shown followed by the 3.3-V data in parentheses. TTL-output levels are driven to a minimum
logic-high level of 2.4 V (2 V) and to a maximum logic-low level of 0.6 V (0.4 V). Figure 10 shows the TTL-level
outputs.
2.4 V (2 V)
2 V (1.6 V)
1 V (0.8 V)
0.6 V (0.4 V)
Figure 10. TTL-Level Outputs
TTL-output transition times are specified as follows:
For a high-to-low transition, the level at which the output is said to be no longer high is 2 V (1.6 V), and the
level at which the output is said to be low is 1 V (0.8 V).
For a low-to-high transition, the level at which the output is said to be no longer low is 1 V (0.8 V), and the
level at which the output is said to be high is 2 V (1.6 V).
Figure 11 shows the TTL-level inputs.
2 V (1.8 V)
0.8 V (0.6 V)
Figure 11. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2 V (1.8 V), and the level at which the input is said to be low is 0.8 V (0.6 V).
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V (0.6 V), and the level at which the input is said to be high is 2 V (1.8 V).
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
CLOCK CHARACTERISTICS AND TIMING
The ’C5x can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the clock mode pins (CLKMD1, CLKMD2, and CLKMD3). Table 9 shows the standard clock
options available on the ’C50, ’LC50, ’C51, ’LC51, ’C52, ’LC52, ’C53, ’LC53, ’C53S, and ’LC53S. For these
devices, the CLKIN2 pin functions as the external frequency input when using the PLL options. An expanded
set of clock options is shown in Table 10 and is available on the ’LC56, ’C57S, and ’LC57 devices. For these
devices, X2/CLKIN functions as the external frequency input when using the PLL options.
Table 9. Standard Clock Options
CLKMD1
CLKMD2
CLOCK SOURCE
†
PLL clock generator option
1
0
0
1
Reserved for test purposes
Externaldivide-by-twooptionorinternaldivide-by-two clockoption
with an external crystal
1
0
1
0
External divide-by-two option with the internal oscillator disabled
†
PLL multiply-by-one option on ’C50, ’C51, ’C53, ’C53S devices, PLL multiply-by-two option on
’C52 device
Table 10. PLL Clock Option for ’LC56, ’C57S, and ’LC57
CLKMD1
CLKMD2
CLKMD3
CLOCK SOURCE
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
PLL multiply-by-three
PLL multiply-by-four
PLL multiply-by-five
PLL multiply-by-nine
External divide-by-two option with oscillator disabled
PLL multiply-by-two
PLL multiply-by-one
External/Internal divide-by-two with oscillator enabled
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-half of the crystal’s oscillating frequency. The crystal should be in either fundamental or overtone
operation and parallel resonant, with an effective series resistance of 30 Ω and a power dissipation of 1 mW;
it should be specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned-LC circuit.
Figure 12 shows an external crystal (fundamental frequency) connected to the on-chip oscillator.
recommended operating conditions for internal divide-by-two clock option
MIN NOM
MAX
40.96
57.14
80
UNIT
†
0
†
0
†
0
†
0
†
0
†
0
†
0
TMS320C5x-40
TMS320C5x-57
TMS320C5x-80
TMS320C5x-100
TMS320LC5x-40
TMS320LC5x-50
TMS320LC5x-80
MHz
‡
f
Input clock frequency
100
40
clk
50
MHz
pF
80
C1, C2 Load capacitance
10
†
‡
This device utilizes a fully static design and, therefore, can operate with input clock cycle time (t
) approaching ∞. The device is characterized
c(CI)
at frequencies approaching 0 Hz, but is tested at f = 6.7 MHz to meet device test time requirements.
clk
’320C51, ’320C52 currently available at this clock speed
X1
X2/CLKIN
Crystal
C1
C2
Figure 12. Internal Clock Option
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. Refer to Table 9 and Table 10 for appropriate configuration of the CLKMD1, CLKMD2 and
CLKMD3 pins to generate the external divide-by-2 clock option. The external frequency injected must conform
to the specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5 t
(see Figure 13)
] (’320C5x only)
c(CO)
’320C5x-40
’320C5x-57
PARAMETER
UNIT
MIN
48.8 2t
3
TYP
MAX
MIN
TYP
MAX
†
†
t
t
t
t
t
t
Cycle time, CLKOUT1
35 2t
3
ns
ns
ns
ns
ns
ns
c(CO)
c(CI)
11
c(CI)
11
Delay time, X2/CLKIN high to CLKOUT1 high/low
Fall time, CLKOUT1
20
20
d(CIH-COH/L)
f(CO)
5
5
5
5
Rise time, CLKOUT1
r(CO)
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H – 3
H
H
H + 2 H – 3
H + 2 H – 3
H
H
H + 2
H + 2
w(COL)
w(COH)
’320C5x-80
’320C5x-100
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
†
†
t
t
t
t
t
t
Cycle time, CLKOUT1
25 2t
20 2t
ns
ns
ns
ns
ns
ns
c(CO)
c(CI)
9
c(CI)
9
Delay time, X2/CLKIN high to CLKOUT1 high/low
Fall time, CLKOUT1
1
18
1
18
d(CIH-COH/L)
f(CO)
4
4
4
4
Rise time, CLKOUT1
r(CO)
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H – 3
H
H
H + 2 H – 3
H + 2 H – 3
H
H
H + 2
H + 2
w(COL)
w(COH)
switching characteristics over recommended operating conditions [H = 0.5 t
(see Figure 13)
] (’320LC5x only)
c(CO)
’320LC5x-40
’320LC5x-50
’320LC5x-80
UNIT
UNIT
ns
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
†
†
†
t
t
Cycle time, CLKOUT1
50 2t
40 2t
25 2t
c(CO)
c(CI)
c(CI)
c(CI)
Delay time, X2/CLKIN high to
CLKOUT1 high/low
3
11
20
3
11
20
1
9
18
ns
d(CIH-COH/L)
t
t
t
t
Fall time, CLKOUT1
5
5
5
5
4
4
ns
ns
ns
ns
f(CO)
Rise time, CLKOUT1
r(CO)
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H – 3
H
H
H + 2 H – 3
H + 2 H – 3
H
H
H + 2 H – 3
H + 2 H – 3
H
H
H + 2
H + 2
w(COL)
w(COH)
†
This device utilizes a fully static design and, therefore, can operate with t
approaching infinity. The device is characterized at frequencies
c(Cl)
approaching 0 Hz but is tested at t
c(CO)
= 300 ns to meet device test time requirements.
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (’320C5x only) (see Figure 13)
’320C5x-40
’320C5x-57
’320C5x-80
’320C5x-100
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
†
†
†
†
t
t
t
t
t
Cycle time, X2/CLKIN
24.4
17.5
12.5
10
ns
ns
ns
ns
ns
c(CI)
‡
Fall time, X2/CLKIN
5
5
4
4
f(CI)
‡
Rise time, X2/CLKIN
5
†
5
†
4
†
4
†
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
11
11
8
8
5
5
5
5
w(CIL)
w(CIH)
†
†
†
†
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (’320LC5x only) (see Figure 13)
’320LC5x-80
’320LC5x-40
’320LC5x-50
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
†
†
†
t
t
t
t
t
Cycle time, X2/CLKIN
25
20
12.5
ns
ns
ns
ns
ns
c(CI)
‡
Fall time, X2/CLKIN
5
5
4
f(CI)
‡
Rise time, X2/CLKIN
5
†
5
†
4
†
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
11
11
9
9
5
5
w(CIL)
w(CIH)
†
†
†
†
This device utilizes a fully static design and, therefore, can operate with t
approaching ∞. The device is characterized at frequencies
c(Cl)
= 150 ns to meet device test time requirements.
approaching 0 Hz, but is tested at a minimum of t
c(Cl)
‡
Values derived from characterization data and not tested
t
r(CI)
t
t
f(CI)
w(CIH)
t
t
w(CIL)
c(CI)
CLKIN
t
t
f(CO)
c(CO)
t
t
r(CO)
w(COH)
t
t
d(CIH-COH/L)
w(COL)
CLKOUT1
Figure 13. External Divide-by-Two Clock Timing
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
PLL clock generator option
‡
An external frequency source can be used by injecting the frequency directly into CLKIN2 with X1 left
unconnected and X2 connected to V . This external frequency is multiplied by the factors shown in Table 9
DD
and Table 10 to generate the internal machine cycle. The multiply-by-one option is available on the ’C50, ’LC50,
’C51, ’LC51, ’C53, ’LC53, ’C53S and ’LC53S. The multiply-by-two option is available on the ’C52 and ’LC52.
Multiplication factors of 1, 2, 3, 4, 5, and 9 are available on the ’LC56, ’LC57, ’C57S and ’LC57S. Refer to Table 9
and Table 10 for appropriate configuration of the CLKMD1, CLKMD2 and CLKMD3 pins to generate the desired
PLL multiplication factor. The external frequency injected must conform to the specifications listed in the timing
requirements table.
switching characteristics over recommended operating conditions [H = 0.5 t
(see Figure 14)
] (’320C5x only)
c(CO)
’320C5x-40
TYP
’320C5x-57
TYP
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
Cycle time, CLKOUT1
48.8
75
35
75
ns
ns
ns
ns
ns
c(CO)
Fall time, CLKOUT1
5
5
5
5
f(CO)
Rise time, CLKOUT1
r(CO)
†
†
†
†
†
†
†
†
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H
H
H + 2
H – 3
H
H
H + 2
w(COL)
w(COH)
H – 3
H + 2
H – 3
H + 2
Delay time, CLKIN2 high to CLKOUT1
high
t
2
9
16
2
9
16
ns
ns
d(C2H-COH)
d(TP)
Delay time, transitory phase—PLL
t
1000t
c(C2)
1000t
c(C2)
†
synchronized after CLKIN2 supplied
’320C5x-80
TYP
’320C5x-100
TYP
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
t
Cycle time, CLKOUT1
25
55
20
45
ns
ns
ns
ns
ns
c(CO)
Fall time, CLKOUT1
4
4
4
4
f(CO)
Rise time, CLKOUT1
r(CO)
†
†
†
†
†
†
†
†
Pulse duration, CLKOUT1 low
Pulse duration, CLKOUT1 high
H – 3
H
H
H + 2
H – 3
H
H
H + 2
w(COL)
w(COH)
H – 3
H + 2
H – 3
H + 2
Delay time, CLKIN2 high to CLKOUT1
high
t
1
8
15
1
8
15
ns
ns
d(C2H-COH)
d(TP)
Delay time, transitory phase—PLL
t
1000t
c(C2)
1000t
c(C2)
†
synchronized after CLKIN2 supplied
†
‡
Values assured by design and not tested
On the TMS320C57S devices, CLKIN2 functions as the PLL clock input.
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
switching characteristics over recommended operating conditions [H = 0.5 t
(see Figure 14)
] (’320LC5x only)
c(CO)
’320LC5x-40
TYP
’320LC5x-50
TYP
’320LC5x-80
TYP
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
Cycle time,
CLKOUT1
†
†
†
55
t
t
50
75
40
75
25
ns
c(CO)
Delay time,
CLKIN2 high to
CLKOUT1 high
2
9
16
2
9
16
1
8
15
ns
d(C2H-COH)
Fall time,
CLKOUT1
t
t
t
t
5
5
5
5
4
4
ns
ns
ns
ns
f(CO)
Rise time,
CLKOUT1
r(CO)
Pulse duration,
CLKOUT1 low
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
H – 3
H
H
H + 2
H – 3
H
H
H + 2
H – 3
H
H
H + 2
w(COL)
w(COH)
Pulse duration,
CLKOUT1 high
H – 3
H + 2
H – 3
H + 2
H – 3
H + 2
Delay time,
transitory
phase—PLL
synchronized
after CLKIN2
supplied
t
1000t
c(C2)
1000t
c(C2)
1000t
c(C2)
ns
d(TP)
†
‡
§
Clocks can only be stopped while executing IDLE2 when using the PLL clock generator option.
Values assured by design and not tested
On the ’LC56, ’LC57, and ’LC57S devices, CLKIN2 functions as the PLL clock input.
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (’320C5x only) (see Figure 14)
’320C5x-40
’320C5x-57
UNIT
MIN
48.8
97.6
MAX
MIN
35
MAX
†
‡
‡
Multiply-by-one
75
75
ns
ns
ns
ns
ns
ns
t
Cycle time, CLKIN2
c(C2)
§
‡
‡
Multiply-by-two
150
70
150
¶
t
t
t
t
Fall time, CLKIN2
5
5
5
5
f(C2)
¶
Rise time, CLKIN2
r(C2)
Pulse duration, CLKIN2 low
Pulse duration, CLKIN2 high
15
15
t
t
–15
–15
11
11
t
t
–11
–11
w(C2L)
w(C2H)
c(C2)
c(C2)
c(C2)
c(C2)
’320C5x-80
’320C5x-100
UNIT
MIN
25
MAX
MIN
20
MAX
†
‡
‡
Multiply-by-one
75
75
ns
ns
ns
ns
ns
ns
t
Cycle time, CLKIN2
c(C2)
§
‡
‡
Multiply-by-two
50
150
40
110
¶
t
t
t
t
Fall time, CLKIN2
4
4
4
4
f(C2)
¶
Rise time, CLKIN2
r(C2)
Pulse duration, CLKIN2 low
Pulse duration, CLKIN2 high
8
8
t
t
–8
–8
7
7
t
t
–7
–7
w(C2L)
w(C2H)
c(C2)
c(C2)
c(C2)
c(C2)
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (’320LC5x only) (see Figure 14)
’320LC5x-40
’320LC5x-50
’320LC5x-80
UNIT
MIN
50
MAX
MIN
40
MAX
MIN
25
MAX
†
‡
‡
‡
Multiply-by-one
75
75
37.5
110
ns
ns
ns
ns
ns
ns
t
Cycle time, CLKIN2
c(C2)
§
‡
‡
‡
Multiply-by-two
100
150
80
150
50
¶
t
t
t
t
Fall time, CLKIN2
5
5
5
5
4
4
f(C2)
¶
Rise time, CLKIN2
r(C2)
Pulse duration, CLKIN2 low
Pulse duration, CLKIN2 high
15
15
t
t
– 15
– 15
13
13
t
t
– 13
– 13
8
8
t
t
– 8
– 8
w(C2L)
w(C2H)
c(C2)
c(C2)
c(C2)
c(C2)
c(C2)
c(C2)
†
‡
Not available on ’C52, ’LC52
Clocks can be stopped only while executing IDLE2 when using the PLL clock generator option. The t
restarting clock from IDLE2 in this mode.
(the transitory phase) occurs when
d(TP)
§
¶
Available on ’C52, ’LC52, ’LC56, ’C57S, ’LC57, and ’LC57S
Values derived from characterization data and not tested
t
t
w(C2L)
f(C2)
t
w(C2H)
t
r(C2)
t
c(C2)
CLKIN2
t
w(COH)
t
d(C2H-COH)
t
f(CO)
t
c(CO)
t
r(CO)
t
w(COL)
t
d(TP)
Unstable
CLKOUT1
Figure 14. PLL Clock Generator Timing
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MEMORY AND PARALLEL I/O INTERFACE READ
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 15)
] (’320C5x only)
c(CO)
’320C5x-40
MIN MAX
’320C5x-57
MIN MAX
’320C5x-80
MIN MAX
’320C5x-100
MIN MAX
PARAMETER
UNIT
Setup time, address valid before
RD low
‡
‡
‡
‡
t
t
H – 10
0
H – 10
0
H – 7
0
H – 6
0
ns
ns
su(AV-RDL)
†
Hold time, address valid after RD
‡
‡
‡
‡
h(RDH-AV)
†
high
§¶#
t
t
Pulse duration, RD low
H – 2 H + 2
H – 2
H – 2 H + 2
H – 2
H – 2 H + 2
H – 2
H – 2 H + 2
H – 2
ns
ns
w(RDL)
§¶#
Pulse duration, RD high
w(RDH)
Delay time, CLKOUT1 to STRB
§¶
t
– 1
3
1
– 2
2
1
– 2
2
1
– 2
2
1
ns
d(CO-ST)
rising or falling edge
Delay time, CLKOUT1 to RD rising
t
t
– 3
– 3
– 3
– 3
ns
ns
d(CO-RD)
§¶
or falling edge
Delay time, RD high to WE low
2H – 5
2H – 5
2H – 4
2H – 4
d(RDH-WEL)
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 15)
] (’320LC5x only)
c(CO)
’320LC5x-40
’320LC5x-50
’320LC5x-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
†
‡
‡
t
t
t
t
t
t
t
Setup time, address valid before RD low
H – 10
0
H – 7
0
ns
ns
ns
ns
ns
ns
ns
su(AV-RDL)
h(RDH-AV)
w(RDL)
†
‡
‡
Hold time, address valid after RD high
§¶#
Pulse duration, RD low
Pulse duration, RD high
H – 2
H – 2
2H – 5
– 2
H + 2
H – 2
H – 2
2H – 4
– 3
H + 2
§¶#
w(RDH)
Delay time, RD high to WE low
Delay time, CLKOUT1 to RD rising or falling edge
Delay time, CLKOUT1 to STRB rising or falling edge
d(RDH-WEL)
d(CO-RD)
d(CO-ST)
§¶
2
4
1
2
§¶
0
– 2
†
A0–A15, PS, DS, IS, R/W, and BR timings all are included in timings referenced as address.
See Figure 16 for address bus timing variation with load capacitance.
These timings are for the cycles following the first cycle after reset, which is always seven wait states.
Values are derived from characterization data and not tested.
‡
§
¶
#
Timings are valid for zero wait-state cycles only.
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t
] (’320C5x only) (see Figure 15)
c(CO)
’320C5x-40
’320C5x-57
’320C5x-80
’320C5x-100
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Access time, read data from
address valid
†
†
†
†
t
t
2H – 18
2H – 15
2H – 10
2H – 10
ns
ns
a(RDAV)
Access time, read data after RD
low
H – 10
H – 10
H – 7
H – 6
a(RDL-RD)
Setup time, read data before RD
high
t
t
10
0
10
0
7
0
6
0
ns
ns
su(RD-RDH)
Holdtime, readdataafterRDhigh
h(RDH-RD)
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (’320LC5x only) (see Figure 15)
c(CO)
’320LC5x-40
’320LC5x-50
’320LC5x-80
UNIT
MIN
MAX
MIN
MAX
†
†
t
t
t
t
Access time, read data from address valid
Setup time, read data before RD high
Hold time, read data after RD high
Access time, read data after RD low
2H – 17
2H – 10
ns
ns
ns
ns
a(RDAV)
10
0
7
0
su(RD-RDH)
h(RDH-RD)
a(RDL-RD)
H – 10
H – 7
†
See Figure 16 for address bus timing variation with load capacitance.
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MEMORY AND PARALLEL I/O INTERFACE WRITE
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 15)
] (’320C5x only)
c(CO)
’320C5x-40
MIN MAX
’320C5x-57
MIN MAX
’320C5x-80
MIN MAX
’320C5x-100
MIN MAX
PARAMETER
UNIT
Setup time, address valid
before WE low
‡
‡
‡
‡
t
t
t
t
H – 5
H – 5
H – 4
H – 3
ns
ns
ns
ns
su(AV-WEL)
su(WDV-WEH)
h(WEH-AV)
†
Setup time, write data
valid before WE high
§¶
2H
§¶
2H
§¶
§¶
2H
2H – 20
2H – 20
2H – 14
2H
2H – 14
Hold time, address valid
‡
‡
‡
‡
H – 7
H – 10
H – 10
H – 7
†
after WE high
Holdtime,writedatavalid
after WE high
§
§
§
§
§
§
H + 7
H – 5 H + 10
H – 5 H + 10
H – 4
H + 7
H – 4
h(WEH-WDV)
§¶
t
t
Pulseduration,WElow
2H – 2 2H + 2
2H – 2
2H – 2 2H + 2
2H – 2
2H – 2
2H – 2
2H + 2
2H – 2
2H – 2
2H + 2
ns
ns
w(WEL)
§
Pulseduration, WEhigh
w(WEH)
Delay time, CLKOUT1 to
STRB rising or falling
edge
t
– 1
3
4
– 2
2
3
– 2
2
3
– 2
2
3
ns
d(CO-ST)
§
Delay time, CLKOUT1 to
t
t
t
0
– 1
– 1
– 1
ns
ns
ns
d(CO-WE)
§
WErisingorfallingedge
Delay time, WE high to
RD low
3H – 10
3H – 10
3H – 7
3H – 7
d(WEH-RDL)
en(WEL-BUd)
Enable time, WE low to
data bus driven
§
– 5
§
– 5
§
– 4
§
– 4
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 15)
] (’320LC5x only)
c(CO)
’320LC5x-40
’320LC5x-50
’320LC5x-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
†
‡
‡
t
t
t
t
t
t
t
t
t
t
Setup time, address valid before WE low
H – 7
H – 4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(AV-WEL)
su(WDV-WEH)
h(WEH-AV)
h(WEH-WDV)
w(WEL)
#
§¶
§¶
2H
Setup time, write data valid before WE high
2H – 20
2H
2H – 14
†
‡
‡
H – 7
Hold time, address valid after WE high
H – 10
§
§
Hold time, write data valid after WE high
H – 5
2H – 4
2H – 2
3H – 10
0
H + 10
H – 4
2H – 4
2H – 2
3H – 7
– 2
H + 7
¶§
Pulse duration, WE low
2H + 2
2H + 2
¶
Pulse duration, WE high
w(WEH)
Delay time, WE high to RD low
Delay time, CLKOUT1 to STRB rising or falling edge
d(WEH-RDL)
d(CO-ST)
¶
4
4
2
3
¶
Delay time, CLKOUT1 to WE rising or falling edge
0
– 1
d(CO-WE)
en(WE-BUd)
§
– 5
§
– 4
Enable time, WE to data bus driven
†
A0–A15, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
See Figure 16 for address bus timing variation with load capacitance.
Values derived from characterization data and not tested
This value holds true for zero wait states or one software wait state only.
STRBandWEedgesare0–4nsfromCLKOUT1edgesonwrites. Risingandfallingedgesofthesesignalstrackeachother;toleranceofresulting
‡
§
¶
#
pulsewidths is ±2 ns, not ±4 ns.
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MEMORY AND PARALLEL I/O INTERFACE WRITE (CONTINUED)
A0–A15
R/W
VALID
VALID
t
h(RDH-AV)
t
su(AV-WEL)
t
h(WEH-AV)
t
a(RDAV)
t
a(RDL-RD)
t
su(RD-RDH)
t
t
h(WEH-WDV)
en(WEL-BUd)
t
h(RDH-RD)
DATA
RD
VALID
VALID
t
su(AV-RDL)
t
su(WDV-WEH)
t
d(RDH-WEL)
t
t
w(RDH)
d(WEH-RDL)
t
w(WEL)
t
w(RDL)
t
w(WEH)
WE
t
d(CO-RD)
STRB
t
t
d(CO-ST)
d(CO-WE)
CLKOUT1
NOTES: A. All timings are for 0 wait states. However, external writes always require two cycles to prevent external bus conflicts. The diagram
illustratesaone-cyclereadandatwo-cyclewriteandisnotdrawntoscale.Allexternalwritesimmediatelyprecededbyanexternal
read or immediately followed by an external read require three machine cycles.
B. Refer to Appendix B of TMS320C5x User’s Guide (literature number SPRU056) for logical timings of external interface.
Figure 15. Memory and Parallel I/O Interface Read and Write Timing
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MEMORY AND PARALLEL I/O INTERFACE WRITE (CONTINUED)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
10 15 20 25
30 35 40
45 50 55
60 65 70 75
80 85 90
95 100
Change in Load Capacitance – pF
Figure 16. Address Bus Timing Variation With Load Capacitance
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
READY TIMING FOR EXTERNALLY-GENERATED WAIT STATES
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (see Note 5) (see Figure 17 and Figure 18)
’320C5x-40
’320C5x-80
’320LC5x-80
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-100
UNIT
MIN
10
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
Setup time, READY before CLKOUT1 rising edge
Setup time, READY before RD falling edge
Hold time, READY after CLKOUT1 rising edge
Hold time, READY after RD falling edge
Hold time, READY after WE falling edge
Valid time, READY after WE falling edge
7
6
ns
ns
ns
ns
ns
ns
su(RY-COH)
su(RY-RDL)
h(COH-RYH)
h(RDL-RY)
h(WEL-RY)
v(WEL-RY)
10
7
0
6
0
0
0
0
0
H + 5
H + 4
H + 3
H – 15
H – 10
H – 8
NOTE 5: The external READY input is sampled only after the internal software wait states are completed.
CLKOUT1
t
su(RY-COH)
t
su(RY-COH)
A0–A15
t
h(COH-RYH)
READY
t
Wait State
Generated
by READY
su(RY-RDL)
Wait State
Generated
Internally
RD
t
h(RDL-RY)
Figure 17. Ready Timing for Externally-Generated Wait States During an External Read Cycle
CLKOUT1
t
h(COH-RYH)
A0–A15
READY
t
su(RY-COH)
t
v(WEL-RY)
t
h(WEL-RY)
WE
Wait State Generated by READY
Figure 18. Ready Timing for Externally-Generated Wait States During an External Write Cycle
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
RESET, INTERRUPT, AND BIO
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (see Figure 19)
c(CO)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320C5x-100
’320LC5x-80
UNIT
MIN
MAX
MIN
MAX
†
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, INT1–INT4, NMI before CLKOUT1 low
Setup time, RS before CLKOUT1 low
Setup time, RS before X2/CLKIN low
15
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(IN-COL)
su(RS-COL)
su(RS-CIL)
su(BI-COL)
h(COL-IN)
h(COL-BI)
w(INL)SYN
w(INH)SYN
w(INL)ASY
w(INH)ASY
w(RSL)
‡
‡
10 2H – 5
15 2H – 5
10
15
0
7
10
0
Setup time, BIO before CLKOUT1 low
†
Hold time, INT1–INT4, NMI after CLKOUT1 low
Hold time, BIO after CLKOUT1 low
0
0
§
§
§
§
§
§
§
§
Pulse duration, INT1–INT4, NMI low, synchronous
4H + 15
2H + 15
6H + 15
4H + 15
4H + 10
2H + 10
6H + 10
4H + 10
Pulse duration, INT1–INT4, NMI high, synchronous
Pulse duration, INT1–INT4, NMI low, asynchronous
‡
‡
Pulse duration, INT1–INT4, NMI high, asynchronous
Pulse duration, RS low
12H
15
12H
10
Pulse duration, BIO low, synchronous
w(BIL)SYN
w(BIL)ASY
d(RSH)
‡
Pulse duration, BIO low, asynchronous
H + 15
34H
H + 10
34H
Delay time, RS high to reset vector fetch
†
These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to ensure internal synchronization.
Values derived from characterization data and not tested
‡
§
If in IDLE2, add 4H to these timings.
X2/CLKIN
t
su(RS-CIL)
t
d(RSH)
t
w(RSL)
RS
t
su(RS-COL)
t
su(BI-COL)
CLKOUT1
t
w(BIL)SYN
BIO
t
h(COL-BI)
A0–A15
INT4–INT1
t
t
su(IN-COL)
h(COL-IN)
t
su(IN-COL)
t
w(INL)SYN
t
w(INH)SYN
Figure 19. Reset, Interrupt, and BIO Timings
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6)
switching characteristics over recommended operating conditions [H = 0.5t
] (see Figure 20)
c(CO)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320C5x-100
’320LC5x-80
PARAMETER
UNIT
MIN
MAX
MIN
MAX
†
‡
‡
‡
‡
‡
‡
t
t
t
t
t
t
t
t
t
Setup time, address valid before IAQ low
Hold time, address valid after IAQ low
Pulse duration, IAQ low
H – 12
H – 10
H – 10
H – 9
H – 7
H – 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(AV-IQL)
h(IQL-AV)
w(IQL)
Delay time, CLKOUT1 falling edge to TOUT
– 6
6
– 6
6
9
d(CO-TU)
su(AV-IKL)
h(IKL-AV)
w(IKL)
§
‡
‡
‡
‡
‡
‡
Setup time, address valid before IACK low
Hold time, address valid after IACK low
Pulse duration, IACK low
H – 12
H – 10
H – 10
H – 9
H – 7
H – 7
Pulse duration, TOUT high
2H – 12
0
2H – 9
0
w(TUH)
Delay time, XF valid after CLKOUT1
12
d(CO-XFV)
†
IAQ goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
‡
§
Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on or code is executing off chip)
IACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A1–A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
NOTE 6: IAQ pin is not present on 100-pin packages.
IACK pin is not present on 100-pin and 128-pin packages.
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (IACK),
EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6) (CONTINUED)
t
h(IQL-AV)
ADDRESS
t
su(AV-IQL)
t
w(IQL)
†
†
IAQ
t
h(IKL-AV)
t
su(AV-IKL)
IACK
t
w(IKL)
STRB
CLKOUT1
t
d(CO-XFV)
t
d(CO-TU)
t
d(CO-TU)
XF
TOUT
t
w(TUH)
†
IAQ and IACK are not affected by wait states.
Figure 20. IAQ, IACK, and XF Timings Example With Two External Wait States
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
EXTERNAL DMA
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 21)
] (see Note 7)
c(CO)
’320C5x-40
’320C5x-80
’320LC5x-80
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-100
PARAMETER
UNIT
MIN
4H
MAX
MIN
4H
MAX
MIN
4H
MAX
†
†
†
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, HOLD low to HOLDA low
Delay time, HOLD high before HOLDA high
Address high-impedance before HOLDA low
Enable time, HOLDA high to address driven
Delay time, XBR low to IAQ low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(HOL-HAL)
d(HOH-HAH)
h(AZ-HAL)
en(HAH-Ad)
d(XBL-IQL)
d(XBH-IQH)
d(XSL-RDV)
h(XSH-RD)
en(IQL-RDd)
h(XRL-DZ)
h(IQH-DZ)
2H
2H
2H
‡
§
§
§
§
§
§
H – 15
H – 10
H – 8
H – 3
4H
§
§
§
§
§
§
H – 5
H – 4
§
§
§
§
§
§
4H
6H
4H
6H
6H
Delay time, XBR high to IAQ high
2H
4H
2H
4H
2H
4H
Delay time, read data valid after XSTRB low
Hold time, read data valid after XSTRB high
40
29
25
0
§
0
§
0
§
¶
§
§
§
§
§
§
§
§
§
2H
Enable time, IAQ low to read data driven
0
0
2H
15
H
0
0
2H
10
H
0
0
§
§
§
Hold time, XR/W low to data high impedance
Hold time, IAQ high to data high impedance
Enable time, data from XR/W going high
8
§
H
2
§
4
3
en(D-XRH)
†
HOLD is not acknowledged until current external access request is complete.
This parameter includes all memory control lines.
Values derived from characterization data and not tested
This parameter refers to the delay between the time the condition (IAQ = 0 and XR/W = 1) is satisfied and the time that the ’C5x data linesbecome
valid.
‡
§
¶
NOTE 7: X preceding a name refers to external drive of the signal.
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (see Note 7) (see Figure 21)
’320C5x-40
’320C5x-80
’320LC5x-80
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-100
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
#
§
§
§
t
t
t
t
t
t
t
t
t
t
Delay time, HOLDA low to XBR low
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(HAL-XBL)
d(IQL-XSL)
su(AV-XSL)
su(DV-XSL)
h(XSL-D)
#
§
§
§
Delay time, IAQ low to XSTRB low
Setup time, Xaddress valid before XSTRB low
Setup time, Xdata valid before XSTRB low
Hold time, Xdata hold after XSTRB low
Hold time, write Xaddress hold after XSTRB low
Pulse duration, XSTRB low
15
15
15
15
45
45
20
0
12
12
12
12
40
40
20
0
10
10
10
10
35
35
18
0
h(XSL-WA)
w(XSL)
Pulse duration, XSTRB high
w(XSH)
Setup time, R/W valid before XSTRB low
Hold time, read Xaddress after XSTRB high
su(RW-XSL)
h(XSH-RA)
§
#
Values derived from characterization data and not tested
XBR, XR/W, and XSTRB lines must be pulled up with a 10-kΩ resistor to be certain that they are in an inactive high state during the transition
period between the ’C5x driving them and the external circuit driving them.
NOTE 7: X preceding a name refers to external drive of the signal.
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
EXTERNAL DMA (CONTINUED)
HOLD
t
d(HOH-HAH)
t
d(HOL-HAL)
HOLDA
t
en(HAH-Ad)
t
h(AZ-HAL)
ADDRESS
BUS/
CONTROL
SIGNALS
t
d(HAL-XBL)
XBR
IAQ
t
d(XBL-IQL)
t
d(XBH-IQH)
t
d(IQL-XSL)
XSTRB
XR/W
t
w(XSH)
t
w(XSL)
t
su(RW-XSL)
t
h(XRL-DZ)
t
h(XSH-RA)
t
h(XSH-RD)
t
su(AV-XSL)
t
en(IQL-RDd)
XADDRESS
t
su(AV-XSL)
t
t
d(XSL-RDV)
h(XSL-WA)
t
h(IQH-DZ)
DATA(RD)
t
t
en(IQL-RDd)
en(D-XRH)
t
h(XSL-D)
t
su(DV-XSL)
XDATA(WR)
Figure 21. External DMA Timing
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
SERIAL-PORT RECEIVE TIMING
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (see Figure 22)
c(CO)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320LC5x-80
’320C5x-100
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
†
‡
†
‡
†
‡
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
5.2H
5.2H
5.2H
ns
ns
ns
ns
ns
ns
ns
ns
c(SCK)
§
§
§
§
§
§
Fall time, serial-port clock
8
6
6
f(SCK)
Rise time, serial-port clock
8
6
6
r(SCK)
†
2.1H
†
2.1H
†
2.1H
Pulse duration, serial-port clock low/high
Setup time, FSR before CLKR falling edge
Setup time, DR before CLKR falling edge
Hold time, FSR after CLKR falling edge
Hold time, DR valid after CLKR falling edge
w(SCK)
10
10
10
10
7
7
7
7
6
6
6
6
su(FS-CK)
su(DR-CK)
h(CK-FS)
h(CK-DR)
†
‡
Values ensured by design but not tested
The serial-port design is fully static and, therefore, can operate with t
of 0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and not tested
approaching ∞. It is characterized approaching an input frequency
c(SCK)
§
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKR
t
t
r(SCK)
h(CK-FS)
t
w(SCK)
t
su(FS-CK)
t
su(DR-CK)
FSR
t
h(CK-DR)
DR
Bit
1
2
7/15
8/16
Figure 22. Serial-Port Receive Timing
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
SERIAL-PORT TRANSMIT TIMING, EXTERNAL CLOCKS, AND EXTERNAL FRAMES
switching characteristics over recommended operating conditions (see Note 8) (see Figure 23)
PARAMETER
Delay time, DX valid after CLKX high
MIN
MAX
UNIT
ns
t
t
t
25
d(CXH-DXV)
dis(CXH-DX)
h(CXH-DXV)
†
40
Disable time, DX invalid after CLKX high
Hold time, DX valid after CLKX high
ns
– 5
ns
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (see Note 8) (see Figure 23)
c(CO)
’320C5x-40
’320C5x-80
’320LC5x-80
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-100
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
‡
‡
‡
t
t
t
t
t
t
t
Cycle time, serial-port clock
5.2H
§
†
5.2H
§
†
5.2H
§
†
ns
ns
ns
ns
ns
ns
ns
c(SCK)
Fall time, serial-port clock
8
8
6
6
6
6
f(SCK)
†
†
†
Rise time, serial-port clock
r(SCK)
‡
2.1H
‡
7
‡
6
Pulse duration, serial-port clock low/high
Delay time, FSX high after CLKX high
Hold time, FSX low after CLKX low
Hold time, FSX low after CLKX high
2.1H
2.1H
w(SCK)
2H – 8
2H – 8
2H – 5
d(CXH-FXH)
h(CXL-FXL)
h(CXH-FXL)
10
¶
¶
¶
2H – 5
2H – 8
2H – 8
†
‡
§
Values derived from characterization data and not tested
Values ensured by design but not tested
The serial-port design is fully static and, therefore, can operate with t
of 0 Hz but tested at a much higher frequency to minimize test time.
approaching ∞. It is characterized approaching an input frequency
c(SCK)
¶
If the FSX pulse does not meet this specification, the first bit of serial data is driven on the DX pin until the falling edge of FSX. After the falling
edgeofFSX,dataisshiftedoutontheDXpin.Thetransmitbufferemptyinterruptisgeneratedwhenthet
is met.
andt
specification
h(CXH-FXL)
h(CXL-FXL)
NOTE 8: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent on the source of CLKX. Specifically, the relationship of FSX to CLKX is
independent of the source of CLKX.
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKX
FSX
t
t
d(CXH-FXH)
r(SCK)
t
h(CXH-FXL)
t
w(SCK)
t
h(CXL-FXL)
t
d(CXH-DXV)
t
dis(CXH-DX)
t
h(CXH-DXV)
DX
BIt
1
2
7/15
8/16
Figure 23. Serial-Port Transmit Timing of External Clocks and External Frames
70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
SERIAL-PORT TRANSMIT TIMING, INTERNAL CLOCKS, AND INTERNAL FRAMES
(SEE NOTE 8)
switching characteristics over recommended operating conditions [H = 0.5t
] (see Figure 24)
c(CO)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320C5x-100
’320LC5x-80
PARAMETER
UNIT
MIN
TYP
MAX
25
MIN
TYP
MAX
18
t
t
t
t
t
t
t
t
Delay time, CLKX rising edge to FSX
Delay time, CLKX rising edge to DX
Disable time, CLKX rising edge to DX
Cycle time, serial-port clock
– 5
– 4
ns
ns
ns
ns
ns
ns
ns
ns
d(CX-FX)
d(CX-DX)
dis(CX-DX)
c(SCK)
25
18
†
40
†
29
8H
5
8H
4
Fall time, serial-port clock
f(SCK)
Rise time, serial-port clock
5
4
r(SCK)
Pulse duration, serial-port clock low/high
Hold time, DX valid after CLKX high
4H – 20
– 5
4H – 14
– 4
w(SCK)
h(CXH-DXV)
†
Values derived from characterization data and not tested
NOTE 8: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent on the source of CLKX. Specifically, the relationship of FSX to CLKX is
independent of the source of CLKX.
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKX
FSX
t
d(CX-FX)
t
t
w(SCK)
r(SCK)
t
d(CX-FX)
t
d(CX-DX)
t
dis(CX-DX)
t
h(CXH-DXV)
DX
Bit
1
2
7 /15
8/16
Figure 24. Serial-Port Transmit Timing of Internal Clocks and Internal Frames
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
SERIAL-PORT RECEIVE TIMING IN TDM MODE
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (see Figure 25)
c(CO)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-80
’320LC5x-80
’320C5x-100
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
†
‡
¶
¶
†
‡
¶
¶
§
‡
¶
¶
t
t
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
5.2H
5.2H
5.2H
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCK)
Fall time, serial-port clock
8
8
8
8
8
8
f(SCK)
Rise time, serial-port clock
r(SCK)
†
2.1H
†
2.1H
†
2.1H
Pulse duration, serial-port clock low/high
Setup time, TDAT before TCLK rising edge
Hold time, TDAT after TCLK rising edge
Setup time, TADD before TCLK rising edge
w(SCK)
30
– 3
20
21
– 2
12
18
– 2
10
su(TD-TCH)
h(TCH-TD)
su(TA-TCH)
h(TCH-TA)
su(TF-TCH)
h(TCH-TF)
#
#
Hold time, TADD after TCLK rising edge
– 3
10
– 2
10
– 2
10
§
Setup time, TFRM before TCLK rising edge
§
Hold time, TFRM after TCLK rising edge
10
10
10
†
‡
Values ensured by design and are not tested
The serial-port design is fully static and, therefore, can operate with t
of 0 Hz but tested at a much higher frequency to minimize test time.
TFRM timing and waveforms shown in Figure 25 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 26.
Values derived from characterization data and not tested
approaching ∞. It is characterized approaching an input frequency
c(SCK)
§
¶
#
These parameters apply only to the first bits in the serial bit string.
t
t
w(SCK)
t
f(SCK)
t
r(SCK)
w(SCK)
TCLK
TDAT
TADD
TFRM
t
su(TD-TCH)
t
c(SCK)
B15
t
h(TCH-TD)
B13
B1
B0
B0
B14
su(TA-TCH)
B12 B8
B7
B2
t
t
h(TCH-TA)
t
h(TCH-TA)
A1
A0
A2
A3
A7
t
su(TF-TCH)
t
h(TCH-TF)
Figure 25. Serial-Port Receive Timing in TDM Mode
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
SERIAL-PORT TRANSMIT TIMING IN TDM MODE
switching characteristics over recommended operating conditions [H = 0.5t
] (see Figure 26)
c(CO)
’320C5x-40
’320C5x-80
’320LC5x-80
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-100
PARAMETER
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
MAX
t
t
t
Hold time, TDAT/TADD valid after TCLK rising edge
0
ns
ns
ns
h(TCH-TDV)
d(TCH-TFV)
d(TC-TDV)
†
Delay time, TFRM valid after TCLK rising edge
Delay time, TCLK to valid TDAT/TADD
H
3H + 10
20
H
3H + 7
15
3H + 5
12
†
TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is
illustrated in the receive timing diagram in Figure 27.
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (see Figure 26)
c(CO)
’320C5x-40
’320C5x-80
’320LC5x-80
’320C5x-57
’320LC5x-40
’320LC5x-50
’320C5x-100
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
‡
5.2H
§
8H
¶
‡
5.2H
§
8H
¶
‡
5.2H
§
8H
¶
t
t
t
Cycle time, serial-port clock
Fall time, serial-port clock
Rise time, serial-port clock
ns
ns
ns
c(SCK)
f(SCK)
r(SCK)
8#
8#
6#
6#
5#
5#
Pulse duration, serial-port clock low/
high
‡
2.1H
‡
2.1H
‡
2.1H
t
ns
w(SCK)
‡
§
¶
Values ensured by design and are not tested
When SCK is generated internally
The serial-port design is fully static and, therefore, can operate with t
approaching ∞. It is characterized approaching an input frequency
c(SCK)
of 0 Hz but tested as a much higher frequency to minimize test time.
Values derived from characterization data and not tested
#
t
f(SCK)
t
w(SCK)
t
w(SCK)
t
r(SCK)
TCLK
t
c(SCK)
t
d(TC-TDV)
B15
TDAT
TADD
B0
h(TCH-TDV)
B14
B13
A2
B12
A3
B8 B7
B2
B1
B0
t
t
h(TCH-TDV)
d(TC-TDV)
t
A1
A7
t
d(TCH-TFV)
A0
t
d(TCH-TFV)
TFRM
Figure 26. Serial-Port Transmit Timing in TDM Mode
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
BUFFERED SERIAL-PORT RECEIVE TIMING
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t ] (see Figure 27)
c(CO)
MIN
MAX
UNIT
ns
†
t
t
t
t
t
t
t
t
Cycle time, serial-port clock
25
c(SCK)
‡
‡
Fall time, serial-port clock
6
ns
f(SCK)
Rise time, serial-port clock
6
ns
r(SCK)
Pulse duration, serial-port clock low/high
Setup time, FSR before CLKR falling edge
Setup time, DR before CLKR falling edge
Hold time, FSR after CLKR falling edge
Hold time, DR after CLKR falling edge
12
2
ns
w(SCK)
ns
su(FS-CK)
su(DR-CK)
h(CK-FS)
h(CK-DR)
0
ns
§
12
15
t
ns
c(SCK)
ns
†
The serial-port design is fully static and, therefore, can operate with t
of 0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and not tested
approaching ∞. It is characterized approaching an input frequency
c(SCK)
‡
§
First bit is read when FSR is sampled low by CLKR clock.
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKR
t
t
r(SCK)
h(CK-FS)
t
w(SCK)
t
su(FS-CK)
t
su(DR-CK)
FSR
t
h(CK-DR)
DR
Bit
1
2
7/15
8/16
Figure 27. Buffered Serial-Port Receive Timing
74
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
BUFFERED SERIAL-PORT TRANSMIT TIMING OF EXTERNAL FRAMES (SEE NOTES 9 AND 10)
switching characteristics over recommended operating conditions (see Figure 28)
PARAMETER
MIN
5
MAX
21
UNIT
ns
t
t
t
t
t
Delay time, DX valid after CLKX rising edge
d(CXH-DXV)
Disable time, DX invalid after CLKX rising edge
Disable time in PCM mode, DX invalid after CLKX rising edge
Enable time in PCM mode, DX valid after CLKX rising edge
Hold time, DX valid after CLKX rising edge
5
15
ns
dis(CXH-DX)
15
ns
dis(CXH-DX)PCM
en(CXH-DX)PCM
h(CXH-DXV)
21
5
ns
20
ns
timing requirements over recommended operating conditions (see Figure 28)
MIN
MAX
UNIT
ns
†
t
t
t
t
t
t
Cycle time, serial-port clock
25
c(SCK)
‡
Fall time, serial-port clock
4
4
ns
f(SCK)
‡
Rise time, serial-port clock
ns
r(SCK)
Pulse duration, serial-port clock low/high
Setup time, FSX before CLKX falling edge
Hold time, FSX after CLKX falling edge
8.5
5
ns
w(SCK)
ns
su(FX-CXL)
h(CXL-FX)
§
–5
5
t
ns
c(SCK)
†
The serial-port design is fully static and, therefore, can operate with t
of 0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and not tested
If the FSX pulse does not meet this specification, the first bit of the serial data is driven on the DX pin until FSX goes low (sampled on falling edge
of CLKX). After falling edge of the FSX, data is shifted out on the DX pin.
approaching ∞. It is characterized approaching an input frequency
c(SCK)
‡
§
NOTE 9: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX. External FSX timings are obtained from the “timing requirements over recommended operating
conditions” table listed in the “Buffered Serial-Port Transmit Timing of External Frames” section and internal FSX timings are obtained
fromthe“switchingcharacteristicsoverrecommendedoperatingconditions”tablelistedunderthe“BufferedSerial-PortTransmitTiming
ofInternalFrameandInternalClock”section. InternalCLKXtimingsareobtainedfromthe“switchingcharacteristicsoverrecommended
operating conditions” table listed under the “Buffered Serial-Port Transmit Timing of Internal Frame and Internal Clock” section and
external CLKX timings are obtained from the “timing requirements over recommended operating conditions” table in the “Buffered
Serial-Port Transmit Timing of External Frames” section.
NOTE 10: Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0
t
c(SCK)
t
f(SCK)
t
w(SCK)
CLKX
t
t
r(SCK)
su(FX-CXL)
t
h(CXL-FX)
t
w(SCK)
FSX
t
d(CXH-DXV)
t
dis(CXH-DX)
t
h(CXH-DXV)
DX BIt
1
2
7/15
8/16
Figure 28. Buffered Serial-Port Transmit Timing of External Clocks and External Frames
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
BUFFERED SERIAL-PORT TRANSMIT TIMING OF INTERNAL FRAME AND INTERNAL CLOCK
(SEE NOTES 9 AND 10)
switching characteristics over recommended operating conditions [H = 0.5t
] (see Figure 29)
c(CO)
PARAMETER
MIN
MAX
10
10
10
8
UNIT
ns
t
t
t
t
t
t
t
t
t
Delay time, FSX high after CLKX rising edge
Delay time, FSX low after CLKX rising edge
Delay time, DX valid after CLKX rising edge
Disable time, DX invalid after CLKX rising edge
Disable time in PCM mode, DX invalid after CLKX rising edge
Enable time in PCM mode, DX valid after CLKX rising edge
Cycle time, serial-port clock
d(CXH-FXH)
d(CXH-FXL)
d(CXH-DXV)
dis(CXH-DX)
dis(CXH-DX)PCM
en(CXH-DX)PCM
c(SCK)
ns
5
4
ns
ns
10
ns
16
ns
2H
62H
ns
†
Fall time, serial-port clock
4
4
ns
f(SCK)
†
Rise time, serial-port clock
ns
r(SCK)
t
t
Pulse duration, serial-port clock low/high
Hold time, DX valid after CLKX rising edge
H–4
4
ns
ns
w(SCK)
8
h(CXH-DXV)
†
Values derived from characterization data and not tested
NOTES: 9. Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending
on the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to
CLKX is independent of the source of CLKX. External FSX timings are obtained from the “timing requirements over recommended
operating conditions” table listed in the “Buffered Serial-Port Transmit Timing of External Frames” section and internal FSX timings
areobtainedfromthe“switchingcharacteristicsoverrecommendedoperatingconditions”tablelistedunderthe“BufferedSerial-Port
TransmitTimingofInternalFrameandInternalClock”section. InternalCLKXtimingsareobtainedfromthe“switchingcharacteristics
over recommended operating conditions” table listed under the “Buffered Serial-Port Transmit Timing of Internal Frame and Internal
Clock”sectionandexternalCLKXtimingsareobtainedfromthe“timingrequirementsoverrecommendedoperatingconditions”table
in the “Buffered Serial-Port Transmit Timing of External Frames” section.
10. Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0.
t
c(SCK)
t
t
f(SCK)
d(CXH-FXH)
t
w(SCK)
CLKX
FSX
t
t
w(SCK)
r(SCK)
t
d(CXH-FXL)
t
d(CXH-DXV)
t
dis(CXH-DX)
t
h(CXH-DXV)
DX
Bit
1
2
7 /15
8/16
Figure 29. Buffered Serial-Port Transmit Timing of Internal Clocks and Internal Frames
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY)
switching characteristics over recommended operating conditions [H = 0.5t
and 12) (see Figure 30 through Figure 33)
] (See Notes 11
c(CO)
PARAMETER
Delay time, DS low to HD valid
Delay time, HDS falling to HD valid for first byte of a subsequent read:
MIN
MAX
UNIT
t
5
ns
d(DSL-HDV)
d(HEL-HDV1)
† ‡
Case 1: Shared-access mode if t
Case 2: Shared-access mode if t
< 7H
> 7H
7H+20–t
40–t
w(HDS)h
w(HDS)h
w(DSH)
20
t
ns
Case 3: Host-only mode if t
Case 4: Host-only mode if t
< 7H
> 7H
w(HDS)h
w(HDS)h
w(DSH)
20
t
t
t
t
t
t
t
Delay time, DS low to HD valid, second byte
Delay time, DS high to HRDY high
20
ns
ns
ns
ns
ns
ns
ns
d(DSL-HDV2)
d(DSH-HYH)
su(HDV-HYH)
h(DSH-HDV)
d(COH-HYH)
d(DSH-HYL)
d(COH-HTX)
Setup time, HD valid before HRDY rising edge
Hold time, HD valid after DS rising edge
Delay time, CLKOUT rising edge to HRDY high
Delay time, HDS or HCS high to HRDY low
3H–10
0
§
12
10
12
10
Delay time, CLKOUT rising edge to HINT change
†
Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
Shared-access mode timings are met automatically if HRDY is used.
HD release
‡
§
NOTES: 11. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
12. On host-read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be
specified here.
timing requirements over recommended operating conditions [H = 0.5t
(see Figure 30 through Figure 33)
] (See Note 11)
c(CO)
MIN
10
MAX
UNIT
ns
#
Setup time, HAD/HBIL valid before HAS or DS falling edge
t
t
t
t
t
su(HBV-DSL)
h(DSL-HBV)
su(HSL-DSL)
w(DSL)
#
Hold time, HAD/HBIL valid after HAS or DS falling edge
Setup time, HAS low before DS falling edge
Pulse duration, DS low
10
ns
10
ns
25
ns
Pulse duration, DS high
10
ns
w(DSH)
Cycle time, DS rising edge to next DS rising edge:
Case 1: When using HRDY (see Figure 32)
Case 2a: SAM accesses and HOM active writes to DSPINT or HINT without using HRDY 10H
(see Figure 30 and Figure 31)
50
¶
t
ns
c(DSH-DSH)
Case 2b: When not using HRDY for other HOM accesses
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge
50
10
0
t
t
ns
ns
su(HDV-DSH)
h(DSH-HDV)
¶
A host not using HRDY must meet the 10 H requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
#
When HAS is tied to V , timing is referenced to DS.
DD
NOTE 11: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRL0, HCNTRL1, and HR/W.
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
FIRST BYTE
SECOND BYTE
Valid
Valid
Valid
HAD
t
h(DSL-HBV)
t
h(DSL-HBV)
t
su(HBV-DSL)
t
su(HBV-DSL)
HBIL
t
t
w(DSH)
w(DSH)
t
w(DSL)
t
w(DSL)
HCS
HDS
t
c(DSH-DSH)
t
d(DSL-HDV2)
Valid
t
d(HEL-HDV1)
t
h(DSH-HDV)
t
h(DSH-HDV)
t
d(DSL-HDV)
HD
READ
Valid
t
t
su(HDV-DSH)
su(HDV-DSH)
t
t
h(DSH-HDV)
h(DSH-HDV)
HD
WRITE
Valid
Valid
Figure 30. Read/Write Access Timings Without HRDY or HAS
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
FIRST BYTE
SECOND BYTE
HAS
t
su(HSL-DSL)
t
h(DSL-HBV)
Valid
Valid
Valid
HAD
HBIL
t
su(HBV-DSL)
t
c(DSH-DSH)
t
w(DSH)
t
c(DSH-DSH)
t
w(DSL)
HCS
HDS
t
d(HEL-HDV1)
t
d(DSL-HDV2)
Valid
t
h(DSH-HDV)
t
h(DSH-HDV)
t
d(DSL-HDV)
t
HD
READ
Valid
t
su(HDV-DSH)
su(HDV-DSH)
t
h(DSH-HDV)
t
h(DSH-HDV)
HD
WRITE
Valid
Valid
Figure 31. Read/Write Access Timings Using HAS Without HRDY
79
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
FIRST BYTE
SECOND BYTE
HAS
t
su(HSL-DSL)
t
su(HBV-DSL)
t
h(DSL-HBV)
HAD
†
t
h(DSL-HBV)
†
t
su(HBV-DSL)
HBIL
t
c(DSH-DSH)
t
w(DSH)
t
w(DSL)
HCS
HDS
t
su(HDV-HYH)
t
d(DSH-HYH)
HRDY
t
d(DSH-HYL)
Valid
t
d(DSL-HDV2)
Valid
t
d(HEL-HDV1)
t
h(DSH-HDV)
t
h(DSH-HDV)
t
d(DSL-HDV)
HD
READ
t
su(HDV-DSH)
t
su(HDV-DSH)
t
h(DSH-HDV)
t
h(DSH-HDV)
HD
WRITE
Valid
Valid
t
d(COH-HYH)
CLKOUT
HINT
t
d(COH-HTX)
†
When HAS is tied to V
DD
Figure 32. Read/Write Access Timing With HRDY
80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
HCS
t
d(DSH-HYL)
HRDY
HDS
t
d(DSH-HYH)
Figure 33. HRDY Signal When HCS Is Always Low
81
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MECHANICAL DATA
PQ (S-PQFP-G132)
PLASTIC QUAD FLATPACK
17
1 132
117
18
116
0.012 (0,30)
0.008 (0,20)
0.006 (0,15)
M
0.800
(20,32)
SQ
0.025 (0,635)
84
0.006
(0,16)
NOM
50
0.150 (3,81)
0.130 (3,30)
51
83
0.966 (24,54)
0.934 (23,72)
1.090 (27,69)
1.070 (27,18)
1.112 (28,25)
1.088 (27,64)
SQ
SQ
SQ
Gage Plane
0.010 (0,25)
0.020
(0,51) MIN
0°–8°
0.046 (1,17)
0.036 (0,91)
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
Thermal Resistance Characteristics
PARAMETER
°C/W
R
35
ΘJA
ΘJC
R
8.5
82
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MECHANICAL DATA
PBK (S-PQFP-G128)
PLASTIC QUAD FLATPACK
0,23
0,40
96
M
0,07
64
0,13
65
97
128
33
0,13 NOM
1
32
Gage Plane
11,60 TYP
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040279-3/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Thermal Resistance Characteristics
PARAMETER
°C/W
R
58
ΘJA
ΘJC
R
10
83
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MECHANICAL DATA
PJ (R-PQFP-G100)
PLASTIC QUAD FLATPACK
0,40
M
0,65
0,13
0,20
80
51
81
50
14,20 18,00
13,80 17,20
12,35 TYP
100
31
1
30
0,15 NOM
18,85 TYP
20,20
19,80
24,00
23,20
Gage Plane
0,25
0,10 MIN
0°–10°
2,70 TYP
1,10
0,70
Seating Plane
3,10 MAX
0,15
4040012/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.
Thermal Resistance Characteristics
PARAMETER
°C/W
R
78
ΘJA
ΘJC
R
13
84
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MECHANICAL DATA
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,50
75
M
0,08
0,17
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
Thermal Resistance Characteristics
PARAMETER °C/W
R
R
58
10
ΘJA
ΘJC
85
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
M
0,08
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
19,80
SQ
SQ
0,25
0,05 MIN
22,20
21,80
0°–7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
Thermal Resistance Characteristics
PARAMETER
°C/W
R
40
ΘJA
ΘJC
R
9.9
86
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
Drawing
PBK
PQ
TMP320LBC57PBK80
TMS320BC51PQ
OBSOLETE
OBSOLETE
NRND
128
132
132
132
132
132
132
132
132
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
TMS320BC51PQ100
TMS320BC51PQ57
TMS320BC51PQ80
TMS320BC51PQA
PQ
36
36
36
CU SNPB
CU SNPB
CU SNPB
Call TI
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Call TI
NRND
PQ
NRND
PQ
OBSOLETE
NRND
PQ
TMS320BC51PQA57
TMS320BC51PQA80
TMS320BC51PQA80G4
PQ
36
36
CU SNPB
CU SNPB
Level-4-220C-72HR
Level-4-220C-72HR
NRND
PQ
OBSOLETE
PQ
Green (RoHS & CU NIPDAU Level-4-260C-72HR
no Sb/Br)
TMS320BC51PZ
OBSOLETE
NRND
LQFP
LQFP
PZ
PZ
100
100
TBD
Call TI
Call TI
TMS320BC51PZ100
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320BC51PZ57
TMS320BC51PZ80
TMS320BC51PZA
TMS320BC51PZA57
NRND
NRND
LQFP
LQFP
LQFP
LQFP
PZ
PZ
PZ
PZ
100
100
100
100
90
90
TBD
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
OBSOLETE
NRND
Call TI
Call TI
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320BC52PJ
TMS320BC52PJ100
TMS320BC52PJ57
OBSOLETE
NRND
QFP
QFP
QFP
PJ
PJ
PJ
100
100
100
TBD
TBD
Call TI
Call TI
66
CUCU NIPDAU Level-4-220C-72HR
NRND
66 Green (RoHS & CUCU NIPDAU Level-4-260C-72HR
no Sb/Br)
TMS320BC52PJ80
NRND
QFP
PJ
100
66 Green (RoHS & CUCU NIPDAU Level-4-260C-72HR
no Sb/Br)
TMS320BC52PJA
OBSOLETE
NRND
QFP
QFP
PJ
PJ
100
100
TBD
Call TI
Call TI
TMS320BC52PJA57
66 Green (RoHS & CUCU NIPDAU Level-4-260C-72HR
no Sb/Br)
TMS320BC52PJA57G4
NRND
QFP
PJ
100
66 Green (RoHS & CUCU NIPDAU Level-4-260C-72HR
no Sb/Br)
TMS320BC52PZ
OBSOLETE
NRND
LQFP
LQFP
PZ
PZ
100
100
TBD
Call TI
Call TI
TMS320BC52PZ100
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320BC52PZ57
TMS320BC52PZ80
NRND
NRND
LQFP
LQFP
PZ
PZ
100
100
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320BC52PZA
TMS320BC52PZA57
TMS320BC53PQ
OBSOLETE
NRND
LQFP
LQFP
BQFP
BQFP
BQFP
BQFP
BQFP
LQFP
LQFP
PZ
PZ
PQ
PQ
PQ
PQ
PQ
PZ
PZ
100
100
132
132
132
132
132
100
100
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
90
CU NIPDAU Level-1-220C-UNLIM
OBSOLETE
NRND
Call TI
CU SNPB
CU SNPB
Call TI
Call TI
TMS320BC53PQ57
TMS320BC53PQ80
TMS320BC53PQA
TMS320BC53PQA57
TMS320BC53SPZ
TMS320BC53SPZ57
36
36
Level-4-220C-72HR
Level-4-220C-72HR
Call TI
NRND
OBSOLETE
NRND
36
CU SNPB
Call TI
Level-4-220C-72HR
Call TI
OBSOLETE
NRND
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TMS320BC53SPZ80
TMS320BC57SPGE57
TMS320BC57SPGE80
NRND
NRND
NRND
LQFP
LQFP
LQFP
PZ
100
144
144
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PGE
PGE
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320C50PGE
OBSOLETE
NRND
LQFP
LQFP
PGE
PGE
144
144
TBD
Call TI
Call TI
TMS320C50PGE57
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320C50PGE80
TMS320C50PGEA57
NRND
NRND
LQFP
LQFP
PGE
PGE
144
144
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320C50PQ
OBSOLETE
NRND
BQFP
BQFP
PQ
PQ
132
132
TBD
Call TI
Call TI
TMS320C50PQ57
36 Green (RoHS & CU NIPDAU Level-4-260C-72HR
no Sb/Br)
TMS320C50PQ80
TMS320C50PQA
TMS320C50PQA57
TMS320C51PQ
NRND
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
BQFP
LQFP
LQFP
LQFP
LQFP
LQFP
QFP
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PQ
PZ
PZ
PZ
PZ
PZ
PJ
132
132
132
132
132
132
132
132
132
132
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
132
132
36
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CU NIPDAU Level-4-220C-72HR
Call TI Call TI
CU NIPDAU Level-4-220C-72HR
OBSOLETE
NRND
36
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
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Call TI
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TMS320C51PQ100
TMS320C51PQ57
TMS320C51PQ80
TMS320C51PQA
TMS320C51PQA57
TMS320C51PQA80
TMS320C51PZ
TMS320C51PZ100
TMS320C51PZ57
TMS320C51PZ80
TMS320C51PZA
TMS320C52PJ
TMS320C52PJ100
TMS320C52PJ57
TMS320C52PJ80
TMS320C52PJA
TMS320C52PJA57
TMS320C52PZ
QFP
PJ
QFP
PJ
QFP
PJ
QFP
PJ
QFP
PJ
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
BQFP
BQFP
PZ
PZ
PZ
PZ
PZ
PZ
PQ
PQ
TMS320C52PZ100
TMS320C52PZ57
TMS320C52PZ80
TMS320C52PZA
TMS320C52PZA57
TMS320C53PQ
TMS320C53PQ57
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2005
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
BQFP
BQFP
LQFP
BQFP
BQFP
LQFP
LQFP
LQFP
LQFP
Drawing
TMS320C53PQ80
TMS320C53PQA
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
NRND
PQ
132
132
100
132
132
100
100
100
100
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
PQ
Call TI
TMS320C53SPZ
PZ
Call TI
Call TI
TMS320LBC51PQ57
TMS320LBC51PQA57
TMS320LBC51PZ
TMS320LBC51PZ57
TMS320LBC51PZA
TMS320LBC51PZA57
PQ
Call TI
Call TI
PQ
36
CU SNPB
Call TI
Level-4-220C-72HR
Call TI
OBSOLETE
OBSOLETE
OBSOLETE
NRND
PZ
PZ
Call TI
Call TI
PZ
Call TI
Call TI
PZ
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320LBC52PJ
TMS320LBC52PJ57
TMS320LBC52PJA
TMS320LBC52PJA57
TMS320LBC52PZ57
TMS320LBC52PZA57
OBSOLETE
NRND
QFP
QFP
PJ
PJ
PJ
PJ
PZ
PZ
100
100
100
100
100
100
TBD
TBD
TBD
TBD
TBD
Call TI
CU SNPB
Call TI
Call TI
66
Level-4-220C-72HR
Call TI
OBSOLETE
OBSOLETE
NRND
QFP
QFP
CU SNPB
Level-4-220C-72HR
LQFP
LQFP
90
CU NIPDAU Level-1-220C-UNLIM
NRND
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320LBC53PQ
TMS320LBC53PQ57
TMS320LBC53SPZ
TMS320LBC53SPZ57
TMS320LBC53SPZ80
TMS320LBC53SPZA57
OBSOLETE
NRND
BQFP
BQFP
LQFP
LQFP
LQFP
LQFP
PQ
PQ
PZ
PZ
PZ
PZ
132
132
100
100
100
100
TBD
TBD
TBD
TBD
TBD
Call TI
CU SNPB
Call TI
Call TI
36
90
Level-4-220C-72HR
Call TI
OBSOLETE
OBSOLETE
NRND
Call TI
Call TI
CU NIPDAU Level-1-220C-UNLIM
NRND
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320LBC56PZ57
TMS320LBC56PZ80
NRND
NRND
LQFP
LQFP
PZ
PZ
100
100
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320LBC57PBK57
TMS320LBC57PBK80
TMS320LBC57PGE57
NRND
NRND
NRND
LQFP
LQFP
LQFP
PBK
PBK
PGE
128
128
144
90
90
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320LBC57PGE80
NRND
LQFP
PGE
144
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TMS320LC50PQ
TMS320LC50PQ50
TMS320LC50PQ57
TMS320LC50PQA
TMS320LC51PZ
OBSOLETE
NRND
BQFP
BQFP
BQFP
BQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PQ
PQ
PQ
PQ
PZ
PZ
PZ
PZ
PZ
PZ
PZ
132
132
132
132
100
100
100
100
100
100
100
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
36
36
36
CU SNPB
Level-4-220C-72HR
NRND
CU NIPDAU Level-4-220C-72HR
CU NIPDAU Level-4-220C-72HR
NRND
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
TMS320LC51PZ57
TMS320LC52PZ
TMS320LC52PZ57
TMS320LC52PZA
TMS320LC53SPZ
TMS320LC53SPZ50
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2005
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
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Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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dsp.ti.com
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www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
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Logic
interface.ti.com
logic.ti.com
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power.ti.com
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www.ti.com/opticalnetwork
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microcontroller.ti.com
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www.ti.com/wireless
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