TMS320C10FNA_技术文档

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

• Performance Up to 8.77 MIPs

• Commercial and Military Versions Available

• All TMS320C1x Devices are Object Code

• Operating Free-Air Temperature

. . . 0°C to 70°C

Compatible

• 144/256-Word On-Chip Data RAM

• Packaging: DIP, PLCC, Quad Flatpack, and

• 1.5K/4K/8K-Word On-Chip Program ROM

CER-QUAD

• 4K-Word On-Chip Program EPROM

• CMOS Technology:

(TMS320E14/P14/E15/P15/E17/P17)

Device

Cycle Time

• One-Time Programmable (OTP)

— TMS320C10 . . . . . . . . . . . . . . . . . . . 200-ns

— TMS320C10-14 . . . . . . . . . . . . . . . . 280-ns

— TMS320C10-25 . . . . . . . . . . . . . . . . 160-ns

— TMS320C14 . . . . . . . . . . . . . . . . . . . 160-ns

— TMS320E14 . . . . . . . . . . . . . . . . . . . 160-ns

— TMS320P14 . . . . . . . . . . . . . . . . . . . 160-ns

— TMS320C15 . . . . . . . . . . . . . . . . . . . 200-ns

— TMS320C15-25 . . . . . . . . . . . . . . . . 160-ns

— TMS320E15 . . . . . . . . . . . . . . . . . . . 200-ns

— TMS320E15-25 . . . . . . . . . . . . . . . . 160-ns

— TMS320LC15 . . . . . . . . . . . . . . . . . . 250-ns

— TMS320P15 . . . . . . . . . . . . . . . . . . . 200-ns

— TMS320C16 . . . . . . . . . . . . . . . . . . . 114-ns

— TMS320C17 . . . . . . . . . . . . . . . . . . . 200-ns

— TMS320E17 . . . . . . . . . . . . . . . . . . . 200-ns

— TMS320LC17 . . . . . . . . . . . . . . . . . . 278-ns

— TMS320P17 . . . . . . . . . . . . . . . . . . . 200-ns

Versions Available (TMS320P14/P15/P17)

• EPROM Code Protection for Copyright

Security

• 4K / 64K-Word Total External Memory at

Full Speed

• 32-Bit ALU/Accumulator

• 16 × 16-Bit Multiplier With a 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• Eight Input/Output Channels

• Dual-Channel Serial Port

• Simple Memory and I/O Interface

• 5-V and 3.3-V Versions Available

(TMS320LC15/LC17)

introduction

TheTMS32010digitalsignalprocessor(DSP), introducedin1983, wasthefirstDSPintheTMS320family. From

it has evolved this TMS320C1x generation of 16-bit DSPs. All ′C1x DSPs are object code compatible with the

TMS32010 DSP. The ′C1x DSPs combine the flexibility of a high-speed controller with the numerical capability

of an array processor, thereby offering an inexpensive alternative to multichip bit-slice processors. The highly

paralleled architecture and efficient instruction set provide speed and flexibility to produce a CMOS

microprocessorgenerationcapableofexecutingupto8.77MIPS(millioninstructionspersecond)(′C16). These

′C1x devices utilize a modified Harvard architecture to optimize speed and flexibility, implementing functions in

hardware that other processors implement through microcode or software.

The ′C1x generation’s powerful instruction set, inherent flexibility, high-speed number-handling capabilities,

reduced power consumption, and innovative architecture have made these cost-effective DSPs the ideal

solution for many telecommunications, computer, commercial, industrial, and military applications.

This data sheet provides detailed design documentation for the ′C1x DSPs. It facilitates the selection of devices

best suited for various user applications by providing specifications and special features for each ′C1x DSP.

This data sheet is arranged as follows: introduction, quick reference table of device parameters and packages,

summary overview of each device, architecture overview, and the ′C1x device instruction set summary. These

are followed by data sheets for each ′C1x device providing available package styles, terminal function tables,

block diagrams, and electrical and timing parameters. An index is provided to facilitate data sheet usage.

PRODUCTION DATA information is current as of

publication date. Products conform to specifications

per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include

testing of all parameters.

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1

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Table1providesanoverviewof′C1xprocessorswithcomparisonsofmemory, I/O, cycletiming, militarysupport,

and package types. For specific availability, contact the nearest TI Field Sales Office.

Table 1. TMS320C1x Device Overview

MEMORY

ROM EPROM

I/O

CYCLE

(ns)

200

280

160

200

160

200

160

250

200

114

PACKAGE (1)

DEVICE

RAM

144

256

PROG.

4K

64K

—

SERIAL PARALLEL

DIP

40

—

PLCC

44

68

—

CER-QUAD

TMS320C10 (2)

TMS320C10-14

TMS320C10-25

TMS320C14 (3)

TMS320E14 (3)

1.5K

4K

—

4K

—

4K

—

4K

—

4K

—

4K

—

1

8 × 16

—

8 × 16

—

7 × 16 (4)

8 × 16

—

1

—

68 CER

—

†

TMS320P14

—

1

—

68

44

—

TMS320C15 (3)

TMS320C15-25

TMS320E15 (3)

TMS320E15-25

TMS320LC15

4K

—

2

40

—

8 × 16

—

8 × 16

44 CER

—

8 × 16

—

4K

—

8 × 16

44

—

†

TMS320P15

8 × 16

—

TMS320C16

8K

4K

—

8 × 16

64 QFP

—

TMS320C17

6 × 16 (5)

200

278

200

40

44

—

TMS320E17 (5)

TMS320LC17 (5)

—

2

44 CER

—

4K

—

2

44

†

TMS320P17 (5)

—

2

†

One-time programmable (OTP) device is in a windowless plastic package and cannot be erased.

NOTES: 1. DIP = dual in-line package. PLCC = plastic-leaded chip carrier. CER = ceramic-leaded chip carrier. QFP = plastic quad flat pack.

2. Military version available.

3. Military versions planned; contact nearest TI Field Sales Office for availability.

4. On-chip 16-bit I/O, four capture inputs, and six compare outputs are available.

5. On-chip 16-bit coprocessor interface is optional by pin selection.

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

description

TMS320C10

The ′C10 provides the core CPU used in all other ′C1x devices. Its microprocessor operates at 5 MIPS. It

provides a parallel I/O of 8 × 16 bits. Three versions with cycle times of 160, 200, and 280 ns are available as

illustrated in Table 1. The ′C10 versions are offered in plastic 40-pin DIP or a 44-lead PLCC packages.

TMS320C14/E14/P14

The ′C14/E14/P14 devices, using the ′C10 core CPU, offer expanded on-chip RAM, and ROM or EPROM

(′E14/P14), 16 pins of bit selectable parallel I/O, an I/O mapped asynchronous serial port, four 16-bit timers, and

external/internal interrupts. The ′C14 devices can provide for microcomputer/microprocessor operating modes.

Three versions with cycle times of 160-ns are available as illustrated in Table 1. These devices are offered in

68-pin plastic PLCC or ceramic CER-QUAD packages.

TMS320C15/E15/P15

The ′C15/E15/P15 devices are a version of the ′C10, offering expanded on-chip RAM, and ROM or EPROM

(′E15/P15). The ′P15 is a one-time programmable (OTP), windowless EPROM version. These devices can

operate in the microcomputer or microprocessor modes. Five versions are available with cycle times of 160 to

200 ns (see Table 1). These devices are offered in 40-pin DIP, 44-pin PLCC, or 44-pin ceramic packages.

TMS320LC15

The ′LC15 is a low-power version of the ′C15, utilizing a V

requirementreductionoverthetypical5-V′C1xdevice. Itoperatesatacycletimeof250ns. Thedeviceisoffered

of only 3.3-V. This feature results in a 2.3: 1 power

DD

in 40-pin DIP or 44-lead PLCC packages.

TMS320C16

The ′C16 offers on-chip RAM of 256-words, an expanded program memory of 64K-words, and a fast instruction

cycle time of 114 ns (8.77 MIPS). It is offered in a 64-pin quad flat-pack package.

TMS320C17/E17/P17

The ′C17/E17/P17 versions consist of five major functional units: the ′C15 microcomputer, a system control

register, a full-duplex dual channel serial port, µ-law/A-law companding hardware, and a coprocessor port. The

dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two

combo-codecs. The hardware companding logic can operate in either µ-law or A-law format with either

sign-magnitude or twos complement numbers in either serial or parallel modes. The coprocessor port allows

the ′C17/E17/P17 to act as a slave microcomputer or as a master to a peripheral microcomputer.

The ′P17 utilizes a one-time programmable (OTP) windowless EPROM version of the ′E17.

TMS320LC17

The ′LC17 is a low-power version of the ′C17, utilizing a V

2.3: 1 power requirement reduction over the typical 5-V ′C1x device. It operates at a cycle time of 278 ns.

of only 3.3-V. This feature results in a

DD

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TMS320C10/C15/LC15/P15

N/JD Packages

TMS320C17/E17/LC17/P17

N/JD Packages

TMS320C10/C15/E15/LC15/P15

FN/FZ Packages

(Top View)

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

A1/PA1

A0/PA0

MC/MP

RS

PA1/RBLE

PA0/HI/LO

MC

1

A2/PA2

A3

1

PA2/TBLF

FSR

2

3

A4

3

FSX

RS

4

A5

4

FR

6

5 4 3 2 1 44 43 42 41 40

INT

EXINT

CLKOUT

X1

5

A6

5

DX1

CLKOUT

X1

6

A7

6

DX0

39

38

37

36

35

34

33

32

31

30

29

CLKOUT

X1

7

A7

7

A8

7

SCLK

DR1

8

A8

X2/CLKIN

BIO

X2/CLKIN

BIO

8

MEN

DEN

WE

8

X2/CLKIN

BIO

9

MEN

DEN

WE

9

DEN/RD

WE/WR

10

11

12

13

14

15

16

17

V

10

11

12

13

14

15

16

10

11

12

13

14

15

16

17

18

19

NC

SS

D8

D8/LD8

V

CC

SS

CC

D9

D9/LD9

A9

DR0

A9

D8

D9

D10

D11

D12

D13

D14

D15

D7

D10/Ld10

D11/LD11

D12/LD12

D13/LD13

D14/LD14

D15/LD15

D7/LD7

A10

A11

D0

D1

D2

D3

D4

D5

XF

A10

A11

D0

MC/PM

D0/LD0

D1/LD1

D2/LD2

D3/LD3

D4/LD4

D5/LD5

D10

D11

D12

D1

17 24

18 23

19 22

20 21

18 19 20 21 22 23 24 25 26 27 28

D6

D6/LD6

20 21

TMS320C14/E14/P14

FN/FZ Packages

(Top View)

TMS320C16

PG Package

(Top View)

64636261605958575655545352

NC

RS

1

2

3

4

5

6

7

8

9

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

NC

A0/PA0

A1/PA1

A2/PA2

9

8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

X1

X2/CLKIN

TCLK/CLKR

TCLK2/CLKX

D4

D5

D6

D7

IOP0

IOP1

IOP2

IOP3

IOP4

IOP5

D8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

V

SS

A8

A7

A6

WE

REN

RS

A3

A4

A5

A6

CLKOUT

D15 10

D14 11

NC 12

D13 13

D12 14

D11 15

D10 16

V

A7

SS

A8

A9

INT

CLKOUT

A5

A10

A11

A12

A13

A14

A4

D9

NMI/MC/MP

WDT

CLKIN

A3

RXD/DATA

TXD/CLK

D10

IOP6

IOP7

17

D9

NC 18

NC

19

NC

20212223242526272829303132

TMS320C17/E17

FN/FZ Packages

(Top View)

A2

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

6

5 4 3 2 1 44 43 42 41 40

39

38

37

36

35

34

33

32

31

30

29

CLKOUT

7

DX0

X1

X2/CLKIN

BIO

SCLK

DR1

8

9

10

11

12

13

14

15

16

17

DEN/RD

NC

WE/WR

V

SS

CC

DR0

D8

D9

XF

D10

D11

D12

MC/PM

D0/LD0

V

SS

18 19 20 21 22 23 24 25 26 27 28

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

architecture

The ′C1x DSPs use a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture,

program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and one-cycle

execution. The ′C1x DSPs modification allows transfers between program and data spaces, thereby increasing

the flexibility of the device. This modification permits coefficients stored in program memory to be read into the

RAM, eliminating the need for a separate coefficient ROM.

32-bit accumulator

All ′C1x devices contain a 32-bit ALU and accumulator for support of double-precision, twos-complement

arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken from the data RAM

or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can perform

Boolean operations, providing the bit manipulation ability required of a high-speed controller. The accumulator

stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit word length. The

accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0).

Instructions are provided for storing the high- and low-order accumulator words in memory.

shifters

Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to 16 places

on data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills

the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1

or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both

shifters are useful for scaling and bit extraction.

16 × 16-bit parallel multiplier

The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction

cycle. The multiplier consists of three units: the T Register, P Register, and a multiplier array. The 16-bit T

Register stores the multiplicand, and the P Register stores the 32-bit product. Multiplier values either come from

the data memory or are derived immediately from the MPYK (multiply immediate) instruction word. The fast

on-chip multiplier allows the device to perform fundamental operations such as convolution, correlation, and

filtering.

data and program memory

Since the ′C1x devices use a Harvard type architecture, data and program memory reside in two separate

spaces. These DSP devices have 144-or 256-words of on-chip data RAM and 1.5K- to 8K-words of on-chip

program ROM. On-chip program EPROM of 4K-words is provided in the ′E14/E15/E17 devices. An on-chip

one-time programmable 4K-word EPROM is provided in the ′P14/P15/P17 devices. The EPROM cell utilizes

standard PROM programmers and is programmed identically to a 64K CMOS EPROM (TMS27C64).

(Reference Table 1.)

program memory expansion

All′C1xdevicesexceptthe′C17/E17/LC17/P17devicesarecapableofexecutingfromoff-chipexternalmemory

at full speed for those applications requiring external program memory space. This allows for external

RAM-based systems to provide multiple functionality. The ′C17/E17/LC17/P17 devices provide no external

memory expansion. (Reference Table 1.)

microcomputer/microprocessor operating modes

All devices except the ′x17 offer two modes of operation defined by the state of the MC/MP pin: the

microcomputer mode (MC/MP = 1) or the microprocessor mode (MC/MP = 0 ). In the microcomputer mode,

on-chip ROM is mapped into the program memory space. In the microprocessor mode, all words of progam

memory are external.

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

interrupts and subroutines

All devices except the ′C16 contain a four-level stack for saving the contents of the program counter during

interrupts and subroutine calls. Because of the larger 64K program space, the ′C16’s hardware stack has been

increased to eight levels. Instructions are available for saving the device’s complete context. PUSH and POP

instructionspermit a level of nesting restricted only by the amount of available RAM. The interrupts used in these

devices are maskable.

input/output

The 16-bit parallel data bus can be utilized to perform I/O functions in two cycles. The I/O ports are addressed

by the three LSBs on the address lines. In addition, a polling input for bit test and jump operations (BIO) and

an interrupt pin (INT) have been incorporated for multitasking. The bit selectable I/O of the ′C14 is suitable for

microcontroller applications.

serial port (TMS320C17/E17)

Two of the I/O ports on the ′C17/E17 are dedicated to the serial port and companding hardware. I/O port 0 is

dedicated to control register 0, which controls the serial port, interrupts, and companding hardware. I/O port 1

accesses control register 1, as well as both serial port channels, and companding hardware. The six remaining

I/O ports are available for external parallel interfaces.

serial port (TMS320C14/E14)

The ′C14/E14 devices include one I/O-mapped serial port that operates asynchronously. I/O-mapped control

registers are used to configure port parameters such as inter-processor communication protocols and baud

rate.

companding hardware (TMS320C17/E17)

On-chip hardware enables the ′C17/E17 to compand (COMpress/exPAND) data in either µ-law or A-law format.

The companding logic operation is configured via the system control register. Data may be companded in either

serial mode for operation on serial port data (converting between linear and logarithmic PCM) or a parallel mode

for computation inside the device. The ′C17/E17 allows the hardware companding logic to operate with either

sign-magnitude or twos-complement numbers.

coprocessor port (TMS320C17/E17)

The coprocessor port on the ′C17/E17 provides a direct connection to most microcomputers and

microprocessors. The port is accessed through I/O port 5 using IN and OUT instructions. The coprocessor

interface allows the device to act as a peripheral (slave) microcomputer to a microprocessor, or as a master to

a peripheral microcomputer. In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O

ports. In the coprocessor mode, the 16-bit parallel port is reconfigured to operate as a 16-bit latched bus

interface. For peripheral transfer, an 8-bit or 16-bit length of the coprocessor port can be selected.

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

instruction set

A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and

general-purpose operations, such as high-speed control. All of the′C1x devices are object-code compatible and

use the same 60 instructions. The instruction set consists primarily of single-cycle single-word instructions,

permitting execution rates of more than six million instructions per second. Only infrequently used branch and

I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute in a single

cycle and are useful for scaling data in parallel with other operations.

NOTE

The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14. An attempt to execute the

BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action.

Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing.

direct addressing

In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer form the

data memory address. This implements a paging scheme in which the first page contains 128 words, and the

second page contains up to 128 words.

indirect addressing

Indirectaddressingformsthedatamemoryaddressfromtheleast-significanteightbitsofoneofthetwoauxiliary

registers, AR0-AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The auxiliary

registers can be automatically incremented or decremented and the ARP changed in parallel with the execution

of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can be used

with all instructions requiring data operands, except for the immediate operand instructions.

immediate addressing

Immediate instructions derive data from part of the instruction word rather than from the data RAM. Some useful

immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load auxiliary

register immediate (LARK).

instruction set summary

Table 2 lists the symbols and abbreviations used in Table 3, the instruction set summary. Table 3contains a short

description and the opcode for each ′C1x instruction. The summary is arranged according to function and

alphabetized within each functional group.

Table 2. Instruction Symbols

SYMBOL

MEANING

ACC

D

M

Accumulator

Data memory address field

Addressing mode bit

K

Immediate operand field

PA

R

S

3-bit port address field

1-bit operand field specifying auxiliary register

4-bit left-shift code

X

3-bit accumulator left-shift field

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Table 3. TMS320C1x Instruction Set Summary

ACCUMULATOR INSTRUCTIONS

OPCODE

NO.

CYCLES

NO.

WORDS

MNEMONIC

DESCRIPTION

INSTRUCTION REGISTER

15 14 13 12 11 10

9

1

8

1

7

6

0

5

0

4

0

3

2

0

1

0

ABS

Absolute value of accumulator

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

D

S

ADD

Add to accumulator with shift

M

D

ADDH

ADDS

AND

Add to high-order accumulator bits

Add to accumulator with no sign extension

AND with accumulator

0

1

0

1

D

S

LAC

Load accumulator with shift

K

D

LACK

OR

Load accumulator immediate

1

0

1

0

1

0

OR with accumulator

M

1

X

SACH

SACL

SUB

Store high-order accumulator bits with shift

Store low-order accumulator bits

Subtract from accumulator with shift

Conditional subtract (for divide)

D

0

S

SUBC

SUBH

SUBS

XOR

ZAC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

D

Subtract from high-order accumulator bits

Subtract from accumulator with no sign extension

Exclusive OR with accumulator

Zero accumulator

0

1

0

1

ZALH

ZALS

Zero accumulator and load high-order bits

Zero accumulator and load low-order bits with no sign extension

M

D

AUXILIARY REGISTER AND DATA PAGE POINTER INSTRUCTIONS

OPCODE

INSTRUCTION REGISTER

NO.

CYCLES

NO.

WORDS

MNEMONIC

DESCRIPTION

15 14 13 12 11 10

9

0

1

0

8

R

0

7

6

5

4

3

2

1

0

D

LAR

Load auxiliary register

1

0

1

0

1

0

1

0

1

0

1

0

M

K

LARK

LARP

LDP

Load auxiliary register immediate

Load auxiliary register pointer immediate

Load data memory page pointer

Load data memory page pointer immediate

Modify auxiliary register and pointer

Store auxiliary register

1

M

0

K

D

1

LDPK

MAR

SAR

0

D

0

M

R

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8

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Table 3. TMS320C1x Instruction Set Summary (continued)

BRANCH INSTRUCTIONS

OPCODE

NO.

CYCLES

NO.

WORDS

MNEMONIC

DESCRIPTION

INSTRUCTION REGISTER

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

B

Branch unconditionally

2

BRANCH ADDRESS

0

1

0

1

0

1

0

1

0

1

0

BANZ

Branch on auxiliary register not zero

BRANCH ADDRESS

0

BGEZ

Branch if accumulator ≥ 0

2

BRANCH ADDRESS

0

BGZ

Branch if accumulator > 0

2

BRANCH ADDRESS

0

†

Branch on BIO = 0

BIOZ

BRANCH ADDRESS

0

BLEZ

BLZ

Branch if accumulator ≤ 0

2

BRANCH ADDRESS

0

Branch if accumulator < 0

BRANCH ADDRESS

0

BNZ

BV

Branch if accumulator ≠ 0

Branch on overflow

2

BRANCH ADDRESS

0

BRANCH ADDRESS

0

BZ

Branch if accumulator = 0

2

1

BRANCH ADDRESS

1

0

1

0

1

0

1

0

1

0

1

0

CALA

CALL

Call subroutine from accumulator

Call subroutine immediately

2

1

BRANCH ADDRESS

1

0

1

0

1

RET

Return from subroutine or interrupt routine

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS

OPCODE

INSTRUCTION REGISTER

NO.

CYCLES

NO.

WORDS

MNEMONIC

DESCRIPTION

15 14 13 12 11 10

9

1

0

1

0

8

1

0

1

7

6

5

4

3

2

1

0

APAC

LT

Add P register to accumulator

1

0

1

0

1

0

1

0

1

0

1

Load T Register

M

D

LTA

LTA combines LT and APAC into one instruction

LTD combines LT, APAC, and DMOV into one instruction

Multiply with T register, store product in P register

LTD

MPY

Multiply T register with immediate operand; store product

in P register

MPYK

1

0

K

PAC

Load accumulator from P register

1

0

1

0

1

0

1

0

1

0

SPAC

Subtract P register from accumulator

†

This instruction is a NOP on the ′320C14/E14/P14.

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Table 3. TMS320C1x Instruction Set Summary (concluded)

CONTROL INSTRUCTIONS

OPCODE

NO.

MNEMONIC

DESCRIPTION

INSTRUCTION REGISTER

CYCLES

WORDS

15 14 13 12 11 10

9

1

0

8

1

0

7

1

6

0

5

0

4

0

3

2

0

1

0

1

0

1

0

DINT

EINT

LST

Disable interrupt

Enable interrupt

Load status register

No operation

1

2

1

0

1

0

1

0

1

0

D

M

1

NOP

POP

0

1

0

1

0

1

0

1

0

1

0

1

POP stack to accumulator

PUSH stack from accumulator

Reset overflow mode

Set overflow mode

1

PUSH

ROVM

SOVM

SST

1

D

Store status register

M

I/O AND DATA MEMORY OPERATIONS

OPCODE

INSTRUCTION REGISTER

NO.

CYCLES

NO.

WORDS

MNEMONIC

DESCRIPTION

15 14 13 12 11 10

9

0

8

7

6

5

4

3

2

1

0

D

DMOV

IN

Copy contents of data memory location into next higher location

Input data from port

1

2

3

1

0

1

0

1

0

1

0

1

0

1

0

1

M

PA

D

OUT

TBLR

TBLW

Output data to port

D

Table read from program memory to data RAM

Table write from data RAM to program memory

1

0

1

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TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Key Features: TMS320C10

+5 V

GND

• Instruction Cycle Timing

— 160-ns (TMS320C10-25)

— 200-ns (TMS32010)

— 280-ns (TMS320C10-14)

144-Word RAM

Interrupt

Data (16)

• 144 Words of On-Chip Data RAM

• 1.5K Words On-Chip Program ROM

1.5K-Word ROM

32-Bit ALU/ACC

Multiplier

• External Memory Expansion up to 4K

Words at Full Speed

• 16 × 16-Bit Multiplier With 32-Bit Product

• 0 to 16-Bit Barrel Shifter

Address (12)

Shifters

• On-Chip Clock Oscillator

• Device Packaging:

— 40-Pin DIP

— 44-Lead PLCC

• Single 5-V Supply

• Operating Free-Air Temperature Range

. . . 0°C to 70°C

TMS320C10

N/JD Package

TMS320C10

FN/FZ Package

(Top View)

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

1

A1/PA1

A0/PA0

MC/MP

RS

INT

CLKOUT

X1

A2/PA2

A3

A4

A5

A6

A7

A8

MEN

DEN

WE

2

3

6

5 4 3 2 1 44 43 42 41 40

4

5

39

38

37

36

35

34

33

32

31

30

29

7

CLKOUT

X1

X2/CLKIN

BIO

A7

A8

MEN

DEN

WE

6

8

7

9

8

X2/CLKIN

BIO

10

11

12

13

9

NC

10

11

12

13

14

15

16

17

V

SS

V

SS

CC

D8

D9

V

CC

A9

D8

A9

D9 14

D10 15

D11 16

D12 17

A10

A11

D0

D10

D11

D12

D13

D14

D15

D7

A10

A11

D0

D1

D2

D3

D4

D5

D1

18 19 20 21 22 23 24 25 26 27 28

18 23

19 22

20 21

D6

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TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TERMINAL FUNCTIONS

†

NAME

A11-A0/PA2-PA0

I/O

DEFINITION

O

I

External address bus. I/O port address multiplexed over PA2-PA0.

External polling input

BIO

CLKOUT

D15-D0

DEN

O

System clock output, 1/4 crystal/CLKIN frequency

16-bit parallel data bus

I/O

O

I

Data enable for device input data on D15-D0

External interrupt input

INT

MC/MP

MEN

NC

I

Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.

Memory enable indicates that D15-D0 will accept external memory instruction.

No connection

O

I

RS

Reset for initializing the device

V

I

+ 5 V supply

CC

I

Ground

SS

WE

O

I

Write enable for device output data on D15-D0

Crystal output for internal oscillator

X1

X2/CLKIN

Crystal input internal oscillator or external system clock input

†

Input/Output/High-impedance state.

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TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

functional block diagram

X1

CLKOUT

X2/CLKIN

16

Program Bus

12 LSB

WE

DEN

MEN

BIO

MUX

12

MC/MP

INT

PC (12)

RS

12

Instruction

3

16

A11-A0/

PA2-PA0

Program

ROM/EPROM

D15-D0

Stack

4 × 12

(1.5K Words)

Program Bus

16

Data Bus

16

7

16

AR0 (16)

AR1 (16)

DP

T(16)

ARP

Shifter

(0–16)

16

8

Multiplier

8

P(32)

32

MUX

8

32

MUX

32

Address

Data RAM

(144 Words)

Legend:

ALU (32)

ACC = Accumulator

Data

32

ALU = Arithmetic Logic Unit

ARP = Auxiliary Register Pointer

AR0 = Auxiliary Register 0

AR1 = Auxiliary Register 1

DP = Data Page Pointer

ACC (32)

32

P

= P Register

PC = Program Counter

= T Register

T

Shifter (0,1,4)

16

Data Bus

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TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical specifications

This section contains the electrical specifications for all speed versions of the ′C10 Digital Signal Processors,

including test parameter measurement information.

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

CC

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mW

Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

°

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

SS.

recommended operating conditions

MIN

NOM

MAX

UNIT

V

Supply voltage

4.5

5

0

5.25

V

CC

SS

CLKIN

3

2

V

High-level input voltage

Low-level input voltage

V

IH

IL

All remaining inputs

MC/MP

V

0.6

0.8

V

All remaining inputs

V

I

High-level output current, all outputs

Low-level output current

–300

2

µA

mA

OH

OL

L suffix

A suffix

0

70

85

°C

Operating free-air temperature

T

A

– 40

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TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

I

= MAX

2.4

3

OH

OL

V

OH

High-level output voltage

‡

V – 0.4

CC

= 20 µA (see Note 7)

V

I

Low-level output voltage

Off-state output current

= MAX

0.3

0.5

20

V

OL

V

= 2.4 V

= 0.4 V

O

V

= MAX

CC

µA

OZ

–20

±20

±50

O

All inputs except CLKIN

CLKIN

I

Input current

V

= V to V

SS CC

CC

‡

25

‡

15

‡

25

‡

10

Data bus

All others

Data bus

All others

C

Input capacitance

Output capacitance

pF

i

f = 1 MHz, all other pins 0 V

o

†

‡

All typical values are at V

= 5 V, T = 25°C.

A

CC

Values derived from characterization data and not tested.

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data

sheet are specified for TTL logic levels and will differ for HC logic levels.

INTERNAL CLOCK OPTION

X1

X2/CLKIN

Crystal

C1

C2

Figure 1. Internal Clock Option

PARAMETER MEASUREMENT INFORMATION

2.15 V

R

= 825 Ω

L

From Output

Under Test

Test

Point

C

= 100 pF

L

Figure 2. Test Load Circuit

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TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

TEST CONDITIONS

(SEE FIGURE 2)

†

TYP

PARAMETER

MIN

MAX

UNIT

TMS320C10

TMS320C10-25

All typical values are at T = 70°C and are used for thermal resistance calculations.

f = 20.5 MHz, V = 5.5 V, T = – 40°C to 85°C

33

40

55

65

CC

f = 25.6 MHz, V

A

‡

I

Supply current

CC

mA

= 5.5 V T = – 0°C to 70°C

CC

A

†

‡

A

I

characteristics are inversely proportional to temperature. For I dependence on temperature, frequency, and loading.

CC

CLOCK CHARACTERISTICS AND TIMING

The ′C10/C10-25 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency

of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and

parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be

specified at a load capacitance of 20 pF.

PARAMETER

TMS320C10

TMS320C10-25

TEST CONDITIONS

= – 40°C to 85°C

MIN

6.7

NOM

MAX

20.5

25.6

UNIT

T

A

Crystal frequency, f

MHz

x

T

= 0°C to 70°C

6.7

A

C1, C2

T

A

= – 40°C to 85°C

10

pF

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

TMS320C10

NOM

TMS320C10-25

NOM MAX

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

156.25

§

t

CLKOUT cycle time

CLKOUT rise time

CLKOUT fall time

195.12

200

160

ns

c(C)

¶

10

r(C)

R

L

= 825 Ω,

8

f(C)

C

= 100 pF

(see Figure 2)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Delay time, CLKIN↑ to CLKOUT↓

92

90

72

70

w(CL)

w(CH)

d(MCC)

¶

25

¶

60

¶

50

25

§

¶

t

is the cycle time of CLKOUT, i.e., 4t

c(MC)

(4 times CLKIN cycle time if an external oscillator is used).

c(C)

Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

NOM

UNIT

MIN

NOM

MAX

MIN

MAX

¶

t

Master clock cycle time

48.78

50

150 39.06

40

150

10

ns

c(MC)

¶

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low

Pulse duration, master clock high

5

10

5

r(MC)

¶

10

f(MC)

¶

0.4t

c(MC)

0.6t

c(MC)

0.45t

c(MC)

0.55t

¶

w(MCP)

w(MCL)

w(MCH)

c(MC)

¶

20

15

¶

Values derived from characterization data and not tested.

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TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

TMS320C10

TYP

TMS320C10-25

TYP

TEST

CONDITIONS

PARAMETER

UNIT

MIN

MAX

MIN

MAX

Delay time, CLKOUT↓ to

address bus valid

†

t

10

50

10

40

ns

d1

d2

d3

d4

d5

Delay time, CLKOUT↓

to MEN↓

†

1/4t

– 5

1/4t

c(C)

+ 15 1/4t

– 5

1/4t

+ 12

ns

c(C)

12

+ 12

Delay time, CLKOUT↓

to MEN↑

†

–10

†

–10

15

Delay time, CLKOUT↓

to DEN↓

†

1

†

1/4t

c(C)

– 5

/ t

4 c(C)

+ 15 1/4t

c(C)

1/4t

c(C)

12

+ 12

Delay time, CLKOUT↓

to DEN↑

†

–10

†

–10

15

†

t

Delay time, CLKOUT↓ to WE↓

Delay time, CLKOUT↓ to WE↑

1/2t

c(C)

– 5

1/2t

1/4t

+ 15 1/2t

–5

1/2t

ns

d6

c(C)

R

= 825 Ω

= 100 pF,

L

C

†

–10

†

–10

L

15

12

d7

(see Figure 2)

Delay time, CLKOUT↓ to data

bus OUT valid

†

t

+ 65

c(C)

1/4t

c(C)

+ 52

ns

d8

Time after CLKOUT↓ that data

bus starts to be driven

†

– 5

†

– 5

1/4t

d9

c(C)

Time after CLKOUT↓ that data

bus stops being driven

†

1/4t

c(C)

+ 40

1/4t

c(C)

+ 40

d10

Data bus OUT valid after

CLKOUT↓

1/4t

–10

–45

1/4t

–10

–35

v

c(C)

Address hold time after WE↑,

MEN↑, or DEN↑ (see Note 8)

†

–10

†

–10

h(A-WMD)

su(A-MD)

Address bus setup time prior

to MEN↓ or DEN↓

1/4t

c(C)

†

Values derived from characterization data and not tested.

NOTE 8: For interfacing I/O devices, see Figure 3.

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TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

NOM MAX

TEST CONDITION

UNIT

MIN

NOM MAX MIN

t

Setup time, data bus valid prior to CLKOUT↓

50

40

ns

R

C

= 825 Ω,

= 100 pF

su(D)

L

Hold time, data bus held valid after CLKOUT↓

(see Note 9)

0

ns

(see Figure 2)

h(D)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

SUGGESTED I/O DECODE CIRCUIT

The circuit shown in Figure 3 is a design example for interfacing I/O devices to the ′C10/C10-25. This circuit

decodes the address for output operations using the OUT instruction. The same circuit can be used to decode

input and output operations if the inverter (’ALS04) is replaced with a NAND gate and both DEN and WE are

connected. Inputs and outputs can be decoded at the same port provided the output of the decoder (’AS137)

is gated with the appropriate signal (DEN or WE) to select read or write (using an ’ALS32). Access times can

beincreasedwhenthecircuitshowninFigure3isrepeatedtosupportINinstructionswithDENconnectedrather

than WE.

The table write (TBLW) function requires a different circuit. A detailed discussion of an example circuit for this

function is described in the application report, “Interfacing External Memory to the TMS32010”, published in the

book, Digital Signal Processing Applications with the TMS320 Family (SPRA012A).

TMS320C10

WE

74AS137

74ALS04

15

14

13

12

11

10

9

32

4

GL

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

2

1

2

A

B

PA0

PA1

PA2

1

40

3

C

6

5

G1

G2

V

CC

I/O Device

7

Figure 3. I/O Decode Circuit

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18

TMS320C10, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

825 Ω,

MIN

TYP

1/2t

MAX

UNIT

R

t

Delay time, DEN↑, WE↑, and MEN↑ from RS

Data bus disable time after RS

+50†

ns

L

d11

c(C)

C

= 100 pF,

L

†

+50

1/4t

ns

dis(R)

(see Figure 2)

†

Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

NOM

UNIT

PARAMETER

MIN

NOM

MAX

MIN

MAX

t

Reset (RS) setup time prior to CLKOUT (see Note 10)

50

40

ns

su(R)

RS pulse duration

5t

c(C)

5t

c(C)

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

TMS320C10

NOM

TMS320C10-25

UNIT

MIN

MAX

MIN

NOM

MAX

t

Fall time, INT

15

ns

f(INT)

Pulse duration, INT

t

w(INT)

su(INT)

c(C)

Setup time, INT↓ before CLKOUT↓

50

40

IO (BIO) TIMING

timing requirements over recommended operating conditions

TMS320C10

TMS320C10-25

NOM

UNIT

MIN

NOM

MAX

MIN

MAX

t

Fall time, BIO

15

ns

f(IO)

Pulse duration, BIO

t

w(IO)

su(IO)

c(C)

Setup time, BIO↓ before CLKOUT↓

50

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

19

TMS320C10-14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

†

PARAMETER

Supply current

All typical values are at T = 70°C and are used for thermal resistance calculations.

TEST CONDITIONS

MIN

TYP

28

MAX

UNIT

‡

I

f = 14.4, MHz, V = 5.5 V, T = 0°C to 70°C

65

mA

CC

A

†

‡

A

I

characteristics are inversely proportional to temperature; i.e., I decreases approximately linearly with temperature.

CC

CLOCK CHARACTERISTICS AND TIMING

The TMS320C10-14 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency

of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and

parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified

at a load capacitance of 20 pF.

PARAMETER

Crystal frequency, f

TEST CONDITIONS

MIN

NOM

MAX

UNIT

MHz

pF

T

= 0°C to 70°C

6.7

14.4

x

A

C1, C2

T

10

A

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

§

t

CLKOUT cycle time

CLKOUT rise time

CLKOUT fall time

277.78

ns

c(C)

r(C)

f(C)

10

8

ns

R

= 825 Ω,

= 100 pF,

L

C

L

t

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Delay time, CLKIN↑ to CLKOUT↓

(see Figure 2)

131

129

ns

w(CL)

w(CH)

d(MCC)

¶

25

¶

60

§ t

is the cycle time of CLKOUT, i.e., 4t

c(MC)

(4 times CLKIN cycle time if an external oscillator is used).

c(C)

¶

Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Master clock cycle time

69.5

150

ns

c(MC)

¶

10

¶

10

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low, t

5

ns

r(MC)

5

f(MC)

¶

0.4t

c(MC)

0.6t

c(MC)

w(MCP)

w(MCL)

w(MCH)

¶

= 50 ns

20

c(MC)

¶

Pulse duration, master clock high, t

= 50 ns

c(MC)

¶

Values derived from characterization data and not tested.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

20

TMS320C10-14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

†

10

t

Delay time, CLKOUT↓ to address bus valid

Delay time, CLKOUT↓ to MEN↓

50

d1

d2

d3

d4

d5

d6

d7

d8

d9

d10

v

†

1/ t

4 c(C)

– 5

1/ t

4 c(C)

+15

ns

†

–10

Delay time, CLKOUT↓ to MEN↑

15

+15

ns

1

Delay time, CLKOUT↓ to DEN↓

1/ t

4 c(C)

/ t

4 c(C)

ns

†

–10

Delay time, CLKOUT↓ to DEN↑

15

+15

ns

Delay time, CLKOUT↓ to WE↓

1/ t

2 c(C)

1/ t

2 c(C)

ns

R

C

= 825 Ω,

= 100 pF

L

†

–10

Delay time, CLKOUT↓ to WE↑

15

+ 65

ns

(see Figure 2)

Delay time, CLKOUT↓ to data bus OUT valid

Time after CLKOUT↓ that data bus starts to be driven

Time after CLKOUT↓ that data bus stops being driven

Data bus OUT valid after CLKOUT↓

1/4t

c(C)

ns

†

1/4t

– 5

ns

c(C)

†

1/4t

c(C)

+ 40

ns

1/4t

– 10

– 45

ns

c(C)

Address hold time after WE↑, MEN↑, or DEN↑

†

–10

t

ns

h(A-WMD)

su(A-MD)

(see Note 8)

Address bus setup time prior to MEN↓ or DEN↓

1/4t

c(C)

†

Values derived from characterization data and not tested.

NOTE 8: For interfacing I/O devices, see Figure 3.

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

R

C

= 825 Ω,

= 100 pF

t

Setup time, data bus valid prior to CLKOUT↓

50

ns

L

su(D)

Hold time, data bus held valid after CLKOUT↓ (see Note 9)

0

ns

(see Figure 2)

h(D)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

21

TMS320C10-14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

1/2t

MAX

UNIT

†

R

L

= 825 Ω,

t

Delay time, DEN↑, WE↑, and MEN↑ from RS

+ 50

ns

d11

c(C)

1/4t

C

= 100 pF

Data bus disable time after RS

+ 50

ns

(see Figure 2)

dis(R)

c(C)

†

Values were derived from characterization data and not tested.

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Reset (RS) setup time prior to CLKOUT (see Note 10)

RS pulse duration

50

ns

su(R)

5t

c(C)

ns

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Fall time, INT

15

ns

f(INT)

Pulse duration, INT

t

ns

w(INT)

su(INT)

c(C)

Setup time, INT↓ before CLKOUT↓

50

IO (BIO) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Fall time, BIO

15

ns

f(IO)

Pulse duration, BIO

t

ns

w(IO)

su(IO)

c(C)

Setup time, BIO↓ before CLKOUT↓

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

22

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TIMING DIAGRAMS

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless

otherwise noted.

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

CLKOUT

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

t

r(C)

f(C)

t

w(CL)

t

c(C)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

†

t

and t

w(MCP)

d(MCC)

memory read timing

t

c(C)

CLKOUT

t

d2

t

d3

MEN

t

su(A-MD)

t

h(A-WMD)

t

d1

A11-A0

Address Bus Valid

t

su(D)

t

h(D)

Instruction Valid

D15-D0

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

23

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TBLR instruction timing

CLKOUT

t

d2

t

d3

t

d3

2

MEN

1

3

7

4

8

t

d1

A11-A0

5

6

t

h(D)

t

su(D)

9

10

11

12

D15-D0

Legend:

1. TBLR Instruction Prefetch

2. Dummy Prefetch

3. Data Fetch

4. Next Instruction Prefetch

5. Address Bus Valid

6. Address Bus Valid

7. Address Bus Valid

8. Address Bus Valid

9. Instruction Valid

10. Instruction Valid

11. Data Input Valid

12. Instruction Valid

TBLW instruction timing

CLKOUT

MEN

1

2

3

7

A11-A0

4

5

6

t

d7

d6

WE

t

d8

t

d10

t

d9

t

v

D15-D0

8

9

10

11

Legend:

1. TBLW Instruction Prefetch

2. Dummy Prefetch

3. Next Instruction Prefetch

4. Address Bus Valid

5. Address Bus Valid

6. Address Bus Valid

7. Address Bus Valid

8. Instruction Valid

9. Instruction Valid

10. Data Output Valid

11. Instruction Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

24

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

IN instruction timing

CLKOUT

MEN

A11-A0

DEN

1

2

t

su(A-MD)

4

t

su(D)

t

3

5

t

d5

d4

t

h(D)

D15-D0

6

7

8

Legend:

1. IN Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Input Valid

8. Instruction Valid

4. Peripheral Address Valid

OUT instruction timing

CLKOUT

MEN

A11-A0

WE

1

3

2

5

4

t

d6

d7

t

d9

t

d10

t

d8

t

v

7

6

8

D15-D0

Legend:

1. OUT Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Output Valid

8. Instruction Valid

4. Peripheral Address Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

25

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

reset timing

CLKOUT

t

su(R)

t

su(R)

RS

t

w(R)

DEN

WE

MEN

(see

Note E)

Data In From

PC ADDR PC+1

Data In From

PC ADDR 0

t

d11

t

dis(R)

Data

Out

Data Shown Relative to WE

D15-D0

MEN

AB = PC+1

AB = Address Bus

AB = PC

Address

Bus

AB = PC = 0

AB = PC+1

NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-

er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.

B. RS must be maintained for a minimum of five clock cycles.

C. Resumption of normal program will commence after one complete CLK cycle from RS↑.

D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK

cycle.

E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.

F. During a write cycle, RS may produce an invalid write address.

interrupt timing

CLKOUT

t

su(INT)

INT

t

f(INT)

t

w(INT)

BIO timing

CLKOUT

t

su(IO)

BIO

t

f(IO)

t

w(IO)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

26

TMS320C10, TMS320C10-14, TMS320C10-25

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TYPICAL POWER VS. FREQUENCY GRAPHS

52

46

40

34

28

22

16

10

T

= – 40°C

= 85°C

A

T

A

V

CC

V

CC

V

CC

= 5.5 V

= 5.0 V

= 4.5 V

T

A

= – 40°C

= 85°C

T

A

T

A

= – 40°C

= 85°C

T

A

1.2

4

8

12

16

20

24

28

f

- Crystal Frequency - MHz

x

(a) – 40°C to 85°C Temperature Range

42

36

30

24

18

12

6

With Load

Without Load

0

1.2

4

8

12

16

20

24

28

f

- Crystal Frequency - MHz

x

(b) Voltage = 5 V; Temperature = 25°C

Figure 4. Typical CMOS I

vs Frequency

CC

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

27

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Key Features: TMS320C14/E14/P14

+5 V

GND

• 160-ns Instruction Cycle

• 256 Words of On-Chip Data RAM

256-Word RAM

Interrupt

• 4K Words of On-Chip Program ROM

Data (16)

(TMS320C14)

8K-Word ROM/

EPROM

• 4K Words of On-Chip Program EPROM

(TMS320E14/P14)

32-Bit ALU/ACC

• One-Time Programmable (OTP) Windowless

EPROM Version Available (′320P14)

Multiplier

Shifters

Address (12)

• EPROM Code Protection for Copyright Security

• External Memory Expansion up to 4K-Words

at Full Speed (Microprocessor Mode)

• 16 × 16-Bit Multipler With 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• Seven Input and Seven Output External Ports

• Bit Selectable I/O Port (16 Pins)

TMS320C14, TMS320E14/P14

FN/FZ Packages

• 16-Bit Bidirectional Data Bus With Greater than

(Top View)

50-Mbps Transfer Rate

• Asynchronous Serial Port

• 15 Internal/External Interrupts

• Event Manager With Capture Inputs and

9

8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

Compare Outputs

TCLK/CLKR

TCLK2/CLKX

D4

D5

D6

D7

IOP0

IOP1

IOP2

IOP3

IOP4

IOP5

D8

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

• Four Independent Timers [Watchdog,

A8

A7

A6

WE

REN

RS

General Purpose (2), Serial Port]

• Four-Level Hardware Stack

• Packaging: 68-Pin PLCC (FN Suffix)

INT

CLKOUT

A5

or CLCC (FZ Suffix)

• Single 5-V Supply

A4

D9

NMI/MC/MP

WDT

CLKIN

A3

RXD/DATA

TXD/CLK

D10

IOP6

IOP7

• Operating Free-Air Temperature

. . . 0°C to 70°C

A2

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

28

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

introduction

The ′C14/E14/P14 are 16/32-bit single-chip digital signal processing (DSP) microcontrollers that combine the

high performance of a DSP with on-chip peripherals. With a 160-ns instruction cycle, these devices are capable

of executing up to 6.4 million instructions per second (MIPS). The ′C14/E14/P14 DSPs are ideal for applications

such as automotive control systems, computer peripherals, industrial controls, and military command/control

system applications.

Control-specific on-chip peripherals include: An event manager with 6 channel PWM D/A/, 6-bit I/O pins, an

asynchronous serial port, four 16-bit timers, and internal/external interrupts.

With 4K-words of on-chip ROM, the ′C14 is a mask programmable device. Code is provided by the customer,

and TI incorporates the customer’s code into the photomask. It is offered in a 68-pin plastic chip carrier package

(FN suffix), rated for operation from 0°C to 70°C.

The ′E14 is provided with a 4K-word on-chip EPROM. This EPROM version is excellent for prototyping and for

customized applications. It is programmable with standard EPROM programmers. It is offered in a 68-pin

(windowed) cerquad package (FZ suffix), rated for operation from 0°C to 70°C.

The ′P14 features a one-time programmable 4K-word on-chip EPROM. The ′P14 is provided in an

unprogrammed state and is programmed as if it were a blank ′E14. It is offered in a low-cost,

volume-production-oriented, 68-pin plastic leaded chip carrier (PLCC) package (FN suffix), rated for operation

from 0°C to 70°C.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

29

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Each device can execute programs form either internal (MC/MP=0) or external program memory (MC/MP=1).

For proprietary code security, the ′E14 and ′P14 incorporate an EPROM protect bit (RBIT). If this bit is

programmed, the device’s internal program memory cannot be accessed by any external means.

TERMINAL FUNCTIONS

DESCRIPTION

†

I/O/Z

NAME

NO.

ADDRESS/DATA BUSES

A11

A10

A9

5

O/Z

Programmemory address bus A11 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through

PA0 (LSB). Addresses A11 through A0 are always active and never go to high impedance except

during reset. During execution of the IN and OUT instructions, pins 26, 27, and 28 carry the port

addresses. Pins A3 through A11 are held high when port accesses are made on pins PA0 through

PA2.

6

9

A8

12

13

14

20

21

25

26

27

28

A7

A6

A5

A4

A3

A2/PA2

A1/PA1

A0/PA0

D15 MSB

D14

D13

D12

D11

D10

D9

35

36

39

40

43

46

49

50

57

58

59

60

61

62

63

64

I/O/Z

Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state

except when WE is active (low). The data bus is also active when internal peripherals are written to.

D8

D7

D6

D5

D4

D3

D2

D1

D0 LSB

INTERRUPT AND MISCELLANEOUS SIGNALS

INT

18

22

I

External interrupt input. The interrupt signal is generated by a high-to-low transition on this pin.

NMI/MC/MP

Non-maskable interrupt. When this pin is brought low, the device is interrupted irrespective of the

state of the INTM bit in status register ST.

Microcomputer/microprocessor select. This pin is also sampled when RS is low. If high during reset,

internal program memory is selected. If low during reset, external memory will be selected.

WE

REN

RS

15

16

17

O

I

Write enable. When active low, WE indicates that device will output data on the bus.

Read enable. When active low, REN indicates that device will accept data from the bus.

Reset. When this pin is low, the device is reset and PC is set to zero.

Continued next page.

†

Input/Output/High-impedance state.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

30

TMS320C10-14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TERMINAL FUNCTIONS (concluded)

DESCRIPTION

†

I/O/Z

NAME

NO.

19

SUPPLY/OSCILLATOR SIGNALS

CLKOUT

O

I

System clock output (one fourth CLKIN frequency).

V

4,33

3,34

24

5-V supply pins.

CC

I

Ground pins.

SS

CLKIN

I

Master clock input from external clock source.

SERIAL PORT AND TIMER SIGNALS

RXD

48

47

10

11

23

I

O/Z

I

Asynchronous mode receive input.

TXD

Asynchronous mode transmit output.

TCLK1

TCLK2

WDT

Timer 1 clock. If external clock is selected, it serves as clock input to Timer 1.

Timer 2 clock. If external clock is selected, it serves as clock input to Timer 2.

Watchdog timer output. An active low is generated on this pin when the watchdog timer times out.

BIT I/O PINS

I

O

IOP15

IOP14

IOP13

IOP12

IOP11

IOP10

IOP9

IOP8

IOP7

IOP6

IOP5

IOP4

IOP3

IOP2

IOP1

IOP0

MSB

29

30

31

32

37

38

41

42

44

45

51

52

53

54

55

56

I/O

16 bit I/O lines that can be individually configured as inputs or outputs and also individually set or

reset

when configured as outputs.

LSB

COMPARE AND CAPTURE SIGNALS

8

7

2

1

O

I

Compareoutputs. Thestatesofthesepinsaredeterminedbythecombinationofcompareandaction

registers.

CMP0

CMP1

CMP2

CMP3

68

67

Capture inputs. A transition on these pins causes the timer register to be captured in FIFO stack.

CAP0

CAP1

CMP4/CAP2

CMP5/CAP3

66

65

I/O

This pin can be configured as compare output or capture input.

†

Input/Output/High-impedance state.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

31

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

functional block diagram

CLKIN CLKOUT

12 LSB

16

WE

MUX

16

12

REN

RS

Watchdog Timer

WDT

12

PC (12)

12

Instruction

Timers

1.2

12

TCLK1.2

16

Program

ROM/EPROM

(4K Words)

16

12

A0-A11

PA0-PA2

16

Stack

4 × 12

3

D15-D0

Program Bus

NMI/

MC/MP

INT

Interrupt

Controller

16

BSR

16

Data Bus

16

6

CMP0-CMP3

CMPR

(6)

ACT

(6)

16

T(16)

7

1

CMP4, 5 /

CAP2, 3

16

AR0 (16)

AR1 (16)

DP

ARP

16

Multiplier

P(32)

4 × 16

FIFO

Stack

(4)

16

CAP

Detect

(4)

4

8

CAP0,1

MUX

32

Shifter

(0–16)

8

Serial

Port

Timer

Serial

MUX

32

Port

16

32

Controller

Address

Data

9

TXD

RXD

TBR TSR

RBR RSR

ALU (32)

32

(256 Words)

Data

IOP

IOP0-IOP15

ACC (32)

32

Legend:

ACC = Accumulator

ACT = Action Register

ALU = Arithmetic Logic Unit

ARP = Auxiliary Register Point

AR0 = Auxiliary Register 0

AR1 = Auxiliary Register 1

BSR = Bank Select Register

CAP = Capture

DP = Data Page Pointer

IOP = Input/Output Port

(Bit Selectable)

PC = Program Counter

P = P Register

RBR = Receive Buffer Register

RSR = Receive Shift Register

T = T Register

TBR = Transmit Buffer Register

TSR = Transmit Shift Register

Shifter (0,1,4)

16

Data Bus

CMPR = Compare Register

architecture

The ′C1x family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture,

program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution.

The ′C1x family’s modification of a Harvard architecture allows transfers between program and data spaces,

thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory

to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate

instructions and subroutines based on computed values.

32-bit ALU/accumulator

The ′C14/E14/P14 devices contain a 32-bit ALU and accumulator for support of double-precision,

twos-complement arithmetic. The ALU is a general-purpose arithmetic unit that operates on 16-bit words taken

from the data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the

ALU can perform Boolean operations, providing the bit manipulation ability required of a high-speed controller.

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The accumulator stores the output from the ALU and is often an input to the ALU. It operates with a 32-bit

wordlength. The accumulator is divided into a high-order word (bits 31 through 16) and a low-order word (bits

15 through 0). Instructions are provided for storing the high- and low- order accumulator words in memory.

shifters

Two shifters are available for manipulating data. The ALU barrel shifter performs a left-shift of 0 to16 places on

data memory words loaded into the ALU. This shifter extends the high-order bit of the data word and zero-fills

the low-order bits for twos-complement arithmetic. The accumulator parallel shifter performs a left-shift of 0, 1,

or 4 places on the entire accumulator and places the resulting high-order accumulator bits into data RAM. Both

shifters are useful for scaling and bit extraction

16 × 16-bit parallel multiplier

The multiplier performs a 16 × 16-bit twos-complement multiplication with a 32-bit result in a single instruction

cycle. The multiplier consists of three units: the T Register, P Register, and the multiplier array. The 16-bit T

Register temporarily stores the multiplicand; the P Register stores the 32-bit product. Multiplier values either

come from the data memory or are derived immediately from the MPYK (multiply immediate) instruction word.

Thefaston-chipmultiplierallowsthedevicetoperformfundamentaloperationssuchasconvolution, correlation,

and filtering.

data and program memory

Since the ′C14/E14/P14 devices use a Harvard architecture, data and program memory reside in two separate

spaces. These devices have 256 words of on-chip data RAM and 4K words of on-chip program ROM (′C14)

or EPROM (′E14 and the OTP ′P14). The EPROM cell utilizes standard PROM programmers and is

programmed identically to a 64K-bit CMOS EPROM (TMS27C64).

program memory expansion

The′C1xdevicesarecapableofexecutingupto4Kwordsofexternalmemoryatfullspeedforthoseapplications

requiring external program memory space. This allows for external RAM-based systems to provide multiple

functionality.

microcomputer/microprocessor operating modes

The ′C14/E14/P14devicesoffertwomodesofoperationdefinedbythestateoftheNMI/MC/MPpinduringreset:

the microcomputer mode (NMI/MC/MP is high) or the microprocessor mode (NMI/MC/MP is low). In the

microcomputer mode, the on-chip ROM is mapped into the program memory space. In the microprocessor

mode, all 4K words of memory are external.

interrupts and subroutines

The ′C14/E14/P14 devices contain a four-level hardware stack for saving the contents of the program counter

during interrupts and subroutine calls. Instructions are available for saving the complete context of the device.

PUSH and POP instructions permit a level of nesting restricted only by the amount of available RAM. The

′C14/E14/P14 have a total of 15 internal/external interrupts. Fourteen of these are maskable; NMI is the

fifteenth.

input/output

The16-bitparalleldatabuscanbeutilizedtoaccessexternalperipherals. However, onlythelowerthreeaddress

lines are active. The upper nine address lines are driven high.

bit I/O

The ′C14/E14/P14 has 16 pins of bit I/O that can be individually configured as inputs or outputs. Each of the

pins can be set or cleared without affecting the others. The input pins can also detect and match patterns and

generate a maskable interrupt signal to the CPU.

serial port

The ′C14/E14/P14 includes an I/O-mapped asynchronous serial port.

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event manager

An event manager is included that provides up to four capture inputs and up to six compare outputs. This

peripheraloperateswiththetimers toprovideaformofprogrammableeventlogging/detection. Thesixcompare

outputs can also be configured to produce six channels of high precision PWM.

timers 1 and 2

Two identical 16-bit timers are provided for general purpose applications. Both timers include a 16-bit period

register and buffer latch, and can generate a maskable interrupt.

serial port timer

Theserialporttimerisa16-bittimerprimarilyintendedforbaudrategenerationfortheserialport. Itsarchitecture

is the same as timers 1 and 2, therefore it can serve as a general purpose timer if not needed for serial

communication.

watchdog timer

The ′C14/E14/P14 contain a 16-bit watchdog timer that can produce a timeout (WDT) signal for various

applications such as software development and event monitoring. The watchdog timer also generates, at the

point of the timeout, a maskable interrupt signal to the CPU.

instruction set

A comprehensive instruction set supports both numeric-intensive operations, such as signal processing, and

general-purpose operations, such as high-speed control. All of the first-generation devices are object-code

compatible and use the same 60 instructions. The instruction set consists primarily of single-cycle single-word

instructions, permitting execution rates of more than six million instructions per second. Only infrequently used

branch and I/O instructions are multicycle. Instructions that shift data as part of an arithmetic operation execute

in a single cycle and are useful for scaling data in parallel with other operations.

NOTE

The BIO pin on other ′C1x devices is not available for use in the ′C14/E14/P14 devices. An attempt to

execute the BIOZ (Branch on BIO low) instruction will result in a two cycle NOP action.

Three main addressing modes are available with the instruction set: direct, indirect, and immediate addressing.

direct addressing

In direct addressing, seven bits of the instruction word concatenated with the 1-bit data page pointer from the

data memory address. This implements a paging scheme in which each page contains 128 words.

indirect addressing

Indirect addressing forms the data memory address from the least-significant eight bits of one of the two

auxiliary registers, AR0 and AR1. The Auxiliary Register Pointer (ARP) selects the current auxiliary register. The

auxiliary registers can be automatically incremented or decremented and the ARP changed in parallel with the

execution of any indirect instruction to permit single-cycle manipulation of data tables. Indirect addressing can

be used with all instructions requiring data operands, except for the immediate operand instructions.

immediate addressing

Immediate instructions derive data from part of the instruction word rather than from part of the data RAM. Some

useful immediate instructions are multiply immediate (MPYK), load accumulator immediate (LACK), and load

auxiliary register immediate (LARK).

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DIGITAL SIGNAL PROCESSORS

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electrical specifications

This section contains all the electrical specifications for the ′C14/E14/P14 devices, including test parameter

measurement information. Parameters with

programming mode.

subscripts apply only to the ′E14 and ′P14 in the EPROM

PP

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

CC

PP

Supply voltage range, V (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W

°

Air temperature range above operating device: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C + 150 C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

4.75

NOM

5

MAX

5.25

UNIT

V

Operating voltage

Fast programming

5.75

6

6.25

V

CC

Supply voltage

SNAP! Pulse programming

6.25

6.5

12.5

13

0

6.75

V

PP

V

PP

V

SS

Supply voltage for Fast programming (see Note 11)

Supply voltage for SNAP! Pulse programming (see Note 11)

Supply voltage

12.25

12.75

13.25

V

CLKIN, CAP0, CAP1, CMP4/CAP2, CMP5/CAP3, RS

All remaining inputs

3

2

V

IH

High-level input voltage

V

Low-level input voltage, all inputs

High-leveloutputcurrent, alloutputs

Low-level output current, all outputs

Operating free-air temperature

0.8

–300

2

V

IL

I

µA

mA

OH

OL

°

C

T

A

0

70

NOTE 11:

V

can be applied only to programming pins designed to accept V as an input. During programming the total supply current

PP

is I

+ I

PP CC

.

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TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

I

= MAX

2.4

3

V

OH

OL

V

High-level output voltage

Low-level output voltage

Off-state output voltage

OH

†

– 0.4

CC

= 20 µA (see Note 7)

V

OL

= MAX

0.3

0.5

20

V

= 2.4 V

= 0.4 V

O

I

V

= MAX

µA

OZ

CC

V = V

–20

±20

±50

90

O

All other inputs except CLKIN

CLKIN

I

Input current

to V

CC

I

SS

§

I

Supply current

f = 25.6 MHz, V

= 5.25 V, T = 0°C to 70°C

70

30

mA

CC

= 5.5 V

A

V

supply current

V

= V

100

µA

PP1

PP

CC

= 13 V

PP

I

V

50

mA

pF

PP2

(during program pulse)

‡

Data bus

25

15

25

10

C

Input capacitance

I

All others

Data bus

All others

f = 1 MHz, All other pins 0 V

Output

capacitance

pF

O

†

‡

§

All typical values are at V

= 5 V, T = 25°C, except I

at 70°C.

CC

Values derived from characterization data and not tested.

characteristics are inversely proportional to temperature.

A

I

CC

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data

sheet are specified for TTL logic levels and will differ for HC logic levels.

PARAMETER MEASUREMENT INFORMATION

2.15 V

R

= 825 Ω

L

From Output

Under Test

Test

Point

C

= 100 pF

L

Figure 5. Test Load Circuit

EXTERNAL CLOCK REQUIREMENTS

The TMS320C14/E14/P14 use an external frequency source for a clock. This source is applied to the CLKIN

pin, and must conform to the specifications in the table below.

PARAMETERS

Input clock frequency

TEST CONDITIONS

= 0°C to 70°C

MIN

NOM

MAX

UNIT

CLKIN

T

6.7

25.6

MHz

A

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DIGITAL SIGNAL PROCESSORS

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CLOCK TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

‡

t

CLKOUT cycle time

156.25

600

c(C)

†

CLKOUT rise time

10

ns

r(C)

R

= 825 Ω,

= 100 pF,

L

†

8

†

72

†

70

†

45

CLKOUT fall time

ns

f(C)

C

L

(see Figure 2)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Delay time CLKIN↑ to CLKOUT↓

ns

w(CL)

w(CH)

d(MCC)

ns

†

Values were derived from characterization data and not tested.

timing requirements over recommended operating conditions

MIN

NOM

40

MAX

UNIT

‡

t

Master clock cycle time

39.06

150

ns

c(MC)

†

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low

Pulse duration, master clock high

5

10

ns

r(MC)

†

f(MC)

†

0.45t

c(MC)

0.55t

c(MC)

w(MCP)

w(MCL)

w(MCH)

†

15

130

15

†

‡

Values were derived from characterization data and not tested.

is the cycle time of CLKOUT, i.e., 4t (4 times CLKIN cycle time if an external oscillator is used).

t

c(C)

c(MC)

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MEMORY READ AND INSTRUCTION TIMING

switching characteristics over recommended operating conditions

TEST

CONDITIONS

PARAMETER

MIN

NOM

MAX

UNIT

t

Address bus valid before REN↓

Address bus valid before WE↓

Address bus valid after REN↑ or WE↑

Data starts being driven before WE↓

Data valid prior to WE↓

0.25 t

–39

–45

ns

su(A)R

c(C)

0.50 t

su(A)W

h(A)

†

5

†

0.25 t

en(D)W

su(D)W

h(D)W

c(C)

0.25 t

–45

–10

R

= 825 Ω,

= 100 pF,

c(C)

L

C

L

Data valid after WE↑

(see Figure 2)

Data in high impedance after WE↑

WE-low duration

0.25 t

c(C)

+ 25

dis(D)W

w(WEL)

w(RENL)

rec(WE)

rec(REN)

d(WE-CLK)

0.50 t

0.75 t

–15

c(C)

REN-low duration

Write recovery time, time between WE↑ and REN↓

Read recovery time, time between REN↑ and WE↓

Time from WE↑ to CLKOUT↑

0.25 t

–5

c(C)

0.50 t

–10

–15

c(C)

†

Values were derived from characterization data and not tested.

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

t

Data set-up prior to REN↑

Data hold after REN↑

52

0

su(D)R

ns

h(D)R

R

= 825 Ω,

= 100 pF,

L

Access time for read cycle data

valid after valid address

C

L

t

–90

ns

a(A)

c(C)

(see Figure 2)

t

Access time for read cycle from REN↓

Data in high impedance after REN↑

0.75 t

–60

†

ns

oe(REN)

c(C)

0.25 t

dis(D)R

c(C)

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

†

t

Delay from RS↓ to REN↑ and WE↑

0.75 t

+ 20

ns

d(RS-RW)

c(C)

Delay from RS↓ to REN and

WE into high impedance

†

1.25 t

ns

R

= 825 Ω,

= 100 pF,

dis(RS-RW)

c(C)

L

C

L

†

t

Data bus disable after RS↓

Address bus disable after RS↓

Address bus enable after RS↑

1.25 t

ns

(see Figure 2)

dis(RS-DB)

dis(RS-AB)

en(RS-AB)

c(C)

t

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

R

= 825 Ω,

= 100 pF,

t

RS setup prior to CLKOUT↓ (see Note 10)

60

ns

L

su(RS)

C

L

RS pulse duration

5t

ns

w(RS)

c(C)

(see Figure 2)

NOTE 10: RS can occur anytime during the clock cycle. Time given is minimum to ensure synchronous operation.

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MICROCOMPUTER/MICROPROCESSOR MODE (NMI/MC/MP)

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

‡

t

Hold time after RS high

t

ns

h(MC/MP)

c(C)

†

‡

Values were derived from characterization data and not tested.

Hold time to put device in microprocessor mode.

INTERRUPT (INT)/NONMASKABLE INTERRUPT (NMI)

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

†

t

Fall time, INT

15

f(INT)

†

Fall time, NMI

ns

f(NMI)

Pulse duration, INT

t

ns

w(INT)

w(NMI)

su(INT)

su(NMI)

c(C)

Pulse duration, NMI

ns

c(C)

60

Setup time, INT before CLKOUT low (see Note 12)

Setup time, NMI before CLKOUT low (see Note 12)

ns

60

ns

NOTE 12: INT and NMI are synchronous inputs and can occur at any time during the cycle. NMI and INT are edge triggered only.

BIT I/O TIMING

switching characteristics over recommended operating conditions

PARAMETER

Rise and fall time outputs

TEST CONDITIONS

MIN

NOM

MAX

UNIT

†

20

R

= 825 Ω,

= 100 pF,

t

ns

L

rfo(IOP)

C

L

CLKOUT low to data valid outputs

0.75 t

+80

ns

d(IOP)

c(C)

(see Figure 2)

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

†

20

t

Rise and fall time inputs

ns

rfl(IOP)

su(IOP)

w(IOP)

R

C

= 825 Ω,

= 100 pF,

L

Data setup time before CLKOUT time

Input pulse duration

40

ns

(see Figure 2)

t

c(C)

GENERAL PURPOSE TIMERS

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

†

t

TCLK1, TCLK2 rise time

TCLK1, TCLK2 fall time

TCLK1, TCLK2 low time

TCLK1, TCLK2 high time

Input pulse duration

20

r(TIM)

†

ns

f(TIM)

R

= 825 Ω,

= 100 pF,

L

C

L

t

+20

+40

ns

wl(TIM)

wh(TIM)

clk(TIM)

c(C)

(see Figure 2)

ns

2t

ns

†

Values were derived from characterization data and not tested.

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TMS320C14, TMS320E14, TMS320P14

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WATCHDOG TIMER TIMING

switching characteristics over recommended operating conditions

PARAMETER

Fall time, WDT

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

†

20

t

f(WDT)

d(WDT)

w(WDT)

R

C

= 825 Ω,

= 100 pF,

L

CLKOUT to WDT valid

0.25 t

)+20

ns

c(C

(see Figure 2)

WDT output pulse duration

7 t

)

ns

c(C

EVENT MANAGER TIMER

switching characteristics over recommended operating conditions

PARAMETER

Fall time, CMP0-CMP5

Rise time, CMP0-CMP5

TEST CONDITIONS

MIN

NOM

MAX

UNIT

†

R

= 825 Ω,

= 100 pF,

t

20

ns

L

f(CMP)

C

L

†

ns

(see Figure 2)

r(CMP)

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

+20

c(C)

MAX

UNIT

R

= 825 Ω,

= 100 pF,

L

t

CAP0-CAP3 input pulse duration

t

ns

w(CAP)

C

L

†

20

Capture input setup time before CLKOUT low

(see Figure 2)

ns

su(CAP)

†

Values were derived from characterization data and not tested.

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TIMING DIAGRAMS

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless

otherwise noted.

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

CLKOUT

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

t

r(C)

f(C)

t

w(CL)

t

c(C)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

†

t

and t

w(MCP)

d(MCC)

memory read timing

REN

t

w(RENL)

t

oe(REN)

t

h(A)

t

su(A)R

A11-A0

D15-D0

Address Bus Valid

t

a(A)

t

su(D)R

t

h(D)R

Instruction Input Valid

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DIGITAL SIGNAL PROCESSORS

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TBLR instruction timing

REN

1

2

3

4

8

t

su(A)R

A11-A0

D15-D0

5

6

7

t

h(D)R

t

a(A)

t

su(D)R

9

10

11

12

Legend:

1. TBLR Instruction Prefetch

2. Dummy Prefetch

3. Data Fetch

4. Next Instruction Prefetch

5. Address Bus Valid

6. Address Bus Valid

7. Address Bus Valid

8. Address Bus Valid

9. Instruction Input Valid

10. Instruction Input Valid

11. Data Input Valid

12. Instruction Input Valid

TBLW instruction timing

REN

1

4

2

3

7

A11-A0

WE

5

6

†

en(D)W

t

w(WEL)

†

t

su(D)W

t

dis(D)W

t

h(D)W

10

D15-D0

8

9

11

†

Data valid prior to WE↓

Legend:

1. TBLW Instruction Prefetch

2. Dummy Prefetch

3. Next Instruction Prefetch

4. Address Bus Valid

5. Address Bus Valid

6. Address Bus Valid

7. Address Bus Valid

8. Instruction Input Valid

9. Instruction Input Valid

10. Data Output Valid

11. Instruction Input Valid

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DIGITAL SIGNAL PROCESSORS

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IN instruction timing

REN

1

2

3

6

t

su(A)R

A11-A0

4

5

t

su(D)R

t

a(A)

t

h(D)R

D15-D0

7

8

9

Legend:

1. IN Instruction Prefetch

2. Data Fetch

3. Next Instruction Prefetch

4. Address Bus Valid

5. Peripheral Address Valid

6. Address Bus Valid

7. Instruction Input Valid

8. Data Input Valid

9. Instruction Input Valid

OUT instruction timing

REN

1

2

3

4

5

A11-A0

t

en(D)W

WE

t

w(WEL)

D15-D0

6

7

t

dis(D)W

t

su(D)W

t

h(D)W

Legend:

1. OUT Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Input Valid

7. Data Output Valid

4. Peripheral Address Valid

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reset timing

CLKOUT

t

su(RS)

t

su(RS)

t

dis(RS-RW)

RS

t

w(RS)

REN

WE

(see

Note E)

t

d(RS-RW)

t

en(RS-AB)

t

dis(RS-DB)

Data Shown Relative To WE

Data Out

D15-D0

Data In From

PC ADDR 0

Data In From

PC ADDR PC+1

t

dis(RS-AB)

AB = PC+1

ADDRESS

BUS

AB = PC

AB = PC = 0

AB = Address Bus

NOTES: A. RS forces REN, and WE high and then places data bus D0-D15, REN, WE, and address bus A0-A11 in a high-impedance state.

AB outputs (and program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↑.

B. RS must be maintained for a minimum of five clock cycles.

C. Resumption of normal program will commence after one complete CLK cycle from RS↑.

D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK

cycle.

E. Diagram shown is for definition purpose only. WE and REN are mutually exclusive.

microcomputer/microprocessor mode timing

CLKOUT

RS

t

h(MC/MP)

NMI/MC/MP

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

44

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

interrupt timing

CLKOUT

t

, t

su(INT) su(NMI)

NMI or INT

t

, t

f(INT) f(NMI)

t

, t

w(INT) w(NMI)

bit I/O timing

CLKOUT

IOP15-IOP0

(Output)

t

rfo(IOP)

t

su(IOP)

IOP15-IOP0

(Input)

t

w(IOP)

t

rfI(IOP)

general purpose timers

t

clk(TIM)

TCLK1, TCLK2

t

wh(TIM)

t

f(TIM)

t

r(TIM)

t

wl(TIM)

watchdog timer

CLKOUT

t

d(WDT)

t

w(WDT)

WDT

t

f(WDT)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

45

TMS320C14, TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

event manager

CLKOUT

t

su(CAP)

CAP3-CAP0

CMP5-CMP0

t

w(CAP)

t

/ t

f(CMP) r(CMP)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

46

TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

PROGRAMMING THE TMS320E14/P14 EPROM CELL

The ′E14 and ′P14 include a 4K × 16-bit industry-standard EPROM cell for prototyping and low-volume

production. The ′C14 with a 4K-word masked ROM then provides a migration path for cost-effective production.

An EPROM adapter socket (part # TMDX3270110), shown in Figure 5, is available to provide 68-pin to 28-pin

conversion for programming the ′E14 and ′P14.

Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM

cell also includes a code protection feature that allows code to be protected against copyright violations.

The ′E14/P14 EPROM cells are programmed using the same family and device codes as the TMS27C64 8K

× 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable,

read-only memories, fabricated using HVCMOS technology. They are pin compatible with existing 28-pin ROMs

andEPROMs. TheseEPROMsoperatefroma5-Vsupplyinthereadmode;however, a12.5-Vsupplyisneeded

forprogramming. AllprogrammingsignalsareTTLlevel. Forprogrammingoutsidethesystem, existingEPROM

programmers can be used. Locations may be programmed singly, in blocks, or at random.

Figure 5. EPROM Adapter Socket

The ′E14/P14 devices use 13 address lines to address the 4K-word memory in byte format (8K-byte memory).

In word format, the most-significant byte of each word is assigned an even address and the least-significant byte

an odd address in the byte format. Programming information should be downloaded to EPROM programmer

memory in a high-byte to low-byte order for proper programming of the devices (see Figure 6).

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

47

TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TMS320C14 On-Chip

Program Memory

(Word Format)

TMS320E14 and

TMS320P14 On-

Chip

EPROM

Programmer

Memory

Program Memory

(Byte Format)

Byte Format with

Adapter Socket

34h

12h

78h

56h

BCh

9Ah

FOh

DEh

.

0(0000h)

12h

34h

56h

78h

9Ah

BCh

DEh

FOh

.

0(0000h)

1(000Ah)

2(0002h)

3(0003h)

1234h

5678h

9ABCh

DEFOh

.

0(0000h)

1(0001h)

2(0002h)

3(0003h)

4(0004h)

5(0005h)

6(0006h)

7(0007h)

.

1(0001h)

2(0002h)

3(0003h)

4(0004h)

5(0005h)

6(0006h)

7(0007h)

.

4095(0FFh)

.

8191(1FFFh)

Figure 6. Programming Data Format

Figure 7 shows the wiring conversion to program the ′E14 and ′P14 using the 28-pin pinout of the TMS27C64.

The table of pin nomenclature provides a description of the TMS27C64 pins.

CAUTION

The ′E14 and ′P14 do not support the signature mode available with some EPROM programmers.

The signature mode places high voltage (12.5 V ) on pin A9. The ′E14 and ′P14 EPROM cells are

dc

not designed for this feature and will be damaged if subjected to it. A 3.9 kΩ resistor is standard

on the TI programmer socket between pin A9 and programmer. This protects the device from

unintentional use of the signature mode.

1

2

3

4

5

6

7

8

9

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

CC

PP

A12

A7

A6

A5

A4

A3

A2

A1

PGM

EPT

A8

9

8

7

6

5

4

3

2

1 68 67 66 65 64 63 62 61

3.9 k Ω

A9

A10

A11

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

A11

G

A10

E

A1

A0

Q8

Q7

Q6

Q5

Q4

A12

PGM

EPT

10

A0

11

12

13

14

Q1

V

Q2

PP

TMS320E14

TMS320P14

Q3

E

GND

TMS27C64 Pinout

G

CLKIN

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Figure 7. TMS320E14/P14 EPROM Programming Conversion to TMS27C64 EPROM Pinout

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

48

TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TERMINAL FUNCTIONS (TMS320E14/P14)

NAME

I/O

DEFINITION

On-chip EPROM programming address lines

A12(MSB)-A0(LSB)

I

CLKIN

I

Clock oscillator input

E

I

EPROM chip enable

EPT

I

EPROM test mode select

G

I

EPROM output enable

GND

PGM

I

Ground

I

EPROM write/program select

Data lines for byte-wide programming of on-chip 8K bytes of EPROM

Reset for initializing the device

5-V to 6.5-V power supply

12.5-V to 13-V power supply

Q8(MSB)-Q1(LSB)

RS

I/O

I

V

CC

V

PP

Table 4 shows the programming levels required for programming, verifying, reading, and protecting the EPROM

cell.

Table 4. TMS320E14/P14 Programming Mode Levels

SIGNAL

NAME

TMS320E14/P14

TMS27C64

PROGRAM

VERIFY

EPROM

PROTECT

VERIFY

PROGRAM

READ

†

E

19

23

20

22

27

1

V

IL

PULSE

IL

PULSE

IH

IL

G

V

IH

IL

PGM

16

PULSE

V

IH

V

IH

V

IH

V

PP

18

V

PP

V

PP

V

PP

V

CC

CCP

V

4,33

3,34

24

28

14

26

V

CCP

V

CCP

V

CCP

CC

CCP

V

SS

V

SS

V

SS

V

SS

V

SS

PP

SS

PP

CLKIN

EPT

V

17

V

42, 41, 38, 37,

32-29

Q1-Q8

11–13, 15-19,

Data In

ADDR

Data Out

ADDR

Data Out

ADDR

Q

= PULSE

X

Q

= RBIT

X

8

2, 23, 21, 24,

25, 3

A12-A7

15, 11, 10, 8, 7, 2

A6

A5

1

4

5

ADDR

X

V

IL

68

67

X

A4

6

V

IH

X

A3-A0

66, 65, 56, 55

7-10

X

†

Signal names shown for ′E14/P14 EPROM programming mode only.

Legend:

V

IH

=

= TTL high level; V = TTL low level; ADDR = byte address bit; V

= 12.5 V ± 0.25 V (FAST) or 13 V ± 0.25 V (SNAP! Pulse).

PP

IL

V

CC

5 V ± 0.25 V; X = don’t care; PULSE = low-going TTL pulse.

D

= byte to be programmed at ADDR; Q

= byte stored at ADDR.; RBIT = ROM protect bit

IN

OUT

= 6 V ± 0.25 V (FAST) or 6.5 V ± 0.25 V (SNAP! Pulse).

V

CCP

programming

Since every memory in the cell is at a logic high, the programming operation reprograms selected bits to low.

Oncethe′320E14isprogrammed, thesebitscanonlybeerasedusingultravioletlight. Thecorrectbyteisplaced

on the data bus with V set to the 12.5-V level. The PGM pin is then pulsed low to program in the zeros.

PP

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

49

TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

erasure

Before programming, the ′E14 must be erased by exposing it to ultraviolet light. The recommended minimum

2

exposure dose (UV-intensity × exposure-time) is 15 W•s/cm . A typical 12-mW•s/cm , filterless UV lamp will

erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After

exposure, all bits are in the high state.

verify/read

To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown

in Table 5, assuming the inhibit bit (RBIT) has not been programmed.

program inhibit

Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.

standard programming procedure

Before programming, the ′E14 must first be completely erased. The device can then be programmed with the

correct code. It is advisable to program unused sections with zeros as a further security measure. After the

programming is complete, the code programmed into the cell should be verified. If the cell passes verification,

the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label

should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this

point, the programming is complete, and the device is ready to be placed into its destination circuit.

Refer to other appendices of the TMS320C1x User’s Guide for additional information on EPROM programming.

recommended timing requirements for programming: V

= 6 V and V

= 12.5 V (FAST) or

CC

PP

V

= 6.5 V and V = 13 V (SNAP! PULSE), T = 25°C (see Note 13)

CC

PP A

MIN

0.95

95

2.85

2

NOM

1

MAX

1.05

UNIT

ms

µs

Fast programming algorithm

SNAP! Pulse programming algorithm

Fast programming only

t

w(PGM)

Initial program pulse duration

100

105

t

Final pulse duration

Address setup time

E setup time

78.75

ms

µs

w(FPGM)

su(A)

2

µs

su(E)

G setup time

2

µs

su(G)

Data setup time

2

µs

su(D)

V

setup time

2

µs

su(VPP)

su(VCC)

h(A)

PP

2

µs

CC

Address hold time

Data hold time

0

µs

2

µs

h(D)

NOTE 13: For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and V

programming.

= 12.5 V ± 0.5 V during

PP

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

50

TMS320E14, TMS320P14

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

program cycle timing

Verify

Program

V

IH

A12-A0

Q8-Q1

Address Stable

su(A)

Address N+1

IL

t

h(A)

/V

IH OH

Data Out

Valid

Data In Stable

t

HI-Z

/V

IL OL

†

t

dis(G)

su(D)

V

PP

V

PP

t

su(VPP)

su(VCC)

V

CC

CCP

V

CC

V

CC

V

IH

V

IL

V

IH

E

t

h(D)

su(E)

PGM

†

t

en(G)

V

IL

t

w(FPGM)

su(G)

V

IH

G

and t

IL

†

t

) are characteristics of the device but must be accommodated by the programmer.

en(G

dis(G)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

51

TMS320C15, TMS320E15, TMS320LC15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Key Features: TM320C15/E15/LC15/P15

+5 V

or

• Instruction Cycle Timing:

— 160-ns (TMS320C15-25/E15-25)

— 200-ns (TMS320C15/E15/P15)

— 250-ns (TMS320LC15)

+3.3 V

GND

• 256 Words of On-Chip Data RAM

256-Word RAM

Interrupt

Data (16)

• 4K Words of On-Chip Program ROM

4K-Word ROM/EPROM

32-Bit ALU/ACC

Multiplier

(TMS320C15/C15-25/LC15)

• 4K Words of On-Chip Program EPROM

(TMS320E15/E15-25)

• One-Time Programmable (OTP) Windowless

Address (12)

EPROM Version Available (TMS320P15)

Shifters

• EPROM Code Protection for Copyright Security

• External Memory up to 4K-Words at Full Speed

• 16 × 16-Bit Multiplier With 32-Bit Product

• 0 to 16-Bit Barrel Shifter

• On-Chip Clock Oscillator

• 3.3-V Low-Power Version Available (TMS320LC15)

• Device Packaging:

— 40-Pin Dip (All Devices)

— 44-Lead PLCC (TMS320C15/C15-25/LC15/P15)

— 44-Lead-QUAD (TMS320E15/E15-25)

TMS320C15/E15/LC15/P15

N/JD Package

TMS320C15/E15/LC15/P15

FN/FZ Package

(Top View)

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

1

A1/PA1

A0/PA0

MC/MP

RS

INT

CLKOUT

X1

A2/PA2

A3

A4

A5

A6

A7

A8

MEN

DEN

WE

2

3

6

5 4 3 2 1 44 43 42 41 40

4

5

39

38

37

36

35

34

33

32

31

30

29

7

CLKOUT

X1

X2/CLKIN

BIO

A7

A8

MEN

DEN

WE

6

8

7

9

8

X2/CLKIN

BIO

10

11

12

13

9

NC

10

11

12

13

14

15

16

17

V

SS

V

SS

CC

D8

D9

V

CC

A9

D8

A9

D9 14

D10 15

D11 16

D12 17

A10

A11

D0

D10

D11

D12

D13

D14

D15

D7

A10

A11

D0

D1

D2

D3

D4

D5

D1

18 19 20 21 22 23 24 25 26 27 28

18 23

19 22

20 21

D6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

52

TMS320C15, TMS320E15, TMS320LC15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

functional block diagram

X1

CLKOUT

X2/CLKIN

16

Program Bus

12 LSB

WE

DEN

MEN

BIO

MUX

12

MC/MP

INT

PC (12)

RS

12

Instruction

12

3

16

A11-A0/

PA2-PA0

Program

ROM/EPROM

(4K Words)

D15-D0

Stack

4 × 12

Program Bus

16

Data Bus

16

7

16

AR0 (16)

AR1 (16)

DP

T(16)

ARP

Shifter

(0–16)

16

8

Multiplier

8

P(32)

32

MUX

8

32

MUX

32

Address

Data RAM

(256 Words)

Legend:

ALU (32)

ACC = Accumulator

Data

32

ALU = Arithmetic Logic Unit

ARP = Auxiliary Register Pointer

AR0 = Auxiliary Register 0

AR1 = Auxiliary Register 1

DP = Data Page Pointer

ACC (32)

32

P

= P Register

PC = Program Counter

= T Register

T

Shifter (0,1,4)

16

Data Bus

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

53

TMS320C15, TMS320E15, TMS320LC15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

†

TERMINAL FUNCTIONS (TMS320C15/E15/LC15/P15)

‡

NAME

A11-A0/PA2-PA0

I/O

DEFINITION

O

I

External address bus. I/O port address multiplexed over PA2-PA0.

External polling input

BIO

CLKOUT

D15-D0

DEN

O

System clock output, 1/4 crystal/CLKIN frequency

16-bit parallel data bus

I/O

O

I

Data enable for device input data on D15-D0

External interrupt input

INT

MC/MP

MEN

NC

I

Memory mode select pin. High selects microcomputer mode. Low selects microprocessor mode.

Memory enable indicates that D15-D0 will accept external memory instruction.

No connection

O

I

RS

Reset for initializing the device

V

I

+ 5 V supply

CC

I

Ground

SS

WE

O

I

Write enable for device output data on D15-D0

Crystal output for internal oscillator

X1

X2/CLKIN

Crystal input internal oscillator or external system clock input

†

‡

See EPROM programming section.

Input/Output/High-impedance state.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

54

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical specifications

This section contains the electrical specifications for the ′C15/E15/P15 digital signal processors, including test

parameter measurement information. Parameters with

programming mode (see Note 11).

subscripts apply only to the ′E15/P15 in the EPROM

PP

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

CC

PP

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 mW

Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

°

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

SS.

recommended operating conditions

MIN

NOM

MAX

UNIT

EPROM devices

All other devices

4.75

4.5

5

5.25

5.5

V

CC

Supply voltage

V

Supply voltage (see Note 11)

Supply voltage

12.25

12.5

0

12.75

V

PP

V

SS

CLKIN

3

2

V

High-level input voltage

IH

All remaining inputs

MC/MP

V

0.6

0.8

V

Low-level input voltage

IL

All remaining inputs

V

I

High-level output current, all outputs

– 300

2

µA

mA

OH

Low-level output current (All outputs except for TMS320LC15)

OL

L suffix

Operating free-air temperature

A suffix

0

70

85

°C

T

A

– 40

NOTE 11: V

PP

can be applied only to programming pins designed to accept V

+ I .

as an input. During programming the total supply current is

PP

I

PP CC

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

55

TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX UNIT

I

= MAX

2.4

3

V

OH

OL

V

High-level output voltage

OH

= 20 µA (see Note 8)

V

– 0.4

CC

V

OL

Low-level output voltage

Off-state output current

= MAX

0.3

0.5

20

V

= 2.4 V

= 0.4 V

O

I

V

= MAX

OZ

CC

µA

–20

±20

±50

55

O

All inputs except CLKIN

CLKIN

I

Input current

V = V

to V

SS CC

I

µA

TMS320C15

TMS320C15-25 f = 25.6 MHz, V

TMS320E15 f = 20.5 MHz, V

f = 20.5 MHz, V

= 5.5 V, T = 0°C to 70°C

45

50

55

65

CC

A

= 5.5 V, T = 0°C to 70°C

65

A

‡

I

Supply current

CC

mA

= 5.25 V, T = – 40°C to 85°C

75

A

TMS320E15-25 f = 25.6 MHz, V

= 5.25 V, T = 0°C to 70°C

85

A

‡

25

‡

15

‡

25

‡

10

Data bus

All other

C

Input capacitance

Output capacitance

i

pF

f =

1 MHz, all other pins 0 V

Data bus

All others

o

†

‡

All typical values are at V

= 5 V, T = 70°C and are used for thermal resistance calculations.

A

CC

characteristics are inversely proportional to temperature. For I

I

dependence on temperature, frequency, and loading, see Figure 3.

CC

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data

sheet are specified for TTL logic levels and will differ for HC logic levels.

CLOCK CHARACTERISTICS AND TIMING

The TMS320C15/E15/P15 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency

of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and

parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be

specified at a load capacitance of 20 pF.

PARAMETER

TMS320C15

TEST CONDITIONS

MIN

6.7

NOM

MAX

20.5

25.6

UNIT

T

= 0°C to 70°C

= – 40°C to 85°C

= 0°C to 70°C

A

Crystal frequency, f

MHz

TMS320E15/P15

T

A

x

TMS320C15-25/E15-25

T

A

C1, C2

T

A

10

pF

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

PARAMETER

TEST CONDITIONS

UNIT

MIN

195.12

NOM

MAX

MIN

NOM

MAX

‡

t

CLKOUT cycle time

CLKOUT rise time

CLKOUT fall time

200

156.25

160

ns

c(C)

r(C)

f(C)

†

10

8

10

8

R

L

= 825 Ω,

†

C

= 100 pF

(see Figure 2)

†

t

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Delay time, CLKIN↑ to CLKOUT↓

92

90

72

70

ns

w(CL)

†

w(CH)

d(MCC)

†

25

†

25

†

50

60

†

‡

Values derived from characterization data and not tested.

is the cycle time of CLKOUT, i.e., 4t (4 times CLKIN cycle time if an external oscillator is used).

t

c(C)

c(MC)

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

timing requirements over recommended operating conditions

TMS320C15/E15/P15

MIN NOM MAX

48.78 50 150

TMS320C15-25/E15-25

UNIT

MIN

NOM

MAX

t

Master clock cycle time

39.06

40

150

ns

c(MC)

†

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low

Pulse duration, master clock high

5

10

5

10

r(MC)

†

10

f(MC)

†

0.4t

c(MC)

0.6t

c(MC)

0.45t

c(MC)

0.55t

c(MC)

w(MCP)

w(MCL)

†

20

15

†

w(MCH)

†

Values derived from characterization data and not tested.

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

NOM MAX

TEST

CONDITIONS

PARAMETER

UNIT

MIN NOM MAX MIN

Delay time, CLKOUT↓ to

address bus valid

†

10

‡

t

d1

50 10

40

ns

†

t

d2

t

d3

t

d4

t

d5

t

d6

t

d7

Delay time, CLKOUT↓ to MEN↓

Delay time, CLKOUT↓ to MEN↑

Delay time, CLKOUT↓ to DEN↓

Delay time, CLKOUT↓ to DEN↑

Delay time, CLKOUT↓ to WE↓

Delay time, CLKOUT↓ to WE↑

1/4t (C) – 5

1/4t

1/2t

+15 1/4t

15 –10

– 5

1/4t

c(C)

+12

12

ns

c

c(C)

†

–10

1

1/4t

–10

– 5

+15

/ t

4 c(C)

1/ t

4 c(C)

+12

12

c(C)

†

15 –10

1/2t

–10

+15 1/2t

15 –10

1/2t

+12

12

c(C)

†

c(C)

†

Delay time, CLKOUT↓ to data bus

OUT valid

+52

t

1/4t

+65

1/4t

ns

d8

d9

c(C)

R

C

= 825 Ω,

= 100 pF

L

Time after CLKOUT↓ that data bus

starts to be driven

†

– 5

†

– 5

t

1/4t

c(C)

(see Figure 2)

Time after CLKOUT↓ that

data bus stops being driven

(TMS320C15/C15-25 only)

†

t

1/4t

+ 40

1/4t

c(C)

+ 40

ns

d10

c(C)

Time after CLKOUT↓ that

data bus stops being driven

(TMS320E15/E15-25 only)

t

1/4t

+ 70

1/4t +70

c(C)

t

Data bus OUT valid after CLKOUT↓

1/4t

– 10

1/4t

– 10

–35

ns

v

c(C)

Address hold time after WE↑, MEN↑,

or DEN↑ (see Note 15)

†

2

†

2

0

h(A-WMD)

Address bus setup time prior to

DEN↓

t

1/4t

–45

1/4t

ns

su(A-MD)

c(C)

†

Values derived from characterization data and not tested.

NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.

timing requirements over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

TEST

CONDITIONS

UNIT

ns

MIN

NOM

MAX

MIN

NOM

MAX

Setup time, data bus valid prior to CLKOU-

T↓

R

C

= 825 Ω,

= 100 pF

(see Figure 2)

L

t

50

40

su(D)

Hold time, data bus held valid after

CLKOUT↓ (see Note 9)

0

ns

h(D)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

1/ t

MAX

UNIT

†

+ 50

R

L

= 825 Ω,

t

Delay time, DEN↑, WE↑, and MEN↑ from RS

ns

d11

2 c(C)

1/ t

C

= 100 pF

†

+ 50

Data bus disable time after RS

ns

dis(R)

(see Figure 2)

4 c(C)

†

Values derived from characterization data and not tested.

timing requirements over recommended operating conditions

TMS320C15/E15/P15

MIN NOM MAX

TMS320C15-25/E15-25

MIN NOM MAX

UNIT

t

Reset (RS) setup time prior to CLKOUT (see Note 10)

RS pulse duration

50

40

ns

su(R)

5t

c(C)

w(R)

c(C)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

t

Fall time, INT

15

ns

f(INT)

Pulse duration, INT

t

w(INT)

su(INT)

c(C)

50

c(C)

40

Setup time, INT↓ before CLKOUT↓

IO (BIO) TIMING

timing requirements over recommended operating conditions

TMS320C15/E15/P15

TMS320C15-25/E15-25

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

t

Fall time, BIO

15

ns

f(IO)

Pulse duration, BIO

t

w(IO)

su(IO)

c(C)

Setup time, BIO↓ before CLKOUT↓

50

40

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TIMING DIAGRAMS

Timingmeasurementsarereferencedtoandfromalowvoltageof0.8voltsandahighvoltageof2.0volts, unless

otherwise noted.

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

CLKOUT

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

t

r(C)

f(C)

t

w(CL)

t

c(C)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

†

t

and t

w(MCP)

d(MCC)

memory read timing

t

c(C)

CLKOUT

t

d2

t

d3

MEN

t

su(A-MD)

t

h(A-WMD)

t

d1

A11-A0

Address Bus Valid

t

su(D)

t

h(D)

Instruction Valid

D15-D0

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TBLR instruction timing

CLKOUT

t

d2

t

d3

t

d3

2

MEN

1

3

7

4

8

t

d1

A11-A0

5

6

t

h(D)

t

su(D)

9

10

11

12

D15-D0

Legend:

1. TBLR Instruction Prefetch

2. Dummy Prefetch

3. Data Fetch

4. Next Instruction Prefetch

5. Address Bus Valid

6. Address Bus Valid

7. Address Bus Valid

8. Address Bus Valid

9. Instruction Valid

10. Instruction Valid

11. Data Input Valid

12. Instruction Valid

TBLW instruction timing

CLKOUT

MEN

1

4

2

5

3

7

A11-A0

6

t

d6

t

d7

WE

t

d8

t

v

t

d10

d9

D15-D0

8

9

10

11

Legend:

1. TBLW Instruction Prefetch

2. Dummy Prefetch

3. Next Instruction Prefetch

4. Address Bus Valid

5. Address Bus Valid

6. Address Bus Valid

7. Address Bus Valid

8. Instruction Valid

9. Instruction Valid

10. Data Output Valid

11. Instruction Valid

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

IN instruction timing

CLKOUT

MEN

1

2

5

t

su(A-MD)

4

t

su(D)

t

A11-A0

3

t

d5

d4

DEN

t

h(D)

D15-D0

6

7

8

Legend:

1. IN Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Input Valid

8. Instruction Valid

4. Peripheral Address Valid

OUT instruction timing

CLKOUT

MEN

A11-A0

WE

1

3

2

4

5

t

d6

d7

t

d9

t

d10

t

d8

t

v

7

6

8

D15-D0

Legend:

1. IN Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Output Valid

8. Instruction Input Valid

4. Peripheral Address Valid

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TMS320C15, TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

reset timing

CLKOUT

t

su(R)

t

su(R)

RS

t

w(R)

DEN

WE

MEN

see

Note E

Data In From

PC ADDR PC+1

Data In From

PC ADDR 0

t

d11

t

dis(R)

Data Shown Relative to WE

D15-D0

MEN

AB = PC+1

AB = Address Bus

AB = PC

Address

Bus

AB = PC = 0

AB = PC+1

NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-

er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.

B. RS must be maintained for a minimum of five clock cycles.

C. Resumption of normal program will commence after one complete CLK cycle from RS↑.

D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK

cycle.

E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.

F. During a write cycle, RS may produce an invalid write address.

interrupt timing

CLKOUT

t

su(INT)

INT

t

f(INT)

t

w(INT)

BIO timing

CLKOUT

t

su(IO)

BIO

t

f(IO)

t

w(IO)

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TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

PP

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

NOM

MAX

UNIT

V

Supply voltage (see Note 11)

can be applied only to programming pins designed to accept V

12.25

12.5

12.75

V

PP

NOTE 11:

V

as an input. During programming the total supply current is

PP

+ I

I

.

PP CC

electrical characteristics over specified temperature range (unless otherwise noted)

‡

PARAMETER

supply current

TEST CONDITIONS

MIN

TYP

MAX

100

50

UNIT

V

I

V

= V

5.5 V

PP1 PP

PP

CC

= 12.75 V

V

supply current (during program pulse)

V

30

V

PP2 PP

‡

All typical values except for I

CC

are at V

= 5 V, T = 25°C.

CC A

recommended timing requirements for programming, T = 25°C, V

= 6, V

= 12.5 V,

A

CC

PP

(see Note 13)

MIN

NOM

MAX

1.05

63

UNIT

ms

µs

t

Initial program pulse duration

Final pulse duration

Address setup time

E setup time

0.95

3.8

2

1

w(IPGM)

w(FPGM)

su(A)

2

µs

su(E)

G setup time

2

µs

su(G)

Output disable time from G (see Note

15)

§

t

0

130

ns

dis(G)

t

Output enable time from G

Data setup time

0

2

0

2

150

ns

µs

en(G)

su(D)

V

setup time

su(VPP)

su(VCC)

h(A)

PP

CC

Address hold time

Data hold time

h(D)

§

Values derived from characterization data and not tested.

NOTES: 13. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and V

programming.

= 12.5 V ± 0.5 V during

PP

15. Common test conditions apply for t

except during programming.

dis(G)

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TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

PROGRAMMING THE TMS320E15/P15 EPROM CELL

′E15/P15 devices include a 4K × 16-bit industry-standard EPROM cell for prototyping, early field testing, and

low-volume production. In conjunction with this EPROM, the ′E15/P15 with a 4K-word masked ROM, then,

provide more migration paths for cost-effective production.

EPROM adapter sockets are available that provide pin-to-pin conversions for programming any ′E15/P15

devices. One adapter socket (part number RTC/PGM320C-06), shown in Figure 8, converts a 40-pin DIPdevice

into an equivalent 28-pin device. Another socket (part number RTC/PGM320A-06), not shown, permits 44- to

28-pin conversion.

Figure 8. EPROM Adapter Socket (40-pin to 28-pin DIP Conversion)

Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM

cell also includes a code protection feature that allows code to be protected against copyright violations.

The ′E15/P15 EPROM cell is programmed using the same family and device pinout codes as the TMS27C64

8K × 8-bit EPROM. The TMS27C64 EPROM series are unltraviolet-light erasable, electrically programmable,

read-only memories, fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin

ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however, a 12.5-V

supplyisneededforprogramming. AllprogrammingsignalsareTTLlevel. Forprogrammingoutsidethesystem,

existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.

Figure 9 shows the wiring conversion to program the ′E15/P15 using the 28-pin pinout of the TMS27C64.

Table 5 on pin nomenclature provides a description of the TMS27C64 pins. The code to be programmed into

the device should be in serial mode. The ′E15/P15 devices use 13 address lines to address 4K-word memory

in byte format.

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TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

A1

1

2

3

4

A2

A3

A4 38

A5 37

40

39

A0(LSB)

VPP

RS

28

27

26

25

24

23 A11

22 G

21 A10

20 E

19

18

17

16

15

V

5

6

7

8

V

1

2

3

4

5

6

7

8

9

EPT

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A6

A7

A8

CC

PP

PGM

EPT

A8

A12

A7

A6

A5

A4

A3

A2

A1

A0 10

Q1 11

Q2 12

Q3 13

GND 14

CLKIN

3.9 kΩ

A9

9

10

11

12

13

14

15

16

17

18

19

20

GND

Q1(LSB)

Q2

Q3

Q4

Q5

Q6

Q7

Q8(MSB)

V

CC

A9

A10

A11

Q8

Q7

Q6

Q5

Q4

(MSB)A12

E

G

PGM

TMS27C64

PINOUT

TMS27C64

PINOUT

TMS320E15/P15

CAUTION

Although acceptable by some EPROM programmers, the signature mode cannot be used on any ′E1x

device. The signature mode will input a high-level voltage (12.5 V ) onto pin A9. Since this pin is not

dc

designed for high voltage, the cell will be damaged. To prevent an accidental application of voltage,

Texas Instruments has inserted a 3.9 kΩ resistor between pin A9 of the TI programmer socket and the

programmer itself.

Pin Nomenclature (TMS320E15/P15)

NAME

A0-A12

I/O

DEFINITION

I

On-chip EPROM programming address lines

Clock oscillator input

CLKIN

E

I

EPROM chip select

EPT

G

GND

PGM

Q1-Q8

RS

I

EPROM test mode select

EPROM read/verify select

Ground

EPROM write/program select

Data lines for byte-wide programming of on-chip 8K bytes of EPROM

Reset for initializing the device

5-V power supply

I/O

I

V

CC

V

PP

12.5-V power supply

Figure 9. TMS320E15/P15 EPROM Programming Conversion to TMS27C64 EPROM Pinout

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TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Table 5 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell.

Table 5. TMS320E15/P15 Programming Mode Levels

SIGNAL NAME TMS320E15 PIN TMS27C64 PIN PROGRAM

VERIFY

READ

PROTECT VERIFY EPROM PROTECT

E

G

25

20

V

IH

V

IH

V

IH

IL

PULSE

IL

PULSE

IL

24

22

V

IH

IL

PGM

23

27

PULSE

V

IH

V

IH

V

IH

V

3

1

V

CC

V

CC

V

CC

V

CC

+ 1

V

PP

CC

PP

+ 1

V

CC

30

28

V

CC

V

CC

V

10

14

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN

RS

8

14

SS

PP

SS

PP

4

5

14

EPT

26

Q1-Q8

A0-A3

A4

11-18

2, 1, 40, 39

38

11-13, 15-19

D

Q

OUT

Q8=RBIT

Q8=PULSE

X

IN

OUT

10-7

ADDR

X

6

V

IH

A5

37

5

X

A6

36

4

V

IL

X

A7-A9

A10-A12

35, 34, 29

28-26

3, 25, 24

21, 23, 2

X

Legend:

V

= TTL high level; V = TTL low level; ADDR = byte address bit

IL

PP

IH

= 12.5 V ± 0.25 V; V

= 5 V ± 0.25 V; X = don’t care

CC

PULSE = low-going TTL level pulse; D = byte to be programmed at ADDR

Q

IN

= byte stored at ADDR; RBIT = ROM protect bit.

OUT

programming

Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once

programmed, these bits can only be erased using ultraviolet light. The correct byte is placed on the data bus

with V set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeros.

PP

erasure

Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum

2

exposuredose(UV-intensity× exposure-time)is15W•s/cm . Atypical12-mW/cm , filterlessUVlampwillerase

the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After

exposure, all bits are in the high state.

verify/read

To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown

in Table 5, assuming the inhibit bit has not been programmed.

program inhibit

Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.

read

The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect

bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents

of the EPROM location selected by the value on the address inputs appear on Q8-Q1.

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TMS320E15, TMS320P15

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

output disable

DuringtheEPROMprogrammingprocess, theEPROMdataoutputsmaybedisabled, ifdesired, byestablishing

the output disable state. This state is selected by setting G and E pins high. While output disable is selected,

Q8-Q1are placed in the high-impedance state.

EPROM protection

To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code

from external accesses can be completely disabled. Programming the RBIT disables external access of the

EPROM cell and disables the microprocessor mode, making it impossible to access the code resident in the

EPROM cell. The only way to remove this protection is to erase the entire EPROM cell, thus removing the

proprietary information. The signal requirements for programming this bit are shown in Table 5. The cell can be

determined as protected by verifying the programming of the RBIT shown in the table.

standard programming procedure

Before programming, the device must first be completely erased. Then the device can be programmed with the

correct code. It is advisable to program unused sections with zeroes as a further security measure. After the

programming is complete, the code programmed into the cell should be verified. If the cell passes verification,

the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label

should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this

point, the programming is complete, and the device is ready to be placed into its destination circuit.

program cycle timing

Verify

Program

V

IH

A12-A0

Q8-Q1

Address Stable

HI-Z

Address N+1

IL

t

su(A)

h(A)

/V

IH OH

Data Out

Valid

Data In Stable

/V

IL OL

t

dis(G)

su(D)

V

PP

V

PP

V

CC

su(VPP)

su(VCC)

+1

CC

V

CC

V

t

V

IH

V

IL

V

IH

E

t

su(E)

t

h(D)

PGM

G

t

su(G)

V

IL

V

IH

V

IL

t

en(G)

w(IPGM)

t

w(FPGM)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

68

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

CC

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.5

CC

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mW

Air temperature range above operating devices: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +150°C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

NOM

3.3

0

MAX

UNIT

V

Supply voltage

3.0

3.6

CC

V

SS

All inputs except CLKIN

CLKIN

2.0

2.5

V

IH

High-level input voltage

V

Low-level input voltage

All inputs

0.55

–300

1.5

V

IL

I

High-level output current (all outputs)

Low-level output current (all outputs)

µA

mA

°C

OH

OL

L version

A version

0

70

T

A

Operating free-air temperature

–40

85

electrical characteristics over specified temperature range (unless otherwise noted)

†

TYP

PARAMETER

High-level output voltage

Low-level output voltage

TEST CONDITIONS

MIN

MAX

UNIT

I

= MAX

2.0

V

OH

OL

V

OH

‡

– 0.4

CC

= 20 µA (see Note 7)

V

OL

= MAX

0.5

20

V

= V

CC = MAX,

O

CC

SS

µA

I

Off-state ouput current

Input current

OZ

I

–20

±20

±50

O

V = V

to V

All inputs except CLKIN

CLKIN

I

SS

CC

I

V = V

I

‡

25

‡

15

‡

25

‡

10

Data bus

All others

Data bus

All others

pF

C

Input capacitance

Output capacitance

i

f = 1 MHz, All other pins 0 V

o

†

‡

All typical values are at V

= 3.3 V, T = 25°C.

A

CC

Values derived from characterization data and not tested.

NOTE 7: This voltage specification is included for interface to HC logic. However, note that all of the other timing parameters defined in this data

sheet are specified for TTL logic levels and will differ for HC logic levels.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

69

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

N Package

(Top View)

FN Package

(Top View)

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

1

A1/PA1

A0/PA0

MC/MP

RS

INT

CLKOUT

X1

A2/PA2

A3

A4

A5

A6

A7

A8

MEN

DEN

WE

2

3

6

5 4 3 2 1 44 43 42 41 40

4

5

39

38

37

36

35

34

33

32

31

30

29

7

CLKOUT

X1

X2/CLKIN

BIO

A7

A8

MEN

DEN

WE

6

8

7

9

8

X2/CLKIN

BIO

10

11

12

13

9

NC

10

11

12

13

14

15

16

17

V

SS

V

SS

CC

D8

D9

V

CC

A9

D8

A9

D9 14

D10 15

D11 16

D12 17

A10

A11

D0

D10

D11

D12

D13

D14

D15

D7

A10

A11

D0

D1

D2

D3

D4

D5

D1

18 19 20 21 22 23 24 25 26 27 28

18 23

19 22

20 21

D6

INTERNAL CLOCK OPTION

′320LC15

X1

X2/CLKIN

Crystal

C1

C2

PARAMETER MEASUREMENT INFORMATION

1.75 V

R

= 825 Ω

L

From Output

Under Test

Test

Point

C

= 100 pF

L

Figure 10. Test Load Circuit

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

70

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

CLOCK CHARACTERISTICS AND TIMING

The ′LC15 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency

of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and

parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified

at a load capacitance of 20 pF.

PARAMETER

Crystal frequency f

TEST CONDITIONS

= – 40°C to 85°C

MIN

NOM

MAX

UNIT

MHz

pF

4.0

16

x

T

A

C1, C2

10

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

†

t

CLKOUT cycle time

CLKOUT rise time

CLKOUT fall time

250

1000

c(C)

‡

R

= 825 Ω,

10

ns

r(C)

L

C

= 100 pF,

L

8

ns

f(C)

Pulse duration, CLKOUT low

(see Figure 2)

117

115

ns

w(CL)

ns

w(CH) Pulse duration, CLKOUT high

Delay time, CLKIN↑ to CLKOUT↓

20

70

ns

d(MCC)

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Master clock cycle time

62.5

150

c(MC)

‡

†

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low at t

5

10

ns

r(MC)

5

10

ns

f(MC)

‡

0.4t

0.6t

c(MC)

ns

w(MCP)

w(MCL)

w(MCH)

c(MC)

min

26

ns

c(MC)

Pulse duration, master clock high at t

min

ns

c(MC)

†

‡

t

is the cycle time of CLKOUT, i.e., 4t

c(MC)

(4 times CLKIN cycle time if an external oscillator is used)

c(C)

Values derived from characterization data and not tested.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

71

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

electrical characteristics over specified temperature range (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

f = 16.0 MHz, V = 3.6 V, T = 0°C to 70°C

MIN

TYP

MAX

UNIT

‡

I

15

20

mA

CC

A

†

‡

All typical values are at T = 70°C and are used for thermal resistance calculations.

A

I

characteristics are inversely proportional to temperature. For I

CC

dependence on frequency, see figure below.

CC

§

typical power vs. frequency graph (outputs unloaded)

20.0

15.0

10.0

5.0

V

= 3.5 V

CC

V

= 3 V

CC

0.0

16

12

14

0

2

4

6

8

10

CLKIN Frequency, MHz

–40°C to 85°C Temperature Range

§

Device operation is not guaranteed below 4 MHz CLKIN.

Graph is for device in RESET; i.e., only clock-out is driven.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

72

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

ns

†

10

t

Delay time CLKOUT↓ to address bus valid

Delay time CLKOUT↓ to MEN↓

75

d1

†

1/4 t

–10

–5

1/4 t

1/2 t

1/4 t

+25

30

d2

c(C)

†

c(C)

t

d3

Delay time CLKOUT↓ to MEN↑

t

d4

Delay time CLKOUT↓ to DEN↓

1/4 t

+25

30

c(C)

t

d5

Delay time CLKOUT↓ to DEN↑

–10†

t

d6

Delay time CLKOUT↓ to WE↓

1/2 t

+25

30

R

= 825Ω,

= 100 pF,

c(C)

L

C

L

†

–10

t

Delay time CLKOUT↓ to WE↑

d7

(see Figure 2)

Delay time CLKOUT↓ to data bus OUT valid

Time after CLKOUT↓ that data bus starts to be driven

Time after CLKOUT↓ that data bus stops being driven

Data bus OUT valid after CLKOUT↓

Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14)

Address bus setup time to DEN↓

+75

d8

†

–5

1/4 t

d9

c(C)

+60

d10

1/4 t

0

–10

v

†

h(A-WMD)

su(A-MD)

†

– 4

†

Values derived from characterization data and not tested.

NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

56

0

NOM

MAX

UNIT

ns

R

= 825Ω,

= 100 pF,

t

Setup time data bus valid prior to CLKOUT↓

L

su(D)

C

L

Hold time, data bus held valid after CLKOUT↓ (see Note 9)

ns

(see Figure 2)

h(D)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

73

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

RESET (RS) TIMING

switching characteristics over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

R

= 825Ω,

= 100 pF,

t

Delay time, DEN↑, WE↑, and MEN↑ from RS

1/2t

c(C)

1/4t

+75

L

d11

C

L

Data bus disable time after RS

+75

c(C)

ns

(see Figure 2)

dis(R)

†

These parameters do not apply to this device.

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Reset (RS) setup time prior to CLKOUT (see Note 10)

RS pulse duration

85

su(R)

5t

c(C)

ns

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Fall time, INT

15

F(INT)

w(INT)

su(INT)

Pulse duration, INT

t

ns

c(C)

85

Setup time, INT↓ before CLKOUT↓

ns

I/O (BIO) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Fall time BIO

15

f(IO)

Pulse duration BIO

t

ns

w(IO)

su(IO)

c(C)

85

Setup time BIO↓ before CLKOUT↓

ns

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

74

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

CLKOUT

t

r(C)

f(C)

t

w(CL)

t

c(C)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

†

t

and t

w(MCP)

d(MCC)

IN instruction timing

CLKOUT

MEN

PA2-PA0

DEN

1

2

5

t

su(A-MD)

4

t

su(D)

t

3

t

d5

d4

t

h(D)

D15-D0

6

7

8

Legend:

1. IN Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Input Valid

8. Instruction Valid

4. Peripheral Address Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

75

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

OUT instruction timing

CLKOUT

MEN

1

3

2

5

4

PA2-PA0

t

d6

d7

WE

t

d9

t

d10

t

d8

t

v

7

6

8

D15-D0

Legend:

1. OUT Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Output Valid

8. Instruction Valid

4. Peripheral Address Valid

external memory read timing

t

c(C)

CLKOUT

t

d2

t

d3

MEN

t

su(A-MD)

t

h(A-WMD)

t

d1

A11-A0

Address Bus Valid

t

su(D)

t

h(D)

Instruction Valid

D15-D0

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

76

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

TBLR instruction timing

CLKOUT

MEN

t

d2

t

d3

t

d3

2

1

3

7

4

8

t

d1

A11-A0

5

6

t

h(D)

t

su(D)

9

10

11

12

D15-D0

Legend:

1. TBLR Instruction Prefetch

2. Dummy Prefetch

3. Data Fetch

7. Address Bus Valid

8. Address Bus Valid

9. Instruction Valid

4. Next Instruction Prefetch

5. Address Bus Valid

6. Address Bus Valid

10. Instruction Valid

11. Data Input Valid

12. Instruction Valid

TBLW instruction timing

CLKOUT

MEN

1

4

2

3

7

A11-A0

WE

5

6

t

d6

t

d7

t

d10

t

d8

t

v

d9

D15-D0

8

9

10

11

Legend:

1. TBLW Instruction Prefetch

2. Dummy Prefetch

3. Next Instruction Prefetch

7. Address Bus Valid

8. Instruction Valid

9. Instruction Valid

4. Address Bus Valid

5. Address Bus Valid

6. Address Bus Valid

10. Data Output Valid

11. Instruction Valid

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

77

TMS320LC15

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

reset timing

CLKOUT

t

su(R)

t

su(R)

RS

t

w(R)

DEN

WE

MEN

(see

Note E)

Data In From

PC ADDR PC+1

Data In From

PC ADDR 0

t

d11

t

dis(R)

Data Shown Relative To WE

D15-D0

MEN

AB = PC+1

AB = Address Bus

AB = PC

ADDRESS

BUS

AB = PC = 0

AB = PC+1

NOTES: A. RS forces DEN, WE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and program count-

er) are synchronously cleared to zero after the next complete CLK cycle from RS↓.

B. RS must be maintained for a minimum of five clock cycles.

C. Resumption of normal program will commence after one complete CLK cycle from RS↑.

D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK

cycle.

E. Diagram shown is for definition purpose only. DEN, WE, and MEN are mutually exclusive.

F. During a write cycle, RS may produce an invalid write address.

interrupt timing

CLKOUT

t

su(INT)

INT

t

f(INT)

t

w(INT)

BIO timing

CLKOUT

t

su(IO)

BIO

t

f(IO)

t

w(IO)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

78

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

+5 V

GND

Key Features: TMS320C16

• 114-ns Instruction Cycle Time

• 256 Words of On-Chip Data RAM

• 8K Words of On-Chip Program ROM

256-Word RAM

Interrupt

Data (16)

• 64K Words Total External Memory at

8K-Word ROM

32-Bit ALU/ACC

8-Level Stack

Multiplier

Full Speed

• 8 Level Stack

• 32-Bit ALU/Accumulator

• 16 × 16-Bit Multiplier With 32-Bit Product

• 16-Bit Barrel Shifter

Address (12)

• Eight Input and Eight Output Channels

Shifters

• Simple Memory and I/O Interface:

— Memory Write Enable Signal MWE

— I/O Write Enable Signal IOWE

• Single 5-V Supply

• 64-Pin Quad Flatpack (PG Suffix)

PG Package

(Top View)

• Operating Free-Air Temperature Range

. . . 0°C to 70°C

64 63 62 61 60 59 58 57 56 55 54 53 52

1

2

3

4

5

6

7

8

51

50

49

48

47

46

45

44

NC

RS

X1

NC

A0/PA0

A1/PA1

A2/PA2

A3

A4

A5

A6

X2/CLKIN

V

SS

V

SS

V

SS

V

SS

9

43

42

41

40

39

38

37

36

35

34

33

CLKOUT

D15

10

11

12

13

14

15

16

17

18

19

V

A7

SS

D14

NC

D13

D12

D11

D10

D9

NC

A8

A9

A10

A11

A12

A13

A14

NC

20 21 22 23 24 25 26 27 28 29 30 31 32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

79

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

TERMINAL FUNCTIONS

DESCRIPTION

†

I/O/Z

NAME

NO.

ADDRESS/DATA BUSES

A15 MSB

A14

32

34

35

36

37

38

39

40

41

43

44

45

46

47

48

49

I/O/Z

Programmemory address bus A15 (MSB) through A0 (LSB) and port addresses PA2 (MSB) through

PA0 (LSB). Addresses A15 through A0 are always active and never go to high impedance. During

executionoftheINandOUTinstructions, pinsA2throughA0carrytheportaddresses. (Addresspins

A15 through A3 are always driven low on IN and OUT instruction.

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2/PA2

A1/PA1

A0/PA0

D15 MSB

D14

D13

D12

D11

D10

D9

10

11

13

14

15

16

17

20

21

22

23

25

27

28

30

31

I/O/Z

Parallel data bus D15 (MSB) through D0 (LSB). The data bus is always in the high-impedance state

except when IOWE or MWE are active (low).

D8

D7

D6

D5

D4

D3

D2

D1

D0 LSB

†

Input/Output/High-impedance state.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

80

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

TERMINAL FUNCTIONS (concluded)

DESCRIPTION

†

I/O/Z

NAME

NO.

INTERRUPT AND MISCELLANEOUS SIGNALS

External polling input. Polled by BIOZ instruction. If low, the device branches to the address

specified by the instruction.

BIO

64

I

Data enable for device input data. When active (low), IOEN indicates that the device will

accept data from the data bus. IOEN is active only during the IN instruction. When IOEN is

active, MEN, IOWE, and MWE will always be inactive (high).

IOEN

IOWE

INT

54

52

63

62

O

I

Write enable for device output data. When active (low), IOWE indicates that data will be

outputfromthedeviceonthedatabus.IOWEisactiveonlyduringtheOUTinstruction.When

IOWE is active, MEN, IOEN, and MWE will always be inactive (high).

External interrupt input. The interrupt signal is generated by applying a negative-going edge

to the INT pin. The edge is used to latch the interrupt flag register (INTF) until an interrupt

is granted by the device. An active low level will also be sensed.

Memory mode select pin. High selects the microcomputer mode, in which 8K words of

on-chip program memory are available. A low on MC/MP pin enables the microprocessor

mode. In this mode, the entire memory space is external; i.e., addresses 0 through 65535.

MC/MP

I

Memory enable. MEN is an active (low) control signal generated by the device to enable

instruction fetches from program memory. MEN will be active on instructions fetched from

both internal and external memory. When MEN is active, MWE, IOWE, and IOEN will be

inactive (high).

MEN

56

O

Write enable for device output data. When active (low), MWE indicates that data will be

output from the device on the data bus. MWE is active only during the TBLW instruction.

When MWE is active, MEN, IOEN, and IOWE will always be inactive (high).

MWE

NC

53

O

1, 12, 18, 19,

24, 29, 33,

50, 51, 55

—

No connection.

Schmitt-triggered input for initializing the device. When held active for a minimum of five

clock cycles. IOEN, IOWE, MWE, and MEN are forced high; and, the data bus (D15 through

D0) is not driven. The program counter (PC) and the address bus (A15 through A0) are then

synchronously cleared after the next complete clock cycle from the falling edge of RS. Reset

also disables the interrupt, clears the interrupt flag register, and leaves the overflow mode

register unchanged. The device can be held in the reset state indefinitely.

RS

2

I

SUPPLY/OSCILLATOR SIGNALS

†

I/O/Z

DESCRIPTION

NAME

CLKOUT

NO.

9

O

I

System clock output (one-fourth crystal/CLKIN frequency).

5-V suppy pins.

26, 57, 58,

59, 60

V

DD

5, 6, 7, 8,

42, 61

I

O

I

Ground pins.

SS

Crystal output pin for internal oscillator. If the internal oscillator is not used, this pin should

be left unconnected.

X1

3

4

Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin for an

external oscillator (CLKIN).

X2/CLKIN

†

Input/Output/High-impedance state.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

81

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

functional block diagram

CLKOUT X1 X2/CLKIN

Program Bus

16 LSB

IOEN

16

MWE

IOWE

MEN

BIO

MUX

16

MC/MP

INT

PC (16)

16

RS

Instruction

16

A15-A0/

PA2-PA0

Program

ROM

D15-D0

(8K Words)

Stack

8 × 16

3

Program Bus

16

Data Bus

7

16

AR0 (16)

AR1 (16)

ARP

DP

T(16)

Shifter

(0–16)

16

8

Multiplier

8

P(32)

32

MUX

8

32

MUX

32

Address

Data RAM

(256 Words)

ALU (32)

DATA

Legend:

ACC= Accumulator

32

ARP= Auxiliary Register Pointer

AR0 = Auxiliary Register 0

AR1 = Auxiliary Register 1

ACC (32)

32

DP

P

=

Data Page Pointer

P Register

PC

T

Program Counter

T Register

Shifter (0,1,4)

16

Data Bus

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82

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

CC

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W

Operating free-air temperature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

°

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

SS.

recommended operating conditions

MIN

NOM

MAX

UNIT

V

Supply voltage

4.75

5

0

5.25

V

CC

SS

All inputs except CLKIN

CLKIN

2

3

V

High-level input voltage

Low-level input voltage

IH

IL

V

All inputs except MC/MP

MC/MP

0.8

0.6

V

I

High-level output current, all outputs

Low-level output current

–300

2

µA

mA

OH

OL

T

A

Operating free-air temperature

0

70

°C

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

High-level output voltage

Low-level output voltage

Off-state output current

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

= MAX

= 20 µA

= MAX

2.4

3

OH

OL

V

OH

V

CC

– 0.4

V

I

0.3

0.5

20

OL

V

= 2.4 V

= 0.4 V

O

V

= MAX

µA

CC

OZ

–20

±20

±50

75

O

All inputs except CLKIN

CLKIN

I

V

= V

to V

CC

µA

mA

pF

Input current

CC

SS

I

Supply current

f = 35 MHz, V

CC

= 5.25 V

60

25

15

25

10

CC

Data bus

All others

Data bus

All others

C

Input capacitance

Output capacitance

i

f = 1 MHz, all other pins 0 V

pF

o

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83

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

internal clock option

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

MHz

pF

Crystal frequency, f

T

= 0°C to 70°C

6.7

35.1

x

A

C1, C2

T

10

A

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Master clock cycle time

28.49

28.57

150

ns

c(MC)

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low

Pulse duration, master clock high

5

10

ns

r(MC)

f(MC)

0.45t

0.55t

c(C)

w(MCP)

w(MCL)

w(MCH)

c(C)

10

switching characteristics over recommended operating conditions

PARAMETER

MIN

NOM

114.3

10

MAX

UNIT

ns

t

CLKOUT cycle time

113.96

600

c(C)

CLKOUT rise time

ns

r(C)

CLKOUT fall time

8

ns

f(C)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Delay time, CLKIN↑ to CLKOUT↓

49

47

ns

w(CL)

w(CH)

d(MCC)

ns

5

50

ns

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84

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

MIN

NOM

MAX

UNIT

ns

t

Delay time, MEN↑, MWE↑, IOEN↑, IOWE↑, to next address bus valid

Delay time, CLKOUT↓ to MEN↓

0

35

d1

1

/ t

– 5

/ t +12

4 c(C)

d2

4 c(C)

– 3

Delay time, CLKOUT↓ to MEN↑

6

d3

Delay time, CLKOUT↓ to IOEN↓

/ t

4 c(C)

+12

d4

4 c(C)

Delay time, CLKOUT↓ to IOEN↑

– 3

6

d5

Delay time, CLKOUT↓ to MWE↓, IOWE↓

/ t

2 c(C)

d6

2 c(C)

Delay time, CLKOUT↓ to MWE↑, IOWE↑

– 3

6

d7

Delay time, MWE↓, IOwE↓, data bus out valid

Delay time, CLKOUT↓ to data bus starts to be driven

Delay time, MEN↑, to data bus starts to be driven

Delay time, CLKOUT↓ to data bus stops being driven

Delay time, MWE↑, IOWE↑, data bus stops being driven

Data bus OUT valid after MWE↑, IOWE↑

0

d8

1

/ t

4 c(C)

– 5

d9(CLK)

d9(MEN)

d10(CLK)

d10(WE)

v

1

/ t

4 c(C)

15

20

5

0

5

10

2

Address bus hold time after MWE↑, MEN↑, IOWE↑, or IOEN↑

Address bus setup time prior to MEN↓, IOEN↓

h(A-WMD)

su(A-MD)

timing requirements over recommended operating conditions

MIN

MAX

UNIT

t

Setup time, data bus valid prior to MEN↑, IOEN↑

Hold time, data bus held valid after MEN↑, IOEN↑

35

ns

su(D)

0

ns

h(D)

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

MIN

MAX

UNIT

1

t

Delay time, IOEN↑, IOWE↑, MWE↑, and MEN↑ from RS

/ t

2 c(C)

+50

ns

d11

1

Data bus disable time after RS

/ t

4 c(C)

ns

dis(R)

timing requirements over recommended operating conditions

MIN

MAX

UNIT

ns

t

Reset (RS) setup time prior to CLKOUT

RS pulse duration

30

su(R)

5t

c(C)

ns

w(R)

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85

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

INTERRUPT (INT) TIMING

timing requirements over recommended operating conditions

MIN

MAX

UNIT

t

Fall time, INT

15

ns

f(INT)

Pulse duration, INT

t

ns

w(INT)

su(INT)

c(C)

Setup time, INT↓ before CLKOUT↓

30

IO (BIO) TIMING

timing requirements over recommended operating conditions

MIN

MAX

UNIT

t

Fall time, BIO

15

ns

f(IO)

Pulse duration, BIO

t

ns

w(IO)

su(IO)

c(C)

Setup time, BIO↓ before CLKOUT↓

30

TIMING DIAGRAMS

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless

otherwise noted.

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

CLKOUT

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

t

r(C)

f(C)

t

w(CL)

t

c(C)

†

t

and t

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

w(MCP)

d(MCC)

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86

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

memory read timing

t

c(C)

CLKOUT

t

d2

t

d3

MEN

t

su(A-MD)

t

h(A-WMD)

t

d1

A15-A0

Address Bus Valid

t

su(D)

t

h(D)

Instruction Input Valid

D15-D0

IN instruction timing

CLKOUT

MEN

1

2

5

t

su(A-MD)

A15-A0

3

4

t

su(D)

t

d4

t

d5

IOEN

t

h(D)

D15-D0

6

7

8

Legend:

1. IN instruction prefetch

2. Next instruction prefetch

3. Address bus valid

5. Address bus valid

6. Instruction input valid

7. Data input valid

4. Peripheral address valid

8. Instruction input valid

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87

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

OUT instruction timing

CLKOUT

MEN

1

3

2

5

t

d6

4

A15-A0

IOWE

t

d8

t

d7

t

d10(WE)

t

d9(MEN)

t

v

t

d10(CLK)

8

d9(CLK)

D15-D0

6

7

Legend:

1. OUT instruction prefetch

2. Next instruction prefetch

3. Address bus valid

5. Address bus valid

6. Instruction valid

7. Data output valid

8. Instruction valid

4. Peripheral address valid

TBLR instruction timing

CLKOUT

t

d2

t

d3

MEN

t

d1

A15-A0

t

h(D)

t

su(D)

D15-D0

TBLW instruction timing

CLKOUT

MEN

t

d6

A15-A0

t

d8

t

d7

MWE

t

d10(WE)

t

d9(MEN)

t

v

t

d10(CLK)

8

d9(CLK)

D15-D0

6

7

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88

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

reset timing

CLKOUT

t

su(R)

t

su(R)

RS

t

w(R)

IOEN, IOWE

(see

MEN, MWE

D15-D0

MEN

Data In From

PC ADDR PC+1

Data In From

PC ADDR 0

Note E)

t

d11

t

dis(R)

Data

Out

Data Shown Relative To IOWE

AB = PC+1

AB = Address Bus

AB = PC

Address

Bus

AB = PC = 0

AB = PC+1

NOTES: A. RS forces IOEN, IOWE, MWE, and MEN high and places data bus D0 through D15 in a high-impedance state. AB outputs (and

program counter) are synchronously cleared to zero after the next complete CLK cycle from RS↓.

B. RS must be maintained for a minimum of five clock cycles.

C. Resumption of normal program will commence after one complete CLK cycle from RS↑.

D. Due to the synchronization action on RS, time to execute the function can vary dependent upon when RS↑ or RS↓ occur in the CLK

cycle.

E. Diagram shown is for definition purpose only. IOEN, IOWE, MWE, and MEN are mutually exclusive.

F. During a write cycle, RS may produce an invalid write address.

interrupt timing

CLKOUT

t

su(INT)

INT

t

f(INT)

t

w(INT)

BIO timing

CLKOUT

t

su(IO)

BIO

t

f(IO)

t

w(IO)

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89

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

design considerations for interfacing to SRAM, EPROM and peripherals

The ′C16 differs somewhat from the other members of the ′C1x family of digital signal processors (DSPs).

Additional control signals are available for easier interface to external memory or peripherals, and the memory

write cycle timings have been changed.

The discussion here will center around changes in t and its impact upon SRAM, EPROM and

v

peripherals/latches interfaces.

Access time requirements for interface may be defined relative to :

1. Valid address (t );

a

2. MEN/IOEN, [(t

];

a(MEN)

Figure 11 and the following examples summarize these timings at 35 MHz CLKIN.

t

c(C)

t

w(CH)

t

f(C)

CLKOUT

MEN

t (CLKOUT)

a

t

d2

d1

t

a(MEN)

t

a

A15-A0

D15-D0

t

su(D)

Figure 11.

where:

t

: (access time from address valid) = t

– t – t

= 44.3 ns

su(D)

a

c(C)

d1

: (access time from MEN valid) = t

– t – t

+ t = 35.73 ns

a(MEN)

c(C)

d2

su(D) d3

and where (for 35 MHz CLKIN):

t

= 114.3 ns

= 35 ns

= [1/4 × (114.3) + 12] ns

c(C)

d1

d2

= 35 ns

su(D)

= 47 ns nominal

= 8 ns nominal

w(CH)

f(C)

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90

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

In addition to the above timings, t must be taken into account. t is the time that the data bus is

v

guaranteed to be held after the rising edge of MWE or IOWE. In other ′C1x devices, the value of t was

v

referenced to CLKOUT↓ and not WE↑ (see Figure 12). For the ′C16, t is a minimum of 5 ns. This implies

v

that MWE and IOWE must be tied directly to the external device. If required, decode logic must be added

to an input other than the read/write input — for example, the chip select on SRAMs. If the external device

does not have two inputs, then transparent latches must be added to extend the time data is held on the

data bus. These latches must be off the bus prior to the next instruction (see Figure 12).

CLKOUT

MWE or IOWE

t

v

t

d10

D15-D0

Figure 12.

where:

t = 5 ns (min)

v

d10

t

= 15 ns (max)

There is a potential for bus conflict on the prefetch and execution of a TBLW or an OUT instruction. Figure 13

details the timings to be considered. In addition to the timings for the ′C16, timing definitions for interface are

also included.

Dummy Prefetch Cycle

CLKOUT

TBLW or OUT Execution

t

ddeco

MEN

t

dmemh

CE

D15-D0

Memory Driven Data

t

d9(MEN)

t

conf

D15-D0

DSP Driven Data

Figure 13.

where:

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TMS320C16

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

t

(data bus conflict time) = t

+ t

– t

dmemh d9(MEN)

conf

ddeco

with:

t

: decode delay time to make the CE or OE signal

: memory data hold time from CE or OE

: delay time, MEN to data bus starts being driven

ddeco

dmemh

d9

: (at 35 MHz CLKIN) = [1/4t

] = [1/4(114.3)] = 28.58 ns

d9

c(C)

If t

is less than or equal to zero, data bus conflict does not occur.

is greater than zero, data conflict occurs.

conf

Note that the following discussion is for CLKIN of 35 MHz.

static memory with output enable and write enable/chip select

The following SRAMs are able to interface directly to the ′C16, needing only to directly connect the ′C16 memory

control signals MEN and MWE to the memory. Device select decode is accomplished with address decode and

then input to the device chip select.

PRODUCT

t

dconf

ddeco

dmemh

UNITS

TC55645-35

TC55328-35

TMS6789-35

TC5588-35

0

15

8

10

–13.58

–20.58

–18.58

ns

TMS6716-35

MWE

MEN

WE

OE

SRAM With OE

CS

TMS320C16

ALS138

(Decoder)

A15-AXX

ADDR

DATA

D15-D0

Figure 14.

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92

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

static memory with chip enable and write enable

Without a separate output enable, a faster SRAM is required. Logic is added to decode address and memory

control to perform a read/write cycle. The MWE signal is directly connected to the WE input of the SRAM to meet

the t specification (see Figure 15).

v

Product

t

dconf

ddeco

7.5

dmemh

Units

ns

CY7C164-25

10

– 11.08

Programmable

Logic

MWE

WE

CE

7.5 ns

MEN

TMS320C16

SRAM With CE

ADDR

A15-AXX

DATA

D15-D0

Figure 15.

EPROM interface

The following high-speed EPROMs can be used directly:

Product

t

dconf

ddeco

dmemh

Units

CY7C291-35

TMS27C291-35

0

25

– 3.58

ns

MEN

CS1

CS2

V

CC

Fast EPROM

TMS27C291-35

TMS320C16

CS3

ADDR

Decoder

7.5 ns

A15-AXX

DATA

D15-D0

Figure 16.

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93

TMS320C16

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

interfacing latches to the TMS320C16

As with the previous devices, the memory control signal must be directly connected to the latch and the latch

needs to have a separate chip select. There are several devices with this feature, including the SN74ALS996.

The SN74ALS996 is an 8-bit D-type edge-triggered read-back latch with three-state outputs, connected to the

′C16 as illustrated in Figure 17.

D15-D0

IOWE

IOEN

CLK

RD

TMS320C16

ALS996A x 2

ALS 138

Decoder

A2

A1

A0

EN

Figure 17.

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94

TMS320C17, TMS320E17, TMS320LC17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Key Features: TMS320C17/E17/LC17/P17

Dua-Channel

Serial Port

• 200-ns Instruction Cycle Timing

Interrupt

(TMS320C17/E17/P17)

Data (16)

Coprocessor

Interface

• 278-ns Instruction Cycle Timing

′320C17

(TMS320LC17)

Serial Interface

or

′320E17

µ-Law/A-Law

Hardware

• 256 Words of On-Chip Data RAM

• 4K Words of On-Chip Program ROM

Address (3)

(TMS320C17/LC17)

Timer

• 4K Words of On-Chip Program EPROM

(TMS320E17/P17)

• One-Time Programmable (OTP) Windowless

• Device Packaging:

EPROM Version Available (TMS320P17)

— 40-Pin DIP (All Devices)

— 44-Lead PLCC (TMS320C17/LC17/P17

— 44-Lead CER-QUAD (TMS320E17)

• EPROM Code Protection for Copyright Security

• Dual-Channel Serial Port for Full-Duplex Serial

• 3.3 -V Low-Power Version Available

Communication

(TMS320LC17)

• Serial Port Timer for Standalone Serial

• Operating Free-Air Temperature Range

. . . 0°C to 70°C

Communication

• On-Chip Companding Hardware for µ-law/A-law

• 16-Bit Coprocessor Interface for Common

PCM Conversions

4/8/16/32-Bit Microcomputers/Microprocessors

TMS320C17/E17/LC17/P17

N/JD Package

TMS320C17, TMS320E17

FN/FZ Packages

(Top View)

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

PA1/RBLE

PA0/HI/LO

MC

PA2/TBLF

FSR

FSX

FR

DX1

DX0

SCLK

DRI

DEN/RD

WE/RD

2

3

4

6 5 4 3 2 1 44 43 42 41 40

RS

5

EXINT

CLKOUT

X1

X2/CLKIN

BIO

7

39

38

37

36

35

34

33

32

31

30

29

CLKOUT

X1

X2/CLKIN

BIO

DX0

SCLK

DR1

DEN/RD

WE/WR

6

8

7

9

8

10

11

12

13

14

15

16

17

9

NC

10

11

12

13

14

15

16

V

SS

V

SS

CC

D8/LD8

D9/LD9

V

CC

D8

D9

D10

D11

D12

DR0

XF

MC/PM

D0/LD0

DR0

XF

D10/LD10

D11/LD11

D12/LD12

D13/LD13

D14/LD14

D15/LD15

D7/LD7

MC/PM

D0/LD0

D1/LD1

D2/LD2

D3/LD3

D4/LD4

D5/LD5

V

SS

18 19 20 21 22 23 24 25 26 27 28

17 24

18 23

19 22

20 21

D6/LD6

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architecture

The ′C17/E17/LC17/P17 consists of five major functional units: the ′C15 microcomputer, a system control

register, a full-duplex dual-channel serial port, companding hardware, and a coprocessor port.

Three of the I/O ports are used by the serial port, companding hardware, and the coprocessor port. Their

operation is determined by the 32 bits of the system control register (see Table 6 for the control register bit

definitions). Port0accessescontrolregister0andconsistsofthelower16registerbits(CR15-CR0), andisused

to control the interrupts, serial port connections, and companding hardware operation. Port 1 accesses control

register 1, consisting of the upper 16 control bits (CR31-CR16), as well as both serial port channels, the

companding hardware, and the coprocessor port channels. Communication with the control register is via IN

and OUT instructions to ports 0 and 1.

Interrupts fully support the serial port interface. Four maskable interrupts (EXINT, FR, FSX, and FSR) are

mapped into I/O port 0 via control register 0. When disabled, these interrupts may be used as single-bit logic

inputs polled by software.

serial port

The dual-channel serial port is capable of full-duplex serial communication and offers direct interface to two

combo-codecs. Two receive and two transmit registers are mapped into I/O port 1, and operate with 8-bit data

samples. Internal and external framing signals for serial port transfers (MSB first) are selected via the system

control register. The serial port clock, SCLK, provides the bit timing for transfers with the serial port, and may

be either an input or output. As an input, an external clock provides the timing for data transfers and framing

pulse synchronization. As an output, SCLK provides the timing for standalone serial communication and is

derived from the ′C17/E17/P17 system clock, X2/CLKIN, and system control register bits CR27-CR24

(see Table 7 for the available divide ratios). The internal framing (FR) pulse frequency is derived from the serial

port clock (SCLK) and system control register bits CR23-CR16. This framing pulse signal provides framing

pulses for combo-codecs, for a sample clock for voice-band systems, or for a timer used in control applications.

µ-law/A-law companding hardware

The ′C17/E17/LC17/P17 features hardware companding logic and can operate in either µ-law or A-law format

with either sign-magnitude or twos-complement numbers. Data may be companded in either a serial mode for

operation on serial port data or a parallel mode for computation inside the device. The companding logic

operation is selected through CR14. No bias is required when operating in twos-complement. A bias of 33 is

required for sign-magnitude in µ-law companding. Upon reset, the device is programmed to operate in

sign-magnitude mode. This mode can be changed by modifying control bit 29 (CR29) in control register 1. For

further information on companding, see the TCM29C13/TCM29C14/TCM29C16/TCM29C17 Combined

Single-Chip PCM Codec and Filter Data Sheet, and the application report, “Companding Routines for the

TMS32010/TMS32020,” in the book Digital Signal Processing Applications with the TMS320 Family

(SPRA012A), both documents published by Texas Instruments.

In the serial mode, sign-magnitude linear PCM (13 magnitude bits plus 1 sign bit for µ-law format or 12

magnitude bits plus 1 sign bit for A-law format) is compressed to 8-bit sign-magnitude logarithmic PCM by the

encoder and sent to the transmit register for transmission on an active framing pulse. The decoder converts 8-bit

sign-magnitude log PCM from the serial port receive registers to sign-magnitude linear PCM.

In the parallel mode, the serial port registers are disabled to allow parallel data from internal memory to be

encoded or decoded for computation inside the device. In the parallel encode mode, the encoder is enabled

and a 14-bit sign-magnitude value written to port 1. The encoded value is returned with an IN instruction from

port 1. In the parallel decode mode, the decoder is enabled and an 8-bit sign-magnitude log PCM value is written

to port 1. On the successive IN instruction from port 1, the decoded value is returned. At least one instruction

should be inserted between an OUT and the successive IN when companding is performed with

twos-complement values.

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Table 6. Control Register Configuration

FR

Pulse

Widt

h

Port 1 Port 0

Frame Counter Modulus

Interrupt Mask Bits

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

I/O

Control

Serial Clock

Prescale Control

Serial-Port Configuration

Companding Hardware Control

Interrupt Flags

Reserved

BIT

0

DESCRIPTION AND CONFIGURATION

†

EXINT Interrupt flag

†

FSR interrupt flag

1

†

FSX interrupt flag

2

†

FR interrupt flag

3

4

EXINT interrupt enable mask. When set to logic 1, an interrupt on EXINT activates device interrupt circuitry.

FSR interrupt enable mask. Same as EXINT control.

5

6

FSX interrupt enable mask. Same as EXINT control.

7

FR interrupt enable mask. Same as EXINT control.

0 = port 1 connects to either serial-port registers or companding hardware.

1 = port 1 accesses CR31-CR16.

8

Port 1 configuration control:

0 = serial-port data transfers controlled by active FR.

9

External framing enable:

XF external logic output flag latch

0 = Parallel companding mode; serial port disabled.

1 = serial-port data transfers controlled by active FSX/FSR.

10

11

Serial-port enable:

1 = serial companding mode; serial port registers enabled.

0 = disabled.

12

13

14

15

µ-law/A-law encoder enable:

1 = data written to port 1 is µ-law or A-law encoded.

0 = disabled.

1 = data written to port 1 is µ-law or A-law decoded.

µ-law/A-law decoder enable:

0 = companding hardware performs µ-law conversion.

1 = companding hardware performs A-law conversion.

µ-law/A-law decoder encode/decoded select:

0 = SCLK is an output, derived from the prescaler in timing logic.

1 = SCLK is an input that provides the clock for serial port and frame counter in timing logic.

Serial clock control:

‡

23-16

27-24

Frame counter modulus. Controls FR frequency = SCLK/(CNT + 2) where CNT is binary value fo CR23-CR16

SCLK prescale cotnrol bits. (See Table 7 for divide ratios.)

0 = fixed-data rate; FR is 1 SCLK cycle wide.

1 = variable-data rate; FR is 8 SCLK cycles wide.

FR pulse-width control:

28

29

0 = sign-magnitude companding

1 = twos-complement companding

Two’s-complement µ-law/A-law conversion enable:

0 = 8-bit byte length

1 = 16-bit word length

30

31

8/16-bit length coprocessor mode select:

Reserved for future expansion: Should be set to zero.

†

‡

Interrupt flag is cleared by writing a logic 1 to the bit with an OUT instruction to port 0.

All ones in CR23-CR16 indicate a degenerative state and should be avoided. Bits are operational whether SCLK is an input or an output.

CNT must be greater than 7.

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Table 7. Serial Clock (SCLK) Divide Ratios (X2/CLKIN = 20.48 MHz)

CR27

CR26

CR25

CR24

DIVIDE RATIO

SCLK FREQUENCY

UNIT

MHz

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

32

28

24

20

16

14

12

10

0.640

0.731

0.853

1.024

1.280

1.463

1.706

2.048

The specification for µ-law and A-law log PCM coding is part of the CCITT G.711 recommendation. The

followingdiagramshowsa′C17/E17/P17interfacetotwocodecsasusedforµ-laworA-lawcompandingformat.

TMS320C17/E17/P17

TCM29C13

Analog Out

Analog In

DX0

DR0

SCLK

FR

PCM In

PCM Out

CLKR/X

FSX

V

SS

CC

+5 V

FSR

MC

MC/PM

TCM29C13

PCM In

X2

X1

Analog Out

Analog In

DX1

DR1

PCM Out

CLKR/X

FSX

FSR

coprocessor port

The coprocessor port, accessed through I/O port 5 using IN and OUT instructions, provides a direct connection

to most 4/8-bit microcomputers and 16/32-bit micorprocessors. The coprocessor interface allows the

′C17/E17/P17 to act as a peripheral (slave) microcomputer to a microprocessor, or a master to a peripheral

microcomputer such as TMS7042. The coprocessor port is enabled by setting MC/PM and MC low. The

microcomputer mode is enabled by setting these two pins high. (Note that MC/PM ≠ MC is undefined.)

In the microcomputer mode, the 16 data lines are used for the 6 parallel 16-bit I/O ports.

Inthecoprocessormode, the16-bitcoprocessorportisreconfiguredtooperateasa16-bitlatchedbusinterface.

Control bit 30 (CR30) in control register 1 is used to configure the coprocessor port to either an 8-bit or a 16-bit

length. When CR30 is high, the coprocessor port is 16 bits wide thereby making all 16 bits of the data port

available for 16-bit transfers to 16 and 32-bit microprocessors. When CR30 is low, the port is 8-bits wide and

mappedtothelowbyteofthedataportforinterfacingto8-bitmicrocomputers. Whenoperatinginthe8-bitmode,

both halves of the 16-bit latch can be addressed using the HI/LO pin, thus allowing 16-bit transfers over 8 data

lines. When not in the coprocessor mode, port 5 can be used as a generic I/O port.

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coprocessor port (continued)

The external processor recognizes the coprocessor interface in which both processors run asynchronously as

a memory-mapped I/O operation. The external processor lowers the WR line and places data on the bus. It next

raises the WR line to clock the data into the on-chip latch. The rising edge of WR automatically creates an

interrupt to the ′C17/E17/P17, and the falling edge of WR clears the RBLE (receive buffer latch empty) flag.

When the ′C17/E17/P17 reads the coprocessor port, it causes the RBLE signal to transition to a logic low state

that clears the data in the latch, and allows the interrupt condition to be cleared internally. Likewise, the external

processorreadsformthelatchbydrivingtheRDlineactivelow, thusenablingtheoutputlatchtodrivethelatched

data. When the data has been read, the external device will again bring the RD line high. This activates the BIO

line to signal that the transfer is complete and the latch is available for the next transfer. The falling edge of RD

resets the TBLF (transmit buffer latch full) flag. Note that the EXINT and BIO lines are reserved for coprocessor

interface and cannot be driven externally when in the coprocessor mode.

An example of the use of a coprocessor interface is shown in Figure 18, in which the ′C17/E17/P17 are DSPs

interfaced to the TMS70C42, an 8-bit microcontroller.

TMS320C17/E17/P17

TMS70C42

3

MC

27

2

MC/PM

HI/LO

6

17

CLKOUT

XTAL2

31

1

7

6

WR

A1

A0

RBLE

32

40

9

8

RD

A3

A2

TBLF

19

20

21

22

23

24

25

26

19

20

21

22

23

24

26

27

LD7

LD6

LD5

LD4

LD3

LD2

LD1

LD0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 18. Coprocessor Interface

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†

TERMINAL FUNCTIONS

‡

I/O

NAME

DEFINITION

BIO

I

External polling input

CLKOUT

O

System clock output, 1/4 crystal/CLKIN frequency

16-bit parallel data bus/data lines for coprocessor latch

Data enable for device input data/external read for output latch

Serial-port receive-channel inputs

D15/LD15-D0/LD0

DEN/RD

DR1, DR0

DX1, DX0

EXINT

I/O

I

O

I

Serial-port transmit-channel outputs

External interrupt input

FR

O

I

Internal serial-port framing output

FSR

External serial-port receive framing input

External serial-port transmit framing input

Microcomputer select (must be same state as MC/PM)

Microcomputer/peripheral coprocessor select (must be same state as MC)

I/O port address output/latch byte select pin

I/O port address output/receive buffer latch empty flag

I/O port address output/transmit buffer latch full flag

Reset for initializing the device

FSX

I

MC

I

MC/PM

PA0/HI/LO

PA1/RBLE

PA2/TBLF

RS

I

I/O

O

I

SCLK

I/O

I

Serial-port clock

V

+ 5 V Supply

CC

I

Ground

SS

WE/WR

X1

O

I

Write enable for device output data/external write for input latch

Crystal output for internal oscillator

X2/CLKIN

XF

Crystal input for internal oscillator or external oscillator system clock input

External-flag output pin

O

†

‡

See EPROM programming section.

Input/Output/High-impedance state.

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functional block diagram

FSR

INT/EXINT

FSX

FR

CLKOUT

X2/CLKIN

X1

Program Bus

Interrupt Latch and

Multiplexer

16

12 LSB

MC

MC/PM

WR/WE

RD/DEN

BIO

MUX

12

Serial-port Timing and

Framing Control

RS

PC (12)

12

HI/LO

RBLE

TBLF

Instruction

16

SCLK

3

12

Program

ROM/EPROM

(4K Words)

D15-D0

PA2–PA0

Data Latch

Stack

4 × 12

Program Bus

16

MUX

Data Bus

16

7

16

System Control

AR0 (16)

AR1 (16)

ARP

DP

T(16)

16

Shifter (0–16)

Register

16

Multiplier

XF

8

µ-Law/A-Law

16

Encoder

P(32)

32

8

MUX

8

14

32

8

MUX

µ-Law/A-Law

Address

Decoder

MUX

32

8

Data RAM

(256 Words)

8

MUX

8

ALU (32)

8

Data

32

TR0/TS0

TR1/TS1

DX0

DX1

Legend:

ACC

PC

=

Accumulator

Program Counter

Auxiliary Register Pointer

P Register

Auxiliary Register 0

T Register

Auxiliary Register 1

Transmit Register

Data Page Pointer

Receive Register

ACC (32)

RR0/RS0

RR1/RS1

DR0

DR1

ARP

P

AR0

T

AR1

TR

DP

32

Shifter (0,1, 4)

16

RR

16

Data Bus

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electrical specifications

This section contains the electrical specifications for all versions of the ′C17/E17/P17 digital signal processors,

including test parameter measurement information. Parameters with

in the EPROM programming mode (see Note 11).

subscripts apply only to the ′E17/P17

PP

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V , except for the ′320LC17 (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

CC

PP

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 14 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 W

Operating free-air temperature: L suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C

°

Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

SS.

recommended operating conditions

MIN

NOM

MAX

UNIT

EPROM devices

All other devices

4.75

4.5

5

5.25

5.5

V

CC

Supply voltage

V

Supply voltage (see Note 11)

Supply voltage

12.25

12.5

0

12.75

V

PP

V

SS

All inputs except CLKIN

CLKIN

2

3

V

High-level input voltage

Low-level input voltage

IH

V

All inputs except MC/MP

MC/MP

0.8

0.6

V

IL

V

I

High-level output current, all outputs

Low-level output current (All outputs)

–300

2

µA

mA

OH

OL

L suffix

A suffix

0

70

85

°C

T

A

Operating free-air temperature

– 40

NOTE 11:

V

PP

is I

can be applied only to programming pins designed to accept V as an input. During programming the total supply current

PP

PP CC

+ I

.

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electrical characteristics over specified temperature range (unless otherwise noted)

†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

65

UNIT

TMS320C17

f = 20.5 MHz, V

f = 25.6 MHz, V

= 5.5 V, T = 0°C to 70°C

50

55

CC

A

‡

I

Supply current

mA

CC

TMS320E17/P1

7

= 5.5 V, T = – 40°C to 85°C

75

A

†

‡

All typical values are at T = 70°C and are used for thermal resistance calculations.

A

I

characteristics are inversely proportional to temperature. For I dependance on temperature, frequency, and loading, see Figure 3.

CC

CLOCK CHARACTERISTICS AND TIMING

The ′C17/E17/P17 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN (see Figure 1). The frequency

of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and

parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and should be

specified at a load capacitance of 20 pF.

PARAMETER

Crystal frequency, f

TEST CONDITIONS

= 0°C to 70°C

MIN NOM

MAX

20.5

UNIT

x

MHz

TMS320C17

T

A

6.7

TMS320E17/P1

7

T = – 40°C to 85°C

A

C1, C2

T

A

= 0°C to 70°C

10

pF

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

PARAMETER

CLKOUT cycle time

CLKOUT rise time

CLKOUT fall time

TEST CONDITIONS

MIN

NOM

MAX

UNIT

ns

§

t

195.12

200

c(C)

¶

10

ns

r(C)

R

C

= 825 Ω,

= 100 pF

L

8

ns

f(C)

(see Figure 2)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Delay time, CLKIN↑ to CLKOUT↓

92

90

ns

w(CL)

w(CH)

d(MCC)

ns

¶

25

¶

60

ns

§ t

c(C)

is the cycle time of CLKOUT, i.e., 4t

c(MC)

(4 times CLKIN cycle time if an external oscillator is used).

Values derived from characterization data and not tested.

¶

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timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Master clock cycle time

48.78

50

150

ns

c(MC)

†

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low

Pulse duration, master clock high

5

10

ns

r(MC)

†

f(MC)

†

0.45t

c(MC)

0.6t

c(MC)

w(MCP)

w(MCL)

w(MCH)

†

20

†

Values derived from characterization data and not tested.

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

†

t

Delay time, CLKOUT↓ to address bus valid

10

50

ns

d1

d4

d5

d6

d7

d8

d9

d10

v

†

Delay time, CLKOUT↓ to DEN↓

1/4t

– 5

1/4t + 15

c(C)

†

Delay time, CLKOUT↓ to DEN↑

–10

1/2t

15

+ 15

Delay time, CLKOUT↓ to WE↓

– 5

1/2t

1/4t

c(C)

15

+ 65

†

–10

Delay time, CLKOUT↓ to WE↑

R

= 825 Ω

= 100 pF,

L

Delay time, CLKOUT↓ to data bus OUT valid

Time after CLKOUT↓ that data bus starts to be driven

Time after CLKOUT↓ that data bus stops bieng driven

Data bus OUT valid after CLKOUT↓

c(C)

C

L

(see Figure 2)

†

– 5

1/4t

c(C)

†

+70

c(C)

1/4t

–10

–45

c(C)

Address hold time after WE↑, or DEN↑

(see Note 14)

†

t

0

2

ns

h(A-WMD)

su(A-MD)

Address bus setup time prior to DEN↓

1/4t

c(C)

†

Values derived from characterization data and not tested.

NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

NOM

MAX

UNIT

t

Setup time, data bus valid prior to CLKOUT↓

50

ns

su(D)

R

C

= 825 Ω,

= 100 pF

L

Hold time, data bus held valid after CLKOUT↓

(see Note 16)

0

ns

(see Figure 2)

h(D)

NOTE 16: Data may be removed from the data bus upon DEN↑ preceding CLKOUT↓.

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RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

1/2t

MAX

UNIT

ns

t

Delay time, DEN↑, and WE↑ from RS

Data bus disable time after RS

+50†

d11

c(C)

R

825 Ω,

= 100 pF,

†

+50

L

1/4t

ns

dis(R)

C

L

†

t

Delay time from RS↓ to high-impedance SCLK

Delay time from RS↓ to high-impedance DX1, DX0

200

ns

(see Figure 2)

d12

d13

t

200

ns

†

Values derived form characterization data and not tested.

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Reset (RS) setup time prior to CLKOUT (see Note 10)

RS pulse duration

50

ns

su(R)

5t

c(C)

ns

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (EXINT) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Fall time, EXINT

15

ns

f(INT)

Pulse duration, EXINT

t

ns

w(INT)

su(INT)

c(C)

Setup time, EXINT↓ before CLKOUT↓

50

IO (BIO) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Fall time, BIO

15

ns

f(IO)

Pulse duration, BIO

t

ns

w(IO)

su(IO)

c(C)

Setup time, BIO↓ before CLKOUT↓

50

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

825 Ω, C = 100 pF,

(see Figure 2)

L

†

5

t

Delay time CLOCKOUT↑ to valid XF

115

ns

d(XF)

†

Values derived form characterization data and not tested.

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105

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

SERIAL PORT TIMING

switching characteristics over recommended operating conditions

PARAMETER

MIN

NOM

MAX

UNIT

ns

t

Internal framing (FR) delay from SCLK rising edge

DX bit 1 valid before SCLK falling edge

DX bit 2 valid before SCLK falling edge

DX hold time after SCLK falling edge

70

d(CH-FR)

d(DX1-XL)

d(DX2-XL)

h(DX)

20

ns

t

/2

ns

c(SCLK)

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

t

Serial port clock (SCLK) cycle time (see Note 17)

Serial port clock (SCLK) fall time

390

4770

ns

c(SCLK)

f(SCLK)

r(SCLK)

w(SCLKL)

w(SCLKH)

su(FS)

†

30

ns

†

Serial port clock (SCLK) rise time

Serial port clock (SCLK) low-pulse duration (see Note 17)

Serial port clock (SCLK) high-pulse duration (see Note 17)

FSX/FSR setup time before SCLK falling edge

DR setup time before SCLK falling edge

185

100

20

2500

su(DR)

DR hold time after SCLK falling edge

20

h(DR)

†

Values derived from characterization data and not tested.

NOTES: 17. Minimum cycle time is 2t where t is CLKOUT cycle time.

c(C)

18. The duty cycle of the serial port clock must be within 45 to 55 percent.

COPROCESSOR INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

MIN

NOM

MAX

75

UNIT

ns

t

RD low to TBLF high

WR low to RBLE high

RD low to data valid

d(R-A)

d(W-A)

a(RD)

h(RD)

75

ns

80

ns

Data hold time after RD high

25

ns

timing requirements over recommended operating conditions

MIN

25

40

30

25

80

60

NOM

MAX

UNIT

ns

t

HI/LO hold time after WR or RD high

HI/LO setup time after WR or RD low

Data setup time prior to WR high

Data hold time after WR high

RD low-pulse duration

h(HL)

ns

su(HL)

su(WR)

h(WR)

w(RDL)

w(WRL)

ns

WR low-pulse duration

ns

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106

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

TIMING DIAGRAMS

Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2 volts, unless

otherwise noted.

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

CLKOUT

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

t

r(C)

f(C)

t

w(CL)

t

c(C)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

†

t

and t

w(MCP)

d(MCC)

memory read timing

t

c(C)

CKKOUT

t

d2

t

d3

MEN

t

su(A-MD)

t

h(A–WMD)

t

d1

A11-A0

Address Bus Valid

t

su(D)

t

h(D)

Instruction Input Valid

D15-D0

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107

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

IN instruction timing

CLKOUT

MEN

1

2

5

t

su(A-MD)

4

t

su(D)

t

A11-A0

3

t

d5

d4

DEN

t

h(D)

D15-D0

6

7

8

Legend:

1. IN Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Input Valid

7. Data Input Valid

8. Instruction Valid

4. Peripheral Address Valid

OUT instruction timing

CLKOUT

MEN

A11-A0

WE

1

3

2

5

4

t

d6

d7

t

d9

t

d10

t

d8

t

v

7

6

8

D15-D0

Legend:

1. OUT Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Input Valid

7. Data Output Valid

8. Instruction Valid

4. Peripheral Address Valid

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108

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

reset timing

CLKOUT

RS

t

su(R)

t

su(R)

t

w(R)

DEN

WE

t

d11

t

dis(R)

Data

Out

D15-D0

t

d12

SCLK

d13

DX1, DX0

PA = Port Address PC3 = 3 LSB of PC

Valid Valid

PC = 0

PC = 1

PA = PC3 = 0

PA = PC3 + 1 = 1

PA2-PA0

interrupt timing

CLKOUT

t

su(INT)

INT

t

f(INT)

t

w(INT)

BIO timing

CLKOUT

t

su(IO)

BIO

t

f(IO)

t

w(IO)

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109

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

XF timing

CLKOUT

PA2-PA0

1

t

d7

t

d6

WE

t

d9

2

t

d10

t

v

t

d8

D15-D0

XF

3

4

t

d(XF)

XF Valid

Legend:

1. Port Address Valid

2. Out Opcode Valid

3. Port Data Valid

4. Next Instruction Opcode Valid

external framing: transmit timing

t

r(SCLK)

t

w(SCLKH)

SCLK

1

2

3

8

t

su(FS)

t

w(SCLKL)

t

su(FS)

t

f(SCLK)

FSX

t

h(DX)

t

d(DX1-CL)

d(DX2-CL)

1

2

DX1, DX0

3

8

NOTES: A. Data valid on transmit output until SCLK rises.

B. The most significant bit is shifted first.

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110

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

external framing: receive timing

SCLK

1

2

3

8

t

su(FS)

t

su(FS)

FSR

t

su(DR)

t

h(DR)

DR1, DR0

1

2

3

8

NOTE: The most significant bit is shifted first.

internal framing: variable-data rate

SCLK

t

d(CH-FR)

FR

t

d(DX2-CL)

t

d(DX1-CL)

1

2

3

8

DX1, DX0

t

su(DR)

t

h(DR)

1

2

3

8

DR1, DR0

NOTE: The most significant bit is shifted first.

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111

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

internal framing: fixed-data rate

K

t

d(CH-FR)

t

d(CH-FR)

R

0

t

d(DX2-CL)

1

2

3

8

t

d(DX1-CL)

t

h(DR)

1

2

3

8

0

t

su(DR)

NOTE: The most significant bit is shifted first.

coprocessor timing: external write to coprocessor port

HI/LO

t

w(WRL)

t

w(WRL)

t

h(HL)

t

su(HL)

t

h(HL)

su(HL)

WR

DATA IN

RBLE

t

h(WR)

t

su(WR)

Valid

su(WR)

Valid

t

)

d(W-A

Only necessary for operation of 8-bit mode

constructing 16-bit data

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112

TMS320C17, TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

coprocessor timing: external read to coprocessor port

HI/LO

t

w(RDL)

su(HL)

t

w(RDL)

su(HL)

t

h(HL)

t

h(HL)

t

RD

t

h(RD)

t

a(RD)

DATA

OUT

Valid

t

d(R-A)

TBLF

Only necessary for operation of 8-bit mode

constructing 16-bit data

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113

TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

EPROM PROGRAMMING

absolute maximum ratings over specified temperature range (unless otherwise noted)

†

Supply voltage range, V (see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 14 V

PP

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to GND.

recommended operating conditions

MIN

NOM

MAX

UNIT

V

PP

Supply voltage (see Note 11)

12.5

12.75

V

NOTE 11: V

can be applied only to programming pins designed to accept V as an input. During programming the total supply current

PP

PP CC

PP

is I

+ I

.

electrical characteristics over specified temperature range (unless otherwise noted)

†

PARAMETER

supply current

TEST CONDITIONS

MIN

TYP

MAX

100

50

UNIT

µA

I

V

= V

= 5.5 V

PP1

PP

CC

= 12.75 V, V

supply current (during program pulse)

= 5.5 V

30

mA

PP2

PP

CC

recommended timing requirements for programming, T = 25°C, V

= 6 V, V

= 12.5 V,

A

CC

PP

(see Note 13)

MIN

0.95

3.8

2

NOM

MAX

UNIT

ms

µs

t

Initial program pulse duration

Final pulse duration

1

1.05

63

w(IPGM)

w(FPGM)

su(A)

Address setup time

E setup time

2

µs

su(E)

G setup time

2

µs

su(G)

‡

Output disable time from G (see Note 15)

Output enable time from G

Data setup time

0

130

ns

dis(G)

en(G)

150

ns

2

0

2

µs

su(D)

V

setup time

µs

su(VPP)

su(VCC)

h(A)

PP

µs

CC

Address hold time

Data hold time

µs

h(D)

†

Values derived from characterization data and not tested.

NOTES: 13. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and V

programming.

= 12.5 V ± 0.25 V during

PP

15. Common test conditions apply for t

except during programming.

dis(G)

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

114

TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

PROGRAMMING THE TMS320E17/P17 EPROM CELL

Each ′E17/P17 devices include a 4K × 16-bit industry-standard EPROM cell for prototyping, early field testing,

and low-volume production. In conjunction with this EPROM, the TMS320C17 with a 4K-word masked ROM,

then, provides more migration paths for cost-effective production.

Note: The TMS320P17 is a one-time programmable (OTP) EPROM device.

EPROM adapter sockets are available that provide pin-to-pin conversions for programming any ′E17/P17

devices. One adapter socket (part number RTC/PGM320C-06), shown in Figure 19, converts a 40-pin DIP into

an equivalent 28-pin device. Another socket (part number RTC/PGM320C-06), not shown, permits 44- to 28-pin

conversion.

Figure 19. EPROM Adapter Socket (40-Pin to 28-Pin DIP Conversion)

Key features of the EPROM cell include the normal programming operation as well as verification. The EPROM

cell also includes a code protection feature that allows code to be protected against copyright violations.

The ′E17/P17 EPROM cell is programmed using the same family and device pinout codes as the TMS27C64

8K × 8-bit EPROM. The TMS27C64 EPROM series are unltraviolet-light erasable, electrically programmable,

read-only memories, fabricated using HVCMOS technology. They are pin-compatible with existing 28-pin

ROMs and EPROMs. These EPROMs operate from a single 5-V supply in the read mode; however, a 12.5-V

supplyisneededforprogramming. AllprogrammingsignalsareTTLlevel. Forprogrammingoutsidethesystem,

existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.

Figure 20 shows the wiring conversion to program the ′E17/P17 using the 28-pin pinout of the TMS27C64.

Table 8 on pin nomenclature provides a description of the TMS27C64 pins. The code to be programmed into

the device should be in serial mode. The ′E17/P17 devices use 13 address lines to address 4K-word memory

in byte format.

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115

TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

A1

1

2

3

4

A2

A3

A4 38

A5 37

40

39

A0(LSB)

VPP

RS

28

27

26

25

24

23 A11

22 G

21 A10

20 E

19

18

17

16

15

V

5

6

7

8

V

1

2

3

4

5

6

7

8

9

EPT

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

A6

A7

A8

CC

PP

PGM

EPT

A8

A12

A7

A6

A5

A4

A3

A2

A1

A0 10

Q1 11

Q2 12

Q3 13

GND 14

CLKIN

3.9 kΩ

A9

9

10

11

12

13

14

15

16

17

18

19

20

GND

Q1(LSB)

Q2

Q3

Q4

Q5

Q6

Q7

Q8(MSB)

V

CC

A9

A10

A11

Q8

Q7

Q6

Q5

Q4

(MSB)A12

E

G

PGM

TMS27C64

PINOUT

TMS27C64

PINOUT

TMS320E17/P17

CAUTION

Although acceptable by some EPROM programmers, the signature mode cannot be used on any

TMS320E1x device. The signature mode will input a high-level voltage (12.5 V ) onto pin A9. Since this

dc

pin is not designed for high voltage, the cell will be damaged. To prevent an accidental application of

voltage, Texas Instruments has inserted a 3.9 kΩ resistor between pin A9 of the TI programmer socket

and the programmer itself.

Pin Nomenclature (TMS320E17/P17)

NAME

A0-A12

I/O

DEFINITION

I

On-chip EPROM programming address lines

Clock oscillator input

CLKIN

E

I

EPROM chip select

EPT

G

GND

PGM

Q1-Q8

RS

I

EPROM test mode select

EPROM read/verify select

Ground

EPROM write/program select

Data lines for byte-wide programming of on-chip 8K bytes of EPROM

Reset for initializing the device

5-V power supply

I/O

I

V

CC

V

PP

12.5-V power supply

Figure 20. TMS320E17/P17 EPROM Programming Conversion to TMS27C64 EPROM Pinout

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116

TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

Table 8 shows the programming levels required for programming, verifying, reading, and protecting the EPROM cell.

Table 8. TMS320E17/P17 Programming Mode Levels

SIGNAL NAME TMS320E17 PIN TMS27C64 PIN PROGRAM

VERIFY

READ

PROTECT VERIFY EPROM PROTECT

E

G

25

20

V

IH

V

IH

V

IH

IL

PULSE

IL

PULSE

IL

24

22

V

IH

IL

PGM

23

27

PULSE

V

IH

V

IH

V

IH

V

3

1

V

CC

V

CC

V

CC

V

CC

+ 1

V

PP

CC

PP

+ 1

V

CC

30

28

V

CC

V

CC

V

10

14

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN

RS

8

14

SS

PP

SS

PP

4

5

14

EPT

26

Q1-Q8

A0-A3

A4

11-18

2, 1, 40, 39

38

11-13, 15-19

D

Q

OUT

Q8=RBIT

Q8=PULSE

X

IN

OUT

10-7

ADDR

X

6

V

IH

A5

37

5

X

A6

36

4

V

IL

X

A7-A9

A10-A12

35, 34, 29

28-26

3, 25, 24

21, 23, 2

X

Legend:

V

= TTL high level; V = TTL low level; ADDR = byte address bit

IL

PP

IH

= 12.5 V ± 0.25 V; V

= 5 V ± 0.25 V; X = don’t care

CC

PULSE = low-going TTL level pulse; D = byte to be programmed at ADDR

Q

IN

= byte stored at ADDR; RBIT = ROM protect bit.

OUT

programming

Since every memory bit in the cell is a logic 1, the programming operation reprograms certain bits to 0. Once

programmed, these bits can be erased only by using ultraviolet light. The correct byte is placed on the data bus

with V set to the 12.5 V level. The PGM pin is then pulsed low to program in the zeroes.

PP

erasure

Before programming, the device must be erased by exposing it to ultraviolet light. The recommended minimum

2

exposuredose(UV-intensity× exposure-time)is15W•s/cm . Atypical12-mW/cm , filterlessUVlampwillerase

the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After

exposure, all bits are in the high state.

verify/read

To verify correct programming, the EPROM cell can be read using either the verify or read line definitions shown

in Table 8 assuming the inhibit bit has not been programmed.

program inhibit

Programming may be inhibited by maintaining a high level input on the E pin or PGM pin.

read

The EPROM contents may be read independent of the programming cycle, provided the RBIT (ROM protect

bit) has not been programmed. The read is accomplished by setting E to zero and pulsing G low. The contents

of the EPROM location selected by the value on the address inputs appear on Q8-Q1.

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117

TMS320E17, TMS320P17

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

output disable

DuringtheEPROMprogrammingprocess, theEPROMdataoutputsmaybedisabled, ifdesired, byestablishing

the output disable state. This state is selected by setting G and E pins high. While output disable is selected,

Q8-Q1are placed in the high-impedance state.

EPROM protection

To protect the proprietary algorithms existing in the code programmed on-chip, the ability to read or verify code

from external accesses can be completely disabled. Programming the RBIT disables external access of the

EPROM cell, making it impossible to access the code resident in the EPROM cell. The only way to remove this

protectionistoerasetheentireEPROMcell, thusremovingtheproprietaryinformation. Thesignalrequirements

for programming this bit are shown in Table 8. The cell can be determined as protected by verifying the

programming of the RBIT shown in the table.

standard programming procedure

Before programming, the device must first be completely erased. The device can then be programmed with the

correct code. It is advisable to program unused sections with zeroes as a further security measure. After the

programming is complete, the code programmed into the cell should be verified. If the cell passes verification,

the next step is to program the ROM protect bit (RBIT). Once the RBIT programming is verified, an opaque label

should be placed over the window to protect the EPROM cell from inadvertent erasure by ambient light. At this

point, the programming is complete, and the device is ready to be placed into its destination circuit.

program cycle timing

Verify

Program

V

IH

A12-A0

Q8-Q1

Address Stable

HI-Z

Address N+1

IL

t

su(A)

h(A)

/V

IH OH

Data Out

Valid

Data In Stable

/V

IL OL

t

dis(G)

su(D)

V

PP

V

PP

V

CC

su(VPP)

su(VCC)

+1

CC

V

CC

V

t

V

IH

V

IL

V

IH

E

t

su(E)

t

h(D)

PGM

G

t

su(G)

V

IL

t

w(IPGM)

t

en(G)

w(FPGM)

V

IH

IL

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118

TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V

CC

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

to 0.5 V

CC

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mW

Air temperature range above operating devices: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +150°C

†

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and

functionaloperation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section of

this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 6: All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

NOM

3.3

0

MAX

UNIT

V

Supply voltage

3.0

3.6

CC

V

SS

All inputs except CLKIN

CLKIN

2.0

2.5

V

IH

High-level input voltage

V

Low-level input voltage

All inputs

0.55

–300

1.5

V

IL

I

High-level output current (all outputs)

Low-level output current (all outputs)

µA

mA

°C

OH

OL

L version

A version

0

70

T

A

Operating free-air temperature

–40

85

electrical characteristics over specified temperature range (unless otherwise noted)

§

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

I

= MAX

2.0

V

OH

OL

V

High-level output voltage

OH

¶

–0.4

CC

= 20 µA (see Note 19)

V

I

Low-level output voltage

Off-state ouput current

= MAX

0.5

20

OL

V

= V

CC = MAX,

O

CC

SS

µA

OZ

–20

±20

±50

O

V = V

to V , All inputs except CLKIN

CC

I

SS

I

Input current

V = V

to V , CLKIN

CC

I

¶

25

¶

15

¶

25

¶

10

Data bus

All others

Data bus

All others

C

Input capacitance

Output capacitance

i

pF

f = 1 MHz, All other pins 0 V

o

§

¶

All typical values are at V

= 3.3 V, T = 25°C.

A

CC

Values derived from characterization data and not tested.

NOTE 19: This voltage specification is included for interface to HC logic. All other timing parameters defined in this data sheet are specified for

the test load circuit shown in Figure 2.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

119

TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

TMS320LC17

FN PACKAGE

(TOP VIEW)

TMS320LC17

N PACKAGE

(TOP VIEW)

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

1

PA1/RBLE

PA0/HI/LO

MC

PA2/TBLF

FSR

FSX

FR

DX1

DX0

SCLK

DR1

DEN/RD

WE/WR

2

3

4

RS

5

EXINT

CLKOUT

X1

X2/CLKIN

BIO

6

5

4

3

2

1 44 43 42 41 40

6

39

38

37

36

35

34

33

32

31

30

29

7

CLKOUT

X1

X2/CLKIN

BIO

DX0

SLCK

DR1

DEN/RD

WE/WR

7

8

9

10

11

12

13

10

11

12

13

14

15

16

17

V

SS

NC

D8/LD8

D9/LD9

V

CC

V

SS

CC

DR0

XF

DR0

XF

MC/PM

D0/LD0

D8/LD8

D10/LD10

D11/LD11

D12/LD12

D13/LD13

D14/LD14

D15/LD15

D7/LD7

D9/LD9 14

D10/LD10 15

D11/LD11 16

D12/LD12 17

MC/PM

D0/LD0

D1/LD1

D2/LD2

D3/LD3

D4/LD4

D5/LD5

V

SS

18 19 20 21 22 23 24 25 26 27 28

18 23

19 22

20 21

D6/LD6

electrical characteristics over specified ranges (unless otherwise noted)

†

PARAMETER

Supply current

All typical values are at T = 70°C and are used for thermal resistance calculations.

TEST CONDITIONS

MIN

TYP

MAX

20

UNIT

mA

I

‡

f = 14.4 MHz, V = 3.6 V, T = 0°C to 70°C

15

CC

A

†

‡

A

I

characteristics are inversely proportional to temperature. For I dependence on frequency, see Figure 3.

CC

clock characteristics and timing

The TMS320LC17 can use either its internal oscillator or an external frequency source for a clock.

internal clock option

TheinternaloscillatorisenabledbyconnectingacrystalacrossX1andX2/CLKIN(see Figure1). Thefrequency

of CLKOUT is one-fourth the crystal fundamental frequency. The crystal should be fundamental mode, and

parallel resonant, with an effective series resistance of 30 ohms, a power dissipation of 1 mW, and be specified

at a load capacitance of 20 pF.

PARAMETER

TEST CONDITIONS

= – 40°C to 85°C

MIN

NOM

MAX

UNIT

MHz

pF

Crystal frequency f

C1, C2

4.0

14.4

x

T

A

10

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120

TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

external clock option

An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left

unconnected. The external frequency injected must conform to the specifications listed in the table below.

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

§

t

CLKOUT cycle time

CLKOUT rise time

CLKOUT fall time

277.78

1000

ns

c(C)

¶

10

ns

r(C)

R

= 825 Ω,

= 100 pF,

L

8

f(C)

C

L

Pulse duration, CLKOUT low

(see Figure 2)

131

129

w(CL)

w(CH) Pulse duration, CLKOUT high

Delay time CLKIN↑ to CLKOUT↓

25

75

d(MCC)

§

¶

t

is the cycle time of CLKOUT, i.e., 4t

(4 times CLKIN cycle time if an external oscillator is used).

c(C)

c(MC)

Values derived from characterization data and not tested

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Master clock cycle time

69.5

150

c(MC)

†

Rise time, master clock input

Fall time, master clock input

Pulse duration, master clock

Pulse duration, master clock low at t

5

10

ns

r(MC)

5

ns

f(MC)

†

0.4t

)

0.6t

)

ns

w(MCP)

w(MCL)

w(MCH)

c(MC

min

30

ns

c(MC)

Pulse duration, master clock high at t

c(MC)

min

ns

†

Values derived from characterization data and not tested.

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

ns

†

10

t

Delay time CLKOUT↓ to address bus valid

Delay time CLKOUT↓ to DEN↓

100

d1

†

1/4 t

–10

–5

1/4 t

1/2 t

1/4 t

+25

30

ns

d4

c(C)

†

c(C)

Delay time CLKOUT↓ to DEN↑

ns

d5

Delay time CLKOUT↓ to WE↓

1/2 t

–5

+25

30

ns

d6

c(C)

†

R

= 825 Ω,

= 100 pF,

L

Delay time CLKOUT↓ to WE↑

–10

ns

d7

C

L

Delay time CLKOUT↓ to data bus OUT valid

Time after CLKOUT↓ that data bus starts to be driven

Time after CLKOUT↓ that data bus stops being driven

Data bus OUT valid after CLKOUT↓

+130

c(C)

ns

(see Figure 2)

d8

†

1/4 t

–5

ns

d9

c(C)

1/4 t

+90

c(C)

ns

d10

1/4 t

0

–10

ns

v

†

Address hold time after WE↑, MEN↑, or DEN↑ (see Note 14)

Address bus setup time or DEN↓

ns

h(A-WMD)

su(A-MD)

0

ns

†

Values derived from characterization data and not tested.

NOTE 14: Address bus will be valid upon WE↑, MEN↑, or DEN↑.

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TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

timing requirements over recommended operating conditions

TEST CONDITIONS

MIN

80

0

NOM

MAX

UNIT

ns

R

= 825 Ω,

= 100 pF,

L

t

Setup time data bus valid prior to CLKOUT↓

su(D)

C

L

Hold time data bus held valid after CLKOUT↓ (see Note 9)

(see Figure 2)

ns

h(D)

NOTE 9: Data may be removed from the data bus upon MEN↑ or DEN↑ preceding CLKOUT↓.

RESET (RS) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

1/2t

MAX

UNIT

ns

t

Delay time DEN↑, WE↑, and MEN↑ from RS

Data bus disable time after RS

+75

d11

c(C)

R

= 825 Ω,

= 100 pF,

L

1/4t

ns

dis(R)

d12

C

L

†

Delay time from RS↓ to high-impedance SCLK

Delay time from RS↓ to high-impedance DX1, DX0

200

ns

(see Figure 2)

†

ns

d13

†

These values were derived from characterization data and not tested.

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Reset (RS) setup time prior to CLKOUT (see Note 10)

RS pulse duration

85

su(R)

5t

c(C)

ns

w(R)

NOTE 10: RS can occur anytime during a clock cycle. Time given is minimum to ensure synchronous operation.

INTERRUPT (EXINT) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Fall time EXINT

15

f(INT)

Pulse duration EXINT

t

ns

w(INT)

su(INT)

c(C)

85

Setup time EXINT↓ before CLKOUT↓

ns

I/O (BIO) TIMING

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Fall time BIO

15

f(IO)

Pulse duration BIO

t

ns

w(IO)

su(IO)

c(C)

85

Setup time BIO↓ before CLKOUT↓

ns

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TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

I/O (BIO) TIMING

switching characteristics over recommended operating conditions

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

R

C

= 825 Ω,

= 100 pF,

L

†

5

t

Delay time CLKOUT↓ to valid XF

115

ns

d(XF)

(see Figure 2)

†

Values derived from characterization data and not tested.

SERIAL PORT TIMING

switching characteristics over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

t

Internal framing (FR) delay from SCLK rising edge

DX bit 1 valid before SCLK falling edge

DX bit 2 valid before SCLK falling edge

DX hold time after SCLK falling edge

120

d(CH-FR)

d(DX1-CL)

d(DX2-CL)

h(DX)

20

ns

t

/2

ns

c(SCLK)

timing requirements over recommended operating conditions

MIN

NOM

MAX

UNIT

ns

‡

t

Serial port clock (SCLK) cycle time

Serial port clock (SCLK) fall time

Serial port clock (SCLK) rise time

555

8000

c(SCLK)

f(SCLK)

r(SCLK)

w(SCLK)

w(SCLKH)

su(FS)

†

30

ns

†

ns

§

Serial port clock (SCLK) low, pulse duration

250

130

20

4400

ns

§

Serial port clock (SCLK) high, pulse duration

FSX/FSR setup time before SCLK falling edge

DR setup time before SCLK falling edge

DR hold time after SCLK falling edge

ns

su(DR)

20

ns

h(DR)

†

‡

§

Values derived from characterization data and not tested.

Minimum cycle time is 2t

where t

is CLKOUT cycle time.

c(C)

The duty cycle of the serial port clock must be within 45 to 55%.

c(C)

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TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

COPROCESSOR INTERFACE TIMING

switching characteristics over recommended operating conditions

MIN

NOM

MAX

150

UNIT

ns

t

RD low to TBLF high

WR low to RBLF high

RD low to data valid

d(R-A)

d(W-A)

a(RD)

h(RD)

ns

Data hold time after RD high

25

timing requirements over recommended operating conditions

MIN

25

NOM

MAX

UNIT

ns

t

HI/RD hold time after WR or RD high

HI/RD setup time prior to WR or RD low

Data setup time prior to WR high

Data hold time after WR high

Pulse duration, RD low

h(HL)

40

ns

su(HL)

su(WR)

h(WR)

w(RDL)

w(WRL)

50

ns

35

ns

150

ns

Pulse duration, WR low

ns

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TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

clock timing

t

r(MC)

w(MCH)

†

t

w(MCP)

t

c(MC)

X2/CLKIN

t

w(MCL)

t

f(MC)

t

w(CH)

†

t

d(MCC)

CLKOUT

t

r(C)

f(C)

t

w(CL)

t

c(C)

are referenced to an intermediate level of 1.5 V on the CLKIN waveform.

†

t

and t

w(MCP)

d(MCC)

IN instruction timing

CLKOUT

MEN

PA2-PA0

DEN

1

2

5

t

su(A-MD)

4

t

su(D)

t

3

t

d5

d4

t

h(D)

D15-D0

6

7

8

Legend:

1. IN Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Input Valid

8. Instruction Valid

4. Peripheral Address Valid

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TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

OUT instruction timing

CLKOUT

MEN

1

3

2

5

4

PA2-PA0

t

d6

d7

WE

t

d9

t

d10

t

d8

t

v

7

6

8

D15-D0

Legend:

1. OUT Instruction Prefetch

2. Next Instruction Prefetch

3. Address Bus Valid

5. Address Bus Valid

6. Instruction Valid

7. Data Output Valid

8. Instruction Valid

4. Peripheral Address Valid

reset timing

CLKOUT

RS

t

su(R)

t

su(R)

t

w(R)

DEN

WE

t

d11

t

dis(R)

Data

Out

D15-D0

t

d12

SCLK

d13

DX1, DX0

PC = 0

PA = PC3 = 0

PC = 1

PA = Port Address PC3 = 3 LSB of PC

Valid Valid

PA = PC3 + 1 = 1

PA2-PA0

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TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

interrupt timing

CLKOUT

t

su(INT)

INT

t

f(INT)

t

w(INT)

BIO timing

CLKOUT

t

su(IO)

BIO

t

f(IO)

t

w(IO)

XF timing

CLKOUT

PA2-PA0

WE

1

t

d7

t

d6

t

d9

2

t

d10

t

v

t

d8

D15-D0

3

4

t

d(XF)

XF

XF Valid

Legend:

1. Port Address Valid

2. Out Opcode Valid

3. Port Data Valid

4. Next Instruction Opcode Valid

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127

TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

external framing: transmit timing

t

r(SCLK)

t

w(SCLKH)

8

SCLK

1

2

3

t

su(FS)

t

w(SCLKL)

t

su(FS)

t

f(SCLK)

FSX

t

h(DX)

t

d(DX1-CL)

d(DX2-CL)

1

2

DX1, DX0

3

8

NOTES: A. Data valid on transmit output until SCLK rises.

B. The most significant bit is shifted first.

external framing: receive timing

SCLK

1

2

3

8

t

su(FS)

t

su(FS)

FSR

t

su(DR)

t

h(DR)

DR1, DR0

1

2

3

8

NOTE B: The most significant bit is shifted first.

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128

TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

internal framing: variable-data rate

SCLK

t

d(CH-FR)

FR

t

h(DX)

2

t

d(DX2-CL)

t

d(DX1-CL)

1

3

8

DX1, DX0

DR1, DR0

t

su(DR)

t

h(DR)

1

2

3

8

NOTE: The most significant bit is shifted first.

internal framing: fixed-data rate

SCLK

t

d(CH-FR)

t

d(CH-FR)

FR

t

d(DX2-CL)

t

h(DX)

2

1

3

8

DX1, DX0

t

d(DX1-CL)

t

h(DR)

1

2

3

8

DR1, DR0

t

su(DR)

NOTE: The most significant bit is shifted first.

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129

TMS320LC17

DIGITAL SIGNAL PROCESSOR

SPRS009C–JANUARY 1987–REVISED JULY 1991

coprocessor timing: external write to coprocessor port

HI/LO

t

w(WRL)

t

w(WRL)

t

h(HL)

t

su(HL)

t

h(HL)

su(HL)

WR

t

h(WR)

t

su(WR)

Valid

su(WR)

Valid

DATA IN

t

d(W-A)

RBLE

Only necessary for operation of 8-bit mode

constructing 16-bit data

coprocessor timing: external read to coprocessor port

HI/LO

t

w(RDL)

su(HL)

t

w(RDL)

su(HL)

t

h(HL)

t

h(HL)

t

RD

t

h(RD)

t

a(RD)

DATA

OUT

Valid

t

d(R-A)

TBLF

Only necessary for operation of 8-bit mode

constructing 16-bit data

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130

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

THERMAL RESISTANCE CHARACTERISTICS

Commercial Devices

Device/Package Thermal Resistance

Junction To Case

R

(°C/W)

θJC

DEVICE

PDIP (N)

CDIP (JD)

PLCC (FN)

CLCC (FZ)

QFP (PG)

TMS320C10

TMS320C10-14

TMS320C10-25

TMS320C14

TMS320E14

TMS320P14

TMS320C15

TMS320C15-25

TMS320E15

TMS320E15-25

TMS320LC15

TMS320P15

TMS320C16

TMS320C17

TMS320E17

TMS320LC17

TMS320P17

26

17

11

8

11

17

26

8

26

13

17

13

25

26

17

8

26

13

17

13

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131

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

THERMAL RESISTANCE CHARACTERISTICS

Commercial Devices

Device/Package Thermal Resistance

Junction To Ambient

R

(°C/W)

θJA

DEVICE

PDIP (N)

CDIP (JD)

PLCC (FN)

CLCC (FZ)

QFP (PG)

TMS320C10

TMS320C10-14

TMS320C10-25

TMS320C14

TMS320E14

TMS320P14

TMS320C15

TMS320C15-25

TMS320E15

TMS320E15-25

TMS320LC15

TMS320P15

TMS320C16

TMS320C17

TMS320E17

TMS320LC17

TMS320P17

84

60

46

49

46

60

84

40

64

84

40

60

55

120

84

60

40

64

84

40

60

55

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132

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

MECHANICAL DATA

40-pin plastic dual-in-line package

53,1 (2.090) Max

40

21

Either or Both

Index Marks

15,24

0,25

(0.600

0.010)

C

L

C

L

1

0,51

(0.020)

Min

5,08

(0.200)

Max

Seating Plane

105°

90°

2,92 (0.115)

Min

0,457 ± 0,076

(0.018 ± 0.003)

0,28 ± 0,08

(0.011 ± 0.003)

0,84

(0.033)

Min

2,41 (0.095)

1,40 (0.055)

2,54 (0.100) T.P.

Pin Spacing

1,52

(0.060)

Nom

(See Note A)

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position.

40-pin windowed ceramic dual-in-line package

51,31 (2.020) Max

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

15,0 (0.590)

Nom

Index Dot

15,24

(0.600

0,25

0.010)

1

2

3

4

5

6

7

8

9

11

10

12 13 14 15 16 17 18 19 20

4,70 (0.185)

C

L

0,508 (0.020)

Min

Max

Seating

Plane

105°

90°

1,27

(0.050

0,254

0.010)

1,27

(0.050

0,508

0.020)

2,54 (0.100) T.P.

Pin Spacing

(see Note A)

3,81

(0.150

0,762

0.030)

0,25(0.010)

Nom

0,457

0,076

(0.018

0.003)

ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

NOTE A: Each pin centerline is located within 0,254 (0.010) of its true longitudinal position.

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

44-lead plastic chip carrier (FN suffix)

16,66 (0.656)

16,51 (0.650)

17,65 (0.695)

17,40 (0.685)

Index

Dot

1,14 (0.045) × 45° Typ

4,57 (0.180)

16,66 (0.656)

16,51 (0.650)

4,19 (0.165)

17,65 (0.695)

17,40 (0.685)

3,05 (0.120)

2,29 (0.090)

0,51

(0.020)

Min

0,533 (0.021)

0,330 (0.013)

16,00 (0.630)

14,99 (0.590)

1,27

(0.050)

Typ

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

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TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

64-pin quad flat pack (PG suffix) (TMS320C16)

24,0 (0.945)

23,2 (0.913)

20,0 (0.787) Nom

51

33

52

32

18,0 (0.709)

17,2 (0.677)

14,0

(0.552)

Nom

64

20

1

19

1,0 (0.039) Typ

C

L

0,35 (0.0014) Typ

0,20 (0.008)

0,10 (0.004)

3,10 (0.122) Max

1,0 (0.040)

0,6 (0.024)

0,1 (0.004) Min

0°-10°

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

135

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

MECHANICAL DATA

68-lead plastic chip carrier package (FN suffix)

1,35 (0.053)

45°

1,19 (0.047)

0,25 (0.010) R Max

in 3 places

2,79 (0.110)

2,41 (0.095)

24,33 (0.956)

24,13 (0.950)

(see Note A)

4,50 (0.177)

4,24 (0.167)

25,27 (0.995)

25,02 (0.985)

23,62 (0.930)

23,11 (0.910)

(At Seating Plane)

1,27 (0.050) T.P.

(see Note B)

24,33 (0.956)

24,13 (0.950)

(see Note A)

1,22 (0.048)

1,07 (0.042)

45°

0,94 (0.037)

0,69 (0.027)

R

25,27 (0.995)

25,02 (0.985)

Seating Plane

0,81 (0.032)

0,66 (0.026)

1,52 (0.060) Min

0,64

(0.025)

Min

0,51 (0.020)

0,36 (0.014)

Lead Detail

NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this deminsion.

B. Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side.

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

136

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

MECHANICAL DATA

68-lead ceramic chip carrier package (FZ suffix)

4,57 (0.180)

3,94 (0.155)

A

(see Note A)

3,55 (0.140)

3,05 (0.120)

B

1.02 (0.040) × 45°

1,27 (0.05) Typ

(see Note B)

0,81 (0.032)

0,66 (0.026)

C

0,51 (0.020)

(at Seating

A

B

0,36 (0.014)

Plane)

0,64 (0.025) R Max

Typ, 3 Places

1.016 (0.040) Min

Optional

EPROM Window

3,05 (0.120)

2,29 (0.090)

Seating Plane

(see Note C)

A

B

C

MIN

12,32

MAX

MIN

MAX

MIN

MAX

12,57

10,92

11,56

10,41

10.92

M0-087AA

28

44

68

(0.485) (0.495) (0.430) (0.455) (0.410) (0.430)

17,40 17,65 16,00 16,64 15,49 16,00

(0.685) (0.695) (0.630) (0.655) 0.610) (0.630)

25,02 25,27 23,62 24,26 23.11 23,62

(0.985) (0.995) (0.930) (0.955) (0.910) (0.930)

M0-087AB

M0-087AD

NOTES: A. Centerline of center pin each side is within 0,10 (0.004) of package centerline as determined by dimension B.

B. Location of each pin is within 0,27 (0.005) of true position with respect to center pin on each side.

C. The lead contact points are planar within 0,15 (0.006)

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

137

TMS320C1x

DIGITAL SIGNAL PROCESSORS

SPRS009C–JANUARY 1987–REVISED JULY 1991

INDEX

accumulator/ALU . . . . . . . . . . . . . . . . . . . . . . 5

key features (TMS320C1x) . . . . . . . . . . . . . . 1

TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 11

TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 28

TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 52

TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 79

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 95

architecture (TMS320C1x family) . . . . . . 5, 6

TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 32

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 96

functional block diagram

TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 13

TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 32

TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 53

TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 82

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 95

mechanical data . . . . . . . . . . . . . . . 133 – 137

memory (TMS320C1x) . . . . . . . . . . . . . 2, 3, 5

TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 11

TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 28

TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 52

TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 79

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 95

codec interface

TMS320C17 . . . . . . . . . . . . . . 3, 6, 96 – 98

companding hardware

TMS320C17 . . . . . . . . . . . . . . . . . . 3, 96, 97

control register

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . . 97

coprocessor interface . . . . . . . . . . . . . . . . . 98

microcomputer/microprocessor mode . . 5, 33

microcomputer/coprocessor . . . . . . . . . . 7, 98

multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

data memory . . . . . . . . . . . . . . . . . . 2, 3, 5, 33

description

package types (TMS320C1x) . . . . . . . . . . . . 4

pinout/nomenclature

TMS320C10 . . . . . . . . . . . . . . . . . . . 2, 3, 11

TMS320C14 . . . . . . . . . . . . . . . 2, 3, 28, 29

TMS320C15 . . . . . . . . . . . . . . . . . . . 2, 3, 52

TMS320LC15 . . . . . . . . . . . . . . . . . . 2, 3, 70

TMS320C16 . . . . . . . . . . . . . . . . . . . 2, 3, 79

TMS320C17 . . . . . . . . . . . . . . . . . . . 2, 3, 95

TMS320LC17 . . . . . . . . . . . . . . . . . 2, 3, 120

TMS320C10 . . . . . . . . . . . . . . . . . . . . . 4, 11

TMS320C14 . . . . . . . . . . . . . . . . . . . . . 4, 28

TMS320C15 . . . . . . . . . . . . . . . . . . . . . 4, 52

TMS320LC15 . . . . . . . . . . . . . . . . . . . . 4, 70

TMS320C16 . . . . . . . . . . . . . . . . . . . . . 4, 79

TMS320C17 . . . . . . . . . . . . . . . . . . . . . 4, 95

TMS320LC17 . . . . . . . . . . . . . . . . . . . 4, 120

electrical specifications

serial port

TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 14

TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 35

TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 55

TMS320LC15 . . . . . . . . . . . . . . . . . . . . . . 69

TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 83

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . 102

TMS320LC17 . . . . . . . . . . . . . . . . . . . . . 120

TMS320C17/E17 . . . . . . . . . . . . . . . . . 6, 96

shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

terminal functions

TMS320C10 . . . . . . . . . . . . . . . . . . . . . . . 12

TMS320C14 . . . . . . . . . . . . . . . . . . . . . . . 30

TMS320C15 . . . . . . . . . . . . . . . . . . . . . . . 54

TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 80

TMS320C17 . . . . . . . . . . . . . . . . . . . . . . 100

EPROM programming

TMS320E14/P14 . . . . . . . . . . . . . . . . . . . 47

TMS320E15/P15 . . . . . . . . . . . . . . . . . . . 65

TMS320E17/P17 . . . . . . . . . . . . . . . . . . 114

thermal data . . . . . . . . . . . . . . . . . 27, 131, 132

timing diagrams

framing pulses

TMS320C10 . . . . . . . . . . . . . . . . . . . 23 – 26

TMS320C14 . . . . . . . . . . . . . . . 41 – 46, 51

TMS320C15 . . . . . . . . . . . . . . . 60 – 63, 68

TMS320LC15 . . . . . . . . . . . . . . . . . . 75 – 78

TMS320C16 . . . . . . . . . . . . . . . . . . . 86 – 91

TMS320C17 . . . . . . . . . . . . 107 – 113, 118

TMS320LC17 . . . . . . . . . . . . . . . 125 – 130

TMS320C17/LC17/E17/P17 . . . . . . . . . 97

instruction set . . . . . . . . . . . . . . . . . . . . . . . . . 7

interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 33

interfacing to SRAM/EPROM/peripherals

TMS320C16 . . . . . . . . . . . . . . . . . . . . . . . 90

I/O channels . . . . . . . . . . . . 2, 3, 6, 28, 79, 95

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

138

PACKAGE OPTION ADDENDUM

www.ti.com

5-Dec-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP SB

JLCC

Drawing

5962-8763308QA

5962-8763308YA

SMJ320C15-25FJM

SMJ320C15-25JDM

TMS320C10FNA

TMS320C10FNL

TMS320C10FNL25

TMS320C10NA

TMS320C10NL

ACTIVE

JD

40

44

40

44

40

0

1

TBD

Call TI

CU SNPB

Call TI

CU SNPB

Call TI

Level-NC-NC-NC

Call TI

FJ

ACTIVE

JLCC

FJ

ACTIVE

CDIP SB

JD

OBSOLETE

NRND

PLCC

PDIP

FN

N

Level-3-220C-168HR

Level-NC-NC-NC

Call TI

26

OBSOLETE

NRND

N

9

TMS320C10NL-25

TMS320C10NL25

TMS320C14FNL

TMS320C15FNA

TMS320C15FNL

TMS320C15FNL25

TMS320C15NA

TMS320C15NL

NRND

N

OBSOLETE

NRND

PLCC

PDIP

PLCC

QFP

FN

N

68

44

40

44

64

44

40

44

40

68

44

40

44

40

Call TI

OBSOLETE

Call TI

N

Call TI

TMS320C15NL-25

TMS320C15NL25

TMS320C15PEL

TMS320C16PGL

TMS320C17FNL

TMS320C17NL

N

Call TI

NL

PE

PG

FN

N

Call TI

QFP

Call TI

PLCC

PDIP

PLCC

PDIP

PLCC

PDIP

PLCC

PDIP

Call TI

TMS320LC15FNL

TMS320LC15NL

TMS320P14FNL

TMS320P15FNL

TMS320P15FNL25

TMS320P15NA

FN

N

Call TI

FN

N

Level-3-220C-168HR

Call TI

TMS320P15NL

N

Call TI

TMS320P15NL25

TMS320P17FNA

TMS320P17FNL

TMS320P17FNLR

TMS320P17NL

N

Call TI

FN

N

Call TI

TMS320SS16NL

N

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Eco Plan

5-Dec-2005

(2)

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MCDI005 – JANUARY 1998

JD (R-CDIP-T**)

CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE

24 PINS SHOWN

A

24

13

0.590 (15,00)

TYP

1

12

0.065 (1,65)

0.045 (1,14)

0.175 (4,45)

0.140 (3,56)

0.620 (15,75)

0.590 (14,99)

0.075 (1,91) MAX (4 Places)

Seating Plane

0.020 (0,51) MIN

0°–15°

0.021 (0,53)

0.015 (0,38)

0.125 (3,18) MIN

0.100 (2,54)

0.012 (0,30)

0.008 (0,20)

PINS **

24

28

1.450

40

48

52

DIM

1.250

2.050

2.435

2.650

A MAX

(31,75) (36,83) (52,07) (61,85) (67,31)

4040087/B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package is hermetically sealed with a metal lid.

D. The terminals are gold-plated.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDI008 – OCTOBER 1994

N (R-PDIP-T**)

PLASTIC DUAL-IN-LINE PACKAGE

24 PIN SHOWN

A

24

13

0.560 (14,22)

0.520 (13,21)

1

12

0.060 (1,52) TYP

0.200 (5,08) MAX

0.020 (0,51) MIN

0.610 (15,49)

0.590 (14,99)

Seating Plane

0.100 (2,54)

0.125 (3,18) MIN

0.010 (0,25) NOM

0°–15°

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

PINS **

M

24

28

32

40

48

52

DIM

1.270

1.450

1.650

2.090

2.450

2.650

A MAX

(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)

1.230

1.410

1.610

2.040

2.390

2.590

A MIN

(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)

4040053/B 04/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-011

D. Falls within JEDEC MS-015 (32 pin only)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

D

0.090 (2,29)

D1

0.020 (0,51) MIN

3

1

19

0.032 (0,81)

0.026 (0,66)

4

18

D2/E2

E

E1

8

14

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

9

13

0.007 (0,18)

M

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

**

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

20

28

44

52

68

84

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MQFP008 – JULY 1998

PG (R-PQFP-G64)

PLASTIC QUAD FLATPACK

0,45

0,25

M

0,20

1,00

51

33

52

32

14,20 18,00

13,80 17,20

12,00 TYP

64

20

1

19

0,15 NOM

18,00 TYP

20,20

19,80

24,00

23,20

Gage Plane

0,25

0,10 MIN

2,70 TYP

0°–10°

1,10

0,70

Seating Plane

3,10 MAX

0,10

4040101/B 03/95

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Contact field sales office to determine if a tighter coplanarity requirement is available for this package.

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	TMS320C10FNA
厂家：	TEXAS INSTRUMENTS
描述：	DIGITAL SIGNAL PROCESSORS 数字信号处理器数字信号处理器
文件：	总146页 (文件大小：1145K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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