TMS320C28346 [TI]
Delfino Microcontrollers; 德尔菲诺微控制器
| 型号： | TMS320C28346 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Delfino Microcontrollers |
| 文件： | 总153页 (文件大小：1965K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
Data Manual
ADVANCE INFORMATION concerns new products in the sampling
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
Literature Number: SPRS516
March 2009
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
Contents
1
TMS320C2834x (Delfino™) MCUs........................................................................................... 9
1.1
1.2
1.3
Overview ...................................................................................................................... 9
Features....................................................................................................................... 9
Getting Started.............................................................................................................. 10
2
3
Introduction....................................................................................................................... 11
2.1
Pin Assignments............................................................................................................ 13
2.2
Signal Descriptions......................................................................................................... 21
Functional Overview ........................................................................................................... 32
3.1
Memory Maps .............................................................................................................. 33
Brief Descriptions........................................................................................................... 39
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
C28x CPU ....................................................................................................... 39
Memory Bus (Harvard Bus Architecture) .................................................................... 39
Peripheral Bus .................................................................................................. 39
Real-Time JTAG and Analysis ................................................................................ 40
External Interface (XINTF) ..................................................................................... 40
M0, M1 SARAMs ............................................................................................... 40
L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs ....................................... 40
Boot ROM ........................................................................................................ 40
Security ........................................................................................................... 41
3.2.10 Peripheral Interrupt Expansion (PIE) Block .................................................................. 41
3.2.11 External Interrupts (XINT1-XINT7, XNMI).................................................................... 41
3.2.12 Oscillator and PLL .............................................................................................. 42
3.2.13 Watchdog ........................................................................................................ 42
3.2.14 Peripheral Clocking ............................................................................................. 42
3.2.15 Low-Power Modes .............................................................................................. 42
3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 43
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 43
3.2.18 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 43
3.2.19 Control Peripherals ............................................................................................. 44
3.2.20 Serial Port Peripherals ......................................................................................... 44
Register Map................................................................................................................ 45
Device Emulation Registers............................................................................................... 46
Interrupts .................................................................................................................... 47
3.3
3.4
3.5
3.5.1
External Interrupts .............................................................................................. 50
3.6
System Control ............................................................................................................. 51
3.6.1
OSC and PLL Block ............................................................................................ 52
3.6.1.1 External Reference Oscillator Clock Option....................................................... 53
3.6.1.2 PLL-Based Clock Module............................................................................ 54
3.6.1.3 Loss of Input Clock ................................................................................... 55
Watchdog Block ................................................................................................. 55
3.6.2
3.7
Low-Power Modes Block .................................................................................................. 56
4
Peripherals ........................................................................................................................ 57
4.1
4.2
4.3
4.4
4.5
4.6
DMA Overview.............................................................................................................. 57
32-Bit CPU-Timers 0/1/2 .................................................................................................. 59
Enhanced PWM Modules (ePWM1/2/3/4/5/6/7/8/9) ................................................................... 61
High-Resolution PWM (HRPWM) ........................................................................................ 64
Enhanced CAP Modules (eCAP1/2/3/4/5/6)............................................................................ 65
Enhanced QEP Modules (eQEP1/2/3) .................................................................................. 67
4.6.1 External ADC Interface .................................................................................................... 69
Multichannel Buffered Serial Port (McBSP) Module................................................................... 70
4.7
2
Contents
Submit Documentation Feedback
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
4.8
4.9
Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)..................................... 73
Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) ........................................... 78
4.10 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D) ............................................................. 81
4.11 Inter-Integrated Circuit (I2C) .............................................................................................. 84
4.12 GPIO MUX .................................................................................................................. 85
4.13 External Interface (XINTF) ................................................................................................ 92
Device Support .................................................................................................................. 94
5
6
5.1
Device and Development Support Tool Nomenclature................................................................ 94
5.2
Documentation Support ................................................................................................... 96
Electrical Specifications .................................................................................................... 100
6.1
6.2
6.3
6.4
Absolute Maximum Ratings ............................................................................................. 100
Recommended Operating Conditions.................................................................................. 101
Electrical Characteristics ................................................................................................ 101
Current Consumption..................................................................................................... 102
6.4.1
Reducing Current Consumption ............................................................................. 103
6.5
6.6
6.7
Thermal Design Considerations ........................................................................................ 105
Emulator Connection Without Signal Buffering for the MCU........................................................ 105
Timing Parameter Symbology........................................................................................... 106
6.7.1
6.7.2
6.7.3
General Notes on Timing Parameters....................................................................... 106
Test Load Circuit .............................................................................................. 106
Device Clock Table ........................................................................................... 107
6.8
6.9
Clock Requirements and Characteristics ............................................................................. 108
Power Sequencing........................................................................................................ 109
6.9.1
Power Management and Supervisory Circuit Solutions................................................... 109
6.10 General-Purpose Input/Output (GPIO)................................................................................. 112
6.10.1 GPIO - Output Timing ......................................................................................... 112
6.10.2 GPIO - Input Timing ........................................................................................... 113
6.10.3 Sampling Window Width for Input Signals.................................................................. 114
6.10.4 Low-Power Mode Wakeup Timing........................................................................... 115
6.11 Enhanced Control Peripherals .......................................................................................... 118
6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing........................................................ 118
6.11.2 Trip-Zone Input Timing ........................................................................................ 118
6.12 External Interrupt Timing................................................................................................. 120
6.13 I2C Electrical Specification and Timing ................................................................................ 121
6.14 Serial Peripheral Interface (SPI) Timing ............................................................................... 121
6.14.1 Master Mode Timing........................................................................................... 121
6.14.2 SPI Slave Mode Timing ....................................................................................... 125
6.15 External Interface (XINTF) Timing...................................................................................... 127
6.15.1 USEREADY = 0................................................................................................ 128
6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) .............................................. 128
6.15.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................. 129
6.15.4 XINTF Signal Alignment to XCLKOUT ...................................................................... 130
6.15.5 External Interface Read Timing .............................................................................. 131
6.15.6 External Interface Write Timing .............................................................................. 132
6.15.7 External Interface Ready-on-Read Timing With One External Wait State ............................. 134
6.15.8 External Interface Ready-on-Write Timing With One External Wait State.............................. 137
6.15.9 XHOLD and XHOLDA Timing ................................................................................ 140
6.16 Multichannel Buffered Serial Port (McBSP) Timing .................................................................. 142
6.16.1 McBSP Transmit and Receive Timing ...................................................................... 142
6.16.2 McBSP as SPI Master or Slave Timing..................................................................... 145
Thermal/Mechanical Data................................................................................................... 149
7
Contents
3
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
List of Figures
2-1
C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew) ........................................... 13
2-2
C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View).......................................... 14
C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View) ........................................... 15
C2834x 179-Ball ZHH MicroStar BGA™ Lower Right Quadrant (Bottom View).......................................... 16
C2834x 256-Ball ZFE Plastic BGA Upper Left Quadrant (Bottom View) .................................................. 17
C2834x 256-Ball ZFE Plastic BGA Upper Right Quadrant (Bottom View) ................................................ 18
C2834x 256-Ball ZFE Plastic BGA Lower Left Quadrant (Bottom View) .................................................. 19
C2834x 256-Ball ZFE Plastic BGA Lower Right Quadrant (Bottom View) ................................................ 20
Functional Block Diagram ....................................................................................................... 32
C28346/C28345 Memory Map .................................................................................................. 34
C28344/C28343 Memory Map .................................................................................................. 35
C28342, C28341 Memory Map.................................................................................................. 36
External and PIE Interrupt Sources............................................................................................. 47
External Interrupts ................................................................................................................ 48
Multiplexing of Interrupts Using the PIE Block ................................................................................ 49
Clock and Reset Domains ....................................................................................................... 51
OSC and PLL Block Diagram ................................................................................................... 52
Using a 3.3-V External Oscillator ............................................................................................... 53
Using a 1.8-V External Oscillator ............................................................................................... 53
Using the Internal Oscillator ..................................................................................................... 53
Watchdog Module................................................................................................................. 55
DMA Functional Block Diagram ................................................................................................. 58
CPU-Timers........................................................................................................................ 59
CPU-Timer Interrupt Signals and Output Signal .............................................................................. 59
Generation of SOC Pulses to the External ADC Module ................................................................... 61
ePWM Submodules Showing Critical Internal Signal Interconnections.................................................... 64
eCAP Functional Block Diagram................................................................................................ 65
eQEP Functional Block Diagram................................................................................................ 67
External ADC Interface........................................................................................................... 69
McBSP Module ................................................................................................................... 71
eCAN Block Diagram and Interface Circuit .................................................................................... 74
eCAN-A Memory Map ............................................................................................................ 75
eCAN-B Memory Map ............................................................................................................ 76
Serial Communications Interface (SCI) Module Block Diagram ............................................................ 80
SPI Module Block Diagram (Slave Mode) ..................................................................................... 83
I2C Peripheral Module Interfaces ............................................................................................... 84
GPIO MUX Block Diagram....................................................................................................... 86
Qualification Using Sampling Window.......................................................................................... 91
External Interface Block Diagram ............................................................................................... 92
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4
List of Figures
Submit Documentation Feedback
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
4-19
4-20
5-1
Typical 16-bit Data Bus XINTF Connections .................................................................................. 92
Typical 32-bit Data Bus XINTF Connections .................................................................................. 93
Example of C2834x Device Nomenclature .................................................................................... 95
Emulator Connection Without Signal Buffering for the MCU............................................................... 105
3.3-V Test Load Circuit ......................................................................................................... 106
Clock Timing ..................................................................................................................... 109
Power-on Reset.................................................................................................................. 110
Warm Reset ...................................................................................................................... 111
Example of Effect of Writing Into PLLCR Register.......................................................................... 112
General-Purpose Output Timing............................................................................................... 112
Sampling Mode .................................................................................................................. 113
General-Purpose Input Timing................................................................................................. 114
IDLE Entry and Exit Timing .................................................................................................... 115
STANDBY Entry and Exit Timing Diagram................................................................................... 116
HALT Wake-Up Using GPIOn ................................................................................................. 117
PWM Hi-Z Characteristics ...................................................................................................... 118
ADCSOCAO or ADCSOCBO Timing ......................................................................................... 120
External Interrupt Timing ....................................................................................................... 120
SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 123
SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 125
SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 126
SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 127
Relationship Between XTIMCLK and SYSCLKOUT ........................................................................ 130
Example Read Access.......................................................................................................... 132
Example Write Access .......................................................................................................... 133
Example Read With Synchronous XREADY Access ....................................................................... 135
Example Read With Asynchronous XREADY Access...................................................................... 136
Write With Synchronous XREADY Access................................................................................... 138
Write With Asynchronous XREADY Access ................................................................................. 139
External Interface Hold Waveform ............................................................................................ 141
McBSP Receive Timing......................................................................................................... 144
McBSP Transmit Timing........................................................................................................ 144
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0.................................................... 145
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0.................................................... 146
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1.................................................... 147
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1.................................................... 148
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
List of Figures
5
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
List of Tables
2-1
C2834x Hardware Features ..................................................................................................... 12
2-2
Signal Descriptions ............................................................................................................... 21
Wait-states ......................................................................................................................... 38
Boot Mode Selection.............................................................................................................. 40
Peripheral Frame 0 Registers .................................................................................................. 45
Peripheral Frame 1 Registers ................................................................................................... 45
Peripheral Frame 2 Registers ................................................................................................... 46
Peripheral Frame 3 Registers ................................................................................................... 46
Device Emulation Registers ..................................................................................................... 46
PIE Peripheral Interrupts ........................................................................................................ 49
PIE Configuration and Control Registers ...................................................................................... 50
External Interrupt Registers...................................................................................................... 50
PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 52
PLL Settings ....................................................................................................................... 54
CLKIN Divide Options ............................................................................................................ 54
Possible PLL Configuration Modes ............................................................................................. 55
Low-Power Modes ................................................................................................................ 56
CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 60
ePWM1-4 Control and Status Registers ....................................................................................... 62
ePWM5-9 Control and Status Registers ....................................................................................... 63
eCAP Control and Status Registers ............................................................................................ 66
eQEP Control and Status Registers............................................................................................ 68
External ADC Interface Registers .............................................................................................. 69
McBSP Register Summary ...................................................................................................... 72
3.3-V eCAN Transceivers ....................................................................................................... 74
CAN Register Map ............................................................................................................... 77
SCI-A Registers .................................................................................................................. 79
SCI-B Registers .................................................................................................................. 79
SCI-C Registers .................................................................................................................. 79
SPI-A Registers ................................................................................................................... 82
SPI-D Registers ................................................................................................................... 82
I2C-A Registers.................................................................................................................... 85
GPIO Registers ................................................................................................................... 87
GPIO-A Mux Peripheral Selection Matrix ..................................................................................... 88
GPIO-B Mux Peripheral Selection Matrix ..................................................................................... 89
GPIO-C Mux Peripheral Selection Matrix ..................................................................................... 90
XINTF Configuration and Control Register Mapping ......................................................................... 93
TMS320x2834x Delfino Peripheral Selection Guide ......................................................................... 96
TMS320C28346/C28344/C28342 Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT ....... 102
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
5-1
6-1
6
List of Tables
Submit Documentation Feedback
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
6-2
TMS320C28345/C28343/C28341 Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT ....... 103
Typical Current Consumption by Various Peripherals ..................................................................... 104
Clocking and Nomenclature (300-MHz devices) ............................................................................ 107
Clocking and Nomenclature (200-MHz devices) ............................................................................ 107
Input Clock Frequency .......................................................................................................... 108
XCLKIN Timing Requirements - PLL Enabled............................................................................... 108
XCLKIN Timing Requirements - PLL Disabled .............................................................................. 108
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 108
Reset (XRS) Timing Requirements ........................................................................................... 111
General-Purpose Output Switching Characteristics......................................................................... 112
General-Purpose Input Timing Requirements ............................................................................... 113
IDLE Mode Timing Requirements ............................................................................................. 115
IDLE Mode Switching Characteristics......................................................................................... 115
STANDBY Mode Timing Requirements ...................................................................................... 115
STANDBY Mode Switching Characteristics ................................................................................. 116
HALT Mode Timing Requirements ............................................................................................ 116
HALT Mode Switching Characteristics ....................................................................................... 117
ePWM Timing Requirements................................................................................................... 118
ePWM Switching Characteristics .............................................................................................. 118
Trip-Zone input Timing Requirements ........................................................................................ 118
High Resolution PWM Characteristics at SYSCLKOUT = (150 - 300 MHz)............................................. 119
Enhanced Capture (eCAP) Timing Requirement............................................................................ 119
eCAP Switching Characteristics ............................................................................................... 119
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements.................................................... 119
eQEP Switching Characteristics............................................................................................... 119
External ADC Start-of-Conversion Switching Characteristics.............................................................. 119
External Interrupt Timing Requirements...................................................................................... 120
External Interrupt Switching Characteristics ................................................................................. 120
I2C Timing ....................................................................................................................... 121
SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 122
SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 124
SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 125
SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 126
Relationship Between Parameters Configured in XTIMING and Duration of Pulse .................................... 127
XINTF Clock Configurations.................................................................................................... 130
External Interface Read Timing Requirements .............................................................................. 131
External Interface Read Switching Characteristics.......................................................................... 131
External Interface Write Switching Characteristics.......................................................................... 132
External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State).................................... 134
External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) ........................................ 134
Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) ......................................... 134
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
List of Tables
7
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
7-1
Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)........................................ 134
External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State).................................... 137
Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ......................................... 137
Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)........................................ 137
XHOLD/XHOLDA Timing Requirements ..................................................................................... 140
McBSP Timing Requirements.................................................................................................. 142
McBSP Switching Characteristics ............................................................................................. 143
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................. 145
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................. 145
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................. 146
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................. 146
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................. 147
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................. 147
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................. 148
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)............................. 148
Thermal Model 179-Ball ZHH Results ........................................................................................ 149
Thermal Model 256-Ball ZFE Results ........................................................................................ 149
7-2
8
List of Tables
Submit Documentation Feedback
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
1
TMS320C2834x (Delfino™) MCUs
1.1 Overview
The TMS320C2834x (C2834x) Delfino™ microcontroller (MCU) devices build on TI's existing F2833x
high-performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point
performance, up to 516KB of single-access RAM, and PWM modules with 65 picoseconds of resolution.
Designed for real-time control applications, the C2834x is based on the C28x™ core, making it
code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency core make the
C2834x an excellent solution for performance-hungry real-time control applications.
1.2 Features
•
•
Dead-Band Generation
PWM Chopping by High-Frequency
Carrier
Trip Zone Input
Up to 9 HRPWM Outputs With 60 ps
MEP Resolution
•
High-Performance Static CMOS Technology
–
–
Up to 300 MHz (3.33-ns Cycle Time)
1.1-V/1.2-V Core, 3.3-V I/O, 1.8-V
PLL/Oscillator Design
•
•
•
High-Performance 32-Bit CPU (TMS320C28x)
–
IEEE-754 Single-Precision Floating-Point
Unit (FPU)
–
Six 32-bit Enhanced Capture (eCAP)
Modules
•
–
–
–
–
–
16 x 16 and 32 x 32 MAC Operations
16 x 16 Dual MAC
Harvard Bus Architecture
Fast Interrupt Response and Processing
Code-Efficient (in C/C++ and Assembly)
Configurable as 3 Capture Inputs or
3 Auxiliary Pulse With Modulator
Outputs
Single-Shot Capture of up to Four Event
Time-Stamps
•
•
•
•
Six Channel DMA Controller (for McBSP,
XINTF, and SARAM)
–
–
Three 32-bit Quadrature Encoder Pulse
(QEP) Modules
Six 32-bit Timers/Nine 16-bit Timers
16-bit or 32-bit External Interface (XINTF)
•
•
Three 32-Bit CPU Timers
Serial Port Peripherals
–
Over 2M x 16 Address Reach
On-Chip Memory
–
–
–
Up to 2 CAN Modules
Up to 3 SCI (UART) Modules
Up to 2 McBSP Modules (Configurable as
SPI)
Up to 2 SPI Modules
–
–
Up to 258K x 16 SARAM
8K x 16 Boot ROM
•
Clock and System Control
–
–
–
Dynamic PLL Ratio Changes Supported
On-Chip Oscillator
Watchdog Timer Module
–
–
One Inter-Integrated-Circuit (I2C) Bus
•
•
External ADC Interface
•
•
Peripheral Interrupt Expansion (PIE) Block
That Supports All 64 Peripheral Interrupts
Up to 88 Individually Programmable,
Multiplexed GPIO Pins With Input Filtering
Enhanced Control Peripherals
–
•
•
Advanced Emulation Features
–
–
Eighteen Enhanced Pulse Width Modulator
(ePWM) Outputs
Analysis and Breakpoint Functions
Real-Time Debug via Hardware
•
Dedicated 16-bit Time-Based Counter
With Period and Frequency Control
2834x Package Options:
–
–
•
Single-Edge, Dual-Edge Symmetric, or
Dual-Edge Asymmetric Outputs
MicroStar BGA™ (ZHH)
Plastic BGA (ZFE)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
Delfino, C28x, MicroStar BGA, TMS320C28x, TMS320C54x, TMS320C55x, Code Composer Studio are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
ADVANCE INFORMATION concerns new products in the sampling
Copyright © 2009, Texas Instruments Incorporated
or preproduction phase of development. Characteristic data and
other specifications are subject to change without notice.
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
1.3 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:
•
•
•
Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0).
C2000 Getting Started Website (http://www.ti.com/c2000getstarted)
TMS320F28x Development and Experimenter's Kits (http://www.ti.com/f28xkits)
10
TMS320C2834x (Delfino™) MCUs
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2
Introduction
The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and
TMS320C28341 devices, members of the TMS320C28x™ MCU generation, are highly integrated,
high-performance solutions for demanding control applications.
Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342,
and C28341, respectively. Table 2-1 provides a summary of features for each device.
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TMS320C28343, TMS320C28342, TMS320C28341
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Table 2-1. C2834x Hardware Features
C28346(2)
(300 MHz)
C28345
(200 MHz)
C28344
(300 MHz)
C28343(2)
(200 MHz)
C28342
(300 MHz)
C28341
(200 MHz)
FEATURE
TYPE(1)
256-Ball ZFE
PBGA(3)
256-Ball ZFE
PBGA(3)
179-Ball ZHH
BGA
256-Ball ZFE
PBGA(3)
256-Ball ZFE
PBGA(3)
179-Ball ZHH
BGA
256-Ball ZFE
PBGA(3)
256-Ball ZFE
PBGA(3)
179-Ball ZHH
BGA
Package Type
–
Instruction cycle
–
–
–
–
–
1
0
3.33 ns
Yes
5 ns
Yes
3.33 ns
Yes
5 ns
Yes
3.33 ns
Yes
5 ns
Yes
98K
No(4)
Yes
Yes
Yes
Floating-point unit
Single-access RAM (SARAM) (16-bit word)
Code security for on-chip SARAM blocks
Boot ROM (8K x 16)
258K
No(4)
Yes
258K
No(4)
Yes
130K
No(4)
Yes
130K
No(4)
Yes
98K
No(4)
Yes
16-/32-bit External Interface (XINTF)
6-channel Direct Memory Access (DMA)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6
ePWM1/2/3/
4/5/6
PWM outputs
0
0
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A
ePWM1A/2A/
3A/4A/5A/6A
HRPWM channels
32-bit Capture inputs or auxiliary PWM outputs
32-bit QEP channels (four inputs/channel)
Watchdog timer
0
0
–
–
–
1
0
0
0
0
6
3
6
3
6
3
6
3
4
2
4
2
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
External ADC Interface
32-bit CPU timers
Multichannel Buffered Serial Port (McBSP)/SPI
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
Enhanced Controller Area Network (eCAN)
Inter-Integrated Circuit (I2C)
2
2
2
2
1
1
2
2
2
2
2
2
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
General-Purpose Input/Output (GPIO) pins
(shared)
–
–
–
–
88
8
88
8
88
8
88
8
88
8
88
8
External interrupts
Temperature
T: - 40°C to 105°C
options
ZFE
TMX
ZFE
ZHH
ZFE
TMX
ZFE
ZHH
ZFE
TMX
ZFE
ZHH
Product status(5)
TMX
TMX
TMX
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect
the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) and in the peripheral
reference guides.
(2) During TMX, only C28346 and C28343 devices will be sampled. Other device configurations will be available later. For initial development, customers should use the C28346 and
C28343 devices.
(3) Initial samples will come with the ZEP designator. The designator will change to ZFE in production.
(4) Custom secure versions of these devices are available. See Section 3.2.9, Security, for more details.
(5) See Section 5.1 for descriptions of device stages.
12
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SPRS516–MARCH 2009
2.1 Pin Assignments
The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-1 through Figure 2-4.
The 256-ball ZFE plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-5 through
Figure 2-8. Table 2-2 describes the function(s) of each pin.
1
2
3
4
5
6
7
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO32/
SDAA/
VDD
P
N
EXTSOC2B
EXTSOC3B
P
N
EPWMSYNCI/
ADCSOCAO
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO33/
SCLA/
VDD
EXTSOC1A
EXTSOC3A EXTADCCLK
TDO
TRST
VSS
EPWMSYNCO/
ADCSOCBO
GPIO21/
EQEP1B/
MDRA/
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
VDD
M
EXTSOC2A EXTSOC1B
M
CANRXB
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO20/
EQEP1A/
MDXA/
VDDIO
VSS
VSS
L
TDI
L
CANTXB
GPIO15/
TZ4/XHOLDA/
SCIRXDB/
MFSXB
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
VSS
VDD
VDDIO
VDDIO
K
K
6
7
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDDIO
VSS
VDD
VDD
J
J
GPIO12/
TZ1/
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
GPIO13/
TZ2/
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VSS
H
H
CANTXB/
MDXB
CANRXB/
MDRB
1
2
3
4
5
Figure 2-1. C2834x 179-Ball ZHH MicroStar BGA™ Upper Left Quadrant (Bottom VIew)
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Delfino Microcontrollers
SPRS516–MARCH 2009
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8
9
10
11
12
13
14
GPIO54/
SPISIMOA/
XD25/
GPIO56/
SPICLKA/
XD23/
GPIO49/
ECAP6/
XD30/
GPIO58/
MCLKRA/
XD21/
VDDIO
P
TCK
P
XRS
EQEP3A
EQEP3S
SPISOMID
EPWM7A
GPIO55/
SPISOMIA/
XD24/
GPIO57/
SPISTEA/
XD22/
GPIO50/
EQEP1A/
XD29/
GPIO51/
EQEP1B/
XD28/
VDD
N
EMU0
N
XRSIO
TMS
VSS
EQEP3B
EQEP3I
SPICLKD
SPISTED
GPIO48/
ECAP5/
XD31/
GPIO59/
MFSRA/
XD20/
GPIO60/
MCLKRB/
XD19/
GPIO52/
EQEP1S/
XD27
VSS
VSS
M
M
SPISIMOD
EPWM7B
EPWM8A
GPIO61/
MFSRB/
XD18/
GPIO62/
SCIRXDC/
XD17/
GPIO53/
EQEP1I/
XD26
VDD
VDDIO
L
EMU1
L
EPWM8B
EPWM9A
GPIO63/
SCITXDC/
XD16/
GPIO64/
XD15
GPIO65/
XD14
VDDIO
VDD
VSS
VDD
K
K
EPWM9B
8
9
GPIO66/
XD13
GPIO67/
XD12
GPIO68/
XD11
VDDIO
VSS
J
J
GPIO70/
XD9
GPIO69/
XD10
VDD
VSS
VDD
H
H
10
11
12
13
14
Figure 2-2. C2834x 179-Ball ZHH MicroStar BGA™ Upper Right Quadrant (Bottom View)
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Delfino Microcontrollers
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SPRS516–MARCH 2009
1
2
3
4
5
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO8/
EPWM5A/
CANTXB/
GPIO10/
EPWM6A/
CANRXB/
VDD
VSS
G
G
ADCSOCBO
ADCSOCAO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO6/
EPWM4A/
GPIO2/
VDDIO
VSS
F
E
F
EPWMSYNCI/
EPWMSYNCO
EPWM2A
6
7
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
GPIO4/
GPIO80/
XA8
GPIO46/
XA6
VDD
VDD
E
EPWM3A
MCLKRB
GPIO85/
XA13
GPIO84/
XA12
GPIO47/
XA7
VDD
VSS
VDDIO
VDDIO
VDD18
VDD
D
C
D
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO30/
CANRXA/
XA18
GPIO29/
SCITXDA/
XA19
GPIO81/
XA9
VDD
VDD
C
GPIO31/
CANTXA/
XA17
GPIO0/
GPIO87/
XA15
GPIO83/
XA11
VDDIO
VDDIO
B
A
B
A
EPWM1A
GPIO39/
XA16
GPIO86/
XA14
GPIO82/
XA10
VSS
VSS
VSS
1
2
3
4
5
6
7
Figure 2-3. C2834x 179-Ball ZHH MicroStar BGA™ Lower Left Quadrant (Bottom View)
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
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10
11
12
13
14
GPIO71/
XD8
GPIO72/
XD7
VDD
VSS
VSS
G
G
GPIO78/
XD1
GPIO75/
XD4
GPIO74/
XD5
GPIO73/
XD6
VDDIO
F
F
E
8
9
GPIO40/
XA0
GPIO77/
XD2
GPIO76/
XD3
VDD18
VSS
VDD
VSS
E
GPIO37/
ECAP2/
XZCS7
GPIO41/
XA1
VSS
VDD
VSS
VDDIO
D
XCLKIN
D
GPIO38/
XWE0
GPIO79/
XD0
VDDIO
VDD
VDD
C
X1
C
XWE1
GPIO35/
SCITXDA/
XR/W
GPIO36/
SCIRXDA/
XZCS0
GPIO45/
XA5
GPIO42/
XA2
VSSK
VSS
B
A
XCLKOUT
B
A
GPIO28/
SCIRXDA/
XZCS6
GPIO34/
ECAP1
GPIO44/
XA4
GPIO43/
XA3
VDDIO
X2
8
XRD
14
XREADY
9
10
11
12
13
Figure 2-4. C2834x 179-Ball ZHH MicroStar BGA™ Lower Right Quadrant (Bottom View)
16
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Delfino Microcontrollers
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SPRS516–MARCH 2009
1
2
3
4
5
6
7
8
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO21/
EQEP1B/
MDRA/
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
VSS
VSS
VDDIO
T
TDI
CANRXB
GPIO20/
EQEP1A/
MDXA/
GPIO22/
EQEP1S/
GPIO25/
ECAP2/
GPIO32/
SDAA/
EXTADCCLK
VSS
VSS
R
P
TRST
TDO
MCLKXA/ EQEP2B/
EPWMSYNCI/
ADCSOCAO
CANTXB
SCITXDB
MDRB
GPIO23/
EQEP1I/
MFSXA/
GPIO26/
ECAP3/
EQEP2I/
GPIO33/
SCLA/
VDD
VSS
VSS
EXTSOC3B
EPWMSYNCO/
ADCSOCBO
SCIRXDB MCLKXB
VSS
VDDIO
VDDIO
VSS
VDDIO
N
M
EXTSOC2A EXTSOC2B EXTSOC3A
GPIO18/
SPICLKA/
EXTSOC1A EXTSOC1B
SCITXDB/
VDDIO
VSS
VDD
VDD
VDD
CANRXA
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD
VDDIO
VDD
VSS
VSS
VSS
L
GPIO15/
TZ4/XHOLDA/
SCIRXDB/
MFSXB
VSS
VDD
VSS
VDD
VSS
VSS
VSS
K
GPIO13/
TZ2/
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VDDIO
VDDIO
VDD
VSS
VSS
VSS
J
CANRXB/
MDRB
Figure 2-5. C2834x 256-Ball ZFE Plastic BGA Upper Left Quadrant (Bottom View)
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Delfino Microcontrollers
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9
10
11
12
13
14
15
16
GPIO50/
EQEP1A/
XD29/
GPIO53/
EQEP1I/
XD26
VDDIO
VSS
VSS
TCK
T
XRSIO
XRS
SPICLKD
GPIO54/
GPIO56/
GPIO48/
ECAP5/
XD31/
GPIO51/
EQEP1B/
XD28/
SPISIMOA/ SPICLKA/
VDDIO
VSS
VSS
EMU1
EMU0
VSS
R
P
N
M
L
XD25/
XD23/
EQEP3A
EQEP3S
SPISIMOD SPISTED
GPIO55/
SPISOMIA/
XD24/
GPIO57/
SPISTEA/
XD22/
GPIO49/
GPIO52/
ECAP6/
EQEP1S/
VSS
VDD
TMS
VSS
VDD
VSS
XD30/
XD27
EQEP3B
EQEP3I
SPISOMID
GPIO59/
MFSRA/
XD20/
GPIO58/
MCLKRA/
XD21/
VDDIO
VDDIO
VSS
VSS
EPWM7B
EPWM7A
GPIO62/
SCIRXDC/
XD17/
GPIO61/
MFSRB/
XD18/
GPIO60/
MCLKRB/
XD19/
VDD
VDD
VSS
VDDIO
EPWM9A
EPWM8B
EPWM8A
GPIO63/
SCITXDC/
XD16/
GPIO65/
XD14
GPIO64/
XD15
VSS
VSS
VDD
VDDIO
EPWM9B
GPIO67/
XD12
GPIO66/
XD13
VSS
VSS
VSS
VDD
VSS
VSS
K
GPIO69/
XD10
GPIO68/
XD11
VSS
VSS
VSS
VDD
VDDIO
VDDIO
J
Figure 2-6. C2834x 256-Ball ZFE Plastic BGA Upper Right Quadrant (Bottom View)
18
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GPIO10/
EPWM6A/ EPWM6B/
CANRXB/ SCIRXDB/ CANTXB/
GPIO11/
GPIO12/
TZ1/
VSS
VDD
VSS
VSS
VSS
H
G
ADCSOCBO ECAP4
MDXB
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO8/
EPWM5A/
CANTXB/
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
VSS
VDD
VSS
VSS
VSS
ADCSOCAO
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO6/
GPIO4/
EPWM4A/
VDDIO
VDDIO
VSS
VDD
VSS
VSS
VDD
VSS
VSS
F
E
D
C
B
A
EPWM3A
EPWMSYNCI/
EPWMSYNCO
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO3/
EPWM2B/
ECAP5/
GPIO2/
VSS
VDD
VDD
EPWM2A
MCLKRB
GPIO29/
SCITXDA/
XA19
GPIO0/
VSS
VDDIO
VDDIO
VDDIO
EPWM1A
GPIO30/
CANRXA/
XA18
GPIO86/
XA14
GPIO83/
XA11
GPIO81/
XA9
GPIO47/
XA7
VDD
VSS
VSS
GPIO31/
CANTXA/
XA17
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO80/
XA8
GPIO46/
XA6
VSS
VSS
GPIO87/
XA15
GPIO84/
XA12
VSS
VSS
VDDIO
VDD18
VSSK
X1
1
2
3
4
5
6
7
8
Figure 2-7. C2834x 256-Ball ZFE Plastic BGA Lower Left Quadrant (Bottom View)
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Delfino Microcontrollers
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GPIO70/
XD9
GPIO71/
XD8
GPIO72/
XD7
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VDD
H
G
F
GPIO73/
XD6
GPIO74/
XD5
GPIO75/
XD4
VSS
VSS
VDD
VSS
GPIO78/
XD1
GPIO77/
XD2
GPIO76/
XD3
VSS
VDD
VDDIO
VDDIO
VSS
VSS
GPIO79/
XD0
GPIO38/
XWE0
XWE1
VDD
VDD
VSS
E
D
C
B
A
XCLKOUT
VDDIO
VDDIO
VSS
XRD
VSS
GPIO35/
SCITXDA/
XR/W
GPIO45/
XA5
GPIO44/
XA4
GPIO42/
XA2
GPIO40/
XA0
VSS
VSS
VDD
GPIO37/
ECAP2/
XZCS7
GPIO28/
SCIRXDA/
XZCS6
GPIO34/
ECAP1/
XREADY
GPIO41/
XA1
GPIO43/
XA3
VDDIO
VSS
VSS
GPIO36/
SCIRXDA/
XZCS0
VDD18
XCLKIN
VDDIO
VSS
VSS
VSS
X2
9
10
11
12
13
14
15
16
Figure 2-8. C2834x 256-Ball ZFE Plastic BGA Lower Right Quadrant (Bottom View)
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2.2 Signal Descriptions
Table 2-2 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available
in all devices. See for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA
(typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on
GPIO0-GPIO11 pins are not enabled at reset. The pullups on GPIO12-GPIO34 are enabled upon reset.
Table 2-2. Signal Descriptions
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
JTAG
M7
R8
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
device operation. An external pulldown resistor is recommended on this pin. The value of this
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate protection. Since this is application-specific, it is recommended
that each target board be validated for proper operation of the debugger and the application. (I, ↓)
TRST
P9
M8
L6
T11
P9
JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers
adequate protection.(I)
TCK
TMS
TDI
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
T8
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
N7
N9
P8
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK.
TDO
P10
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
EMU0
EMU1
L9
R10
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
Clock
B14
D16
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled
by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register.
At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in
high-impedance state during a reset.
XCLKOUT
XCLKIN
D9
C8
A12
A7
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to VSSK. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to VSS. (I)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected
across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external
oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS
If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to VSSK. (I)
X1
X2
.
A8
A9
Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it
must be left unconnected. (O)
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Introduction
21
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
Reset
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
XRS
P8
N8
T10
T9
The output buffer of this pin is an open-drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is
low (reset), the level detected on this pin puts all output buffers on the device.in high-impedance
mode.
XRSIO
External ADC Interface Signals
EXTSOC1A
EXTSOC1B
EXTSOC2A
EXTSOC2B
EXTSOC3A
EXTSOC3B
EXTADCCLK
N1
M3
M2
P1
N2
P2
N3
M2
M3
N1
N2
N3
P2
R3
External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCA internal signals (O)
External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCB internal signals (O)
External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCA internal signals (O)
External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCB internal signals (O)
External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCA internal signals (O)
External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCB internal signals (O)
External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO and Peripheral Signals
GPIO0
General purpose input/output 0 (I/O/Z)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
B1
C1
F5
E4
E2
E3
F3
F2
D2
E1
E2
E3
F1
F2
F3
G1
GPIO1
General purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
EPWM1B
ECAP6
MFSRB
GPIO2
EPWM2A
-
-
General purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
General purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
MCLKRB
GPIO4
EPWM3A
-
-
General purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
General purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
EPWM3B
MFSRA
ECAP1
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
General purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
General purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
EPWM4B
MCLKRA
ECAP2
Enhanced capture input/output 2 (I/O)
22
Introduction
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
GPIO8
General Purpose Input/Output 8 (I/O/Z)
EPWM5A
CANTXB
ADCSOCAO
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
G4
G2
G3
H3
H2
H4
G2
G3
H1
H2
H3
J2
GPIO9
General purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
EPWM5B
SCITXDB
ECAP3
Enhanced capture input/output 3 (I/O)
GPIO10
General purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
EPWM6A
CANRXB
ADCSOCBO
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4
General purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
General purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
General purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
General purpose input/output 14 (I/O/Z)
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface
(XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To
prevent this from happening when TZ3 signal goes active, disable this function by writing
XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3
goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the
code. The XINTF will release the bus when any current access is complete and there are no
pending accesses on the XINTF. (I)
TZ3/XHOLD
H5
J3
SCITXDB
MCLKXB
SCI-B Transmit (I)
McBSP-B transmit clock (I/O)
GPIO15
General purpose input/output 15 (I/O/Z)
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the
direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is
chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven
active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals
will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when XHOLDA is active (low). (I/0)
TZ4/XHOLDA
K2
K2
SCIRXDB
MFSXB
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
General purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
K4
J5
L1
P3
L1
L2
GPIO17
SPISOMIA
CANRXB
TZ6
General purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
General purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
SPICLKA
SCITXDB
CANRXA
M1
T4
Enhanced CAN-A receive (I)
GPIO19
General purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
SPISTEA
SCIRXDB
CANTXA
Enhanced CAN-A transmit (O)
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Introduction
23
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
GPIO20
EQEP1A
MDXA
DESCRIPTION
BALL # BALL #
General purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
L4
M4
N4
P4
P5
M5
K6
M6
R4
T5
R5
P5
T6
R6
P6
T7
CANTXB
GPIO21
EQEP1B
MDRA
General purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
CANRXB
GPIO22
General purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
EQEP1S
MCLKXA
SCITXDB
GPIO23
EQEP1I
MFSXA
SCIRXDB
General purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
General purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
General purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
General purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB
General purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
General purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
A12
C3
C2
B2
B13
D1
C2
B3
GPIO29
SCITXDA
XA19
General purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
General purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17
General purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
General purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
P6
N6
R7
P7
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
General-Purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
General-Purpose Input/Output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
A13
B13
B14
C15
GPIO35
SCITXDA
XR/W
General-Purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
24
Introduction
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
GPIO36
SCIRXDA
XZCS0
General-Purpose Input/Output 36 (I/O/Z)
SCI-A receive data (I)
External Interface zone 0 chip select (O)
B12
D11
C12
A2
A13
B12
E15
B4
GPIO37
ECAP2
XZCS7
General-Purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0
General-Purpose Input/Output 38 (I/O/Z)
-
External Interface Write Enable 0 (O)
GPIO39
-
General-Purpose Input/Output 39 (I/O/Z)
-
XA16
External Interface Address Line 16 (O)
GPIO40
General-Purpose Input/Output 40 (I/O/Z)
-
E10
D10
B10
A10
A9
C12
B11
C11
B10
C10
C9
-
XA0
External Interface Address Line 0
GPIO41
-
XA1
General-Purpose Input/Output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2
General-Purpose Input/Output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3
General-Purpose Input/Output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4
General-Purpose Input/Output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
General-Purpose Input/Output 45 (I/O/Z)
B9
-
XA5
External Interface Address Line 5 (O)
GPIO46
General-Purpose Input/Output 46 (I/O/Z)
-
E7
B8
-
XA6
External Interface Address Line 6 (O)
GPIO47
General-Purpose Input/Output 47 (I/O/Z)
-
D6
C8
-
XA7
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
General-Purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
SPI-D slave in, master out (I/O)
M10
P10
N10
N11
R11
P11
T12
R12
SPISIMOD
GPIO49
ECAP6
XD30
General-Purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
SPI-D slave out, master in (I/O)
SPISOMID
GPIO50
EQEP1A
XD29
General-Purpose Input/Output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
SPI-D Clock input/output (I/O)
SPICLKD
GPIO51
EQEP1B
XD28
General-Purpose Input/Output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
SPISTED
SPI-D slave transmit enable input/output (I/O)
GPIO52
EQEP1S
XD27
General-Purpose Input/Output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
M11
L11
P12
T13
GPIO53
EQEP1I
XD26
General-Purpose Input/Output 53 (I/O/Z)
Enhanced CAP1 lndex (I/O)
External Interface Data Line 26 (O)
Submit Documentation Feedback
Introduction
25
TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
GPIO54
SPISIMOA
XD25
DESCRIPTION
BALL # BALL #
General-Purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
Enhanced QEP3 input A (I)
P12
N12
P13
N13
P14
M13
M14
L12
L13
K13
R13
P13
R14
P15
N16
N15
M16
M15
M14
L16
EQEP3A
GPIO55
SPISOMIA
XD24
General-Purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
Enhanced QEP3 input B (I)
EQEP3B
GPIO56
SPICLKA
XD23
General-Purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
Enhanced QEP3 strobe (I/O)
EQEP3S
GPIO57
SPISTEA
XD22
General-Purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
Enhanced QEP3 index (I/O)
EQEP3I
GPIO58
MCLKRA
XD21
General-Purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
EPWM7A
Enhanced PWM 7 output A and HRPWM channel (O)
GPIO59
MFSRA
XD20
General-Purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
Enhanced PWM 7 output B (O)
EPWM7B
GPIO60
MCLKRB
XD19
General-Purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
EPWM8A
Enhanced PWM 8 output A and HRPWM channel (O)
GPIO61
MFSRB
XD18
General-Purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
Enhanced PWM8 output B (O)
EPWM8B
GPIO62
SCIRXDC
XD17
General-Purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
Enhanced PWM9 output A and HRPWM channel (O)
EPWM9A
GPIO63
SCITXDC
XD16
General-Purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
Enhanced PWM9 output B (O)
EPWM9B
GPIO64
-
XD15
General-Purpose Input/Output 64 (I/O/Z)
-
External Interface Data Line 15 (O)
K12
K14
J11
J12
J13
H13
L15
L14
K15
K14
J15
J14
GPIO65
-
XD14
General-Purpose Input/Output 65 (I/O/Z)
-
External Interface Data Line 14 (O)
GPIO66
-
XD13
General-Purpose Input/Output 66 (I/O/Z)
-
External Interface Data Line 13 (O)
GPIO67
-
XD12
General-Purpose Input/Output 67 (I/O/Z)
-
External Interface Data Line 12 (O)
GPIO68
-
XD11
General-Purpose Input/Output 68 (I/O/Z)
-
External Interface Data Line 11 (O)
GPIO69
-
General-Purpose Input/Output 69 (I/O/Z)
-
XD10
External Interface Data Line 10 (O)
26
Introduction
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
GPIO70
General-Purpose Input/Output 70 (I/O/Z)
-
H12
G12
G13
F14
F13
F12
E13
E11
F10
C14
E6
H16
H15
H14
G16
G15
G14
F16
F15
F14
E16
B7
-
XD9
External Interface Data Line 9 (O)
GPIO71
-
XD8
General-Purpose Input/Output 71 (I/O/Z)
-
External Interface Data Line 8 (O)
GPIO72
-
XD7
General-Purpose Input/Output 72 (I/O/Z)
-
External Interface Data Line 7 (O)
GPIO73
-
XD6
General-Purpose Input/Output 73 (I/O/Z)
-
External Interface Data Line 6 (O)
GPIO74
-
XD5
General-Purpose Input/Output 74 (I/O/Z)
-
External Interface Data Line 5 (O)
GPIO75
-
XD4
General-Purpose Input/Output 75 (I/O/Z)
-
External Interface Data Line 4 (O)
GPIO76
-
XD3
General-Purpose Input/Output 76 (I/O/Z)
-
External Interface Data Line 3 (O)
GPIO77
-
XD2
General-Purpose Input/Output 77 (I/O/Z)
-
External Interface Data Line 2 (O)
GPIO78
-
XD1
General-Purpose Input/Output 78 (I/O/Z)
-
External Interface Data Line 1 (O)
GPIO79
-
XD0
General-Purpose Input/Output 79 (I/O/Z)
-
External Interface Data Line 0 (O)
GPIO80
-
General-Purpose Input/Output 80 (I/O/Z)
-
XA8
External Interface Address Line 8 (O)
GPIO81
General-Purpose Input/Output 81 (I/O/Z)
-
C5
C7
-
XA9
External Interface Address Line 9 (O)
GPIO82
-
General-Purpose Input/Output 82 (I/O/Z)
-
A5
B6
XA10
External Interface Address Line 10 (O)
GPIO83
-
General-Purpose Input/Output 83 (I/O/Z)
-
B5
C6
XA11
External Interface Address Line 11 (O)
GPIO84
-
General-Purpose Input/Output 84 (I/O/Z)
-
D5
A5
XA12
External Interface Address Line 12 (O)
GPIO85
-
General-Purpose Input/Output 85 (I/O/Z)
-
D4
B5
XA13
External Interface Address Line 13 (O)
GPIO86
-
General-Purpose Input/Output 86 (I/O/Z)
-
A3
C5
XA14
External Interface Address Line 14 (O)
GPIO87
-
General-Purpose Input/Output 87 (I/O/Z)
-
B3
A4
XA15
External Interface Address Line 15 (O)
XRD
A14
C13
D15
E14
External Interface Read Enable (O)
XWE1
External Memory Interface Write Enable for Upper 16-bits (O)
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Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
CPU and I/O Power Pins
VDD18
E8
C7
B8
A6
A11
A8
Oscillator and PLL Power Pin (1.8 V)
VDD18
VSSK
Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 3-10
through Figure 3-12 for proper application board connections.
VDD
D1
E1
C1
C16
E6
VDD
VDD
G1
VDD
K3
E7
VDD
M1
N5
E8
VDD
E9
VDD
P7
E10
E11
F5
VDD
J3
VDD
J4
VDD
K9
F12
G5
VDD
L10
N14
K11
H11
H14
G10
E12
D12
C11
C10
B7
VDD
G12
H5
VDD
VDD
H12
J5
VDD
CPU and logic digital power pins (1.1 V/1.2 V)
VDD
J12
K3
VDD
VDD
K5
VDD
K12
L3
VDD
VDD
L5
VDD
C6
L12
M6
M7
M8
M9
M10
M11
P1
VDD
E5
VDD
C4
VDD
VDD
VDD
VDD
VDD
VDD
P16
A3
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
D3
F1
A14
B9
J1
L2
D5
K5
K7
K8
P11
L14
D6
Digital I/O power pins (3.3 V)
D8
D11
D12
E4
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Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VSS
J14
F11
D14
A11
C9
E13
F4
F13
J1
J4
D7
J13
J16
L4
B6
B4
L13
M4
M13
N5
Digital I/O power pins
N6
N8
N11
N12
R9
T3
T14
A1
D2
F4
VSS
A2
VSS
G5
H1
A10
A15
A16
B1
VSS
VSS
J2
VSS
K1
VSS
L3
B2
VSS
L5
B15
B16
C3
VSS
L7
VSS
L8
VSS
M9
K10
M12
J10
H10
G14
G11
E14
D13
B11
E9
C4
VSS
C13
C14
D3
VSS
VSS
Digital ground pins
VSS
D4
VSS
D7
VSS
D9
VSS
D10
D13
D14
E5
VSS
VSS
VSS
VSS
D8
E12
F6
VSS
A7
VSS
A6
F7
VSS
A4
F8
VSS
F9
VSS
F10
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Delfino Microcontrollers
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Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
F11
G4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G6
G7
G8
G9
G10
G11
G13
H4
H6
H7
H8
H9
H10
H11
H13
J6
J7
J8
J9
J10
J11
K1
Digital ground pins
K4
K6
K7
K8
K9
K10
K11
K13
K16
L6
L7
L8
L9
L10
L11
M5
M12
N4
N7
N9
N10
N13
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SPRS516–MARCH 2009
Table 2-2. Signal Descriptions (continued)
ZHH
ZFE
NAME
DESCRIPTION
BALL # BALL #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N14
P3
P4
P14
R1
R2
Digital ground pins
R15
R16
T1
T2
T15
T16
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3
Functional Overview
L0 SARAM 4K x 16
(0-Wait)
M0 SARAM 1K x 16
(0-Wait)
H0 SARAM 32K x 16
(1 Wait, Prefetch)
L1 SARAM 42K x 16
(0-Wait)
M1 SARAM 1K x 16
(0-Wait)
H1 SARAM 32K x 16
(1 Wait, Prefetch)
L2 SARAM 4K x 16
(0-Wait)
H2 SARAM 32K x 16
(1 Wait, Prefetch)
L3 SARAM 4K x 16
(0-Wait)
H3 SARAM 32K x 16
(1 Wait, Prefetch)
L4 SARAM 4K x 16
(0-Wait)
H4 SARAM 32K x 16
(1 Wait, Prefetch)
L5 SARAM 4K x 16
(0-Wait)
Boot ROM
8K x 16
H5 SARAM 32K x 16
(1 Wait, Prefetch)
L6 SARAM 4K x 16
(1-Wait)
L7 SARAM 4K x 16
(1-Wait)
Memory Bus
XD31:0
FPU
TCK
TDI
XHOLDA
XHOLD
XREADY
XR/W
TMS
TDO
32-bit CPU
GPIO
MUX
88 GPIOs
(300 MHz @ 1.2 V
200 MHz @ 1.1 V)
TRST
EMU0
EMU1
XZCS0
XZCS7
XZCS6
XWE0
XCLKIN
X1
CPU Timer 0
CPU Timer 1
CPU Timer 2
XA19:1
OSC,
PLL,
LPM,
WD
DMA
6 Ch
X2
XCLKOUT
XRS
XRD
PIE
XWE1
(Interrupts)
88 GPIOs
8 External Interrupts
GPIO
MUX
Memory Bus
EXTADCCLK
EXTSOC
ADC
SoC
DMA Bus
32-bit peripheral bus
(DMA accessible)
32-bit peripheral bus
16-bit peripheral bus
FIFO
FIFO
FIFO
ePWM-1/../9
(16 Levels)
(16 Levels)
(16 Levels)
CAN-A/B
eQEP-1/2/3
McBSP-A/B
eCAP-1/../6
(32-mbox)
SCI-A/B/C
SPI-A/D
I2C
HRPWM-1/../9
GPIO MUX
88 GPIOs
Figure 3-1. Functional Block Diagram
32
Functional Overview
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3.1 Memory Maps
In Figure 3-2 through Figure 3-4, the following apply:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
•
Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline
order. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature
number SPRUFN1) for more details.
•
•
Certain memory ranges are EALLOW protected against spurious writes after configuration.
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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Block
On-Chip Memory
Start Address
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARA
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
Reserved
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
Res
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
0x01 2000
0x01 4000
0x01 6000
0x01 8000
L0 SARAM (8K x 16, DMA Accessible)
L1 SARAM (8K x 16, DMA Accessible)
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
L4 SARAM (8K x 16, DMA Accessible)
L5 SARAM (8K x 16, DMA Accessible)
L6 SARAM (8K x 16, DMA Accessible)
L7 SARAM (8K x 16, DMA Accessible)
Reserved
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
Reserved
0x30 0000
0x30 8000
0x31 0000
0x31 8000
0x32 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
H2 SARAM
(32K x 16 Prefetch)
H3 SARAM
(32K x 16 Prefetch)
H4 SARAM
(32K x 16 Prefetch)
H5 SARAM
0x32 8000
0x33 0000
(32K x 16 Prefetch)
Reserved
Reserved
0x33 FFF8
0x33 FFFF
(A)
128-Bit Password
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 3.2.9.
Figure 3-2. C28346/C28345 Memory Map
34
Functional Overview
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Block
On-Chip Memory
External Memory XINTF
Start Address
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARA
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
Reserved
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
Res
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
0x01 2000
0x01 4000
0x01 6000
0x01 8000
L0 SARAM (8K x 16, DMA Accessible)
Reserved
L1 SARAM (8K x 16, DMA Accessible)
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
L4 SARAM (8K x 16, DMA Accessible)
L5 SARAM (8K x 16, DMA Accessible)
L6 SARAM (8K x 16, DMA Accessible)
L7 SARAM (8K x 16, DMA Accessible)
0x10 0000
0x20 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
Reserved
0x30 0000
0x30 0000
0x30 8000
0x31 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
Reserved
Reserved
0x33 FFF8
0x33 FFFF
(A)
128-Bit Password
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 3.2.9.
Figure 3-3. C28344/C28343 Memory Map
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TMS320C28346, TMS320C28345, TMS320C28344
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Delfino Microcontrollers
SPRS516–MARCH 2009
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Block
On-Chip Memory
Start Address
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARA
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
Reserved
(Enabled if
VMAP = 1,
ENPIE =1)
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
Res
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
L0 SARAM (8K x 16, DMA Accessible)
Reserved
L1 SARAM (8K x 16, DMA Accessible)
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
Reserved
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
0x30 0000
0x30 8000
0x31 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
Reserved
Reserved
0x33 FFF8
0x33 FFFF
(A)
128-Bit Password
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 3.2.9.
Figure 3-4. C28342, C28341 Memory Map
36
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Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode ensures that all accesses to these
blocks happen as written. Because of the C28x pipeline, a write immediately followed by a read, to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The C28x CPU supports a block protection mode where a region of memory can be protected so as to
make sure that operations occur as written (the penalty is extra cycles are added to align the operations).
This mode is programmable and by default, it will protect the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 3-1.
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Table 3-1. Wait-states
WAIT-STATES
(CPU)
WAIT-STATES
AREA
COMMENTS
(DMA)(1)
M0 and M1 SARAMs
Peripheral Frame 0
0-wait
Fixed
0-wait (writes)
1-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (reads)
Peripheral Frame 3
Peripheral Frame 1
0-wait (writes)
1-wait (reads)
Assumes no conflicts between CPU and DMA.
Cycles can be extended by peripheral generated ready.
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed. Cycles cannot be extended by the peripheral.
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM
L5 SARAM
L6 SARAM
L7 SARAM
XINTF
0-wait data and
program
Assumes no CPU conflicts
1-wait
Assumes no conflicts between CPU and DMA
1-wait
Programmable
1-wait minimum
Programmed via the XTIMING registers or extendable via
external XREADY signal.
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes
with write buffer
enabled
0-wait data (write)
0-wait data (read)
0-wait minimum for writes assumes write buffer enabled and
not full.
Assumes no conflicts between CPU and DMA. When DMA
and CPU attempt simultaneous conflict, 1-cycle delay is
added for arbitration.
H0 SARAM
H1 SARAM
H2 SARAM
H3 SARAM
H4 SARAM
H5 SARAM
Boot-ROM
1-wait
A program-access prefetch mechanism is enabled on these
memories to improve instruction fetch performance for linear
code execution.
1-wait
(1) The DMA has a base of 4 cycles/word.
38
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3.2 Brief Descriptions
3.2.1 C28x CPU
The C2834x (C28x+FPU) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The
C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs,
but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++
engine, enabling users to develop their system control software in a high-level language. It also enables
math algorithms to be developed using C/C++. The device is as efficient in DSP math tasks as it is in
system control tasks. This efficiency removes the need for a second processor in many systems. The 32 x
32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution
problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers,
resulting in a device that is capable of servicing many asynchronous events with minimal latency. The
device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it
to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
3.2.2 Memory Bus (Harvard Bus Architecture)
As with many MCU type devices, multiple busses are used to move data between the memories and
peripherals and the CPU. The C28x memory bus architecture contains a program read bus, data read bus
and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read
and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable
single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the
C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus will prioritize memory accesses. Generally, the priority of memory
bus accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the memory
bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory
bus.)
Data Reads
Program
Reads
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the memory
bus.)
3.2.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
C2834x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge
multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16
address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus
are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports DMA access
and both 16- and 32-bit accesses (called peripheral frame 3).
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3.2.4 Real-Time JTAG and Analysis
The C2834x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices
support real-time mode of operation whereby the contents of memory, peripheral and register locations
can be modified while the processor is running and executing code and servicing interrupts. The user can
also single step through non-time critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This is a feature
unique to the C2834x device, requiring no software monitor. Additionally, special analysis hardware is
provided that allows setting of hardware breakpoint or data/address watch-points and generate various
user-selectable break events when a match occurs.
3.2.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The
chip-select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be
programmed with a different number of wait states, strobe signal setup and hold timing and each zone can
be programmed for extending wait states externally or not. The programmable wait-state, chip-select and
programmable strobe timing enables glueless interface to external memories and peripherals.
3.2.6 M0, M1 SARAMs
All C2834x devices contain these two blocks of single access memory, each 1K × 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks
on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to
execute code or for data variables. The partitioning is performed within the linker. The C28x device
presents a unified memory map to the programmer. This makes for easier programming in high-level
languages.
3.2.7 L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
The 2834x has up to 256K x 16 single-access RAM (SARAM) divided up into the following categories:
L0/1/2/3/4/5 SARAM Blocks Up to 48K x 16 of SARAM at all frequencies. Each block is
8K x 16.
L6/L7 SARAM Blocks
These 8K x 16 SARAM blocks are single-wait state at all
frequencies.
H0/1/2/3/4/5 SARAM Blocks H0-H5 are each 32K x 16 and 1-wait state at all
frequencies. A program-access prefetch buffer is used to
improve performance of linear code.
All SARAM blocks are mapped to both program and data space. L0-L7 are accessible by both the CPU
and the DMA (1 wait state).
3.2.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math
related algorithms.
Table 3-2. Boot Mode Selection
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
MODE(1)
F
E
D
1
1
1
1
1
1
1
1
0
1
0
1
TI test only
SCI-A boot
SPI-A boot
(1) All four GPIO pins have an internal pullup.
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Table 3-2. Boot Mode Selection (continued)
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
MODE(1)
I2C-A boot Timing 1
C
B
A
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
eCAN-A boot Timing 1
McBSP-A boot
Jump to XINTF x16
Reserved
eCAN-A boot Timing 2
Parallel GPIO I/O boot
Parallel XINTF boot
Jump to SARAM
Branch to check boot mode
I2C-A boot Timing 2
Reserved
TI Test Only
3.2.9 Security
The 128-bit password locations on these devices will always read back 0xFFFF. To preserve compatibility
with other C28x designs with code security, the password locations at 0x33FFF8 – 0x33FFFF must be
read after a device reset; otherwise, certain memory locations will be inaccessible. The Boot ROM code
performs this read during startup. If during debug the Boot ROM is bypassed, then it is the responsibility of
the application software to read the password locations after a reset.
Custom Encryption Option:
Custom secure versions of these devices are available. In the custom version, the 128-bit password
locations are set to a customer-chosen value, activating the Code Security Module (CSM), which protects
the Hx RAM memories from unauthorized access. Additionally, a TI-generated AES decryption routine is
embedded into an on-chip secure ROM, providing a method to secure application code that is stored
externally. Contact TI for more details.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the C2834x, 64 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12
CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
3.2.11 External Interrupts (XINT1-XINT7, XNMI)
The devices support eight masked external interrupts (XINT1-XINT7, XNMI). XNMI can be connected to
the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or
both negative and positive edge triggering and can also be enabled/disabled (including the XNMI). XINT1,
XINT2, and XNMI also contain a 16-bit free running up counter, which is reset to zero when a valid
interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. Unlike the
281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts
can accept inputs from GPIO0 – GPIO31 pins. XINT3 – XINT7 interrupts can accept inputs from GPIO32
– GPIO63 pins.
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3.2.12 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit.
A PLL is provided supporting up to 31 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly
in software, enabling the user to scale back on operating frequency if lower power operation is desired.
Refer to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.
3.2.13 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter
within a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog
can be disabled if necessary.
3.2.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption
when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN)
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled
from increasing CPU clock speeds.
3.2.15 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that need to function during IDLE are left operating. An
enabled interrupt from an active peripheral or the watchdog timer will wake the
processor from IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
Turns off the internal oscillator. This mode basically shuts down the device and
places it in the lowest possible power consumption mode. A reset or external signal
can wake the device from this mode.
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3.2.16 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE:
XINTF:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
External Interface Registers
DMA
Timers:
PF1: eCAN:
GPIO:
DMA Registers
CPU-Timers 0, 1, 2 Registers
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
ePWM:
eCAP:
eQEP:
PF2: SYS:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
External ADC Interface
SPI:
ADC:
I2C:
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
XINT
PF3: McBSP
Multichannel Buffered Serial Port Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS
is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be
connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.
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3.2.19 Control Peripherals
The C2834x devices support the following peripherals which are used for embedded control and
communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support HRPWM
features.
eCAP:
eQEP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer.
This peripheral has a watchdog timer to detect motor stall and input error detection
logic to identify simultaneous edge transition in QEP signals.
3.2.20 Serial Port Peripherals
The devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is CAN 2.0B-compliant.
McBSP: The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality
codecs for modem applications or high-quality stereo audio DAC devices. The McBSP
receive and transmit registers are supported by the DMA to significantly reduce the
overhead for servicing this peripheral. Each McBSP module can be configured as an SPI
as required.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications between the
MCU and external peripherals or another processor. Typical applications include external
I/O or peripheral expansion through devices such as shift registers, display drivers, and
ADCs. Multi-device communications are supported by the master/slave operation of the
SPI. The SPI contains a 16-level receive and transmit FIFO for reducing interrupt
servicing overhead.
SCI:
I2C:
The serial communications interface is a two-wire asynchronous serial port, commonly
known as UART. The SCI contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between an MCU and other
devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version
2.1 and connected by way of an I2C-bus. External components attached to this 2-wire
serial bus can transmit/receive up to 8-bit data to/from the MCU through the I2C module.
The I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing
overhead.
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3.3 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 3-3.
Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 3-4.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 3-5.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit DMA-accessible
peripheral bus. See Table 3-6.
Table 3-3. Peripheral Frame 0 Registers(1)
NAME
Device Emulation Registers
Code Security Module Registers
XINTF Registers
ADDRESS RANGE
0x00 0880 - 0x00 09FF
0x00 0AE0 - 0x00 0AEF
0x00 0B20 - 0x00 0B3F
0x00 0C00 - 0x00 0C3F
0x00 0CE0 - 0x00 0CFF
0x00 0D00 - 0x00 0DFF
0x00 1000 - 0x00 11FF
SIZE (×16)
ACCESS TYPE(2)
EALLOW protected
384
16
EALLOW protected
32
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
CPU–TIMER0/1/2 Registers
PIE Registers
64
32
PIE Vector Table
256
512
DMA Registers
EALLOW protected
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
Table 3-4. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6000 - 0x00 61FF
0x00 6200 - 0x00 63FF
0x00 6800 - 0x00 683F
0x00 6840 - 0x00 687F
0x00 6880 - 0x00 68BF
0x00 68C0 - 0x00 68FF
0x00 6900 - 0x00 693F
0x00 6940 - 0x00 697F
0x00 6980 - 0x00 69BF
0x00 69C0 - 0x00 69FF
0x00 6600 - 0x00 663F
0x00 6A00 - 0x00 6A1F
0x00 6A20 - 0x00 6A3F
0x00 6A40 - 0x00 6A5F
0x00 6A60 - 0x00 6A7F
0x00 6A80 - 0x00 6A9F
0x00 6AA0 - 0x00 6ABF
0x00 6B00 - 0x00 6B3F
0x00 6B40 - 0x00 6B7F
0x00 6B80 - 0x00 6BBF
0x00 6F80 - 0x00 6FFF
SIZE (×16)
512
512
64
eCAN-A Registers
eCAN-B Registers
ePWM1 + HRPWM1 registers
ePWM2 + HRPWM2 registers
ePWM3 + HRPWM3 registers
ePWM4 + HRPWM4 registers
ePWM5 + HRPWM5 registers
ePWM6 + HRPWM6 registers
ePWM7 + HRPWM7 registers
ePWM8 + HRPWM8 registers
ePWM9 + HRPWM9 registers
eCAP1 registers
64
64
64
64
64
64
64
64
32
eCAP2 registers
32
eCAP3 registers
32
eCAP4 registers
32
eCAP5 registers
32
eCAP6 registers
32
eQEP1 registers
64
eQEP2 registers
64
eQEP3 registers
64
GPIO registers
128
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Table 3-5. Peripheral Frame 2 Registers
NAME
System Control Registers
ADDRESS RANGE
0x00 7010 - 0x00 702F
0x00 7040 - 0x00 704F
0x00 7050 - 0x00 705F
0x00 7070 - 0x00 707F
0x00 7750 - 0x00 775F
0x00 7770 - 0x00 777F
0x00 7780 - 0x00 778F
0x00 7900 - 0x00 793F
SIZE (×16)
32
16
16
16
16
16
16
64
SPI-A Registers
SCI-A Registers
External Interrupt Registers
SCI-B Registers
SCI-C Registers
SPI-D Registers
I2C-A Registers
Table 3-6. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
0x00 5000 - 0x00 503F
0x00 5040 - 0x00 507F
SIZE (×16)
McBSP-A Registers
McBSP-B Registers
64
64
3.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 3-7.
Table 3-7. Device Emulation Registers
ADDRESS
RANGE
NAME
SIZE (x16)
DESCRIPTION
0x0880
0x0881
DEVICECNF
PARTID
2
1
Device Configuration Register
0x0882
Part ID Register
TMS320C28346
0xFFD0
TMS320C28345
TMS320C28344
TMS320C28343
TMS320C28342
TMS320C28341
0xFFD1
0xFFD2
0xFFD3
0xFFD4
0xFFD5
REVID
0x0883
1
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMX
PROTSTART
PROTRANGE
0x0884
0x0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
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3.5 Interrupts
Figure 3-5 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, I2C, CAN, McBSP(A),
Clear
EPWM, ECAP, EQEP)
DMA
WDINT
Watchdog
Low Power Models
WAKEINT
DMA
Sync
LPMINT
SYSCLKOUT
XINT1
XINT1
Latch
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1
to
INT12
GPIOXINT1SEL(4:0)
C28
XINT2
Core
DMA
XINT2
Latch
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
CPU Timer 1
INT14
INT13
TINT1
GPIO0.int
XNMI_
XINT13
GPIO
Mux
Latch
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
DMA
A. DMA-accessible
Figure 3-5. External and PIE Interrupt Sources
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DMA
XINT3
Interrupt Control
XINT3CR(15:0)
Latch
GPIOXINT3SEL(4:0)
DMA
XINT4
Interrupt Control
XINT4CR(15:0)
Latch
GPIOXINT4SEL(4:0)
DMA
INT1
to
XINT5
PIE
Latch
Interrupt Control
XINT5CR(15:0)
INT12
C28
Core
GPIOXINT5SEL(4:0)
DMA
XINT6
Interrupt Control
XINT6CR(15:0)
Latch
GPIOXINT6SEL(4:0)
DMA
XINT7
GPIO32.int
GPIO63.int
GPIO
Mux
Interrupt Control
XINT7CR(15:0)
Latch
GPIOXINT7SEL(4:0)
Figure 3-6. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the C2834x devices, 64 of these are used by
peripherals as shown in Table 3-8.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals or
External
INTx
MUX
INTx.6
INTx.7
INTx.8
Interrupts
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 3-7. Multiplexing of Interrupts Using the PIE Block
Table 3-8. PIE Peripheral Interrupts(1)
PIE INTERRUPTS
CPU INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
Reserved
XINT2
XINT1
Reserved
Reserved
Reserved
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
EPWM8_INT
(ePWM8)
EPWM7_INT
(ePWM7)
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP6_INT
(eCAP6)
ECAP5_INT
(eCAP5)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
Reserved
Reserved
Reserved
Reserved
EQEP3_INT
(eQEP3)
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
Reserved
Reserved
Reserved
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
MXINTA
(McBSP-A)
MRINTA
(McBSP-A)
MXINTB
(McBSP-B)
MRINTB
(McBSP-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
DINTCH6
(DMA)
DINTCH5
(DMA)
DINTCH4
(DMA)
DINTCH3
(DMA)
DINTCH2
(DMA)
DINTCH1
(DMA)
Reserved
Reserved
Reserved
Reserved
SCITXINTC
(SCI-C)
SCIRXINTC
(SCI-C)
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
Reserved
Reserved
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
EPWM9_TZINT
(ePWM9)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XINT7
Reserved
Reserved
XINT6
Reserved
Reserved
XINT5
Reserved
Reserved
XINT4
EPWM9_INT
(ePWM9)
LUF
(FPU)
LVF
(FPU)
XINT3
(1) Out of the 96 possible interrupts, 64 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is
being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there is one sage case when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
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Table 3-9. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (X16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
3.5.1 External Interrupts
Table 3-10. External Interrupt Registers
NAME
XINT1CR
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7073
0x00 7074
0x00 7075
0x00 7076
0x00 7077
0x00 7078
0x00 7079
0x707A - 0x707E
0x00 707F
SIZE (x16)
DESCRIPTION
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT4 configuration register
XINT5 configuration register
XINT6 configuration register
XINT7 configuration register
XNMI configuration register
XINT1 counter register
1
1
1
1
1
1
1
1
1
1
5
1
XINT2CR
XINT3CR
XINT4CR
XINT5CR
XINT6CR
XINT7CR
XNMICR
XINT1CTR
XINT2CTR
Reserved
XNMICTR
XINT2 counter register
XNMI counter register
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Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2834x Delfino System Control and Interrupts
Reference Guide (literature number SPRUFN1).
3.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. shows the various clock and reset domains that will be discussed.
C28x Core
SYSCLKOUT
System
Clock enables
control
register
LSPCLK
LOSPCP
Bridge
I/O
Peripheral
SPI-A/D, SCI-A/B/C
registers
Clock enables
/4
I/O
Peripheral
eCAN-A/B
registers
Clock enables
GPIO
Mux
Bridge
I/O
Peripheral
registers
ePWM1/../9, HRPWM1/../9,
eCAP1/../6, eQEP1/../3
Clock enables
LSPCLK
LOSPCP
I/O
Peripheral
registers
McBSP-A/B
Clock enable
Bridge
CPU timer
registers
CPU timer 0/1/2
Clock enable
EXTADCCLK
EXTSOC
HISPCP
Bridge
ADC SOC
Peripheral
registers
I2C-A
DMA
Clock Enables
Figure 3-8. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers
(enables peripheral clocks) occurs to when the action is valid. This delay must be taken
into account before attempting to access the peripheral configuration registers.
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-11.
Table 3-11. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
ADDRESS
0x00 7011
SIZE (x16)
DESCRIPTION
PLLSTS
1
7
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
6
1
1
PLL Status Register
Reserved
Reserved
PCLKCR2
HISPCP
0x00 7012 - 0x00 7018
0x00 7019
Peripheral Clock Control Register 2
High-Speed Peripheral Clock Pre-Scaler Register
Low-Speed Peripheral Clock Pre-Scaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Low Power Mode Control Register 1
Peripheral Clock Control Register 3
PLL Control Register
0x00 701A
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
SCSR
0x00 7022
System Control and Status Register
Watchdog Counter Register
Reserved
WDCNTR
Reserved
WDKEY
0x00 7023
0x00 7024
0x00 7025
Watchdog Reset Key Register
Reserved
Reserved
WDCR
0x00 7026 - 0x00 7028
0x00 7029
Watchdog Control Register
Reserved
Reserved
EXTSOCCFG
Reserved
0x00 702A - 0x00 702C
0x00 702D
External ADC SOC Configuration Register
Reserved
0x00 702E
3.6.1 OSC and PLL Block
Figure 3-9 shows the OSC and PLL block.
OSCCLK
OSCCLK
/1
XCLKIN
(3.3-V clock input
from external
oscillator)
0
n
OSCCLK or
VCOCLK
/2
/4
/8
CLKIN
To
CPU
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
VCOCLK
PLL
n ≠ 0
PLLSTS[DIVSEL]
5-bit multiplier PLLCR[DIV]
X1
External
Crystal or
Resonator
On-chip
oscillator
X2
Figure 3-9. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the C2834x devices using the
X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the
following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied to VSSK. The logic-high level in this case should not exceed VDDIO
.
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left
unconnected and the XCLKIN pin tied to VSS. The logic-high level in this case should not exceed
VDD18
.
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The three possible input-clock configurations are shown in Figure 3-10 through Figure 3-12.
XCLKIN
X1
X2
VSSK
NC
External Clock Signal
)
(Toggling 0 -VDDIO
Figure 3-10. Using a 3.3-V External Oscillator
X2
X1
XCLKIN
External Clock Signal
NC
(Toggling 0−V
)
DD
Figure 3-11. Using a 1.8-V External Oscillator
VSSK
VDD18
X1
X2
XCLKIN
Crystal
1.8 V
C1
C2
Figure 3-12. Using the Internal Oscillator
3.6.1.1 External Reference Oscillator Clock Option
The on-chip oscillator requires an external crystal to be connected across the X1 and X2 pins.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in
Figure 3-12. The load capacitors, C1 and C2, must be chosen such that the equation below is satisfied
(typical values are on the order of C1=C2=10 pF). CL in the equation is the load specified for the crystal.
All discrete components used to implement the oscillator circuit must be placed as close as possible to the
associated oscillator pins (X1, X2, and VSSK).
NOTE
The external crystal load capacitors must be connected only to the oscillator ground pin
(VSSK). Do not connect to board ground (VSS).
C1C2
CL +
(C1 ) C2)
Where: CL equals the crystal load capacitance.
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TI recommends that customers have the crystal vendor characterize the operation of their device with the
MCU chip. The crystal vendor has the equipment and expertise to tune the crystal circuit. The vendor can
also advise the customer regarding the proper component values that will produce proper start up and
stability over the entire operating range.
3.6.1.2 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized. The input
clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) falls between 400 MHz and 600 MHz. The PLLSTS[DIVSEL] bit should be selected such that
SYSCLKOUT(CLKIN) does not exceed the maximum operating frequency allowed for the device
(300 MHz or 200 MHz).
Table 3-12. PLL Settings(1)
SYSCLKOUT (CLKIN)
PLLCR[DIV]
VALUE(2) (3)
PLLSTS[DIVSEL] = 0
PLLSTS[DIVSEL] = 1
(4)
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3
00000 (PLL bypass)
00001
OSCCLK/8 (Default)
(OSCCLK * 2)/8
(OSCCLK * 3)/8
(OSCCLK * 4)/8
(OSCCLK * 5)/8
(OSCCLK * 6)/8
(OSCCLK * 7)/8
(OSCCLK * 8)/8
(OSCCLK * 9)/8
(OSCCLK * 10)/8
(OSCCLK * 11)/8
OSCCLK/4
OSCCLK/2
OSCCLK
(OSCCLK * 2)/4
(OSCCLK * 3)/4
(OSCCLK * 4)/4
(OSCCLK * 5)/4
(OSCCLK * 6)/4
(OSCCLK * 7)/4
(OSCCLK * 8)/4
(OSCCLK * 9)/4
(OSCCLK * 10)/4
(OSCCLK * 11)/4
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
(OSCCLK * 11)/2
–
–
–
–
–
–
–
–
–
–
–
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011 - 11111
(OSCCLK * 12)/8 –
(OSCCLK * 32)/8
(OSCCLK * 12)/4 –
(OSCCLK * 32)/4
(OSCCLK * 12)/2 –
(OSCCLK * 32)/2
(1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set only to 2 or 3 after PLLSTS[PLLLOCKS] = 1. By default,
PLLSTS[DIVSEL] is configured for /8. The boot ROM changes this to /2 or /1, depending on the boot option.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(3) This register is EALLOW protected. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number
SPRUFN1) for more information.
(4) PLLSTS[DIVSEL] = 3 should be used only when the PLL is bypassed or off.
Table 3-13. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/8
/4
/2
/1
The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
•
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
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Table 3-14. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL](1)
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0
1
2
3
OSCCLK/8
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0
1
2
3
OSCCLK/8
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
0
1
2
3
OSCCLK*n/8
OSCCLK*n/4
OSCCLK*n/2
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
(2)
–
(1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set to 2 or 3 only after PLLSTS[PLLLOCKS] = 1. See the
TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for more information.
(2) PLLSTS[DIVSEL] should not be set to /1 mode while the PLL is enabled and not bypassed.
3.6.1.3 Loss of Input Clock
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C
circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O
pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged.
3.6.2 Watchdog Block
The watchdog block on the C2834x device is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset
the watchdog counter. Figure 3-13 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR(7:0)
OSCCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Watchdog
55 + AA
Key Detector
Output Pulse
(512 OSCCLKs)
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
1
0
1
(A)
WDRST
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-13. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
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In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section Section 3.7,
Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
3.7 Low-Power Modes Block
The low-power modes on the C2834x devices devices are similar to the 240x devices. Table 3-15
summarizes the various modes.
Table 3-15. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
IDLE
00
On
On
On(2)
On
XRS, Watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
STANDBY
HALT
01
1X
Off
Off
Off
Off
(watchdog still running)
Off
XRS, GPIO Port A signal, XNMI,
debugger(3)
(oscillator and PLL turned off,
watchdog not functional)
(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized
by the processor. The LPM block performs no tasks during this mode as
long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the
device from HALT mode. The user selects the signal in the GPIOLPMSEL
register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included).
They will be in whatever state the code left them in when the IDLE instruction was
executed. See the TMS320x2834x Delfino System Control and Interrupts Reference
Guide (literature number SPRUFN1) for more details.
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4
Peripherals
The integrated peripherals are described in the following subsections:
•
•
•
6-channel Direct Memory Access (DMA)
Three 32-bit CPU-Timers
Up to nine enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7,
ePWM8, ePWM9)
•
•
•
•
•
•
•
•
•
•
Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)
Up to three enhanced QEP modules (eQEP1, eQEP2, eQEP3)
External analog-to-digital converter (ADC) Interface
Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)
Up to two serial peripheral interface (SPI) modules (SPI-A, SPI-D)
Inter-integrated circuit module (I2C)
Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules
Digital I/O and shared pin functions
External Interface (XINTF)
4.1 DMA Overview
Features:
•
•
6 Channels with independent PIE interrupts
Trigger Sources:
–
–
–
–
McBSP-A and McBSP-B transmit and receive logic
XINT1-7 and XINT13
CPU Timers
Software
•
Data Sources/Destinations:
–
–
–
L0-L7 64K ×16 SARAM
All XINTF zones
McBSP-A and McBSP-B transmit and receive buffers
•
•
Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
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CPU bus
INT7
L0
L0 RAM
I/F
External
interrupts
CPU
timers
PIE
L1
L1 RAM
I/F
L2
L2 RAM
I/F
L3
L3 RAM
I/F
CPU
L4
L4 RAM
I/F
McBSP A
Event
DMA
6-ch
L5
L5 RAM
triggers
I/F
PF3
I/F
L6
I/F
McBSP B
L6 RAM
L7 RAM
L7
I/F
DMA bus
Figure 4-1. DMA Functional Block Diagram
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4.2 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
SYSCLKOUT
PSCH:PSC
TCR.4
32-Bit Counter
TIMH:TIM
(Timer Start Status)
Borrow
Borrow
TINT
Figure 4-2. CPU-Timers
The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3.
INT1
TINT0
PIE
CPU-TIMER 0
to
INT12
28x
CPU
TINT1
CPU-TIMER 1
INT13
INT14
XINT13
TINT2
CPU-TIMER 2
(Reserved for DSP/BIOS)
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers. For more information, see the
TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1).
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
TIMER0TIM
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
0x0C12
0x0C13
0x0C14
0x0C15
0x0C16
0x0C17
SIZE (x16)
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
0x0C18
0x0C3F
Reserved
40
60
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4.3 Enhanced PWM Modules (ePWM1/2/3/4/5/6/7/8/9)
The devices contain up to nine enhanced PWM Modules (ePWM). Figure 4-4 shows a block diagram of
multiple ePWM modules. Figure 4-4 shows the signal interconnections with the ePWM.
Table 4-2 and Table 4-3 show the complete ePWM register set per module.
EXTSOC1A
POLSEL
0
EXTSOC1A
1
ePWM1SOCA
ePWM1
EXTSOC1B
ePWM1SOCB
POLSEL
ePWM2SOCA
ePWM2
ePWM2SOCB
0
1
EXTSOC1B
ePWM3SOCA
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
EXTSOC2A
POLSEL
ePWM3SOCB
ePWM4SOCA
0
1
ePWM4SOCB
EXTSOC2A
ePWM5SOCA
ePWM5SOCB
EXTSOC2B
POLSEL
ePWM6SOCA
ePWM6SOCB
0
EXTSOC2B
1
ePWM7SOCA
ePWM7SOCB
EXTSOC3A
POLSEL
ePWM8SOCA
ePWM8SOCB
0
1
EXTSOC3A
ePWM9SOCA
ePWM9SOCB
EXTSOC3B
POLSEL
0
1
EXTSOC3B
Figure 4-4. Generation of SOC Pulses to the External ADC Module
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
www.ti.com
Table 4-2. ePWM1-4 Control and Status Registers
SIZE (x16) /
#SHADOW
NAME
TBCTL
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6811
0x6812
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6851
0x6852
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x6891
0x6892
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
0x68D1
0x68D2
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Time Base Control Register
Time Base Status Register
TBSTS
TBPHSHR
TBPHS
TBCTR
TBPRD
CMPCTL
CMPAHR
CMPA
Time Base Phase HRPWM Register
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
TZCTL
Trip Zone Control Register
TZEINT
TZFLG
Trip Zone Enable Interrupt Register
Trip Zone Flag Register
TZCLR
TZFRC
ETSEL
Trip Zone Clear Register
Trip Zone Force Register
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
62
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SPRS516–MARCH 2009
Table 4-3. ePWM5-9 Control and Status Registers
SIZE (x16) /
#SHADOW
NAME
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
DESCRIPTION
TBCTL
0x6900
0x6901
0x6902
0x6903
0x6904
0x6905
0x6907
0x6908
0x6909
0x690A
0x690B
0x690C
0x690D
0x690E
0x690F
0x6910
0x6911
0x6912
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6920
0x6940
0x6941
0x6942
0x6943
0x6944
0x6945
0x6947
0x6948
0x6949
0x694A
0x694B
0x694C
0x694D
0x694E
0x694F
0x6950
0x6951
0x6952
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
0x6960
0x6980
0x6981
0x6982
0x6983
0x6984
0x6985
0x6987
0x6988
0x6989
0x698A
0x698B
0x698C
0x698D
0x698E
0x698F
0x6990
0x6991
0x6992
0x6994
0x6995
0x6996
0x6997
0x6998
0x6999
0x699A
0x699B
0x699C
0x699D
0x699E
0x69A0
0x69C0
0x69C1
0x69C2
0x69C3
0x69C4
0x69C5
0x69C7
0x69C8
0x69C9
0x69CA
0x69CB
0x69CC
0x69CD
0x69CE
0x69CF
0x69D0
0x69D1
0x69D2
0x69D4
0x69D5
0x69D6
0x69D7
0x69D8
0x69D9
0x69DA
0x69DB
0x69DC
0x69DD
0x69DE
0x69E0
0x6600
0x6601
0x6602
0x6603
0x6604
0x6605
0x6607
0x6608
0x6609
0x660A
0x660B
0x660C
0x660D
0x660E
0x660F
0x6610
0x6611
0x6612
0x6614
0x6615
0x6616
0x6617
0x6618
0x6619
0x661A
0x661B
0x661C
0x661D
0x661E
0x6620
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Time Base Control Register
TBSTS
TBPHSHR
TBPHS
TBCTR
TBPRD
CMPCTL
CMPAHR
CMPA
Time Base Status Register
Time Base Phase HRPWM Register
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
TZCTL
Trip Zone Control Register
TZEINT
TZFLG
Trip Zone Enable Interrupt Register
Trip Zone Flag Register
TZCLR
TZFRC
ETSEL
Trip Zone Clear Register
Trip Zone Force Register
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
(1) Registers that are EALLOW protected.
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Delfino Microcontrollers
SPRS516–MARCH 2009
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Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
EPWMxSYNCO
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMxSYNCI
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
TBCTR
CTR_Dir
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
Phase
control
Event
trigger
and
EPWMxINT
TBPHS active (24)
CTR = CMPA
CTR = CMPB
CTR_Dir
EPWMxSOCA
EPWMxSOCB
interrupt
(ET)
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMxAO
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMB
EPWMxBO
EPWMxTZINT
TZ1 to TZ6
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 4-5. ePWM Submodules Showing Critical Internal Signal Interconnections
4.4 High-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can
be achieved using conventionally derived digital PWM methods. The key points for the HRPWM module
are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
Typically used when effective PWM resolution falls below ~ 9-10 bits. This occurs at PWM frequencies
greater than ~500 kHz when using a CPU/System clock of 300 MHz or ~375 kHz when using a
CPU/system clock of 200 MHz.
•
•
This capability can be utilized in both duty cycle and phase-shift control methods.
Finer time granularity control or edge positioning is controlled via extensions to the Compare A and
Phase registers of the ePWM module.
•
HRPWM capabilities are offered only on the A signal path of an ePWM module (i.e., on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
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4.5 Enhanced CAP Modules (eCAP1/2/3/4/5/6)
The device contains up to six enhanced capture (eCAP) modules. Figure 4-6 shows a functional block
diagram of a module.
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
control
Figure 4-6. eCAP Functional Block Diagram
The eCAP modules are clocked at the SYSCLKOUT rate.
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Delfino Microcontrollers
SPRS516–MARCH 2009
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The clock enable bits (ECAP1/2/3/4/5/6ENCLK) in the PCLKCR1 register are used to turn off the eCAP
modules individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK,
ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and ECAP6ENCLK are set to low, indicating that the
peripheral clock is off.
Table 4-4. eCAP Control and Status Registers
SIZE
(x16)
NAME
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
DESCRIPTION
Time-Stamp Counter
TSCTR
0x6A00
0x6A02
0x6A20
0x6A22
0x6A40
0x6A42
0x6A60
0x6A62
0x6A80
0x6A82
0x6AA0
0x6AA2
2
2
CTRPHS
Counter Phase Offset Value
Register
CAP1
CAP2
0x6A04
0x6A06
0x6A08
0x6A0A
0x6A24
0x6A26
0x6A28
0x6A2A
0x6A44
0x6A46
0x6A48
0x6A4A
0x6A64
0x6A66
0x6A68
0x6A6A
0x6A84
0x6A86
0x6A88
0x6A8A
0x6AA4
0x6AA6
0x6AA8
0x6AAA
2
2
2
2
8
Capture 1 Register
Capture 2 Register
Capture 3 Register
Capture 4 Register
Reserved
CAP3
CAP4
Reserved
0x6A0C-
0x6A12
0x6A2C-
0x6A32
0x6A4C-
0x6A52
0x6A6C-
0x6A72
0x6A8C- 0x6AAC-
0x6A92
0x6A94
0x6A95
0x6A96
0x6A97
0x6A98
0x6A99
0x6AB2
0x6AB4
0x6AB5
0x6AB6
0x6AB7
0x6AB8
0x6AB9
ECCTL1
ECCTL2
ECEINT
ECFLG
0x6A14
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A34
0x6A35
0x6A36
0x6A37
0x6A38
0x6A39
0x6A54
0x6A55
0x6A56
0x6A57
0x6A58
0x6A59
0x6A74
0x6A75
0x6A76
0x6A77
0x6A78
0x6A79
1
1
1
1
1
1
6
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Reserved
ECCLR
ECFRC
Reserved
0x6A1A-
0x6A1F
0x6A3A-
0x6A3F
0x6A5A-
0x6A5F
0x6A7A-
0x6A7F
0x6A9A-
0x6A9F
0x6ABA-
0x6ABF
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4.6 Enhanced QEP Modules (eQEP1/2/3)
The device contains up to three enhanced quadrature encoder (eQEP) modules with 32-bit resolution.
System
control registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
QCLK
QDIR
QI
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
PIE
Position counter/
control unit
(PCCU)
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 4-7. eQEP Functional Block Diagram
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Table 4-5. eQEP Control and Status Registers
eQEPx
SIZE(x16)/
#SHADOW
eQEP1
ADDRESS
eQEP2
ADDRESS
eQEP3
ADDRESS
NAME
REGISTER DESCRIPTION
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B40
0x6B42
0x6B44
0x6B46
0x6B48
0x6B4A
0x6B4C
0x6B4E
0x6B50
0x6B52
0x6B53
0x6B54
0x6B55
0x6B56
0x6B57
0x6B80
0x6B82
0x6B84
0x6B86
0x6B88
0x6B8A
0x6B8C
0x6B8E
0x6B90
0x6B92
0x6B93
0x6B94
0x6B95
0x6B96
0x6B97
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
eQEP Position Counter
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
QCAPCTL
QPOSCTL
eQEP Capture Control Register
eQEP Position-compare Control
Register
QEINT
0x6B18
0x6B19
0x6B58
0x6B59
0x6B5A
0x6B5B
0x6B5C
0x6B5D
0x6B5E
0x6B5F
0x6B60
0x6B98
0x6B99
0x6B9A
0x6B9B
0x6B9C
0x6B9D
0x6B9E
0x6B9F
0x6BA0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
31/0
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
0x6B1A
QFRC
0x6B1B
QEPSTS
QCTMR
QCPRD
QCTMRLAT
QCPRDLAT
Reserved
0x6B1C
0x6B1D
eQEP Capture Timer
0x6B1E
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
0x6B1F
0x6B20
0x6B21- 0x6B3F
0x6B61- 0x6B7F 0x6BBA1 - 0x6BBF
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4.6.1 External ADC Interface
The external ADC interface operation is configured, controlled, and monitored by the External SoC
Configuration Register (EXTSOCCFG) at address 0x702E.
EXTSOC1A
POLSEL
0
EXTSOC1A
1
ePWM1SOCA
ePWM1
EXTSOC1B
ePWM1SOCB
POLSEL
ePWM2SOCA
ePWM2
ePWM2SOCB
0
1
EXTSOC1B
ePWM3SOCA
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
EXTSOC2A
POLSEL
ePWM3SOCB
ePWM4SOCA
0
1
ePWM4SOCB
EXTSOC2A
ePWM5SOCA
ePWM5SOCB
EXTSOC2B
POLSEL
ePWM6SOCA
ePWM6SOCB
0
EXTSOC2B
1
ePWM7SOCA
ePWM7SOCB
EXTSOC3A
POLSEL
ePWM8SOCA
ePWM8SOCB
0
1
EXTSOC3A
ePWM9SOCA
ePWM9SOCB
EXTSOC3B
POLSEL
0
1
EXTSOC3B
Figure 4-8. External ADC Interface
Table 4-6. External ADC Interface Registers
NAME
DESCRIPTION
ADDRESS
EXTSOCCFG
External SoC Configuration Register
0x00 702E
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4.7 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
•
Compatible to McBSP in TMS320C54x™/TMS320C55x™ DSP devices
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially
connected A/D and D/A devices
•
•
Works with SPI-compatible devices
The following application interfaces can be supported on the McBSP:
–
–
–
–
–
T1/E1 framers
IOM-2 compliant devices
AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
IIS-compliant devices
SPI
•
McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O
buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less
than the I/O buffer speed limit.
NOTE
See Section 6 for maximum I/O pin toggling speed.
Figure 4-9 shows the block diagram of the McBSP module.
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TX
Interrupt
MXINT
Peripheral Write Bus
CPU
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
16
DXR1 Transmit Buffer
16
LSPCLK
MFSXx
MCLKXx
Compand Logic
XSR2
XSR1
MDXx
MDRx
CPU
DMA Bus
RSR1
16
RSR2
16
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
16
16
Interrupt Select Logic
RX
RX Interrupt Logic
Interrupt
MRINT
CPU
Peripheral Read Bus
To CPU
Figure 4-9. McBSP Module
Table 4-7 provides a summary of the McBSP registers.
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Table 4-7. McBSP Register Summary
McBSP-A
ADDRESS
McBSP-B
ADDRESS
NAME
TYPE
RESET VALUE
DESCRIPTION
Data Registers, Receive, Transmit
DRR2
0x5000
0x5001
0x5002
0x5003
0x5040
0x5041
0x5042
0x5043
R
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 2
McBSP Data Receive Register 1
McBSP Data Transmit Register 2
McBSP Data Transmit Register 1
DRR1
DXR2
DXR1
W
W
McBSP Control Registers
SPCR2
SPCR1
RCR2
0x5004
0x5005
0x5006
0x5007
0x5008
0x5009
0x500A
0x500B
0x5044
0x5045
0x5046
0x5047
0x5048
0x5049
0x504A
0x504B
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RCR1
XCR2
XCR1
SRGR2
SRGR1
Multichannel Control Registers
MCR2
0x500C
0x500D
0x500E
0x500F
0x5010
0x5011
0x5012
0x5013
0x5014
0x5015
0x5016
0x5017
0x5018
0x5019
0x501A
0x501B
0x501C
0x501D
0x501E
0x5023
0x5024
0x504C
0x504D
0x504E
0x504F
0x5050
0x5051
0x5052
0x5053
0x5054
0x5055
0x5056
0x5057
0x5058
0x5059
0x505A
0x505B
0x505C
0x505D
0x505E
0x5063
0x5064
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
MCR1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
MFFINT
MFFST
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
McBSP Interrupt Enable Register
McBSP Pin Status Register
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4.8 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
–
–
–
–
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
•
•
•
•
•
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
•
Self-test mode
–
Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 300 MHz, the smallest bit rate possible is 11.719 kbps.
For a SYSCLKOUT of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
The CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.
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Address
Controls
Data
32
eCAN0INT
eCAN1INT
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and Message
Objects Control
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 × 32-Bit Words
32
32
32
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
eCAN Protocol Kernel
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 4-10. eCAN Block Diagram and Interface Circuit
Table 4-8. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230Q
SN65HVD231Q
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Sleep
Adjustable
Adjustable
None
Yes
Yes
–
–
–
-40°C to 125°C
-40°C to 125°C
-40°C to 125°C
-40°C to 125°C
None
None
None
Standby
Adjustable
Diagnostic
Loopback
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Standby and Sleep
Standby
Adjustable
Adjustable
None
None
–
-40°C to 125°C
-40°C to 125°C
Autobaud
Loopback
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eCAN-A Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-A Memory (512 Bytes)
Control and Status Registers
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6000h
603Fh
6040h
607Fh
6080h
60BFh
60C0h
60FFh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN-A Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6100h−6107h
6108h−610Fh
6110h−6117h
6118h−611Fh
6120h−6127h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
61E0h−61E7h
61E8h−61EFh
61F0h−61F7h
61F8h−61FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
61E8h−61E9h
61EAh−61EBh
61ECh−61EDh
61EEh−61EFh
Figure 4-11. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS,
MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock
should be enabled for this.
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eCAN-B Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
eCAN-B Memory (512 Bytes)
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
6200h
Control and Status Registers
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
Bit-Timing Configuration − CANBTC
Error and Status − CANES
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
(32 × 32-Bit RAM)
eCAN-B Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
6300h−6307h
6308h−630Fh
6310h−6317h
6318h−631Fh
6320h−6327h
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
63E0h−63E7h
63E8h−63EFh
63F0h−63F7h
63F8h−63FFh
Reserved
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
63E8h−63E9h
63EAh−63EBh
63ECh−63EDh
63EEh−63EFh
Figure 4-12. eCAN-B Memory Map
The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
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Table 4-9. CAN Register Map(1)
eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
REGISTER NAME
DESCRIPTION
CANME
CANMD
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
0x6200
0x6202
0x6204
0x6206
0x6208
0x620A
0x620C
0x620E
0x6210
0x6212
0x6214
0x6216
0x6218
0x621A
0x621C
0x621E
0x6220
0x6222
0x6224
0x6226
0x6228
0x622A
0x622C
0x622E
0x6230
0x6232
1
Mailbox enable
1
Mailbox direction
CANTRS
CANTRR
CANTA
1
Transmit request set
Transmit request reset
1
1
Transmission acknowledge
Abort acknowledge
CANAA
1
CANRMP
CANRML
CANRFP
CANGAM
CANMC
1
Receive message pending
Receive message lost
1
1
Remote frame pending
Global acceptance mask
Master control
1
1
CANBTC
CANES
1
Bit-timing configuration
Error and status
1
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
1
Transmit error counter
Receive error counter
1
1
Global interrupt flag 0
1
Global interrupt mask
1
Global interrupt flag 1
1
Mailbox interrupt mask
Mailbox interrupt level
1
1
Overwrite protection control
TX I/O control
1
1
RX I/O control
1
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
1
1
(1) These registers are mapped to Peripheral Frame 1.
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4.9 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
The devices include three serial communications interface (SCI) modules. The SCI modules support
digital communications between the CPU and other asynchronous peripherals that use the standard
non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the
full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity,
overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit
baud-select register.
Features of each SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
Baud rate programmable to 64K different rates:
–
LSPCLK
(BRR ) 1) * 8
Baud rate =
when BRR ≠ 0
when BRR = 0
LSPCLK
16
Baud rate =
NOTE
See Section 6 for maximum I/O pin toggling speed.
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from one to eight bits
Optional even/odd/no parity bit
One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (non-return-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
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The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and
Table 4-12.
Table 4-10. SCI-A Registers(1)
NAME
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
SCICCRA
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-11. SCI-B Registers(1) (2)
NAME
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
SCICCRB
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 4-12. SCI-C Registers(1) (2)
NAME
ADDRESS
0x7770
0x7771
0x7772
0x7773
0x7774
SIZE (x16)
DESCRIPTION
SCI-C Communications Control Register
SCI-C Control Register 1
SCICCRC
1
1
1
1
1
SCICTL1C
SCIHBAUDC
SCILBAUDC
SCICTL2C
SCI-C Baud Register, High Bits
SCI-C Baud Register, Low Bits
SCI-C Control Register 2
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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Table 4-12. SCI-C Registers (continued)
NAME
ADDRESS
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
SIZE (x16)
DESCRIPTION
SCI-C Receive Status Register
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC(2)
SCIFFRXC(2)
SCIFFCTC(2)
SCIPRC
1
1
1
1
1
1
1
1
SCI-C Receive Emulation Data Buffer Register
SCI-C Receive Data Buffer Register
SCI-C Transmit Data Buffer Register
SCI-C FIFO Transmit Register
SCI-C FIFO Receive Register
SCI-C FIFO Control Register
SCI-C Priority Control Register
Figure 4-13 shows the SCI module block diagram.
SCICTL1.1
SCITXD
Frame Format and Mode
SCITXD
TXSHF
Register
TXENA
Parity
Even/Odd Enable
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TXRDY
TX INT ENA
SCICTL2.0
Transmitter-Data
Buffer Register
SCICTL2.7
TXWAKE
SCICTL1.3
1
8
TX FIFO _0
TX FIFO
Interrupts
TXINT
TX Interrupt
Logic
TX FIFO _1
-----
To CPU
TX FIFO _15
SCI TX Interrupt select logic
SCITXBUF.7-0
WUT
TX FIFO registers
SCIFFENA
AutoBaud Detect logic
SCIFFTX.14
SCIHBAUD. 15 - 8
SCIRXD
RXSHF
Register
Baud Rate
MSbyte
Register
SCIRXD
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
Receive Data
Buffer register
SCIRXBUF.7-0
RXRDY
RX/BK INT ENA
SCIRXST.6
8
RX FIFO _15
BRKDT
SCIRXST.5
-----
RX FIFO
Interrupts
RX FIFO_1
RX FIFO _0
RXINT
RX Interrupt
Logic
SCIRXBUF.7-0
RX FIFO registers
To CPU
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCICTL1.6
SCI RX Interrupt select logic
Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram
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4.10 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
The device includes the four-pin serial peripheral interface (SPI) module. Two SPI modules (SPI-A and
SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the MCU controller and external
peripherals or another processor. Typical applications include external I/O or peripheral expansion through
devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by
the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to 127
when SPIBRR = 0,1, 2
(SPIBRR ) 1)
LSPCLK
Baud rate =
4
NOTE
See Section 6 for maximum I/O pin toggling speed.
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7-0), and the upper
byte (15-8) is read as zeros. Writing to the upper byte has no effect.
Enhanced feature:
•
•
16-level transmit/receive FIFO
Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 4-13 and Table 4-14.
Table 4-13. SPI-A Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (X16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Baud Rate Register
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 4-14. SPI-D Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7780
0x7781
0x7782
0x7784
0x7786
0x7787
0x7788
0x7789
0x778A
0x778B
0x778C
0x778F
SIZE (X16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-D Configuration Control Register
SPI-D Operation Control Register
SPI-D Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-D Baud Rate Register
SPI-D Receive Emulation Buffer Register
SPI-D Serial Input Buffer Register
SPI-D Serial Output Buffer Register
SPI-D Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-D FIFO Transmit Register
SPI-D FIFO Receive Register
SPI-D FIFO Control Register
SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 4-14 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX FIFO _15
RX Interrupt
Logic
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPISTS.6
SPITXBUF
Buffer Register
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 − 0
S
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 4-14. SPI Module Block Diagram (Slave Mode)
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4.11 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 4-15 shows how the I2C peripheral module interfaces
within the device.
System Control
C28X CPU
Block
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
SDAA
Data[16]
GPIO
MUX
2
I C−A
Addr[16]
I2CINT1A
SCLA
PIE
Block
I2CINT2A
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 4-15. I2C Peripheral Module Interfaces
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (Philips Fast-mode rate)
•
•
One 16-word receive FIFO and one 16-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
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–
–
–
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
The registers in Table 4-15 configure and control the I2C port operation.
Table 4-15. I2C-A Registers
NAME
I2COAR
I2CIER
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
DESCRIPTION
I2C own address register
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
-
4.12 GPIO MUX
On the 2834x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a
single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block
diagram per pin is shown in Figure 4-16. Because of the open drain capabilities of the I2C pins, the GPIO
MUX block diagram for these pins differ. See the TMS320x2834x Delfino System Control and Interrupts
Reference Guide (literature number SPRUFN1) for details.
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and
GPxQSELn registers occurs to when the action is valid.
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GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
GPIOXINT7SEL
GPIOXNMISEL
External Interrupt
MUX
Low Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Peripheral 2 Input
Input
Internal
Pullup
Qualification
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
TMS320x2834x Delfino System Control and Interrupts Reference Guide (literature number SPRUFN1) for pin-specific
variations.
Figure 4-16. GPIO MUX Block Diagram
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The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-16 shows the
GPIO register mapping.
Table 4-16. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control Register (GPIO0 to 31)
SIZE (x16)
DESCRIPTION
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
2
2
2
2
18
0x6F82
0x6F84
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
0x6F86
0x6F88
GPIO A MUX 2 Register (GPIO16 to 31)
0x6F8A
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAPUD
0x6F8C
Reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F8E – 0x6F8F
0x6F90
GPIO B Control Register (GPIO32 to 35)
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
Reserved
0x6F92
0x6F94
0x6F96
GPIO B MUX 1 Register (GPIO32 to 35)
GPIO B MUX 2 Register (GPIO48 to 63)
GPIO B Direction Register (GPIO32 to 35)
GPIO B Pull Up Disable Register (GPIO32 to 35)
0x6F98
0x6F9A
GPBPUD
0x6F9C
Reserved
GPCMUX1
GPCMUX2
GPCDIR
0x6F9E – 0x6FA5
0x6FA6
GPIO C MUX1 Register (GPIO64 to 79)
GPIO C MUX2 Register (GPIO80 to 87)
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pull Up Disable Register (GPIO64 to 87)
0x6FA8
0x6FAA
GPCPUD
Reserved
0x6FAC
0x6FAE – 0x6FBF
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
2
2
2
2
2
2
2
2
2
2
2
2
8
GPIO A Data Register (GPIO0 to 31)
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 35)
GPACLEAR
GPATOGGLE
GPBDAT
0x6FC4
0x6FC6
0x6FC8
GPBSET
0x6FCA
GPIO B Data Set Register (GPIO32 to 35)
GPIO B Data Clear Register (GPIO32 to 35)
GPIOB Data Toggle Register (GPIO32 to 35)
GPIO C Data Register (GPIO64 to 87)
GPBCLEAR
GPBTOGGLE
GPCDAT
0x6FCC
0x6FCE
0x6FD0
GPCSET
0x6FD2
GPIO C Data Set Register (GPIO64 to 87)
GPIO C Data Clear Register (GPIO64 to 87)
GPIO C Data Toggle Register (GPIO64 to 87)
GPCCLEAR
GPCTOGGLE
Reserved
0x6FD4
0x6FD6
0x6FD8 0x6FDF
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
GPIOXINT3SEL
GPIOXINT4SEL
GPIOXINT5SEL
0x6FE0
0x6FE1
0x6FE2
0x6FE3
0x6FE4
0x6FE5
1
1
1
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO32 to 63)
XINT4 GPIO Input Select Register (GPIO32 to 63)
XINT5 GPIO Input Select Register (GPIO32 to 63)
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Table 4-16. GPIO Registers (continued)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
XINT6 GPIO Input Select Register (GPIO32 to 63)
XINT7 GPIO Input Select Register (GPIO32 to 63)
LPM GPIO Select Register (GPIO0 to 31)
GPIOXINT6SEL
GPIOINT7SEL
GPIOLPMSEL
Reserved
0x6FE6
0x6FE7
1
1
0x6FE8
2
0x6FEA – 0x6FFF
22
Table 4-17. GPIO-A Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPADIR
GPADAT
GPASET
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1=0,0
PER1
GPAMUX1 = 0, 1
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
GPACLR
GPATOGGLE
QUALPRD0
0
1
1, 0
GPIO0 (I/O)
GPIO1 (I/O)
GPIO2 (I/O)
GPIO3 (I/O)
GPIO4 (I/O)
GPIO5 (I/O)
GPIO6 (I/O)
GPIO7 (I/O)
GPIO8 (I/O)
GPIO9 (I/O)
GPIO10 (I/O)
GPIO11 (I/O)
GPIO12 (I/O)
GPIO13 (I/O)
GPIO14 (I/O)
GPIO15 (I/O)
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
Reserved
ECAP6 (I/O)
Reserved
Reserved
MFSRB (I/O)
Reserved
3, 2
2
5, 4
3
7, 6
ECAP5 (I/O)
Reserved
MCLKRB (I/O)
Reserved
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
MFSRA (I/O)
EPWMSYNCI (I)
MCLKRA (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
ADCSOCAO (O)
ECAP3 (I/O)
ADCSOCBO (O)
ECAP4 (I/O)
MDXB (O)
6
7
QUALPRD1
8
9
10
11
12
13
14
15
TZ2 (I)
MDRB (I)
TZ3 (I)/XHOLD (I)
TZ4 (I)/XHOLDA (O)
MCLKXB (I/O)
MFSXB (I/O)
GPAMUX2
GPAQSEL2
GPAMUX2 =0, 0
GPAMUX2 = 0, 1
GPAMUX2 = 1, 0
GPAMUX2 = 1, 1
QUALPRD2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1, 0
GPIO16 (I/O)
GPIO17 (I/O)
GPIO18 (I/O)
GPIO19 (I/O)
GPIO20 (I/O)
GPIO21 (I/O)
GPIO22 (I/O)
GPIO23 (I/O)
GPIO24 (I/O)
GPIO25 (I/O)
GPIO26 (I/O)
GPIO27 (I/O)
GPIO28 (I/O)
GPIO29 (I/O)
GPIO30 (I/O)
GPIO31 (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXA (O)
TZ5 (I)
3, 2
TZ6 (I)
5, 4
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXB (O)
7, 6
9, 8
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
EQEP1B (I)
MDRA (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
MCLKXA (I/O)
MFSXA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
QUALPRD3
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
XZCS6 (O)
XA19 (O)
XA18 (O)
XA17 (O)
CANTXA (O)
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Table 4-18. GPIO-B Mux Peripheral Selection Matrix
REGISTER BITS
GPBDIR
PERIPHERAL SELECTION
GPBDAT
GPBSET
GPBCLR
GPBMUX1
GPBQSEL1
GPIOx
GPBMUX1=0, 0
PER1
GPBMUX1 = 0, 1
PER2
GPBMUX1 = 1, 0
PER3
GPBMUX1 = 1, 1
GPBTOGGLE
QUALPRD0
0
1
1, 0
GPIO32 (I/O)
GPIO33 (I/O)
GPIO34 (I/O)
GPIO35 (I/O)
GPIO36 (I/O)
GPIO37 (I/O)
GPIO38 (I/O)
GPIO39 (I/O)
GPIO40 (I/O)
GPIO41 (I/O)
GPIO42 (I/O)
GPIO43 (I/O)
GPIO44 (I/O)
GPIO45 (I/O)
GPIO46 (I/O)
GPIO47 (I/O)
SDAA (I/OC)(1)
SCLA (I/OC)(1)
ECAP1 (I/O)
SCITXDA (O)
SCIRXDA (I)
ECAP2 (I/O)
EPWMSYNCI (I)
ADCSOCAO (O)
ADCSOCBO (O)
3, 2
EPWMSYNCO (O)
2
5, 4
XREADY (I)
3
7, 6
XR/W (O)
XZCS0 (O)
XZCS7 (O)
XWE0 (O)
XA16 (O)
XA0 (O)
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
6
7
QUALPRD1
8
9
XA1 (O)
10
11
12
13
14
15
XA2 (O)
Reserved
XA3 (O)
XA4 (O)
XA5 (O)
XA6 (O)
XA7 (O)
GPBMUX2
GPBQSEL2
GPBMUX2 =0, 0
GPBMUX2 = 0, 1
GPBMUX2 = 1, 0
GPBMUX2 = 1, 1
QUALPRD2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1, 0
GPIO48 (I/O)
GPIO49 (I/O)
GPIO50 (I/O)
GPIO51 (I/O)
GPIO52 (I/O)
GPIO53 (I/O)
GPIO54 (I/O)
GPIO55 (I/O)
GPIO56 (I/O)
GPIO57 (I/O)
GPIO58 (I/O)
GPIO59 (I/O)
GPIO60 (I/O)
GPIO61 (I/O)
GPIO62 (I/O)
GPIO63 (I/O)
ECAP5 (I/O)
ECAP6 (I/O)
XD31 (I/O)
XD30 (I/O)
XD29 (I/O)
XD28 (I/O)
XD27 (I/O)
XD26 (I/O)
XD25 (I/O)
XD24 (I/O)
XD23 (I/O)
XD22 (I/O)
XD21 (I/O)
XD20 (I/O)
XD19 (I/O)
XD18 (I/O)
XD17 (I/O)
XD16 (I/O)
SPISIMOD (I/O)
SPISOMID (I/O)
SPICLKD (I/O)
SPISTED (I/O)
Reserved
3, 2
5, 4
EQEP1A (I)
7, 6
EQEP1B (I)
9, 8
EQEP1S (I/O)
EQEP1I (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
Reserved
EQEP3A (I)
EQEP3B (I)
QUALPRD3
EQEP3S (I/O)
EQEP3I (I/O)
EPWM7A (O)
EPWM7B (O)
EPWM8A (O)
EPWM8B (O)
EPWM9A (O)
EPWM9B (O)
(1) Open drain
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Table 4-19. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPCDIR
GPCDAT
GPCSET
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
GPCMUX1
GPCCLR
GPCTOGGLE
no qual
0
1, 0
3, 2
GPIO64 (I/O)
GPIO65 (I/O)
GPIO66 (I/O)
GPIO67 (I/O)
GPIO68 (I/O)
GPIO69 (I/O)
GPIO70 (I/O)
GPIO71 (I/O)
GPIO72 (I/O)
GPIO73 (I/O)
GPIO74 (I/O)
GPIO75 (I/O)
GPIO76 (I/O)
GPIO77 (I/O)
GPIO78 (I/O)
GPIO79 (I/O)
GPCMUX2 = 0, 0 or 0, 1
GPIO80 (I/O)
GPIO81 (I/O)
GPIO82 (I/O)
GPIO83 (I/O)
GPIO84 (I/O)
GPIO85 (I/O)
GPIO86 (I/O)
GPIO87 (I/O)
XD15 (I/O)
XD14 (I/O)
XD13 (I/O)
XD12 (I/O)
XD11 (I/O)
XD10 (I/O)
XD9 (I/O)
1
2
5, 4
3
7, 6
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPCMUX2
1, 0
6
7
XD8 (I/O)
no qual
8
XD7 (I/O)
9
XD6 (I/O)
10
11
12
13
14
15
XD5 (I/O)
XD4 (I/O)
XD3 (I/O)
XD2 (I/O)
XD1 (I/O)
XD0 (I/O)
GPCMUX2 = 1, 0 or 1, 1
XA8 (O)
no qual
16
17
18
19
20
21
22
23
3, 2
XA9 (O)
5, 4
XA10 (O)
7, 6
XA11 (O)
9, 8
XA12 (O)
11, 10
13, 12
15, 14
XA13 (O)
XA14 (O)
XA15 (O)
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
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Time between samples
GPyCTRL Reg
Input Signal
Qualification
GPIOx
SYNC
Qualified By 3
or 6 Samples
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 4-17. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).
No Synchronization (GPxQSEL1/2=1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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4.13 External Interface (XINTF)
This section gives a top-level view of the external interface (XINTF) that is implemented on the C2834x
devices.
The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into
three fixed zones shown in Figure 4-18.
Data Space
Prog Space
0x0000−0000
XD(31:0)
XA(19:0)
0x0000−4000
XINTF Zone 0
XZCS0
(8K x 16)
0x0000−5000
0x0010−0000
0x0020−0000
0x0030−0000
XZCS6
XINTF Zone 6
(1M x 16)
XZCS7
XWE1
XINTF Zone 7
(1M x 16)
XWE0
XRD
XR/W
XREADY
XHOLD
XHOLDA
XCLKOUT
Figure 4-18. External Interface Block Diagram
Figure 4-19 and Figure 4-20 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how
the functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 4-20 defines
XINTF configuration and control registers.
XINTF
External
XREADY
16-bits
wait-state
XCLKOUT
generator
CS
XZCS0/6/7
XA(19:0)
XWE1
A(19:0)
X
OE
WE
XRD
XWE0
D(15:0)
XD(15:0)
Figure 4-19. Typical 16-bit Data Bus XINTF Connections
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XINTF
External
wait-state
generator
XREADY
Low 16-bits
XCLKOUT
CS
X
XA(0)
A(18:0)
OE
XA(19:1)
XRD
WE
XWE0
XD(15:0)
D(15:0)
High 16-bits
A(18:0)
CS
OE
WE
XZCS0/6/7
XWE1
D(31:16)
XD(31:16)
Figure 4-20. Typical 32-bit Data Bus XINTF Connections
Table 4-20. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
0x00–0B20
0x00–0B2C
0x00–0B2E
0x00–0B34
0x00–0B38
0x00–0B3A
0x00 083D
SIZE (x16)
DESCRIPTION
XINTF Timing Register, Zone 0
XTIMING0
XTIMING6(1)
XTIMING7
XINTCNF2(2)
XBANK
2
2
2
2
1
1
1
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XREVISION
XRESET
XINTF Reset Register
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
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5
Device Support
Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs,
including tools to evaluate the performance of the processors, generate code, develop algorithm
implementations, and fully integrate and debug software and hardware modules.
The following products support development of 2834x-based applications:
Software Development Tools
•
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
–
C/C++ Compiler
Code generation tools
Assembler/Linker
Cycle Accurate Simulator
•
•
Application algorithms
Sample applications code
Hardware Development Tools
•
•
•
•
•
Development board
Evaluation modules
JTAG-based emulators - SPI515, XDS510PP, XDS510PP Plus, XDS510USB
Universal 5-V dc power supply
Documentation and cables
5.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320™ commercial family member has one of three
prefixes: TMX, TMP, or TMS (e.g., TMS320C28345). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary
stages of product development from engineering prototypes (TMX/TMDX) through fully qualified
production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZFE) and temperature range (for example, T). Figure 5-1 provides a legend
for reading the complete device name for any family member.
TMS 320 C 28346
ZFE
T
PREFIX
TEMPERATURE RANGE
experimental device
prototype device
qualified device
TMX =
TMP =
TMS =
T = −40°C to 105°C
PACKAGE TYPE
ZFE = 256-ball Plastic BGA (lead-free)
ZHH = 179-ball Microstar BGA (lead-free)
BGA = Ball Grid Array
DEVICE FAMILY
320 = TMS320 Device Family
DEVICE
28346
28345
28344
28343
28342
28341
TECHNOLOGY
C = Non-Flash (1.1/1.2-V Core/3.3-V I/O)
Figure 5-1. Example of C2834x Device Nomenclature
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5.2 Documentation Support
Extensive documentation supports all of the TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets and data manuals, with design specifications; and hardware and software applications.
Table 5-1 shows the peripheral reference guides appropriate for use with the devices in this data manual.
See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) for more information on types
of peripherals.
Table 5-1. TMS320x2834x Delfino Peripheral Selection Guide
28346, 28345,
28344, 28343,
28342, 28341
LITERATURE
NUMBER
PERIPHERAL GUIDE
TYPE(1)
TMS320x2834x Delfino System Control and Interrupts
SPRUFN1
SPRUFN4
SPRUEU4
SPRUG80
SPRUG75
SPRUG73
SPRUFN5
SPRUG74
SPRUFZ6
SPRUG79
SPRUG76
SPRUG77
SPRUG78
-
X
X
X
X
X
X
X
X
X
X
X
X
X
TMS320x2834x Delfino External Interface (XINTF)
1
0
1
0
0
-
TMS320x2834x Delfino Enhanced Controller Area Network (eCAN)
TMS320x2834x Delfino Multichannel Buffered Serial Port (McBSP)
TMS320x2834x Delfino Serial Communications Interface (SCI)
TMS320x2834x Delfino Serial Peripheral Interface (SPI)
TMS320x2834x Delfino Boot ROM
TMS320x2834x Delfino Enhanced Quadrature Encoder Pulse (eQEP)
TMS320x2834x Delfino Enhanced Pulse Width Modulator Module (ePWM)
TMS320x2834x Delfino Enhanced Capture (eCAP) Module
TMS320x2834x Delfino Inter-Integrated Circuit (I2C)
0
0
0
0
0
0
TMS320x2834x Delfino High-Resolution Pulse-Width Modulator (HRPWM)
TMS320x2834x Delfino Direct Memory Access (DMA)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
TMS320x28xx, 28xxx DSP Peripheral Reference Guide (SPRU566) and in the peripheral reference guides.
Useful reference documentation includes:
CPU User's Guides
SPRU430
TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central
processing unit (CPU) and the assembly language instructions of the TMS320C28x
fixed-point digital signal processors (DSPs). It also describes emulation features available on
these DSPs.
SPRUEO2 TMS320C28x Floating Point Unit and Instruction Set Reference Guide describes the
floating-point unit and includes the instructions for the FPU.
Peripheral Guides
SPRU566
TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference
guides of the 28x digital signal processors (DSPs).
SPRUFN1 TMS320x2834x Delfino System Control and Interrupts Reference Guide. This document
describes the various interrupts and system control features of the x2834x microcontroller
(MCUs).
SPRUFN4 TMS320x2834x Delfino External Interface (XINTF) Reference Guide describes the XINTF,
which is a nonmultiplexed asynchronous bus, as it is used on the 2834x device.
SPRUFN5 TMS320x2834x Delfino Boot ROM Reference Guide describes the purpose and features of
the bootloader (factory-programmed boot-loading software) and provides examples of code.
It also describes other contents of the device on-chip boot ROM and identifies where all of
the information is located within that memory.
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SPRUG80 TMS320x2834x Delfino Multichannel Buffered Serial Port (McBSP) Reference Guide.
This document describes the McBSP available on the x2834x devices. The McBSPs allow
direct interface between a microcontroller (MCU) and other devices in a system.
SPRUG78 TMS320x2834x Delfino Direct Memory Access (DMA) Reference Guide describes the DMA
on the 2834x device.
SPRUFZ6 TMS320x2834x Delfino Enhanced Pulse Width Modulator (ePWM) Module Reference Guide
describes the main areas of the enhanced pulse width modulator that include digital motor
control, switch mode power supply control, UPS (uninterruptible power supplies), and other
forms of power conversion.
SPRUG77 TMS320x2834x Delfino High-Resolution Pulse Width Modulator (HRPWM) Reference Guide
describes the operation of the high-resolution extension to the pulse width modulator
(HRPWM).
SPRUG79 TMS320x2834x Delfino Enhanced Capture (eCAP) Module Reference Guide describes the
enhanced capture module. It includes the module description and registers.
SPRUG74 TMS320x2834x Delfino Enhanced Quadrature Encoder Pulse (eQEP) Reference Guide
describes the eQEP module, which is used for interfacing with a linear or rotary incremental
encoder to get position, direction, and speed information from a rotating machine in high
performance motion and position control systems. It includes the module description and
registers.
SPRUEU4 TMS320x2834x Delfino Enhanced Controller Area Network (eCAN) Reference Guide.
This document describes the eCAN that uses established protocol to communicate serially
with other controllers in electrically noisy environments.
SPRUG75 TMS320x2834x Delfino Serial Communication Interface (SCI) Reference Guide. This
document describes the SCI, which is a two-wire asynchronous serial port, commonly known
as a UART. The SCI modules support digital communications between the CPU and other
asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
SPRUG73 TMS320x2834x Delfino Serial Peripheral Interface (SPI) Reference Guide. This
document describes the SPI - a high-speed synchronous serial input/output (I/O) port - that
allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and
out of the device at a programmed bit-transfer rate.
SPRUG76 TMS320x2834x Delfino Inter-Integrated Circuit (I2C) Reference Guide. This document
describes the features and operation of the inter-integrated circuit (I2C) module.
Tools Guides
SPRU513
TMS320C28x Assembly Language Tools User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the
TMS320C28x device.
SPRU514
SPRU608
SPRU625
TMS320C28x Optimizing C Compiler User's Guide describes the TMS320C28x™ C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320
DSP assembly language source code for the TMS320C28x device.
The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,
available within the Code Composer Studio for TMS320C2000 IDE, that simulates the
instruction set of the C28x™ core.
TMS320C28x DSP/BIOS Application Programming Interface (API) Reference Guide
describes development using DSP/BIOS.
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Application Reports and Software
Key Links Include:
1. C2000 Get Started - www.ti.com/c2000getstarted
2. C2000 Digital Motor Control Software Library - www.ti.com/c2000appsw
3. C2000 Digital Power Supply Software Library - www.ti.com/dpslib
4. DSP Power Management Reference Designs - www.ti.com/dsppower
SPRAAQ7 TMS320x281x to TMS320x2833x or 2823x Migration Overview
describes how to migrate from the 281x device design to 2833x or 2823x designs.
SPRAAQ8 TMS320x280x to TMS320x2833x or 2823x Migration Overview
describes how to migrate from a 280x device design to 2833x or 2823x designs.
SPRAAN9 C28x FPU Primer
provides an overview of the floating-point unit (FPU) in the TMS320F28335,
TMS320F28334, and TMS320F28332 Digital Signal Controller (DSC) devices.
SPRAAM0 Getting Started With TMS320C28x™ Digital Signal Controllers is organized by development
flow and functional areas to make your design effort as seamless as possible. Tips on
getting started with C28x™ DSP software and hardware development are provided to aid in
your initial design and debug efforts. Each section includes pointers to valuable information
including technical documentation, software, and tools for use in each phase of design.
SPRA958
Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the
requirements needed to properly configure application software for execution from on-chip
flash memory. Requirements for both DSP/BIOS™ and non-DSP/BIOS projects are
presented. Example code projects are included.
SPRAA85 Programming TMS320x28xx and 28xxx Peripherals in C/C++ explores a hardware
abstraction layer implementation to make C/C++ coding easier on 28x DSPs. This method is
compared to traditional #define macros and topics of code efficiency and special case
registers are also addressed.
SPRAA88 Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x presents a method
for utilizing the on-chip pulse width modulated (PWM) signal generators on the
TMS320F280x family of digital signal controllers as a digital-to-analog converter (DAC).
SPRAA91 TMS320F280x DSC USB Connectivity Using TUSB3410 USB-to-UART Bridge Chip presents
hardware connections as well as software preparation and operation of the development
system using a simple communication echo program.
SPRAAH1 Using the Enhanced Quadrature Encoder Pulse (eQEP) Module provides a guide for the use
of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x,
28xxx family of processors.
SPRAAI1
Using Enhanced Pulse Width Modulator (ePWM) Module for 0-100% Duty Cycle Control
provides a guide for the use of the ePWM module to provide 0% to 100% duty cycle control
and is applicable to the TMS320x280x family of processors.
SPRAAD5 Power Line Communication for Lighting Apps using BPSK w/ a Single DSP Controller
presents a complete implementation of a power line modem following CEA-709 protocol
using a single DSP.
SPRAAD8 TMS320280x and TMS320F2801x ADC Calibration describes a method for improving the
absolute accuracy of the 12-bit ADC found on the TMS320280x and TMS3202801x devices.
Inherent gain and offset errors affect the absolute accuracy of the ADC. The methods
described in this report can improve the absolute accuracy of the ADC to levels better than
0.5%. This application report has an option to download an example program that executes
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from RAM on the F2808 EzDSP.
SPRAB26 TMS320x2833x/2823x to TMS320x2834x Delfino Migration Overview This application report
describes differences between the Texas Instruments TMS320x2833x/2823x and the
TMS320x2834x devices to assist in application migration.
SPRA820
Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for
online stack overflow detection on the TMS320C28x™ DSP. C-source code is provided that
contains functions for implementing the overflow detection on both DSP/BIOS™ and
non-DSP/BIOS applications.
SPRA806
An Easy Way of Creating a C-callable Assembly Function for the TMS320C28x DSP
provides instructions and suggestions to configure the C compiler to assist with
understanding of parameter-passing conventions and environments expected by the C
compiler.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Updated information on the TMS320 DSP controllers can be found on the worldwide web at:
http://www.ti.com.
To send comments regarding this data manual (literature number SPRS516), use the
comments@books.sc.ti.com email address, which is a repository for feedback. For questions and support,
contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site.
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6
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
6.1 Absolute Maximum Ratings(1)(2)
Supply voltage range, VDDIO
Supply voltage range, VDD
with respect to VSS
with respect to VSS
with respect to VSS
– 0.3 V to 4.0 V
– 0.3 V to 1.5 V
– 0.3 V to 2.4 V
– 0.3 V to 4.0 V
– 0.3 V to 2.4 V
– 0.3 V to 4.0 V
± 20 mA
Supply voltage range, VDD18
Input voltage range, VIN (3.3 V)
Input voltage range, VIN (1.8 V)
Output voltage range, VO
(3)
Input clamp current, IIK (VIN < 0 or VIN > VDDIO
)
Output clamp current, IOK (VO < 0 or VO > VDDIO
)
± 20 mA
(4)
Junction temperature range, TJ
– 40°C to 150°C
– 65°C to 150°C
(4)
Storage temperature range, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 6.2 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ± 2 mA.
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for
TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).
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6.2 Recommended Operating Conditions
MIN
3.14
1.14
1.05
NOM
3.3
1.2
1.1
0
MAX
3.46
1.26
1.16
UNIT
V
Device supply voltage, I/O, VDDIO
300-MHz devices
V
Device supply voltage CPU, VDD
200-MHz devices
V
Supply ground, VSS, VSSIO
Oscillator supply ground, VSSK
PLL/oscillator supply, VDD18
V
0
V
1.71
2
1.8
1.89
300
V
Device clock frequency (system clock),
fSYSCLKOUT
C28346/C28344/C28342
(VDD = 1.2 V ± 5%)
MHz
C28345/C28343/C28341
2
200
(VDD = 1.1 V ± 5%)
High-level input voltage, VIH (3.3 V)
High-level input voltage, VIH (1.8 V)
Low-level input voltage, VIL (3.3 V)
Low-level input voltage, VIL (1.8 V)
2
VDDIO
V
V
0.7 * VDD18
0.8
V
0.3 * VDD18
V
High-level output source current, VOH = 2.4 V, IOH All I/Os
– 4
4
mA
Low-level output sink current, VOL = VOL MAX,
IOL
All I/Os
mA
(1)
Junction temperature, TJ
T version
– 40
105
°C
(1) TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. See Section 6.5,
Thermal Design Considerations.
6.3 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOHMAX
IOH = 50 µA
VOH High-level output voltage
VOL Low-level output voltage
V
VDDIO – 0.2
IOL = IOLMAX
0.4
V
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
All I/Os (including XRS)
–190
–130
Input current
(low level)
IIL
µA
Pin with pulldown
enabled
±15
±3
Pin with pullup
enabled
Input current
(high level)
IIH
µA
Pin with pulldown
enabled
100
175
±15
Output current, pullup or
pulldown disabled
IOZ
CI
µA
Input capacitance
2
pF
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6.4 Current Consumption
Table 6-1. TMS320C28346/C28344/C28342 Current Consumption by Power-Supply Pins at 300-MHz
SYSCLKOUT
(1)
IDD
IDDIO
IDD18
MODE
TEST CONDITIONS
25°C
105°C
25°C
105°C
25°C
105°C
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6/7/8/9
eCAP1/2/3
eQEP1/2/3
eCAN-A
SCI-A/B (FIFO mode)
SPI-A (FIFO mode)
McBSP-A
Typical
Operational
208 mA
353 mA
46 mA
50 mA
39 mA
33 mA
I2C
XINTF
DMA
CPU Timer 0/1/2
All PWM pins are toggled at
300 kHz.
All I/O pins are left
unconnected. XCLKOUT is
turned off. Pullups on output
pins and XINTF pns are
disabled.(2)
XCLKOUT is turned off.
Peripheral clocks are off.
IDLE
82 mA
21 mA
20 mA
211 mA
145 mA
140 mA
12 mA
11 mA
11 mA
14 mA
14 mA
13 mA
40 mA
40 mA
20 µA
33 mA
34 mA
540 µA
STANDBY
HALT
Peripheral clocks are off.
Peripheral clocks are off.
Input clock is disabled.(3)
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Floating-point multiplication and addition are performed.
Watchdog is reset.
32-bit read/write of the XINTF is performed.
DMA channels 1 and 2 transfer data from SARAM to SARAM.
GPIO19 is toggled.
(3) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available
peripherals from being used at the same time. This is because more than one peripheral
function may share an I/O pin. It is, however, possible to turn on the clocks to all the
peripherals at the same time, although such a configuration is not useful. If this is done,
the current drawn by the device will be more than the numbers specified in the current
consumption tables.
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Table 6-2. TMS320C28345/C28343/C28341 Current Consumption by Power-Supply Pins at 200-MHz
SYSCLKOUT
(1)
IDD
IDDIO
IDD18
MODE
TEST CONDITIONS
25°C
105°C
25°C
105°C
25°C
105°C
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
The following peripheral clocks
are enabled:
•
•
•
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4
eQEP1/2
eCAN-A
SCI-A/B (FIFO mode)
SPI-A (FIFO mode)
McBSP-A
Typical
operation
120 mA
227 mA
35 mA
39 mA
37 mA
31 mA
I2C
XINTF
DMA
CPU TImers 0/1/2
All PWM pins are toggled at 200
kHz. All I/O pins are left
unconnected. XCLKOUT is
turned off. Pullups on output pins
(2)
and XINTf pins are disabled.
Peripheral clocks are off.
XCLKOUT is turned off.
IDLE
50 mA
13 mA
12 mA
151 mA
114 mA
111 mA
12 mA
11 mA
11 mA
14 mA
14 mA
14 mA
40 mA
40 mA
10 µA
31 mA
31 mA
100 µA
STANDBY
HALT
Peripheral clocks are off.
Peripheral clocks are off. Input
(3)
clock is disabled.
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Floating-point multiplication and addition are performed.
Watchdog is reset.
32-bit read/write of the XINTF is performed.
DMA channels 1 and 2 transfer data from SARAM to SARAM.
GPIO19 is toggled.
(3) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
6.4.1 Reducing Current Consumption
Methods of reducing current consumption include the following:
•
Turn off the clock to any peripheral module that is not used in a given application since each peripheral
unit has an individual clock-enable bit. Table 6-3 indicates the typical reduction in current consumption
achieved by turning off the clocks.
•
•
•
Use any one of the three low-power modes to reduce current even further.
Turn off XCLKOUT, reducing IDDIO current consumption by 15 mA (typical).
Disable the pullups on pins that assume an output function and on XINTF pins for significant savings in
IDDIO
.
NOTE
The TMS320C2834x devices are manufactured in a high-performance process node.
Compared to the previous generation of the C28x devices, this process has more leakage
current. Leakage current is significantly impacted by the operating temperature, and the
increase in current with temperature is non-linear. The total power for a given operating
condition includes switching/active power plus leakage power. Low-power HALT mode
power is due to the leakage current alone. The maximum operational power is expected
to be approximately 1.3 W. This limit will be finalized after production test data becomes
available.
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Table 6-3. Typical Current Consumption by Various
Peripherals(1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
I2C
eQEP
ePWM
eCAP
SCI
5
5
3
1
4
SPI
4
eCAN
McBSP
CPU - Timer
XINTF
DMA
2
8
1
4(2)
7
FPU
8
(1) All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral clocks
are turned on.
(2) Operating the XINTF bus has a significant effect on IDDIO current.
It will increase considerably based on the following:
•
•
•
•
•
How many address/data pins toggle from one cycle to another
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Whether internal pullups are enabled on the XINTF pins.
104
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6.5 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature
number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number
SPRA963) help to understand the thermal metrics and definitions.
6.6 Emulator Connection Without Signal Buffering for the MCU
Figure 6-1 shows the connection between the MCU and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-1 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
For details on buffering JTAG signals and multiple processor connections, see TMS320F/C24x DSP
Controllers CPU and Instruction Set Reference Guide (literature number SPRU160).
6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
GND
1
6
GND
GND
GND
GND
3
8
TDI
7
10
12
TDO
TDO
11
9
TCK
TCK
TCK_RET
MCU
JTAG Header
Figure 6-1. Emulator Connection Without Signal Buffering for the MCU
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6.7 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
6.7.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
6.7.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
(Α)
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 6-2. 3.3-V Test Load Circuit
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6.7.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Table 6-4 through Table 6-5 list the cycle times of various clocks.
Table 6-4. Clocking and Nomenclature (300-MHz devices)
MIN
33
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
30
ns
MHz
ns
On-chip oscillator clock
XCLKIN
20
tc(CI), Cycle time
Frequency
6.67
4
250
150
500
300
2000
50(1)
MHz
ns
tc(SCO), Cycle time
Frequency
3.33
2
SYSCLKOUT
MHz
ns
tc(XCO), Cycle time
Frequency
20
XCLKOUT
0.5
25
MHz
ns
tc(HCO), Cycle time
Frequency
213(3)
4.7(3)
13.3(3)
75(3)
HSPCLK/EXTADCCLK(2)
LSPCLK(4)
40
MHz
ns
tc(LCO), Cycle time
Frequency
6.67
150
MHz
(1) Although the maximum XCLKOUT frequency is 50 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(2) This frequency is limited by GPIO switching characteristics.
(3) This is the default reset value if SYSCLKOUT = 300 MHz.
(4) Lower LSPCLK and HSPCLK will reduce device power consumption.
Table 6-5. Clocking and Nomenclature (200-MHz devices)
MIN
33
20
6.67
4
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
30
ns
MHz
ns
On-chip oscillator clock
XCLKIN
tc(CI), Cycle time
Frequency
250
150
500
200
2000
50(1)
MHz
ns
tc(SCO), Cycle time
Frequency
5
SYSCLKOUT
2
MHz
ns
tc(XCO), Cycle time
Frequency
20
0.5
10
XCLKOUT
MHz
ns
tc(HCO), Cycle time
Frequency
320(3)
3.1(3)
20(3)
50(3)
HSPCLK/EXTADCCLK(2)
LSPCLK(4)
25
MHz
ns
tc(LCO), Cycle time
Frequency
10
100
MHz
(1) Although the maximum XCLKOUT frequency is 50 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(2) This frequency is limited by GPIO switching characteristics.
(3) This is the default reset value if SYSCLKOUT = 200 MHz.
(4) Lower LSPCLK and HSPCLK will reduce device power consumption.
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6.8 Clock Requirements and Characteristics
Table 6-6. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
MIN
TYP MAX UNIT
30
Crystal (X1/X2)
30
MHz
150
fx
Input clock frequency(1)
XCLKIN
X1
4
4
External oscillator/clock
source
100
(1) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
Table 6-7. XCLKIN Timing Requirements - PLL Enabled
NO.
MIN
6.67
10
MAX UNIT
C8
tc(CI)
Cycle time
XCLKIN
X1
50
50
2
ns
C9
tf(CI)
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
ns
ns
%
%
C10 tr(CI)
2
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45
45
55
55
(1)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
(1) This applies to the X1 pin also.
Table 6-8. XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
6.67
10
MAX UNIT
C8
tc(CI)
Cycle time
XCLKIN
X1
250
250
2
ns
C9
tf(CI)
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
ns
ns
%
%
C10 tr(CI)
2
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
45
45
55
55
(1)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 3-14.
Table 6-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1)(2)
NO.
C1
C3
C4
C5
C6
PARAMETER
Cycle time, XCLKOUT
MIN
TYP
MAX
UNIT
ns
tc(XCO)
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
20
Fall time, XCLKOUT
2
2
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
ns
H – 2
H – 2
H + 2
ns
H + 2
ns
(3)
2600tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
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C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6-3. Clock Timing
6.9 Power Sequencing
No special requirements are placed on the power up/down sequence of the various power pins to ensure
the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output
buffers of the I/O pins are powered prior to the 1.1-V/1.2-V transistors, it is possible for the output buffers
to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD
pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7-V before
the VDDIO pins reach 0.7 V. The 1.8-V rail for the PLL and oscillator logic can be powered up along with
VDD/VDDIO rails. The 1.8-V rail must be powered even if the PLL is not used. It should never be left
unpowered. In any configuration, all the rails should ramp up within tpup (5 ms, typical) to allow early
stability of clocks and IOs.
There is a requirement on the XRS pin:
•
During power up, the XRS pin must be held low for tw(RSL1) (8 OSC clock cycles) after the input clock is
stable. This is to enable the entire device to start from a known condition.
Additionally it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any
pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal
P-N junctions in unintended ways and produce unpredictable results.
6.9.1 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to www.ti.com and click
on Power Management for a complete list of TI power ICs or select the Power Management Selection
Guide link for specific power reference designs.
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VDDIO (3.3 V)
VDD18 (1.8 V)
VDD (1.2 V/1.1 V)
XCLKIN
X1/X2
(A)
OSCCLK/16
OSCCLK/64
XCLKOUT
User-Code Dependent
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/8. Since the XTIMCLK, CLKMODE, and BY4CLKMODE bits in the
XINTFCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 8 before it applies to
XCLKOUT. This explains why XCLKOUT = OSCCLK/64 during this phase. Subsequently, boot ROM changes
SYSCLKOUT to OSCLK/2. Because the XTIMCLK register is unchanged by the boot ROM, XCLKOUT is OSCCLK/16
during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
C. See Section 6.9 for requirements to ensure a high-impedance state for GPIO pins during power-up.
Figure 6-4. Power-on Reset
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Table 6-10. Reset (XRS) Timing Requirements
MIN
NOM
MAX
UNIT
cycles
cycles
(1)
tw(RSL1)
Pulse duration, stable input clock to XRS high
Pulse duration, XRS low
64tc(OSCCLK)
64tc(OSCCLK)
tw(RSL2)
tw(WDRS)
td(EX)
Warm reset
Pulse duration, reset pulse generated by
watchdog
512tc(OSCCLK)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
tOSCST
1
th(boot-mode)
tpup
Hold time for boot-mode pins
Power-up time
200tc(OSCCLK)
cycles
ms
5
(1) In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Don’t Care)
User-Code Execution
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 6-5. Warm Reset
Figure 6-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0003 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0007 (setting for OSCCLK x
8). Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase,
SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete (which takes 2600 OSCCLK cycles),
SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
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OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(Changed CPU Frequency)
(PLL Lock-up Time, t ) is
p
2600 OSCCLK Cycles Long.)
Figure 6-6. Example of Effect of Writing Into PLLCR Register
6.10 General-Purpose Input/Output (GPIO)
6.10.1 GPIO - Output Timing
Table 6-11. General-Purpose Output Switching Characteristics
PARAMETER
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
MIN
MAX
11
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
11
ns
40
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-7. General-Purpose Output Timing
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6.10.2 GPIO - Input Timing
(A)
1
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
by GPxCTRL[QUALPRD]
w(SP)
(B)
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin
will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide
pulse ensures reliable recognition.
Figure 6-8. Sampling Mode
Table 6-12. General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
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6.10.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
XCLKOUT
GPIOxn
t
w(GPI)
Figure 6-9. General-Purpose Input Timing
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6.10.4 Low-Power Mode Wakeup Timing
Table 6-13 shows the timing requirements, Table 6-14 shows the switching characteristics, and
Figure 6-10 shows the timing diagram for IDLE mode.
Table 6-13. IDLE Mode Timing Requirements(1)
MIN NOM
MAX
UNIT
Without input qualifier
With input qualifier
2tc(SCO)
5tc(SCO) + tw(IQSW)
Pulse duration, external wake-up
signal
tw(WAKE-INT)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12.
Table 6-14. IDLE Mode Switching Characteristics(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, external wake signal to
(2)
program execution resume
td(WAKE-IDLE)
Without input qualifier
With input qualifier
20tc(SCO)
cycles
•
Wake-up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 6-10. IDLE Entry and Exit Timing
Table 6-15. STANDBY Mode Timing Requirements
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Without input qualification
With input qualification(1)
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
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Table 6-16. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake
signal to program execution
resume(1)
td(WAKE-STBY)
cycles
cycles
Without input qualifier
With input qualifier
100tc(SCO)
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
•
•
•
8 cycles, when DIVSEL = 00
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is
in progress and its access time is longer than this number then it will fail. It is recommended to enter STANDBY
mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-11. STANDBY Entry and Exit Timing Diagram
Table 6-17. HALT Mode Timing Requirements
MIN NOM
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Table 6-10 for an explanation of toscst
.
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Table 6-18. HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
45tc(SCO)
UNIT
cycles
cycles
cycles
Delay time, IDLE instruction executed to XCLKOUT
low
td(IDLE-XCOL)
tp
32tc(SCO)
PLL lock-up time
2600tc(OSCCLK)
35tc(SCO)
Delay time, PLL lock to program execution resume
td(WAKE-HALT)
•
Wake up from SARAM
(G)
(A)
(C)
(E)
(B)
(D)
HALT
(F)
Device
Status
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
•
•
•
•
8 cycles when DIVSEL = 00
16 cycles, when DIVSEL = 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in
progress and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from
SARAM without an XINTF access in progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin
asynchronously begins the wakeup process, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or
XCLKIN) cycles.
F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the
interrupt (if enabled), after a latency.
G. Normal operation resumes.
Figure 6-12. HALT Wake-Up Using GPIOn
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6.11 Enhanced Control Peripherals
6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1-6. Table 6-19 shows the PWM timing requirements and
Table 6-20, switching characteristics.
Table 6-19. ePWM Timing Requirements(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12.
Table 6-20. ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
ns
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
ns
6.11.2 Trip-Zone Input Timing
(A)
XCLKOUT
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(B)
PWM
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-13. PWM Hi-Z Characteristics
Table 6-21. Trip-Zone input Timing Requirements(1)
MIN
1tc(SCO)
MAX UNIT
cycles
tw(TZ)
Pulse duration, TZx input low
Asynchronous
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12.
Table 6-22 shows the high-resolution PWM switching characteristics.
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Table 6-22. High Resolution PWM Characteristics at SYSCLKOUT = (150 - 300 MHz)
MIN
TYP
55
MAX UNIT
Micro Edge Positioning (MEP) step size(1)
VDD = 1.2 V
VDD = 1.1 V
120
140
ps
ps
65
(1) Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage. MEP step size will increase
with low voltage and high temperature and decrease with voltage and cold temperature.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
Table 6-23 shows the eCAP timing requirement and Table 6-24 shows the eCAP switching characteristics.
Table 6-23. Enhanced Capture (eCAP) Timing Requirement(1)
TEST CONDITIONS
Asynchronous
MIN
2tc(SCO)
MAX UNIT
cycles
tw(CAP)
Capture input pulse width
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12.
Table 6-24. eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
Table 6-25 shows the eQEP timing requirement and Table 6-26 shows the eQEP switching
characteristics.
Table 6-25. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1)
TEST CONDITIONS
Asynchronous/synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2(1tc(SCO) + tw(IQSW)
)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Asynchronous/synchronous
With input qualifier
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous/synchronous
With input qualifier
Asynchronous/synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12.
Table 6-26. eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO)
6tc(SCO)
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync
output
Table 6-27. External ADC Start-of-Conversion Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCAL)
Pulse duration, ADCSOCAO low
32tc(HCO)
cycles
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t
w(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
Figure 6-14. ADCSOCAO or ADCSOCBO Timing
6.12 External Interrupt Timing
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-15. External Interrupt Timing
Table 6-28. External Interrupt Timing Requirements(1)
TEST CONDITIONS
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
(2)
tw(INT)
Pulse duration, INT input low/high
Synchronous
With qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-12.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-29. External Interrupt Switching Characteristics(1)
PARAMETER
MIN
MAX
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
tw(IQSW) + 12tc(SCO)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-12.
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6.13 I2C Electrical Specification and Timing
Table 6-30. I2C Timing
TEST CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
400
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
Vih
0.7 VDDIO
Vhys
Vol
0.05 VDDIO
V
Low level output voltage
Low period of SCL clock
3-mA sink current
0
0.4
V
tLOW
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
1.3
µs
tHIGH
High period of SCL clock
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
-10
µs
lI
Input current with an input voltage
10
µA
between 0.1 VDDIO and 0.9 VDDIO MAX
6.14 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
6.14.1 Master Mode Timing
Table 6-31 lists the master mode timing (clock phase = 0) and Table 6-32 lists the timing (clock
phase = 1). Figure 6-16 and Figure 6-17 show the timing waveforms.
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Table 6-31. SPI Master Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
NO.
UNIT
MIN
4tc(LCO)
MAX
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
128tc(LCO)
0.5tc(SPC)M
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M - 0.5tc(LCO) - 10
0.5tc(SPC)M + 0.5tc(LCO)-10
0.5tc(SPC)M + 0.5tc(LCO)- 10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
10
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M
0.5tc(SPC)M
0.5tc(SPC)M
10
3
4
5
8
9
tw(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
td(SPCH-SIMO)M
td(SPCL-SIMO)M
tv(SPCL-SIMO)M
tv(SPCH-SIMO)M
tsu(SOMI-SPCL)M
tsu(SOMI-SPCH)M
tv(SPCL-SOMI)M
tv(SPCH-SOMI)M
Delay time, SPICLK high to SPISIMO
valid (clock polarity = 0)
Delay time, SPICLK low to SPISIMO
valid (clock polarity = 1)
10
10
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
20
0.5tc(SPC)M + 0.5tc(LCO) -10
0.5tc(SPC)M + 0.5tc(LCO) -10
20
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
ns
ns
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
20
20
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M - 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
0.5tc(SPC)M- 0.5tc(LCO)- 10
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 20-MHz MAX, slave mode receive 20-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
122
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1
SPICLK
(clock polarity = 0)
2
4
3
SPICLK
(clock polarity = 1)
5
SPISIMO
SPISOMI
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 1tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 1tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-16. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-32. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
SPI WHEN (SPIBRR + 1) IS EVEN OR
SPI WHEN (SPIBRR + 1) IS ODD
AND SPIBRR > 3
SPIBRR = 0
OR 2
NO.
UNIT
MIN
4tc(LCO)
MAX
128tc(LCO)
0.5tc(SPC)M
MIN
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
5tc(LCO)
127tc(LCO)
ns
ns
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 0)
0.5tc(SPC)M -10
0.5tc(SPC)M - 0.5tc
(LCO)-10
0.5tc(SPC)M - 0.5tc(LCO)
0.5tc(SPC)M - 0.5tc(LCO
0.5tc(SPC)M + 0.5tc(LCO)
0.5tc(SPC)M + 0.5tc(LCO)
tw(SPCL))M
Pulse duration, SPICLK low (clock polarity
= 1)
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
20
0.5tc(SPC)M
0.5tc(SPC)M - 0.5tc
(LCO)-10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
6
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity
= 0)
0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) -
10
tw(SPCH)M
Pulse duration, SPICLK high (clock
polarity = 1)
0.5tc(SPC)M
0.5tc(SPC)M + 0.5tc(LCO)
-10
tsu(SIMO-SPCH)M
tsu(SIMO-SPCL)M
tv(SPCH-SIMO)M
tv(SPCL-SIMO)M
tsu(SOMI-SPCH)M
tsu(SOMI-SPCL)M
tv(SPCH-SOMI)M
tv(SPCL-SOMI)M
Setup time, SPISIMO data valid before
SPICLK high (clock polarity = 0)
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M -10
20
Setup time, SPISIMO data valid before
SPICLK low (clock polarity = 1)
7
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
10
11
Setup time, SPISOMI before SPICLK high
(clock polarity = 0)
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
20
20
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
0.25tc(SPC)M -10
0.25tc(SPC)M -10
0.5tc(SPC)M -10
0.5tc(SPC)M -10
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 20-MHz MAX, slave mode receive 20 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
124
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
SPISOMI
Master Out Data Is Valid
10
Data Valid
11
Master In Data Must
Be Valid
(A)
SPISTE
A. In the master mode, SPISTE goes active 1tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the
word, the SPISTE will go inactive 1tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE
stays active between back-to-back transmit words in both FIFO and nonFIFO modes.
Figure 6-17. SPI Master Mode External Timing (Clock Phase = 1)
6.14.2 SPI Slave Mode Timing
Table 6-33 lists the slave mode external timing (clock phase = 0) and Table 6-34 (clock phase = 1).
Figure 6-18 and Figure 6-19 show the timing waveforms.
Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
MIN
4tc(LCO)
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLK
ns
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)
Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S
ns
ns
ns
ns
ns
ns
ns
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
20
14 tw(SPCL)S
tw(SPCH)S
15 td(SPCH-SOMI)S
td(SPCL-SOMI)S
16 tv(SPCL-SOMI)S
20
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
0.75tc(SPC)S
0.75tc(SPC)S
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
ns
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 20-MHz MAX, slave mode receive 20-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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Table 6-33. SPI Slave Mode External Timing (Clock Phase = 0) (continued)
NO.
MIN
MAX UNIT
19 tsu(SIMO-SPCL)S
tsu(SIMO-SPCH)S
20 tv(SPCL-SIMO)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
20
20
ns
ns
ns
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 0)
0.5tc(SPC)S-10
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 1)
0.5tc(SPC)S-10
ns
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISIMO
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 1tc(SPC) (minimum) before the valid SPI clock
edge and remain low for at least 1tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 0)
Table 6-34. SPI Slave Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)
NO.
MIN
8tc(LCO)
MAX UNIT
12 tc(SPC)S
13 tw(SPCH)S
tw(SPCL)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.5tc(SPC)S - 10
0.125tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
14 tw(SPCL)S
tw(SPCH)S
17 tsu(SOMI-SPCH)S
tsu(SOMI-SPCL)S
0.125tc(SPC)S
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 20-MHz MAX, slave mode receive 20-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
126
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Table 6-34. SPI Slave Mode External Timing (Clock Phase = 1) (continued)
NO.
MIN
0.75tc(SPC)S
MAX UNIT
18 tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
ns
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0.75tc(SPC)S
ns
21 tsu(SIMO-SPCH)S
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
20
20
ns
ns
ns
22 tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)S-10
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)S-10
ns
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISIMO
SPISOMI Data Is Valid
Data Valid
21
22
SPISIMO Data
Must Be Valid
(A)
SPISTE
A. In the slave mode, the SPISTE signal should be asserted low at least 1tc(SPC) before the valid SPI clock edge and
remain low for at least 1tc(SPC) after the receiving edge (SPICLK) of the last data bit.
Figure 6-19. SPI Slave Mode External Timing (Clock Phase = 1)
6.15 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the
Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF
zone. Table 6-35 shows the relationship between the parameters configured in the XTIMING register and
the duration of the pulse in terms of XTIMCLK cycles.
Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)(1)(2)
DESCRIPTION
Lead period, read access
(1) tc(XTIM) – Cycle time, XTIMCLK
X2TIMING = 0
X2TIMING = 1
LR
XRDLEAD × tc(XTIM)
(XRDLEAD × 2) × tc(XTIM)
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
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Table 6-35. Relationship Between Parameters Configured in XTIMING and Duration of Pulse (continued)
DURATION (ns)(1)(2)
DESCRIPTION
X2TIMING = 0
(XRDACTIVE + WS + 1) × tc(XTIM)
XRDTRAIL × tc(XTIM)
X2TIMING = 1
AR
TR
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
LW
AW
TW
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
(XWRACTIVE + WS + 1) × tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No
internal device hardware is included to detect illegal settings.
6.15.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
Lead:
Active:
Trail:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
AR ≥ 6 × tc(XTIM)
AW ≥ 1 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 6
≥ 0
≥ 3
≥ 1
≥ 3
0(1)
(1) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Valid(2)
0
2
0
6
0
0
0
3
0
1
0
3
0(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed.
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
6.15.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1
2
3
Lead:
Active:
Trail:
LR ≥ × 2 t c(XTIM)
LW ≥ 3 × tc(XTIM)
AR ≥ 6 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
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XRDLEAD
≥ 2
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 6
≥ 0
≥ 3
≥ 2
≥ 3
0(1)
(1) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Invalid(1)
Valid(2)
0
1
2
0
0
6
0
0
0
0
1
3
0
0
2
0
0
3
0, 1
0(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
6.15.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
2
3
Lead:
Active:
Trail:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
AR ≥ 6 × tc(XTIM)
AW ≥ 4 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
NOTE
Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 6
0
≥ 3
≥ 4
0
0(1)
(1) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
Invalid(1)
Invalid(1)
Valid(2)
0
1
1
2
0
0
1
6
0
0
0
0
0
1
1
3
0
0
1
4
0
0
0
3
0, 1
0, 1
0
0(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers
Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-36.
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Table 6-36. XINTF Clock Configurations
MODE
SYSCLKOUT
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
XTIMCLK
SYSCLKOUT
300 MHz
XCLKOUT(1)
1
SYSCLKOUT
300 MHz
Example:
2
SYSCLKOUT
300 MHz
1/2 SYSCLKOUT
150 MHz
Example:
3
SYSCLKOUT
300 MHz
1/2 SYSCLKOUT
150 MHz
Example:
4
SYSCLKOUT
300 MHz
1/4 SYSCLKOUT
75 MHz
Example:
5
Example:
6
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/4 SYSCLKOUT
75 MHz
Example:
7
1/2 SYSCLKOUT
150 MHz
1/4 SYSCLKOUT
75 MHz
Example:
8
1/2 SYSCLKOUT
150 MHz
1/8 SYSCLKOUT
37.5 MHz
Example:
(1) The XCLKOUT signal is limited to the output buffer speed.
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-20.
PCLKR3[XINTFENCLK]
XTIMING0
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
0
0
1
SYSCLKOUT
C28x
CPU
XTIMCLK
/2
1
0
/2
1
0
/2
1
0
XCLKOUT
XINTCNF2 (XTIMCLK)
XINTCNF2
(CLKMODE)
XINTCNF2
(BY4CLKMODE)
XINTCNF2
(CLKOFF)
Figure 6-20. Relationship Between XTIMCLK and SYSCLKOUT
6.15.4 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock
XTIMCLK. Strobes such as XRD, XWE0, XWE1, and zone chip-select (XZCS) change state in relationship
to the rising edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or
one-half the frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the
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rising edge of XCLKOUT. For the case where XCLKOUT = one-half or one-fourth XTIMCLK, some strobes
will change state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF
timing tables, the notation XCOHL is used to indicate that the parameter is with respect to either case;
XCLKOUT rising edge (high) or XCLKOUT falling edge (low). If the parameter is always with respect to
the rising edge of XCLKOUT, the notation XCOH is used.
For the case where XCLKOUT = one-half or one-fourth XTIMCLK, the XCLKOUT edge with which the
change will be aligned can be determined based on the number of XTIMCLK cycles from the start of the
access to the point at which the signal changes. If this number of XTIMCLK cycles is even, the alignment
will be with respect to the rising edge of XCLKOUT. If this number is odd, then the signal will change with
respect to the falling edge of XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active low
XR/W active low
XRNWL
•
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if
the total number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK
cycles is odd, then the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XWEL
XRD active low
XWE1 or XWE0 active low
•
•
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the
total number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If
the number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment
will be with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XWEH
XRD inactive high
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total
number of lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number
of lead + active + trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will
be with respect to the falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XR/W inactive high
XRNWH
6.15.5 External Interface Read Timing
Table 6-37. External Interface Read Timing Requirements
MIN
Access time, read data from address valid
MAX
(LR + AR) –13.5(1)
AR –13(1)
UNIT
ns
ta(A)
ta(XRD)
Access time, read data valid from XRD active low
ns
tsu(XD)XRD
th(XD)XRD
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
13
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
Table 6-38. External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
2
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
0
–0.2
0.9
ns
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Table 6-38. External Interface Read Switching Characteristics (continued)
PARAMETER
MIN
MAX
0.57
0.4
UNIT
ns
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH
th(XA)XZCSH
th(XA)XRD
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–0.2
ns
–0.4
(1)
0.4
ns
ns
(1)
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Trail
(A)(B)
(C)
Active
Lead
XCLKOUT = XTIMCLK(D)
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
XA[0:19]
t
d(XCOH-XA)
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE, XWE1(E)
t
su(XD)XRD
XR/W
t
a(A)
t
h(XD)XRD
t
a(XRD)
XD[0:31], XD[0:15]
XREADY(F)
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-21. Example Read Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 2
≥ 6
≥ 0
0
0
N/A(1)
N/A(1)
N/A(1)
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
6.15.6 External Interface Write Timing
Table 6-39. External Interface Write Switching Characteristics
PARAMETER
MIN
0
MAX
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low
2
0.9
–0.2
ns
0.57
0.5
ns
td(XCOHL-XWEL)
–0.5
ns
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Table 6-39. External Interface Write Switching Characteristics (continued)
PARAMETER
MIN
–0.5
-0.2
0.3
MAX
0.5
UNIT
ns
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE0, XWE1 high
Delay time, XCLKOUT high to XR/W low
0.4
ns
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high
0.6
ns
–7.5
ns
td(XWEL-XD)
4
ns
(1)
th(XA)XZCSH
ns
th(XD)XWE
TW-7.5(2)
ns
tdis(XD)XRNW
Maximum time for processor to release the data bus after XR/W inactive
high
0
ns
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
(2) TW = Trail period, write access. See Table 6-35.
Active
(A) (B)
(C)
Lead
Trail
XCLKOUT = XTIMCLK(D)
XZCS0, XZCS6, XZCS7
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE0, XWE1(E)
XR/W
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
XD[0:31], XD[0:15]
XREADY(F)
DOUT
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which
remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 6-22. Example Write Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
0
0
≥ 3
≥ 1
≥ 3
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
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6.15.7 External Interface Ready-on-Read Timing With One External Wait State
Table 6-40. External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
0
MAX
2
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive
high
- 0.2
0.9
ns
td(XCOH-XA)
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
th(XA)XRD
Delay time, XCLKOUT high to address valid
0.57
0.4
ns
ns
ns
ns
ns
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–0.2
-0.4
(1)
0.4
(1)
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
Table 6-41. External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
(LR + AR) - 13.5(1)
AR - 13(1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
13
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 6-35.
Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1)
MIN
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
14
1tc(XTIM)
14
ns
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
ns
0
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-23:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
UNIT
ns
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
14
1tc(XTIM)
14
ns
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
ns
0
ns
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WS (Synch)
(A) (B)
(C)
Active
Lead
Trail
(D)
XCLKOUT = XTIMCLK
t
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
d(XCOH-XA)
XZCS0, XZCS6, XZCS7
XA[0:19]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
t
su(XD)XRD
(E)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:31], XD[0:15]
DIN
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
Legend:
(F)
(G)
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is valid only in 32-bit data bus mode.
F. For each sample, setup time from the beginning of the access (E) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
G. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the
sample number: n = 1, 2, 3, and so forth.
Figure 6-23. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 2
6
≥ 0
1
0
N/A(1)
N/A(1)
N/A(1)
0 = XREADY
(Synch)
(1) N/A = “Don’t care” for this example
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WS (Async)
Active
(A) (B)
Lead
Trail
(C)
(D)
XCLKOUT = XTIMCLK
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
t
d(XCOH-XA)
XA[0:19]
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
(E)
t
su(XD)XRD
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
DIN
XD[0:31], XD[0:15]
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is valid only in 32-bit data bus mode.
F. For each sample, setup time from the beginning of the access can be calculated as:
E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and
so forth.
G. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 6-24. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 2
6
≥ 0
1
0
N/A(1)
N/A(1)
N/A(1)
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
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6.15.8 External Interface Ready-on-Write Timing With One External Wait State
Table 6-44. External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN
0
MAX
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XWE0, XWE1 low(1)
Delay time, XCLKOUT high/low to XWE0, XWE1 high(1)
Delay time, XCLKOUT high to XR/W low
–0.2
0.9
0.57
0.5
0.5
0.4
0.6
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
–0.5
–0.5
-0.2
0.3
Delay time, XCLKOUT high/low to XR/W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high(1)
–7.5
td(XWEL-XD)
4
(2)
th(XA)XZCSH
th(XD)XWE
TW-7.5(3)
tdis(XD)XRNW
Maximum time for processor to release the data bus after XR/W
inactive high
(1) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
(3) TW = trail period, write access (see Table 6-35)
Table 6-45. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)
MIN
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
14
1tc(XTIM)
14
ns
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
ns
0
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-25:
E =(XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is high, then the access will complete. If XREADY (synchronous) is low, it is sampled
again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE +n –1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Table 6-46. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1)
MIN
MAX UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
14
1tc(XTIM)
14
ns
ns
ns
ns
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
0
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 6-25:
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
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WS (Synch)
Active
(A) (B)
(C)
Trail
Lead 1
XCLKOUT = XTIMCLK(D)
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
t
t
h(XRDYsynchH)XZCSH
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY (Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE +
n –1) tc(XTIM) – tsu(XRDYsynchL)XCOH where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 6-25. Write With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 3
2
≥3
0 = XREADY
(Synch)
(1) N/A = "Don't care" for this example.
138
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WS (Async)
(A) (B)
(C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK(D)
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
(E)
XWE0, XWE1
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
t
)
h(XD)XWEH
t
en(XD)XWEL
XD[31:0], XD[15:0]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE
-3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 6-26. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 3
4
≥ 3
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
SPRS516–MARCH 2009
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6.15.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of
high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the
bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active
low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still
execute code from internal memory. If an access is made to the external interface, the CPU is stalled until
the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XD[31:0], XD[15:0] XZCS6
XWE0, XWE1,
XRD
XZCS7
XR/W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
Table 6-47. XHOLD/XHOLDA Timing Requirements(1)(2)(3)
MIN
MAX
4tc(XTIM) + tc(XCO)
4tc(XTIM + 2tc(XCO)
4tc(XTIM)
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
ns
6tc(XTIM)
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT.
Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value
specified.
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XCLKOUT
XHOLD
t
d(HL-Hiz)
t
d(HH-HAH)
XHOLDA
XR/W
t
d(HL-HAL)
t
d(HH-BV)
High-Impedance
XZCS0, XZCS6, XZCS7
Valid
XA[19:0]
Valid
High-Impedance
XD[31:0], XD[15:0]
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-27. External Interface Hold Waveform
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6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-48. McBSP Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
1
kHz
(3)
40
MHz
ns
25
1
ms
ns
M11
M12
M13
M14
M15
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
2P
tw(CKRX)
tr(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
P – 4
ns
4
4
ns
tf(CKRX)
Fall time, CLKR/X
ns
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
20
2
ns
M16
M17
M18
M19
M20
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
0
ns
ns
ns
ns
ns
6
20
2
0
6
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
20
2
0
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
CLKSRG can be LSPCLK, CLKX, CLKR
as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (40 MHz).
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Table 6-49. McBSP Switching Characteristics(1)(2)
NO.
PARAMETER
Cycle time, CLKR/X
MIN
MAX UNIT
M1
M2
M3
M4
tc(CKRX)
tw(CKRXH)
tw(CKRXL)
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P
ns
(3)
(3)
Pulse duration, CLKR/X high
D – 2
D + 2
ns
ns
ns
(3)
(3)
Pulse duration, CLKR/X low
C – 2
C + 2
td(CKRH-FRV)
Delay time, CLKR high to internal FSR valid
0
3
0
3
4
20
4
M5
M6
M7
td(CKXH-FXV)
tdis(CKXH-DXHZ)
td(CKXH-DXV)
Delay time, CLKX high to internal FSX valid
ns
ns
ns
20
8
Disable time, CLKX high to DX high impedance
following last data bit
14
4
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
20
4
Delay time, CLKX high to DX valid
DXENA = 0
20
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
P + 4
P + 20
M8
M9
ten(CKXH-DX)
Enable time, CLKX high to DX driven
DXENA = 0
CLKX int
CLKX ext
CLKX int
CLKX ext
0
10
P
ns
Only applies to first bit transmitted when DXENA = 1
in Data Delay 1 or 2 (XDATDLY=01b or
10b) modes
P + 10
td(FXH-DXV)
Delay time, FSX high to DX valid
DXENA = 0
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
4
16
ns
ns
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode.
P + 4
P + 16
M10 ten(FXH-DX)
Enable time, FSX high to DX driven
DXENA = 0
0
6
Only applies to first bit transmitted when DXENA = 1
in Data Delay 0 (XDATDLY=00b) mode
P
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
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M1, M11
M2, M12
M3, M12
M13
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
(RDATDLY=00b)
M18
DR
Bit (n−1)
(n−3)
(RDATDLY=01b)
M17
M18
DR
Bit (n−1)
(n−2)
(RDATDLY=10b)
Figure 6-28. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
Bit (n−1)
M8
Bit 0
M6
(XDATDLY=01b)
M7
DX
Bit 0
Bit (n−1)
(XDATDLY=10b)
Figure 6-29. McBSP Transmit Timing
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6.16.2 McBSP as SPI Master or Slave Timing
Table 6-50. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(BFXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P –10
8P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-51. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
M24
M25
M28
th(CKXL-FXL)
td(FXL-CKXH)
tdis(FXH-DXHZ)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
4P + 6
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by
setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 150 MHz, CLKX maximum frequency
will be LSPCLK/16 , that is 9.375 MHz and P = 6.67 ns.
M33
M32
MSB
LSB
CLKX
FSX
M25
M24
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-30. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 6-52. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
NO.
UNIT
MIN
30
1
MAX
MIN MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
M41 tsu(FXL-CKXH)
M42 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-53. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M34
M35
M37
th(CKXL-FXL)
td(FXL-CKXH)
tdis(CKXL-DXHZ)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
P
2P(1)
ns
ns
ns
Disable time, DX high impedance following last data bit
from CLKX low
P + 6
7P + 6
4P + 6
M38
td(FXL-DXV)
Delay time, FSX low to DX valid
6
ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With a maximum LSPCLK speed of 150 MHz, CLKX maximum
frequency is LSPCLK/16; that is, 9.375 MHz and P =6.67 ns.
M42
MSB
LSB
M41
CLKX
FSX
DX
M35
M34
M37
M38
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M39
M40
(n-2)
DR
Bit 0
(n-3)
(n-4)
Figure 6-31. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M49
M50
M51
M52
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXL)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P –10
ns
ns
ns
ns
8P –10
8P + 10
16P
2P(1)
(1) 2P = 1/CLKG
Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
M43 th(CKXH-FXL)
M44 td(FXL-CKXL)
M47 tdis(FXH-DXHZ)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
6
6P + 6
4P + 6
M48 td(FXL-DXV)
(1) 2P = 1/CLKG
Delay time, FSX low to DX valid
6
ns
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also, CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 150 MHz, CLKX maximum
frequency will be LSPCLK/16; that is, 9.375 MHz and P = 6.67 ns.
M52
M51
MSB
LSB
CLKX
FSX
M43
M44
M48
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M50
(n-3)
(n-4)
M49
Bit 0
(n-2)
(n-3)
(n-4)
Figure 6-32. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(1)
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 150 MHz, CLKX maximum
frequency is LSPCLK/16 , that is 9.375 MHz and P = 6.67 ns.
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1)
MASTER(2)
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
P
MAX
M53 th(CKXH-FXL)
M54 td(FXL-CKXL)
M56 tdis(CKXH-DXHZ)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
ns
2P(1)
Disable time, DX high impedance following last data bit from
CLKX high
P + 6
7P + 6
4P + 6
M57 td(FXL-DXV)
(1) 2P = 1/CLKG
Delay time, FSX low to DX valid
6
ns
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
M61
M60
MSB
M54
LSB
CLKX
M53
FSX
M56
M55
(n-2)
M57
DX
DR
Bit 0
Bit(n-1)
(n-3)
(n-4)
M58
M59
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 6-33. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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Electrical Specifications
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TMS320C28346, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28342, TMS320C28341
Delfino Microcontrollers
www.ti.com
SPRS516–MARCH 2009
7
Thermal/Mechanical Data
Table 7-1 and Table 7-2 show the thermal data.
The mechanical package diagram(s) that follow the tables reflect the most current released mechanical
data available for the designated device(s).
Table 7-1. Thermal Model 179-Ball ZHH Results
AIR FLOW
PARAMETER
0 lfm
40.8
0.4
150 lfm
32.4
250 lfm
31.0
500 lfm
29.1
θJA[°C/W] High k PCB
ΨJT[°C/W]
ΨJB
0.5
0.6
0.8
21.0
10.3
21.2
20.4
20.2
19.9
θJC
θJB
Table 7-2. Thermal Model 256-Ball ZFE Results
AIR FLOW
PARAMETER
0 lfm
30
150 lfm
21.8
250 lfm
20.6
500 lfm
19.1
θJA[°C/W] High k PCB
ΨJT[°C/W]
ΨJB
1.24
14
2.63
3.15
4.05
13.6
13.5
13.4
θJC
14
θJB
13.9
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Thermal/Mechanical Data
149
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320C28341ZFET
TMS320C28341ZHHT
ACTIVE
ACTIVE
BGA
ZFE
256
179
90
TBD
TBD
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BGA MI
CROSTA
R
ZHH
160
TMS320C28342ZFET
TMS320C28343ZFET
TMS320C28343ZHHT
ACTIVE
ACTIVE
ACTIVE
BGA
BGA
ZFE
ZFE
ZHH
256
256
179
90
90
TBD
TBD
TBD
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BGA MI
CROSTA
R
160
TMS320C28344ZFET
TMS320C28345ZFET
TMS320C28345ZHHT
ACTIVE
ACTIVE
ACTIVE
BGA
BGA
ZFE
ZFE
ZHH
256
256
179
90
90
TBD
TBD
TBD
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BGA MI
CROSTA
R
160
TMS320C28346ZFET
TMX320C28343ZHH
ACTIVE
ACTIVE
BGA
ZFE
ZHH
256
179
90
1
TBD
TBD
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BGA MI
CROSTA
R
TMX320C28346ZEP
ACTIVE
BGA
ZEP
256
1
TBD
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(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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