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TMS320C5517

ZHCS222C –AUGUST 2012–REVISED APRIL 2014

TMS320C5517 定点数字信号处理器

1 器件概述

1.1 特性

1

– 直接存储器存取 (DMA) 控制器

四个 DMA，各配有四条通道

– 三个 32 位通用 (GP) 定时器

• 内核：

•

– 高性能、低功耗 TMS320C55x 定点数字信号处

理器

•

13.33ns 至 5ns 指令周期时间

75MHz 至 200MHz 时钟速率

每个周期执行一条或两条指令

•

一个可被选为安全装置或 GP

计时选项，包括外部通用 I/O (GPIO) 时钟输

入

– 两个多媒体卡和安全数字（eMMC，MMC 和

SD）接口

两个乘积累积单元（每秒高达 4.5 亿次乘积累

积运算 [MMACS]）

– 具有四芯片选择的串行端口接口 (SPI)

– 主控和受控内部集成电路（I²C 总线）

•

两个算术和逻辑单元 (ALU)

三个内部数据或操作数读取总线和两个写入总

线

– 三个用于数据传输的内部集成电路 (IC) 声音（I²S

总线）模块

•

与 C55x 器件软件兼容

提供工业温度器件

– 10 位 4 输入逐次逼近 (SAR) ADC

– IEEE-1149.1 (JTAG)

边界扫描兼容

– 320KB 零等待状态片上 RAM：

•

64KB 双访问 RAM (DARAM)，

8 块 4K x 16 位

– 多达 26 个 GPIO 引脚（与其它功能多路复用）

• 电源：

•

256KB 单访问 RAM (SARAM)，

32 块 4K x 16 位

– 四个内核隔离的电源域：模拟，RTC，CPU 和外

设，以及 USB

– 四个 I/O 隔离电源域：RTC I/O，EMIF

I/O，USB PHY 和 DV_DDIO

– 128KB 零等待状态片上 ROM

（4 块 16K x 16 位）

– 紧密耦合快速傅里叶变换 (FFT) 硬件加速器

– 1.05V 内核，1.8V、2.75V 或 3.3V I/O

– 1.3V 内核，1.8V、2.75V 或 3.3V I/O

– 1.4V 内核，1.8V、2.75V 或 3.3V I/O

• 外设：

– 一个带有 16 位复用地址或数据总线的通用主机

端口接口 (UHPI)

• 时钟：

– 具有三芯片选择的主控和受控多通道串行端口接

口 (McSPI)

– 具有晶振输入、独立时钟域和电源的实时时钟

(RTC)

– 主控和受控多通道经缓冲串行端口接口 (McBSP)

– 软件可编程锁相环 (PLL) 时钟发生器

• 引导加载程序：

– 与下列器件有无缝接口连接的 16 位和 8 位外部

存储器接口 (EMIF)

•

8 位或 16 位 NAND 闪存，1 位或 4 位纠错码

(ECC)

8 位和 16 位 NOR 闪存

异步静态 RAM (SRAM)

– 片上 ROM 引导加载程序

•

每个外设均支持不加密启动

• 封装：

– 196 端子无铅塑料 BGA（球栅阵列）封装（后缀

ZCH），0.65mm 间距

•

SDRAM 或 mSDRAM（1.8，2.75 和 3.3 V）

– 3.84375M x 16 位最大可寻址外部存储器空

间（SDRAM 或 mSDRAM）

– 通用异步收发器 (UART)

– 带有集成型 2.0 高速物理层 (PHY) 的器件 USB

端口，支持：

•

USB 2.0 全速和高速器件

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SPRS727

TMS320C5517

ZHCS222C –AUGUST 2012–REVISED APRIL 2014

www.ti.com.cn

1.2 应用

•

数字双向无线电

•

音频器件（例如：回声抵消耳机和免提电话或者无

线耳机和麦克风）

低功耗分析应用（例如：语音识别、视觉传感和指

纹识别）

便携式医疗设备

•

语音应用（例如：录音机、免提套件和语音增强子

系统）

1.3 说明

此器件是 TI C5000™ 定点数字信号处理器 (DSP) 产品系列的成员之一，专用于低运行和待机功耗应用。

此器件基于 TMS320C55x DSP 生成 CPU 处理器内核。 C55x DSP 架构通过增加的并行性和重视节能来实

现高性能和低功耗。 CPU 支持一个内部总线结构，此结构包含一条程序总线，一条 32 位读取总线和两条

16 位数据读取总线，两条数据写入总线和专门用于外设和 DMA 操作的附加总线。这些总线可实现在一个

单周期内执行高达四次 16 位数据读取和两次 16 位数据写入的功能。此器件还包含四个 DMA 控制器，每

个控制器具有 4 条通道，可在无需 CPU 干预的情况下提供 16 条独立通道的数据传送。每个 DMA 控制器

在每周期可执行一个 32 位数据传输，此数据传输与 CPU 的运行并行并且不受 CPU 运行的影响。

C55x CPU 提供两个乘积累积 (MAC) 单元，每个单元在一个单周期内能够进行 17 位乘以 17 位乘法以及 32

位加法。一个中央 40 位算术和逻辑单元 (ALU) 由一个附加 16 位 ALU 提供支持。 ALU 的使用受指令集控

制，从而提供优化并行运行和功耗的能力。 C55x CPU 内的地址单元 (AU) 和数据单元 (DU) 对这些资源进

行管理。

C55x CPU 支持一个可变字节宽度指令集以改进代码密度。指令单元 (IU) 执行从内部或外部存储器中的 32

位程序取指令并且进行针对程序单元 (PU) 的指令排队。 PU 对指令进行解码，将任务指向地址单元和数据

单元资源，并管理受到完全保护的管线。跳转预测功能避免了条件指令执行时的管线冲刷。

GPIO 功能与 10 位 SAR ADC 一起为状态、中断以及用于键盘和媒体接口的位 I/O 提供足够的引脚。

通过以下器件为串行媒体提供支持：两个多媒体卡和安全数字（MMC 和 SD）外设、三个内部 IC 声

音（I2S 总线）模块、一个具有四芯片选择的串行端口接口 (SPI)、一个具有三芯片选择主控和受控多通道经

缓冲串行端口接口 (McSPI)、一个多通道串行端口 (McBSP)、一个 I²C 多主控和受控接口以及一个通用异步

收发器 (UART) 接口

该器件的外设集包括一个外部存储器接口 (EMIF)，此接口提供到异步存储器的无缝访问，例如

EPROM，NOR，NAND 和 SRAM，以及高速、高密度存储器，例如同步 DRAM (SDRAM) 和移动 SDRAM

(mSDRAM)。

其它外设包括：一个可配置 16 位通用主机端口接口 (UHPI)、一条仅支持器件模式的高速通用串行总线

(USB2.0)、一个实时时钟 (RTC)、三个通用定时器（其中一个可配置为看门狗定时器）和一个模拟锁相环

(APLL) 时钟发生器。

器件还包含一个紧密耦合 FFT 硬件加速器 - 支持 8 至 1024 点（2 的次幂）实值和复值 FFT，三个集成低压

降稳压器 (LDO) - 为器件的各部分供电（需要外部电源的 CV_DDRTC除外）：ANA_LDO 为 SAR 和电源管理

电路 (V_{DDA_ANA}) 提供 1.3V 电压，DSP_LDO 为 DSP 内核 (CV_DD)（一旦检测到工作频率范围，便可由软件

实时进行选择）提供 1.3V 或 1.05V 电压，USB_LDO 为 USB 内核数字电路 (USB_V_DD1P3) 和 PHY 电路

(USB_V_DDA1P3) 提供 1.3V 电压。

此器件由业界备受赞誉的 eXpressDSP™、 Code Composer Studio™ 集成开发环境 (IDE)、

DSP/BIOS™、德州仪器 (TI) 的算法标准和一个大型第三方网络提供支持。 Code Composer Studio IDE 提

供的代码生成工具包括一个 C 语言编译器和连接器、 RTDX™、XDS100、 XDS510™、 XDS560™ 仿真

器件驱动程序和评估模块。此器件也受 C55x DSP 库以及芯片支持库的支持，此库特有超过 50 个基础软件

内核（FIR 滤波器、IIR 滤波器、FFT 和多种数学函数）。

器件信息

封装

部件号

TMS320C5517AZCH20

TMS320C5517AZCHA20

封装尺寸

NFBGA (196)

10.0mm x 10.0mm

2

器件概述

TMS320C5517

www.ti.com.cn

ZHCS222C –AUGUST 2012–REVISED APRIL 2014

1.4 功能方框图

图 1-1可展示器件的功能框图

DSP System

C55x DSP CPU

JTAG Interface

FFT Hardware

Accelerator

Input

Clocks

PLL/Clock

Generator

64KB DARAM

256KB SARAM

128KB ROM

Power

Management

Multiplexing

Switched Central Resource (SCR)

Peripherals

Interconnect

App-Spec

Serial Interfaces

I²S

(x3)

10-Bit

DMA

(x4)

I²C

SPI

McSPI

UART

SAR

ADC

McBSP

Connectivity

System

Program/Data Storage

USB 2.0

PHY (HS)

[DEVICE]

NAND, NOR,

SRAM, mSDRAM

MMC/SD

(x2)

GP Timer

(x2)

GP Timer

or WD

LDOs

UHPI

RTC

图 1-1. 功能方框图

器件概述

3

TMS320C5517

ZHCS222C –AUGUST 2012–REVISED APRIL 2014

www.ti.com.cn

内容

1

器件概述.................................................... 1

1.1 特性 ................................................... 1

1.2 应用 ................................................... 2

1.3 说明 ................................................... 2

1.4 功能方框图............................................ 3

修订历史记录............................................... 5

Device Comparison ..................................... 6

Terminal Configuration and Functions.............. 8

4.1 Pin Diagram .......................................... 8

4.2 Signal Descriptions ................................... 9

4.3 Pin Multiplexing...................................... 51

4.4 Connections for Unused Signals.................... 55

Specifications ........................................... 56

5.1 Absolute Maximum Ratings......................... 56

5.2 Recommended Operating Conditions............... 57

5.3 Electrical Characteristics ............................ 58

5.4 Handling Ratings.................................... 60

5.5 Thermal Characteristics............................. 60

5.6 Power-On Hours .................................... 60

5.7 Timing and Switching Characteristics ............... 61

Detailed Description.................................. 153

6.1 CPU ................................................ 153

6.2 Memory ............................................ 153

6.3 Identification........................................ 181

6.4 Boot Modes ........................................ 182

Device and Documentation Support.............. 189

7.1 Device Support..................................... 189

7.2 Documentation Support............................ 191

7.3 社区资源 ........................................... 191

7.4 商标 ................................................ 191

7.5 静电放电警告....................................... 191

7.6 Glossary............................................ 191

6

2

3

4

7

8

5

Mechanical Packaging and Orderable

Information............................................. 192

4

内容

TMS320C5517

www.ti.com.cn

ZHCS222C –AUGUST 2012–REVISED APRIL 2014

2 修订历史记录

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

本数据手册修订历史记录强调了对之前版本的器件专用数据手册所做的技术更改。

参见

新增内容、修改内容和删除内容

全局

删除了 225MHz 器件信息。

修订历史记录

5

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Product Folder Links: TMS320C5517

TMS320C5517

ZHCS222C –AUGUST 2012–REVISED APRIL 2014

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3 Device Comparison

Table 3-1 provides characteristics of the C5517 processor.

The table shows significant features of the devices, including the capacity of on-chip RAM, the

peripherals, the CPU frequency, and the package type with pin count. For more detailed information on

the actual device part number and maximum device operating frequency, see Section 7.1.2, Device

Nomenclature.

Table 3-1. Characteristics of the Processor

HARDWARE FEATURES

C5517

Asynchronous (8- and 16-bit bus width) SRAM,

Flash (NOR, NAND),

External Memory Interface (EMIF)

SDRAM and Mobile SDRAM (16-bit bus width)⁽¹⁾

Peripherals

Not all peripheral pins

are available at the

same time (for more

detail, see Section 5).

Four DMA controllers each with four channels,

for a total of 16 channels

DMA

2 32-Bit General-Purpose (GP) Timers

Additional Timer Configurable as

1

a 32-Bit GP Timer or a

Watchdog

Timers

Each timer is capable of selecting its clock source among the

choices of:

•

External from a GPIO pin

System PLL

12.00 MHz USB oscillator

UART

SPI

1 (with RTS and CTS flow control)

1 with 4 chip selects (Master only)

1 (Master and Slave synchronous serial bus) with 3 chip selects

1 (A configurable 16-bit multiplexed host port interface)

1 (Master and Slave)

McSPI

UHPI

I²C

I²S

3 (Two Channel, Full Duplex Communication)

High- and Full-Speed Device (device mode only, host mode not

supported)

USB 2.0

2 MMC and SD, 256 byte read and write buffer, max 50-MHz clock

for SD cards, and signaling for DMA transfers

MMC and SD

McBSP

1 (with transmit and receive)

ADC (Successive Approximation [SAR])

Real-Time Clock (RTC)

FFT Hardware Accelerator

1 (10-bit, 4-input, 16-µs conversion time)

1 (Crystal Input, Separate Clock Domain and Power Supply)

1 (Supports 8 to 1024-point 16-bit real and complex FFT)

Up to 26 pins (with 1 Additional General-Purpose Output (XF) and 4

General-Purpose Outputs for Use With SAR)

General-Purpose Input/Output Port (GPIO)

•

64KB On-Chip Dual-Access RAM (DARAM)

256KB On-Chip Single-Access RAM (SARAM)

128KB On-Chip Single-Access ROM (SAROM)

On-Chip Memory

Size and Organization

•

JTAGID Register

(Value is: 0x0B95 602F)

JTAG BSDL_ID

CPU Frequency

see Figure 6-2

1.05-V Core

1.3-V Core

1.4-V Core

1.05-V Core

1.3-V Core

75 MHz

175 MHz

200 MHz

13.3 ns

MHz

Cycle Time

ns

5.71 ns

(1) For more information on SDRAM devices support, see Section 5.7.6, External Memory Interface (EMIF).

Device Comparison

6

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Table 3-1. Characteristics of the Processor (continued)

HARDWARE FEATURES

C5517

5 ns

1.4-V Core

1.05 V (75 MHz)

1.3 V (175 MHz)

1.4 V (200 MHz)

1.8 V, 2.75 V, 3.3 V

Core (V)

I/O (V)

Voltage

LDOs

1.3 V or 1.05 V, 250 mA max current for the digital core (to be used

only to supply CV_DD).

DSP_LDO

Cannot be used to drive CV_DDat the 1.4 V (>200 MHz) operating

range.

1.3 V, 4 mA max current for SAR and power management circuits

ANA_LDO

USB_LDO

(to be used only to supply V_{DDA_ANA}

)

1.3 V, 25 mA max current for USB core digital and PHY circuits (to

be used only to supply USB_V_DD1P3and USB_V_DDA1P3

TMS320C5517AZCH20

)

Commercial Temperature (default)

Industrial Temperature

Phase Lock Loop

Temperature

TMS320C5517AZCHA20

PLL

1 (Software Programmable PLL)

196-Terminal BGA (ZCH), 0.65-mm Pitch

BGA Package

10 x 10 mm

Product Preview (PP),

Advance Information (AI),

or Production Data (PD)

Product Status⁽²⁾

PD

(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Device Comparison

7

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Product Folder Links: TMS320C5517

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ZHCS222C –AUGUST 2012–REVISED APRIL 2014

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4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the bottom view of the package pin assignments.

I2S2_FS/

I2S2_DX/

UART_CTS/ UART_TXD/

UHPI_HD[9]/ UHPI_HD[11]/ UHPI_HD[13]/ UHPI_HD[15]/

SPI_CS0/

UHPI_HCNTL0

EM_DQM1/

UHPI_HBE1

SPI_RX/ GP[12]/

UHPI_HD[0] UHPI_HD[2]

GP[15]/ GP[17]/

UHPI_HD[5] UHPI_HD[7]

SPI_CS2/

UHPI_HR_NW

DV

DDIO

P

N

M

L

DDEMIF

GP[19]/

SPI_CS0

GP[27]/

SPI_TX

GP[29]/

I2S3_FS

GP[31]/

I2S3_DX

I2S2_CLK/

I2S2_RX/

UART_RTS/ UART_RXD/

UHPI_HD[8]/ UHPI_HD[10]/ UHPI_HD[12]/ UHPI_HD[14]/

SPI_CLK/

UHPI_HINT

GP[21]/

EM_A[15]

EM_SDCKE/

UHPI_HHWIL

SPI_CS1/

UHPI_HCNTL1

SPI_CS3/

SPI_TX/

GP[13]/

GP[14]/

UHPI_HRDY UHPI_HD[1] UHPI_HD[3] UHPI_HD[4] UHPI_HD[6]

GP[16]/

DV

DDIO

GP[18]/

SPI_CLK

GP[20]/

SPI_RX

GP[28]/

I2S3_CLK

GP[30]/

I2S3_RX

MMC0_D1/ MMC0_CMD/

MMC1_D1/ MMC1_CLK/ MMC1_D0/

McSPI_SOMI/ McSPI_CLK/ McSPI_SIMO/

I2S0_RX/ I2S0_FS/

GP[3]/ GP[1]/

McBSP_DR McBSP_FSX

EMU1

EM_SDCLK

EM_D[12]

EM_D[14]

EM_CS3

EM_D[4]

EM_D[13]

EM_A[14]

EM_A[13]

EM_D[5]

XF

TCK

TDO

TDI

TRST

GP[9]

GP[6]

GP[8]

MMC0_D3/

GP[5]/

McBSP_

MMC0_D0/ MMC0_CLK/

MMC1_CMD/

McSPI_CS0/

GP[7]

MMC0_D2/

GP[4]/

McBSP_FSR

MMC1_D3/

McSPI_CS2/

GP[11]

I2S0_DX/

GP[2]/

I2S0_CLK/

GP[0]/

McBSP_DX McBSP_CLKX

EM_A[10]

CV

EMU0

TMS

DD

CLKR_CLKS

MMC1_D2/

McSPI_CS1/

GP[10]

EM_A[12]/

(CLE)

EM_A[11]/

(ALE)

EM_WAIT3

EM_D[6]

DV

V

CV

V

SS

DV

V

SS

K

J

DDIO

SS

DD

DDIO

GP[26]/

EM_A[20]

V

USB_VBUS USB_V

USB_DM

USB_DP

USB_MXO

LDOI

EM_A[8]

EM_WE

EM_A[9]

EM_A[7]

EM_D[15]

RSV1

RSV2

DD1P3

SS1P3

DV

V

CV

DD

V

DDEMIF

SS

USB_

V

DDA3P3

EM_WAIT5

USB_V

EM_D[7]

EM_D[0]

DV

V

SS

DV

CV

DD

H

G

F

DDEMIF

V

SSA1P3

DDA1P3

SSA3P3

GP[24]/

EM_A[18]

GP[25]/

EM_A[19]

EM_WAIT4

USB_V

USB_R1

USB_V

DDOSC

USB_MXI

DDPLL

SSREF

SSPLL

V

V_SS

SS

GP[23]/

EM_A[17]

DV

USB_V

USB_LDOO

LDOI

EM_A[6]

EM_D[2]

EM_D[8]

EM_D[10]

EM_CS4

EM_D[9]

EM_OE

SSOSC

CV_DD

DV

DDRTC

V

SS

V

SS

DDIO

GP[22]/

EM_A[16]

DSP_LDOO

EM_D[1]

WAKEUP

DV

INT1

V

SS

V

SS

E

D

C

B

A

EM_A[2]

EM_A[5]

DDEMIF

RESET

INT0

SS

RTC_

CLKOUT

DSP_

LDO_EN

V

SSA_PLL

EM_WAIT2

GPAIN0

RSV16

RSV5

RSV3

RSV4

EM_A[3]

EM_A[1]

EM_A[0]

EM_D[3]

EM_D[11]

V

SS

V

CV

DDA_PLL

EM_CS2

DDRTC

EM_A[4]

CLK_SEL

SSRTC

GPAIN3

GPAIN2

RSV0

LDOI

V

SSA_ANA

EM_BA[1]

EM_CS0/

UHPI_HDS1

EM_DQM0/

UHPI_HBE0

RTC_XI

SSA_ANA

BG_CAP

EM_R/W

EM_SDCAS/

UHPI_HCS

SCL

SDA

EM_BA[0]

EM_CS1/

UHPI_HDS2

RTC_XO

V

ANA_LDOO

GPAIN1

DV

EM_CS5

DV

EM_SDRAS/

UHPI_HAS

DDA_ANA

CLKOUT

CLKIN

DDEMIF

V

SS

V

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to

GP[21] when reset).

Figure 4-1. Pin Diagram

8

Terminal Configuration and Functions

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4.2 Signal Descriptions

The signal descriptions tables (Table 4-1 through Table 4-19) identify the external signal names, the

associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin

has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more

information on pin multiplexing, see Section 4.3, Pin Multiplexing.

For proper device operation, external pullup and pulldown resistors may be required on some pins.

Section 5.7.20.1.1, Pullup and Pulldown Resistors discusses situations where external pullup and

pulldown resistors are required.

Terminal Configuration and Functions

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4.2.1 Oscillator and PLL

Table 4-1. Oscillator and PLL Signal Descriptions

TYPE⁽¹⁾

SIGNAL

NAME

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap

different clocks within the system clock generator. The CLKOUT_SRC bits in the

CLKOUT Configuration Register (CLKOUTCR) can be used to specify the

CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be

controlled by the Output Slew Rate Control Register (OSRCR) [0x1C16].

The output driver of the CLKOUT pin is enabled and disabled through the

CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin's

output driver is placed in high-impedance (Hi-Z) and the IPD is automatically

enabled. When enabled, the output driver of the pin is enabled and the IPD is

automatically disabled.

IPD

DV_DDIO

BH

CLKOUT

A7

O/Z

At reset the CLKOUT pin is enabled until the beginning of the boot sequence, at

which point the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is

disabled (Hi-Z). For more information on the ST3_55 register, see the C55x 3.0

CPU Reference Guide [literature number: SWPU073].

The IPD resistor on this pin is enabled when CLKOUT is in Hi-Z state.

Input clock. This signal is used to input an external clock when the 12-MHz on-

chip USB oscillator is not used as the system clock (CLK_SEL = 1).

To appropriately set the various serial port frequencies during bootloading, the

bootloader ROM code assumes CLKIN is running at the frequency indicated by

the setting (see Section 6.4, Boot Modes, for the supported frequencies and

details about the bootmode).

IPD

DV_DDIO

BH

CLKIN

A8

I

The CLK_SEL pin selects the source for the system clock generator, with the

options being the USB oscillator (CLK_SEL=0) or CLKIN (CLK_SEL=1) pins.

When the CLK_SEL pin is low, this pin should be tied to ground (V_SS). When

CLK_SEL is high, this pin should be driven by an external clock source.

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD disabled at reset.

Clock input select. This pin selects between the on-chip USB oscillator or CLKIN.

0 = The on-chip USB oscillator is enabled at reset and drives the system clock

generator. The CLKIN is ignored. Also, the USB LDOO is enabled at reset

(USB_LDO_EN=1). The on-chip USB oscillator and USB_LDO cannot be disabled

if CLK_SEL=0.

–

CLK_SEL

C7

I

DV_DDIO

BH

1 = CLKIN drives the system clock generator. The on-chip USB oscillator and USB

LDO are disabled at reset (USB_LDO_EN=1), but they can be enabled by

software.

This pin is not allowed to change during device operation; it must be tied high or

low at the board.

1.3-V Analog PLL power supply for the system clock generator.

see Section 5.2,

ROC

V_{DDA_PLL}

C10

D9

PWR

GND

This supply pin must not be connected to ANA_LDOO pin. The supply pin must be

externally powered.

see Section 5.2,

ROC

V_{SSA_PLL}

Analog PLL ground for the system clock generator.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.

Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where

external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

10

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4.2.2 Real-Time Clock (RTC)

Table 4-2. RTC Signal Descriptions

TYPE⁽¹⁾

SIGNAL

OTHER^{(3) (4)}

DESCRIPTION

(2)

NAME

NO.

Real-time clock oscillator output. This pin operates at the RTC core voltage,

CV_DDRTC, and supports a 32.768-kHz crystal.

If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to

CV_DDRTCand RTC_XO to ground (V_SS).

–

RTC_XO

A9

O/Z

CV_DDRTC

DV_DDRTC

A voltage must still be applied to CV_DDRTCby an external power source (see

Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can

power CV_DDRTC

.

Note: When RTC oscillator is disabled, the RTC registers (I/O address range

1900h – 197Fh) are not accessible.

Real-time clock oscillator input.

If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to

CV_DDRTCand RTC_XO to ground (V_SS).

–

A voltage must still be applied to CV_DDRTCby an external power source (see

Section 5.2, Recommended Operating Conditions). None of the on-chip LDOs can

RTC_XI

B9

I

CV_DDRTC

DV_DDRTC

power CV_DDRTC

.

Note: When RTC oscillator is disabled, the RTC registers (I/O address range

1900h – 197Fh) are not accessible.

Real-time clock output pin. This pin operates at DV_DDRTCvoltage.

–

The RTC_CLKOUT pin is enabled and disabled through the RTCCLKOUTEN bit in

the RTC Power Management Register (RTCPMGT).

RTC_CLKOUT

WAKEUP

D8

E8

O/Z

DV_DDRTC

At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]).

The active-high pin is used to WAKEUP the core from idle condition. This pin

defaults to an input at CV_DDRTCpowerup, but can also be configured as an active-

low open-drain output signal to wakeup an external device from an RTC alarm.

–

I/O/Z

DV_DDRTC

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.

Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where

external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

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4.2.3 RESET, Interrupts, and JTAG

Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions

SIGNAL

NAME

TYPE^{(1) (2)}OTHER^{(3) (4)}

DESCRIPTION

NO.

RESET

External Flag Output. XF is used for signaling other processors in

multiprocessor configurations or XF can be used as a fast general-

purpose output pin.

XF is set high by the BSET XF instruction and XF is set low by the

BCLR XF instruction or by writing to bit 13 of the ST1_55 register. For

more information on the ST1_55 register, see the C55x 3.0 CPU

Reference Guide [literature number: SWPU073].

IPU

DV_DDIO

BH

XF

M8

O/Z

For the XF pin's states after reset, see Figure 5-9, BootMode Latching.

XF pin can manually configured as Hi-Z state only in boundary-scan

mode. When this pin is in Hi-Z state, the IPU is enabled.

The IPU on this pin is disabled at reset.

Device reset. RESET causes the DSP to terminate execution and loads

the program counter with the contents of the reset vector. When

RESET is brought to a high level, the reset vector in ROM at FFFF00h

forces the program execution to branch to the location of the on-chip

ROM bootloader.

IPU

DV_DDIO

BH

RESET

D6

I

RESET affects the various registers and status bits.

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h).

The IPU is disabled at reset.

JTAG

For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference [literature number:

SPRU589].

IEEE standard 1149.1 test mode select. This serial control input is

clocked into the TAP controller on the rising edge of TCK.

If the emulation header is located greater than 6 inches from the

device, TMS must be buffered. In this case, the input buffer for TMS

needs a pullup resistor connected to DV_DDIOto hold the signal at a

known value when the emulator is not connected. A resistor value of

4.7 kΩ or greater is suggested. For board design guidelines related to

the emulation header, see the XDS560 Emulator Technical Reference

[literature number: SPRU589].

IPU

DV_DDIO

BH

TMS

L8

I

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is enabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.

Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where

external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

12

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Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)

SIGNAL

TYPE^{(1) (2)}OTHER^{(3) (4)}

DESCRIPTION

NAME

NO.

IEEE standard 1149.1 test data output. The contents of the selected

register (instruction or data) are shifted out of TDO on the falling edge

of TCK. TDO is in the high-impedance (Hi-Z) state except when the

scanning of data is in progress.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference [literature number: SPRU589].

If the emulation header is located greater than 6 inches from the

device, TDO must be buffered.

IPU

DV_DDIO

BH

Despite the fact that the IEEE 1149.1 (JTAG) standard defines the TDO

pin as a 3-state output (O/Z), this device has a bidirectional IO-cell. The

bidirectional cell's input buffer is used for non-JTAG production test

purposes. To achieve the lowest power, this input buffer must not be

allowed to float.

TDO

M7

I/O/Z

The IEEE standard defines the pin as tri-stated in the Test-Logic-Reset

state and our device obeys that requirement. Therefore, to achieve the

lowest power the IPU should remain enabled.

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is enabled at reset.

IEEE standard 1149.1 test data input. TDI is clocked into the selected

register (instruction or data) on a rising edge of TCK.

If the emulation header is located greater than 6 inches from the

device, TDI must be buffered. In this case, the input buffer for TDI

needs a pullup resistor connected to DV_DDIOto hold this signal at a

known value when the emulator is not connected. A resistor value of

4.7 kΩ or greater is suggested.

IPU

DV_DDIO

BH

TDI

L7

I

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is enabled at reset.

IEEE standard 1149.1 test clock. TCK is normally a free-running clock

signal with a 50% duty cycle. The changes on input signals TMS and

TDI are clocked into the TAP controller, instruction register, or selected

test data register on the rising edge of TCK. Changes at the TAP output

signal (TDO) occur on the falling edge of TCK.

If the emulation header is located greater than 6 inches from the

device, TCK must be buffered.

IPU

DV_DDIO

BH

TCK

M6

I

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference [literature number: SPRU589].

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is enabled at reset.

IEEE standard 1149.1 reset signal for test and emulation logic. TRST,

when high, allows the IEEE standard 1149.1 scan and emulation logic

to take control of the operations of the device. If TRST is not connected

or is driven low, the device operates in its functional mode, and the

IEEE standard 1149.1 signals are ignored. The device will not operate

properly if this reset pin is never asserted low.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference [literature number: SPRU589].

IPD

DV_DDIO

BH

TRST

M9

I

It is recommended that an external pulldown resistor be used in

addition to the IPD -- especially if there is a long trace to an emulation

header.

The IPD resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPD is enabled at reset.

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Table 4-3. RESET, Interrupts, and JTAG Signal Descriptions (continued)

SIGNAL

NAME

TYPE^{(1) (2)}OTHER^{(3) (4)}

DESCRIPTION

NO.

Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator

system and is defined as input/output by way of the emulation logic.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference [literature number: SPRU589].

An external pullup to DV_DDIOis required to provide a signal rise time of

less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.

IPU

DV_DDIO

BH

EMU1

M5

I/O/Z

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference [literature number: SPRU589].

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is enabled at reset.

Emulator 0 pin. When TRST is driven low and then high, the state of

the EMU0 pin is latched and used to connect the JTAG pins (TCK,

TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when

the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the

latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an

interrupt to or from the emulator system and is defined as input/output

by way of the emulation logic.

IPU

DV_DDIO

BH

An external pullup to DV_DDIOis required to provide a signal rise time of

less than 10 µsec. A 4.7-kΩ resistor is suggested for most applications.

EMU0

L6

I/O/Z

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference [literature number: SPRU589].

The IPU resistor on this pin can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is enabled at reset.

EXTERNAL INTERRUPTS

IPU

DV_DDIO

BH

External interrupt inputs (INT1 and INT0). These pins are maskable via

INT1

INT0

E7

C6

I

their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt

mode bit. The pins can be polled and reset by their specific Interrupt

Flag Register (IFR1, IFR0).

IPU

DV_DDIO

BH

The IPU resistor on these pins can be enabled or disabled via the

PUDINHIBR2 (1C18h) register.

The IPU is disabled at reset.

14

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4.2.4 External Memory Interface (EMIF)

Table 4-4. EMIF Signal Descriptions

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)

Note: When accessing 8-bit Asynchronous memory:

•

Connect EM_A[20:0] to memory address pins [22:2]

Connect EM_BA[1:0] to memory address pins [1:0]

For 16-bit Asynchronous memory:

•

Connect EM_A[20:1] to memory address pins [20:1]

Connect EM_BA[1] to memory address pin [0]

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

external address pin 20.

IPD

DV_DDEMIF

BH

Mux control via the A20_MODE bit in the EBSR (see Figure 5-10).

GP[26]/

EM_A[20]

J3

G4

G2

F2

E2

I/O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD is disabled at reset.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

external address pin 19.

IPD

DV_DDEMIF

BH

Mux control via the A19_MODE bit in the EBSR (see Figure 5-10).

GP[25]/

EM_A[19]

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD is disabled at reset.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

external address pin 18.

IPD

DV_DDEMIF

BH

Mux control via the A18_MODE bit in the EBSR (see Figure 5-10).

GP[24]/

EM_A[18]

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD is disabled at reset.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

external address pin 17.

IPD

DV_DDEMIF

BH

Mux control via the A17_MODE bit in the EBSR (see Figure 5-10).

GP[23]/

EM_A[17]

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD is disabled at reset.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

external address pin 16.

IPD

DV_DDEMIF

BH

Mux control via the A16_MODE bit in the EBSR (see Figure 5-10).

GP[22]/

EM_A[16]

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD is disabled at reset.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.

Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where

external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

(5) Pins with multiple names default to the first, bolded name when reset (for example, GP[21]/EM_A[15] defaults to GP[21] when reset).

Terminal Configuration and Functions

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Table 4-4. EMIF Signal Descriptions (continued)

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

external address pin 15.

IPD

DV_DDEMIF

BH

Mux control via the A15_MODE bit in the EBSR (see Figure 5-10).

GP[21]/

EM_A[15]

N1

I/O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR2

(1C18h) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 14.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

EM_A[14]

EM_A[13]

M1

L1

I/O/Z

The IPD is disabled at reset.

This pin is the EMIF external address pin 13.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 12. When interfacing with NAND Flash,

this pin also acts as Command Latch Enable (CLE).

IPD

DV_DDEMIF

BH

EM_A[12]/

(CLE)

K1

K2

I/O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 11. When interfacing with NAND Flash,

this pin also acts as Address Latch Enable (ALE).

IPD

DV_DDEMIF

BH

EM_A[11]/

(ALE)

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 10.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

EM_A[10]

EM_A[9]

EM_A[8]

EM_A[7]

L2

J2

J1

H2

I/O/Z

The IPD is disabled at reset.

This pin is the EMIF external address pin 9.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 8.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 7.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

16

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Table 4-4. EMIF Signal Descriptions (continued)

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

This pin is the EMIF external address pin 6.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

EM_A[6]

F1

I/O/Z

The IPD is disabled at reset.

This pin is the EMIF external address pin 5.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

EM_A[5]

EM_A[4]

EM_A[3]

EM_A[2]

EM_A[1]

EM_A[0]

D1

C1

D2

E1

C2

B2

The IPD is disabled at reset.

This pin is the EMIF external address pin 4.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 3.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 2.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 1.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

This pin is the EMIF external address pin 0.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR5

(1C4Dh) register.

The IPD is disabled at reset.

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Table 4-4. EMIF Signal Descriptions (continued)

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

J4

EM_D[15]

EM_D[14]

EM_D[13]

EM_D[12]

EM_D[11]

EM_D[10]

EM_D[9]

EM_D[8]

EM_D[7]

EM_D[6]

EM_D[5]

EM_D[4]

EM_D[3]

EM_D[2]

EM_D[1]

EM_D[0]

K3

K4

L3

C4

D3

F4

E3

H3

K5

M2

L4

EMIF 16-bit bidirectional bus.

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR4

(1C4Ch) register.

I/O/Z

The IPD is disabled at reset.

D4

F3

E5

G3

EMIF chip select 5 output for use with asynchronous memories (that is, NOR flash,

NAND flash, or SRAM).

IPD

DV_DDEMIF

BH

EM_CS5

EM_CS4

EM_CS3

EM_CS2

A3

C3

M4

C5

O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is disabled at reset.

EMIF chip select 4 output for use with asynchronous memories (that is, NOR flash,

NAND flash, or SRAM).

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is disabled at reset.

EMIF NAND chip select 3 output for use with asynchronous memories (that is, NOR

flash, NAND flash, or SRAM).

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is disabled at reset.

EMIF NAND chip select 2 output for use with asynchronous memories (that is, NOR

flash, NAND flash, or SRAM).

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is disabled at reset.

EMIF asynchronous memory write enable output

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

EM_WE

EM_OE

H1

E4

O/Z

The IPD is disabled at reset.

EMIF asynchronous memory read enable output

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is disabled at reset.

18

Terminal Configuration and Functions

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Table 4-4. EMIF Signal Descriptions (continued)

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

EMIF asynchronous read and write output

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

EM_R/W

B6

O/Z

The IPD is disabled at reset.

IPD

DV_DDEMIF

BH

EM_DQM1/

UHPI_HBE1

These pins are multiplexed between EMIF and UHPI. For EMIF, asynchronous data

write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits.

P1

B5

B1

I/O/Z

O/Z

Mux control via the PPMODE bits in the EBSR.

IPD

DV_DDEMIF

BH

The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

EM_DQM0/

UHPI_HBE0

The IPD is disabled at reset.

IPD

DV_DDEMIF

BH

EMIF asynchronous bank address

EM_BA[1]

EM_BA[0]

16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device

address [23].

8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device

address [0].

IPD

DV_DDEMIF

BH

EMIF SDRAM and mSDRAM bank address.

A1

O/Z

The IPD resistor on these pins can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is disabled at reset.

EMIF wait state extension input 5 for EM_CS5

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

EM_WAIT5

EM_WAIT4

EM_WAIT3

EM_WAIT2

H4

G1

K6

D5

I

The IPD is enabled at reset.

EMIF wait state extension input 4 for EM_CS4

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is enabled at reset.

EMIF wait state extension input 3 for EM_CS3

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is enabled at reset.

EMIF wait state extension input 2 for EM_CS2

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR6

(1C4Fh) register.

The IPD is enabled at reset.

EMIF FUNCTIONAL PINS: SDRAM and mSDRAM ONLY

This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM

chip select 1 output

IPD

EM_CS1/

UHPI_HDS2

Mux control via the PPMODE bits in the EBSR.

DV_DDEMIF

A4

I/O/Z

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7

(1C50h) register.

The IPD is disabled at reset.

Terminal Configuration and Functions

19

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Table 4-4. EMIF Signal Descriptions (continued)

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM

chip select 0 output

IPD

DV_DDEMIF

BH

EM_CS0/

UHPI_HDS1

B3

I/O/Z

O/Z

Mux control via the PPMODE bits in the EBSR.

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7

(1C50h) register.

EMIF SDRAM and mSDRAM clock

IPD

DV_DDEMIF

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7

(1C50h) register.

EM_SDCLK

M3

N2

The IPD is disabled at reset.

This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM

clock enable

IPD

DV_DDEMIF

BH

EM_SDCKE/

UHPI_HHWIL

Mux control via the PPMODE bits in the EBSR.

I/O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7

(1C50h) register.

The IPD is disabled at reset.

This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM

row address strobe

IPD

DV_DDEMIF

BH

EM_SDRAS/

UHPI_HAS

Mux control via the PPMODE bits in the EBSR.

A6

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7

(1C50h) register.

The IPD is disabled at reset.

This pin is multiplexed between EMIF and UHPI. For EMIF, SDRAM and mSDRAM

column strobe

IPD

DV_DDEMIF

BH

EM_SDCAS/

UHPI_HCS

Mux control via the PPMODE bits in the EBSR.

B4

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR7

(1C50h) register.

The IPD is disabled at reset.

20

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4.2.5 Inter-Integrated Circuit (I2C)

Table 4-5. Inter-Integrated Circuit (I2C) Signal Descriptions

TYPE⁽¹⁾

SIGNAL

NAME

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

I2C

–

This pin is the I2C clock output. Per the I2C standard, an external pullup is required

on this pin.

SCL

SDA

B7

B8

I/O/Z

DV_DDIO

BH

–

This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup

is required on this pin.

DV_DDIO

BH

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder

(2) Input pins of type I, I/O, and I/O/Z are required to be driven at all times. To achieve the lowest power, these pins must not be allowed to

float. When they are configured as input or tri-stated, and not driven to a known state, they may cause an excessive IO-supply current.

Prevent this current by externally terminating it or enabling IPD and IPU, if applicable.

(3) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup and pulldown resistors and situations where

external pullup and pulldown resistors are required, see Section 5.7.20.1.1, Pullup and Pulldown Resistors.

(4) Specifies the operating I/O supply voltage for each signal

Terminal Configuration and Functions

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4.2.6 Inter-IC Sound (I2S)

Table 4-6. Inter-IC Sound (I2S0, I2S2, and I2S3) Signal Descriptions

TYPE⁽¹⁾

SIGNAL

NAME⁽⁵⁾

OTHER^{(3) (4)}

DESCRIPTION

(2)

NO.

Interface 0 (I2S0)

This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.

For I2S, it is I2S0 transmit data output I2S0_DX.

MMC0_D0/

I2S0_DX/

GP[2]/

IPD

DV_DDIO

BH

Mux control via the SP0MODE bits in the EBSR.

L9

I/O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1

(1C17h) register.

McBSP_DX

The IPD is disabled at reset.

This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.

For I2S, it is I2S0 clock input/output I2S0_CLK.

Mux control via the SP0MODE bits in the EBSR.

MMC0_CLK/

I2S0_CLK/

GP[0]/

IPD

DV_DDIO

BH

L10

M10

M11

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1

(1C17h) register.

McBSP_CLKX

The IPD is disabled at reset.

This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.

For I2S, it is I2S0 receive data input I2S0_RX.

Mux control via the SP0MODE bits in the EBSR.

MMC0_D1/

I2S0_RX/

GP[3]/

IPD

DV_DDIO

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1

(1C17h) register.

McBSP_DR

The IPD is disabled at reset.

This pin is multiplexed between MMC0, I2S0, McBSP and GPIO.

For I2S, it is I2S0 frame synchronization input/output I2S0_FS.

Mux control via the SP0MODE bits in the EBSR.

MMC0_CMD/

I2S0_FS/

GP[1]/

McBSP_FSX

IPD

DV_DDIO

BH

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR1

(1C17h) register.

The IPD is disabled at reset.

Interface 1 (I2S2)

This pin is multiplexed between I2S2, UHPI, GPIO, and SPI.

For I2S, it is I2S2 transmit data output I2S2_DX.

Mux control via the PPMODE bits in the EBSR.

I2S2_DX/

UHPI_HD[11]/

GP[27]/

IPD

DV_DDIO

BH

P12

I/O/Z

The IPD resistor on this pin can be enabled or disabled via the PUDINHIBR3

(1C19h) register.