TMS320C6202GLS-233_技术文档

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Highest Performance Fixed-Point Digital

Flexible Phase-Locked-Loop (PLL) Clock

Generator

Signal Processors (DSPs) TMS320C62x

– 5-, 4-, 3.33-ns Instruction Cycle Time

– 200-, 250-, 300-MHz Clock Rate

– Eight 32-Bit Instructions/Cycle

– 1600, 2000, 2400 MIPS

32-Bit Expansion Bus

– Glueless/Low-Glue Interface to Popular

PCI Bridge Chips

– Glueless/Low-Glue Interface to Popular

Synchronous or Asynchronous

Microprocessor Buses

– Master/Slave Functionality

– Glueless Interface to Synchronous FIFOs

and Asynchronous Peripherals

VelociTI Advanced Very Long Instruction

Word (VLIW) ’C62x CPU Core

– Eight Highly Independent Functional

Units:

– Six ALUs (32-/40-Bit)

– Two 16-Bit Multipliers (32-Bit Result)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

Multichannel Buffered Serial Ports

(McBSPs)

– Direct Interface to T1/E1, MVIP, SCSA

Framers

– ST-Bus-Switching Compatible

– Up to 256 Channels Each

– AC97-Compatible

– Serial-Peripheral Interface (SPI)

Compatible (Motorola )

Instruction Set Features

– Byte-Addressable (8-, 16-, 32-Bit Data)

– 32-Bit Address Range

– 8-Bit Overflow Protection

– Saturation

– Bit-Field Extract, Set, Clear

– Bit-Counting

– Normalization

Two 32-Bit General-Purpose Timers

†

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

352-Pin BGA Package (GJL) (’02/02B/03)

384-Pin BGA Package (GLS) (’02/02B/03)

On-Chip SRAM

– 1M-Bit (’C6204)

– 3M-Bit (’C6202/’C6202B)

– 7M-Bit (’C6203)

340-Pin BGA Package (GLW) (’C6204 only)

– Pin-Compatible With the GLS Package

Except Inner Row of Balls (Additional

32-Bit External Memory Interface (EMIF)

– Glueless Interface to Synchronous

Memories: SDRAM or SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

‡

Power and Ground Pins) are Removed

0.18-µm/5-Level Metal Process (’6202 only)

0.15-µm/5-Level Metal Process (’02B/03/04)

– CMOS Technology

Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

With an Auxiliary Channel

3.3-V I/Os, 1.8-V Internal (’C6202 only)

3.3-V I/Os, 1.5-V Internal (’C6202B/03/04)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments Incorporated.

Motorola is a trademark of Motorola, Inc.

†

‡

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

For more details, see the GLS/GLW BGA package bottom view.

This document contains information on products in more than one phase

of development. The status of each device is indicated on the page(s)

specifying its electrical characteristics.

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE (’C6202/02B/03 ONLY)

(BOTTOM VIEW)

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25

10 12 14 16 18 20 22 24 26

2

4

6

8

GLS 384-PIN BGA PACKAGE (’C6202/02B/03 ONLY)

GLW 340-PIN BGA PACKAGE (’C6204 ONLY)

(BOTTOM VIEW)

AB

Y

AA

W

U

R

N

L

V

T

P

M

K

J

H

F

G

E

C

A

D

B

1

3

5

7

9

11 13 15 17 19 21

2

4

6

8

10 12 14 16 18 20 22

These balls are NOT applicable for the ’C6204 devices GLW 340-pin BGA package.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

selection guide

Table 1 provides an overview of the TMS320C6202/02B/03/04 pin-compatible DSPs. The table shows

significant features of each device, including the capacity of on-chip RAM, the peripherals, the execution time,

and the package type with pin count, etc.

Table 1. TMS320C6202/02B/03/04 DSP Selection Guide

HARDWARE FEATURES

’C6202

’C6202B

’C6203

’C6204

EMIF

√

4-Channel With

Throughput

4-Channel With

Throughput

4-Channel With

Throughput

DMA

4-Channel

Enhancements

Peripherals

Expansion Bus

McBSPs

√

3

√

3

√

3

√

2

32-Bit Timers

Size (Bytes)

2

256K

384K

64K

Block 0:

128K Bytes

Mapped Program

Block 1:

128K Bytes

Cache/Mapped

Program

128K Bytes

Mapped Program

Block 1:

128K Bytes

Cache/Mapped

Program

256K Bytes Mapped

Program

Block 1:

128K Bytes

Cache/Mapped

Program

1 Block:

Internal Program

Memory

64K Bytes

Cache/Mapped

Program

Organization

Size (Bytes)

Organization

128K

512K

64K

2 Blocks:

Four 16-Bit Banks

per Block

2 Blocks:

Four 16-Bit Banks

per Block

2 Blocks:

Four 16-Bit Banks

per Block

2 Blocks:

Four 16-Bit Banks

per Block

Internal Data

Memory

50/50 Split

Frequency

Cycle Time

MHz

ns

200, 250

250

250, 300

200

4 ns (’6202-250)

5 ns (’6202-200)

3.33 ns (’6203-300)

4 ns (’6203-250)

4 ns (’6202B-250)

5 ns (’6204-200)

Core (V)

1.8

1.5

Voltage

I/O (V)

3.3

Bypass (x1)

√

x4

√

PLL Options:

In Both Packages

x8

–

√

–

x10

–

√

–

Additional

x6

–

√

–

PLL Options:

18 x 18 mm

Packages

x7

–

√

–

x9

–

√

–

(GLS/GLW only)

x11

–

√

–

27 x 27 mm

18 x 18 mm

352-pin GJL

384-pin GLS

352-pin GJL

384-pin GLS

352-pin GJL

384-pin GLS

–

BGA Package

340-pin GLW

Process

Technology

µm

0.18 µm (18C05)

0.15 µm (15C05)

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

Product Status

AI

PP

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

description

The TMS320C6202, TMS320C6202B, TMS320C6203, and TMS320C6204 devices are part of the

TMS320C62x fixed-point DSP family in the TMS320C6000 platform. The ’C62x devices are based on the

high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas

Instruments (TI ), making these DSPs an excellent choice for multichannel and multifunction applications.

The TMS320C62x DSP offers cost-effective solutions to high-performance DSP programming challenges. The

TMS320C6202B/’03 has a performance of up to 2400 million instructions per second (MIPS) at 300 MHz, while

the TMS320C6202 has a performance of up to 2000 MIPS at 250 MHz, and the TMS320C6204 has a

performance of up to 1600 MIPS at 200 MHz. The ’C6202/’02B/’03/’04 DSP possesses the operational flexibility

of high-speed controllers and the numerical capability of array processors. These processors have

32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight

functionalunitsprovidesixarithmeticlogicunits(ALUs)forahighdegreeofparallelismandtwo16-bitmultipliers

for a 32-bit result. The ’C6202/’02B/’03/’04 can produce two multiply-accumulates (MACs) per cycle. This gives

a total of 600 million MACs per second (MMACS) for the ’C6202B/’03 device, a total of 500 MMACS for the

’C6202 device, and a total of 400 MMACS for the ’C6204 device. The ’C6202/’02B/’03/’04 DSP also has

application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The TMS320C62x DSPs include an on-chip memory, with the ’C6203 device offering the most memory at

7 Mbits. Forthe’C6202/’02Bdevice, programmemoryconsistsoftwoblocks, witha128K-byteblockconfigured

as memory-mapped program space, and the other 128K-byte block user-configurable as cache or

memory-mapped program space. Data memory consists of two 64K-byte blocks of RAM. Similarly, the ’C6203

deviceprogrammemoryconsistsoftwoblocks, witha256K-byteblockconfiguredasmemory-mappedprogram

space, and the other 128K-byte block user-configurable as cache or memory-mapped program space. Data

memory consists of two 256K-byte blocks of RAM. For the ’C6204 device, program memory consists of a single

64K-byte block that is user-configured as cache or memory-mapped program space. Data memory consists of

two 32K-byte blocks of RAM.

The ’C6202/’02B/’03/’04 device has a powerful and diverse set of peripherals. The peripheral set includes

multichannel buffered serial ports (McBSPs), general-purpose timers, a 32-bit expansion bus (XB) that offers

ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit

externalmemoryinterface(EMIF)capableofinterfacingtoSDRAMorSBSRAMandasynchronousperipherals.

The ’C62x devices have a complete set of development tools which includes: a new C compiler, an assembly

optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source

code execution.

TI is a trademark of Texas Instruments Incorporated

Windows is a registered trademark of the Microsoft Corporation.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

’C62x device compatibility

The TMS320C6202, ’C6202B, ’C6203, and ’C6204 devices are pin-compatible; thus, making new system

designseasierandprovidingfastertimetomarket. Thefollowinglistsummarizesthe’C62xdevicecharacteristic

differences:

Core Supply Voltage (1.8 V versus 1.5 V)

PLL Options Availability

Table 1 identifies the available PLL multiply factors [e.g., CLKIN x1 (PLL bypassed), x4] for each of the

’C62x devices. For additional details on the PLL clock module, see the Clock PLL section of this data sheet.

On-Chip Memory Size

The ’C6202/’02B, ’C6203, and ’C6204 devices have different on-chip program memory and data memory

sizes (see Table 1).

McBSPs

The ’C6204 device has two McBSPs while the ’C6202/’02B/’03 devices have three McBSPs on-chip.

For a more detailed discussion on migration concerns, and similarities/differences between the ’C6202,

’C6202B, ’C6203, and ’C6204 devices, see the How to Begin Development and Migrate Across the

TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603) document.

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

functional and CPU block diagram (’C62x devices)

’C6202/’02B/’03/’04 Digital Signal Processors

SDRAM or

SBSRAM

Program

Access/Cache

Controller

32

Internal Program Memory

(see Table 1)

SRAM

External Memory

Interface (EMIF)

ROM/FLASH

I/O Devices

’C62x CPU

Timer 0

Timer 1

Instruction Fetch

Control

Registers

Instruction Dispatch

Instruction Decode

Control

Logic

Multichannel

Buffered Serial

Port 0

Data Path A

Data Path B

Test

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices

Codecs

A Register File

B Register File

In-Circuit

Emulation

Multichannel

Buffered Serial

Port 1

Interrupt

Control

.L1 .S1 .M1 .D1

.D2 .M2 .S2 .L2

Multichannel

Buffered Serial

†

Port 2

Direct Memory

Access Controller

(DMA)

Synchronous

FIFOs

Internal Data

Memory

Data

Access

Controller

32

Expansion

Bus

Power-

Down

Logic

(see Table 1)

I/O Devices

(see Table 1)

HOST CONNECTION

Master /Slave

TI PCI2040

Power PC

683xx

PLL

(see Table 1)

960

†

McBSP2 is not applicable for the ’C6204 device.

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

CPU description

The CPU fetches VelociTI axdvanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features

controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The

first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the

previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.

Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length

executepacketsareakeymemory-savingfeature, distinguishingthe’C62xCPUfromotherVLIWarchitectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

eachcontain1632-bitregistersforatotalof32general-purposeregisters. Thetwosetsoffunctionalunits, along

with two register files, compose sides A and B of the CPU (see the Functional and CPU Block Diagram and

Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that

side. Additionally, each side features a single data bus connected to all the registers on the other side, by which

the two sets of functional units can access data from the register files on the opposite side. While register access

by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,

register access using the register file across the CPU supports one read and one write per cycle.

Another key feature of the ’C62x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

’C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of

the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet

can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one

per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

CPU description (continued)

src1

src2

dst

long dst

long src

.L1

8

32

ST1

8

long src

long dst

dst

Register

File A

Data Path A

.S1

src1

(A0–A15)

src2

dst

src1

.M1

.D1

src2

LD1

dst

src1

src2

DA1

2X

1X

src2

src1

dst

DA2

.D2

LD2

src2

.M2

.S2

src1

dst

src2

Register

File B

(B0–B15)

Data Path B

src1

dst

long dst

long src

8

32

8

ST2

8

long src

long dst

dst

.L2

src2

src1

Control

Register

File

Figure 1. TMS320C62x CPU Data Paths

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

signal groups description

CLKIN

CLKOUT2

CLKOUT1

RESET

CLKMODE0

†

NMI

CLKMODE1

Clock/PLL

†

EXT_INT7

EXT_INT6

EXT_INT5

CLKMODE2

PLLV

PLLG

PLLF

Reset and

EXT_INT4

Interrupts

IACK

INUM3

INUM2

INUM1

TMS

TDO

TDI

IEEE Standard

1149.1

(JTAG)

Emulation

INUM0

TCK

TRST

EMU1

EMU0

DMAC3

DMAC2

DMAC1

DMAC0

DMA Status

RSV11

RSV10

RSV9

RSV8

’C6204

Only

Power-Down

Status

PD

RSV7

RSV6

RSV5

‡

Reserved

RSV4

RSV3

RSV2

RSV1

RSV0

Control/Status

†

‡

CLKMODE1 is NOT available on the ’C6202 device GJL package.

CLKMODE2 is NOT available on the GJL packages for the ’C6202/’02B/’03 devices.

RSV5 through RSV11 pins are used on the ’C6204 device only.

Figure 2. CPU Signals

9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

signal groups description (continued)

ARE

Asynchronous

Memory

32

AOE

AWE

ARDY

ED[31:0]

Data

Control

CE3

CE2

CE1

CE0

Memory Map

Space Select

SDA10

Synchronous

Memory

SDRAS/SSOE

SDCAS/SSADS

SDWE/SSWE

Control

20

EA[21:2]

Word Address

Byte Enables

BE3

BE2

BE1

BE0

HOLD

HOLD/

HOLDA

EMIF

(External Memory Interface)

TOUT1

TINP1

TOUT0

TINP0

Timer 1

Timer 0

Timers

McBSP1

Transmit

McBSP0

Transmit

CLKX1

FSX1

DX1

CLKX0

FSX0

DX0

CLKR1

FSR1

DR1

CLKR0

FSR0

DR0

Receive

Clock

Receive

Clock

CLKS1

CLKS0

N/A For ’C6204 Devices

McBSP2

Transmit

CLKX2

FSX2

DX2

CLKR2

FSR2

DR2

Receive

Clock

CLKS2

McBSPs

(Multichannel Buffered Serial Ports)

Figure 3. Peripheral Signals

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

signal groups description (continued)

32

XCLKIN

XFCLK

XD[31:0]

Data

Clocks

XBE3/XA5

XBE2/XA4

XBE1/XA3

XBE0/XA2

Byte-Enable

Control/

Address

XOE

XRE

XWE/XWAIT

XCE3

XCE2

I/O Port

Control

XRDY

Control

XCE1

XCE0

XHOLD

Arbitration

XHOLDA

XCS

XAS

XCNTL

XW/R

XBLAST

XBOFF

Host

Interface

Control

Expansion Bus

Figure 3. Peripheral Signals (Continued)

11

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GLW

GJL

CLOCK/PLL

Clock Input

Clock output at full device speed

Clock output at half of device speed

Used for synchronous memory interface

Clock mode selects

CLKIN

C12

B10

Y18

B10

Y18

I

CLKOUT1

AD20

O

CLKOUT2

AC19

B15

AB19

B12

AB19

B12

O

•

CLKMODE0

CLKMODE1

CLKMODE2

I

•

Selects what multiply factors of the input clock frequency the CPU frequency

equals.

§

C11

¶

A9

¶

A9

For more detail on CLKMODE pins and the PLL multiply factors, see the Clock

PLL section of this data sheet.

¶

A14

¶

A14

–

#

||

A

||

A

||

A

PLLV

D13

D14

C13

C11

C12

A11

C11

C12

A11

PLL analog V connection for the low-pass filter

CC

#

PLLG

PLLF

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

TMS

TDO

TDI

AD7

AE6

AF5

AE5

AC7

AF6

AC8

Y5

I

JTAG test-port mode select (features an internal pullup)

JTAG test-port data out

AA4

Y4

AA4

Y4

O/Z

I

JTAG test-port data in (features an internal pullup)

JTAG test-port clock

TCK

AB2

AA3

AA5

AB4

AB2

AA3

AA5

AB4

TRST

EMU1

EMU0

JTAG test-port reset (features an internal pulldown)

Emulation pin 1, pullup with a dedicated 20-kΩ resistor

Emulation pin 0, pullup with a dedicated 20-kΩ resistor

RESET AND INTERRUPTS

I/O/Z

RESET

NMI

K2

L2

J3

I

Device reset

Nonmaskable interrupt

K2

•

Edge-driven (rising edge)

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

IACK

V4

Y2

U2

U3

W1

V2

V1

R3

T1

T2

T3

U2

U3

W1

V2

V1

R3

T1

T2

T3

External interrupts

Edge-driven (rising edge)

I

•

AA1

W4

Y1

O

Interrupt acknowledge for all active interrupts serviced by the CPU

Active interrupt identification number

INUM3

V2

INUM2

U4

V3

•

Valid during IACK for all active interrupts (not just external)

Encoding order follows the interrupt-service fetch-packet ordering

INUM1

INUM0

W2

†

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

‡

§

¶

#

||

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

For the ’C6202 GJL package, the C11 pin is ground (V ).

SS

For the ’C6202 GLS and ’C6204 GLW packages, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.

PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.

A = Analog Signal (PLL Filter)

For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0

with a dedicated 20-kΩ resistor.

12

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GJL

GLW

POWER-DOWN STATUS

PD

AB2

Y2

O

Power-down modes 2 or 3 (active if high)

EXPANSION BUS

XCLKIN

XFCLK

XD31

XD30

XD29

XD28

XD27

XD26

XD25

XD24

XD23

XD22

XD21

XD20

XD19

XD18

XD17

XD16

XD15

XD14

XD13

XD12

XD11

XD10

XD9

A9

C8

I

Expansion bus synchronous host interface clock input

Expansion bus FIFO interface clock output

B9

A8

O

D15

B16

A17

B17

D16

A18

B18

D17

C18

A20

D18

C19

A21

D19

C20

B21

A22

D20

B22

E25

F24

E26

F25

G24

H23

F26

G25

J23

G26

H25

J24

K23

C13

A13

C14

B14

B15

C15

A15

B16

C16

A17

B17

C17

B18

A19

C18

B19

C19

B20

A21

C21

D20

B22

D21

E20

E21

D22

F20

F21

E22

G20

G21

G22

C13

A13

C14

B14

B15

C15

A15

B16

C16

A17

B17

C17

B18

A19

C18

B19

C19

B20

A21

C21

D20

B22

D21

E20

E21

D22

F20

F21

E22

Expansion bus data

•

Used for transfer of data, address, and control

Also controls initialization of DSP modes and expansion bus at reset via pullup/

pulldown resistors

(Note: Reserved boot configuration fields should be pulled down.)

– XCE[3:0] memory type

– XBLAST polarity

– XW/R polarity

– Asynchronous or synchronous host operation

– Arbitration mode (internal or external)

– FIFO mode

– Little endian/big endian

– Boot mode

I/O/Z

XD8

XD7

XD6

XD5

XD4

XD3

XD2

G20

G21

G22

XD1

XD0

†

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

13

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

EXPANSION BUS (CONTINUED)

Expansion bus I/O port memory space enables

†

GJL

GLW

XCE3

F2

E1

D2

B1

D3

C2

C5

A4

B5

C6

A6

C7

B7

C9

B6

D2

B1

D3

C2

C5

A4

B5

C6

A6

C7

B7

C9

B6

XCE2

O/Z

•

Enabled by bits 28, 29, and 30 of the word address

Only one asserted during any I/O port data access

XCE1

F3

XCE0

E2

XBE3/XA5

XBE2/XA4

XBE1/XA3

XBE0/XA2

XOE

C7

D8

A6

Expansion bus multiplexed byte-enable control/address signals

I/O/Z

•

Act as byte enable for host port operation

Act as address for I/O port operation

C8

A7

O/Z

I

Expansion bus I/O port output enable

XRE

C9

D10

A10

D9

Expansion bus I/O port read enable

XWE/XWAIT

XCS

Expansion bus I/O port write enable and host port wait signals

Expansion bus host port chip-select input

Expansion bus host port address strobe

XAS

I/O/Z

Expansion bus host control. XCNTL selects between expansion bus address or data

register

XCNTL

B10

B9

I

XW/R

D11

A5

B8

C4

B4

B8

C4

B4

I/O/Z

I

Expansion bus host port write/read enable. XW/R polarity selected at reset

Expansion bus host port ready (active low) and I/O port ready (active high)

Expansion bus host port burst last–polarity selected at reset

Expansion bus back off

XRDY

XBLAST

XBOFF

XHOLD

XHOLDA

B6

B11

B5

A10

A2

A10

A2

I/O/Z

Expansion bus hold request

D7

B3

Expansion bus hold acknowledge

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

CE3

CE2

CE1

CE0

BE3

BE2

BE1

BE0

AB25

AA24

AB26

AA25

Y24

Y21

W20

AA22

W21

V20

Y21

Memory space enables

W20

O/Z

•

Enabled by bits 24 and 25 of the word address

Only one asserted during any external data access

AA22

W21

V20

Byte-enable control

W23

AA26

Y25

V21

•

Decoded from the two lowest bits of the internal address

Byte-write enables for most types of memory

Can be directly connected to SDRAM read and write mask signal (SDQM)

O/Z

W22

U20

W22

U20

†

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

14

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GLW

GJL

EMIF – ADDRESS

EA21

J25

J26

H20

H21

H22

J20

H20

H21

H22

J20

EA20

EA19

EA18

EA17

EA16

EA15

EA14

EA13

EA12

EA11

EA10

EA9

L23

K25

L24

L25

M23

M24

M25

N23

P24

P23

R25

R24

R23

T25

T24

U25

T23

V26

J21

K21

K20

K22

L21

L20

L22

M20

M21

N22

N20

N21

P21

P20

R22

R21

K21

K20

K22

L21

L20

L22

M20

M21

N22

N20

N21

P21

P20

R22

R21

O/Z

External address (word address)

EA8

EA7

EA6

EA5

EA4

EA3

EA2

EMIF – DATA

ED31

ED30

ED29

ED28

ED27

ED26

ED25

ED24

ED23

ED22

ED21

ED20

ED19

ED18

ED17

ED16

ED15

ED14

AD8

AC9

Y6

AA6

AB6

Y7

Y6

AA6

AB6

Y7

AF7

AD9

AC10

AE9

AA7

AB8

Y8

AA7

AB8

Y8

AF9

AC11

AE10

AD11

AE11

AC12

AD12

AE12

AC13

AD14

AC14

AE15

AA8

AA9

Y9

AA8

AA9

Y9

I/O/Z

External data

AB10

Y10

AA10

AA11

Y11

AB10

Y10

AA10

AA11

Y11

AB12

Y12

AA12

AB12

Y12

AA12

†

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

15

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

EMIF – DATA (CONTINUED)

†

GLW

GJL

ED13

AD15

AC15

AE16

AD16

AE17

AC16

AF18

AE18

AC17

AD18

AF20

AC18

AD19

AF21

AA13

Y13

AA13

Y13

ED12

ED11

ED10

ED9

ED8

ED7

ED6

ED5

ED4

ED3

ED2

ED1

ED0

AB13

Y14

AB13

Y14

AA14

AA15

Y15

AA14

AA15

Y15

I/O/Z

External data

AB15

AA16

Y16

AB15

AA16

Y16

AB17

AA17

Y17

AB17

AA17

Y17

AA18

EMIF – ASYNCHRONOUS MEMORY CONTROL

ARE

V24

V25

U23

W25

T21

R20

T22

T20

T21

R20

T22

T20

O/Z

I

Asynchronous memory read enable

Asynchronous memory output enable

Asynchronous memory write enable

Asynchronous memory ready input

AOE

AWE

ARDY

EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL

SDA10

AE21

AE22

AF22

AC20

AA19

AB21

Y19

AA19

AB21

Y19

O/Z

SDRAM address 10 (separate for deactivate command)

SDRAM column-address strobe/SBSRAM address strobe

SDRAM row-address strobe/SBSRAM output enable

SDRAM write enable/SBSRAM write enable

SDCAS/SSADS

SDRAS/SSOE

SDWE/SSWE

AA20

EMIF – BUS ARBITRATION

HOLD

Y26

V23

V22

U21

V22

U21

I

Hold request from the host

HOLDA

O

Hold-request-acknowledge to the host

TIMERS

TOUT1

TINP1

TOUT0

TINP0

J4

G2

F1

H4

F2

F3

D1

E2

F2

F3

D1

E2

O

I

Timer 1 or general-purpose output

Timer 1 or general-purpose input

Timer 0 or general-purpose output

Timer 0 or general-purpose input

O

I

DMA ACTION COMPLETE STATUS

DMAC3

DMAC2

DMAC1

DMAC0

Y3

V3

W2

AA1

W3

V3

W2

AA1

W3

AA2

AB1

AA3

O

DMA action complete

†

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

16

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GJL

GLW

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

CLKS0

M4

M2

M3

R2

P4

N3

N4

K3

L2

K3

L2

I

External clock source (as opposed to internal)

Receive clock

CLKR0

CLKX0

DR0

I/O/Z

I

K1

M2

M3

M1

L3

K1

M2

M3

M1

L3

Transmit clock

Receive data

DX0

O/Z

I/O/Z

Transmit data

FSR0

FSX0

Receive frame sync

Transmit frame sync

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

CLKS1

CLKR1

CLKX1

DR1

G1

J3

H2

L4

J1

J2

K4

E1

G2

G3

H1

H2

H3

G1

E1

G2

G3

H1

H2

H3

G1

I

External clock source (as opposed to internal)

Receive clock

I/O/Z

I

Transmit clock

Receive data

DX1

O/Z

I/O/Z

Transmit data

FSR1

FSX1

Receive frame sync

Transmit frame sync

MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) (’C6202/’C6202B/’C6203 ONLY)

CLKS2

CLKR2

CLKX2

DR2

R3

T2

R4

V1

T4

U2

T3

N1

N2

N3

R2

R1

P3

P2

–

I

External clock source (as opposed to internal)

Receive clock

I/O/Z

I

Transmit clock

Receive data

DX2

O/Z

I/O/Z

Transmit data

FSR2

FSX2

Receive frame sync

Transmit frame sync

RESERVED FOR TEST

RSV0

RSV1

RSV2

RSV3

RSV4

L3

J2

I

Reserved for testing, pullup with a dedicated 20-kΩ resistor

Reserved (leave unconnected, do not connect to power or ground)

G3

E3

A12

C15

D12

B11

B13

C10

B11

B13

C10

I

O

ADDITIONAL RESERVED FOR TEST (’C6204 ONLY)

RSV5

RSV6

RSV7

RSV8

RSV9

RSV10

RSV11

–

N1

N2

N3

R2

R1

P3

P2

I

Reserved (leave unconnected)

I/O

I

O

I/O

†

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

17

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GJL

GLW

SUPPLY VOLTAGE PINS

A11

A16

B7

A3

A7

A3

A7

A16

A20

D4

A16

A20

D4

B8

B19

B20

C6

D6

D7

C10

C14

C17

C21

G4

D9

D10

D13

D14

D16

D17

D19

F1

D10

D13

D14

D16

D17

D19

F1

G23

H3

H24

K3

F4

K24

L1

F19

F22

G4

F19

F22

G4

L26

N24

P3

DV

G19

J4

G19

J4

S

3.3-V supply voltage (I/O)

DD

T1

J19

K4

J19

K4

T26

U3

K19

L1

K19

L1

U24

W3

M22

N4

M22

N4

W24

Y4

N19

P4

N19

P4

Y23

AD6

AD10

AD13

AD17

AD21

AE7

AE8

AE19

AE20

AF11

P19

T4

P19

T4

T19

U1

T19

U1

U4

U19

U22

W4

W6

W7

U19

U22

W4

W6

W7

†

‡

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

SUPPLY VOLTAGE PINS (CONTINUED)

†

GJL

GLW

AF16

–

W9

W10

W13

W14

W16

W17

W19

AB5

AB9

AB14

AB18

E7

W9

W10

W13

W14

W16

W17

W19

AB5

AB9

AB14

AB18

E7

–

DV

–

S

3.3-V supply voltage (I/O)

DD

–

A1

A2

A3

A24

A25

A26

B1

B2

B3

B24

B25

B26

C1

C2

C3

C4

C23

C24

C25

C26

D3

D4

D5

D22

D23

D24

E4

E23

AB4

E8

E10

E11

E12

E13

E15

E16

F7

E10

E11

E12

E13

E15

E16

–

F8

–

F9

–

F11

F12

F14

F15

F16

G5

–

1.5-V supply voltage (core) (’C6202B, ’C6203, and ’C6204 only)

1.8-V supply voltage (core) (’C6202 only)

CV

–

S

DD

–

G5

–

G6

G17

G18

H5

–

G18

H5

–

H6

H17

H18

J6

–

H18

–

J17

K5

–

K5

K18

L5

K18

L5

†

‡

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

19

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

SUPPLY VOLTAGE PINS (CONTINUED)

†

GJL

GLW

AB23

AC3

AC4

AC5

AC22

AC23

AC24

AD1

AD2

AD3

AD4

AD23

AD24

AD25

AD26

AE1

AE2

AE3

AE24

AE25

AE26

AF1

AF2

AF3

AF24

AF25

AF26

–

L6

L17

L18

M5

–

L18

M5

–

M6

M17

M18

N5

–

M18

N5

N18

–

N18

P6

P17

R5

–

R5

–

R6

R17

R18

T5

–

R18

T5

–

T6

1.5-V supply voltage (core) (’C6202B, ’C6203, and ’C6204 only)

1.8-V supply voltage (core) (’C6202 only)

CV

T17

T18

U7

–

S

DD

T18

–

U8

–

U9

–

U11

U12

U14

U15

U16

V7

–

V7

V8

V10

V11

V12

V13

V15

V16

–

V8

–

V10

V11

V12

V13

V15

V16

–

GROUND PINS

A4

A8

A1

A5

A1

A5

V

SS

GND

Ground pins

A13

A14

A12

A18

A12

A18

†

‡

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GLW

GJL

GROUND PINS (CONTINUED)

A15

A19

A23

B4

A22

B2

A22

B2

B21

C1

B21

C1

C3

C20

C22

D5

D8

D11

D12

D15

D18

E4

B12

B13

B14

B23

C5

C3

C20

C22

D5

D8

C11

C16

C22

D1

D11

D12

D15

D18

E4

D2

D6

E5

D21

D25

D26

E3

E6

E9

E14

E17

E18

E19

F5

E14

E17

E18

E19

F5

E24

F4

V

SS

GND

Ground pins

F23

H1

F6

–

H26

K1

F10

F13

F17

F18

H4

–

K26

M1

–

F18

H4

H19

J1

M26

N1

H19

J1

N2

N25

N26

P1

J5

J18

J22

K6

J18

J22

–

P2

P25

P26

R1

K17

L4

–

L4

L19

M4

M19

N6

L19

M4

M19

–

R26

U1

U26

†

‡

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

For the ’C6202 GJL package, the C11 pin is ground (V ). See CLKMODE1 (C11) description for all other ’C62x devices GJL packages.

SS

21

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

Signal Descriptions (Continued)

PIN NO.

GLS

SIGNAL

NAME

‡

DESCRIPTION

TYPE

†

GJL

GLW

GROUND PINS (CONTINUED)

W1

W26

AA4

AA23

AB3

AB24

AC1

AC2

AC6

AC21

AC25

AC26

AD5

AD22

AE4

AE13

AE14

AE23

AF4

AF8

AF10

AF12

AF13

AF14

AF15

AF17

AF19

AF23

–

N17

P1

–

P1

P5

P18

P22

R4

P18

P22

R4

R19

U5

R19

U5

U6

–

U10

U13

U17

U18

V4

–

U18

V4

V5

V6

V9

V14

V17

V18

V19

W5

V14

V17

V18

V19

W5

V

SS

GND

Ground pins

W8

W11

W12

W15

W18

Y1

W11

W12

W15

W18

Y1

Y3

–

Y20

Y22

AA2

AA21

AB1

AB3

AB7

AB11

AB16

AB20

AB22

Y20

Y22

AA2

AA21

AB1

AB3

AB7

AB11

AB16

AB20

AB22

–

†

‡

The GLW BGA package (’C6204 only) is a subset of the GLS package (’C6202/02B/03), with the inner row of core supply voltage (CV ) and

DD

ground (V ) pins removed (see the GLS/GLW BGA package bottom view).

SS

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

22

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

development support

TI offers an extensive line of development tools for the ’C6000 generation of DSPs, including tools to evaluate

the performance of the processors, generate code, develop algorithm implementations, and fully integrate and

debug software and hardware modules.

The following products support development of ’C6000-based applications:

Software Development Tools:

Assembly optimizer

Assembler/Linker

Simulator

Optimizing ANSI C compiler

Application algorithms

C/Assembly debugger and code profiler

Hardware Development Tools:

Extended development system (XDS ) emulator (supports ’C6000 multiprocessor system debug)

EVM (Evaluation Module)

The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about

development-support products for all TMS320 family member devices, including documentation. See this

document for further information on TMS320 documentation or any TMS320 support products from Texas

Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains

informationaboutTMS320-relatedproductsfromothercompaniesintheindustry. ToreceiveTMS320literature,

contact the Literature Response Center at 800/477-8924.

See Table 2 for a complete listing of development-support tools for the ’C6000. For information on pricing and

availability, contact the nearest TI field sales office or authorized distributor.

Table 2. TMS320C6000 Development-Support Tools

DEVELOPMENT TOOL

PLATFORM

Software

PART NUMBER

C Compiler/Assembler/Linker/Assembly Optimizer

Simulator

Win32

TMDX3246855-07

SPARC Solaris

Win32

TMDX3246555-07

TMDS3246851-07

TMDS3246551-07

TMDX324016X-07

Simulator

SPARC Solaris

Win32, Windows NT

Hardware

XDS510 Debugger/Emulation Software

†

XDS510 Emulator

PC

TMDS00510

‡

XDS510WS Emulator

SCSI

TMDS00510WS

Software/Hardware

PC/Win95/Windows NT

EVM Evaluation Kit

TMDX3260A6201

TMDX326006201

EVM Evaluation Kit (including TMDX3246855–07)

†

‡

Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.

Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.

XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.

Win32 and Windows NT are trademarks of Microsoft Corporation.

SPARC is a trademark of SPARC International, Inc.

Solaris is a trademark of Sun Microsystems, Inc.

23

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

device and development-support tool nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320

devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas

Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These

prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)

through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical

specifications

Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, GJL), the temperature range (for example, blank is the default commercial temperature range),

and the device speed range in megahertz (for example, -300 is 300 MHz). Figure 4 provides a legend for

reading the complete device name for any TMS320 family member.

24

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

device and development-support tool nomenclature (continued)

(A)

TMS 320

C

6203 GJL

–300

PREFIX

DEVICE SPEED RANGE

–100 MHz

TMX= Experimental device

TMP= Prototype device

TMS= Qualified device

SMJ = MIL-STD-883C

–150 MHz

–167 MHz

–200 MHz

–233 MHz

SM = High Rel (non-883C)

–250 MHz

–300 MHz

DEVICE FAMILY

320 = TMS320 family

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

Blank = 0°C to 90°C, commercial temperature

A

= –40°C to 105°C, extended temperature

†

PACKAGE TYPE

N

=

Plastic DIP

J

Ceramic DIP

TECHNOLOGY

JD

GB

FZ

FN

FD

PJ

PQ

PZ

Ceramic DIP side-brazed

Ceramic PGA

Ceramic CC

Plastic leaded CC

Ceramic leadless CC

100-pin plastic EIAJ QFP

132-pin plastic bumpered QFP

100-pin plastic TQFP

C = CMOS

E

F

=

CMOS EPROM

CMOS Flash EEPROM

PBK = 128-pin plastic TQFP

PGE = 144-pin plastic TQFP

GFN = 256-pin plastic BGA

GGU = 144-pin plastic BGA

GGP = 352-pin plastic BGA

GJC = 352-pin plastic BGA

GJL = 352-pin plastic BGA

GLS = 384-pin plastic BGA

GLW = 340-pin plastic BGA

DEVICE

’1x DSP:

10

14

15

16

17

’2x DSP:

’2xx DSP:

’3x DSP:

25

26

203

204

206

209

240

30

31

32

’4x DSP:

’5x DSP:

40

44

50

51

52

53

56

57

†

DIP

PGA

CC

=

Dual-In-Line Package

Pin Grid Array

Chip Carrier

’54x DSP:

’6x DSP:

541

542

543

545

546

548

=

QFP

Quad Flat Package

TQFP = Thin Quad Flat Package

BGA Ball Grid Array

6201

6204

6205

6211

6701

6711

6201B

6202

=

6202B

6203

Figure 4. TMS320 Device Nomenclature (Including TMS320C6202, ’C6202B, ’C6203, and ’C6204)

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement

through applications development. The types of documentation available include: data sheets, such as this

document, with design specifications; complete user’s reference guides for all devices; technical briefs;

development-support tools; and hardware and software applications. The following is a brief, descriptive list of

support documentation specific to the ’C6x devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of

the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface

(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced

direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and

power-down modes. This guide also includes information on internal data and program memories.

The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and

assembly code for ’C6x devices and includes application program examples.

The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the

’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the

debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.

The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes

the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both

by header file and alphabetically, provides a complete description of each, and gives code examples to show

how they are used.

TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly

language tools (assembler, linker, and other tools used to develop assembly language code), assembler

directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of

devices.

The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for

installing and operating the ’C6x evaluation module. It also includes support software documentation,

application programming interfaces, and technical reference material.

TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides

instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support

software documentation, application programming interfaces, and technical reference material.

TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical

reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software

documentation, application programming interface references, and hardware descriptions for the ’C62x

McEVM.

TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools

and APIs to analyze embedded real-time DSP applications.

Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer

development environment to build and debug embedded real-time DSP applications.

Code Composer Studio Tutorial(literaturenumberSPRU301)introducestheCodeComposerStudiointegrated

development environment and software tools.

26

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

documentation support (continued)

The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x

devices, associated development tools, and third-party support.

The How to Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application

report (literature number SPRA603) describes the migration concerns and identifies the similarites and

differences between the ’C6202, ’C6202B, ’C6203, and ’C6204 ’C6000 DSP devices.

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and

education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to

update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides

access to information pertaining to the TMS320 family, including documentation, source code, and object code

for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform

resource locator (URL).

27

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

clock PLL

All of the internal ’C62x clocks are generated from a single source through the CLKIN pin. This source clock

either drives the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.

To use the PLL to generate the CPU clock, the filter circuit shown in Figure 5 must be properly designed.

Toconfigurethe’C6202/’C6202B/’C6203/’C6204PLLclockforproper operation, see Figure 5, Table 3, Table 4,

Table 5, Table 6, Table 7, and Table 8. To minimize the clock jitter, a single clean power supply should power

both the ’C62x device and the external clock oscillator circuit. The minimum CLKIN rise and fall times should

also be observed. See the input and output clocks electrical section for input clock timing requirements.

3.3 V

3 OUT

’320C6202/’02B/’03/’04

PLLV

PLLF

÷ 1

÷ 2

CLKOUT1

CLKOUT2

R1

CPU Clock

1 IN

GND

2

PLLG

10 µF

0.1 µF C1 C2

(Bypass)

CLKIN

(For PLL Options, See Table 3 and Table 4)

NOTES: A. The ’C6202/’C6202B/’C6203/’C6204 PLL can generate CPU clock frequencies in the range of 130 MHz to the device’s maximum

clock rate (for example, the ’C6203 range is 130 MHz to 300 MHz). For frequencies below 130 MHz, the PLL should be configured

to operate in bypass mode.

B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal

has to be connected to a clean 3.3-V supply and the PLLG and PLLF terminals should be tied together.

C. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DV

D. EMI filter manufacturer TDK part number ACF451832-153-T

.

DD

Figure 5. ’C6202/’C6202B/’C6203/’C6204 PLL Block Diagram

28

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

clock PLL (continued)

†

Table 3. TMS320C6202/’02B/’03/’04 GLS/GLW Packages PLL Multiply and Bypass (x1) Options

GLS PACKAGE – 18 x 18 mm BGA (’C6202/’02B/’03 only)

GLW PACKAGE – 18 x 18 mm BGA (’C6204 only)

DEVICES AND PLL CLOCK OPTIONS

BIT (PIN NO.)

CLKMODE2 (A14)

CLKMODE1 (A9)

CLKMODE0 (B12)

‡

’C6202, ’C6204

Bypass (x1)

x4

’C6202B, ’C6203

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bypass (x1)

x4

x8

Bypass (x1)

x4

x10

x6

Value

Bypass (x1)

x4

x9

Bypass (x1)

x4

x7

x11

†

‡

f(CPU Clock) = f(CLKIN) x (PLL mode)

For the ’C6202 GLS and ’C6204 GLW packages, the CLKMODE2 (A14) and CLKMODE1 (A9) pins are internally unconnected.

†§

Table 4. TMS320C6202/’02B/’03 GJL Package PLL Multiply and Bypass (x1) Options

GJL PACKAGE 27 x 27 mm BGA

DEVICES AND PLL CLOCK OPTIONS

¶#

CLKMODE2 (N/A)

§¶

BIT (PIN NO.)

CLKMODE1 (C11)

CLKMODE0 (B15)

¶

’C6202

’C6202B, ’C6203

Bypass (x1)

x4

0

1

Bypass (x1)

x4

#

N/A

Value

1

0

1

x8

CLKMODE1 pin

(C11) Must Be

Grounded

x10

§#

†

§

f(CPU Clock) = f(CLKIN) x (PLL mode)

Note:TheC11pinisCLKMODE1onthe’C6202B/’03GJLpackageandagroundpin(V ) for the ’C6202 GJL package. If a ’C6202 GJL package

SS

is placed in a ’C6202B/’03 GJL board with the CLKMODE1 pin pulled to the non-default state (default is GND), current is drawn through the pullup

(3.3 V/ 20 kΩ or 165 µA). If a ’C6202 GJL package is placed in a ’C6202B/’03 board with the C11 pin directly connected to the V

plane

CC

for the PLL mode, a ground/power is shorted through the package. For more detailed information on device compatibility, see the How to

Begin Development and Migrate Across the TMS320C6202/6202B/6203/6204 DSPs application report (literature number SPRA603).

CLKMODE2 and CLKMODE1 pins are not available on the ’C6202 GJL package.

The CLKMODE2 pin is not available on the ’C6202B/’C6203 GJL package.

N/A = Not Applicable

¶

#

||

Table 5. TMS320C6202 PLL Component Selection Table

CPU CLOCK

FREQUENCY

(CLKOUT1)

CLKIN

RANGE

(MHz)

CLKOUT2

RANGE

(MHz)

TYPICAL

LOCK TIME

(µs)

R1

(Ω)

C1

(nF)

C2

(pF)

CLKMODE

RANGE (MHz)

x4

32.5–62.5

130–250

65–125

60.4

27

560

75

||

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

clock PLL (continued)

†

Table 6. TMS320C6202B PLL Component Selection Table

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

TYPICAL

LOCK TIME

(µs)

R1

(Ω)

C1

(nF)

C2

(pF)

‡

CLKMODE

x4

x6

32.5–62.5

21.7–41.7

18.6–35.7

16.3–31.3

14.4–27.8

13–25

x7

x8

130–250

65–125

60.4

27

560

75

x9

x10

x11

11.8–22.7

†

‡

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS device. The GJL device is restricted to x1, x4, x8, and x10 multiply factors.

†

Table 7. TMS320C6203 PLL Component Selection Table

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

TYPICAL

LOCK TIME

(µs)

R1

(Ω)

C1

(nF)

C2

(pF)

‡

CLKMODE

x4

x6

32.5–75

21.7–50

x7

18.6–42.9

16.3–37.5

14.4–33.3

13–30

x8

130–300

65–150

60.4

27

560

75

x9

x10

x11

11.8–27.3

†

‡

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

CLKMODE x1, x4, x6, x7, x8, x9, x10, and x11 apply to the GLS device. The GJL device is restricted to x1, x4, x8, and x10 multiply factors.

†

Table 8. TMS320C6204 PLL Component Selection Table

CLKIN

RANGE

(MHz)

CPU CLOCK

FREQUENCY

RANGE (MHz)

CLKOUT2

RANGE

(MHz)

TYPICAL

LOCK TIME

(µs)

R1

(Ω)

C1

(nF)

C2

(pF)

CLKMODE

x4

32.5–50

130–200

65–100

60.4

27

560

75

†

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

power-supply sequencing

For ’C6202B, ’C6203, and ’C6204 devices only, the 1.5-V supply powers the core and the 3.3-V supply powers

the I/O buffers. For the ’C6202 device only, the 1.8-V supply powers the core and the 3.3-V supply powers the

I/O buffers. For internal device reliability, there are no specific sequencing requirements between the core

supply and the I/O supply. The only constraint is that neither supply should be powered on for extended periods

of time if the other supply is below the valid operating voltage.

System-level issues, such as bus contention, may require supply sequencing to be implemented. In this case,

the core supply should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O

buffers have valid inputs from the core before the output buffers are powered up, thus preventing bus contention

with other chips on the board.

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

†

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Supply voltage range, CV

Supply voltage range, DV

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 2.3 V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

DD

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 90 C

C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

SS

.

recommended operating conditions

MIN NOM

1.425 1.5 1.575

1.71

MAX UNIT

’C6202B, ’C6203, and ’C6204 only

’C6202 only

CV

DV

Supply voltage (CORE)

V

DD

1.8

3.30

0

1.89

3.46

0

Supply voltage (I/O)

3.14

0

V

Supply ground

SS

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating case temperature

2.0

V

IH

IL

0.8

–8

8

V

I

mA

C

OH

OL

T

C

0

90

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

electrical characteristics over recommended ranges of supply voltage and operating case

temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level output voltage

Low-level output voltage

DV

= MIN,

I

= MAX

2.4

OH

DD

OH

OL

0.6

±10

V

OL

†

I

Input current

V = V

I

to DV

uA

SS

= DV

DD

or 0 V

I

Off-state output current

V

O

uA

OZ

DD

’C6202, CV

= NOM,

CPU clock = 200 MHz

520

mA

pF

DD

’C6202B, CV

CPU clock = 200 MHz

TBD

Supply current, CPU + CPU

DD

I

DD2V

‡

memory access

’C6203, CV

’C6204, CV

’C6202, CV

= NOM,

DD

TBD

390

’C6202B, CV

DD

= NOM,

TBD

70

‡

Supply current, peripherals

DD2V

DD3V

’C6203, CV

’C6204, CV

’C6202, DV

= NOM,

DD

’C6202B, DV

DD

= NOM,

TBD

‡

Supply current, I/O pins

’C6203, DV

’C6204, DV

= NOM,

DD

C

Input capacitance

Output capacitance

10

i

pF

o

†

‡

TMS and TDI are not included due to internal pullups. TRST is not included due to internal pulldown.

Measuredwithaverageactivity(50%high/50%lowpower). FormoredetailedinformationonCPU/peripheral/I/Oactivity, seetheTMS320C6000

Power Consumption Summary application report (literature number SPRA486).

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

PARAMETER MEASUREMENT INFORMATION

I

OL

Tester Pin

Electronics

Output

Under

Test

50 Ω

V

ref

†

= 30 pF

C

T

I

OH

†

Typical distributed load circuit capacitance

Figure 6. Test Load Circuit

signal transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

V

ref

= 1.5 V

Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

INPUT AND OUTPUT CLOCKS

†‡§

timing requirements for CLKIN (PLL used)

(see Figure 8)

-200

-250

MIN

-300

MIN

NO.

UNIT

MIN

5 * M

0.4C

MAX

1

2

3

4

t

Cycle time, CLKIN

4 * M

0.4C

3.33 * M

0.4C

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.4C

5

†

‡

§

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V

IH

M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11) For more detail, see the clock PLL section.

C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.

.

†§

timing requirements for CLKIN [PLL bypassed (x1)] (see Figure 8)

-200

MIN

-250

MIN

-300

NO.

UNIT

MAX

MIN

3.33

MAX

1

2

3

4

t

Cycle time, CLKIN

5

0.45C

4

0.45C

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.45C

0.6

†

§

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V

C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.

.

IH

1

4

2

CLKIN

3

4

Figure 8. CLKIN Timings

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

INPUT AND OUTPUT CLOCKS (CONTINUED)

†

timing requirements for XCLKIN (see Figure 9)

-200

-250

-300

NO.

UNIT

MIN MAX

4P

1

2

3

t

Cycle time, XCLKIN

ns

c(XCLKIN)

Pulse duration, XCLKIN high

Pulse duration, XCLKIN low

1.8P

w(XCLKINH)

1.8P

w(XCLKINL)

†

P = 1/CPU clock frequency in ns.

1

2

XCLKIN

3

Figure 9. XCLKIN Timings

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

INPUT AND OUTPUT CLOCKS (CONTINUED)

†

switching characteristics for CLKOUT2 (see Figure 10)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

2P + 0.7

P + 0.7

1

2

3

t

Cycle time, CLKOUT2

2P – 0.7

P – 0.7

ns

c(CKO2)

Pulse duration, CLKOUT2 high

Pulse duration, CLKOUT2 low

w(CKO2H)

w(CKO2L)

†

P = 1/CPU clock frequency in ns.

1

2

CLKOUT2

3

Figure 10. CLKOUT2 Timings

†‡

switching characteristics for XFCLK (see Figure 11)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

D * P – 0.7

MAX

1

2

3

t

Cycle time, XFCLK

D * P + 0.7

ns

c(XFCK)

Pulse duration, XFCLK high

Pulse duration, XFCLK low

(D/2) * P – 0.7 (D/2) * P + 0.7

w(XFCKH)

w(XFCKL)

†

‡

P = 1/CPU clock frequency in ns.

D = 8, 6, 4, or 2; FIFO clock divide ratio, user-programmable

1

2

XFCLK

3

Figure 11. XFCLK Timings

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

ASYNCHRONOUS MEMORY TIMING

†‡§¶

timing requirements for asynchronous memory cycles

(see Figure 12 – Figure 15)

-200

-250

-300

NO.

UNIT

MIN

MAX

3

4

t

Setup time, EDx valid before ARE high

Hold time, EDx valid after ARE high

Setup time, ARDY high before ARE low

Hold time, ARDY high after ARE low

Setup time, ARDY low before ARE low

Hold time, ARDY low after ARE low

Pulse width, ARDY high

0.5

3.5

ns

su(EDV-AREH)

h(AREH-EDV)

6

–[(RST – 3) * P – 5]

(RST – 3) * P + 3

–[(RST – 3) * P – 5]

(RST – 3) * P + 3

2P

su(ARDYH-AREL)

h(AREL-ARDYH)

su(ARDYL-AREL)

h(AREL-ARDYL)

w(ARDYH)

7

9

10

11

15

16

18

19

Setup time, ARDY high before AWE low

Hold time, ARDY high after AWE low

Setup time, ARDY low before AWE low

Hold time, ARDY low after AWE low

–[(WST – 3) * P – 5]

(WST – 3) * P + 3

–[(WST – 3) * P – 5]

(WST – 3) * P + 3

su(ARDYH-AWEL)

h(AWEL-ARDYH)

su(ARDYL-AWEL)

h(AWEL-ARDYL)

†

‡

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold

time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are

programmed via the EMIF CE space control registers.

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

§

¶

‡§¶#

switching characteristics for asynchronous memory cycles

(see Figure 12 – Figure 15)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

RS * P – 1

RH * P – 1

TYP

MAX

4P + 5

1

2

t

Output setup time, select signals valid to ARE low

Output hold time, ARE high to select signals invalid

Pulse width, ARE low

ns

osu(SELV-AREL)

oh(AREH-SELIV)

w(AREL)

5

RST * P

8

Delay time, ARDY high to ARE high

3P

WS * P – 1

WH * P – 1

d(ARDYH-AREH)

osu(SELV-AWEL)

oh(AWEH-SELIV)

w(AWEL)

12

13

14

17

Output setup time, select signals valid to AWE low

Output hold time, AWE high to select signals invalid

Pulse width, AWE low

WST * P

Delay time, ARDY high to AWE high

3P

d(ARDYH-AWEH)

‡

RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are

programmed via the EMIF CE space control registers.

§

¶

#

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use ARDY input to extend strobe width.

Selectsignals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0], with the exception that CEx can stay active for anadditional

7P ns following the end of the cycle.

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2 Strobe = 3

Hold = 2

CLKOUT1

CEx

1

2

1

2

BE[3:0]

EA[21:2]

3

4

ED[31:0]

AOE

1

2

5

6

7

ARE

AWE

ARDY

Figure 12. Asynchronous Memory Read Timing (ARDY Not Used)

Setup = 2 Strobe = 3

Not Ready

Hold = 2

CLKOUT1

CEx

1

2

BE[3:0]

EA[21:2]

3

4

ED[31:0]

AOE

1

9

2

8

10

ARE

AWE

11

ARDY

Figure 13. Asynchronous Memory Read Timing (ARDY Used)

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Setup = 2 Strobe = 3

Hold = 2

CLKOUT1

CEx

12

13

BE[3:0]

EA[21:2]

ED[31:0]

AOE

15

16

ARE

14

AWE

ARDY

Figure 14. Asynchronous Memory Write Timing (ARDY Not Used)

Setup = 2 Strobe = 3

Not Ready

Hold = 2

CLKOUT1

12

13

CEx

BE[3:0]

EA[21:2]

ED[31:0]

AOE

ARE

17

18

19

AWE

11

ARDY

Figure 15. Asynchronous Memory Write Timing (ARDY Used)

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (see Figure 16)

-200

MIN

-250

MIN

-300

MIN MAX

NO.

UNIT

MAX

Setup time, read EDx valid before CLKOUT2

high

7

8

t

2.5

1.5

2

1.7

1.5

ns

su(EDV-CKO2H)

Hold time, read EDx valid after CLKOUT2 high

1.5

h(CKO2H-EDV)

†‡

switching characteristics for synchronous-burst SRAM cycles (see Figure 16 and Figure 17)

-200

MIN

-250

MIN

-300

MIN

NO.

PARAMETER

UNIT

MAX

Output setup time, CEx valid

before CLKOUT2 high

1

2

3

4

5

6

t

P – 0.5

P – 4

P + 0.2

P – 3

P + 0.1

P – 2.3

P + 0.1

P – 2.3

P + 0.1

P – 2.3

ns

osu(CEV-CKO2H)

oh(CKO2H-CEV)

osu(BEV-CKO2H)

oh(CKO2H-BEIV)

osu(EAV-CKO2H)

oh(CKO2H-EAIV)

Output hold time, CEx valid after

CLKOUT2 high

Output setup time, BEx valid

before CLKOUT2 high

P – 0.5

P – 4

P + 0.2

P – 3

Output hold time, BEx invalid after

CLKOUT2 high

Output setup time, EAx valid

before CLKOUT2 high

P – 0.5

P – 4

P + 0.2

P – 3

Output hold time, EAx invalid after

CLKOUT2 high

Output setup time,

9

t

SDCAS/SSADS valid before

CLKOUT2 high

P – 0.5

P + 0.2

P + 0.1

ns

osu(ADSV-CKO2H)

Output hold time, SDCAS/SSADS

valid after CLKOUT2 high

10

11

12

13

14

15

16

t

P – 4

P – 0.5

P – 4

P – 3

P + 0.2

P – 3

P – 2.3

P + 0.1

P – 2.3

P + 0.1

P – 2.3

P + 0.1

P – 2.3

ns

oh(CKO2H-ADSV)

osu(OEV-CKO2H)

oh(CKO2H-OEV)

osu(EDV-CKO2H)

oh(CKO2H-EDIV)

osu(WEV-CKO2H)

oh(CKO2H-WEV)

Output setup time, SDRAS/SSOE

valid before CLKOUT2 high

Output hold time, SDRAS/SSOE

valid after CLKOUT2 high

Output setup time, EDx valid

P – 0.5

P – 4

P + 0.2

P – 3

§

before CLKOUT2 high

Output hold time, EDx invalid after

CLKOUT2 high

Output setup time, SDWE/SSWE

valid before CLKOUT2 high

P – 0.5

P – 4

P + 0.2

P – 3

Output hold time, SDWE/SSWE

valid after CLKOUT2 high

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate

the ED enable time.

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

CLKOUT2

1

2

CEx

3

4

6

BE[3:0]

BE1

BE2

A2

BE3

A3

BE4

5

A1

A4

8

EA[21:2]

ED[31:0]

7

Q1

Q2

Q3

10

Q4

9

†

SDCAS/SSADS

11

12

†

SDRAS/SSOE

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

Figure 16. SBSRAM Read Timing

CLKOUT2

1

2

CEx

BE[3:0]

3

4

6

BE1

BE2

A2

BE3

A3

BE4

A4

5

EA[21:2]

A1

13

14

10

Q1

Q2

Q3

Q4

ED[31:0]

9

†

SDCAS/SSADS

†

SDRAS/SSOE

SDWE/SSWE

15

16

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses.

Figure 17. SBSRAM Write Timing

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 18)

-200

-250

-300

NO.

UNIT

MIN MAX

7

8

t

Setup time, read EDx valid before CLKOUT2 high

Hold time, read EDx valid after CLKOUT2 high

1

3

0.5

3

0.5

2

ns

su(EDV-CKO2H)

h(CKO2H-EDV)

†‡

switching characteristics for synchronous DRAM cycles (see Figure 18–Figure 23)

-200

MIN

-250

MIN

-300

MIN MAX

NO.

PARAMETER

UNIT

MAX

Output setup time, CEx valid

before CLKOUT2 high

1

2

3

4

5

6

t

P – 1

P

P – 2.5

P

P + 0.6

P – 1.8

P + 0.6

P – 1.8

P + 0.6

P – 1.8

ns

osu(CEV-CKO2H)

oh(CKO2H-CEV)

osu(BEV-CKO2H)

oh(CKO2H-BEIV)

osu(EAV-CKO2H)

oh(CKO2H-EAIV)

Output hold time, CEx valid after

CLKOUT2 high

P – 3.5

P – 1

Output setup time, BEx valid

before CLKOUT2 high

Output hold time, BEx invalid after

CLKOUT2 high

P – 3.5

P – 1

P – 2.5

P

Output setup time, EAx valid

before CLKOUT2 high

Output hold time, EAx invalid after

CLKOUT2 high

P – 3.5

P – 2.5

Output setup time,

9

t

SDCAS/SSADS valid before

CLKOUT2 high

P – 1

P

P + 0.6

ns

osu(CASV-CKO2H)

Output hold time, SDCAS/SSADS

valid after CLKOUT2 high

10

11

12

13

14

15

16

17

18

t

P – 3.5

P – 1

P – 2.5

P

P – 1.8

P + 0.6

P – 1.8

P + 0.6

P – 1.8

P + 0.6

P – 1.8

P + 0.6

P – 1.8

ns

oh(CKO2H-CASV)

osu(EDV-CKO2H)

oh(CKO2H-EDIV)

osu(WEV-CKO2H)

oh(CKO2H-WEV)

osu(SDA10V-CKO2H)

oh(CKO2H-SDA10IV)

osu(RASV-CKO2H)

oh(CKO2H-RASV)

Output setup time, EDx valid

§

before CLKOUT2 high

Output hold time, EDx invalid after

CLKOUT2 high

P – 3.5

P – 1

P – 2.5

P

Output setup time, SDWE/SSWE

valid before CLKOUT2 high

Output hold time, SDWE/SSWE

valid after CLKOUT2 high

P – 3.5

P – 1

P – 2.5

P

Output setup time, SDA10 valid

before CLKOUT2 high

Output hold time, SDA10 invalid

after CLKOUT2 high

P – 3.5

P – 1

P – 2.5

P

Output setup time, SDRAS/SSOE

valid before CLKOUT2 high

Output hold time, SDRAS/SSOE

valid after CLKOUT2 high

P – 3.5

P – 2.5

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate

the ED enable time.

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

CLKOUT2

CEx

1

5

2

3

4

BE[3:0]

EA[15:2]

BE1

BE2

CA3

BE3

7

6

CA1

CA2

8

D1

D2

D3

ED[31:0]

SDA10

15

9

16

10

†

SDRAS/SSOE

†

SDCAS/SSADS

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 18. Three SDRAM READ Commands

WRITE

CLKOUT2

CEx

1

3

5

2

4

6

BE[3:0]

BE1

CA1

BE2

CA2

D2

BE3

CA3

D3

EA[15:2]

11

12

D1

ED[31:0]

SDA10

15

16

†

SDRAS/SSOE

9

10

14

†

SDCAS/SSADS

13

†

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 19. Three SDRAM WRT Commands

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

SYNCHRONOUS DRAM TIMING (CONTINUED)

ACTV

CLKOUT2

1

2

CEx

BE[3:0]

5

Bank Activate/Row Address

EA[15:2]

ED[31:0]

15

Row Address

SDA10

17

18

†

SDRAS/SSOE

SDCAS/SSADS

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 20. SDRAM ACTV Command

DCAB

CLKOUT2

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

15

16

SDA10

17

18

†

SDRAS/SSOE

SDCAS/SSADS

13

14

†

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 21. SDRAM DCAB Command

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

SYNCHRONOUS DRAM TIMING (CONTINUED)

REFR

CLKOUT2

CEx

1

2

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

17

18

†

SDRAS/SSOE

9

10

†

SDCAS/SSADS

†

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 22. SDRAM REFR Command

MRS

CLKOUT2

1

2

6

CEx

BE[3:0]

5

EA[15:2]

ED[31:0]

SDA10

MRS Value

17

18

10

14

†

SDRAS/SSOE

9

†

SDCAS/SSADS

13

SDWE/SSWE

†

SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.

Figure 23. SDRAM MRS Command

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

HOLD/HOLDA TIMING

†

timing requirements for the HOLD/HOLDA cycles (see Figure 24)

-200

-250

-300

NO.

UNIT

MIN MAX

3

t Hold time, HOLD low after HOLDA low

oh(HOLDAL-HOLDL)

P

ns

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

†‡

switching characteristics for the HOLD/HOLDA cycles (see Figure 24)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

4P

0

MAX

§

1

2

4

5

t

Response time, HOLD low to EMIF Bus high impedance

Delay time, EMIF Bus high impedance to HOLDA low

Response time, HOLD high to EMIF Bus low impedance

Delay time, EMIF Bus low impedance to HOLDA high

ns

R(HOLDL-EMHZ)

d(EMHZ-HOLDAL)

R(HOLDH-EMLZ)

d(EMLZ-HOLDAH)

2P

7P

2P

3P

0

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with

external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the

minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.

External Requestor

DSP Owns Bus

Owns Bus

3

HOLD

2

5

HOLDA

1

4

†

EMIF Bus

’C62x

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.

Figure 24. HOLD/HOLDA Timing

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

RESET TIMING

†

timing requirements for reset (see Figure 25)

-200

-250

-300

NO.

UNIT

MIN

MAX

‡

Width of the RESET pulse (PLL stable)

10P

250

5P

ns

µs

ns

1

t

w(RST)

§

Width of the RESET pulse (PLL needs to sync up)

¶

Setup time, XD configuration bits valid before RESET high

10

11

t

su(XD)

¶

Hold time, XD configuration bits valid after RESET high

5P

h(XD)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL

are stable.

§

¶

ThisparameterappliestoCLKMODEx4, x6, x7, x8, x9, x10, andx11only(ItdoesnotapplytoCLKMODEx1). TheRESETsignalisnotconnected

internally to the clock PLL circuit. The PLL, however, may need up to 250 µs to stabilize following device power up or after PLL configuration

has been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.

XD[31:0] are the boot configuration pins during device reset.

†#

switching characteristics during reset (see Figure 25)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

4P

2

3

4

5

6

7

8

9

t

Delay time, RESET low to CLKOUT2 invalid

Delay time, RESET high to CLKOUT2 valid

Delay time, RESET low to high group invalid

Delay time, RESET high to high group valid

Delay time, RESET low to low group invalid

Delay time, RESET high to low group valid

Delay time, RESET low to Z group high impedance

Delay time, RESET high to Z group valid

P

ns

d(RSTL-CKO2IV)

d(RSTH-CKO2V)

d(RSTL-HIGHIV)

d(RSTH-HIGHV)

d(RSTL-LOWIV)

d(RSTH-LOWV)

d(RSTL-ZHZ)

4P

d(RSTH-ZV)

†

#

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

High group consists of:

Low group consists of:

Z group consists of:

XFCLK, HOLDA

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,

SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,

FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,

and XHOLDA

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

RESET TIMING (CONTINUED)

CLKOUT1

1

10

11

RESET

2

3

5

7

9

CLKOUT2

4

†

HIGH GROUP

LOW GROUP

6

8

†

Z GROUP

Boot Configuration

‡

XD[31:0]

†

‡

High group consists of:

Low group consists of:

Z group consists of:

XFCLK, HOLDA

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,

SDA10, CLKX0, CLKX1, CLKX2, FSX0, FSX1, FSX2, DX0, DX1, DX2, CLKR0, CLKR1, CLKR2, FSR0, FSR1,

FSR2, XCE[3:0], XBE[3:0]/XA[5:2], XOE, XRE, XWE/XWAIT, XAS, XW/R, XRDY, XBLAST, XHOLD,

and XHOLDA.

XD[31:0] are the boot configuration pins during device reset.

Figure 25. Reset Timing

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXTERNAL INTERRUPT TIMING

†

timing requirements for interrupt response cycles (see Figure 26)

-200

-250

-300

NO.

UNIT

MIN

MAX

2

3

t

Width of the interrupt pulse low

Width of the interrupt pulse high

2P

ns

w(ILOW)

w(IHIGH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

†

switching characteristics during interrupt response cycles (see Figure 26)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

1

4

5

6

t

Response time, EXT_INTx high to IACK high

Delay time, CLKOUT2 low to IACK valid

Delay time, CLKOUT2 low to INUMx valid

Delay time, CLKOUT2 low to INUMx invalid

9P

0

ns

R(EINTH – IACKH)

d(CKO2L-IACKV)

d(CKO2L-INUMV)

d(CKO2L-INUMIV)

10

0

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

1

CLKOUT2

3

2

EXT_INTx, NMI

Intr Flag

4

IACK

6

5

INUMx

Interrupt Number

Figure 26. Interrupt Timing

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS FIFO TIMING

timing requirements for synchronous FIFO interface (see Figure 27, Figure 28, and Figure 29)

-200

-250

-300

MIN MAX

2.5

NO.

UNIT

5

6

t

Setup time, read XDx valid before XFCLK high

Hold time, read XDx valid after XFCLK high

ns

su(XDV-XFCKH)

2

h(XFCKH-XDV)

switching characteristics for synchronous FIFO interface (see Figure 27, Figure 28, and Figure 29)

’C6202B-250

’C6202B-300

’C6203-250

’C6203-300

’C6204-200

’C6202-200,

’C6202-250

NO.

PARAMETER

UNIT

MIN

MAX

MIN

1.5

MAX

4.5

1

2

3

4

7

8

9

t

Delay time, XFCLK high to XCEx valid

Delay time, XFCLK high to XBE[3:0]/XA[5:2] valid

Delay time, XFCLK high to XOE valid

Delay time, XFCLK high to XRE valid

1.5

5.2

ns

d(XFCKH-XCEV)

d(XFCKH-XAV)

d(XFCKH-XOEV)

d(XFCKH-XREV)

d(XFCKH-XWEV)

d(XFCKH-XDV)

d(XFCKH-XDIV)

†

1.5

‡

Delay time, XFCLK high to XWE/XWAIT valid

Delay time, XFCLK high to XDx valid

Delay time, XFCLK high to XDx invalid

1.5

†

‡

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

XFCLK

1

†

XCE3

2

3

4

2

3

‡

XA1

XA2

XA3

XA4

XBE[3:0]/XA[5:2]

XOE

XRE

4

§

XWE/XWAIT

6

5

XD[31:0]

FIFO read (glueless) mode only available in XCE3.

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

D1

D2

D3

D4

†

‡

§

Figure 27. FIFO Read Timing (Glueless Read Mode)

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS FIFO TIMING (CONTINUED)

XFCLK

XCEx

1

2

3

4

1

2

3

†

XBE[3:0]/XA[5:2]

XA1

XA2

XA3

XA4

XOE

XRE

4

‡

XWE/XWAIT

6

5

XD[31:0]

D1

D2

D3

D4

†

‡

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 28. FIFO Read Timing

XFCLK

1

XCEx

2

†

XBE[3:0]/XA[5:2]

XA1

XA2

XA3

XA4

XOE

XRE

7

8

7

‡

XWE/XWAIT

9

XD[31:0]

D1

D2

D3

D4

†

‡

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during synchronous FIFO accesses.

XWE/XWAIT operates as the write enable signal XWE during synchronous FIFO accesses.

Figure 29. FIFO Write Timing

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING

†‡§¶

timing requirements for asynchronous peripheral cycles

(see Figure 30–Figure 33)

-200

-250

-300

NO.

UNIT

MIN

MAX

3

4

t

Setup time, XDx valid before XRE high

Hold time, XDx valid after XRE high

Setup time, XRDY high before XRE low

Hold time, XRDY high after XRE low

Setup time, XRDY low before XRE low

Hold time, XRDY low after XRE low

Pulse width, XRDY high

4

1

ns

su(XDV-XREH)

h(XREH-XDV)

6

–[(RST – 3) * P – 5]

(RST – 3) * P + 3

–[(RST – 3) * P – 5]

(RST – 3) * P + 3

2P

su(XRDYH-XREL)

h(XREL-XRDYH)

su(XRDYL-XREL)

h(XREL-XRDYL)

w(XRDYH)

7

9

10

11

15

16

18

19

Setup time, XRDY high before XWE low

Hold time, XRDY high after XWE low

Setup time, XRDY low before XWE low

Hold time, XRDY low after XWE low

–[(WST – 3) * P – 5]

(WST – 3) * P + 3

–[(WST – 3) * P – 5]

(WST – 3) * P + 3

su(XRDYH-XWEL)

h(XWEL-XRDYH)

su(XRDYL-XWEL)

h(XWEL-XRDYL)

†

‡

To ensure data setup time, simply program the strobe width wide enough. XRDY is internally synchronized. If XRDY does meet setup or hold

time, it may be recognized in the current cycle or the next cycle. Thus, XRDY can be an asynchronous input.

RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are

programmed via the XBUS XCE space control registers.

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

§

¶

‡§¶#

switching characteristics for asynchronous peripheral cycles

(see Figure 30–Figure 33)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

RS * P – 1

RH * P – 1

TYP

MAX

4P + 5

1

2

t

Output setup time, select signals valid to XRE low

Output hold time, XRE low to select signals invalid

Pulse width, XRE low

ns

osu(SELV-XREL)

oh(XREH-SELIV)

w(XREL)

5

RST * P

WST * P

8

Delay time, XRDY high to XRE high

3P

WS * P – 1

WH * P – 1

d(XRDYH-XREH)

osu(SELV-XWEL)

oh(XWEH-SELIV)

w(XWEL)

12

13

14

17

Output setup time, select signals valid to XWE low

Output hold time, XWE low to select signals invalid

Pulse width, XWE low

Delay time, XRDY high to XWE high

3P

d(XRDYH-XWEH)

‡

RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold. These parameters are

programmed via the XBUS XCE space control registers.

§

¶

#

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

The sum of RS and RST (or WS and WST) must be a minimum of 4 in order to use XRDY input to extend strobe width.

Select signals include: XCEx, XBE[3:0], XA[5:2], XOE; and for writes, include XD[31:0], with the exception that XCEx can stay active for an

additional 7P ns following the end of the cycle.

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)

Setup = 2 Strobe = 3

Hold = 2

CLKOUT1

1

2

XCEx

XBE[3:0]/

†

XA[5:2]

3

4

XD[31:0]

XOE

1

2

5

6

7

XRE

‡

XWE/XWAIT

§

XRDY

†

‡

§

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.

XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 30. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Not Used)

Setup = 2 Strobe = 3

Not Ready

Hold = 2

CLKOUT1

1

2

XCEx

XBE[3:0]/

†

XA[5:2]

3

4

XD[31:0]

XOE

1

9

2

8

10

XRE

‡

XWE/XWAIT

11

§

XRDY

†

‡

§

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.

XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 31. Expansion Bus Asynchronous Peripheral Read Timing (XRDY Used)

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING (CONTINUED)

Setup = 2 Strobe = 3

Hold = 2

CLKOUT1

XCEx

12

13

XBE[3:0]/

†

XA[5:2]

12

13

XD[31:0]

XOE

XRE

15

16

14

‡

§

XWE/XWAIT

XRDY

†

‡

§

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.

XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 32. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Not Used)

Setup = 2 Strobe = 3

Not Ready

Hold = 2

CLKOUT1

12

13

XCEx

XBE[3:0]/

†

XA[5:2]

12

13

XD[31:0]

XOE

XRE

17

18

19

‡

XWE/XWAIT

11

§

XRDY

†

‡

§

XBE[3:0]/XA[5:2] operates as address signals XA[5:2] during expansion bus asynchronous peripheral accesses.

XWE/XWAIT operates as the write enable signal XWE during expansion bus asynchronous peripheral accesses.

XRDY operates as active-high ready input during expansion bus asynchronous peripheral accesses.

Figure 33. Expansion Bus Asynchronous Peripheral Write Timing (XRDY Used)

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING

timing requirements with external device as bus master (see Figure 34 and Figure 35)

-200

-250

-300

NO.

UNIT

MIN MAX

1

2

3

4

t

Setup time, XCS valid before XCLKIN high

Hold time, XCS valid after XCLKIN high

Setup time, XAS valid before XCLKIN high

Hold time, XAS valid after XCLKIN high

4

ns

su(XCSV-XCKIH)

h(XCKIH-XCS)

su(XAS-XCKIH)

h(XCKIH-XAS)

2.3

4

2.3

5

6

t

Setup time, XCNTL valid before XCLKIN high

Hold time, XCNTL valid after XCLKIN high

4

2.3

4

ns

su(XCTL-XCKIH)

h(XCKIH-XCTL)

su(XWR-XCKIH)

h(XCKIH-XWR)

su(XBLTV-XCKIH)

h(XCKIH-XBLTV)

†

Setup time, XW/R valid before XCLKIN high

7

†

8

Hold time, XW/R valid after XCLKIN high

Setup time, XBLAST valid before XCLKIN high

2.3

4

‡

9

‡

10

Hold time, XBLAST valid after XCLKIN high

Setup time, XBE[3:0]/XA[5:2] valid before XCLKIN high

2.3

§

16

17

18

19

t

4

2.3

4

ns

su(XBEV-XCKIH)

h(XCKIH-XBEV)

su(XD-XCKIH)

h(XCKIH-XD)

§

Hold time, XBE[3:0]/XA[5:2] valid after XCLKIN high

Setup time, XDx valid before XCLKIN high

Hold time, XDx valid after XCLKIN high

2.3

†

‡

§

XW/R input/output polarity selected at boot.

XBLAST input polarity selected at boot.

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

¶

switching characteristics with external device as bus master (see Figure 34 and Figure 35)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

11

12

13

14

15

20

21

t

Delay time, XCLKIN high to XDx low impedance

Delay time, XCLKIN high to XDx valid

5

ns

d(XCKIH-XDLZ)

d(XCKIH-XDV)

d(XCKIH-XDIV)

d(XCKIH-XDHZ)

d(XCKIH-XRY)

d(XCKIH-XRYLZ)

d(XCKIH-XRYHZ)

15.5

Delay time, XCLKIN high to XDx invalid

Delay time, XCLKIN high to XDx high impedance

18

15.5

#

Delay time, XCLKIN high to XRDY valid

5

Delay time, XCLKIN high to XRDY low impedance

Delay time, XCLKIN high to XRDY high impedance

#

2P + 5 3P + 15.5

¶

#

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

XRDY operates as active-low ready input/output during host-port accesses.

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

2

1

XCS

4

3

XAS

6

5

XCNTL

8

7

†

XW/R

8

7

†

‡

XW/R

XBE[3:0]/XA[5:2]

10

9

§

XBLAST

§

13

14

12

11

D1

15

D2

D3

D4

XD[31:0]

21

20

15

¶

XRDY

†

‡

§

¶

XW/R input/output polarity selected at boot

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XBLAST input polarity selected at boot

XRDY operates as active-low ready input/output during host-port accesses.

Figure 34. External Host as Bus Master—Read

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

2

1

XCS

4

3

XAS

6

5

XCNTL

8

7

†

XW/R

8

7

17

16

‡

XBE[3:0]/XA[5:2]

XBLAST

XBE1

XBE2

XBE3

9

XBE4

10

§

9

§

XBLAST

19

18

D1

15

D2

D3

D4

XD[31:0]

21

20

15

¶

XRDY

†

‡

§

¶

XW/R input/output polarity selected at boot

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XBLAST input polarity selected at boot

XRDY operates as active-low ready input/output during host-port accesses.

Figure 35. External Host as Bus Master—Write

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

timing requirements with ’C62x as bus master (see Figure 36, Figure 37, and Figure 38)

-200

-250

-300

NO.

UNIT

MIN

MAX

9

t

Setup time, XDx valid before XCLKIN high

Hold time, XDx valid after XCLKIN high

Setup time, XRDY valid before XCLKIN high

4

ns

su(XDV-XCKIH)

h(XCKIH-XDV)

su(XRY-XCKIH)

h(XCKIH-XRY)

10

11

12

2.3

4

†

Hold time, XRDY valid after XCLKIN high

2.3

14

15

t

Setup time, XBOFF valid before XCLKIN high

Hold time, XBOFF valid after XCLKIN high

4

ns

su(XBFF-XCKIH)

h(XCKIH-XBFF)

t

2.3

†

XRDY operates as active-low ready input/output during host-port accesses.

switching characteristics with ’C62x as bus master (see Figure 36, Figure 37, and Figure 38)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN MAX

1

2

3

4

5

6

7

8

t

Delay time, XCLKIN high to XAS valid

Delay time, XCLKIN high to XW/R valid

5

15.5

ns

d(XCKIH-XASV)

d(XCKIH-XWRV)

d(XCKIH-XBLTV)

d(XCKIH-XBEV)

d(XCKIH-XDLZ)

d(XCKIH-XDV)

d(XCKIH-XDIV)

d(XCKIH-XDHZ)

‡

5

§

Delay time, XCLKIN high to XBLAST valid

¶

Delay time, XCLKIN high to XBE[3:0]/XA[5:2] valid

Delay time, XCLKIN high to XDx low impedance

Delay time, XCLKIN high to XDx valid

15.5

Delay time, XCLKIN high to XDx invalid

5

Delay time, XCLKIN high to XDx high impedance

18

#

13

t

Delay time, XCLKIN high to XWE/XWAIT valid

15.5

ns

d(XCKIH-XWTV)

‡

§

¶

#

XW/R input/output polarity selected at boot.

XBLAST output polarity is always active low.

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XWE/XWAIT operates as XWAIT output signal during host-port accesses.

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

1

XAS

2

4

2

3

†

XW/R

3

‡

§

XBLAST

4

XBE[3:0]/XA[5:2]

BE

5

9

7

6

8

10

D2

AD

D1

D3

D4

XD[31:0]

XRDY

11

12

13

¶

XWE/XWAIT

†

‡

§

¶

XW/R input/output polarity selected at boot

XBLAST output polarity is always active low.

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XWE/XWAIT operates as XWAIT output signal during host-port accesses.

Figure 36. ’C62x as Bus Master—Read

XCLKIN

XAS

1

†

XW/R

2

3

4

7

†

3

‡

XBLAST

4

§

XBE[3:0]/XA[5:2]

6

Addr

5

8

D1

D2

11

D3

D4

XD[31:0]

XRDY

12

13

¶

XWE/XWAIT

†

‡

§

¶

XW/R input/output polarity selected at boot

XBLAST output polarity is always active low.

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XWE/XWAIT operates as XWAIT output signal during host-port accesses.

Figure 37. ’C62x as Bus Master—Write

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS SYNCHRONOUS HOST PORT TIMING (CONTINUED)

XCLKIN

1

XAS

†

XW/R

2

†

‡

XW/R

XBLAST

4

7

§

XBE[3:0]/XA[5:2]

6

5

8

Addr

D1

11

D2

XD[31:0]

XRDY

12

15

14

XBOFF

¶

#

XHOLD

XHOLDA

XHOLD

#

XHOLDA

†

‡

§

¶

#

||

XW/R input/output polarity selected at boot

XBLAST output polarity is always active low.

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

Internal arbiter enabled

External arbiter enabled

This diagram illustrates XBOFF timing. Bus arbitration timing is shown in Figure 41 and Figure 42.

||

Figure 38. ’C62x as Bus Master—BOFF Operation

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING

†

timing requirements with external device as asynchronous bus master (see Figure 39 and

Figure 40)

-200

-250

-300

MIN MAX

4P

NO.

UNIT

1

t

Pulse duration, XCS low

Pulse duration, XCS high

ns

w(XCSL)

2

t

4P

2

ns

w(XCSH)

‡

Setup time, expansion bus select signals valid before XCS low

3

su(XSEL-XCSL)

h(XCSL-XSEL)

h(XRYL-XCSL)

su(XBEV-XCSH)

h(XCSH-XBEV)

su(XDV-XCSH)

h(XCSH-XDV)

‡

4

Hold time, expansion bus select signals valid after XCS low

2

10

11

12

13

14

Hold time, XCS low after XRDY low

P

2

§

Setup time, XBE[3:0]/XA[5:2] valid before XCS high

§

Hold time, XBE[3:0]/XA[5:2] valid after XCS high

Setup time, XDx valid before XCS high

Hold time, XDx valid after XCS high

2

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

Expansion bus select signals include XCNTL and XR/W.

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

switching characteristics with external device as asynchronous bus master (see Figure 39 and

Figure 40)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN MAX

5

6

7

8

9

t

Delay time, XCS low to XDx low impedance

Delay time, XCS high to XDx invalid

Delay time, XCS high to XDx high impedance

Delay time, XRDY low to XDx valid

0

ns

d(XCSL-XDLZ)

d(XCSH-XDIV)

d(XCSH-XDHZ)

d(XRYL-XDV)

d(XCSH-XRYH)

0

12

4

0

Delay time, XCS high to XRDY high

12

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING (CONTINUED)

1

2

10

XCS

3

4

XCNTL

†

XBE[3:0]/XA[5:2]

3

4

‡

XR/W

‡

7

6

7

6

5

8

5

8

Word

XD[31:0]

XRDY

9

†

‡

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XW/R input/output polarity selected at boot

Figure 39. External Device as Asynchronous Master—Read

1

10

2

10

1

XCS

3

4

XCNTL

11

12

†

‡

XBE[3:0]/XA[5:2]

XR/W

3

4

XR/W

13

14

9

14

9

wWoorrdd

XD[31:0]

XRDY

†

‡

XBE[3:0]/XA[5:2] operates as byte enables XBE[3:0] during host-port accesses.

XW/R input/output polarity selected at boot

Figure 40. External Device as Asynchronous Master—Write

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

XHOLD/XHOLDA TIMING

†

timing requirements for expansion bus arbitration (internal arbiter enabled) (see Figure 41)

-200

-250

-300

NO.

UNIT

MIN MAX

3

t

Output hold time, XHOLD high after XHOLDA high

P

ns

oh(XHDAH-XHDH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

†‡

switching characteristics for expansion bus arbitration (internal arbiter enabled) (see Figure 41)

-200

-250

-300

MIN MAX

3P

NO.

PARAMETER

UNIT

§

1

2

4

5

t

Response time, XHOLD high to XBus high impedance

Delay time, XBus high impedance to XHOLDA high

Response time, XHOLD low to XHOLDA low

ns

R(XHDH-XBHZ)

d(XBHZ-XHDAH)

R(XHDL-XHDAL)

d(XHDAL-XBLZ)

0

2P

3P

0

Delay time, XHOLDA low to XBus low impedance

2P

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

All pending XBus transactions are allowed to complete before XHOLDA is asserted.

External Requestor

DSP Owns Bus

Owns Bus

DSP Owns Bus

3

XHOLD (input)

2

4

XHOLDA (output)

1

5

†

’C62x

XBus

†

XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

Figure 41. Expansion Bus Arbitration—Internal Arbiter Enabled

63

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

XHOLD/XHOLDA TIMING (CONTINUED)

†

switching characteristics for expansion bus arbitration (internal arbiter disabled) (see Figure 42)

-200

-250

NO.

PARAMETER

UNIT

-300

MAX

2P 2P + 10

2P

MIN

‡

1

2

t

Delay time, XHOLDA high to XBus low impedance

ns

d(XHDAH-XBLZ)

‡

Delay time, XBus high impedance to XHOLD low

0

d(XBHZ-XHDL)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

2

XHOLD (output)

XHOLDA (input)

1

†

XBus

’C62x

†

XBus consists of XBE[3:0]/XA[5:2], XAS, XW/R, and XBLAST.

Figure 42. Expansion Bus Arbitration—Internal Arbiter Disabled

64

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING

†‡

timing requirements for McBSP (see Figure 43)

-200

-250

-300

NO.

UNIT

MIN

MAX

§

2

3

t

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

¶

P–1

Pulse duration, CLKR/X high or CLKR/X low

w(CKRX)

9

1

6

3

8

0

3

9

1

6

3

5

6

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH-CKRL)

h(CKRL-FRH)

su(DRV-CKRL)

h(CKRL-DRV)

su(FXH-CKXL)

h(CKXL-FXH)

7

8

Hold time, DR valid after CLKR low

10

11

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

†

‡

§

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

P = 1/CPU clock frequency in ns.

ThemaximumMcBSPbitrateis100MHz;therefore, theminimumCLKR/XclockcycleiseithertwicetheCPUcycletime(2P), or10ns(100MHz),

whichever value is larger. For example, when running parts at 250 MHz (P = 4 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting

the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum

CLKR/X clock cycle.

The minimum CLKR/X pulse duration is either (P–1) or 4 ns, whichever is larger. For example, when running parts at 250 MHz (P = 4 ns), use

4 ns as the minimum CLKR/X pulse duration. When running parts at 100 MHz (P = 10 ns), use (P–1) = 9 ns as the minimum CLKR/X pulse

duration.

¶

65

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

switching characteristics for McBSP (see Figure 43)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal

CLKR/X generated from CLKS input

1

t

4

10

ns

d(CKSH-CKRXH)

§¶

2

3

4

t

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

#

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

C – 1

C + 1

w(CKRX)

–2

3

9

4

9

4

9

d(CKRH-FRV)

9

t

Delay time, CLKX high to internal FSX valid

ns

d(CKXH-FXV)

dis(CKXH-DXHZ)

d(CKXH-DXV)

–1

3

Disable time, DX high impedance following last data bit from

CLKX high

12

13

–1

3

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid

FSX int

FSX ext

–1

3

9

14

t

ns

d(FXH-DXV)

ONLY applies when in data delay 0 (XDATDLY = 00b) mode.

†

‡

§

¶

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

Minimum delay times also represent minimum output hold times.

P = 1/CPU clock frequency in ns.

ThemaximumMcBSPbitrateis100MHz;therefore, theminimumCLKR/XclockcycleiseithertwicetheCPUcycletime(2P), or10ns(100MHz),

whichever value is larger. For example, when running parts at 250 MHz (P = 4 ns), use 10 ns as the minimum CLKR/X clock cycle (by setting

the appropriate CLKGDV ratio or external clock source). When running parts at 100 MHz (P = 10 ns), use 2P = 20 ns (50 MHz) as the minimum

CLKR/X clock cycle.

#

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.

66

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

1

2

3

CLKR

4

FSR (int)

5

6

FSR (ext)

7

8

DR

Bit(n-1)

(n-2)

(n-3)

2

3

CLKX

9

FSX (int)

11

10

FSX (ext)

FSX (XDATDLY=00b)

13

(n-2)

14

13

12

DX

Bit 0

Bit(n-1)

(n-3)

Figure 43. McBSP Timings

67

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 44)

-200

-250

-300

NO.

UNIT

MIN

MAX

1

2

t

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

4

ns

su(FRH-CKSH)

h(CKSH-FRH)

CLKS

1

2

FSR external

CLKR/X (no need to resync)

CLKR/X(needs resync)

Figure 44. FSR Timing When GSYNC = 1

68

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 45)

-200

-250

-300

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

MIN

2 – 3P

5 + 6P

MAX

4

5

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

ns

su(DRV-CKXL)

h(CKXL-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

(see Figure 45)

-200

-250

-300

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX low

T – 2 T + 3

L – 2 L + 3

ns

h(CKXL-FXL)

d(FXL-CKXH)

d(CKXH-DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX high to DX valid

–2

4

3P + 4 5P + 17

Disable time, DX high impedance following last data bit from

CLKX low

6

t

L – 2 L + 3

ns

dis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

7

8

t

P + 3 3P + 17

2P + 2 4P + 17

ns

dis(FXH-DXHZ)

Delay time, FSX low to DX valid

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

69

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

70

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 46)

-200

-250

-300

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

MIN

2 – 3P

5 + 6P

MAX

4

5

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

ns

su(DRV-CKXH)

h(CKXH-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0

(see Figure 46)

-200

-250

-300

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX low

L – 2 L + 3

T – 2 T + 3

ns

h(CKXL-FXL)

d(FXL-CKXH)

d(CKXL-DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX low to DX valid

–2

4

3P + 4 5P + 17

3P + 3 5P + 17

Disable time, DX high impedance following last data bit from

CLKX low

6

t

–2

4

ns

dis(CKXL-DXHZ)

7

t

Delay time, FSX low to DX valid

H – 2 H + 4

2P + 2 4P + 17

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

71

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

1

2

7

FSX

DX

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

Bit 0

(n-2)

(n-4)

Figure 46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

72

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 47)

-200

-250

-300

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

MIN

2 – 3P

5 + 6P

MAX

4

5

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

ns

su(DRV-CKXH)

h(CKXH-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1

(see Figure 47)

-200

-250

-300

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX high

T – 2 T + 3

H – 2 H + 3

ns

h(CKXH-FXL)

d(FXL-CKXL)

d(CKXL-DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX low to DX valid

–2

4

3P + 4 5P + 17

Disable time, DX high impedance following last data bit from

CLKX high

6

t

H – 2 H + 3

ns

dis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

7

8

t

P + 3 3P + 17

2P + 2 4P + 17

ns

dis(FXH-DXHZ)

Delay time, FSX low to DX valid

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

73

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

1

2

8

FSX

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

74

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 48)

-200

-250

-300

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

MIN

2 – 3P

5 + 6P

MAX

4

5

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

ns

su(DRV-CKXL)

h(CKXL-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1

(see Figure 48)

-200

-250

-300

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX high

H – 2 H + 3

T – 2 T + 1

ns

h(CKXH-FXL)

d(FXL-CKXL)

d(CKXH-DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX high to DX valid

–2

4

3P + 4 5P + 17

3P + 3 5P + 17

Disable time, DX high impedance following last data bit from

CLKX high

6

t

–2

4

ns

dis(CKXH-DXHZ)

7

t

Delay time, FSX low to DX valid

L – 2 L + 4

2P + 2 4P + 17

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 100 MHz limit.

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

75

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

1

2

FSX

DX

7

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

(n-2)

(n-3)

(n-4)

Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

76

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

DMAC, TIMER, POWER-DOWN TIMING

†

switching characteristics for DMAC outputs (see Figure 49)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

2P–3

MAX

1

t

Pulse duration, DMAC high

ns

w(DMACH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

1

DMAC[3:0]

Figure 49. DMAC Timing

†

timing requirements for timer inputs (see Figure 50)

-200

-250

-300

NO.

UNIT

MIN

MAX

1

2

t

Pulse duration, TINP high

Pulse duration, TINP low

2P

ns

w(TINPH)

w(TINPL)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

†

switching characteristics for timer outputs (see Figure 50)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

3

4

t

Pulse duration, TOUT high

Pulse duration, TOUT low

2P–3

ns

w(TOUTH)

w(TOUTL)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

2

1

TINPx

4

3

TOUTx

Figure 50. Timer Timing

77

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)

†

switching characteristics for power-down outputs (see Figure 51)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

2P

MAX

1

t

Pulse duration, PD high

ns

w(PDH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

1

PD

Figure 51. Power-Down Timing

78

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 52)

-200

-250

-300

NO.

UNIT

MIN

MAX

1

3

4

t

Cycle time, TCK

50

10

9

ns

c(TCK)

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

su(TDIV-TCKH)

h(TCKH-TDIV)

switching characteristics for JTAG test port (see Figure 52)

-200

-250

-300

NO.

PARAMETER

UNIT

MIN

MAX

2

t

Delay time, TCK low to TDO valid

0

15

ns

d(TCKL-TDOV)

1

TCK

TDO

2

4

3

TDI/TMS/TRST

Figure 52. JTAG Test-Port Timing

79

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MECHANICAL DATA

GJL (S-PBGA-N352)

PLASTIC BALL GRID ARRAY

27,20

SQ

26,80

25,20

SQ

25,00 TYP

24,80

1,00

16,30 NOM

0,50

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25

2

4

6

8

10 12 14 16 18 20 22 24 26

Heat Slug

See Note E

3,50 MAX

1,00 NOM

Seating Plane

0,15

0,70

0,50

M

0,10

0,60

0,40

4173516-2/C 07/99

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Thermally enhanced plastic package with heat slug (HSL).

D. Flip chip application only

E. Possible protrusion in this area, but within 3,50 max package height specification

F. Falls within JEDEC MO-151/AAL-1

thermal resistance characteristics (S-PBGA package)

†

NO

°C/W

0.47

14.2

12.3

10.2

8.6

Air Flow LFPM

1

2

3

4

5

RΘ

Junction-to-case

N/A

0

JC

JA

Junction-to-free air

100

250

500

†

LFPM = Linear Feet Per Minute

80

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MECHANICAL DATA

GLS (S-PBGA-N384)

PLASTIC BALL GRID ARRAY

18,10

17,90

SQ

16,80 TYP

0,80

0,40

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21

2

4

6

8

10 12 14 16 18 20 22

Heat Slug

2,80 MAX

1,00 NOM

Seating Plane

0,15

0,55

0,45

M

0,10

0,45

0,35

4188959/B 12/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Thermally enhanced plastic package with heat slug (HSL)

D. Flip chip application only

thermal resistance characteristics (S-PBGA package)

†

NO

°C/W

0.85

21.6

17.9

14.2

11.8

Air Flow LFPM

1

2

3

4

5

RΘ

Junction-to-case

N/A

0

JC

JA

Junction-to-free air

100

250

500

†

LFPM = Linear Feet Per Minute

81

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320C6202, TMS320C6202B, TMS320C6203, TMS320C6204

FIXED-POINT DIGITAL SIGNAL PROCESSORS

SPRS104 – OCTOBER 1999

MECHANICAL DATA

GLW (S-PBGA-N340)

PLASTIC BALL GRID ARRAY (CAVITY DOWN)

18,10

17,90

SQ

16,80 TYP

0,80

0,40

AB

Y

AA

W

U

R

N

L

V

T

P

M

K

H

F

J

G

E

D

B

C

A

1

3

5

7

8

9

11 13 15 17 19 21

10 12 14 16 18 20 22

2

4

6

Heat Slug

2,00 NOM

2,80 MAX

Seating Plane

0,15

0,55

0,45

M

0,10

0,45

0,35

4200619/A 00/99

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Thermally enhanced plastic package with heat slug (HSL).

82

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TMS320C6202GLS-233
厂家：	TEXAS INSTRUMENTS
描述：	32-BIT, 233MHz, OTHER DSP, PBGA384, PLASTIC, BGA-384
文件：	总83页 (文件大小：1175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320C6202GLS-233 [TI]

相关型号：

TMS320C6202GLS-300

TMS320C6202GLS100

TMS320C6202GLS200

TMS320C6202GLS250

TMS320C6202GLS250X

TMS320C6202GLSA-100

TMS320C6202GLSA-150

TMS320C6202GLSA-167

TMS320C6202GLSA-200

TMS320C6202GLSA-250

TMS320C6202GLW100

TMS320C6203