TMS320C6421ZDU7 [TI]
C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2、SDRAM | ZDU | 376 | 0 to 90;
| 型号： | TMS320C6421ZDU7 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2、SDRAM | ZDU | 376 | 0 to 90 动态存储器 双倍数据速率 控制器 微控制器 微控制器和处理器 数字信号处理器 |
| 文件： | 总59页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C6421
Fixed-Point Digital Signal Processor
www.ti.com
SPRS346A–JANUARY 2007–REVISED MARCH 2007
1 TMS320C6421 Fixed-Point Digital Signal Processor
1.1 Features
[Flexible Allocation]
512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
•
High-Performance Digital Signal Processor
(C6421)
–
–
–
–
–
–
–
2.5-, 2.-, 1.67-ns Instruction Cycle Time
400-, 500-, 600-MHz C64x+™ Clock Rate
Eight 32-Bit C64x+ Instructions/Cycle
3200, 4000, 4800 MIPS
Fully Software-Compatible With C64x
Commercial and Extended Temperature
Ranges
•
•
Endianess: Supports Both Little Endian and
Big Endian
External Memory Interfaces (EMIFs)
–
16-Bit DDR2 SDRAM Memory Controller
With 128M-Byte Address Space (1.8-V I/O)
Asynchronous 8-Bit-Wide EMIF (EMIFA)
With up to 64M-Byte Address Reach
–
•
VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
•
Flash Memory Interfaces
•
•
NOR (8-Bit-Wide Data)
NAND (8-Bit-Wide Data)
–
Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
•
•
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
•
Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
•
Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
•
•
•
One 64-Bit Watch Dog Timer
One UART With RTS and CTS Flow Control
Master/Slave Inter-Integrated Circuit
(I2C Bus™)
–
Load-Store Architecture With Non-Aligned
Support
•
Multichannel Buffered Serial Port (McBSP0)
–
–
–
–
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
–
–
–
–
–
–
I2S and TDM
AC97 Audio Codec Interface
SPI
Standard Voice Codec Interface (AIC12)
Telecom Interfaces – ST-Bus, H-100
128 Channel Mode
Additional C64x+™ Enhancements
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
•
Multichannel Audio Serial Port (McASP0)
Four Serializers and SPDIF (DIT) Mode
•
Hardware Support for Modulo Loop
Auto-Focus Module Operation
–
•
•
16-Bit Host-Port Interface (HPI)
•
C64x+ Instruction Set Features
10/100 Mb/s Ethernet MAC (EMAC)
–
–
–
–
–
–
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2 Increased Orthogonality
C64x+ Extensions
–
–
IEEE 802.3 Compliant
Supports Multiple Media Independent
Interfaces (MII, RMII)
–
Management Data I/O (MDIO) Module
•
•
•
•
•
•
VLYNQ™ Interface (FPGA Interface)
Three Pulse Width Modulator (PWM) Outputs
On-Chip ROM Bootloader
•
•
Compact 16-bit Instructions
Additional Instructions to Support
Complex Multiplies
Individual Power-Savings Modes
Flexible PLL Clock Generators
•
C64x+ L1/L2 Memory Architecture
–
128K-Bit (16K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
IEEE-1149.1 (JTAG™)
Boundary-Scan-Compatible
–
128K-Bit (16K-Byte) L1D Data RAM/Cache
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007–2007, Texas Instruments Incorporated
TMS320C6421
Fixed-Point Digital Signal Processor
www.ti.com
SPRS346A–JANUARY 2007–REVISED MARCH 2007
•
•
Up to 111 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
•
3.3-V and 1.8-V I/O, 1.2-V Internal (-600, -500,
-400)
Packages:
•
•
3.3-V and 1.8-V I/O, 1.05-V Internal (-400)
Applications:
–
361-Pin Pb-Free PBGA Package
(ZWT Suffix), 0.8-mm Ball Pitch
–
–
–
Telecom
Audio
Industrial Applications
–
376-Pin Plastic BGA Package
(ZDU Suffix), 1.0-mm Ball Pitch
•
0.09-µm/6-Level Cu Metal Process (CMOS)
1.2 Description
The TMS320C64x+™ DSPs (including the TMS320C6421 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The C6421 device is based on the third-generation
high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by
Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications.
The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™
DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from
previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in telecom, audio, and industrial
applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For
more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference
Guide (literature number SPRU732).
The C6421 also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The C6421 core uses a two-level
cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 128K-bit memory
space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D)
consists of a 128K-bit memory space that can be configured as mapped memory or 2-way set-associative
cache. The Level 2 memory/cache (L2) consists of a 512K-bit memory space that is shared between
program and data space. L2 memory can be configured as mapped memory, cache, or combinations of
the two.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output
(MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus
interface; a multichannel buffered serial port (McBSP0); a multichannel audio serial port (McASP0) with 4
serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit
watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose
input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other
peripherals; 1 UART with hardware handshaking support; 3 pulse width modulator (PWM) peripherals; and
2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower
memories/peripherals, and a higher speed synchronous memory interface for DDR2.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6421 and the
network. The C6421 EMAC supports 10Base-T and 100Base-TX or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
2
TMS320C6421 Fixed-Point Digital Signal Processor
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The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow C6421 to easily control peripheral devices and/or communicate with host
processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The C6421 has a complete set of development tools. These include C compilers, a DSP assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
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TMS320C6421
Fixed-Point Digital Signal Processor
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SPRS346A–JANUARY 2007–REVISED MARCH 2007
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the C6421 device.
JTAG Interface
System Control
OSC
DSP
Input
Clock(s)
C64x+™ DSP CPU
64 KB L2 RAM
PLLs/Clock Generator
Power/Sleep
Controller
16 KB
L1 Pgm
16 KB
L1 Data
Pin Multiplexing
Boot ROM
Switched Central Resource (SCR)
Peripherals
Serial Interfaces
System
General-
Purpose
Timer
Watchdog
Timer
I2C
GPIO
UART
McASP
McBSP
PWM
EDMA
Program/Data Storage
Connectivity
EMAC
With
MDIO
DDR2
Mem Ctlr
(16b)
Async EMIF/
NAND/
(8b)
VLYNQ
HPI
Figure 1-1. TMS320C6421 Functional Block Diagram
4
TMS320C6421 Fixed-Point Digital Signal Processor
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Fixed-Point Digital Signal Processor
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Contents
1
2
TMS320C6421 Fixed-Point Digital Signal
5
Device Operating Conditions ........................ 52
Processor.................................................. 1
1.1 Features .............................................. 1
1.2 Description............................................ 2
1.3 Functional Block Diagram ............................ 4
Device Overview ......................................... 6
2.1 Device Characteristics................................ 6
2.3 Memory Map Summary............................... 7
2.4 Pin Assignments...................................... 9
2.5 Terminal Functions.................................. 18
5.1
Absolute Maximum Ratings Over Operating
Temperature Range (Unless Otherwise Noted)..... 52
5.2 Recommended Operating Conditions............... 53
5.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted) ............ 54
7
Mechanical Data ........................................ 55
7.1 Thermal Data for ZWT .............................. 55
7.1.1 Thermal Data for ZDU .............................. 56
7.1.2 Packaging Information .............................. 56
2.7
Device and Development-Support Tool
Nomenclature ....................................... 50
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Contents
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TMS320C6421
Fixed-Point Digital Signal Processor
www.ti.com
SPRS346A–JANUARY 2007–REVISED MARCH 2007
2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the TMS320C6421 DSP. The tables show significant features of the
C6421 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
Table 2-1. Characteristics of the C6421 Processor
HARDWARE FEATURES
C6421
DDR2 Memory Controller
(16-bit bus width) [1.8 V I/O]
Asynchronous (8-bit bus width),
RAM, Flash, (8-bit NOR or 8-bit NAND)
Asynchronous EMIF [EMIFA]
EDMA3
1 (64 independent channels, 8 QDMA channels)
2 64-bit General Purpose
(configurable as 2 64-bit or 4 32-bit)
1 64-bit Watch Dog
Timers
Peripherals
UART
I2C
1 with RTS and CTS flow control
Not all peripherals pins
are available at the same
time (For more detail, see
the Device Configuration
section).
1 (Master/Slave)
1
McBSP
McASP
1 (4 serailizers)
10/100 Ethernet MAC (EMAC) with
Management Data Input/Output (MDIO)
1
VLYNQ
1
Up to 111 pins
3 outputs
General-Purpose Input/Output Port (GPIO)
PWM
HPI (16-bit)
Size (Bytes)
1
96KB RAM, 64KB ROM
16K-Byte (16KB) L1 Program (L1P) RAM/Cache
16KB L1 Data (L1D) RAM/Cache
64KB Unified Mapped RAM/Cache (L2)
64KB Boot ROM
On-Chip Memory
Organization
Revision ID Register (MM_REVID.[15:0])
(address location: 0x0181 2000)
See theTMS320C6424/21 Digital Signal Processor
(DSP) [Silicon Revisions 1.1 and 1.0] Silicon Errata
(literature number SPRZ252).
Megamodule Rev ID
CPU ID + CPU Rev ID
JTAG BSDL_ID
Control Status Register (CSR.[31:16])
JTAGID register
(address location: 0x01C4 0028)
See Section 6.1.1, JTAG Peripheral Register
Description(s) – JTAG ID Register
CPU Frequency
MHz
ns
400, 500, 600
2.5 ns (-400)
2 ns (-500)
Cycle Time
1.67 ns (-600)
Core (V)
I/O (V)
1.2 V (-600, -500, -400), 1.05 V (-400)
1.8 V, 3.3 V
Voltage
MXI/CLKIN frequency multiplier
(15–30 MHz reference)
PLL Options
BGA Package(s)
x1 (Bypass), x14 to x 32
16 x 16 mm, 0.8 mm pitch
23 x 23 mm, 1.0 mm pitch
µm
361-Pin BGA (ZWT)
376-Pin BGA (ZDU)
0.09 µm
Process Technology
Product Status(1)
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
PP
(1) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
6
Device Overview
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Fixed-Point Digital Signal Processor
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2.3 Memory Map Summary
Table 2-5 shows the memory map address ranges of the device. Table 2-6 depicts the expanded map of
the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories
associated with its two processors and various subsystems. To help simplify software development a
unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.
Table 2-5. Memory Map Summary
START
ADDRESS
END
ADDRESS
SIZE
(Bytes)
C64x+
MEMORY MAP
EDMA PERIPHERAL
MEMORY MAP
0x0000 0000
0x000F FFFF
1M
Reserved
Boot ROM
Reserved
Reserved
0x0010 0000
0x0011 0000
0x0080 0000
0x0081 0000
0x0082 0000
0x00E0 8000
0x00E0 C000
0x00E1 0000
0x00F0 4000
0x00F1 0000
0x00F1 4000
0x00F1 8000
0x0180 0000
0x01C0 0000
0x0200 0000
0x1010 0000
0x1011 0000
0x1080 0000
0x1081 0000
0x1082 0000
0x10E0 8000
0x10E0 C000
0x10E1 0000
0x10F1 0000
0x10F1 4000
0x10F1 8000
0x2000 0000
0x2000 8000
0x4200 0000
0x4300 0000
0x4400 0000
0x4500 0000
0x4600 0000
0x4700 0000
0x4800 0000
0x4900 0000
0x4C00 0000
0x5000 0000
0x8000 0000
0x9000 0000
0x0010 FFFF
0x007F FFFF
0x0080 FFFF
0x0081 FFFF
0x00E0 7FFF
0x00E0 BFFF
0x00E0 FFFF
0x00F0 3FFF
0x00F0 FFFF
0x00F1 3FFF
0x00F1 7FFF
0x017F FFFF
0x01BF FFFF
0x01FF FFFF
0x100F FFFF
0x1010 FFFF
0x107F FFFF
0x1080 FFFF
0x1081 FFFF
0x10E0 7FFF
0x10E0 BFFF
0x10E0 FFFF
0x10F0 FFFF
0x10F1 3FFF
0x10F1 7FFF
0x1FFF FFFF
0x2000 7FFF
0x41FF FFFF
0x42FF FFFF
0x43FF FFFF
0x44FF FFFF
0x45FF FFFF
0x46FF FFFF
0x47FF FFFF
0x48FF FFFF
0x4BFF FFFF
0x4FFF FFFF
0x7FFF FFFF
0x8FFF FFFF
0xFFFF FFFF
64K
7M-64K
64K
64K
L2 RAM/Cache(1)
Reserved
6048K
16K
Reserved
Reserved
16K
L1P RAM/Cache(2)
Reserved
976K
48K
Reserved
16K
Reserved
16K
L1D RAM/Cache(2)
Reserved
9120K
4M
CFG Space
4M
CFG Bus Peripherals
Reserved
CFG Bus Peripherals
Reserved
225M
64K
Boot ROM
7M-48K
64K
Reserved
Reserved
Reserved
64K
L2 RAM/Cache(1)
Reserved
L2 RAM/Cache(1)
Reserved
6048K
16K
Reserved
Reserved
16K
L1P RAM/Cache(2)
Reserved
L1P RAM/Cache(2)
Reserved
1M
16K
Reserved
Reserved
16K
L1D RAM/Cache(2)
Reserved
L1D RAM/Cache(2)
Reserved
241M-96K
32K
DDR2 Control Regs
Reserved
DDR2 Control Regs
Reserved
544M-32K
16M
EMIFA Data (CS2)(3)
Reserved
EMIFA Data (CS2)(3)
Reserved
16M
16M
EMIFA Data (CS3)(3)
Reserved
EMIFA Data (CS3)(3)
Reserved
16M
16M
EMIFA Data (CS4)(3)
Reserved
EMIFA Data (CS4)(3)
Reserved
16M
16M
EMIFA Data (CS5)(3)
Reserved
EMIFA Data (CS5)(3)
Reserved
48M
64M
VLYNQ (Remote Data)
Reserved
VLYNQ (Remote Data)
Reserved
768M
256M
1792M
DDR2 Memory Controller
Reserved
DDR2 Memory Controller
Reserved
(1) On the C6421, L2 RAM/Cache defaults to all RAM (L2CFG.L2MODE = 0h)
(2) To intialize L1P and L1D RAM/Cache to a valid cache setting, the user must follow the sequence outlined in , Device Initialization
Sequence After Reset.
(3) The EMIFA CS0 and CS1 are not functionally supported on the C6421 device, and therefore, are not pinned out.
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Table 2-6. Configuration Memory Map Summary
START
END
SIZE
C64x+
ADDRESS
ADDRESS
(Bytes)
0x0180 0000
0x0181 0000
0x0181 1000
0x0181 2000
0x0182 0000
0x0183 0000
0x0184 0000
0x0185 0000
0x0188 0000
0x01BC 0000
0x01BC 0100
0x01BC 0400
0x01C0 0000
0x01C1 0000
0x01C1 0400
0x01C1 0800
0x01C1 0C00
0x01C2 0000
0x01C2 0400
0x01C2 1000
0x01C2 1400
0x01C2 1800
0x01C2 1C00
0x01C2 2000
0x01C2 2400
0x01C2 2800
0x01C2 2C00
0x01C4 0000
0x01C4 0800
0x01C4 0C00
0x01C4 1000
0x01C4 2000
0x01C6 7000
0x01C6 7800
0x01C6 8000
0x01C8 0000
0x01C8 1000
0x01C8 2000
0x01C8 4000
0x01C8 4800
0x01D0 0000
0x01D0 0800
0x01D0 1000
0x01D0 1400
0x01D0 1800
0x01E0 0000
0x01E0 1000
0x01E0 2000
0x0180 FFFF
0x0181 0FFF
0x0181 1FFF
0x0181 2FFF
0x0182 FFFF
0x0183 FFFF
0x0184 FFFF
0x0187 FFFF
0x01BB FFFF
0x01BC 00FF
0x01BC 01FF
0x01BF FFFF
0x01C0 FFFF
0x01C1 03FF
0x01C1 07FF
0x01C1 0BFF
0x01C1 FFFF
0x01C2 03FF
0x01C2 0FFF
0x01C2 13FF
0x01C2 17FF
0x01C2 1BFF
0x01C2 1FFF
0x01C2 23FF
0x01C2 27FF
0x01C2 2BFF
0x01C3 FFFF
0x01C4 07FF
0x01C4 0BFF
0x01C4 0FFF
0x01C4 1FFF
0x01C6 6FFF
0x01C6 77FF
0x01C6 7FFF
0x01C7 FFFF
0x01C8 0FFF
0x01C8 1FFF
0x01C8 3FFF
0x01C8 47FF
0x01CF FFFF
0x01D0 07FF
0x01D0 0FFF
0x01D0 13FF
0x01D0 17FF
0x01DF FFFF
0x01E0 0FFF
0x01E0 1FFF
0x0FFF FFFF
64K
4K
C64x+ Interrupt Controller
C64x+ Powerdown Controller
C64x+ Security ID
C64x+ Revision ID
C64x+ EMC
4K
4K
64K
64K
64K
192K
3328K
256
256
255K
64K
1K
Reserved
C64x+ Memory System
Reserved
Reserved
Reserved
Pin Manager and Trace
Reserved
EDMA CC
EDMA TC0
1K
EDMA TC1
1K
EDMA TC2
29K
1K
Reserved
UART0
3K
Reserved
1K
I2C
1K
Timer0
1K
Timer1
1K
Timer2 (Watchdog)
PWM0
1K
1K
PWM1
1K
PWM2
117K
2K
Reserved
System Module
PLL Controller 1
PLL Controller 2
Power and Sleep Controller
Reserved
1K
1K
4K
148K
2K
GPIO
2K
HPI
96K
4K
Reserved
EMAC Control Registers
EMAC Control Module Registers
EMAC Control Module RAM
MDIO Control Registers
Reserved
4K
8K
2K
494K
2K
McBSP0
2K
Reserved
1K
McASP0 Control
McASP0 Data
Reserved
1K
1018K
4K
EMIFA Control
VLYNQ Control Registers
Reserved
4K
226M-8K
8
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2.4 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see TBD, Multiplexed Pin Configurations of this document.
2.4.1 Pin Map (Bottom View)
Figure 2-6 through Figure 2-9 show the bottom view of the ZWT package pin assignments in four
quadrants (A, B, C, and D). Figure 2-10 through Figure 2-13 show the bottom view of the ZDU package
pin assignments in four quadrants (A, B, C, and D).
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1
2
3
4
5
6
7
8
9
10
W
V
U
T
V
V
W
V
U
T
DDR_D[7]
DDR_D[9]
DDR_D[12]
DDR_D[14]
DDR_CLK0
DDR_CLK0
DDR_A[12]
DDR_A[11]
SS
SS
DV
DDR_D[4]
DDR_D[3]
DDR_D[1]
TRST
DDR_D[6]
DDR_D[5]
RSV16
DDR_D[8]
DDR_DQS[0]
DDR_DQM[0]
DDR_D[11]
DDR_D[10]
DDR_D[13]
DDR_DQS[1]
DDR_DQM[1]
DDR_D[15]
DDR_RAS
DDR_CAS
DDR_CKE
DDR_BS[0]
DDR_WE
DDR_BS[1]
DDR_BS[2]
DDR_CS
DDR_A[8]
DDR_A[10]
DDR_ZN
DDR2
DDR_D[2]
DDR_D[0]
DV
DDR2
R
P
N
M
L
R
P
N
M
L
TMS
DV
V
V
DV
V
DV
V
DV
DDR2
SS
SS
DDR2
SS
DDR2
SS
DDR2
EMU0
TDO
TDI
POR
DV
V
DV
V
DV
V
SS
DD33
SS
DDR2
SS
DDR2
DV
DDR2
TCK
EMU1
RESETOUT
V
DV
V
CV
V
CV
DD
SS
DD33
SS
DD
SS
CLKOUT0/
PWM2/
GP[84]
RESET
SCL
SDA
DV
V
CV
V
CV
V
SS
DD33
SS
DD
SS
DD
URTS0/
PWM0/
GP[88]
UCTS0/
GP[87]
URXD0/
GP[85]
TINP1L/
GP[56]
RSV3
DV
V
CV
V
CV
DD
DD33
SS
DD
SS
TINP0L/
GP[98]
UTXD0/
GP[86]
TOUT1L/
GP[55]
K
K
V
RSV2
5
V
CV
V
CV
V
SS
SS
SS
DD
SS
DD
1
2
3
4
6
7
8
9
10
Figure 2-6. ZWT Pin Map [Quadrant A]
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11
12
13
14
15
16
17
18
19
W
V
U
T
W
V
U
T
DDR_A[6]
DDR_A[5]
DDR_A[0]
RSV24
RSV26
RSV29
RSV35
DV
DV
DDR2
DDR2
DDR_A[7]
DDR_A[9]
DDR_ZP
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
RSV25
RSV22
RSV20
RSV27
RSV28
RSV30
RSV23
RSV21
RSV32
RSV33
RSV31
RSV37
V
SS
RSV36
RSV34
RSV38
DDR_VDDDLL DDR_VSSDLL
DDR_VREF
RSV39
R
P
N
M
L
R
P
N
M
L
V
DV
RSV5
DV
V
DV
V
V
V
SS
SS
DDR2
DDR2
SS
DDR2
SS
SS
DV
V
DV
V
RSV14
RSV13
RSV11
RSV15
RSV12
RSV10
RSV8
RSV9
RSV7
RSV6
DDR2
SS
DDR2
SS
SS
SS
V
CV
V
SS
V
SS
DD
CV
V
CV
V
DV
V
V
V
V
V
V
DD
SS
DD
DD33
SS
SS
SS
SS
SS
SS
CV
PLL
V
V
DV
RSV4
MXV
MXV
DD
PWR18
SS
SS
DDR2
DD
MXI/
CLKIN
K
K
CV
V
CV
V
DV
V
DV
SS
DD
SS
DD
SS
DD33
SS
DD33
11
12
13
14
15
16
17
18
19
Figure 2-7. ZWT Pin Map [Quadrant B]
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11
12
13
14
15
16
17
18
19
J
H
G
F
J
MXO
V
CV
V
DV
V
DV
V
V
SS
SS
DD
SS
DD33
SS
DD33
SS
RMTXD1/
GP[27]/
(LENDIAN)
RMTXEN/
GP[29]
RMTXD0/
GP[28]
H
G
F
CV
V
CV
V
DV
V
SS
DD
SS
DD
SS
DD33
GP[24]/
GP[25]/
GP[26]/
RMCRSDV/
GP[30]
V
DV
V
DV
V
SS
SS
DD33
SS
DD33
(BOOTMODE2) (BOOTMODE3) (FASTBOOT)
RMRXD1/
EM_CS5/
GP[33]
GP[23]/
(BOOTMODE1)
EM_D[6]/
GP[20]
EM_D[7]/
GP[21]
GP[22]/
(BOOTMODE0)
DV
V
DV
V
SS
DD33
SS
DD33
RMRXD0/
EM_CS4/
GP[32]
EM_WAIT/
(RDY/BSY)
EM_D[3]/
GP[17]
EM_D[5]/
GP[19]
EM_D[4]/
GP[18]
E
E
D
C
B
A
RSV18
RSV19
V
EM_WE
GP[40]
GP[38]
GP[39]
SS
RMREFCLK/
GP[31]
EM_A[18]/
GP[46]
EM_A[21]/
GP[34]
EM_R/W/
GP[35]
EM_D[0]/
GP[14]
EM_D[2]/
GP[16]
EM_D[1]/
GP[15]
D
EM_OE
GP[36]
GP[37]
EM_BA[1]/
GP[5]/
(AEM0)
EM_BA[0]/
GP[6]/
(AEM1)
EM_A[16]/
GP[48]
EM_A[20]/
GP[44]
EM_CS3/
GP[13]
EM_CS2/
GP[12]
C
GP[41]
GP[42]
EM_A[2]/
(CLE)/GP[8]/
(PLLMS0)
EM_A[0]/
GP[7]/
(AEM2)
EM_A[19]/
GP[45]
EM_A[15]/
GP[49]
EM_A[3]/
GP[11]
B
V
V
SS
EM_A[1]/
(ALE)/GP[9]/
(PLLMS1)
EM_A[4]/
GP[10]/
(PLLMS2)
RMRXER/
GP[52]
EM_A[17]/
GP[47]
A
GP[43]
12
GP[53]
13
GP[54]
14
DV
DD33
SS
11
15
16
17
18
19
Figure 2-8. ZWT Pin Map [Quadrant C]
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1
2
3
4
5
6
7
8
9
10
AHCLKR0/
CLKR0/
GP[101]
AXR0[1]/
DX0/
GP[104]
CLKS0/
TOUT0L/
GP[97]
V
SS
J
H
G
F
J
DV
DV
V
CV
V
CV
DD
DD33
DD33
SS
DD
SS
ACLKR0/
CLKX0/
GP[99]
AXR0[2]/
FSX0/
GP[103]
AFSR0/
DR0/
GP[100]
AXR0[0]/
GP[105]
DV
DD33
H
V
CV
V
CV
V
SS
SS
DD
SS
DD
AXR0[3]/
FSR0/
GP[102]
AHCLKX0/
GP[108]
AFSX0/
GP[107]
AMUTE0/
GP[110]
V
SS
G
DV
V
DV
V
DV
DD33
DD33
SS
DD33
SS
ACLKX0/
GP[106]
AMUTEIN0/
GP[109]
GP[4]/
PWM1
V
SS
F
DV
V
DV
V
DV
V
SS
DD33
SS
DD33
SS
DD33
E
D
C
B
A
E
GP[0]
GP[1]
GP[2]
GP[3]
RSV1
DV
V
DV
V
SS
RSV17
DD33
SS
DD33
HAS/
MDIO/
GP[83]
HRDY/
MRXD2/
GP[80]
HCNTL1/
MTXEN/
GP[75]
HD14/
MTXD0/
GP[72]
HD12/
MTXD2/
GP[70]
HD6/
HD1/
EM_A[6]/
GP[95]
EM_A[9]/
GP[92]
EM_A[12]/
GP[89]
D
VLYNQ_TXD1/ VLYNQ_RXD0/
GP[64]
GP[59]
HD0/
HCS/
MDCLK/
GP[81]
HINT/
MRXD3/
GP[82]
HDS2/
MRXD0/
GP[78]
HHWIL/
MRXDV/
GP[74]
HD11/
MTXD3/
GP[69]
HD9/
MCOL/
GP[67]
HD4/
VLYNQ_RXD3/
GP[62]
VLYNQ_
SCRUN/
GP[58]
EM_A[7]/
GP[94]
EM_A[11]/
GP[90]
C
HDS1/
MRXD1/
GP[79]
HCNTL0/
MRXER/
GP[76]
HD13/
MTXD1/
GP[71]
HD10/
MCRS/
GP[68]
HD7/
HD3/
EM_A[5]/
GP[96]
EM_A[8]/
GP[93]
EM_A[13]/
GP[51]
B
V
VLYNQ_TXD2/ VLYNQ_RXD2/
SS
GP[65]
GP[61]
HR/W/
MRXCLK/
GP[77]
HD15/
MTXCLK/
GP[73]
HD8/
HD5/
VLYNQ_
CLOCK/
GP[57]
HD2/
VLYNQ_RXD1/
GP[60]
EM_A[10]/
GP[91]
EM_A[14]/
GP[50]
A
DV
DV
VLYNQ_TXD3/ VLYNQ_TXD0/
DD33
DD33
GP[66]
GP[63]
1
2
3
4
5
6
7
8
9
10
Figure 2-9. ZWT Pin Map [Quadrant D]
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Fixed-Point Digital Signal Processor
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SPRS346A–JANUARY 2007–REVISED MARCH 2007
1
2
3
4
5
6
7
8
9
10
11
V
V
SS
SS
DDR_D[6]
DDR_D[8]
DDR_D[12]
DDR_D[15]
DDR_CLK0
DDR_CLK0
DDR_BS[1]
DDR_BS[2]
DDR_A[10]
AB
AA
AB
AA
DV
DDR_D[3]
DDR_D[4]
DDR_DQS[0] DDR_D[10]
DDR_D[13] DDR_DQS[1]
DDR_A[12]
DDR_WE
DDR_A[11]
DDR_CS
DDR_CKE
DDR_RAS
DDR_BS[0]
DDR_CAS
DDR2
DDR_DQM[0]
DDR_D[7]
DDR_DQM[1]
DDR_D[11]
DDR_D[9]
DDR_D[14]
DDR_D[0]
DDR_D[1]
DDR_D[2]
DDR_D[5]
RSV16
Y
Y
W
V
V
SS
V
DV
V
DV
V
SS
DDR2
SS
DV
DDR2
SS
DDR2
W
DV
TRST
TDO
EMU1
POR
SDA
TMS
TDI
V
V
V
V
DDR2
DV
DV
SS
SS
DV
SS
DV
DDR2
SS
DDR2
DDR2
DDR2
V
U
6
7
9
10
8
11
TCK
V
DV
U
SS
DDR2
EMU0
RESETOUT
RESET
DV
V
SS
DD33
T
T
CLKOUT0/
PWM2/
GP[84]
V
SS
DV
DD33
R
P
R
P
UCTS0/
GP[87]
TINP1L/
GP[56]
DV
V
V
CV
CV
DD
DD33
SS
SS
DD
P
N
UTXD0/
GP[86]
TOUT1L/
GP[55]
N
SCL
V
DV
N
CV
V
V
V
SS
DD33
DD
SS
SS
URTS0/
PWM0/
GP[88]
URXD0/
GP[85]
M
V
RSV3
4
V
M
CV
9
CV
10
M
SS
SS
5
DD
DD
SS
1
2
3
11
Figure 2-10. ZDU Pin Map [Quadrant A]
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12
13
14
15
16
17
18
19
20
21
22
DDR_A[7]
DDR_A[9]
DDR_A[4]
DDR_A[1]
DDR_A[0]
RSV26
RSV29
RSV30
RSV33
RSV36
DV
DV
DDR2
DDR2
AB
AB
AA
AA
DDR_A[6]
DDR_A[5]
DDR_ZP
DDR_A[3]
DDR_A[2]
RSV22
RSV20
RSV24
RSV25
RSV5
RSV27
RSV28
RSV23
RSV21
RSV31
RSV32
RSV34
RSV35
RSV38
RSV37
V
SS
Y
DDR_A[8]
DDR_ZN
RSV39
Y
W
V
DDR_VDDDLL
DDR_VSSDLL
W
V
DV
DDR_VREF
DV
V
V
V
SS
DDR2
DDR2
SS
SS
DV
V
DV
V
RSV12
RSV11
RSV13
RSV7
RSV15
RSV9
RSV6
RSV8
DV
V
DV
V
DDR2
SS
DDR2
SS
SS
DDR2
SS
DDR2
SS
17
13
14
16
12
15
U
T
V
V
V
V
U
T
SS
RSV14
RSV10
SS
R
V
V
V
V
R
P
SS
SS
SS
SS
SS
P
N
P
N
M
DV
RSV4
DV
V
DV
DD33
DD33
DD33
SS
CV
V
CV
V
V
SS
DD
DD
MXI/
CLKIN
V
DV
PLL
MXV
MXV
N
M
CV
CV
SS
DD33
PWR18
DD
DD
DD
SS
SS
V
V
DV
V
SS
M
DV
MXO
22
SS
SS
DD33
DD33
SS
18
19
20
21
12
13
14
Figure 2-11. ZDU Pin Map [Quadrant B]
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18
19
20
21
22
12
SS
13
14
RMTXD1/
GP[27]/
(LENDIAN)
GP[24]/
(BOOTMODE2)
L
V
V
CV
CV
L
K
J
V
L
DV
V
DD
DD
DD
SS
DD33
SS
GP[26]/
(FASTBOOT)
GP[23]/
(BOOTMODE1)
RMTXEN/
GP[29]
RMCRSDV/
GP[30]
V
CV
SS
SS
K
K
DV
DD33
RMRXD1/
EM_CS5/
GP[33]
GP[22]/
(BOOTMODE0)
RMTXD0/
GP[28]
CV
CV
V
DD
J
DD
SS
V
DV
DV
DV
J
SS
DD33
RMRXD0/
EM_CS4/
GP[32]
GP[25]/
(BOOTMODE3)
EM_D[7]/
GP[21]
H
G
F
V
H
DV
SS
DD33
EM_D[1]/
GP[15]
EM_D[4]/
GP[18]
RMREFCLK/
GP[31]
V
G
F
SS
DD33
EM_D[3]/
GP[17]
EM_D[6]/
GP[20]
EM_D[5]/
GP[19]
DV
V
SS
DD33
12
13
14
15
16
17
EM_BA[0]/
GP[6]/
(AEM1)
EM_D[0]/
GP[14]
EM_D[2]/
GP[16]
E
E
V
DV
V
DV
V
DV
V
V
SS
SS
DD33
SS
DD33
SS
DD33
DD33
EM_WAIT/
(RDY/BSY)
EM_A[3]/
GP[11]
EM_CS3/
GP[13]
D
D
C
B
A
RSV17
RSV18
RSV19
V
DV
DV
EM_OE
EM_WE
GP[36]
SS
DD33
SS
DD33
EM_A[0]/
GP[7]/
(AEM2)
EM_BA[1]/
GP[5]/
(AEM0)
EM_A[11]/
GP[90]
EM_A[15]/
GP[49]
EM_A[19]/
GP[45]
EM_A[20]/
GP[44]
EM_A[21]/
GP[34]
EM_R/W/
GP[35]
EM_CS2/
GP[12]
C
B
A
GP[40]
GP[37]
EM_A[1]/
(ALE)/GP[9]/
(PLLMS1)
EM_A[4]/
GP[10]/
(PLLMS2)
EM_A[12]/
GP[89]
EM_A[16]/
GP[48]
EM_A[17]/
GP[47]
GP[42]
GP[41]
GP[38]
V
V
SS
EM_A[2]/
(CLE)/GP[8]/
(PLLMS0)
EM_A[13]/
GP[51]
EM_A[14]/
GP[50]
EM_A[18]/
GP[46]
RMRXER/
GP[52]
GP[43]
15
GP[39]
16
GP[53]
17
GP[54]
18
DV
DD33
SS
12
13
14
19
20
21
22
Figure 2-12. ZDU Pin Map [Quadrant C]
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Fixed-Point Digital Signal Processor
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1
2
3
4
5
9
10
V
11
V
CLKS0/
TOUT0L/
GP[97]
TINP0L/
GP[98]
L
K
J
L
K
J
CV
L
K
J
DV
RSV2
DV
DD33
DD
DD
SS
SS
DD33
AHCLKR0/
CLKR0/
GP[101]
AXR0[1]/
DX0/
GP[104]
AFSR0/
DR0/
GP[100]
V
CV
V
V
SS
SS
SS
DV
DD33
ACLKR0/
CLKX0/
GP[99]
AXR0[2]/
FSX0/
GP[103]
AXR0[3]/
FSR0/
GP[102]
DV
V
V
CV
CV
DD
DD33
SS
SS
DD
AHCLKX0/
GP[108]
AXR0[0]/
GP[105]
AMUTE0/
GP[110]
H
G
F
V
H
G
F
DV
SS
DD33
ACLKX0/
GP[106]
AFSX0/
GP[107]
AMUTEIN0/
GP[109]
DV
V
DD33
SS
GP[4]/
PWM1
V
SS
GP[2]
GP[0]
GP[3]
GP[1]
DV
DD33
6
7
8
9
10
11
E
D
C
B
A
V
V
V
E
DV
DV
DV
DV
V
DV
DD33
SS
SS
SS
DD33
DD33
DD33
DD33
SS
HCS/
MDCLK/
GP[81]
HINT/
MRXD3/
GP[82]
HHWIL/
MRXDV/
GP[74]
V
V
SS
D
C
B
A
SS
RSV1
V
DV
DV
DV
V
SS
SS
DD33
DD33
DD33
HAS/
MDIO/
GP[83]
HDS2/
MRXD0/
GP[78]
HRDY/
MRXD2/
GP[80]
HCNTL1/
MTXEN/
GP[75]
HD12/
MTXD2/
GP[70]
HD9/
MCOL/
GP[67]
HD6/
HD4/
HD1/
VLYNQ_RXD0/
GP[59]
EM_A[7]/
GP[94]
EM_A[9]/
GP[92]
/
VLYNQ_TXD1/ VLYNQ_RXD3
GP[64]
HD7/
GP[62]
HD0/
HCNTL0/
MRXER/
GP[76]
HDS1/
MRXD1/
GP[79]
HD13/
MTXD1/
GP[71]
HD14/
MTXD0/
GP[72]
HD10/
MCRS/
GP[68]
HD3/
VLYNQ_
SCRUN/
GP[58]
EM_A[6]/
GP[95]
EM_A[10]/
GP[91]
VLYNQ_TXD2/ VLYNQ_RXD2/
DV
DD33
GP[65]
GP[61]
HR/W/
MRXCLK/
GP[77]
HD15/
MTXCLK/
GP[73]
HD11/
MTXD3/
GP[69]
HD8/
HD5/
VLYNQ_
CLOCK/
GP[57]
HD2/
VLYNQ_RXD1/
GP[60]
EM_A[5]/
GP[96]
EM_A[8]/
GP[93]
V
DV
VLYNQ_TXD3/ VLYNQ_TXD0/
GP[66]
SS
DD33
2
GP[63]
6
1
3
4
5
7
8
9
10
11
Figure 2-13. ZDU Pin Map [Quadrant D]
2.4.2 Signal Groups Description
TBD
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Fixed-Point Digital Signal Processor
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SPRS346A–JANUARY 2007–REVISED MARCH 2007
2.5 Terminal Functions
The terminal functions tables (Table 2-7 through Table 2-28) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see the Device Configurations section of this data manual.
All device boot and configuration pins are multiplexed configuration pins— meaning they are multiplexed
with functional pins. These pins function as device boot and configuration pins only during device reset.
The input states of these pins are sampled and latched into the BOOTCFG register when device reset is
deasserted (see Note below). After device reset is deasserted, the values on these multiplexed pins no
longer have to hold the configuration.
For proper device operation, external pullup/pulldown resistors may be required on these device boot and
configuration pins. Section 3.2.1, Pullup/Pulldown Resistors discusses situations where external
pullup/pulldown resistors are required.
Note: Internal to the chip, the two device reset pins RESET and POR are logically AND’d together for the
purpose of latching device boot and configuration pins. The values on all device boot and configuration
pins are latched into the BOOTCFG register when the logical AND of RESET and POR transitions from
low-to-high.
Table 2-7. BOOT Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
BOOT
GP[25]/
(BOOTMODE3)
G16
G15
F15
F18
H21
L20
K20
J20
Bootmode configuration bits. These bootmode functions along with
the FASTBOOT function determine what device bootmode
configuration is selected.
The C6421 device supports several types of bootmodes along with a
FASTBOOT option; for more details on the types/options, see , Boot
Modes.
GP[24]/
(BOOTMODE2)
IPD
I/O/Z
DVDD33
GP[23]/
(BOOTMODE1)
GP[22]/
(BOOTMODE0)
Fast Boot
0 = Not Fast Boot
1 = Fast Boot
GP[26]/
(FASTBOOT)
IPD
I/O/Z
G17
A17
A16
B16
K19
B21
B20
A20
DVDD33
EM_A[4]/
GP[10]/
(PLLMS2)
IPD
I/O/Z
DVDD33
Fast Boot PLL Multiplier Select (PLLMS)
EM_A[1]/(ALE)/
GP[9]/
(PLLMS1)
IPD
I/O/Z
These pins select the PLL multiplier for Fast Boot.
For more details, see , Fast Boot PLL Multiplier Select (PLLMS).
DVDD33
EM_A[2]/(CLE)/
GP[8]/
(PLLMS0)
IPD
I/O/Z
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-7. BOOT Terminal Functions (continued)
SIGNAL
ZWT
TYPE(1) OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
NO.
EM_A[0]/
GP[7]/(AEM2)
IPD
I/O/Z
Selects EMIFA Pinout Mode
B17
C21
E20
DVDD33
The C6421 supports the following EMIFA Pinout Modes:
EM_BA[0]/
GP[6]/(AEM1)
IPD
I/O/Z
C17
C16
AEM[2:0] = 000, No EMIFA
AEM[2:0] = 010, EMIFA (Async) Pinout Mode 2
AEM[2:0] = 101, EMIFA (NAND) Pinout Mode 5
DVDD33
EM_BA[1]/
GP[5]/(AEM0)
IPD
I/O/Z
C20
DVDD33
This signal doesn't actually affect the EMIFA module. It only affects
how the EMIFA is pinned out.
For proper C6421 device operation, if this pin is both routed and
3-stated (not driven) during device reset, it must be pulled down via
an external resistor. For more detailed information on
pullup/pulldown resistors, see Section 3.2.1, Pullup/Pulldown
Resistors.
IPD
I/O/Z
RMTXD0/GP[28]
H16
H17
J21
L19
DVDD33
Endian selection
0 = Big Endian
1 = Little Endian
RMTXD1/GP[27]/
(LENDIAN)
IPU
I/O/Z
DVDD33
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Table 2-8. Oscillator/PLL Terminal Functions
SIGNAL
ZWT
TYPE(1)
OTHER(2)
DESCRIPTION
ZDU
NO.
NAME
NO.
OSCILLATOR, PLL
Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz).
If the internal oscillator is bypassed, this is the external oscillator clock
input.(3)
MXI/
CLKIN
K19
N22
I
MXVDD
MXO
J19
L18
M22
N21
O
S
MXVDD
Crystal output for MX oscillator
1.8 V power supply for MX oscillator. On the board, this pin can be
connected to the same 1.8 V power supply as DVDDR2
(4)
MXVDD
.
(4)
(4)
MXVSS
K18
L16
M21
N20
GND
S
Ground for MX oscillator
PLLPWR18
1.8 V power supply for PLLs
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information on external board connections, see , External Clock Input From MXI/CLKIN Pin.
(4) For more information, see the Recommended Operating Conditions table.
Table 2-9. Clock Generator Terminal Functions
SIGNAL
TYPE(1) OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
CLOCK GENERATOR
This pin is multiplexed between the System Clock generator (PLL1), PWM2,
and GPIO.
For the System Clock generator (PLL1), it is clock output CLKOUT0. This is
configurable for toggling at the device input clock frequency (MXI/CLKIN
frequency) or other divided-down (/1 to /32) clock outputs.
CLKOUT0/
PWM2/GP[84]
IPD
I/O/Z
M1
R1
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-10. RESET and JTAG Terminal Functions
SIGNAL
ZWT
TYPE(1) OTHER(2)(3)
RESET
DESCRIPTION
ZDU
NO.
NAME
NO.
IPU
DVDD33
RESET
RESETOUT
POR
M4
N3
N4
R3
T3
R2
I
Device reset
–
O/Z
Reset output status pin. The RESETOUT pin indicates when the
device is in reset.
DVDD33
IPU
DVDD33
I
Power-on reset.
JTAG
IPU
DVDD33
TMS
TDO
TDI
R3
P3
P4
N1
V3
U2
U3
U1
I
JTAG test-port mode select input
JTAG test-port data output
JTAG test-port data input
JTAG test-port clock input
–
O/Z
DVDD33
IPU
DVDD33
I
IPU
DVDD33
TCK
I
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see
the IEEE 1149.1 JTAG compatibility statement portion of this data
sheet
IPD
DVDD33
TRST
R2
V2
I
IPU
I/O/Z
EMU1
EMU0
N2
P2
T2
T1
Emulation pin 1
Emulation pin 0
DVDD33
IPU
I/O/Z
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-11. EMIFA Terminal Functions (Boot Configuration)
SIGNAL
ZWT
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
NO.
EMIFA: BOOT CONFIGURATION
EM_BA[1]/
GP[5]/(AEM0)
IPD
DVDD33
These pins are multiplexed between the EMIFA, and GPIO. When
RESET or POR is asserted, these pins function as EMIFA
configuration pins. At reset, the input states of AEM[2:0] are sampled
to set the EMIFA Pinout Mode. For more details, see , Configurations
at Reset. After reset, these pins function as EMIFA or GPIO pin
functions based on pin mux selection.
C16
C17
C20
E20
I/O/Z
I/O/Z
EM_BA[0]/
GP[6]/(AEM1)
IPD
DVDD33
EM_A[0]/
GP[7]/(AEM2)
IPD
DVDD33
B17
C21
I/O/Z
For more details on the AEM functions, see , EMIFA Pinout Mode
(AEM[2:0]).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal.
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EMIFA FUNCTIONAL PINS: 8-Bit ASYNC/NOR (EMIFA Pinout Mode 2, AEM[2:0] = 010)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEM[2:0], etc.). For more details, see ,
Multiplexed Pin Configurations.
This pin is multiplexed between EMIFA, and GPIO.
For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with
asynchronous memories (i.e., NOR flash).
EM_CS2/
GP[12]
IPD
DVDD33
This is the chip select for the default boot and ROM boot modes.
C19
C22
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA, and GPIO.
For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with
asynchronous memories (i.e., NOR flash).
EM_CS3/
GP[13]
IPD
DVDD33
C18
D22
H22
I/O/Z
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA, and GPIO.
For EMIFA, it is Chip Select 4 output EM_CS4 for use with
asynchronous memories (i.e., NOR flash).
RMRXD0/
EM_CS4/
GP[32]
IPD
DVDD33
E19
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA, and GPIO.
For EMIFA, it is Chip Select 5 output EM_CS5 for use with
asynchronous memories (i.e., NOR flash).
RMRXD1/
EM_CS5/
GP[33]
IPD
DVDD33
F19
D13
J22
I/O/Z
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA and GPIO.
For EMIFA, it is read/write output EM_R/W.
EM_R/W/
GP[35]
IPD
DVDD33
C17
EM_WAIT/
(RDY/BSY)
IPU
DVDD33
For EMIFA (ASYNC/NOR), this pin is wait state extension input
EM_WAIT.
E15
D15
E14
D20
D19
C19
I/O/Z
I/O/Z
I/O/Z
IPU
DVDD33
EM_OE
EM_WE
For EMIFA, it is output enable output EM_OE.
IPU
DVDD33
For EMIFA, it is write enable output EM_WE.
This pin is multiplexed between EMIFA and GPIO.
EM_BA[0]/
GP[6]/(AEM1)
IPD
DVDD33
For EMIFA, this is the Bank Address 0 output (EM_BA[0]).
When connected to an 8-bit asynchronous memory, this pin is the
lowest order bit of the byte address.
C17
C16
E20
C20
I/O/Z
I/O/Z
This pin is multiplexed between EMIFA and GPIO.
EM_BA[1]/
GP[5]/(AEM0)
IPD
DVDD33
For EMIFA, this is the Bank Address 1 output EM_BA[1].
When connected to an 8-bit asynchronous memory, this pin is the 2nd
bit of the address.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)
SIGNAL
TYPE(1)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
EM_A[21]/GP[34]
D12
C12
B12
D11
A11
C11
B11
A10
B10
D10
C10
A9
C16
C15
C14
A14
B14
B13
C13
A13
A12
B12
C12
B11
For EMIFA (AEM[2:0] = 010), this pin is address bit 21 output
EM_A[21].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
EM_A[20]/GP[44]
EM_A[19]/GP[45]
EM_A[18]/GP[46]
EM_A[17]/GP[47]
EM_A[16]/GP[48]
EM_A[15]/GP[49]
EM_A[14]/GP[50]
EM_A[13]/GP[51]
EM_A[12]/GP[89]
EM_A[11]/GP[90]
EM_A[10]/GP[91]
For EMIFA (AEM[2:0] = 010), this pin is address bit 20 output
EM_A[20].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 19 output
EM_A[19].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 18 output
EM_A[18].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 17 output
EM_A[17].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 16 output
EM_A[16].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 15 output
EM_A[15].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 14 output
EM_A[14].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 13 output
EM_A[13].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 12 output
EM_A[12].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 11 output
EM_A[11].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 10 output
EM_A[10].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
EM_A[9]/GP[92]
EM_A[8]/GP[93]
EM_A[7]/GP[94]
EM_A[6]/GP[95]
EM_A[5]/GP[96]
D9
B9
C9
D8
B8
C11
A11
C10
B10
A10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
For EMIFA (AEM[2:0] = 010), this pin is address bit 9 output EM_A[9].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 8 output EM_A[8].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 7 output EM_A[7].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 6 output EM_A[6].
This pin is multiplexed between EMIFA and GPIO.
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 5 output EM_A[5].
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
This pin is multiplexed between EMIFA and GPIO.
EM_A[4]/
GP[10]/(PLLMS2)
IPD
DVDD33
A17
B18
B16
A16
B21
D21
A20
B20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
For EMIFA (AEM[2:0] = 010), this pin is address bit 4 output EM_A[4].
This pin is multiplexed between EMIFA and GPIO.
EM_A[3]/
GP[11]
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 3 output EM_A[3].
This pin is multiplexed between EMIFA and GPIO.
EM_A[2]/(CLE)/
GP[8]/(PLLMS0)
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address bit 2 output EM_A[2].
This pin is multiplexed between EMIFA and GPIO.
EM_A[1]/(ALE)/
GP[9]/(PLLMS1)
IPD
DVDD33
For EMIFA (AEM[2:0] = 010), this pin is address output EM_A[1].
This pin is multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), this pin is Address output EM_A[0],
which is the least significant bit on a 32-bit word address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the
address.
EM_A[0]/
GP[7]/(AEM2)
IPD
DVDD33
B17
C21
I/O/Z
EM_D0/
GP[14]
IPD
DVDD33
D16
D18
D17
E16
E18
E17
F16
F17
E21
G20
E22
F20
G21
F22
F21
H20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
EM_D1/
GP[15]
IPD
DVDD33
EM_D2/
GP[16]
IPD
DVDD33
EM_D3/
GP[17]
IPD
DVDD33
These pins are multiplexed between EMIFA and GPIO.
For EMIFA (AEM[2:0] = 010), these pins are the 8-bit bi-directional
data bus (EM_D[7:0]).
EM_D4/
GP[18]
IPD
DVDD33
EM_D5/
GP[19]
IPD
DVDD33
EM_D6/
GP[20]
IPD
DVDD33
EM_D7/
GP[21]
IPD
DVDD33
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 2, AEM[2:0] = 010)
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_A[1]/(ALE)/
GP[9]/(PLLMS1)
IPD
DVDD33
A16
B16
B20
A20
I/O/Z
I/O/Z
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_A[2]/(CLE)/
GP[8]/(PLLMS0)
IPD
DVDD33
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
EM_WAIT/
(RDY/BSY)
IPU
DVDD33
E15
D15
E14
D20
D19
C19
I/O/Z
I/O/Z
I/O/Z
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
When used for EMIFA (NAND), this pin is read enable output (RE).
IPU
DVDD33
EM_OE
EM_WE
IPU
DVDD33
When used for EMIFA (NAND), this pin is write enable output (WE).
This pin is multiplexed between EMIFA (NAND) and GPIO.
For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use
with NAND flash.
EM_CS2/
GP[12]
IPD
DVDD33
This is the chip select for the default boot and ROM boot modes.
C19
C22
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
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Table 2-12. EMIFA Terminal Functions (EMIFA Pinout Mode 2, AEM[2:0] = 010) (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
This pin is multiplexed between EMIFA (NAND) and GPIO.
For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use
with NAND flash.
EM_CS3/
GP[13]
IPD
DVDD33
C18
D22
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and
GPIO.
For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with
NAND flash.
RMRXD0/
EM_CS4/
GP[32]
IPD
DVDD33
E19
H22
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and
GPIO.
For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with
NAND flash.
RMRXD1/
EM_CS5/
GP[33]
IPD
DVDD33
F19
J22
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
EM_D0/
GP[14]
IPD
DVDD33
D16
D18
D17
E16
E18
E17
F16
F17
E21
G20
E22
F20
G21
F22
F21
H20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
EM_D1/
GP[15]
IPD
DVDD33
EM_D2/
GP[16]
IPD
DVDD33
EM_D3/
GP[17]
IPD
DVDD33
These pins are multiplexed between EMIFA (NAND) and GPIO.
For EMIFA (NAND) (AEM[2:0] = 010), these pins are the 8-bit
bi-directional data bus (EM_D[7:0]).
EM_D4/
GP[18]
IPD
DVDD33
EM_D5/
GP[19]
IPD
DVDD33
EM_D6/
GP[20]
IPD
DVDD33
EM_D7/
GP[21]
IPD
DVDD33
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Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EMIFA FUNCTIONAL PINS: 8-Bit NAND (EMIFA Pinout Mode 5, AEM[2:0] = 101)
Actual pin functions are determined by the PINMUX0 and PINMUX1 register bit settings (e.g., AEM[2:0], etc.). For more details, see ,
Multiplexed Pin Configurations.
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_A[1]/(ALE)/
GP[9]/(PLLMS1)
IPD
DVDD33
A16
B16
B20
A20
I/O/Z
I/O/Z
When used for EMIFA (NAND) , this pin is the Address Latch Enable
output (ALE).
This pin is multiplexed between EMIFA (NAND) and GPIO.
EM_A[2]/(CLE)/
GP[8]/(PLLMS0)
IPD
DVDD33
When used for EMIFA (NAND) , this pin is the Command Latch
Enable output (CLE).
EM_WAIT/
(RDY/BSY)
IPU
DVDD33
E15
D15
E14
D20
D19
C19
I/O/Z
I/O/Z
I/O/Z
When used for EMIFA (NAND), it is ready/busy input (RDY/BSY).
When used for EMIFA (NAND), this pin is read enable output (RE).
IPU
DVDD33
EM_OE
EM_WE
IPU
DVDD33
When used for EMIFA (NAND), this pin is write enable output (WE).
This pin is multiplexed between EMIFA (NAND) and GPIO.
For EMIFA (NAND), this pin is Chip Select 2 output EM_CS2 for use
with NAND flash.
EM_CS2/
GP[12]
IPD
DVDD33
This is the chip select for the default boot and ROM boot modes.
C19
C18
E19
C22
D22
H22
I/O/Z
I/O/Z
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMIFA (NAND) and GPIO.
For EMIFA (NAND), this pin is Chip Select 3 output EM_CS3 for use
with NAND flash.
EM_CS3/
GP[13]
IPD
DVDD33
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and
GPIO.
For EMIFA (NAND), it is Chip Select 4 output EM_CS4 for use with
NAND flash.
RMRXD0/
EM_CS4/
GP[32]
IPD
DVDD33
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
This pin is multiplexed between EMAC (RMII), EMIFA (NAND), and
GPIO.
For EMIFA (NAND), it is Chip Select 5 output EM_CS5 for use with
NAND flash.
RMRXD1/
EM_CS5/
GP[33]
IPD
DVDD33
F19
J22
I/O/Z
Note: This pin features an internal pulldown (IPD). If this pin is
connected and used as an EMIFA chip select signal, for proper device
operation, an external pullup resistor must be used to ensure the
EM_CSx function defaults to an inactive (high) state.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-13. EMIFA Terminal Functions (EMIFA Pinout Mode 5, AEM[2:0] = 101) (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
EM_D0/
GP[14]
IPD
DVDD33
D16
D18
D17
E16
E18
E17
F16
F17
E21
G20
E22
F20
G21
F22
F21
H20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
EM_D1/
GP[15]
IPD
DVDD33
EM_D2/
GP[16]
IPD
DVDD33
EM_D3/
GP[17]
IPD
DVDD33
These pins are multiplexed between EMIFA (NAND) and GPIO.
For EMIFA (NAND) AEM[2:0] = 101, these pins are the 8-bit
bi-directional data bus (EM_D[7:0]).
EM_D4/
GP[18]
IPD
DVDD33
EM_D5/
GP[19]
IPD
DVDD33
EM_D6/
GP[20]
IPD
DVDD33
EM_D7/
GP[21]
IPD
DVDD33
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Table 2-14. DDR2 Memory Controller Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
DDR2 Memory Controller
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
DDR_CLK0
DDR_CLK0
DDR_CKE
DDR_CS
W7
W8
V8
T9
AB7
AB8
AA8
Y11
Y10
Y7
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DVDDR2
DDR2 Clock Output
DDR2 Differential Clock Output
DDR2 Clock Enable Output
DDR2 Active Low Chip Select Output
DDR2 Active Low Write Enable Output
DDR_WE
T8
DDR_DQM[1]
T6
DDR2 Data Mask Outputs
DQM1: For DDR_D[15:8]
DQM0: For lower byte DDR_D[7:0]
DDR_DQM[0]
T4
Y4
I/O/Z
DVDDR2
DDR_RAS
DDR_CAS
U7
T7
U4
Y8
Y9
I/O/Z
I/O/Z
I/O/Z
DVDDR2
DVDDR2
DVDDR2
DDR2 Row Access Signal Output
DDR2 Column Access Signal Output
DDR_DQS[0]
AA4
Data Strobe Input/Outputs for each byte of the 16-bit data bus. They
are outputs to the DDR2 memory when writing and inputs when
reading. They are used to synchronize the data transfers.
DQS1: For DDR_D[15:8]
DDR_DQS[1]
U6
AA7
I/O/Z
I/O/Z
DVDDR2
DQS0: For bottom byte DDR_D[7:0]
DDR_BS[0]
DDR_BS[1]
DDR_BS[2]
DDR_A[12]
DDR_A[11]
DDR_A[10]
DDR_A[9]
DDR_A[8]
DDR_A[7]
DDR_A[6]
DDR_A[5]
DDR_A[4]
DDR_A[3]
DDR_A[2]
DDR_A[1]
DDR_A[0]
U8
V9
AA9
AB9
Bank Select Outputs (BS[2:0]). Two are required to support 1Gb DDR2
memories.
DVDDR2
U9
AB10
AA10
AA11
AB11
AA12
Y12
W9
W10
U10
U11
V10
V11
W11
W12
V12
U12
V13
U13
W13
AB12
AA13
Y13
I/O/Z
DVDDR2
DDR2 Address Bus Output
AB13
AA14
Y14
AB14
AB15
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Fore more information, see the Recommended Operating Conditions table
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Table 2-14. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
ZDU
NO.
NAME
NO.
V7
DDR_D[15]
DDR_D[14]
DDR_D[13]
DDR_D[12]
DDR_D[11]
DDR_D[10]
DDR_D[9]
AB6
Y6
W6
V6
AA6
AB5
Y5
W5
V5
U5
W4
V4
AA5
W5
DDR_D[8]
AB4
W4
I/O/Z
DVDDR2
DDR2 bi-directional data bus is configured as 16-bits wide.
DDR_D[7]
W3
V3
DDR_D[6]
AB3
Y3
DDR_D[5]
U3
V2
DDR_D[4]
AA3
AA2
W2
DDR_D[3]
U2
U1
T2
DDR_D[2]
DDR_D[1]
Y2
DDR_D[0]
T1
Y1
(3)
(3)
(3)
DDR_VREF
DDR_VSSDLL
DDR_VDDDLL
T15
T13
T12
W18
W15
W14
I
Reference voltage input for the SSTL_18 I/O buffers
Ground for the DDR2 DLL
GND
S
Power (1.8 Volts) for the DDR2 Digital Locked Loop
Impedance control for DDR2 outputs. This must be connected via a
(3)
(3)
DDR_ZN
DDR_ZP
T10
T11
W12
W13
200-Ω resistor to DVDDR2
Impedance control for DDR2 outputs. This must be connected via a
200-Ω resistor to VSS
.
.
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Table 2-15. EMAC (MII/RMII) and MDIO Terminal Functions
SIGNAL
ZWT
TYPE(1)
OTHER(2)(3)
EMAC (MII)
DESCRIPTION
ZDU
NO.
NAME
NO.
HCNTL1/MTXEN/
GP[75]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Enable output MTXEN.
D3
A4
C6
C5
D5
B4
D4
A3
C4
A4
C6
A5
C5
B4
B5
A3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
HD15/MTXCLK/
GP[73]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Clock input MTXCLK.
HD9/MCOL/
GP[67]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Collision Detect input MCOL.
HD11/MTXD3/
GP[69]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 3 output MTXD3.
HD12/MTXD2/
GP[70]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 2 output MTXD2.
HD13/MTXD1/
GP[71]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 1 output MTXD1.
HD14/MTXD0/
GP[72]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Transmit Data 0 output MTXD0.
HR/W/MRXCLK/
GP[77]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Clock input MRXCLK.
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data Valid input
MRXDV.
HHWIL/MRXDV/
GP[74]
IPD
DVDD33
C4
D3
I/O/Z
HCNTL0/MRXER/
GP[76]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Error input MRXER.
B3
B5
C2
D2
B2
C3
B2
B6
D2
C3
B3
C2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
HD10/MCRS/
GP[68]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Carrier Sense input MCRS.
HINT/MRXD3/
GP[82]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 3 input MRXD3.
HRDY/MRXD2/
GP[80]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 2 input MRXD2.
HDS1/MRXD1/
GP[79]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive data 1 input MRXD1.
HDS2/MRXD0/
GP[78]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In Ethernet MAC (MII) mode, it is Receive Data 0 input MRXD0.
EMAC (RMII)
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC carrier sense/receive
data valid (RMCRSDV) [I].
IPD
DVDD33
RMCRSDV/GP[30]
RMRXER/GP[52]
G19
A15
H17
H16
D19
H15
K22
A19
L19
J21
G22
K21
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC receive error (RMRXER)
[I].
IPD
DVDD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit data pin 1
(RMTXD1) [O/Z].
RMTXD1/GP[27]/
(LENDIAN)
IPU
DVDD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit data pin 0
(RMTXD0) [O/Z].
IPD
DVDD33
RMTXD0/GP[28]
RMREFCLK/GP[31]
RMTXEN/GP[29]
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC RMII reference clock
(RMREFCLK) [I].
IPD
DVDD33
This pin is multiplexed between EMAC (RMII) and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC transmit enable
(RMTXEN) [O/Z].
IPD
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-15. EMAC (MII/RMII) and MDIO Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
ZDU
NO.
NAME
NO.
This pin is multiplexed between EMAC (RMII), EMIFA, and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC receive data pin 1
(RMRXD1) [I].
RMRXD1/EM_CS5/
GP[33]
IPD
DVDD33
F19
J22
I/O/Z
I/O/Z
This pin is multiplexed between EMAC (RMII), EMIFA, and GPIO.
In Ethernet MAC(RMII) mode, it is EMAC receive data pin 0
(RMRXD0) [I].
RMRXD0/EM_CS4/
GP[32]
IPD
DVDD33
E19
H22
MDIO
This pin is multiplexed between HPI, MDIO, and GPIO.
In Ethernet MAC mode, it is Management Data Clock output
MDCLK.
HCS/MDCLK/
GP[81]
IPU
DVDD33
C1
D1
D1
C1
I/O/Z
I/O/Z
HAS/MDIO/
GP[83]
IPU
DVDD33
This pin is multiplexed between HPI, MDIO, and GPIO.
In Ethernet MAC mode, it is Management Data I/O MDIO (I/O/Z).
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Table 2-16. VLYNQ Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
VLYNQ
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
VLYNQ_CLOCK/
GP[57]
IPU
DVDD33
This pin is multiplexed between VLYNQ and GPIO.
For VLYNQ, it is the clock VLYNQ_CLOCK (I/O/Z).
A7
C8
A8
B9
I/O/Z
I/O/Z
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is the Serial Clock run request VLYNQ_SCRUN
(I/O/Z).
HD0/VLYNQ_SCRUN/
GP[58]
IPU
DVDD33
HD8/VLYNQ_TXD3/
GP[66]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.
A5
B6
D6
A6
C7
B7
A8
D7
A6
B7
C7
A7
C8
B8
A9
C9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
HD7/VLYNQ_TXD2/
GP[65]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.
HD6/VLYNQ_TXD1/
GP[64]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.
HD5/VLYNQ_TXD0/
GP[63]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is transmit bus bit 0 output VLYNQ_TXD0.
HD4/VLYNQ_RXD3/
GP[62]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.
HD3/VLYNQ_RXD2/
GP[61]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.
HD2/VLYNQ_RXD1/
GP[60]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.
HD1/VLYNQ_RXD0/
GP[59]
IPD
DVDD33
This pin is multiplexed between HPI, VLYNQ, and GPIO.
For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-17. Host-Port Interface Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
Host-Port Interface (HPI)
HD0/VLYNQ_SCRUN/
GP[58]
IPU
DVDD33
C8
D7
A8
B7
C7
A6
D6
B6
A5
C6
B5
C5
D5
B4
D4
A4
B9
C9
A9
B8
C8
A7
C7
B7
A6
C6
B6
A5
C5
B4
B5
A4
HD1/VLYNQ_RXD0/
GP[59]
HD2/VLYNQ_RXD1/
GP[60]
HD3/VLYNQ_RXD2/
GP[61]
HD4/VLYNQ_RXD3/
GP[62]
HD5/VLYNQ_TXD0/
GP[63]
HD6/VLYNQ_TXD1/
GP[64]
This pin is multiplexed between HPI, VLYNQ or EMAC (MII),
and GPIO.
In HPI mode, these pins are host-port data pins HD[15:0]
(I/O/Z) and are multiplexed internally with the HPI address
lines.
HD7/VLYNQ_TXD2/
GP[65]
I/O/Z
HD8/VLYNQ_TXD3/
GP[66]
IPD
DVDD33
HD9/MCOL/
GP[67]
HD10/MCRS/
GP[68]
HD11/MTXD3/
GP[69]
HD12/MTXD2/
GP[70]
HD13/MTXD1/
GP[71]
HD14/MTXD0/
GP[72]
HD15/MTXCLK/
GP[73]
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is half-word identification input HHWIL
(I).
HHWIL/MRXDV/
GP[74]
IPD
DVDD33
C4
D3
D3
C4
I/O/Z
I/O/Z
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is control input 1 HCNTL1 (I). The state
of HCNTL1 and HCNTL0 determines if address, data, or
control information is being transmitted between an external
host and the C6421.
HCNTL1/MTXEN/
GP[75]
IPD
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is control input 0 HCNTL0 (I). The state
of HCNTL1 and HCNTL0 determines if address, data, or
control information is being transmitted between an external
host and the C6421.
HCNTL0/MRXER/
GP[76]
IPD
DVDD33
B3
B2
I/O/Z
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is host read or write select input
HR/W(I).
HR/W/MRXCLK/
GP[77]
IPD
DVDD33
A3
C3
A3
C2
I/O/Z
I/O/Z
HDS2/MRXD0/
GP[78]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is host data strobe input 2 HDS2 (I).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-17. Host-Port Interface Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
HDS1/MRXD1/
GP[79]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is host data strobe input 1 HDS1 (I).
B2
B3
I/O/Z
I/O/Z
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is host ready output from DSP to host
(O/Z).
HRDY/MRXD2/
GP[80]
IPU
DVDD33
D2
C3
This pin is multiplexed between HPI, MDIO, and GPIO.
In HPI mode, this pin is HPI active low chip select input HCS
(I).
HCS/MDCLK/
GP[81]
IPU
DVDD33
C1
D1
I/O/Z
HINT/RXD3/
GP[82]
IPU
DVDD33
This pin is multiplexed between HPI, EMAC (MII), and GPIO.
In HPI mode, this pin is host interrupt output HINT (O/Z).
C2
D1
D2
C1
I/O/Z
I/O/Z
HAS/MDIO/
GP[83]
IPU
DVDD33
This pin is multiplexed between HPI, MDIO, and GPIO.
In HPI mode, this pin is host address strobe HAS (I).
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Table 2-18. I2C Terminal Functions
SIGNAL
ZWT
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
NO.
I2C
For I2C, this pin is I2C clock. In I2C master mode, this pin is an
output. In I2C slave mode, this pin is an input.
When the I2C module is used, for proper device operation, this pin
must be pulled up via an external resistor.
SCL
SDA
M2
M3
N2
P2
I/O/Z
I/O/Z
DVDD33
For I2C, this pin is the I2C bi-directional data signal.
When the I2C module is used, for proper device operation, this pin
must be pulled up via an external resistor.
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-19. Multichannel Buffered Serial Port 0 (McBSP0) Terminal Functions
SIGNAL
ZWT
NO.
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
Multichannel Buffered Serial Port 0 (McBSP0)
Pin Muxing Control: TBD
CLKS0/TOUT0L/
IPD
DVDD33
This pin is multiplexed between McBSP0, Timer0, and GPIO.
For McBSP0, it is McBSP0 external clock source (I).
J4
L3
J1
K1
I/O/Z
I/O/Z
I/O/Z
GP[97]
ACLKR0/CLKX0/
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit clock CLKX0 (I/O/Z).
H1
GP[99]
AHCLKR0/CLKR0/
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive clock CLKR0 (I/O/Z).
J2
GP[101]
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 transmit frame synchronization FSX0
(I/O/Z).
AXR0[2]/FSX0/
H3
IPD
DVDD33
J2
J3
I/O/Z
I/O/Z
GP[103]
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 receive frame synchronization FSR0
(I/O/Z).
AXR0[3]/FSR0/
G4
IPD
DVDD33
GP[102]
AXR0[1]/DX0/
J3
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data transmit output DX0 (O/Z).
K2
K3
I/O/Z
I/O/Z
GP[104]
AFSR0/DR0/
H4
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McBSP0, it is McBSP0 data receive input DR0 (I).
GP[100]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-20. Multichannel Audio Serial Port (McASP0) Terminal Functions
SIGNAL
ZWT
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
NO.
McASP0
AMUTEIN0/
GP[109]
IPD
DVDD33
This pin is multiplexed between McASP0 and GPIO.
For McASP0, it is McASP0 mute input AMUTEIN0 (I).
F2
G3
H1
G3
H3
J1
I/O/Z
I/O/Z
I/O/Z
AMUTE0/
GP[110]
IPD
DVDD33
This pin is multiplexed between McASP0 and GPIO.
For McASP0, it is McASP0 mute output AMUTE0 (O/Z).
ACLKR0/CLKX0/
GP[99]
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive bit clock ACLKR0 (I/O/Z).
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive high-frequency master clock
AHCLKR0 (I/O/Z).
AHCLKR0/CLKR0/
GP[101]
IPD
DVDD33
J2
F1
G1
K1
G1
H1
I/O/Z
I/O/Z
I/O/Z
ACLKX0/
GP[106]
IPD
DVDD33
This pin is multiplexed between McASP0 and GPIO.
For McASP0, it is McASP0 transmit bit clock ACLKX0 (I/O/Z).
This pin is multiplexed between McASP0 and GPIO.
For McASP0, it is McASP0 transmit high-frequency master clock
AHCLKX0 (I/O/Z).
AHCLKX0/
GP[108]
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 receive frame synchronization AFSX0
(I/O/Z).
AFSR0/DR0/
GP[100]
IPD
DVDD33
H4
G2
G4
H3
J3
K3
G2
J3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin is multiplexed between McASP0 and GPIO.
For McASP0, it is McASP0 transmit frame synchronization AFSR0
(I/O/Z).
AFSX0/
GP[107]
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 3
AXR0[3] (I/O/Z).
AXR0[3]/FSR0/
GP[102]
IPD
DVDD33
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 2
AXR0[2] (I/O/Z).
AXR0[2]/FSX0/
GP[103]
IPD
DVDD33
J2
This pin is multiplexed between McASP0, McBSP0, and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 1
AXR0[1] (I/O/Z).
AXR0[1]/DX0/
GP[104]
IPD
DVDD33
K2
H2
This pin is multiplexed between McASP0 and GPIO.
For McASP0, it is McASP0 transmit/receive (TX/RX) data pin 0
AXR0[0] (I/O/Z).
AXR0[0]/
GP[105]
IPD
DVDD33
H2
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-21. UART0 Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
UART0
URXD0/
GP[85]
IPU
DVDD33
This pin is multiplexed between UART0 (Data) and GPIO.
When used by UART0 this pin is the receive data input URXD0.
L2
K3
L1
M2
N1
P1
I/O/Z
I/O/Z
I/O/Z
UTXD0/
GP[86]
IPU
DVDD33
This pin is multiplexed between UART0 (Data) and GPIO.
In UART0 mode, this pin is the transmit data output UTXD0.
UCTS0/
GP[87]
IPU
DVDD33
This pin is multiplexed between the UART0 (Flow Control) and GPIO.
In UART0 mode, this pin is the clear to send input UCTS0.
URTS0/
PWM0/
GP[88]
This pin is multiplexed between the UART0 (Flow Control), PWM0,
and GPIO.
In UART0 mode, this pin is the ready to send output URTS0.
IPU
DVDD33
L3
M3
I/O/Z
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-22. PWM0, PWM1, and PWM2 Terminal Functions
SIGNAL
ZWT
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
NO.
PWM2
This pin is multiplexed between the System Clock generator (PLL1),
PWM2, and GPIO.
For PWM2, this pin is output PWM2.
CLKOUT0/PWM2/
GP[84]
IPD
DVDD33
M1
R1
F3
I/O/Z
I/O/Z
I/O/Z
PWM1
IPD
DVDD33
This pin is multiplexed between GPIO and PWM1.
For PWM1, this pin is output PWM1.
GP[4]/PWM1
F3
L3
PWM0
This pin is multiplexed between the UART0 (Flow Control), PWM0,
and GPIO.
For PWM0, this pin is output PWM0.
URTS0/PWM0/
GP[88]
IPU
DVDD33
M3
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-23. Timer 0, Timer 1, and Timer 2 Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
Timer 2
No external pins. The Timer 2 (watchdog) peripheral pins are not pinned out as external pins.
Timer 1
This pin is multiplexed between the Timer 1 and GPIO.
For Timer 1, this pin is the timer 1 input pin for the lower 32-bit
counter
TINP1L/
GP[56]
IPU
DVDD33
L4
K4
P3
N3
I/O/Z
I/O/Z
This pin is multiplexed between the Timer 1 and GPIO.
For Timer 1, this pin is the timer 1 output pin for the lower 32-bit
counter
TOUT1L/
GP[55]
IPU
DVDD33
Timer 0
This pin is multiplexed between the Timer 0 and GPIO.
For Timer 0, this pin is the timer 0 input pin for the lower 32-bit
counter
TINP0L/
GP[98]
IPD
DVDD33
K2
J4
L2
L3
I/O/Z
I/O/Z
CLKS0/
TOUT0L/
GP[97]
This pin is multiplexed between the McBSP0, Timer 0, and GPIO.
For Timer 0, this pin is the timer 0 output pin for the lower 32-bit
counter
IPD
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-24. GPIO Terminal Functions
SIGNAL
ZWT
NO.
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
GPIO
92 out of 111 GPIO pins on the C6421 device are multiplexed with other peripherals pin functions (e.g., EMAC/MDIO, McASP0, McBSP0,
Timer 0, Timer 1, UART0, PWM0, PWM1, PWM2, EMIFA, and the CLKOUT0 pin), see the peripheral-specific Terminal Functions tables for
the GPIO multiplexing.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-25. Standalone GPIO 3.3 V Terminal Functions
SIGNAL
TYPE(1)
OTHER(2)(3)
Standalone GPIO 3.3 V
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
IPD
DVDD33
GP[0]
GP[1]
GP[2]
GP[3]
E1
E2
E1
E2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
This pin functions as standalone GPIO pin 0.
This pin functions as standalone GPIO pin 1.
This pin functions as standalone GPIO pin 2.
This pin functions as standalone GPIO pin 3.
IPD
DVDD33
IPD
DVDD33
E3
F1
IPD
DVDD33
E4
F2
GP[22]/
(BOOTMODE0)
IPD
DVDD33
F18
F15
G15
G16
G17
C15
B15
C14
B14
D14
C13
B13
A12
A13
A14
J20
K20
L20
H21
K19
B19
B18
B17
A16
C18
B16
B15
A15
A17
A18
GP[23]/
(BOOTMODE1)
IPD
DVDD33
GP[24]/
(BOOTMODE2)
IPD
DVDD33
These pins function as boot configuration pins during device reset.
After device reset, these pins function as standalone GPIO.
GP[25]/
(BOOTMODE3)
IPD
DVDD33
GP[26]/
(FASTBOOT)
IPD
DVDD33
IPD
DVDD33
GP[36]
GP[37]
GP[38]
GP[39]
GP[40]
GP[41]
GP[42]
GP[43]
GP[53]
GP[54]
This pin functions as standalone GPIO pin 36.
This pin functions as standalone GPIO pin 37.
This pin functions as standalone GPIO pin 38.
This pin functions as standalone GPIO pin 39.
This pin functions as standalone GPIO pin 40.
This pin functions as standalone GPIO pin 41.
This pin functions as standalone GPIO pin 42.
This pin functions as standalone GPIO pin 43.
This pin functions as standalone GPIO pin 53.
This pin functions as standalone GPIO pin 54.
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
IPD
DVDD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-26. Reserved Terminal Functions
SIGNAL
ZWT
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZDU
NO.
NAME
NO.
RESERVED
RSV1
RSV2
RSV3
RSV4
RSV5
E5
K5
D4
L4
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
L5
M4
L15
R13
P19
W16
A O
A O
Reserved. This pin must be tied directly to VSS for normal device
operation.
RSV6
N19
V22
A I
RSV7
RSV8
RSV9
RSV10
P19
P18
N18
N17
V21
U22
T21
T22
A O
A O
A O
A O
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. This pin must be tied directly to VSS for normal device
operation.
RSV11
RSV12
RSV13
RSV14
RSV15
RSV16
RSV17
RSV18
RSV19
P16
P17
N15
P15
N16
T3
U20
V20
T20
T19
U21
W3
Reserved. This pin must be tied directly to VSS for normal device
operation.
Reserved. This pin must be tied directly to VSS for normal device
operation.
Reserved. This pin must be tied directly to VSS for normal device
operation.
Reserved. This pin must be tied directly to VSS for normal device
operation.
IPD
DVDD33
Reserved. For proper C6421 device operation, this pin must be pulled
down via an external resistor and tied to VSS.
I
IPD
DVDD33
E10
E11
E12
D12
D13
D14
I/O/Z
I/O/Z
I/O/Z
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
IPD
DVDD33
IPD
DVDD33
RSV20
RSV21
T14
T16
Y15
Y18
I/O/Z
I/O/Z
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. For proper C6421 device operation, this pin must be pulled
down via an external 1-kΩ resistor.
RSV22
RSV23
U14
U16
AA15
AA18
I/O/Z
I/O/Z
Reserved. For proper C6421 device operation, this pin must be pulled
down via an external 1-kΩ resistor.
RSV24
RSV25
RSV26
RSV27
RSV28
RSV29
RSV30
RSV31
RSV32
RSV33
W14
V14
W15
V15
U15
W16
V16
T17
V17
U17
AA16
Y16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
AB16
AA17
Y17
AB17
AB18
AA19
Y19
AB19
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.2.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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Table 2-26. Reserved Terminal Functions (continued)
SIGNAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
RSV34
RSV35
RSV36
RSV37
RSV38
RSV39
T18
W17
U18
V18
U19
T19
AA20
Y20
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
Reserved. (Leave unconnected, do not connect to power or ground)
AB20
Y21
AA21
Y22
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Table 2-27. Supply Terminal Functions
SIGNAL
ZWT
TYPE(1) OTHER
SUPPLY VOLTAGE PINS
DESCRIPTION
ZDU
NO.
NAME
NO.
A1
A2
A2
A21
B1
A18
E6
D6
E8
D8
F5
D10
D16
D18
E3
F7
F9
F11
F13
G6
E5
E7
G8
E9
G10
G12
G14
H5
E11
E13
E15
E17
E19
F4
H18
J1
J6
F18
G5
J14
J16
K15
K17
L6
3.3 V I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDD33
S
G19
H4
H18
J5
M5
M15
N6
J19
K4
K18
L1
P1
L5
L21
M18
M20
N5
N19
P4
P18
P20
P22
R5
T4
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-27. Supply Terminal Functions (continued)
SIGNAL
TYPE(1) OTHER
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
L14
P5
U5
V1
P7
V4
P9
V6
P11
P13
R4
V8
V10
V12
V14
V16
V18
W7
R6
R8
1.8 V DDR2 I/O supply voltage
(see the Power-Supply Decoupling section of this data manual)
DVDDR2
S
R10
R12
R14
R16
T5
W9
W11
W17
W19
AA1
AB21
AB22
J10
J11
J12
J13
K9
V1
W18
W19
H7
H9
H11
H13
J8
J10
J12
K7
K14
L9
L13
L14
M9
K9
K11
K13
L8
1.20 V supply voltage (-600, -500, -400 devices)
1.05 V core supply voltage (-400 devices)
CVDD
M10
M14
N9
S
(see the Power-Supply Decoupling section of this data manual)
L10
L12
M7
N14
P10
P11
P12
P13
M9
M11
M13
N8
N10
N12
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Table 2-28. Ground Terminal Functions
SIGNAL
ZWT
TYPE(1) OTHER
DESCRIPTION
ZDU
NO.
NAME
NO.
GROUND PINS
A19
B1
A1
A22
B22
D5
B19
E7
E9
D7
E13
F4
D9
D11
D15
D17
E4
F6
F8
F10
F12
F14
G5
E6
E8
E10
E12
E14
E16
E18
F5
G7
G9
G11
G13
G18
H6
F19
G4
VSS
H8
GND
Ground pins
H10
H12
H14
H19
J5
G18
H5
H19
J4
J9
J7
J14
J18
K5
J9
J11
J13
J15
J17
J18
K1
K10
K11
K12
K13
L10
L11
L12
L18
L22
M1
K6
K8
K10
K12
K14
K16
M5
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Table 2-28. Ground Terminal Functions (continued)
SIGNAL
TYPE(1) OTHER
DESCRIPTION
ZWT
NO.
ZDU
NO.
NAME
L7
L9
M11
M12
M13
M19
N4
L11
L13
L17
L19
M6
N10
N11
N12
N13
N18
P5
M8
M10
M12
M14
M16
M17
M18
M19
N5
P9
P14
P21
R4
R18
R19
R20
R21
R22
T5
N7
N9
N11
N13
N14
P6
VSS
T18
U4
GND
Ground pins
P8
P10
P12
P14
R1
U18
U19
V5
V7
R5
V9
R7
V11
V13
V15
V17
V19
W1
R9
R11
R15
R17
R18
R19
V19
W1
W2
W6
W8
W10
W20
W21
W22
AA22
AB1
AB2
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2.7 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMX320C6421AZWTA). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default
[600-MHz]).
Figure 2-14 provides a legend for reading the complete device name for any TMS320C642x DSP platform
member.
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TMX 320 C6421
A
ZWT
(
)
( )
DEVICE SPEED RANGE
400 MHz
PREFIX
TMX = Experimental device
TMS = Qualified device
500 MHz
600 MHz
TEMPERATURE RANGE (JUNCTION)
Blank = 0°C to 90°C, Commercial Temperature
A
= −40°C to 125°C, Extended Temperature
(A)
PACKAGE TYPE
ZWT = 361-pin plastic BGA, with Pb-Free soldered balls
ZDU = 376-pin plastic BGA, with Pb-Free soldered balls [Green]
DEVICE FAMILY
320 = TMS320t DSP family
SILICON REVISION
Blank = Revision 1.0
A
= Revision 1.1
DEVICE
C64x+tDSP:
C6424
C6421
A. BGA = Ball Grid Array
B. For “TMX” initial devices, the device number is C6424. The temperature range is A (extended temperature), and the device speed is left blank.
Figure 2-14. Device Nomenclature(B)
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise
Noted)(1)
Supply voltage ranges:
(2)
Core (CVDD
)
1.05-V operation
1.20-V operation
–0.5 V to 1.5 V
–0.5 V to 1.5 V
–0.5 V to 4.2 V
–0.5 to 2.5 V
(2)
I/O, 3.3V (DVDD33
)
(2)
I/O, 1.8V (DVDDR2, DDR_VDDDLL, PLLPWR18, MXVDD
)
Input voltage ranges:
Output voltage ranges:
VI I/O, 3.3-V pins
VI I/O, 1.8 V
VO I/O, 3.3-V pins
VO I/O, 1.8 V
Commercial
Extended
–0.5 V to 4.2 V
–0.5 V to 2.5 V
–0.5 V to 4.2 V
–0.5 V to 2.5 V
0°C to 90°C
Operating Junction temperature
ranges, TJ:
–40°C to 125°C
–65°C to 150°C
Storage temperature range, Tstg
(default)
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
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5.2 Recommended Operating Conditions(1)
MIN
1.14
NOM
1.2
MAX
1.26
UNIT
V
(-600, -500,
-400 devices)
(2)
CVDD
Supply voltage, Core (CVDD)
(-400 devices)
1.0
1.05
3.3
1.1
V
V
Supply voltage, I/O, 3.3V (DVDD33
)
3.14
3.46
DVDD
Supply voltage, I/O, 1.8V (DVDDR2, DDR_VDDDLL, PLLPWR18
,
1.71
1.8
1.89
V
(3)
MXVDD
)
(4)
VSS
Supply ground (VSS, DDR_VSSDLL, MXVSS
DDR2 reference voltage(5)
)
0
0
0.5DVDDR2
VSS
0
V
V
V
V
V
DDR_VREF
DDR_ZP
DDR_ZN
0.49DVDDR2
0.51DVDDR2
DDR2 impedance control, connected via 200 Ω resistor to VSS
DDR2 impedance control, connected via 200 Ω resistor to DVDDR2
High-level input voltage, 3.3V (except I2C pins)
High-level input voltage, I2C
DVDDR2
2
VIH
VIL
TJ
0.7DVDD33
Low-level input voltage, 3.3V (except I2C pins)
Low-level input voltage, I2C
0.8
0.3DVDD33
90
V
V
0
0
Commercial
Operating Junction temperature(6)(7)
Extended
°C
–40
0
125
°C
Commercial
Operating Ambient Temperature(7)
Extended
70
°C
TA
-40
85
°C
(-600 devices)
600
MHz
MHz
MHz
FSYSCLK1
DSP Operating Frequency (SYSCLK1)
(-500 devices)
(-400 devices)
500
400
(1) For -400 speed devices, either a 1.05-V or a 1.2-V core supply voltage can be used. The actual voltage must be determined at device
power-up, and not be changed dynamically during run-time.
(2) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future versions of TI SOC
devices.
(3) Oscillator 1.8 V power supply (MXVDD) can be connected to the same 1.8 V power supply as DVDDR2
(4) Oscillator ground (MXVSS) must be kept separate from other grounds and connected directly to the crystal load capacitor ground.
(5) DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDDR2
.
.
(6) In the absence of a heat sink or direct thermal attachment on the top of the device, use the following formula to determine the device
junction temperature: TJ = TC + (Power x PsiJT). Power and TC can be measured by the user. Section 7.1, Thermal Data for ZWT and
Section 7.1.1, Thermal Data for ZDU provide the junction-to-package top (PSIJT) value based on airflow in the system. In the presence
of a heat sink or direct thermal attachment on the top of the device, additional calculations and considerations must be taken into
account. For more detailed information on thermal considerations, measurements, and calculations, see the TMS320C642x Thermal
Considerations Application Report (literuature number SPRAATBD).
(7) Applications must meet both the Operating Junction Temperature and Operating Ambient Temperature requirements. For more detailed
information on thermal considerations, measurements, and calculations, see the TMS320C642x Thermal Considerations Application
Report (literature number SPRAATBD).
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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
High-level output voltage (3.3V I/O except
I2C pins)
VOH
DVDD33 = MIN, IOH = MAX
2.4
V
Low-level output voltage (3.3V I/O except
I2C pins)
DVDD33 = MIN, IOL = MAX
0.4
0.4
V
V
VOL
Low-level output voltage (3.3V I/O I2C pins) IO = 3 mA
0
VI = VSS to DVDD33 without internal
resistor
±10
µA
Input current [DC] (except I2C capable
pins)
VI = VSS to DVDD33 with internal pullup
resistor
50
100
250
µA
(3)
II(2)
VI = VSS to DVDD33 with opposing
internal pulldown resistor
–250
–100
–50
±10
8
µA
µA
(3)
Input current [DC] (I2C)
VI = VSS to DVDD33
CLK_OUT0/PWM2/GPIO[84] and
VLYNQ_CLOCK/GP[57]
mA
IOH
High-level output current [DC]
DDR2
–13.4 mA
All other peripherals
4
8
mA
mA
CLK_OUT0/PWM2/GPIO[84] and
VLYNQ_CLOCK/GP[57]
IOL
Low-level output current [DC]
I/O Off-state output current
DDR2
13.4 mA
All other peripherals
4
mA
µA
VO = DVDD33 or VSS; internal pull
disabled
±20
(4)
IOZ
VO = DVDD33 or VSS; internal pull
enabled
±100
µA
CVDD = 1.2 V, DSP clock = 600 MHz
CVDD = 1.2 V, DSP clock = 500 MHz
CVDD = 1.2 V, DSP clock = 400 MHz
CVDD = 1.05 V, DSP clock = 400 MHz
DVDD = 3.3 V, DSP clock = 600 MHz
DVDD = 3.3 V, DSP clock = 500 MHz
DVDD = 3.3 V, DSP clock = 400 MHz
DVDD = 1.8 V, DSP clock = 600 MHz
DVDD = 1.8 V, DSP clock = 500 MHz
DVDD = 1.8 V, DSP clock = 400 MHz
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
pF
ICDD
Core (CVDD, VDDA_1P1V) supply current(5)
IDDD
3.3V I/O (DVDD33) supply current(5)
1.8V I/O (DVDDR2, DDR_VDDDLL,
PLLVPRW18, VDDA_1P8V, MXVDD) supply
current(5)
IDDD
CI
Input capacitance
Output capacitance
5
5
Co
pF
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(5) Measured under the following conditions: 60% DSP CPU utilization; DDR2 Memory Controller at 50% utilization (135 MHz), 50% writes,
32 bits, 50% bit switching; 2-MHz McBSP at 100% utilization; Timer0 at 100% utilization. At room temperature (25 °C) for typical
process devices. The actual current draw varies across manufacturing processes and is highly application-dependent. For more details
on core and I/O activity, as well as information relevant to board power supply design, see the TMS320C642x Power Consumption
Summary Application Report (literature number TBD).
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7 Mechanical Data
The following table(s) show the thermal resistance characteristics for the PBGA–ZWT and ZDU
mechanical package(s).
TBD see Power Application Report
7.1 Thermal Data for ZWT
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZWT]
NO.
1
°C/W(1)
5.4
AIR FLOW (m/s)(2)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
N/A
N/A
0.00
1.0
2
16.0
26.6
21.9
20.4
0.0
3
4
RΘJA
PsiJT
PsiJB
Junction-to-free air
Junction-to-package top
Junction-to-board
5
2.00
0.00
1.0
7
8
0.1
9
0.2
2.00
0.00
1.0
11
12
13
15.9
15.8
15.3
2.00
(1) The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC
defined 1S2P system and will change based on environment as well as application.
For more information, see these three EIA/JEDEC standards:
•
•
EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
•
.
(2) m/s = meters per second
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7.1.1 Thermal Data for ZDU
Table 7-2. Thermal Resistance Characteristics (PBGA Package) [ZDU]
NO.
1
°C/W(1)
7.7
AIR FLOW (m/s)(2)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
N/A
N/A
0.00
1.0
2
10.5
19.7
15.5
14.3
4.9
3
4
RΘJA
PsiJT
PsiJB
Junction-to-free air
Junction-to-package top
Junction-to-board
5
2.00
0.00
1.0
7
8
5.1
9
5.2
2.00
0.00
1.0
11
12
13
10.4
9.8
9.6
2.00
(1) The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC
defined 1S2P system and will change based on environment as well as application.
For more information, see these three EIA/JEDEC standards:
•
•
•
EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
(2) m/s = meters per second
7.1.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
56
Mechanical Data
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相关型号：
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