TMS320C6474FGUN [TI]
TMS320C6474 Multicore Digital Signal Processor; TMS320C6474多核数字信号处理器型号: | TMS320C6474FGUN |
厂家: | TEXAS INSTRUMENTS |
描述: | TMS320C6474 Multicore Digital Signal Processor |
文件: | 总214页 (文件大小:1798K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMS320C6474
www.ti.com
SPRS552H–OCTOBER 2008–REVISED APRIL 2011
TMS320C6474 Multicore Digital Signal Processor
1 Features
12
•
•
1.2-GHz Device: -40°C to 95°C(1)
1-GHz Device: -40°C to 100°C
• Key Features
– High-Performance Multicore DSP (C6474)
• 3 TMS320C64x+™ DSP Cores
– Dedicated SPLOOP Instructions
– Compact Instructions (16-Bit)
– Exception Handling
– Instruction Cycle Time: 0.83 ns (1.2-GHz
Device); 1 ns (1-GHz Device); 1.18 ns
(850-MHz Device)
– Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz
Device); 1 GHz (1-GHz Device); 850 MHz
(850-MHz Device)
– Commercial Temperature and Extended
Temperature
– 3 TMS320C64x+™ DSP Cores; Six RSAs for
CDMA Processing (2 per core)
– Enhanced VCP2/TCP2
– Frame Synchronization Interface
– 16-/32-Bit DDR2-667 Memory Controller
– EDMA3 Controller
• TMS320C64x+ Megamodule L1 Memory
Architecture
– 256 K-Bit (32 K-Byte) L1P Program Cache
[Direct Mapped]
– 256 K-Bit (32 K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 512 K-Bit (64 K-Byte) L3 ROM
• Enhanced VCP2
– Supports Over 694 7.95-Kbps AMR
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Antenna Interface
– Two 1x Serial RapidIO® Links, v1.2
– Supports up to Eight 2-Mbps 3 GPP
(6 Iterations)
• Endianness: Little Endian, Big Endian
• Frame Synchronization Interface
Compliant
– One 1.8-V Inter-Integrated Circuit (I2C) Bus
– Two 1.8-V McBSPs
– Time Alignment Between Internal
– 1000 Mbps Ethernet MAC (EMAC)
– Six 64-Bit General-Purpose Timers
– 16 General-Purpose I/O (GPIO) Pins
– Internal Semaphore Module
Subsystems, External Devices/System
– OBSAI RP1 Compliant for Frame Burst Data
– Alternate Interfaces for non-RP1 and
non-UMTS Systems
– System PLL and PLL Controller/DDR PLL
and PLL Controller, Dedicated to DDR2
Memory Controller
• 16-/32-Bit DDR2-667 Memory Controller
• EDMA3 Controller (64 Independent Channels)
• Antenna Interface
• High-Performance Multicore DSP (C6474)
– Instruction Cycle Time:
– 6 Configurable Links (Full Duplex)
– Supports OBSAI RP3 Protocol, v1.0:
768-Mbps, 1.536-, 3.072-Gbps Link Rates
– Supports CPRI Protocol V2.0: 614.4-Mbps,
•
•
•
1.2-GHz Device: 0.83-ns
1-GHz Device: 1-ns
850-MHz Device: 1.18 ns
1.2288-, 2.4576-Gbps Link Rates
– Clock Rate:
– Clock Input Independent or Shared with CPU
(Selectable at Boot-Time)
•
•
•
1.2-GHz Device: 1 GHz to 1.2 GHz
1-GHz Device: 1 GHz
850-MHz Device: 850 MHz
• Two 1x Serial RapidIO® Links, v1.2 Compliant
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing and DirectIO Support
– Error Management Extensions and
Congestion Control
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• Two 1.8-V McBSPs
– Eight 32-Bit Instructions/Cycle
– Commercial Temperature:
•
•
1.2-GHz Device: 0°C to 95°C
850-MHZ and 1-GHz Device: 0°C to 100°C
– Extended Temperature:
(1)
Note: Advance Information is presented in this document for
the C6474 1.2-GHz extended temperature device.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
TMS320C6474
SPRS552H–OCTOBER 2008–REVISED APRIL 2011
www.ti.com
• 1000 Mbps Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– 32 General Purpose Semaphore Resources
• System PLL and PLL Controller
– Supports SGMII, v1.8 Compliant
– 8 Independent Transmit (TX) and 8
• DDR PLL and PLL Controller, Dedicated to
DDR2 Memory Controller
Independent Receive (RX) Channels
• IEEE-1149.1 and IEEE-1149.6 (JTAG™)
Boundary-Scan-Compatible
• 561-Pin Ball Grid Array (BGA) Packages (CUN,
GUN, or ZUN Suffix), 0.8-mm Ball Pitch
• 0.065-μm/7-Level Cu Metal Process (CMOS)
• SmartReflex™ Class 0 - 0.9-V to 1.2-V Adaptive
• Six 64-Bit General-Purpose Timers
– Configurable up to Twelve 32-Bit Timers
– Configurable in a Watchdog Timer mode
• 16 General-Purpose I/O (GPIO) Pins
• Internal Semaphore Module
Core Voltage
• 1.8-V, 1.1-V I/Os
– Software Method to Control Access to
Shared Resources
1.1 CUN/GUN/ZUN BGA Package (Bottom View)
The devices are designed for a package temperature range of 0°C to 100°C (commercial temperature
range; 1-GHz device), -40°C to 100°C (extended temperature range; 1-GHz device), 0°C to 95°C
(commercial temperature range; 850-MHz and 1.2-GHz device), and -40°C to 95°C (extended temperature
range; 1.2-GHz device). A heatsink is required so that this range is not exceeded.
NOTE
Advance Information is presented in this document for the C6474 1.2-GHz extended
temperature device.
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27
2
4
6
8 10 12 14 16 18 20 22 24 26
Figure 1-1. CUN/GUN/ZUN 561-Pin BGA Package (Bottom View)
2
Features
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1.2 Description
The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore
DSP generation in the TMS320C6000™ DSP platform.
The C6474 device is based on the third-generation high-performance, advanced VelociTI™
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).
The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™
DSP platform.
1.2.1 Core Processor
Based on 65-nm process technology and 3.6 GHz of total raw DSP processing power with performance of
up to 28,800 million instructions per second (MIPS) [or 28,800 16-bit MMACs per cycle], the C6474 device
offers cost-effective solutions to high-performance DSP programming challenges with three independent
DSP subsystems. The DSP possesses the operational flexibility of high-speed controllers and numerical
capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these functional units are multipliers or .M units. Each C64x+ .M unit doubles the
multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs)
every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At
a1.2-GHz rate, this means 9600 16-bit MMACs can occur every microsecond. Moreover, each multiplier
on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.
The C6474 DSP integrates a large amount of on-chip memory organized as a three-level memory system.
The level-1 data memories on the device are 32 KB each. This memory can be configured as mapped
RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a
direct-mapped cache where as L1 data (L1D) is a two-way set associative cache. The level-3 (L3) ROM is
64 KB in the device. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an
internal DMA (IDMA) controller, a system component with reset/boot control, and a free-running 32-bit
timer for time stamp.
The C64x+ DSP core has a complete set of development tools which includes: a new C compiler, an
assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for
visibility into source code execution.
The DMA switch fabric provides enhanced on-chip connectivity between the DSP cores and the
peripherals and accelerators.
1.2.2 Peripherals
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs) each at 100 Mbps; six 64-bit general-purpose timers (also configurable as twelve 32-bit
timers); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation
modes; a 1000-Mbps Ethernet media access controller (EMAC), which provides an efficient interface
between the C6474 DSP core processor and the network; a management data input/output (MDIO)
module (also part of EMAC), which controls PHY configuration and status monitoring; a frame
synchronization (FSYNC) module, which synchronizes DMA transactions; a semaphore hardware block
(Semaphore), which allows access to shared resources with unique interrupts to each of the cores to
identify when that core has acquired the resource; and a 16-/32-bit DDR2 SDRAM interface.
The I2C port allows the DSP to easily control peripheral devices and communicate with a host processor.
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The device includes two Serial RapidIO® (SRIO) with link rates of 1.25 Gbps, 2.5 Gbps or 3.125 Gbps.
This high-bandwidth peripheral is used for point-to-point inter-device communication and may connect the
C6474 device to other DSPs, ASICs, or switches on the same board or across the backplane. This
dramatically improves system performance and reduces system cost for applications that include multiple
DSPs on a board such as video and telecom infrastructures and medical/imaging. The SRIO also provides
alarm, interrupt, and messaging events.
The device includes the SerDes-based antenna interface (AIF) capable of up to 3.072 Gbps operation per
link. The AIF comprises six high-speed serial links, compliant to OBSAI RP3 and CPRI standards. The
antenna interface is used to connect the backplane for antenna data transmission and reception. Each link
of the AIF includes a differential receive and transmit signal pair.
1.2.3 Accelerators
The device has two high-performance embedded coprocessors [enhanced Viterbi Decoder Coprocessor
(VCP2) and enhanced turbo decoder coprocessor (TCP2)] that significantly speed up channel-decoding
operations on-chip. The VCP2 operating at CPU clock divided-by-3 can decode over 694 7.95-Kbps
adaptive multi-rate (AMR) [K=9, R=1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7,
8, and 9, rates R = 3/4, 1/2, 1/3, and 1/5, and flexible polynomials, while generating hard decisions or soft
decisions. The TCP2 operating at CPU clock divided-by-3 can decode up to fifty 384-Kbps or eight
2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map
algorithm and is designed to support all polynomials and rates required by third-generation partnership
projects (3 GPP and 3 GPP2), with fully programmable frame length and turbo interleaver. Decoding
parameters such as the number of iterations and stopping criteria are also programmable.
Communications between the VCP2/TCP2 and the CPU are carried out through the EDMA3 controller.
4
Features
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1.3 C6474 Functional Block Diagram
Figure 1-2 shows the functional block diagram of the C6474 device.
DSP Subsystem 2
DSP Subsystem 1
32
DDR2 Memory
DSP Subsystem 0
Controller
32K Bytes
L1P SRAM/Cache
Direct-Mapped
PLL2
C64x+ Megamodule
L1P Memory Controller (Memory Protect/Bandwidth Mgmt)
2
Serial RapidIO
(2x)
C64x+ DSP Core
Instruction Fetch
Control Registers
TCP2
VCP2
16-/32-bit
Instruction Dispatch
SPLOOP Buffer
Instruction Decode
In-Circuit Emulation
McBSP0
McBSP1
A Register File
B Register File
A31 - A16
A15 - A0
B31 - B16
B15 - B0
EMAC
.M1
.M2
10/100/1000
.L1
.S1
xx
xx
.D1
.D2
xx
xx
.S2
.L2
SGMII
MDIO
L1 Data Memory Controller (Memory Protect/Bandwidth Mgmt)
I2C
16
GPIO16
FSYNC
32K Bytes Total
L1D SRAM/Cache 2-Way
Set Associative
Semaphore
Antenna
Interface
EDMA 3.0
PLL1 and
PLL1 Controller
Power-Down and Device
Configuration Logic
L3 ROM
Timer [0-5]
Boot Configuration
Figure 1-2. Functional Block Diagram
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1
Features ................................................... 1
5.6 Megamodule Resets ................................ 63
5.7 Megamodule Revision .............................. 63
1.1
CUN/GUN/ZUN BGA Package (Bottom View) ....... 2
1.2 Description ........................................... 3
1.3 C6474 Functional Block Diagram .................... 5
5.8
C64X+ Megamodule Register Description(s) ....... 64
6
7
Device Operating Conditions ....................... 72
6.1
Absolute Maximum Ratings Over Operating Case
Revision History .............................................. 7
2
Temperature Range (Unless Otherwise Noted) .... 72
Device Overview ........................................ 8
2.1 Device Characteristics ............................... 8
2.2 CPU (DSP Core) Description ........................ 9
2.3 Memory Map Summary ............................. 12
2.4 Boot Sequence ..................................... 15
2.5 Pin Assignments .................................... 17
2.6 Signal Groups Description .......................... 21
2.7 Terminal Functions ................................. 26
2.8 Development and Device Support .................. 41
6.2 Recommended Operating Conditions .............. 73
6.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 74
Peripheral Information and Electrical
Specifications .......................................... 75
7.1 Parameter Information .............................. 75
7.2
Recommended Clock and Control Signal Transition
Behavior ............................................ 76
7.3 Power Supplies ..................................... 76
7.4 Peripheral IDs (PIDs) ............................... 79
2.9 Documentation Support ............................ 42
2.10 Community Resources ............................. 44
Device Configuration ................................. 45
7.5
Enhanced Direct Memory Access (EDMA3)
3
Controller ........................................... 80
7.6 Interrupts .......................................... 104
7.7 Reset Controller ................................... 112
7.8 PLL1 and PLL1 Controller ......................... 117
7.9 PLL2 and PLL2 Controller ......................... 130
7.10 DDR2 Memory Controller ......................... 132
7.11 I2C Peripheral ..................................... 135
7.12 Multichannel Buffered Serial Port (McBSP) ....... 140
7.13 Ethernet MAC (EMAC) ............................ 149
7.14 Management Data Input/Output (MDIO) .......... 157
7.15 Timers ............................................. 159
7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)
..................................................... 168
7.17 Enhanced Turbo Decoder Coprocessor (TCP2)
..................................................... 170
7.18 Serial RapidIO (SRIO) Port ....................... 172
7.19 General Purpose Input/Output (GPIO) ............ 184
7.20 Emulation Features and Capability ............... 185
7.21 Semaphore ........................................ 189
7.22 Antenna Interface Subsystem ..................... 192
7.23 Frame Synchronization ............................ 204
Mechanical Data ...................................... 208
3.1 Device Configuration at Device Reset .............. 45
3.2
Peripheral Selection After Device Reset ........... 45
3.3 Device State Control Registers ..................... 46
3.4 Device Status Register Descriptions ............... 47
3.5
Inter-DSP Interrupt Registers (IPCGR0-IPCGR2
and IPCAR0-IPCAR2) .............................. 49
3.6
JTAG ID (JTAGID) Register Description ........... 50
3.7 Debugging Considerations ......................... 50
4
5
System Interconnect .................................. 51
4.1
Internal Buses, Switch Fabrics, and
Bridges/Gaskets .................................... 51
4.2 Data Switch Fabric Connections ................... 52
4.3 Configuration Switch Fabric ........................ 55
4.4 Priority Allocation ................................... 57
C64x+ Megamodule ................................... 58
5.1 Megamodule Diagram .............................. 58
5.2 Memory Architecture ............................... 59
5.3 Memory Protection ................................. 61
5.4 Bandwidth Management ............................ 62
5.5 Power-Down Control ............................... 63
8
8.1 Thermal Data ...................................... 208
8.2 Packaging Information ............................ 208
6
Contents
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the technical changes made to the data manual in this
revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6474 device,
have been incorporated.
C6474 Revision History
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 7.13.2
EMAC Peripheral Register Descriptions:
Corrected starting address for Table 7-57, EMAC Descriptor Memory
Modified Table 7-59, EMAC Interrupt Control (EMIC) Registers
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2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the C6474 DSP. The tables show significant features of the C6474
device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.
Table 2-1. Characteristics of the C6474 Processor
HARDWARE FEATURES
C6474
Peripherals
DDR2 Memory Controller (32-bit bus width) [1.8 V I/O]
(clock memory = DDRREFCLK(N|P)
1
Not all peripherals pins
are available at the same
time.
(For more detail, see
Section 3, Device
Configuration)
EDMA3 (64 independent channels [CPU/3 clock rate]
High-speed 1x Serial RapidIO Port (2 lanes)
I2C
1
1
1
McBSPs
2
(internal or external clock source up to 100 Mbps)
1000 Ethernet MAC (EMAC)
Management Data Input/Output (MDIO)
Antenna Interface (AIF)
1
1
1
1
Frame Synchronization (FSYNC)
64-bit Timers (Configurable)
(internal clock source CPU/6 clock frequency)
6 64-bit or 12 32-bit
SYSCLKOUT
1
General Purpose Input/Output Port (GPIO)
VCP2 (clock source = CPU/3 clock frequency)
TCP2 (clock source = CPU/3 clock frequency)
Size (Bytes)
16
Decoder Coprocessors
On-Chip Memory
1
1
3200 KB
Organization
32KB L1P Program Cache (SRAM/Cache)
32KB L1D Data Cache (SRAM/Cache)
32KB Data Memory Controller
3072KB Total L2 Unified Memory SRAM/Cache
64KB L3 ROM
CPU Megamodule
Revision ID
Revision ID Register
(MM_REVID. [15:0]) 0x0181 2000)
0x0
JTAG Device_ID
Frequency
Cycle Time
Voltage
JTAG Register (address location: 0x0288 0814)
For details, see Section 3.6
850 - 1200 (850 MHz to 1.2 GHz)
1.18 ns - 0.83 ns (850 MHz to 1.2 GHz CPU)
0.9-V to 1.2-V SmartReflex(1) 1.1 V
1.8 V, 1.1 V
MHz
ns
Core (V)
I/O (V)
PLL1 and PLL1 Controller CLKIN1 Frequency Multiplier
Options
Bypass (x1), (x4 to x32)
PLL2
DDR Clock
23 X 23 mm
μm
X10
561-Pin Flip-Chip with BGA CUN/GUN/ZUN
0.065 μm
BGA Package
Process Technology
(1) A heatsink and implementation of the SmartReflex solution is required for proper device operation. For more details on SmartReflex, see
Section 7.3.4.
8
Device Overview
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Table 2-1. Characteristics of the C6474 Processor (continued)
HARDWARE FEATURES
C6474
Product Status(1)
Product Preview (PP), Advance Information (AI), or
Production Data (PD)
PD
Device Part Numbers
(For more details on C64x+ DSP part numbering, see
Figure 2-11)
TMS320C6474CUN/GUN/ZUN
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Note: Advance Information
is presented in this document for the C6474 1.2-GHz extended temperature device.
2.2 CPU (DSP Core) Description
The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data
paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 (thirty-two)
32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, 32-bit data, 40-bit data, and
64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register
pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next
upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, two 16 x
16 bit multiplies, two 16 x 32 bit multiplies, four 8 x 8 bit multiplies, four 8 x 8 multiplies with add
operations and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There
is also support for Galois filed multiplication for 8-bit and 32-bit data. Many communications algorithms
such FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes
four 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex
multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and
16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for
audio and other high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or arithmetic logic unit now incorporates the ability to do parallel add/subtract operations on a pair
of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64X+ core, they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - a small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size of the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
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•
•
•
•
Instruction Set Enhancements - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exception Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for real-time operating system (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU that is not sensitive to system stalls.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871)
TMS320C64X to TMS320C64x+ CPU Migration Guide (literature number SPRAA84)
10
Device Overview
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Even
Odd
register
src1
src2
register
file A
.L1
fileA
(A0, A2,
(A1, A3,
A4...A30)
A5...A31)
odd dst
even dst
long src
(D)
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
Datapath A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
.D1
.D2
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
DA1
DA2
2x
1x
Even
register
file B
Odd
register
src2
(B0, B2,
file B
src1
dst
B4...B30)
(B1, B3,
B5...B31)
32 LSB
32 MSB
LD2a
LD2b
src2
(C)
.M2
.S2
src1
dst2
dst1
32
32
(B)
(A)
src2
src1
odd dst
even dst
long src
(D)
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
odd dst
src2
.L2
src1
Control Register
A. On .M unit, dst2 is 32 MB.
B. On .M unit, dst1 is 32 LSB.
C. On 64x+ CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+TM CPU (DSP Core) Data Path
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2.3 Memory Map Summary
Table 2-2 shows the memory map address of the C6474 device. For more information about the registers
in these address ranges, click on the links in the table. The external memory configuration register
address ranges in the C6474 device begin at the hex address location 0x7000 for DDR2 Memory
Controller.
Table 2-2. Memory Map Summary
HEX ADDRESS RANGE
START
MEMORY BLOCK DESCRIPTION
SIZE
END
C64x+ MEGAMODULE CORE 0 C64x+ MEGAMODULE CORE 1 C64x+ MEGAMODULE CORE 2
Internal RAM
0000 0000
0080 0000
0088 0000
009 00000
0098 0000
00A0 0000
00E0 0000
00E0 8000
00F0 0000
00F0 8000
0100 0000
01C0 0000
007F FFFF
0087 FFFF
008F FFFF
0097 FFFF
009F FFFF
00DF FFFF
00E0 7FFF
00EF FFFF
00F0 7FFF
00FF FFFF
01BF FFFF
027F FFFF
8M
512K
512K
512K
512K
4M
Reserved
L2 SRAM
Reserved
Reserved
Reserved
32K
L1P SRAM
1M - 32K
32K
Reserved
L1D SRAM
1M - 32K
4M
Reserved
C64x+ Megamodule Registers
12.5M
Reserved
Control Registers on CFG SCR
0280 0000
0280 0400
0288 0000
0288 0100
0288 0200
0288 0300
0288 0400
0288 0404
0288 0408
0288 040C
0288 0800
0288 0900
0288 0904
0288 0908
0288 090C
0288 0940
0288 0944
0288 0948
0288 0C00
028C 0000
028C 0100
028D 0000
028D 0100
028E 0000
0290 0000
0290 0040
0291 0000
0291 0040
0292 0000
0292 0040
0293 0000
0293 0040
0294 0000
0294 0040
0280 03FF
0287 FFFF
0288 00FF
0288 01FF
0288 02FF
0288 03FF
0288 0403
0288 0407
0288 040B
0288 07FF
0288 0BFF
0288 0903
0288 0907
0288 090B
0288 093F
0288 0943
0288 0947
0288 094B
028B FFFF
028C 00FF
028C FFFF
208D 00FF
028D FFFF
028F FFFF
0290 003F
0290 FFFF
0291 003F
0291 FFFF
0292 003F
0292 FFFF
0293 003F
0293 FFFF
0294 003F
0294 FFFF
1K
511K
256
Frame Synchronization (FSYNC)
Reserved
Chip Interrupt Controller 0 (CIC0)
256
Chip Interrupt Controller 1 (CIC1)
256
Chip Interrupt Controller 2 (CIC2)
256
Chip Interrupt Controller 3 (CIC3)
4
DSP Trace Formatter 1 (DTF1)
4
DSP Trace Formatter 2 (DTF2)
DSP Trace Formatter 3 (DTF3)
Reserved
4
1K- 6
1K
CFGC
4B
IPCGR0
4B
IPCGR1
4B
IPCGR2
52B
Reserved
4B
IPCAR0
4B
IPCAR1
4B
IPCAR2
253K
256
Reserved
McBSP0
64K - 256
256
Reserved
McBSP1
64K - 256
128K
64
Reserved
Reserved
Timer Pin Manager (TPMGR)
Reserved
64K - 64
64
Timer0
64K - 64
64
Reserved
Timer1
64K - 64
64
Reserved
Timer2
64K - 64
64
Reserved
Timer3
64K - 64
Reserved
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HEX ADDRESS RANGE
START
MEMORY BLOCK DESCRIPTION
SIZE
END
C64x+ MEGAMODULE CORE 0 C64x+ MEGAMODULE CORE 1 C64x+ MEGAMODULE CORE 2
0295 0000
0295 0040
0296 0000
0296 0040
029A 0000
029A 0200
029C 0000
029C 0200
02A0 0000
02A0 8000
02A2 0000
02A2 8000
02A3 0000
02A3 8000
02A4 0000
02A4 8000
02A5 0000
02A8 0000
02A8 0100
02AC 0000
02AC 1000
02AC 4000
02AC 4100
02AD 0000
02AD 8000
02AE 0000
02AE 8000
02B0 0000
02B0 0100
02B0 2000
02B0 2400
02B0 4000
02B0 4080
02B4 0000
02B4 0800
02B8 0000
02B8 0100
02BA 0000
02BA 0100
02BC 0000
02C0 0000
02C0 0400
02C4 0000
02C4 0100
02C8 0000
02C8 0800
02C8 1000
02C8 1100
02C8 1800
02C8 1900
02C8 2000
02C8 4000
02D0 0000
02D2 1000
02D4 0000
02D8 0000
0295 003F
0295 FFFF
0296 003F
0296 FFFF
029A 01FF
029B FFFF
029C 01FF
029C 02FF
02A0 7FFF
02A1 FFFF
02A2 7FFF
02A2 FFFF
02A3 7FFF
02A3 FFFF
02A4 7FFF
02A4 FFFF
02A7 FFFF
02A8 00FF
02AB FFFF
02AC 0FFF
02AC 3FFF
02AC 40FF
02AC FFFF
02AD 7FFF
02AD FFFF
02AE 7FFF
02AF FFFF
02B0 00FF
02B0 1FFF
02B0 23FF
02B0 3FFF
02B0 407F
02B3 FFFF
02B4 07FF
02B7 FFFF
02B8 00FF
02B8 FFFF
02BA 00FF
02BB FFFF
02BF FFFF
02C0 03FF
02C3 FFFF
02C4 00FF
02C7 FFFF
02C8 07FF
02C8 0FFF
02C8 10FF
02C8 17FF
02C8 18FF
02C8 FFFF
02C8 3FFF
02CF FFFF
02D2 0FFF
02D3 FFFF
02D7 FFFF
02DB FFFF
64
64K - 64
64
Timer4
Reserved
Timer5
Reserved
256K - 64
512
PLL Controller 1 (Main)
Reserved
128K - 512
512
Reserved
256K - 512
32K
Reserved
EDMA3 Channel Controller (TPCC)
Reserved
96K
32K
EDMA3 Transfer Controller 0 (TPTC0)
EDMA3 Transfer Controller 1 (TPTC1)
EDMA3 Transfer Controller 2 (TPTC2)
EDMA3 Transfer Controller 3 (TPTC3)
EDMA3 Transfer Controller 4 (TPTC4)
EDMA3 Transfer Controller 5 (TPTC5)
Reserved
32K
32K
32K
32K
32K
192K
256
Reserved
256K - 256
4K
Reserved
Power/Sleep Controller (PSC)
Reserved
12K
256
Reserved
48K - 256
32K
Reserved
Embedded Trace Buffer 0 (ETB0)
Embedded Trace Buffer 1 (ETB1)
Embedded Trace Buffer 2 (ETB2)
Reserved
32K
32K
96K
256
GPIO
8K - 256
1K
Reserved
Reserved
7K
Reserved
128
I2C Data and Control
Reserved
256K - 128
2K
Semaphore
254K
256
Reserved
VCP2 Control
128K - 256
256
Reserved
TCP2 Control
128K - 256
256K
1K
Reserved
Antenna Interface Control
Reserved
255K
256
Reserved
SMGII Control
256K - 256
2K
Reserved
EMAC Control
2K
Reserved
256
EMAC Interrupt Controller
Reserved
2K - 256
256
MDIO
2K - 256
8K
Reserved
EMAC Descriptor Memory
Reserved
496K
132K
124K
256K
256K
RapidIO
Reserved
Reserved
Reserved
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HEX ADDRESS RANGE
MEMORY BLOCK DESCRIPTION
SIZE
START
END
C64x+ MEGAMODULE CORE 0 C64x+ MEGAMODULE CORE 1 C64x+ MEGAMODULE CORE 2
02DC 0000
02E0 0000
02E0 4000
02F0 0000
02F1 0000
02F2 0000
02F4 0000
02F6 0000
02DF FFFF
02E0 3FFF
02EF FFFF
02F0 FFFF
02F1 FFFF
02F3 FFFF
02F5 FFFF
02FF FFFF
256K
16K
Reserved
RapidIO Descriptor Memory
1M - 16K
64K
Reserved
Reserved
64K
Reserved
128K
128K
576K
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Global Ram
Reserved
0300 0000
0400 0000
03FF FFFF
0FFF FFFF
16M
192M
1000 0000
1080 0000
1088 0000
1090 0000
1098 0000
10A0 0000
10E0 0000
10E0 8000
10F0 0000
10F0 8000
1100 0000
1180 0000
1188 0000
1190 0000
1198 0000
11A0 0000
11E0 0000
11E0 8000
11F0 0000
11F0 8000
1200 0000
1280 0000
1288 0000
1290 0000
1298 0000
12A0 0000
12E0 0000
12E0 8000
12F0 0000
12F0 8000
1300 0000
107F FFFF
1087 FFFF
108F FFFF
1097 FFFF
109F FFFF
10DF FFFF
10E0 7FFF
10EF FFFF
10F0 7FFF
10FF FFFF
117F FFFF
1187 FFFF
118F FFFF
1197 FFFF
119F FFFF
11DF FFFF
11E0 7FFF
11EF FFFF
11F0 7FFF
11FF FFFF
127F FFFF
1287 FFFF
128F FFFF
1297 FFFF
129F FFFF
12DF FFFF
12E0 7FFF
12EF FFFF
12F0 7FFF
12FF FFFF
1FFF FFFF
8M
512K
512K
512K
512K
4M
C64x+ Megamodule Core 0 L2 RAM
Reserved
Reserved
Reserved
32K
C64x+ Megamodule Core 0 L1P SRAM
Reserved
1M - 32K
32K
C64x+ Megamodule Core 0 L1D SRAM
Reserved
1M - 32K
8M
Reserved
512K
512K
512K
512K
4M
C64x+ Megamodule Core 1 L2 SRAM
Reserved
Reserved
Reserved
32K
C64x+ Megamodule Core 1 L1P SRAM
Reserved
1M - 32K
32K
C64x+ Megamodule Core 1 L1D SRAM
Reserved
1M - 32K
8M
Reserved
512K
512K
512K
512K
4M
C64x+ Megamodule Core 2 L2 SRAM
Reserved
Reserved
Reserved
32K
C64x+ Megamodule Core 2 L1P SRAM
1M - 32K
32K
Reserved
C64x+ Megamodule Core 2 L1D SRAM
1M - 32K
208M
Reserved
Reserved
Data Space on EDMA SCR
Reserved
2000 0000
3000 0000
3000 0100
3400 0000
3400 0100
3C00 0000
3C01 0000
4000 0000
5000 0000
5010 0000
5800 0000
5801 0000
2FFF FFFF
3000 00FF
33FF FFFF
3400 00FF
3BFF FFFF
3C00 FFFF
3FFF FFFF
4FFF FFFF
500F FFFF
57FF FFFF
5800 FFFF
5FFF FFFF
256M
256
McBSP0 Data
Reserved
64M - 256
256
McBSP1 Data
Reserved
128M - 256
64K
L3 ROM
64M - 64K
256M
Reserved
Reserved
1M
TCP2 Data
Reserved
127M
64K
VCP2 Data
Reserved
128M 64K
14
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HEX ADDRESS RANGE
START
MEMORY BLOCK DESCRIPTION
SIZE
END
C64x+ MEGAMODULE CORE 0 C64x+ MEGAMODULE CORE 1 C64x+ MEGAMODULE CORE 2
6000 0000
6040 0000
7000 0000
7000 0100
8000 0000
A000 0000
B000 0000
C000 0000
D000 0000
E000 0000
F000 0000
603F FFFF
6FFF FFFF
7000 00FF
7FFF FFFF
9FFF FFFF
AFFF FFFF
BFFF FFFF
CFFF FFFF
DFFF FFFF
EFFF FFFF
FFFF FFFF
4M
252M
256
Reserved
Reserved
DDR2 EMIF Configuration
Reserved
256M - 256
512M
256M
256m
256m
256m
256m
256m
DDR2 EMIF Data
AIF Data
Reserved
Reserved
Reserved
Reserved
Reserved
2.4 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data
sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is
started automatically after each power-on reset, warm reset, and system reset. A local reset to an
individual C64x+ Megamodule should not affect the state of the hardware boot controller on the device.
For more details on the initiators of the resets, see Section 7.7, Reset Controller.
The C6474 device supports several boot processes begins execution at the ROM base address, which
contains the bootloader code necessary to support various device boot modes. The boot processes are
software driven; using the BOOTMODE[3:0] device configuration inputs to determine the software
configuration that must be completed.
2.4.1 Boot Modes Supported
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes
are software driven, using the BOOTMODE[3:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are three possible boot modes:
•
•
No Boot (BOOTMODE[3:0] = 0000b)
With no boot, the CPU executes directly from the internal L2 RAM located at address 0x80 0000.
Note: Device operations are undefined if invalid code is located at address 0x80 0000. This boot mode
is a hardware boot mode.
Public ROM Boot
The C64x+ Megamodule Core 0 is released from reset and begins executing from the L3 ROM base
address. C64x+ Megamodule Core 0 is responsible for performing the boot process (e.g., from I2C
ROM, Ethernet, or RapidIO), after which C64x+ Megamodule Core 0 brings the other C64x+
megamodule cores out of reset by setting to 1 the EVTPULSE4 bit (bit 4) of the C64x+ Megamodule
Core 0's EVTASRT register. This process is valid only once: writing 1, then writing 1 again will not
bring Core 1 and 2 out of reset again. Then, the C64x+ Megamodule Core 0 begins execution from the
entry address defined in the boot table. The C64x+ Megamodule Core 1 and 2 begin execution from
their L2 RAMs' base address.
The boot process performed by C64x+ Megamodule Core 0 in public ROM boot is determined by the
BOOTMODE[3:0] value in the DEVSTAT register. C64x+ Megamodule Core 0 reads this value, and then
executes the associated boot process in software.
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Table 2-3. C6474 Supported Boot Modes
MODE NAME
BOOTMODE[3:0]
DESCRIPTION
No Boot (BOOTMODE[3:0] = 0000b)
No Boot
0000b
0001b
I2C Master Boot A
Slave I2C address is 0x50. C64x+ Megamodule Core 0 configures I2C, acts as a
master to the I2C bus and copies data from an I2C EEPROM or a device acting as an
I2C slave to the DSP using a predefined boot table format. The destination address
and length are contained within the boot table. After boot table copy is complete, the
C64x+ Megamodule Core 0 brings the other C64x+ Megamodule Cores out of reset
by setting to 1 the EVTPULSE4 bit (bit 4) of the C64x+ Megamodule Core EVTASRT
register.
I2C Master Boot B
I2C Slave Boot
0010b
0011
Similar to I2C boot A except the slave I2C address is 0x51.
The C64x+ Megamodule Core 0 configures I2C and acts as a slave and will accept
data and code section packets through the I2C interface. It is required that an I2C
master in present in the system.
EMAC Master Boot
EMAC Slave Boot
0100b
0101b
0110b
TI Ethernet Boot, C64x+ Megamodule Core 0 configures EMAC0 and EDMA, if
required, and brings the code image into the internal on-chip memory via the protocol
defined by the boot method (EMAC bootloader). After initializing the on-chip memory
to the known state, C64x+ Megamodule Core 0 brings the other C64x+ Megamodule
Cores out of reset.
EMAC Forced-Mode Boot
Reserved
0111b
1000b
1001b
1010b
1011b
Reserved
Serial RapidIO Boot (Config 0)
Serial RapidIO Boot (Config 1)
Serial RapidIO Boot (Config 2)
Serial RapidIO Boot (Config 3)
The C64x+ Megamodule Core 0 configures the SRIO and an external host loads the
application via SRIO peripheral, using directIO protocol. A doorbell interrupt is used to
indicate that the code has been loaded. For more details on the Serial RapidIO
configurations, see Table 2-4.
C64x+ Megamodule Core 0 configures Serial RapidIO and EDMA, if required, and brings the code image
into the internal on-chip memory via the protocol defined by the boot method (SRIO bootloader) and then
C64x+ Megamodule Core 0 brings the other C64x+ Megamodule Cores out of reset. Note that SRIO boot
modes are only supported on port 0.
Table 2-4. Serial RapidIO (SRIO) Supported Boot Modes
SRIO BOOT MODE
Bootmode 8 - Config 0
Bootmode 9 - Config 1
Bootmode 10 - Config 2
Bootmode 11 - Config 3
SERDES CLOCK
125 MHz
LINK RATE
1.25 Gbps
3.125 Gbps
1.25 Gbps
3.125 Gbps
BOOTMODE[3:0]
1000b
125 MHz
1001b
156.25 MHz
156.25 MHz
1010b
1011b
All the other BOOTMODE[3:0] modes are reserved.
2.4.2 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader
allows for any level of customization to current boot methods as well as the definition of a completely
customized boot.
16
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2.5 Pin Assignments
2.5.1 Pin Map
Figure 2-2 through Figure 2-5 show the C6474 pin assignments in four quadrants (A, B, C, and D).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DVDD18
AVDD118
RSV04
AIF_VDDT11
VSS
AIFTXN4
AIFTXP4
DVDD18
VSS
VSS
VSS
VSS
CVDDMON
DVDD18MON
AG
AF
AE
AD
AC
AB
AA
Y
AG
AF
AE
AD
AC
AB
AA
Y
ALTFSYNC CORECLK
SEL
ALTCORE
CLKP
ALTCORE
CLKN
VSS
VSS
VSS
VSS
AIFRXN5
AIFRXP5
AIFRXP4
AIFTXN5
VSS
VSS
VSS
VSS
VSS
DVDD18
RESETSTAT
RSV23
CLK
ALTFSYNC
PULSE
VSS
AIFRXN4
RSV02
VSS
VSS
VSS
RSV06
RSV07
SYSCLKP
SYSCLKN
POR
SMFRAME
CLK
SYSCLK
OUT
FSYNC
CLKP
FSYNC
CLKN
FRAME
BURSTP
FRAME
BURSTN
AIFTXP5
VSS
VSS
TRT
GP15
GP12
GP10
GP07
TDO
XWRST
VSS
DVDD18
VSS
AIF_VDDT11 AIF_VDDA11
AIF_VDDT11
DVDD18
VSS
DVDD18
VSS
DVDD18
TRTCLK
VSS
GP13
VSS
DVDD18
VSS
GP11
GP14
VSS
GP09
DVDD18
TRST
GP05
VSS
GP08
TCK
VSS
TMS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
W
DVDD18
W
VSS
VSS
VSS
V
GP06
GP03
GP00
TDI
VSS
V
GP02
DVDD18
EMU15
CVDD
CVDD
CVDD
U
DVDD18
U
GP01
GP04
VSS
CVDD
VSS
CVDD
VSS
CVDD
T
EMU11
VSS
T
DVDD18
CVDD
VSS
CVDD
VSS
CVDD
VSS
R
R
EMU10
EMU01
EMU07
EMU00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 2-2. C6474 Pin Map (Bottom View) [Quadrant A]
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15
16
17
18
19
20
21
22
23
24
25
26
27
VSS
VSS
AIFRXP2
AIFRXN2
VSS
AIFRXN1
AIFRXP1
VSS
RSV05
RSV24
AG
AF
AE
AD
AC
AB
AA
Y
AVDD218
AIF_VDDD11
DVDD18
AG
AF
AE
AD
AC
AB
AA
Y
AIF_VDDT11
AIFTXN2
AIFTXP2
AIFRXN3
AIFTXN3
AIF_VDDT11
AIF_VDDT11
VSS
VSS
RSV08
VSS
AIFRXP0
AIFTXN0
AIFTXN1
AIF_VDDA11
AIFRXN0
AIFTXP0
RSV09
VSS
VSS
AIFRXP3
VSS
VSS
VSS
DDRDQM1
DDRD15
RSV01
AIF_VDDR18
VSS
VSS
DDRSLRATE
DDRD13
DDRD14
DDRD11
DDRD08
VSS
DDRREF
CLKN
DDRREF
CLKP
AIF_VDDR18
AIFTXP3
AIFTXP1
VSS
DDRDQS1N DDRDQS1P
AIF_VDDA11
VSS
AIF_VDDT11
VSS
DVDD18
DDRD12
DDRD10
DDRD09
AIF_VDDA11
DDRRCV
ENOUT0
DDRRCV
ENIN0
VSS
DVDD18
DVDD18
DDRD04
DDRD02
DDRD00
VSS
DDRD07
DDRD06
DDRD05
VSS
DVDD18
DDRDQS0N DDRDQS0P
AIF_VDDD11
DVDD18
DDRDQM0
DDRD01
DDRD03
W
AIF_VDDD11
AIF_VDDD11
VSS
AIF_VDDD11
VSS
W
VSS
AIF_VDDD11
VSS
DDRCLK
OUTN0
DDRCLK
OUTP0
VSS
VSS
DVDD18
V
VSS
VSS
V
CVDD
CVDD
DVDD18
VSS
DDRBA2
DDRBA0
DDRA07
DDRA12
U
AIF_VDDD11
U
VSS
VSS
DDRCKE
VREFSSTL
VSS
T
VSS
CVDD
VSS
CVDD
T
CVDD
DVDD18
VSS
DDRBA1
DDRA03
DDRA09
R
CVDD
VSS
CVDD
VSS
R
15
16
17
18
19
20
21
22
23
24
25
26
27
Figure 2-3. C6474 Pin Map (Bottom View) [Quadrant B]
18
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15
16
17
18
19
20
21
22
23
24
25
26
27
VSS
CVDD
VSS
CVDD
VSS
DDRWE
DDRA10
P
N
M
L
VSS
DVDD18
VSS
P
N
M
L
CVDD
VSS
CVDD
CVDD
DVDD18
RSV03
DDRA05
DDRA01
DDRA02
DDRCAS
VSS
CVDD
VSS
VSS
CVDD
VSS
VSS
DDRRAS
VSS
DVDD18
VSS
DVDD18
VSS
CVDD
VSS
CVDD
CVDD
DDRA04
DDRA00
DDRA06
DDRA08
DDRA11
DDRA13
DVDD18
DDRCE
VSS
SGR_VDDD11
VSS
DDRODT
K
VSS
CVDD
K
J
DDRCLK
OUTN1
DDRCLK
OUTP1
SGR_VDDD11
VSS
CVDD
VSS
CVDD
DVDD18
J
VSS
VSS
DDRD31
DDRD28
DDRD27
DVDD18
H
G
F
DDRDQM3
DDRD29
DDRD30
H
G
F
DVDD18
VSS
DDRDQS3P DDRDQS3N
VSS
DDRD24
DDRD25
DDRD26
DDRRCV
ENIN1
DDRRCV
ENOUT1
DVDD18
DVDD18
VSS
E
D
C
B
A
SGR_VDDA11
VSS
SGR_VDDT11
VSS
SGR_VDDA11
VSS
VSS
VSS
E
D
C
B
A
DVDD18
VSS
VSS
DX0
RSV25
CLKX1
DX1
VSS
DDRD19
DDRD17
DDRD21
DDRD22
DDRD23
DDRD20
VSS
CLKS0
CLKX0
CLKR0
DR1
MDCLK
MDIO
RSV26
VSS
DDRDQS2N DDRDQS2P
VSS
SGMIIRXN
SGMIIRXP
FSR1
FSR0
VSS
DDRDQM2
DDRD16
DDRD18
VSS
VSS
SGR_VDDT11
RSV18
DVDD18
FSX1
22
DVDD18
CLKR1
24
CLKS1
25
VSS
DVDD18
SGMIITXP
SGMIITXN
VSS
SGR_VDDR18
DR0
20
FSX0
21
15
16
17
18
19
23
26
27
Figure 2-4. C6474 Pin Map (Bottom View) [Quadrant C]
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSS
CVDD
VSS
CVDD
VSS
CVDD
P
VSS
DVDD18
EMU16
EMU13
VSS
P
N
M
L
CVDD
VSS
CVDD
VSS
CVDD
CVDD
VSS
CVDD
VSS
VSS
N
EMU03
EMU05
DVDD18
RSV12
NMI2
VSS
EMU09
EMU04
VSS
EMU02
EMU18
EMU12
DVDD18
EMU06
EMU08
EMU17
VSS
VSS
VSS
CVDD
M
VSS
CVDD
CVDD
CVDD
VSS
DVDD18
L
VSS
CVDD
VSS
VSS
SGR_VDDD11
SGR_VDDD11
K
EMU14
NMI1
VSS
K
RSV11
RSV29
RSV10
NMI0
VSS
CVDD
VSS
SGR_VDDD11
VSS
DVDD18
CVDD
J
J
H
G
F
DVDD18
VCNTL3
VCNTL0
RSV14
TIMI0
VSS
VCNTL2
RSV13
TIMO1
SCL
VSS
DVDD18
VSS
H
G
F
VSS
VCNTL1
VSS
TIMO0
DVDD18
SGR_VDDT11
VSS
SGR_VDDA11
VSS
SGR_VDDT11
VSS
E
D
C
B
A
DVDD18
VSS
RSV21
RSV19
RSV20
VSS
VSS
E
D
C
B
A
RSV22
RSV15
RSV16
VSS
RIOSGMII
CLKN
VSS
VSS
VSS
VSS
VSS
SGR_VDDA11
SGR_VDDR18
RSV17
VSS
VSS
SDA
RSV27
RSV28
VSS
RIOSGMII
CLKP
VSS
RIOTXP0
RIOTXN0
RIOTXN1
RIOTXP1
VSS
VSS
VSS
TIMI1
SGR_VDDT11
VSS
VSS
VSS
SGR_VDDT11
VSS
VSS
VSS
VSS
VSS
DVDD18
VSS
RIORXN0
RIORXP0
VSS
RIORXP1
RIORXN1
VSS
DVDD18
VSS
VSS
VSS
VSS
VSS
8
1
2
3
4
5
6
7
9
10
11
12
13
14
Figure 2-5. C6474 Pin Map (Bottom View) [Quadrant D]
20
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2.6 Signal Groups Description
AVDD118
SYSCLKP
SYSCLKN
Clock/PLL1
and
PLL Controller
SYSCLKOUT
CORECLKSEL
ALTCORECLKP
ALTCORECLKN
RESETSTAT
RESET
NMI0
Reset and
Interrupts
NMI1
NMI2
XWRST
AVDD218
Clock/PLL2
TMS
TDO
TDI
RSV
TCK
TRST
Reserved
EMU00
EMU01
EMU02
IEEE Standard
1149.1
(JTAG)
Emulation
·
·
·
EMU14
EMU15
EMU16
EMU17
EMU18
Control/Status
Figure 2-6. CPU and Peripheral Signals
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32
Data
DDRD[31:0]
DDRCLKOUTP
DDRCLKOUTN
DDRCAS
DDRRAS
DDRWE
DDRCE
Memory Map
Address
External
Memory
Controller
DDRDQSP[3:0]
DDRDQSN[3:0]
14
DDRA[13:0]
DDRRCVENIN[2:0]
DDRRCVENOUT[2:0]
DDRODT
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRSLRATE
VREFSSTL
Byte Enables
DDRBA0
DDRBA1
DDRBA2
Bank Address
DDR Memory Controller (32-bit Data Bus)
Figure 2-7. DDR Memory Controller Peripheral Signals
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TIMI0
TIMO0
TIMO1
TIMI1
Timer Pin Manager
Timers (64-Bit)
GP00
GP01
GP08
GP09
GP10
GP11
GP12
GP13
GP14
GP15
GP02
GP03
GP04
GP05
GP06
GP07
GPIO
General-Purpose Input/Output 0 (GPIO) Port
RIOTXN0
RIOTXP0
RIOTXN1
RIOTXP1
RIOSGMIICLKN(A)
RIOSGMIICLKP(A)
Transmit
Clock
RIORXN0
RIORXP0
RIORXN1
RIORXP1
Receive
RapidIO
A. Reference Clock to drive RapidIO and SGMII.
Figure 2-8. Timers/GPIO/RapidIO Peripheral Signals
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McBSP1
Transmit
McBSP0
Transmit
CLKX1
FSX1
DX1
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
CLKR0
FSR0
DR0
Receive
Clock
Receive
Clock
CLKS1
CLKS0
Multichannel Buffered Serial Ports
(McBSPs)
FSYNCCLKN
FSYNCCLKP
FRAMEBURSTN
FRAMEBURSTP
ALTFSYNCPULSE
TRT
ALTFSYNCCLK
TRTCLK
FSYNC
Clock
SMFRAMECLK
Frame Synchroniztion (FSYNC)
AIFTXN[5:0]
AIFTXP[5:0]
Transmit
SCL
SDA
I2C
AIFRXN[5:0]
AIFRXP[5:0]
Receive
Antenna Interface (AIF)
Figure 2-9. McBSP/FSYNC/AIF/I2C Peripheral Signals
24
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Ethernet MAC
(EMAC)
SGMIITXN
SGMIITXP
SGMII
Transmit
MDIO
MDIO
SGMIIRXN
SGMIIRXP
SGMII
Receive
MDCLK
RIOSGMIICLKN(A)
RIOSGMIICLKP(A)
SGMII
Clock
Ethernet MAC (EMAC) and MDIO
A. Reference Clock to drive RapidIO and SGMII.
Figure 2-10. EMAC/MDIO [SGMII] Peripheral Signals
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2.7 Terminal Functions
The terminal functions table (Table 2-5) identifies the external signal names, the pin type (I, O, O/Z, or
I/O/Z), whether the pin has any internal pullup/pulldown resistors, and the signal function description.
Table 2-5. Terminal Functions
SIGNAL
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NAME
NO.
ANTENNA INTERFACE
AIFRXN0
AF22
AF21
AG20
AG21
AG18
AG17
AE17
AE18
AE14
AE13
AF12
AF13
AE21
AE22
AD21
AD20
AF16
AF17
AD17
AD16
AG13
AG14
AD13
AD12
I
I
AIFRXP0
AIFRXN1
AIFRXP1
AIFRXN2
AIFRXP2
AIFRXN3
AIFRXP3
AIFRXN4
AIFRXP4
AIFRXN5
AIFRXP5
AIFTXN0
AIFTXP0
AIFTXN1
AIFTXP1
AIFTXN2
AIFTXP2
AIFTXN3
AIFTXP3
AIFTXN4
AIFTXP4
AIFTXN5
AIFTXP5
I
I
I
I
Antenna Interface Receive Data (6 links)
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
Antenna Interface Transmit Data (6 links)
CLOCK/RESETS
NMI0
NMI1
NMI2
J4
J2
J1
I
I
I
IPD
IPD
IPD
Non-maskable interrupts. NMI0, NMI1, and NMI2 pins are mapped to C64x+
Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core
2, respectively. NMIs are edge-driven (rising edge). Any noise on the NMI pin
may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is
recommended that the NMI pin be grounded rather than relying on the IPD.
XWRST
AD5
AF4
I
O
I
Warm Reset
RESETSTAT
POR
Reset Status Output
Power-on Reset
AE5
SYSCLKP
AE9
I
System Clock Input to Antenna Interface and main PLL (Main PLL optional vs
ALTCORECLK)
SYSCLKN
AE10
AF10
AF9
I
ALTCORECLKN
ALTCORECLKP
DDRREFCLKN
DDRREFCLKP
I
Alternate Core Clock Input to main PLL (vs SYSCLK)
DDR Reference Clock Input to DDR PLL
I
AD23
AD24
I
I
System Clock Output to be used as a general purpose output clock for debug
purposes
SYSCLKOUT
AD6
O/Z
IPD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = internal pulldown, IPU = internal pullup. All internal pullups and pulldowns are 100 μA.
26
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
Core Clock Select to select between SYSCLK(N|P) and ALTCORECCLK to the
main PLL
CORECLKSEL
AF7
I
RIOSGMIICLKN
RIOSGMIICLKP
D9
C9
I
I
RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SERDES
DDR MEMORY CONTROLLER
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRCE
W24
AE24
B24
H24
L24
T25
R25
U25
K25
N25
M25
R26
L25
N27
L26
U26
K26
R27
P25
L27
U27
K27
V25
V24
J25
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
DDR2 EMIF Data Masks
DDR2 EMIF Chip Enable
DDR Bank Address
DDRBA0
DDRBA1
DDRBA2
DDRA00
DDRA01
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDR2 EMIF Address Bus
DDRA07
DDRA08
DDRA09
DDRA10
DDRA11
DDRA12
DDRA13
DDRCLKOUTP0
DDRCLKOUTN0
DDRCLKOUTP1
DDRCLKOUTN1
DDR2 EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)
J24
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
DDRD00
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
W27
W25
Y27
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
DDRD06
DDRD07
DDRD08
DDRD09
DDRD10
DDRD11
DDRD12
DDRD13
DDRD14
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD30
DDRD31
DDRCAS
DDRRAS
DDRWE
DDRCKE
W26
AA27
AA26
AA25
AA24
AC27
AC26
AC25
AD27
AC24
AE26
AE27
AE25
B25
DDR2 EMIF Data Bus
D25
B26
D24
B27
D26
D27
C27
F24
F25
F26
F27
G27
H25
H26
H27
N26
DDR2 EMIF Column Address Strobe
DDR2 Row Address Strobe
DDR2 EMIF Write Enable
M24
P24
O/Z
O/Z
T24
O/Z
DDR2 EMIF Clock Enable
DDRDQS0P
DDRDQS0N
DDRDQS1P
DDRDQS1N
DDRDQS2P
DDRDQS2N
DDRDQS3P
DDRDQS3N
Y26
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Y25
AD26
AD25
C26
DDR2 EMIF Data Strobe
C25
G25
G26
28
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
AB25
AB24
E24
DDRRCVENIN0
DDRRCVENOUT0
DDRRCVENIN1
DDRRCVENOUT1
I
O/Z
I
DDR2 EMIF Data Strobe Gate Input/Outputs to help meet DDR Timing
E25
O/Z
DDR2 EMIF On-Die Termination Outputs used to set termination on the
SDRAMs
The DDR2 ODT control register is found at 0x7000 00F0
Bits 1:0 are the ODT status, these bits are Read/Write:
00 - no termination
DDRODT
K24
O/Z
01- half termination
11 - full termination
DDRSLRATE
VREFSSTL
AE23
T26
I
DDR2 Slew rate control
A
Reference Voltage Input for SSTL18 buffers used by DDR2 EMIF (VDDS18/2)
JTAG EMULATION
JTAG Clock Input
JTAG Data Input
JTAG Data Output
JTAG Test Mode Input
JTAG Reset
TCK
W4
V4
W3
W1
W2
R4
R2
N3
N1
M2
M1
N4
R3
M4
N2
R1
T2
I
IPU
IPU
TDI
I
TDO
O/Z
TMS
I
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
TRST
I
EMU00
EMU01
EMU02
EMU03
EMU04
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Emulation and Trace Port
L3
P4
K2
T1
P3
L4
M3
FRAME SYNCHRONIZATION (FSYNC)
FSYNCCLKN
FSYNCCLKP
SMFRAMECLK
FRAMEBURSTN
FRAMEBURSTP
ALTFSYNCCLK
ALTFSYNCPULSE
TRT
AD8
AD7
AD4
AD10
AD9
AF6
I
Frame Sync Interface Clock used to drive the frame synchronization interface
(OBSAI RP1 clock)
I
O/Z
IPD
Frame Sync Clock Output
I
I
I
I
I
I
Frame Burst to drive frame indicators to the frame synchronization module
(OBSAI RP1)
IPD
IPD
IPD
IPD
Alternate Frame Sync Clock Input (vs FSYNCCLK(N|P)
Alternate Frame Sync Input (vs FRAMEBURST (N|P)
Multi-standard Frame Synchronization Tick
AE6
AD3
AC4
TRTCLK
Multi-standard Frame Synchronization Clock
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
IPD
GP00
GP01
GP02
GP03
GP04
GP05
GP06
GP07
GP08
GP09
GP10
GP11
GP12
GP13
GP14
GP15
T3
U4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
V1
U3
General Purpose Input/Output
GPIO[3:0] are mapped to BOOTMODE[3:0]
(see Section 2.4.1, Boot Modes Supported)
GPIO4 is mapped to LENDIAN
0 = Big Endian
1 = Little Endian (default)
GPIO5 is mapped to L2_CONFIG is a reserved bootstrap pin and should be
pulled up to DVDD18
during bootstrap
GPIO[7:6] are not multiplexed
GPIO[11:8] are mapped to DEVNUM[3:0]
(see Section 2.4.1, Boot Modes Supported)
GPIO[15:12] are not multiplexed
T4
V2
V3
Y3
Y4
AA2
AA3
AB4
AB3
AB2
AA4
AC3
I2C
SCL
SDA
E4
D4
I/O/Z
I/O/Z
I2C Clock (open drain)
I2C Data (open drain)
MULTICHANNEL BUFFERED SERIAL PORT (McBSP)
CLKS0
CLKR0
CLKX0
DR0
D20
B20
C20
A20
D19
B21
A21
A25
A24
C22
D21
B22
C21
A22
I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McBSP0 Module Clock
McBSP0 Receive Clock
McBSP0 Transmit Clock
McBSP0 Receive Data
McBSP0 Transmit Data
McBSP0 Receive Frame Sync
McBSP0 Transmit Frame Sync
McBSP1 Module Clock
McBSP1 Receive Clock
McBSP1 Transmit Clock
McBSP1 Receive Data
McBSP1 Transmit Data
McBSP1 Receive Frame Sync
McBSP1 Transmit Frame Sync
MISCELLANEOUS
I/O/Z
I/O/Z
I
DX0
O/Z
I/O/Z
I/O/Z
I
FSR0
FSX0
CLKS1
CLKR1
CLKX1
DR1
I/O/Z
I/O/Z
I
DX1
O/Z
I/O/Z
I/O/Z
FSR1
FSX1
VCNTL0
VCNTL1
VCNTL2
VCNTL3
G3
G2
H4
H3
O
O
O
O
Voltage Control Outputs to variable core power supply (open-drain buffers)
Note: These pins must be externally pulled up. For more infomation, see the
TMS320C6474 Hardware Design Guide application report (literature number
SPRAAW7).
SERIAL RAPIDIO (SRIO)
RIORXN0
RIORXP0
RIORXN1
RIORXP1
A9
I
I
I
I
A10
A13
A12
Serial RapidIO Receive Data (2 links)
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
C11
C10
C13
C14
RIOTXN0
RIOTXP0
RIOTXN1
RIOTXP1
O
O
O
O
Serial RapidIO Transmit data (2 links)
ETHERNET MAC (EMAC) AND SGMII
SGMIIRXN
SGMIIRXP
SGMIITXN
SGMIITXP
C16
C17
A16
A15
I
Ethernet MAC SGMII Receive Data
I
O
O
Ethernet MAC SGMII Transmit Data
MANAGEMENT DATA INPUT/OUTPUT (MDIO)
MDIO
B19
C19
I/O/Z
O
IPU
IPD
MDIO Data
MDIO Clock
MDCLK
TIMERS
TIMI0
TIMI1
TIMO0
TIMO1
E3
C4
F2
F4
I
IPD
IPD
IPD
IPD
Timer Inputs
I
O/Z
O/Z
Timer Outputs
RESERVED
RSV01
RSV02
RSV03
RSV04
RSV05
RSV06
RSV07
RSV08
RSV09
RSV10
RSV11
RSV12
RSV13
RSV14
RSV15
RSV16
RSV17
RSV18
RSV19
RSV20
RSV21
RSV22
RSV23
RSV24
RSV25
RSV26
RSV27
RSV28
AE19
AD14
N24
AG10
AG24
AE7
AE8
AF24
AF25
K4
A
A
Reserved, unconnected
Reserved, unconnected
Reserved, 45.3-Ω 1% resistor to GND
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, GND connection
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, unconnected
Reserved, CVDD connection
Reserved, CVDD connection
Reserved, unconnected
Reserved, unconnected
Reserved, GND connection
Reserved, GND connection
Reserved, unconnected
Reserved, unconnected
A
A
A
O
O
O
O
I/O/Z
I/O/Z
I/O/Z
O/Z
O/Z
A
IPU
IPU
IPU
IPD
IPD
K3
K1
G4
F3
D7
C7
A
B12
B18
D6
A
A
I/O/Z
I/O/Z
IPU
IPU
C6
E6
E7
AE4
AG25
D22
C23
D5
O/Z
O/Z
A
IPD
IPD
A
A
C5
A
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
RSV29
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
J3
Reserved, DVDD18 connection
SUPPLY VOLTAGE PINS
J11
J17
J19
J9
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
K10
K18
L11
L13
L15
L17
L19
L9
M10
M12
M14
M16
M18
N11
N13
N15
N17
N19
N9
CVDD
0.9 - 1.2-V Core Supply Voltage
P10
P12
P14
P16
P18
R11
R13
R15
R17
R19
R9
T10
T12
T14
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
T16
S
S
S
S
S
S
S
S
S
S
S
S
S
A
A
A
A
A
A
A
A
A
A
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
T18
U11
U13
U15
U19
U9
CVDD
0.9 - 1.2-V Core Supply Voltage
V10
V12
V14
W11
W13
W9
AC12
AC15
AC18
AC21
D12
D18
E11
AIF_V DDA11
1.1-V AIF Serdes Analog Supply
SGR_V DDA11
1.1-V SRIO/SGMII Serdes Analog Supply
1.8-V PLL Supply
E15
AVDD218
AVDD118
AG23
AG9
AG26
U17
V16
AIF _V DDD11
V18
1.1-V AIF Serdes Digital Supply
W15
W17
W19
J13
J15
SGR_V DDD11
K12
1.1-V SRIO/SGMII Serdes Digital Supply
K14
K16
CVDDMON
AG6
AD19
AD15
C12
A18
0.9 - 1.2-V CVDD Supply Monitor
1.8-V AIF Serdes Regulator Supply
AIF_VDDR18
SGR_VDDR18
1.8-V SRIO/SGMII Serdes Regulator Supply
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
A1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
A19
A23
A27
A5
AA23
AA5
AB26
AC1
AC23
AC5
AC7
AC9
AF5
AG1
AG27
AG8
E1
E19
E21
E23
E27
E5
DVDD18
1.8-V I/O Supply
G23
G5
H2
J23
J27
J5
L1
L23
L5
M26
N23
N5
P2
P26
R23
R5
U1
U23
U5
V26
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
W23
W5
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
DVDD18
1.8-V I/O Supply
Y2
Y24
DVDD18MON
AG7
AC11
AC14
AC17
AC20
AF15
AF19
AG11
B13
1.8-V DVDD18 Supply Monitor
AIF_VDDT11
1.1-V AIF Serdes Termination Supply
B17
B8
SGR_VDDT11
1.1-V SRIO/SGMII Serdes Termination Supply
E13
E17
E9
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
GROUND PINS
A11
A14
A17
A2
A26
A3
A4
A6
A7
A8
AA1
AB1
AB23
AB27
AB5
AC10
AC13
AC16
AC19
AC2
AC22
AC6
AC8
AD1
AD11
AD18
AD2
AD22
AE1
AE11
AE12
AE15
AE16
AE2
AE20
AE3
AF1
VSS
GND
Ground
AF11
AF14
AF18
AF2
AF20
AF23
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
AF26
AF27
AF3
AF8
AG12
AG15
AG16
AG19
AG2
AG22
AG3
AG4
AG5
B1
B10
B11
B14
B15
B16
B2
B23
B3
VSS
GND
Ground
B4
B5
B6
B7
B9
C1
C15
C18
C2
C24
C3
C8
D1
D10
D11
D13
D14
D15
D16
D17
D2
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
D23
D3
D8
E10
E12
E14
E16
E18
E2
E20
E22
E26
E8
F1
F23
F5
G1
G24
H1
H23
H5
VSS
J10
J12
J14
J16
J18
J26
K11
K13
K15
K17
K19
K23
K5
GND
Ground
K9
L10
L12
L14
L16
L18
L2
M11
M13
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
M15
M17
M19
M23
M27
M5
M9
N10
N12
N14
N16
N18
P1
P11
P13
P15
P17
P19
P23
P27
P5
VSS
P9
GND
Ground
R10
R12
R14
R16
R18
R24
T11
T13
T15
T17
T19
T23
T27
T5
T9
U10
U12
U14
U16
U18
U2
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Table 2-5. Terminal Functions (continued)
SIGNAL
NAME
TYPE(1) IPD/IPU(2)
SIGNAL DESCRIPTION
NO.
U24
V11
V13
V15
V17
V19
V23
V27
V5
VSS
GND
Ground
V9
W10
W12
W14
W16
W18
Y1
Y23
Y5
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2.8 Development and Device Support
2.8.1 Development Support
In case the customer would like to develop their own features and software on the C6474 device, TI offers
an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tool's support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE). The following products support
development of C6000 DSP-based applications:
Software Development Tools: Code Composer Studio Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any DSP application.
Hardware Development Tools: Extended Development System (XDS™) Emulator (supports C6000 DSP
multiprocessor system debug) Evaluation Module (EVM).
2.8.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320C6474ZUN). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
•
•
•
TMX: Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP: Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS: Fully qualified production device.
Support tool development evolutionary flow:
•
TMDX: Development-support product that has not yet completed Texas Instruments internal
qualification testing.
•
TMDS: Fully qualified development-support product .
TMX and TMP devices and TMDX development-support tools are shipped with against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZUN), the temperature range (for example, Blank is the default commercial
temperature range), and the device speed range in megahertz (for example, Blank is 1000 [1 GHz]).
Figure 2-11 provides a legend for reading the complete device name for any TMS320C64x+ DSP
generation member. For device part numbers and further ordering information for TMS320C6474 in the
CUN, GUN, or ZUN package type, see the TI website (www.ti.com) or contact your TI sales
representative.
TMS
320
ZUN
(
)
(
)
(
)
C6474
PREFIX
DEVICE SPEED RANGE
TMX = Experimental device
TMS = Qualified device
Blank = 1 GHz
2 = 1.2 GHz
8 = 850 MHz
TEMPERATURE RANGE
DEVICE FAMILY
320 = TMS320ä DSP family
Blank = 0°C to 100°C (default commercial temperature; 850-MHz and 1-GHz
Blank = 0°C to 95°C (default commercial temperature; 1.2-GHz device)
A = -40°C to 100°C (extended temperature; 1-GHz device)
A = -40°C to 95°C (extended temperature; 1.2-GHz device)
DEVICE
C64x+ DSP:
C6474
SILICON REVISION(A)
F = Silicon Revision 2.1
PACKAGE TYPE(B)
CUN = 561-pin plastic BGA (lead-free die bump and solder balls)
GUN = 561-pin plastic BGA (leaded [Pb] solder balls)
ZUN = 561-pin plastic BGA (lead-free solder balls and leaded [Pb] die bumps)
A. Silicon revision correlates to the lot trace code found on the second line of the package marking. For more
information, see the TMS320C6474 Digital Signal Processor Silicon Errata (literature number SPRZ283).
B. BGA = Ball Grid Array
Figure 2-11. TMS320C64x+™ DSP Device Nomenclature (including TMS320C6474 DSP)
2.9 Documentation Support
The following documents describe the TMS320C6474 multicore digital signal processor. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
SPRU732
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871
TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRAA84 TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in
the devices that is identical is not included.
SPRU889
High-Speed DSP Systems Design Reference Guide. Provides recommendations for
meeting the many challenges of high-speed DSP system design. These recommendations
include information about DSP audio, video, and communications systems for the C5000 and
C6000 DSP platforms.
SPRUG08 TMS320C6474 DSP Ethernet Media Access Controller (EMAC)/ Management Data
Input/Output (MDIO) User's Guide. This document provides a functional description of the
Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management
Data Input/Output (MDIO) module integrated with the TMS320C6474 digital signal
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processors (DSPs).
SPRUG09 TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL) Controller
User's Guide. This document describes the operation of the software-programmable
phase-locked loop (PLL) controller in the TMS320C6474 digital signal processors (DSPs).
SPRUG10 TMS320C6474 DSP PSC User's Guide. This document describes the Power/Sleep
Controller (PSC) for the TMS320C6474 digital signal processors (DSPs).
SPRUG11 TMS320C6474 DSP Enhanced DMA (EDMA3) Controller User's Guide. This document
describes the Enhanced DMA (EDMA3) Controller on the TMS320C6474 digital signal
processors (DSPs).
SPRUG12 TMS320C6474 DSP Antenna Interface User's Guide. This document describes the
Antenna Interface module on the TMS320C6474 digital signal processors (DSPs).
SPRUG13 TMS320C6474 DSP Frame Synchronization User's Guide. This document describes the
reference guide for Frame Synchronization module on the TMS320C6474 digital signal
processors (DSPs).
SPRUG14 TMS320C6474 DSP Semaphore User's Guide. This document describes the usage of the
semaphore and some of the CSL calls used to configure/use the Semaphore module on the
TMS320C6474 digital signal processors (DSPs).
SPRUG16 TMS320C6474 DSP General-Purpose Input/Output (GPIO) User's Guide. This document
describes the general-purpose input/output (GPIO) peripheral in the digital signal processors
(DSPs) of the TMS320C6474 DSP family.
SPRUG17 TMS320C6474 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide. This
document describes the operation of the multichannel buffered serial port (McBSP) in the
digital signal processors (DSPs) of the TMS320C6474 device.
SPRUG18 TMS320C6474 DSP 64-Bit Timer User’s Guide. This document provides an overview of the
64-bit timer in the TMS320C6474 digital signal processors (DSPs).
SPRUG19 TMS320C6474 DSP DDR2 Memory Controller User's Guide. This document describes the
DDR2 memory controller in the TMS320C6474 digital signal processors (DSPs).
SPRUG20 TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 (VCP2) Reference Guide. This
document describes the operation and programming of the VCP2 in the TMS320C6474
digital signal processors (DSPs).
SPRUG21 TMS320C6474 DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide. This
document describes the operation and programming of the TCP2 in the TMS320C6474
digital signal processors (DSPs).
SPRUG22 TMS320C6474 DSP Inter-Integrated Circuit (I2C) Module User's Guide. This document
describes the inter-integrated circuit (I2C) module in the TMS320C6474 digital signal
processors (DSPs).
SPRUG23 TMS320C6474 DSP Serial RapidIO (SRIO) User's Guide. This document describes the
Serial RapidIO (SRIO) on the TMS320C6474 digital signal processors (DSPs).
SPRUEC6 TMS320C645x/C647x DSP Bootloader User's Guide. This document describes the
features of the on-chip Bootloader provided with the TMS320C645x/C647x digital signal
processors (DSPs).
SPRUFK6 TMS320C6474 DSP Chip Interrupt Controller (CIC) User's Guide. This document
describes the system event routing using the chip interrupt controller (CIC) for the
TMS320C6474 digital signal processors (DSPs).
SPRAAW5 TMS320C6474 Module Throughput. This document provides information on the
TMS320C6474 module throughput.
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SPRAAW7 TMS320C6474 Hardware Design Guide. This document describes hardware system design
considerations for the TMS320C6474 DSP.
SPRAAW8 TMS320C6474 DDR2 Implementation Guidelines. This document provides implementation
instructions for the DDR2 interface contained on the TMS320C6474 DSP.
SPRAAW9 TMS320C6474 SERDES Implementation Guidelines. This document contains
implementation instructions for the three serializer/deserializer (SERDES) based interfaces
on the TMS320C6474 DSP.
SPRAAX3 TMS320C6474 Power Consumption Summary. This document discusses the power
consumption of the Texas Instruments TMS320C6474 digital signal processor (DSP).
SPRAB25 How to Approach Inter-Core Communication on TMS320C6474. This document
discusses the of handling the three cores that are present on the TMS320C6474 DSP along
with what features are supported and how can they be used, how the cores communicate
effectively with each other, and how board-level scalability is allowed.
2.10 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and
help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
44
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3 Device Configuration
On the C6474 device, certain device configurations (like boot mode, pin multiplexing, and endianness) are
selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset.
By default, the peripherals on the device are disabled and must be enabled by software before being
used.
3.1 Device Configuration at Device Reset
Table 3-1 describes the C6474 device. The logic level is latched at reset to determine the device
configuration. The logic level can be set by using external pullup/pulldown resistors or by using some
control device to intelligently drive these pins. When using a control device, take care to avoid contention
on the lines when the device is out of reset. The are sampled during power-on reset and are driven after
the reset is removed. To avoid contention, the control device must stop driving the of the DSP.
NOTE
If a configuration pin must be routed out from the device, the internal pullup/pulldown
(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external
pullup/pulldown resistor.
Table 3-1. Device Configuration Pins
CONFIGURATION
DEFAULT IPU/IPD
FUNCTIONAL DESCRIPTION
PIN
BOOTMODE[3:0]
LENDIAN
0000b
1b
Boot Mode Selection
Device Endian Mode
0
1
Big Endian
Little Endian
DEVNUM[3:0]
CORECLKSEL
0000b
0b
Device number
Core Clock Select
0
1
SYSCLK is shared between the Antenna Interface and the input to PLLCTL1.
ALTCORECLK is used as the input to PLLCTL1 and SYSCLK is used only for the
Antenna Interface.
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the C6474 device are controlled by the Power/Sleep Controller (PSC). By
default the AIF, SRIO, TCP, and VCP are held in reset and clock-gated. The memories in these modules
are also in a low-leakage sleep mode. Software will be required to turn these memories on then enable
the modules (turn on clocks and de-assert reset) before these modules can be used.
If one of the above modules is used in the selected boot mode, the ROM code will automatically enable
the used module.
All other modules come up enabled by default and there is no special software sequence to enable.
For more detailed information on the PSC usage, see the TMS320C6474 DSP Power/Sleep Controller
(PSC) User's Guide (literature number SPRUG10).
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3.3 Device State Control Registers
The C6474 device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 3-2.
Table 3-2. Device State Control Registers
ADDRESS START
ADDRESS END
SIZE
ACRONYM
DESCRIPTION
0288 0800
0288 0803
4B
DEVCFG1
The first register with the parameters is set through
software to configure different components on the device
0288 0804
0288 0807
4B
DEVSTAT
Stores all parameters latched from configuration pins or
configured through the DEVCFG register
0288 0808
0288 080C
0288 0810
0288 0814
0288 080B
0288 080F
0288 0813
0288 0817
4B
4B
4B
4B
DSP_BOOT_ADDR0
DSP_BOOT_ADDR1
DSP_BOOT_ADDR2
DEVID
The boot address for C64x+ Megamodule Core 0
The boot address for C64x+ Megamodule Core 1
The boot address for C64x+ Megamodule Core 2
Parameters for DSP device IDs also referred to as JTAG
or BSDL IDs. These must be readable by the
configuration bus so that this can be accessed via JTAG
and CPU
0288 0818
0288 0828
0288 082C
0288 0830
0288 0834
0288 083C
0288 0840
0288 0900
0288 0827
0288 082B
0288 082F
0288 0833
0288 083B
0288 083F
0288 08FF
0288 0903
16B
4B
Reserved
Reserved
Reserved
Reserved
EFUSE_MAC
PRI_ALLOC
Reserved
IPCGR0
4B
4B
8B
Required for EMAC boot
Priority Allocation Register
N/A
4B
192B
4B
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
0288 0904
0288 0908
0288 0907
0288 090B
4B
4B
IPCGR1
IPCGR2
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
0288 090C
0288 0940
0288 093F
0288 0943
52B
4B
Reserved
IPCAR0
N/A
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
0288 0944
0288 0948
0288 0947
0288 094B
4B
4B
IPCAR1
IPCAR2
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
46
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3.4 Device Status Register Descriptions
The device status register depicts the device configuration selected upon device reset. Once set, these
bits remain set until a device reset.
Figure 3-1 shows the device configuration register 1 and Table 3-3 describes the parameters that are set
through software to configure different components on the device. The configuration is done through the
device configuration DEVCFG register, which is one-time writeable through software. The register is reset
on all hard resets and is locked after the first write.
31
3
2
1
0
Reserved
CLKS1 CLKS0
R/W-0 R/W-0
SYSCLKOUTEN
R/W-1
R-00000000000000000000000000000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-1. Device Configuration Register (DEVCFG)
Table 3-3. Device Configuration Register (DEVCFG) Field Descriptions
Bit
31:3
2
Field
Value Description
Reserved
Reserved
CLKS1
McBSP1 CLKS Select
0
1
CLKS1 device pin
chip_clks from Main.PLL
McBSP0 CLKS Select
CLKS0 device pin
1
0
CLKS0
0
1
chip_clks from Main.PLL
SYSCLKOUT Enable
No Clock Output
SYSCLKOUTEN
0
1
Clock output Enabled
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31
16
Reserved
R-0
15
10
2
9
8
0
Reserved
R-0
DEVNUM
7
6
5
1
DEVNUM
BOOTMODE
Reserved
LENDIAN
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-2. Device Configuration Status Register (DEVSTAT)
Table 3-4. Device Configuration Status Register Field Descriptions
Bit
Field
Value Description
Reserved
31:10 Reserved
9:6
5:2
DEVNUM
Device number
BOOTMODE
Determines the boot method for the device. For more information on bootmode, see Section 2.4.
0000 No Boot
0001 I2C Master Boot (Slave Address 0x50)
0010 I2C Master Boot (Slave Address 0x51)
0011 I2C Slave Boot
0100 EMAC Master Boot
0101 EMAC Slave Boot
0110 EMAC Forced Mode Boot
0111 Reserved
1000 RapidIO Boot (Configuration 0)
1001 RapidIO Boot (Configuration 1)
1010 RapidIO Boot (Configuration 2)
1011 RapidIO Boot (Configuration 3)
11xx
Reserved
Reserved
1
0
Reserved
LENDIAN
Device Endian mode. Shows the status of whether the system is operating in Big Endian mode or
Little Endian mode.
0
1
Big Endian mode
Little Endian mode
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3.5 Inter-DSP Interrupt Registers (IPCGR0-IPCGR2 and IPCAR0-IPCAR2)
The IPCGRn (IPCGR0 thru IPCGR2) and IPCARn (IPCAR0 thru IPCAR2) registers facilitate inter-DSP
interrupts. This can be utilized by external hosts or C64x+ megamodules to generate interrupts to other
DSPs. A write of 1 to the IPCG field of IPCGRn register generates an interrupt pulse to C64x+
Megamodulen (n = 0-2). These registers also provide a source ID, by which up to 28 different sources of
interrupts can be identified.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 SRCS22 SRCS21 SRCS20 SRCS19 SRCS18 SRCS17 SRCS16 SRCS15 SRCS14 SRCS13 SRCS12
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
SRCS11 SRCS10
SRCS9
SRCS8
SRCS7
SRCS6
SRCS5
SRCS4
SRCS3
SRCS2
SRCS1
SRCS0
Reserved
IPCG
R/W- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
0
R-000
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-3. IPC Generation Registers (IPCGR0-IPCGR2)
Table 3-5. IPC Generation Registers (IPCGR0-IPCGR2) Field Descriptions
Bit
Field
Value Description
31:4
SRCS[27:0]
Write:
0
1
No effect
Set register bit
Read:
Returns current value of internal register bit
3:1
0
Reserved
IPCG
Reserved
Write:
0
1
No effect
Create an inter-DSP interrupt pulse to the corresponding C64x+ megamodule (C64x+
Megamodule0 for IPCGR0, etc.)
Read:
Returns 0, no effect
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRCC27 SRCC26 SRCC25 SRCC24 SRCC23 SRCC22 SRCC21 SRCC20 SRCC19 SRCC18 SRCC17 SRCC16 SRCC15 SRCC14 SRCC13 SRCC12
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
0
SRCC11 SRCC10
SRCC9
SRCC8
SRCC7
SRCC6
SRCC5
SRCC4
SRCC3
SRCC2
SRCC1
SRCC0
Reserved
R/W- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
0
R-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-4. IPC Acknowledgment Registers (IPCAR0-IPCAR2)
Table 3-6. IPC Acknowledgment Registers (IPCAR0-IPCAR2) Field Descriptions
Bit
Field
Value Description
31:4
SRCC[27:0]
Write:
0
1
No effect
Clear register bit
Read:
Returns current value of internal register bit
Reserved
3:0
Reserved
3.6 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
C6474 device, the JTAG ID register resides at address location 0x0288 0814. For the actual register bit
names and their associated bit field descriptions, see Figure 3-5 and Table 3-7.
31
28 27
12 11
1
0
VARIANT
(4-bit)
PART NUMBER
(16-bit)
MANUFACTURER
(11-bit)
LSB
R-1
R-n
R-0000 0000 1001 0010b
R-000 0001 0111b
LEGEND: R = Read only; -n = value after reset
Figure 3-5. JTAG ID (JTAGID) Register
Table 3-7. JTAG ID (JTAGID) Register Field Descriptions
Bit
Field
Value Description
31:28 VARIANT
Variant (4-Bit) value. The value of this field depends on the silicon revision being used.
Note: the VARIANT filed may be invalid if no CLKIN1 signal is applied.
Part Number (16-Bit) value. C6474 value: 0000 0000 1001 0010b.
Manufacturer (11-Bit) value. C6474 value: 000 0001 0111b.
LSB value. This bit is read as 1 for C6474.
27:12 PART NUMBER
11:1
0
MANUFACTURER
LSB
3.7 Debugging Considerations
It is recommended that external connections be provided to device configuration pins. Although internal
pullup/pulldown resistors exist on these pins, providing external connectivity adds convenience to the user
in debugging and flexibility in switching operating modes.
For the internal pullup/pulldown resistors for all device pins, see Table 2-5.
50
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4 System Interconnect
On the C6474 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system
peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency,
concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric the
CPU can send data to the Viterbi co-processor (VCP2) without affecting a data transfer through the DDR2
memory controller. The switch fabrics also allow for seamless arbitration between the system masters
when accessing system slaves.
4.1 Internal Buses, Switch Fabrics, and Bridges/Gaskets
Two types of buses exist in the C6474 device: data buses and configuration buses. Some C6474
peripherals have both a data bus and a configuration bus interface, while others only have one type of
interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.
Configuration buses are mainly used to access the register space of a peripheral and the data buses are
used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer
data. For example, data is transferred to the VCP2 and TCP2 via their configuration bus interface.
Similarly, the data bus can also be used to access the register space of a peripheral. For example, the
DDR2 memory controller registers are accessed through their data bus interface.
The C64x+ megamodule, the EDMA3 transfer controllers, and the various system peripherals can be
classified into two categories: masters and slaves. Masters are capable of initiating read and write
transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves on the other hand
rely on the EDMA3 to perform transfers to and from them. Examples of masters include the EDMA3
transfer controllers, SRIO, and EMAC. Examples of slaves include the McBSP and I2C.
The C6474 device contains two switch fabrics through which masters and slaves communicate. The data
switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect
mainly used to move data across the system (for more information, see Section 4.3). The SCR adds no
latency and allows seamless arbitration (i.e., no dead cycles inserted by the fabric) between the masters
and slaves. The data SCR connects masters to slaves via 128-bit data buses (SCR B) and 64-bit data
buses (SCR A) running at a CPU/3 frequency (CPU/3 is generated from PLL1 controller). Peripherals that
have a 128-bit data bus interface running at this speed can connect directly to the data SCR; other
peripherals require a bridge.
The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly
used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.4).
The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a
CPU/3 frequency (CPU/3 is generated from PLL1 controller). As with the data SCR, some peripherals
require the use of a bridge to interface to the configuration SCR. Note that the data SCR also connects to
the configuration SCR.
Bridges and gaskets are required to perform a variety of functions. For the purpose of this document,
bridges and gaskets can be considered as identical. Within the switch fabric infrastructure, gaskets are
simpler than bridges in that they only modify control signals to convert protocols. Bridges perform a variety
of functions:
•
•
•
Conversion between configuration bus and data bus.
Width conversion between peripheral bus width and SCR bus width.
Frequency conversion between peripheral bus frequency and SCR bus frequency.
For more information on the common bus architecture and its throughput in the C6474 device, see the
TMS320C6474 Common Bus Architecture Throughput application report (literature number SPRAAX6)
and the TMS320C6474 Module Throughput application report (literature number SPRAAW5).
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4.2 Data Switch Fabric Connections
Figure 4-1 shows the DMA switch fabric, including the EDMA3, connection between slaves and masters
through the data switched central resource (SCR). Masters are shown on the right and slaves on the left.
The number of master ports for the EDMA is 2x the number of TPTCs implemented because each TPTC
has a read port and a write port.
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Chip events
Channel
Controller
(CC)
64 channels
SCR B
64-bit
VBUSM
64
64
M
M
S
S
Transfer
Controller
(TC)
x6
x6
64
64
64
64
64
64
Bridge
28
Bridge
12
M
M
M
S
S
S
S
TCP
VCP
3 channels
64
32
Bridge
29
Bridge
11
32
32
32
64
64
Bridge
6
Bridge
7
M
M
M
S
S
S
S
S
S
S
S
EMAC
SCRD
(CFG)
Bridge
10
64
128
Bridge
25
RapidIO
32
32
MCBSPs
(2)
32
32
Bridge
64
RapidIO
CPPI
Bridge
16
Bridge
17
M
32
9
64
C64x+
Megamodule M
Core 1
S
S
ROM
C64x+
Megamodule M
Core 2
64
64
64
DDR2
EMIF
M
C64x+
Megamodule M
Core 3
64
64
Bridge
5
M
M
Bridge
4
128
128
64
64
SCR A
128-bit
VBUSM
128
Bridge
3
S
M
M
M
128
Bridge
2
S
S
Bridge
23
S
S
AIF Read
AIF Write
128
M
128
Bridge
22
Bridge
24
Transfer
Controller
(TC)
x6
x6
128
128
128
C64x+
Megamodule
Core 1
3 channels
128
S
M
M
M
M
S
C64x+
Megamodule
Core 2
S
S
C64x+
Megamodule
Core 3
Figure 4-1. Switched Central Resource Block Diagram
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Not all masters on the C6474 DSP may connect to slaves. Allowed connections are summarized in
Table 4-1 and Table 4-2.
SCR A is the main 128-bit switch fabric, which includes the slave ports of all C64x+ Megamodules. There
are three dedicated, 128-bit TPTC channels for internal memory-to-memory transfers, though the channels
can be used to access anything on SCR B as well. Note that any module accessing these particular
C64x+ Megamodules ports, including the EDMA, must use the global addresses, not the local addresses.
The Antenna Interface (AIF) is connected to the SCR via a special bridge that separates the read and
write interfaces into individual ports. The AIF is fully accessible to TPTC channels 3, 4, and 5, allowing
antenna data to be transferred between the AIF and any DSP memory.
Two of the SCR slave ports are driven by masters from SCR B, allowing data to be transferred between
the device peripherals and L2 memory.
Table 4-1. SCR A Connection Matrix
C64x+
MEGAMODULE
CORE 0
C64x+
MEGAMODULE
CORE 1
C64x+
MEGAMODULE
CORE 2
SCR B (Br4)
SCR B (Br5)
AIF (Br22)
SCR B (Br2)
SCR B (Br3)
TPTC3-RM
TPTC3-WM
TPTC4-RM
TPTC4-WM
TPTC5-RM
TPTC5-WM
N
N
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SCR B is a secondary, 64-bit switch fabric, primarily dedicated to slave peripherals that require servicing
by the TPDMA. Additionally, master peripherals that are sub-128 bit are connected to this switch fabric.
There are two master ports on the SCR that allow masters to send commands to any of the slaves on
SCR A. There are three TPTC channels directly connected to SCR B to service the slave peripherals.
The Ethernet MAC (EMAC) is connected to the switch fabric with a pair of bridges to convert from VBUSP
to VBUSM (Br 6), along with a change in the bus width and frequency (Br 7). The Br 7 handles a majority
of this conversion, with the Br 6 bridge serving as a protocol-conversion gasket.
The RapidIO CPPI port is connected to the switch fabric similarly to the EMAC connection. This enables
RapidIO to use L2 or DDR2 for buffer descriptors. RapidIO is connected directly to the switch fabric and
can master any memory.
The DDR EMIF is also directly connected as a slave, allowing any master full access to the external
memory space.
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Table 4-2. SCR B Connection Matrix
TCP
(Br12)
VCP
(Br11)
SCR D
(Br10)
SCR C
(Br9)
SCR A
(Br2)
SCR A
(Br3)
L3 ROM
DDR2
TPTC0-RM
Y
Y
N
N
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
Y
Y
N
Y
N
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
N
N
N
N
N
N
N
N
N
N
Y
Y
N
N
Y
Y
Y
N
N
Y
Y
Y
TPTC0-WM
TPTC1-RM
TPTC1-WM
TPTC2-RM
TPTC2-WM
EMAC (Br7)
RapidIO
RapidIO CPPI (Br17)
SCR A (Br4)
SCR A (Br5)
C64x+ Megamodule Core 0
C64x+ Megamodule Core 1
C64x+ Megamodule Core 2
The SCR C connection matrix allows for the master to SCR B to access any of the 32-bit slaves on the
switch fabric, plus the boot ROM. The SCR C switch connections between SCR B (Br9) to McBSP0 and
McBSP1 are required.
4.3 Configuration Switch Fabric
Figure 4-2 shows the connections between the C64x+ Megamodules and the configuration switched
central resource (SCR).
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Bridge
20
ETB (3)
S
M
M
S
S
TCP
VCP
3
Semaphore
FSYNC
S
S
CFGC/CIC/
DTF
S
S
S
GPIO
C64x+
Megamodule
Core 0
McBSPs
(2)
M
S
2
S
S
I2C
Bridge
15
M
GPSC
C64x+
Megamodule
Core 1
M
M
S
S
PLL Ctrls
(2)
2
S
SCR D
32-bit
VBUSP
T
i
m
e
r
C64x+
Megamodule
Core 2
S
S
TPMGR
M
S
AIF
6
Timer64s
(6)
RapidIO
S
S
SCR G
32-bit
VBUSP
M
M
M
RapidIO
CPPI
SCR B
(see
Figure 4-1)
S
S
MDIO
M
S
CP-GMAC
Ethernet
CPPI
E
M
A
C
S
Bridge
14
Reserved
S
SGMII
Wrapper
S
S
EMIC
E
D
M
A
3
6
TPTCs
(6)
Bridge
13
S
S
SCR E
32-bit
VBUSP
TPCC
M
Figure 4-2. Configuration Switched Central Resource Block Diagram
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4.4 Priority Allocation
On the C6474 device, each of the masters is assigned a priority via the Priority Allocation Register
(PRI_ALLOC), see Figure 4-3. User-programmable priority registers allow software configuration of the
data traffic through the SCR. The priority is enforced when several masters in the system vie for the same
endpoint. The PRI value of 000b has the highest priority, while the PRI value 111b has the lowest priority.
A chip-level register must be provided to set these values for masters that do not have their own register
internally.
The configuration SCR port on the data SCR is considered a single endpoint meaning priority will be
enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the
configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the
C64x+ Megamodule.
The 4-Byte PRI_ALLOC register address range is 0288 083C - 0288 083F.
31
6
5
3
2
0
Reserved
RapidIO CPPI
RW, +001
EMAC
RW, +00 0000 0000 0000 0000 0000 0000
RW, +001
Figure 4-3. Priority Allocation Register (PRI_ALLOC)
All other master peripherals are not present in the PRI_ALLOC register, as they have their own registers
to program their priorities and do not need a default priority setting. For more information on the default
priority values in these peripheral registers, see the device-compatible peripheral reference guides. TI
recommends that these priority registers be reprogrammed upon initial use.
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5 C64x+ Megamodule
5.1 Megamodule Diagram
The C64x+ Megamodule consists of several components - the C64x+ CPU and associated C64x+
Megamodule core, level-one and level-two memories (L1P, L1D, L2), data trace formatter (DTF),
embedded trace buffer (ETB), the interrupt controller, power-down controller, external memory controller
and a dedicated power/sleep controller (LPSC). The C64x+ Megamodule also provides support for
memory protection and bandwidth management (for resources local to the C64x+ Megamodule).
Figure 5-1 provides a block diagram of the C64x+ Megamodule.
32KB L1P
Memory Controller (PMC) with
Memory Protect/Bandwidth Mgmt
C64x+ DSP Core
Instruction Fetch
L2 Cache/
SRAM
16-/32-bit Instruction Dispatch
1024 KB
Control Registers
In-Circuit Emulation
Boot
Controller
Instruction Decode
Data Path A
Data Path B
A Register File
B Register File
PLLC
LPSC
GPSC
A31 - A16
A15 - A0
B31 - B16
B15 - B0
DMA Switch
Fabric
.M1
.M2
.L1
.S1
xx
xx
.D1
.D2
xx
xx
.S2
.L2
Data Memory Controller (DMC) with
Memory Protect/Bandwidth Mgmt
CFG Switch
Fabric
32KB L1D
Figure 5-1. C64x+ Megamodule Block Diagram
58
C64x+ Megamodule
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5.2 Memory Architecture
The C6474 device contains a 3MB level-2 memory (L2) total, a 32KB level-1 program memory (L1P) per
core, and a 32KB level-1 data memory (L1D) per core. All memory has a unique location in the memory
map and can be directly accessed by any master on the device.
The L1P memory configuration for the device is as follows:
•
•
Region 0 size is 0K bytes (disabled).
Region 1 size is 32K bytes with no wait states.
The L1D memory configuration for the device is as follows:
•
•
Region 0 size is 0K bytes (disabled).
Region 1 size is 32K bytes with no wait states.
After core reset, L1P and L1D cache are configured as all cache by default. The L1P and L1D cache can
be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE)
and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule. L1D is a
two-way set-associative cache while L1P is a direct-mapped cache.
L1P and L1D are configured as memory-mapped SRAM, rather than only unmapped cache. Though
all-cache is the default configuration after device reset, the amount of cache for L1P and L1D may be
programmed to be 0Kb, 4Kb, 8Kb, 16Kb, or 32Kb. All additional L1P or L1D memory space is
memory-mapped SRAM. Figure 5-2 provides the memory mapping of L1P. Figure 5-2 provides the
memory mapping of L1D. L1P SRAM and L1D SRAM begin at the same address regardless of the SRAM
size configured.
L1P Mode Bits
Block Base
Address
000
001
010
011
100
L1P Memory
00E0 0000
1/2
16K bytes
SRAM
3/4
SRAM
7/8
direct
mapped
cache
SRAM
All
SRAM
00E0 4000
8K bytes
direct
mapped
cache
00E0 6000
00E0 7000
00E0 8000
4K bytes
4K bytes
direct
mapped
cache
dm
cache
Figure 5-2. TMS320C6474 L1P Memory Configurations
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L1D Mode Bits
Block Base
Address
000
001
010
011
100
L1D Memory
00F0 0000
1/2
16K bytes
SRAM
3/4
SRAM
7/8
SRAM
All
Cache
SRAM
00F0 4000
8K bytes
Cache
00F0 6000
00F0 7000
00F0 8000
4K bytes
4K bytes
Cache
Cache
Figure 5-3. TMS320C6474 L1D Memory Configurations
Each core has 1024K bytes of local L2 RAM, with up to 256KB configurable as cache. The following figure
provides the possible memory maps for the local L2. The L2 memory is typically shared across the two
unified memory access ports (UMAP0 and UMAP1). The L2 SRAM begins at the same address.
L2 Mode Bits
000
001
010
011
100
L2 Memory
Block Base Address
00800000
768K bytes
75%
SRAM
87.5%
SRAM
93.75%
SRAM
96.875%
SRAM
100%
All
SRAM
008C0000
008E0000
008F0000
008F8000
128K bytes
64K bytes
32K bytes
32K bytes
Cache
25%
Cache
12.5%
Cache
6.25%
Cache
3.125%
Figure 5-4. L2 Memory Configuration 1024KB
All memory on the device has a unique location in the memory (see Section 2.3, Memory Map Summary).
Global addresses that are accessible to all masters in the system are in all memory local to the
processors. Additionally, local memory can be accessed directly by the associated processor through
aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled within the C64x+
Megamodule and allows for common code to be run unmodified on multiple cores. For example, address
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location 0x10800000 is the global base address for C64x+ Megamodule Core 0's L2 memory. C64x+
Megamodule Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other
master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the
three cores as their own L2 base addresses. For C64x+ Megamodule Core 0, as mentioned this is
equivalent to 0x10800000, for C64x+ Megamodule Core 1 this is equivalent to 0x11800000, and for
C64x+ Megamodule Core 2 this is equivalent to 0x12800000. Local addresses should only be used for
shared code or data, allowing a single image to be included in memory. Any code/data targeted to a
specific core, or a memory region allocated during run-time by a particular core should always use the
global address only.
5.3 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and up to 64 pages of L2. The L1D, L1P, and L2
memory controllers in the C64x+ Megamodule are equipped with a set of registers that specify the
permissions for each memory page. For L2, the number of protection pages and their sizes depend on the
L2 configuration of the device, as defined in the previous section. The actual sizes are listed in Table 5-1.
Table 5-1. L2 Memory Protection Page Sizes
C64x+ MEGAMODULE
CORE 0
C64x+ MEGAMODULE
CORE 1
C64x+ MEGAMODULE
CORE 2
ADDRESS RANGE
0x0080 0000 - 0x0087 FFFF
0x0088 0000 - 0x008F FFFF
0x0090 0000 - 0x0097 FFFF
0x0098 0000 - 0x009F FFFF
32 KB
32 KB
N/A
32 KB
32 KB
N/A
32 KB
32 KB
N/A
N/A
N/A
N/A
Table 5-2 shows the memory addresses used to access the L2 memory. Cells in normal font should be
used by the software for memory accesses. The L2 addresses are common between all three cores,
allowing for the same code to be run unmodified on each. Cells in italic (N/A) are not accessible. Memory
protection pages are 1/32nd of the size of each UMAP. The memory protection sizes are constant across
all three cores.
Table 5-2. L2 Memory Address Ranges
C64x+ MEGAMODULE
CORE 0
C64x+ MEGAMODULE
CORE 1
C64x+ MEGAMODULE
CORE 2
ADDRESS RANGE
0x0080 0000 - 0x0087 FFFF
0x0088 0000 - 0x008F FFFF
0x0090 0000 - 0x0097 FFFF
0x0098 0000 - 0x009F FFFF
UMAP 0
UMAP 0
N/A
UMAP 0
UMAP 0
N/A
UMAP 0
UMAP 0
N/A
N/A
N/A
N/A
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. Additionally, a page may be marked as either (or both) locally or globally accessible. A local
access is one initiated by the CPU, while a global access is initiated by a DMA (either IDMA or DMA
access by any C64x+ Megamodule or master peripheral).
The CPU and each of the system masters on the device are all assigned a privilege ID (see Table 5-3).
The AIDx (x=0,1,2,3,4,5) and LOCAL bits of the memory protection page attribute registers specify the
memory page protection scheme as listed in Table 5-4.
Whenever the CPU is the initiator of a memory transaction, the privilege mode (user or supervisor) in
which the CPU is running at that time is carried with those transactions. This includes EDMA3 transfers
that are programmed by the CPU. Other system masters (EMAC, RapidIO) are always in user mode.
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Table 5-3. Available Memory Page Protection Scheme with Privilege ID
PRIVID MODULE
PRIVILEGE MODE
Inherited from CPU(1)
Inherited from CPU(1)
Inherited from CPU(1)
User
DESCRIPTION
C64x+ Megamodule Core 0
C64x+ Megamodule Core 1
C64x+ Megamodule Core 2
EMAC
0
1
2
3
4
User
RapidIO and RapidIO CPPI
(1) Also applies to EDMA3 transfers that are programmed by the CPU.
Table 5-4. Available Memory Page Protection Scheme with AIDx and Local Bits
AIDx BIT
LOCAL BIT
DESCRIPTION
(x=0,1,2,3,4,5)
0
0
0
1
No access to memory page is permitted.
Only direct access by CPU is permitted
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA
accesses initiated by the CPU)
1
1
0
1
All accesses permitted
Faults are handled by software in an interrupt (or exception, programmable within each C64x+
Megamodule interrupt controller) service routine. A CPU or DMA access to a page without the proper
permissions will:
•
•
•
Block the access - reads return zero, writes are voided.
Capture the initiator in a status register - ID, address, and access type are stored.
Signal event to CPU interrupt controller.
The software is responsible for taking corrective action to respond to the event and resetting the error
status in the memory controller.
5.4 Bandwidth Management
When multiple requesters contend for a single C64x+ Megamodule resource, the conflict is solved by
granting access to the highest priority requestor. The following four resources are managed by the
Bandwidth Management control hardware:
•
•
•
•
Level 1 Program (L1P) SRAM/Cache
Level 1 Data (L1D) SRAM/Cache
Level 2 (L2) SRAM/Cache
Memory-mapped registers configuration bus
The priority level for operations initiated within the C64x+ Megamodule; e.g., CPU-initiated transfers,
user-programmed cache coherency operations, and IDMA-initiated transfers, are declared through
registers in the C64x+ Megamodule. The priority level for operations initiated outside the C64x+
Megamodule by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see
Section 4.4. System peripherals with no fields in PRI_ALLOC have their own registers to program their
priorities.
Table 5-5 shows the default priorities of all masters in the device.
62
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Table 5-5. C6474 Default Master Priorities
DEFAULT MASTER PRIORITIES
(0 = Highest priority,
MASTER
PRIORITY CONTROL
7 = Lowest priority)
EDMA3TCx
0
0
QUEPRI.PRIQx (EDMA3 register)
SRIO (Data Access)
PER_SET_CNTL.CBA_TRANS_PRI (SRIO
register)
SRIO (Descriptor Access)
EMAC
1
1
7
PRI_ALLOC.SRIO_CPPI
PRI_ALLOC.EMAC
C64x+ Megamodule (MDMA port)
MDMAARBE.PRI (C64x+ Megamodule
register)
C64x+ Megamodule (CPU Arbitration control
to L2)
1
0
CPUARBU (C64x+ Megamodule register)
C64x+ Megamodule (IDMA channel 1)
IDMA1_COUNT (C64x+ Megamodule
register)
5.5 Power-Down Control
The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The
power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache
control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used
to design systems for lower overall system power requirements. Note that the device does not support
power-down modes for the L2 memory at this time.
5.6 Megamodule Resets
Table 5-6 shows the reset types supported on the device and if the resetting affects the Megamodule
globally or just locally.
Table 5-6. Megamodule Reset (Global or Local)
RESET TYPE
Power-On
Warm
GLOBAL RESET
LOCAL RESET
Y
Y
Y
N
Y
Y
Y
Y
System
CPU
5.7 Megamodule Revision
The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID
Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5
and described in Table 5-7. The C64x+ Megamodule revision is dependant on the silicon revision being
used.
Figure 5-5. Megamodule Revision ID Register (MM_REVID) [Hex Address: 0181 2000h]
31
16 15
0
VERSION
R-3h
REVISION(1)
R-n
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) The C64x+ Megamodule revision is dependent on the silicon revision being used.
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Table 5-7. Megamodule Revision ID Register (MM_REVID) Field Descriptions
BIT
31:16
15:0
FIELD
VALUE
DESCRIPTION
VERSION
REVISION
3H
Version of the C64x+ Megamodule implemented on the device. This field is always read as 3h.
Revision of the C64x+ Megamodule version implemented on the device. The C64x+ Megamodule
revision is dependent on the silicon revision being used.
5.8 C64X+ Megamodule Register Description(s)
In some applications, some specific addresses may need to be read from their physical locations each
time they are accessed (e.g., a status register within FPGA).
The L2 controller offers registers that control whether certain ranges of memory are cacheable and
whether one or more requestors are actually permitted to access these ranges. The registers are referred
to as memory attribute registers (MARs). A list of MARs is provided in Table 5-12.
Table 5-8. Megamodule Interrupt Registers
HEX ADDRESS
0180 0000
ACRONYM
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
-
REGISTER NAME
Event Flag Register 0 (Events [31:0])
0180 0004
Event Flag Register 1
0180 0008
Event Flag Register 2
0180 000C
Event Flag Register 3
0180 0010 - 0180 001C
0180 0020
Reserved
EVTSET0
EVTSET1
EVTSET2
EVTSET3
-
Event Set Register 0 (Events [31:0])
Event Set Register 1
0180 0024
0180 0028
Event Set Register 2
0180 002C
Event Set Register 3
0180 0030 - 0180 003C
0180 0040
Reserved
EVTCLR0
EVTCLR1
EVTCLR2
EVTCLR3
-
Event Clear Register 0 (Events [31:0])
Event Clear Register 1
0180 0044
0180 0048
Event Clear Register 2
0180 004C
Event Clear Register 3
0180 0050 - 0180 007C
0180 0080
Reserved
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
-
Event Mask Register 0 (Events [31:0])
Event Mask Register 1
0180 0084
0180 0088
Event Mask Register 2
0180 008C
Event Mask Register 3
0180 0090 - 0180 009C
0180 00A0
Reserved
MEVFLAG0
MEVFLAG1
MEVFLAG2
MEVFLAG3
-
Masked Event Flag Status Register 0 (Events [31:0])
Masked Event Flag Status Register 1
Masked Event Flag Status Register 2
Masked Event Flag Status Register 3
Reserved
0180 00A4
0180 00A8
0180 00AC
0180 00B0 - 0180 00BC
0180 00C0
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
-
Exception Mask Register 0 (Events [31:0])
Exception Mask Register 1
Exception Mask Register 2
Exception Mask Register 3
Reserved
0180 00C4
0180 00C8
0180 00CC
0180 00D0 - 0180 00DC
0180 00E0
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
Masked Exception Flag Register 0(Events [31:0])
Masked Exception Flag Register 1
Masked Exception Flag Register 2
Masked Exception Flag Register 3
0180 00E4
0180 00E8
0180 00EC
64
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Table 5-8. Megamodule Interrupt Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
0180 00F0 - 0180 00FC
0180 0100
-
Reserved
-
Reserved
0180 0104
INTMUX1
INTMUX2
INTMUX3
-
Interrupt Multiplexer Register 1
Interrupt Multiplexer Register 2
Interrupt Multiplexer Register 3
Reserved
0180 0108
0180 010C
0180 0110 - 0180 013C
0180 0140
AEGMUX0
AEGMUX1
-
Advanced Event Generator Mux Register 0
Advanced Event Generator Mux Register 1
Reserved
0180 0144
0180 0148 - 0180 017C
0180 0180
INTXSTAT
INTXCLER
INTDMASK
-
Interrupt Exception Status Register
Interrupt Exception Clear Register
Dropped Interrupt Mask Register
Reserved
0180 0184
0180 0188
0180 0188 - 0180 01BC
0180 01C0
EVTASRT
-
Event Asserting Register (boot complete register)(1)
0180 01C4 - 0180 FFFF
Reserved
(1) Only bit 4 is used, all other bits are reserved. Bit 4 is write only and has the default 0. After boot is complete, bit 4 is set to 1 and Cores
1 and 2 are released out of reset and start executing their codes.
Table 5-9. Megamodule Power-Down Control Registers
HEX ADDRESS
0181 0000
ACRONYM
PDCCMD
-
REGISTER NAME
Power-Down Controller Command Register
Reserved
0181 0004 - 0181 1FFF
Table 5-10. Megamodule Revision Register
HEX ADDRESS
0181 2000
ACRONYM
REGISTER NAME
MM_REVID
-
Megamodule Revision ID Register
Reserved
0181 2004 - 0181 2FFF
Table 5-11. Megamodule IDMA Registers
HEX ADDRESS
0182 0000
ACRONYM
REGISTER NAME
IDMA0STAT
IDMA Channel 0 Status Register
IDMA Channel 0 Mask Register
IDMA Channel 0 Source Address Register
IDMA Channel 0 Destination Address Register
IDMA Channel 0 Count Register
Reserved
0182 0004
IDMA0MASK
0182 0008
IDMA0SCR
0182 000C
IDMA0DST
0182 0010
IDMA0CNT
0182 0014 - 0182 00FC
0182 0100
-
IDMA1STAT
IDMA Channel 1 Status Register
Reserved
0182 0104
-
0182 0108
IDMA1SRC
IDMA Channel 1 Source Address Register
IDMA Channel 1 Destination Address Register
IDMA Channel 1 Count Register
Reserved
0182 010C
IDMA1DST
0182 0110
IDMA1CNT
0182 0114 - 0182 017C
0182 0180
-
-
-
Reserved
0182 0184 - 0182 01FC
Reserved
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Table 5-12. Megamodule Cache Configuration Registers
HEX ADDRESS
0184 0000
ACRONYM
L2CFG
-
REGISTER NAME
L2 Cache Configuration Register
Reserved
0184 0004 - 0184 001F
0184 0020
L1PCFG
L1PCC
-
L1P Configuration Register
L1P Cache Control Register
Reserved
0184 0024
0184 0028 - 0184 003F
0184 0040
L1DCFG
L1DCC
-
L1D Configuration Register
L1D Cache Control Register
Reserved
0184 0044
0184 0048 - 0184 0FFF
0184 1000 - 0184 104F
0184 1050 - 0184 3FFF
0184 4000
-
See Table 5-15, CPU Megamodule Bandwidth Management Registers
Reserved
-
L2WBAR
L2WWC
-
L2 Writeback Base Address Register - for Block Writebacks
L2 Writeback Word Count Register
Reserved
0184 4004
0184 4008 - 0184 400C
0184 4010
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
L2 Writeback and Invalidate Base Address Register - for Block Writebacks
L2 Writeback and Invalidate Word Count Register
L2 Invalidate Base Address Register
L2 Invalidate Word Count Register
L1P Invalidate Base Address Register
L1P Invalidate Word Count Register
L1D Writeback and Invalidate Base Address Register
L1D Writeback and Invalidate Word Count Register
Reserved
0184 4014
0184 4018
0184 401C
0184 4020
0184 4024
0184 4030
0184 4034
0184 4038
0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D Writeback Base Address Register - for Block Writebacks
L1D Writeback Word Count Register
L1D Invalidate Base Address Register
L1D Invalidate Word Count Register
Reserved
0184 4044
0184 4048
0184 404C
0184 4050 - 0184 4FFF
0184 5000
L2WB
L2WBINV
L2INV
-
L2 Global Writeback Register
0184 5004
L2 Global Writeback and Invalidate Register
L2 Global Invalidate Register
0184 5008
0184 500C - 0184 5024
0184 5028
Reserved
L1PINV
-
L1P Global Invalidate Register
0184 502C - 0184 503C
0184 5040
Reserved
L1DWB
L1DWBINV
L1DINV
-
L1D Global Writeback Register
0184 5044
L1D Global Writeback and Invalidate Register
L1D Global Invalidate Register
0184 5048
0184 504C - 0184 5FFF
0184 6000 - 0184 640F
0184 6400 - 0184 7FFF
0184 8000 - 0184 803C
0184 8040
Reserved
-
See Table 5-13, Megamodule Error Detection Correct Registers
Reserved
-
-
Reserved
MAR16
MAR17
MAR18
-
Controls the Global L2 Locations 1000 0000 - 10FF FFFF
Controls the Global L2 Locations 1100 0000 - 11FF FFFF
Controls the Global L2 Locations 1200 0000 - 12FF FFFF
Reserved
0184 8044
0184 8048
0184 804C - 0184 81FC
0184 8200
MAR128
MAR129
MAR130
Controls DDR2 CE0 Range 8000 0000 - 80FF FFFF
Controls DDR2 CE0 Range 8100 0000 - 81FF FFFF
Controls DDR2 CE0 Range 8200 0000 - 82FF FFFF
0184 8204
0184 8208
66
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Table 5-12. Megamodule Cache Configuration Registers (continued)
HEX ADDRESS
ACRONYM
MAR131
MAR132
MAR133
MAR134
MAR135
MAR136
MAR137
MAR138
MAR139
MAR140
MAR141
MAR142
MAR143
MAR144
MAR145
MAR146
MAR147
MAR148
MAR149
MAR150
MAR151
MAR152
MAR153
MAR154
MAR155
MAR156
MAR157
MAR158
MAR159
-
REGISTER NAME
0184 820C
0184 8210
Controls DDR2 CE0 Range 8300 0000 - 83FF FFFF
Controls DDR2 CE0 Range 8400 0000 - 84FF FFFF
Controls DDR2 CE0 Range 8500 0000 - 85FF FFFF
Controls DDR2 CE0 Range 8600 0000 - 86FF FFFF
Controls DDR2 CE0 Range 8700 0000 - 87FF FFFF
Controls DDR2 CE0 Range 8800 0000 - 88FF FFFF
Controls DDR2 CE0 Range 8900 0000 - 89FF FFFF
Controls DDR2 CE0 Range 8A00 0000 - 8AFF FFFF
Controls DDR2 CE0 Range 8B00 0000 - 8BFF FFFF
Controls DDR2 CE0 Range 8C00 0000 - 8CFF FFFF
Controls DDR2 CE0 Range 8D00 0000 - 8DFF FFFF
Controls DDR2 CE0 Range 8E00 0000 - 8EFF FFFF
Controls DDR2 CE0 Range 8F00 0000 - 8FFF FFFF
Controls DDR2 CE0 Range 9000 0000 - 90FF FFFF
Controls DDR2 CE0 Range 9100 0000 - 91FF FFFF
Controls DDR2 CE0 Range 9200 0000 - 92FF FFFF
Controls DDR2 CE0 Range 9300 0000 - 93FF FFFF
Controls DDR2 CE0 Range 9400 0000 - 94FF FFFF
Controls DDR2 CE0 Range 9500 0000 - 95FF FFFF
Controls DDR2 CE0 Range 9600 0000 - 96FF FFFF
Controls DDR2 CE0 Range 9700 0000 - 97FF FFFF
Controls DDR2 CE0 Range 9800 0000 - 98FF FFFF
Controls DDR2 CE0 Range 9900 0000 - 99FF FFFF
Controls DDR2 CE0 Range 9A00 0000 - 9AFF FFFF
Controls DDR2 CE0 Range 9B00 0000 - 9BFF FFFF
Controls DDR2 CE0 Range 9C00 0000 - 9CFF FFFF
Controls DDR2 CE0 Range 9D00 0000 - 9DFF FFFF
Controls DDR2 CE0 Range 9E00 0000 - 9EFF FFFF
Controls DDR2 CE0 Range 9F00 0000 - 9FFF FFFF
Reserved
0184 8214
0184 8218
0184 821C
0184 8220
0184 8224
0184 8228
0184 822C
0184 8230
0184 8234
0184 8238
0184 823C
0184 8240
0184 8244
0184 8248
0184 824C
0184 8250
0184 8254
0184 8258
0184 825C
0184 8260
0184 8264
0184 8268
0184 826C
0184 8270
0184 8274
0184 8278
0184 827C
0184 8280 - 0184 837C
0184 8380 - 0184 83BC
0184 83C0 - 0184 83FC
-
Reserved
-
Reserved
Table 5-13. Megamodule Error Detection Correct Registers
HEX ADDRESS
0184 6000
ACRONYM
-
REGISTER NAME
Reserved
0184 6004
L2EDSTAT
L2EDCMD
L2EDADDR
L2EDEN0
L2EDEN1
L2EDCPEC
L2EDNPEC
-
L2 Error Detection Status Register
0184 6008
L2 Error Detection Command Register
L2 Error Detection Address Register
0184 600C
0184 6010
L2 Error Detection Enable Map 0 Register
L2 Error Detection Enable Map 1 Register
L2 Error Detection - Correctable Parity Error Count Register
L2 Error Detection - Non-correctable Parity Error Count Register
Reserved
0184 6014
0184 6018
0184 601C
0184 6020 - 0184 6400
0184 6404
L1Pedstat
L1PEDCMD
L1PEDADDR
L1P Error Detection Status Register
0184 6408
L1P Error Detection Command Register
L1P Error Detection Address Register
0184 640C
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Table 5-14. Megamodule L1/L2 Memory Protection Registers
HEX ADDRESS
0184 A000
0184 A004
0184 A008
0184 A00C - 0184 A0FF
0184 A100
0184 A104
0184 A108
0184 A10C
0184 A110
0184 A114
0184 A118 - 0184 A1FF
0184 A200
0184 A204
0184 A208
0184 A20C
0184 A210
0184 A214
0184 A218
0184 A21C
0184 A220
0184 A224
0184 A228
0184 A22C
0184 A230
0184 A234
0184 A238
0184 A23C
0184 A240
0184 A244
0184 A248
0184 A24C
0184 A250
0184 A254
0184 A258
0184 A25C
0184 A260
0184 A264
0184 A268
0184 A26C
0184 A270
0184 A274
0184 A278
0184 A27C
0184 A280
0184 A284
0184 A288
ACRONYM
L2MPFAR
L2MPFSR
L2MPFCR
-
REGISTER NAME
L2 Memory Protection Fault Address Register
L2 Memory Protection Fault Status Register
L2 memory protection Fault Command Register
Reserved
L2MPLKO
L2MPLK1
L2MPLK2
L2MPLK3
L2MPLKCMD
L2MPLKSTAT
-
L2 Memory Protection Lock Key Bits [31:0]
L2 Memory Protection Lock Key Bits [63:32]
L2 Memory Protection Lock Key Bits [95:64]
L2 Memory Protection Lock Key Bits [127:96]
L2 Memory Protection Lock Key Command Register
L2 Memory Protection Lock Key Status Register
Reserved
L2MPPA0
L2MPPA1
L2MPPA2
L2MPPA3
L2MPPA4
L2MPPA5
L2MPPA6
L2MPPA7
L2MPPA8
L2MPPA9
L2MPPA10
L2MPPA11
L2MPPA12
L2MPPA13
L2MPPA14
L2MPPA15
L2MPPA16
L2MPPA17
L2MPPA18
L2MPPA19
L2MPPA20
L2MPPA21
L2MPPA22
L2MPPA23
L2MPPA24
L2MPPA25
L2MPPA26
L2MPPA27
L2MPPA28
L2MPPA29
L2MPPA30
L2MPPA31
L2MPPA32
L2MPPA33
L2MPPA34
L2 Memory Protection Page Attribute Register 0(1)
L2 Memory Protection Page Attribute Register 1
L2 Memory Protection Page Attribute Register 2
L2 Memory Protection Page Attribute Register 3
L2 Memory Protection Page Attribute Register 4
L2 Memory Protection Page Attribute Register 5
L2 Memory Protection Page Attribute Register 6
L2 Memory Protection Page Attribute Register 7
L2 Memory Protection Page Attribute Register 8
L2 Memory Protection Page Attribute Register 9
L2 Memory Protection Page Attribute Register 10
L2 Memory Protection Page Attribute Register 11
L2 Memory Protection Page Attribute Register 12
L2 Memory Protection Page Attribute Register 13
L2 Memory Protection Page Attribute Register 14
L2 Memory Protection Page Attribute Register 15
L2 Memory Protection Page Attribute Register 16
L2 Memory Protection Page Attribute Register 17
L2 Memory Protection Page Attribute Register 18
L2 Memory Protection Page Attribute Register 19
L2 Memory Protection Page Attribute Register 20
L2 Memory Protection Page Attribute Register 21
L2 Memory Protection Page Attribute Register 22
L2 Memory Protection Page Attribute Register 23
L2 Memory Protection Page Attribute Register 24
L2 Memory Protection Page Attribute Register 25
L2 Memory Protection Page Attribute Register 26
L2 Memory Protection Page Attribute Register 27
L2 Memory Protection Page Attribute Register 28
L2 Memory Protection Page Attribute Register 29
L2 Memory Protection Page Attribute Register 30
L2 Memory Protection Page Attribute Register 31
L2 Memory Protection Page Attribute Register 32
L2 Memory Protection Page Attribute Register 33
L2 Memory Protection Page Attribute Register 34
(1) The default value of all L2MPPAn registers is 0x0000 FFFF.
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Table 5-14. Megamodule L1/L2 Memory Protection Registers (continued)
HEX ADDRESS
ACRONYM
L2MPPA35
L2MPPA36
L2MPPA37
L2MPPA38
L2MPPA39
L2MPPA40
L2MPPA41
L2MPPA42
L2MPPA43
L2MPPA44
L2MPPA45
L2MPPA46
L2MPPA47
L2MPPA48
L2MPPA49
L2MPPA50
L2MPPA51
L2MPPA52
L2MPPA53
L2MPPA54
L2MPPA55
L2MPPA56
L2MPPA57
L2MPPA58
L2MPPA59
L2MPPA60
L2MPPA61
L2MPPA62
L2MPPA63
-
REGISTER NAME
0184 A28C
0184 A290
L2 Memory Protection Page Attribute Register 35
L2 Memory Protection Page Attribute Register 36
L2 Memory Protection Page Attribute Register 37
L2 Memory Protection Page Attribute Register 38
L2 Memory Protection Page Attribute Register 39
L2 Memory Protection Page Attribute Register 40
L2 Memory Protection Page Attribute Register 41
L2 Memory Protection Page Attribute Register 42
L2 Memory Protection Page Attribute Register 43
L2 Memory Protection Page Attribute Register 44
L2 Memory Protection Page Attribute Register 45
L2 Memory Protection Page Attribute Register 46
L2 Memory Protection Page Attribute Register 47
L2 Memory Protection Page Attribute Register 48
L2 Memory Protection Page Attribute Register 49
L2 Memory Protection Page Attribute Register 50
L2 Memory Protection Page Attribute Register 51
L2 Memory Protection Page Attribute Register 52
L2 Memory Protection Page Attribute Register 53
L2 Memory Protection Page Attribute Register 54
L2 Memory Protection Page Attribute Register 55
L2 Memory Protection Page Attribute Register 56
L2 Memory Protection Page Attribute Register 57
L2 Memory Protection Page Attribute Register 58
L2 Memory Protection Page Attribute Register 59
L2 Memory Protection Page Attribute Register 60
L2 Memory Protection Page Attribute Register 61
L2 Memory Protection Page Attribute Register 62
L2 Memory Protection Page Attribute Register 63
Reserved
0184 A294
0184 A298
0184 A29C
0184 A2A0
0184 A2A4
0184 A2A8
0184 A2AC
0184 A2B0
0184 A2B4
0184 A2B8
0184 A2BC
0184 A2C0
0184 A2C4
0184 A2C8
0184 A2CC
0184 A2D0
0184 A2D4
0184 A2D8
0184 A2DC
0184 A2E0
0184 A2E4
0184 A2E8
0184 A2EC
0184 A2F0
0184 A2F4
0184 A2F8
0184 A2FC
0184 A300 - 0184 A3FF
0184 A400
L1PMPFAR
L1PMPFSR
L1PMPFCR
-
L1 Program (L1P) Memory Protection Fault Address Register
L1P Memory Protection Fault Status Register
L1P Memory Protection Fault Command Register
Reserved
0184 A404
0184 A408
0184 A40C - 0184 A4FF
0184 A500
L1PMPLK0
L1PMPLK1
L1PMPLK2
L1PMPLK3
L1PMPLKCMD
L1PMPLKSTAT
-
L1P Memory Protection Lock Key Bits [31:0]
L1P Memory Protection Lock Key Bits [63:32]
L1P Memory Protection Lock Key Bits [95:64]
L1P Memory Protection Lock Key Bits [127:96]
L1P Memory Protection Lock Key Command Register
L1P Memory Protection Lock Key Status Register
Reserved
0184 A504
0184 A508
0184 A50C
0184 A510
0184 A514
0184 A518 - 0184 A5FF
0184 A600 - 0184 A63C(2)
0184 A640
-
Reserved
L1PMPPA16
L1PMPPA17
L1PMPPA18
L1P Memory Protection Page Attribute Register 16
L1P Memory Protection Page Attribute Register 17
L1P Memory Protection Page Attribute Register 18
0184 A644
0184 A648
(2) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C64x+
megamodule. These registers are not supported for the C6474 device. The default value after the device reset for registers L1PMPPA16
to L1PMPPA31 is 0x0000 FFFF.
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Table 5-14. Megamodule L1/L2 Memory Protection Registers (continued)
HEX ADDRESS
0184 A64C
ACRONYM
L1PMPPA19
L1PMPPA20
L1PMPPA21
L1PMPPA22
L1PMPPA23
L1PMPPA24
L1PMPPA25
L1PMPPA26
L1PMPPA27
L1PMPPA28
L1PMPPA29
L1PMPPA30
L1PMPPA31
-
REGISTER NAME
L1P Memory Protection Page Attribute Register 19
L1P Memory Protection Page Attribute Register 20
L1P Memory Protection Page Attribute Register 21
L1P Memory Protection Page Attribute Register 22
L1P Memory Protection Page Attribute Register 23
L1P Memory Protection Page Attribute Register 24
L1P Memory Protection Page Attribute Register 25
L1P Memory Protection Page Attribute Register 26
L1P Memory Protection Page Attribute Register 27
L1P Memory Protection Page Attribute Register 28
L1P Memory Protection Page Attribute Register 29
L1P Memory Protection Page Attribute Register 30
L1P Memory Protection Page Attribute Register 31
Reserved
0184 A650
0184 A654
0184 A658
0184 A65C
0184 A660
0184 A664
0184 A668
0184 A66C
0184 A670
0184 A674
0184 A678
0184 A67C
0184 A680 - 0184 ABFF
0184 AC00
L1DMPFAR
L1DMPFSR
L1DMPFCR
-
L1 Data (L1D) Memory Protection Fault Address Register
L1D Memory Protection Fault Status Register
L1D Memory Protection Fault Command Register
Reserved
0184 AC04
0184 AC08
0184 AC0C - 0184 ACFF
0184 AD00
L1DMPLK0
L1DMPLK1
L1DMPLK2
L1DMPLK3
L1DMPLKCMD
L1DMPLKSTAT
-
L1D Memory Protection Lock Key Bits [31:0]
L1D Memory Protection Lock Key Bits [63:32]
L1D Memory Protection Lock Key Bits [95:64]
L1D Memory Protection Lock Key Bits [127:96]
L1D Memory Protection Lock Key Command Register
L1D Memory Protection Lock Key Status Register
Reserved
0184 AD04
0184 AD08
0184 AD0C
0184 AD10
0184 AD14
0184 AD18 - 0184 ADFF
0184 AE00 - 0184 AE3C(3)
0184 AE40
-
Reserved
L1DMPPA16
L1DMPPA17
L1DMPPA18
L1DMPPA19
L1DMPPA20
L1DMPPA21
L1DMPPA22
L1DMPPA23
L1DMPPA24
L1DMPPA25
L1DMPPA26
L1DMPPA27
L1DMPPA28
L1DMPPA29
L1DMPPA30
L1DMPPA31
-
L1D Memory Protection Page Attribute Register 16
L1D Memory Protection Page Attribute Register 17
L1D Memory Protection Page Attribute Register 18
L1D Memory Protection Page Attribute Register 19
L1D Memory Protection Page Attribute Register 20
L1D Memory Protection Page Attribute Register 21
L1D Memory Protection Page Attribute Register 22
L1D Memory Protection Page Attribute Register 23
L1D Memory Protection Page Attribute Register 24
L1D Memory Protection Page Attribute Register 25
L1D Memory Protection Page Attribute Register 26
L1D Memory Protection Page Attribute Register 27
L1D Memory Protection Page Attribute Register 28
L1D Memory Protection Page Attribute Register 29
L1D Memory Protection Page Attribute Register 30
L1D Memory Protection Page Attribute Register 31
Reserved
0184 AE44
0184 AE48
0184 AE4C
0184 AE50
0184 AE54
0184 AE58
0184 AE5C
0184 AE60
0184 AE64
0184 AE68
0184 AE6C
0184 AE70
0184 AE74
0184 AE78
0184 AE7C
0184 AE80 - 0185 FFFF
(3) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C64x+
megamodule. These registers are not supported for the C6474 device. The default value after the device reset for registers L1DMPPA16
to L1DMPPA31 is 0x0000 FFF6.
70
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Table 5-15. CPU Megamodule Bandwidth Management Registers
HEX ADDRESS
ACRONYM
REGISTER NAME
EMC CPU Arbitration Control Register
0182 0200
0182 0204
EMCCPUARBE
EMCIDMAARBE EMC IDMA Arbitration Control Register
0182 0208
EMCSDMAARBE EMC Slave DMA Arbitration Control Register
EMCMDMAARBE EMC Master DMA Arbitration Control Register
0182 020C
0182 0210 - 0182 02FF
0184 1000
-
Reserved
L2DCPUARBU
L2DIDMAARBU
L2D CPU Arbitration Control Register
L2D IDMA Arbitration Control Register
0184 1004
0184 1008
L2DSDMAARBU L2D Slave DMA Arbitration Control Register
0184 100C
L2DUCARBU
-
L2D User Coherence Arbitration Control Register
Reserved
0184 1010 - 0184 103F
0184 1040
L1DCPUARBD
L1DIDMAARBD
L1D CPU Arbitration Control Register
L1D IDMA Arbitration Control Register
0184 1044
0184 1048
L1DSDMAARBD L1D Slave DMA Arbitration Control Register
0184 104C
L1DUCARBD
L1D User Coherence Arbitration Control Register
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6 Device Operating Conditions
Based
on
JESD22-C101C
(Field-Induced
Charged-Device
Model
Test
Method
for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components), the TMS320C6474
device's charged-device model (CDM) sensitivity classification is Class II (200 to <500 V). Specifically,
DDR memory interface and SERDES pins conform to ±200-V level. All other pins conform to ±500 V.
6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless
Otherwise Noted)(1)
CVDD
-0.3 V - 1.35 V
-0.3 V to 1.35 V
(3)
DVDD11
DVDD18
-0.3 V to 2.45 V
VREFSSTL
0.49 * DVDD18 to 0.51 * DVDD18
-0.3 V to 1.35 V
AIF_VDDA11, AIF_VDDD11, AIF_VDDT11
AIF_VDDR18
Supply voltage range(2)
:
-0.3 V to 2.45 V
SGR_VDDA11, SGR_VDDD11, SGR_VDDT11
SGR_VDDR18
-0.3 V to 1.35 V
-0.3 V to 2.45 V
AVDD118, AVDD218
-0.3 V to 2.45 V
VSS Ground
0 V
1.8-V Single-Ended I/Os
DDR2
-0.3 V to DVDD18 + 0.3 V
-0.3 V to 2.45 V
I2C/VCNTL
-0.3 V to 2.45 V
Input voltage (VI) range:
Frame Sync Differential Clocks
-0.3 V to DVDD18 + 0.3 V
SYSCLK, CORECLK, DDR REFCLK, SRIO/EMAC
REFCLK
-0.3 V to 1.35 V
SERDES
-0.3 V to DVDD11 + 0.3 V
-0.3 V to DVDD18 + 0.3 V
-0.3 V to 2.45 V
1.8-V Single-Ended I/Os
DDR2
Output voltage (VO) range:
I2C/VCNTL
-0.3 V to 2.45 V
SERDES
-0.3 V to DVDD11 + 0.3 V
0°C to 100°C(4)
850-MHz and 1-GHz device commercial temperature
1.2-GHz device commercial temperature
1-GHz device extended temperature
1.2-GHz device extended temperature(5)
0°C to 95°C(4)
-40°C to 100°C(4)
-40°C to 95°C(4)
Operating case temperature range, TC:
Storage temperature range, Tstg
:
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) There is no pin named DVDD11 available on the device. DVDD11 represents the AIF_VDDA11, AIF_VDDD11, AIF_VDDT11, SGR_VDDA11
SGR_VDDD11, and SGR_VDDT11 pins.
,
(4) A heatsink is required for proper device operation.
(5) Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.
72
Device Operating Conditions
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6.2 Recommended Operating Conditions(1)(2)
MIN
CVDD - (0.03CVDD
NOM
MAX UNIT
CVDD
Supply core voltage (scalable)(1)
1.1-V supply core I/O voltage
1.8-V supply I/O voltage
)
0.9 - 1.2 CVDD + (0.03CVDD
)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DVDD11
1.045
1.71
1.1
1.155
DVDD18
1.8
1.89
0.51 * DVDD18
1.155
1.155
1.89
VREFSSTL
AIF_VDDA11
AIF_VDDD11
AIF_VDDR18
AIF_VDDT11
DDR2 reference voltage
0.49 * DVDD18
1.045
1.045
1.71
0.5 * DVDD18
AIF SERDES analog supply
AIF SERDES digital supply
AIF SERDES regulator supply
AIF SERDES termination supply
1.1
1.1
1.8
1.1
1.1
1.1
1.8
1.1
1.8
1.8
0
1.045
1.045
1.045
1.71
1.155
1.155
1.155
1.89
SGR_VDDA11 SRIO/SGMII SERDES analog supply
SGR_VDDD11 SRIO/SGMII SERDES digital supply
SGR_VDDR18 SRIO/SGMII SERDES regulator supply
SGR_VDDT11 SRIO/SGMII SERDES termination supply
1.045
1.71
1.155
1.89
AVDD118
AVDD218
VSS
PLL1 analog supply
PLL2 analog supply
1.71
1.89
Ground
0
0
Input voltage at PADP or PADN
Input frequency
0
2
VI
30
625 MHz
2000 mV
VID
Peak-to-peak differential input voltage
250
1.8-V Single
Ended I/Os
0.65 * DVDD18
V
V
VIH
High-level input voltage(3)
Low-level input voltage(3)
I2C/VCNTL,
SmartReflex
0.7 * DVDD18
DDR2 EMIF
VREFSSTL + 0.125
DVDD18 + 0.3
V
V
1.8-V Single
Ended I/Os
0.35 * DVDD18
VIL
DDR2 EMIF
I2C/VCNTL
-0.3
VREFSSTL - 0.1
0.3 * DVDD18
V
V
1.2-GHz device
(commercial
temperature)
0
95
95
1.2-GHz device
(extended
-40
temperature)(4)
TC
Operating case temperature
°C
850-MHz and
1.0-GHz device
(commercial
0
100
100
temperature)
1.0-GHz device
(extended
-40
temperature)
(1) A heatsink and implementation of the SmartReflex solution is required for proper device operation. For more details on SmartReflex, see
Section 7.3.4.
(2) All SERDES I/Os comply with the XAUI Electical Specification, IEEE 802.3ae-2002.
(3) All differential clock inputs comply with the Frame Sync Differential Clocks Electrical Specification, IEEE 1596.3-1996 and all SERDES
I/Os comply with the XAUI Electical Specification, IEEE 802.3ae-2002.
(4) Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.
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Device Operating Conditions
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6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
1.8-V Single Ended
I/Os
IO = IOH
DVDD18 - 0.45
High-level
output voltage
VOH
V
DDR2
1.4
I2C/VCNTL
0.1 * DVdd18
1.8-V Single Ended
I/Os
IO = IOL
0.45
Low-level output
voltage
VOL
V
DDR2
0.4
I2C/VCNTL
IO = 3 mA, pulled up to 1.8 V
No IPD/IPU
0.4
5
-5
-169
49
1.8-V Single Ended
I/Os
Internal pullup
-100
100
-47
μA
μA
Input current
[DC]
(2)
II
Internal pulldown
160
0.1 * DVDD18 V < VI < 0.9 *
I2C/VCNTL
-20
20
-8
DVDD18
V
EMU[18:00],
GPIO[15:0], TIMO[1:0]
SYSCLKOUT, TDO,
CLKR0, CLKX0, DX0,
FSR0, FSX0, CLKR1,
CLKX1, DX1, FSR1,
FSX1
-6
High-level
output current
[DC]
IOH
mA
RESETSTAT,
SMFRAMECLK, MDIO,
MDCLK
-4
DDR2
4
8
EMU[18:00],
GPIO[15:0], TIM[1:0]
SYSCLKOUT, TDO,
CLKR0, CLKX0, DX0,
FSR0, FSX0, CLKR1,
CLKX1, DX1, FSR1,
FSX1
6
Low-level output
current [DC]
IOL
mA
RESETSTAT,
SMFRAMECLK, MDIO,
MDCLK
4
DDR2
-4
Off-state output 1.8-V Single Ended
current [DC] I/Os
(3)
IOZ
-20
20
μA
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
includes input leakage current and off-state (hi-Z) output leakage current.
(3) IOZ applies to output-only pins, indicating off-state (hi-Z) output leakage current.
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7 Peripheral Information and Electrical Specifications
7.1 Parameter Information
Device
DDR2 Output Test Load
Transmission Line
Z0 = 50 W
4 pf
Data Sheet Timing
Reference Point
Device Pin(A)
Device
Output Test Load Excluding DDR2
Transmission Line
Z0 = 50 W
5 pf
A. The data sheet provides timing at the device pin. For output analysis, the transmission line and associated parasitics
(vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending on the trace
length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end product design.
For recommended transmission line lengths, see the appropriate application notes, user's guides, and design guides.
A transmission line delay of 2 ns was used for all output measurements, except the DDR2 which was evaluated using
a 528-ps delay.
B. This figure represents all outputs, except differential or I2C.
Figure 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is for characterization and measurement of AC timing signals. This load
capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1 1.8 V Signal Transition Levels
All input and output timing parameters are referenced to 0.9 V for both "0" and "1" logic levels.
Vref = 0.9 V
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks.
Vref = VIHMIN (or VOHMIN)
Vref = VILMAX (or VOLMAX)
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
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7.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
7.3 Power Supplies
7.3.1 Power-Supply Sequencing
Power supply sequencing must be followed as seen in Figure 7-4.
Table 7-1. Timing Requirements for Power Supply Ramping
(see Figure 7-4)
NO.
PARAMETERS
MIN
MAX UNIT
3
tsu(DVDD18-DVDD11)
th(DVDD11-POR)
Setup Time, DVDD18 and VREFSSTL supply stable before
DVDD11 and CVDD11 supplies stable(1)
Hold time, POR low after CVDD11 and DVDD11 supplies stable(1)
0.5
200
ms
4
100
μs
(1) Stable means that the voltage is valid as per Section 6.2, Recommended Operating Conditions.
DVDD18
3
VREFSSTL
DVDD11
CVDD11
4
POR
Figure 7-4. Power-Supply Timing
For more information on power-supply sequencing, see the TMS320C6474 Hardware Design Guide
application report (literature number SPRAAW7)
7.3.2 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling
capacitors, therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value. As with the selection of any component, verification of capacitor availability over the
product's production lifetime should be considered.
7.3.3 Power-Down Operation
One of the power goals for the C6474 device is to reduce power dissipation due to unused peripherals.
There are different ways to power down peripherals on the C6474 device.
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Some peripherals can be statically powered down at device reset through the device configuration pins
(see Section 3.1, Device Configuration at Device Reset). Once in a static power-down state, the peripheral
is held in reset and its clock is turned off. Peripherals cannot be enabled once they are in a static
power-down state. To take a peripheral out of the static power-down state, a device reset must be
executed with a different configuration pin setting.
After device reset, all peripherals on the C6474 device are in a disabled state and must be enabled by
software before being used. It is possible to enable only the peripherals needed by the application while
keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks
gated. For more information on how to enable peripherals, see Section 3.2, Peripheral Selection After
Device Reset.
Peripherals used for booting, like I2C, are automatically enabled after device reset. It is possible to disable
peripherals used for booting after the boot process is complete. This, too, results in gating of the clock(s)
to the powered-down peripheral. Once a peripheral is powered-down, it must remain powered down until
the next device reset.
The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+
Megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or
the entire C64x+ Megamodule through the power-down controller based on its own execution thread or in
response to an external stimulus from a host or global controller. More information on the power-down
features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide
(literature number SPRU871).
Table 7-2 lists the Power/Sleep Controller (PSC) registers.
Table 7-2. Power/Sleep Controller Registers
HEX ADDRESS
02AC 0000
02AC 0120
02AC 0128
02AC 0200
02AC 0300
02AC 0304
02AC 0308
02AC 030C
02AC 0310
02AC 0314
02AC 0800
02AC 0804
02AC 0808
02AC 080C
02AC 0810
02AC 0814
02AC 0818
02AC 081C
02AC 0820
02AC 0824
02AC 0828
02AC 082C
02AC 0A00
02AC 0A04
02AC 0A08
ACRONYM
PID
REGISTER NAME
Peripheral Revision and Class Information
PTCMD
PTSTAT
PDSTAT
PDCTL0
PDCTL1
PDCTL2
-
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain Status Register
Power Domain Control Register 0 (AlwaysOn)
Power Domain Control Register 1 (Antenna Interface)
Power Domain Control Register 2 (Serial RapidIO)
Reserved
PDCTL4
PDCTL5
-
Power Domain Control Register 4 (TCP)
Power Domain Control Register 5 (VCP)
Reserved
-
Reserved
-
Reserved
MDSTAT3
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
-
Module Status Register 3 (C64x+ Core 0)
Module Status Register 4 (C64x+ Core 1)
Module Status Register 5 (C64x+ Core 2)
Module Status Register 6 (Antenna Interface)
Module Status Register 7 (Serial RapidIO)
Reserved
MDSTAT9
MDSTAT10
MDSTAT11
-
Module Status Register 9 (TCP)
Module Status Register 10 (VCP)
Module Status Register 11 (Never Gated)
Reserved
-
Reserved
-
Reserved
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Table 7-2. Power/Sleep Controller Registers (continued)
HEX ADDRESS
02AC 0A0C
02AC 0A10
02AC 0A14
02AC 0A18
02AC 0A1C
02AC 0A20
02AC 0A24
02AC 0A28
02AC 0A2C
ACRONYM
MDCTL3
MDCTL4
MDCTL5
MDCTL6
MDCTL7
-
REGISTER NAME
Module Control Register 3 (C64x+ Core 0)
Module Control Register 4 (C64x+ Core 1)
Module Control Register 5 (C64x+ Core 2)
Module Control Register 6 (Antenna Interface)
Module Control Register 7 (Serial RapidIO)
Reserved
MDCTL9
MDCTL10
MDCTL11
Module Control Register 9 (TCP)
Module Control Register 10 (VCP)
Module Control Register 11 (Never Gated)
7.3.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor
structures responsible for higher achievable clock rates and increased performance, comes an inevitable
penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently
of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type
and process technology. Higher clock rates also increase dynamic power, the power used when
transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O
activity.
Texas Instruments' SmartReflex™ technology is used to decrease both static and dynamic power
consumption while maintaining the device performance. SmartReflex in the C6474 device is a feature that
allows the core voltage to be optimized based on the process corner of the device. This requires a voltage
regulator for each C6474 device.
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is
required to be implemented whenever the C6474 device is used.
The voltage selection is done using 4 VCNTL pins which are used to select the output voltage of the core
voltage regulator. For complete information on SmartReflex, see the TMS320C6474 Hardware Design
Guide application report (literature number SPRAAW7).
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7.4 Peripheral IDs (PIDs)
The peripheral ID is a unique ID for each peripheral module. It represents the module version details.
Table 7-3 shows the PIDs for each peripheral module.
Table 7-3. C6474 Modules Peripheral IDs
PID
MEMORY MAPPED
ADDRESS
SR NO.
MODULE
EDMA TC0
PG1.2
PG1.3
PG2.0
1
0x02A20000
0x02A28000
0x02A30000
0x02A38000
0x02A40000
0x02A48000
0x02A00000
0x70000000
0x028C0058
0x028D0058
0x02B04034
0x02B04038
0x02910000
0x02920000
0x02930000
0x02940000
0x02950000
0x02960000
0x029A0000
0x02AC0000
0x02B00000
0x02D00000
0x02BC0000
0x02800000
Not used
0x40003300
0x40003300
0x40003300
0x40003300
0x40003300
0x40003300
0x40015300
0x0031031b
0x00020103
0x00020103
0x00000106
0x00000005
0x00010701
0x00010701
0x00010701
0x00010701
0x00010701
0x00010701
0x0001080d
0x44821105
0x44830105
0x44A43102
0x4800200C
0x48010900
Not used
0x40003300
0x40003300
0x40003300
0x40003300
0x40003300
0x40003300
0x40015340
0x0031031b
0x00020103
0x00020103
0x00000106
0x00000005
0x00010701
0x00010701
0x00010701
0x00010701
0x00010701
0x00010701
0x0001080d
0x44821105
0x44830105
0x44A43102
0x4800200C
0x48010900
Not used
0x40003300
0x40003300
0x40003300
0x40003300
0x40003300
0x40003300
0x40015340
0x0031031b
0x00020103
0x00020103
0x00000106
0x00000005
0x00010701
0x00010701
0x00010701
0x00010701
0x00010701
0x00010701
0x0001080d
0x44821105
0x44830105
0x44A43102
0x4800200C
0x48010900
Not used
2
EDMA TC1
EDMA TC2
EDMA TC3
EDMA TC4
EDMA TC5
EDMA CC
DDR2
3
4
5
6
7
8
9
McBSP0
McBSP1
I2C PID1
I2C PID2
Timer64_0
Timer64_1
Timer64_2
Timer64_3
Timer64_4
Timer64_5
PLL CTRL
PSC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
GPIO
SRIO
AIF
FSYNC
-
TCP3
0x02BA0000
0x02C80000
0x02C80010
0X02C81800
0x02C40000
0x02C81000
0x02B40000
0x02B80000
0x00021105
0x000C0A0B
0x000C0A0B
0x00070104
0x002c0100
0x002d0102
0x48020100
0x00011107
0x00021105
0x000C0A0B
0x000C0A0B
0x00070104
0x002C0100
0x002d0102
0x48020100
0x00011107
0x00021105
0x000C0A0B
0x000C0A0B
0x00070104
0x002C0100
0x002d0102
0x48020100
0x00011107
EMAC TX
EMAC RX
MDIO
SGMII
EMAC Control Module
SEM
VCP
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7.5 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two
memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers
(e.g., data movement between external memory and internal memory), performs sorting or subframe
extraction of various data structures, services event driven peripherals such as a McBSP port, and
offloads data transfers from the device CPU.
The EDMA3 includes the following features:
•
Fully orthogonal transfer description
–
–
–
3 transfer dimensions: array (multiple bytes), frame (multiple arrays), and block (multiple frames)
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
•
Flexible transfer definition:
–
–
Increment or FIFO transfer addressing modes
Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
–
Chaining allows multiple transfers to execute with one event
•
256 PaRAM entries
–
–
Used to define transfer context for channels
Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
•
•
64 DMA channels
–
Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
8 Quick DMA (QDMA) channels
–
–
Used for software-driven transfers
Triggered upon writing to a single PaRAM set entry
•
•
•
6 transfer controllers and 6 event queues with programmable system-level priority
Interrupt generation for transfer completion and error conditions
Debug visibility
–
–
Queue watermarking/threshold allows detection of maximum usage of event queues
Error and status recording to facilitate debug
Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 4-1
lists the peripherals that can be accessed by the transfer controllers.
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7.5.1 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move
data between system memories. DMA channels can be triggered by synchronization events generated by
system peripherals. Table 7-4 lists the source of the synchronization event associated with each of the
DMA channels. The association of each synchronization event and DMA channel is fixed and cannot be
reprogrammed. Additional events are available to the EDMA3 via an external interrupt controller. For more
details on Chip Interrupt Controller 3 (CIC3), see Section 7.6.2.
Table 7-4. EDMA3 Channel Synchronization Events(1)
EVENT CHANNEL
EVENT
TINT0L
EVENT DESCRIPTION
0
Timer Interrupt Low
Timer Interrupt High
Timer Interrupt Low
Timer Interrupt High
Timer Interrupt Low
Timer Interrupt High
1
TINT0H
2
TINT1L
3
TINT1H
4
TINT2L
5
TINT2H
6
CIC3_EVT0
CIC3_EVT1
CIC3_EVT2
CIC3_EVT3
CIC3_EVT4
CIC3_EVT5
XEVT0
CIC_EVT_o [0] from Chip Interrupt Controller
CIC_EVT_o [1] from Chip Interrupt Controller
CIC_EVT_o [2] from Chip Interrupt Controller
CIC_EVT_o [3] from Chip Interrupt Controller
CIC_EVT_o [4] from Chip Interrupt Controller
CIC_EVT_o [5] from Chip Interrupt Controller
McBSP 0 Transmit Event
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
REVT0
McBSP 0 Receive Event
XEVT1
McBSP 1 Transmit Event
REVT1
McBSP 1Receive Event
FSEVT4
FSEVT5
FSEVT6
FSEVT7
FSEVT8
FSEVT9
FSEVT10
FSEVT11
FSEVT12
FSEVT13
CIC3_EVT6
CIC3_EVT7
VCPREVT
VCPXEVT
TCPREVT
TCPXEVT
SEMINT0
SEMINT1
SEMINT2
-
Frame Synchronization Event 4
Frame Synchronization Event 5
Frame Synchronization Event 6
Frame Synchronization Event 7
Frame Synchronization Event 8
Frame Synchronization Event 9
Frame Synchronization Event 10
Frame Synchronization Event 11
Frame Synchronization Event 12
Frame Synchronization Event 13
CIC_EVT_o [6] from Chip Interrupt Controller
CIC_EVT_o [7] from Chip Interrupt Controller
VCP Receive Event
VCP Transmit Event
TCP Receive Event
TCP Transmit Event
Semaphore Interrupt 0
Semaphore Interrupt 1
Semaphore Interrupt 2
Reserved
AIF_EVT0
AIF_EVT1
AIF CPU Interrupt 0
AIF CPU Interrupt 1
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the manual event set or transfer
completion events.
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Table 7-4. EDMA3 Channel Synchronization Events(1) (continued)
EVENT CHANNEL
EVENT
AIF_EVT2
AIF_EVT3
AIF_PSEVT1
AIF_PSEVT3
AIF_PSEVT5
CIC3_EVT8
IREVT
EVENT DESCRIPTION
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
AIF CPU Interrupt 2
AIF CPU Interrupt 3
Packet Switched Transfer Event 1
Packet Switched Transfer Event 3
Packet Switched Transfer Event 5
CIC_EVT_o [8] from Chip Interrupt Controller
I2C Receive Event
IXEVT
I2C Transmit Event
CIC3_EVT9
CIC3_EVT10
CIC3_EVT11
CIC3_EVT12
CIC3_EVT13
CIC3_EVT14
CIC3_EVT15
GPINT5
CIC_EVT_o [9] from Chip Interrupt Controller
CIC_EVT_o [10] from Chip Interrupt Controller
CIC_EVT_o [11] from Chip Interrupt Controller
CIC_EVT_o [12 from Chip Interrupt Controller
CIC_EVT_o [13] from Chip Interrupt Controller
CIC_EVT_o [14] from Chip Interrupt Controller
CIC_EVT_o [15] from Chip Interrupt Controller
GPIO Event 5
GPINT6
GPIO Event 6
GPINT7
GPIO Event 7
GPINT8
GPIO Event 8
GPINT9
GPIO Event 9
GPINT10
GPIO Event 10
GPINT11
GPIO Event 11
GPINT12
GPIO Event 12
GPINT13
GPIO Event 13
GPINT14
GPIO Event 14
GPINT15
GPIO Event 15
7.5.2 EDMA3 Peripheral Register Description(s)
Table 7-5. EDMA3 Registers
HEX ADDRESS
02A0 0000
ACRONYM
PID
REGISTER NAME
Peripheral ID Register
02A0 0004
CCCFG
EDMA3CC Configuration Register
Reserved
02A0 0008 - 02A0 00FC
02A0 0100
-
DCHMAP0
DCHMAP1
DCHMAP2
DCHMAP3
DCHMAP4
DCHMAP5
DCHMAP6
DCHMAP7
DCHMAP8
DCHMAP9
DCHMAP10
DCHMAP11
DCHMAP12
DMA Channel 0 Mapping Register
DMA Channel 1 Mapping Register
DMA Channel 2 Mapping Register
DMA Channel 3 Mapping Register
DMA Channel 4 Mapping Register
DMA Channel 5 Mapping Register
DMA Channel 6 Mapping Register
DMA Channel 7 Mapping Register
DMA Channel 8 Mapping Register
DMA Channel 9 Mapping Register
DMA Channel 10 Mapping Register
DMA Channel 11 Mapping Register
DMA Channel 12 Mapping Register
02A0 0104
02A0 0108
02A0 010C
02A0 0110
02A0 0114
02A0 0118
02A0 011C
02A0 0120
02A0 0124
02A0 0128
02A0 012C
02A0 0130
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 0134
02A0 0138
02A0 013C
02A0 0140
02A0 0144
02A0 0148
02A0 014C
02A0 0150
02A0 0154
02A0 0158
02A0 015C
02A0 0160
02A0 0164
02A0 0168
02A0 016C
02A0 0170
02A0 0174
02A0 0178
02A0 017C
02A0 0180
02A0 0184
02A0 0188
02A0 018C
02A0 0190
02A0 0194
02A0 0198
02A0 019C
02A0 01A0
02A0 01A4
02A0 01A8
02A0 01AC
02A0 01B0
02A0 01B4
02A0 01B8
02A0 01BC
02A0 01C0
02A0 01C4
02A0 01C8
02A0 01CC
02A0 01D0
02A0 01D4
02A0 01D8
02A0 01DC
02A0 01E0
02A0 01E4
02A0 01E8
02A0 01EC
DCHMAP13
DCHMAP14
DCHMAP15
DCHMAP16
DCHMAP17
DCHMAP18
DCHMAP19
DCHMAP20
DCHMAP21
DCHMAP22
DCHMAP23
DCHMAP24
DCHMAP25
DCHMAP26
DCHMAP27
DCHMAP28
DCHMAP29
DCHMAP30
DCHMAP31
DCHMAP32
DCHMAP33
DCHMAP34
DCHMAP35
DCHMAP36
DCHMAP37
DCHMAP38
DCHMAP39
DCHMAP40
DCHMAP41
DCHMAP42
DCHMAP43
DCHMAP44
DCHMAP45
DCHMAP46
DCHMAP47
DCHMAP48
DCHMAP49
DCHMAP50
DCHMAP51
DCHMAP52
DCHMAP53
DCHMAP54
DCHMAP55
DCHMAP56
DCHMAP57
DCHMAP58
DCHMAP59
DMA Channel 13 Mapping Register
DMA Channel 14 Mapping Register
DMA Channel 15 Mapping Register
DMA Channel 16 Mapping Register
DMA Channel 17 Mapping Register
DMA Channel 18 Mapping Register
DMA Channel 19 Mapping Register
DMA Channel 20 Mapping Register
DMA Channel 21 Mapping Register
DMA Channel 22 Mapping Register
DMA Channel 23 Mapping Register
DMA Channel 24 Mapping Register
DMA Channel 25 Mapping Register
DMA Channel 26 Mapping Register
DMA Channel 27 Mapping Register
DMA Channel 28 Mapping Register
DMA Channel 29 Mapping Register
DMA Channel 30 Mapping Register
DMA Channel 31 Mapping Register
DMA Channel 32 Mapping Register
DMA Channel 33 Mapping Register
DMA Channel 34 Mapping Register
DMA Channel 35 Mapping Register
DMA Channel 36 Mapping Register
DMA Channel 37 Mapping Register
DMA Channel 38 Mapping Register
DMA Channel 39 Mapping Register
DMA Channel 40 Mapping Register
DMA Channel 41 Mapping Register
DMA Channel 42 Mapping Register
DMA Channel 43 Mapping Register
DMA Channel 44 Mapping Register
DMA Channel 45 Mapping Register
DMA Channel 46 Mapping Register
DMA Channel 47 Mapping Register
DMA Channel 48 Mapping Register
DMA Channel 49 Mapping Register
DMA Channel 50 Mapping Register
DMA Channel 51 Mapping Register
DMA Channel 52 Mapping Register
DMA Channel 53 Mapping Register
DMA Channel 54 Mapping Register
DMA Channel 55 Mapping Register
DMA Channel 56 Mapping Register
DMA Channel 57 Mapping Register
DMA Channel 58 Mapping Register
DMA Channel 59 Mapping Register
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
02A0 01F0
ACRONYM
REGISTER NAME
DCHMAP60
DCHMAP61
DCHMAP62
DCHMAP63
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
-
DMA Channel 60 Mapping Register
DMA Channel 61 Mapping Register
DMA Channel 62 Mapping Register
DMA Channel 63 Mapping Register
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
Reserved
02A0 01F4
02A0 01F8
02A0 01FC
02A0 0200
02A0 0204
02A0 0208
02A0 020C
02A0 0210
02A0 0214
02A0 0218
02A0 021C
02A0 0220 - 02A0 023C
02A0 0240
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
DMAQNUM4
DMAQNUM5
DMAQNUM6
DMAQNUM7
QDMAQNUM
-
DMA Queue Number Register 0
DMA Queue Number Register 1
DMA Queue Number Register 2
DMA Queue Number Register 3
DMA Queue Number Register 4
DMA Queue Number Register 5
DMA Queue Number Register 6
DMA Queue Number Register 7
QDMA Queue Number Register
02A0 0244
02A0 0248
02A0 024C
02A0 0250
02A0 0254
02A0 0258
02A0 025C
02A0 0260
02A0 0264 - 02A0 027C
02A0 0280
Reserved
QUETCMAP
QUEPRI
-
Queue to TC Mapping Register
02A0 0284
Queue Priority Register
02A0 0288 - 02A0 02FC
02A0 0300
Reserved
EMR
Event Missed Register
02A0 0304
EMRH
Event Missed Register High
02A0 0308
EMCR
Event Missed Clear Register
02A0 030C
02A0 0310
EMCRH
Event Missed Clear Register High
QDMA Event Missed Register
QEMR
02A0 0314
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
02A0 0318
CCERR
02A0 031C
02A0 0320
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
02A0 0324 - 02A0 033C
02A0 0340
-
Reserved
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register High for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register High for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register High for Region 2
DMA Region Access Enable Register for Region 3
DMA Region Access Enable Register High for Region 3
DMA Region Access Enable Register for Region 4
DMA Region Access Enable Register High for Region 4
DMA Region Access Enable Register for Region 5
02A0 0344
DRAEH0
DRAE1
02A0 0348
02A0 034C
02A0 0350
DRAEH1
DRAE2
02A0 0354
DRAEH2
DRAE3
02A0 0358
02A0 035C
02A0 0360
DRAEH3
DRAE4
02A0 0364
DRAEH4
DRAE5
02A0 0368
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SPRS552H–OCTOBER 2008–REVISED APRIL 2011
Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 036C
02A0 0370
02A0 0374
02A0 0378
02A0 037C
02A0 0380
02A0 0384
02A0 0388
02A0 038C
02A0 0390
02A0 0394
02A0 0398
02A0 039C
02A0 0400
02A0 0404
02A0 0408
02A0 040C
02A0 0410
02A0 0414
02A0 0418
02A0 041C
02A0 0420
02A0 0424
02A0 0428
02A0 042C
02A0 0430
02A0 0434
02A0 0438
02A0 043C
02A0 0440
02A0 0444
02A0 0448
02A0 044C
02A0 0450
02A0 0454
02A0 0458
02A0 045C
02A0 0460
02A0 0464
02A0 0468
02A0 046C
02A0 0470
02A0 0474
02A0 0478
02A0 047C
02A0 0480
02A0 0484
DRAEH5
DRAE6
DRAEH6
DRAE7
DRAEH7
QRAE0
QRAE1
QRAE2
QRAE3
QRAE4
QRAE5
QRAE6
QRAE7
Q0E0
DMA Region Access Enable Register High for Region 5
DMA Region Access Enable Register for Region 6
DMA Region Access Enable Register High for Region 6
DMA Region Access Enable Register for Region 7
DMA Region Access Enable Register High for Region 7
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 4
QDMA Region Access Enable Register for Region 5
QDMA Region Access Enable Register for Region 6
QDMA Region Access Enable Register for Region 7
Event Queue 0 Entry Register 0
Q0E1
Event Queue 0 Entry Register 1
Q0E2
Event Queue 0 Entry Register 2
Q0E3
Event Queue 0 Entry Register 3
Q0E4
Event Queue 0 Entry Register 4
Q0E5
Event Queue 0 Entry Register 5
Q0E6
Event Queue 0 Entry Register 6
Q0E7
Event Queue 0 Entry Register 7
Q0E8
Event Queue 0 Entry Register 8
Q0E9
Event Queue 0 Entry Register 9
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Q1E0
Event Queue 0 Entry Register 10
Event Queue 0 Entry Register 11
Event Queue 0 Entry Register 12
Event Queue 0 Entry Register 13
Event Queue 0 Entry Register 14
Event Queue 0 Entry Register 15
Event Queue 1 Entry Register 0
Q1E1
Event Queue 1 Entry Register 1
Q1E2
Event Queue 1 Entry Register 2
Q1E3
Event Queue 1 Entry Register 3
Q1E4
Event Queue 1 Entry Register 4
Q1E5
Event Queue 1 Entry Register 5
Q1E6
Event Queue 1 Entry Register 6
Q1E7
Event Queue 1 Entry Register 7
Q1E8
Event Queue 1 Entry Register 8
Q1E9
Event Queue 1 Entry Register 9
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
Q2E0
Event Queue 1 Entry Register 10
Event Queue 1 Entry Register 11
Event Queue 1 Entry Register 12
Event Queue 1 Entry Register 13
Event Queue 1 Entry Register 14
Event Queue 1 Entry Register 15
Event Queue 2 Entry Register 0
Q2E1
Event Queue 2 Entry Register 1
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
02A0 0488
02A0 048C
02A0 0490
02A0 0494
02A0 0498
02A0 049C
02A0 04A0
02A0 04A4
02A0 04A8
02A0 04AC
02A0 04B0
02A0 04B4
02A0 04B8
02A0 04BC
02A0 04C0
02A0 04C4
02A0 04C8
02A0 04CC
02A0 04D0
02A0 04D4
02A0 04D8
02A0 04DC
02A0 04E0
02A0 04E4
02A0 04E8
02A0 04EC
02A0 04F0
02A0 04F4
02A0 04F8
02A0 04FC
02A0 0500
02A0 0504
02A0 0508
02A0 050C
02A0 0510
02A0 0514
02A0 0518
02A0 051C
02A0 0520
02A0 0524
02A0 0528
02A0 052C
02A0 0530
02A0 0534
02A0 0538
02A0 053C
02A0 0540
ACRONYM
REGISTER NAME
Q2E2
Q2E3
Q2E4
Q2E5
Q2E6
Q2E7
Q2E8
Q2E9
Q2E10
Q2E11
Q2E12
Q2E13
Q2E14
Q2E15
Q3E0
Q3E1
Q3E2
Q3E3
Q3E4
Q3E5
Q3E6
Q3E7
Q3E8
Q3E9
Q3E10
Q3E11
Q3E12
Q3E13
Q3E14
Q3E15
Q4E0
Q4E1
Q4E2
Q4E3
Q4E4
Q4E5
Q4E6
Q4E7
Q4E8
Q4E9
Q4E10
Q4E11
Q4E12
Q4E13
Q4E14
Q4E15
Q5E0
Event Queue 2 Entry Register 2
Event Queue 2 Entry Register 3
Event Queue 2 Entry Register 4
Event Queue 2 Entry Register 5
Event Queue 2 Entry Register 6
Event Queue 2 Entry Register 7
Event Queue 2 Entry Register 8
Event Queue 2 Entry Register 9
Event Queue 2 Entry Register 10
Event Queue 2 Entry Register 11
Event Queue 2 Entry Register 12
Event Queue 2 Entry Register 13
Event Queue 2 Entry Register 14
Event Queue 2 Entry Register 15
Event Queue 3 Entry Register 0
Event Queue 3 Entry Register 1
Event Queue 3 Entry Register 2
Event Queue 3 Entry Register 3
Event Queue 3 Entry Register 4
Event Queue 3 Entry Register 5
Event Queue 3 Entry Register 6
Event Queue 3 Entry Register 7
Event Queue 3 Entry Register 8
Event Queue 3 Entry Register 9
Event Queue 3 Entry Register 10
Event Queue 3 Entry Register 11
Event Queue 3 Entry Register 12
Event Queue 3 Entry Register 13
Event Queue 3 Entry Register 14
Event Queue 3 Entry Register 15
Event Queue 4 Entry Register 0
Event Queue 4 Entry Register 1
Event Queue 4 Entry Register 2
Event Queue 4 Entry Register 3
Event Queue 4 Entry Register 4
Event Queue 4 Entry Register 5
Event Queue 4 Entry Register 6
Event Queue 4 Entry Register 7
Event Queue 4 Entry Register 8
Event Queue 4 Entry Register 9
Event Queue 4 Entry Register 10
Event Queue 4 Entry Register 11
Event Queue 4 Entry Register 12
Event Queue 4 Entry Register 13
Event Queue 4 Entry Register 14
Event Queue 4 Entry Register 15
Event Queue 5 Entry Register 0
86
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SPRS552H–OCTOBER 2008–REVISED APRIL 2011
Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 0544
02A0 0548
Q5E1
Q5E2
Event Queue 5 Entry Register 1
Event Queue 5 Entry Register 2
Event Queue 5 Entry Register 3
Event Queue 5 Entry Register 4
Event Queue 5 Entry Register 5
Event Queue 5 Entry Register 6
Event Queue 5 Entry Register 7
Event Queue 5 Entry Register 8
Event Queue 5 Entry Register 9
Event Queue 5 Entry Register 10
Event Queue 5 Entry Register 11
Event Queue 5 Entry Register 12
Event Queue 5 Entry Register 13
Event Queue 5 Entry Register 14
Event Queue 5 Entry Register 15
Reserved
02A0 054C
Q5E3
02A0 0550
Q5E4
02A0 0554
Q5E5
02A0 0558
Q5E6
02A0 055C
Q5E7
02A0 0560
Q5E8
02A0 0564
Q5E9
02A0 0568
Q5E10
Q5E11
Q5E12
Q5E13
Q5E14
Q5E15
-
02A0 056C
02A0 0570
02A0 0574
02A0 0578
02A0 057C
02A0 0580 - 02A0 05FC
02A0 0600
QSTAT0
QSTAT1
QSTAT2
QSTAT3
QSTAT4
QSTAT5
-
Queue Status Register 0
02A0 0604
Queue Status Register 1
02A0 0608
Queue Status Register 2
02A0 060C
Queue Status Register 3
02A0 0610
Queue Status Register 4
02A0 0614
Queue Status Register 5
02A0 0618 - 02A0 061C
02A0 0620
Reserved
QWMTHRA
QWMTHRB
-
Queue Watermark Threshold A Register
Queue Watermark Threshold B Register
Reserved
02A0 0624
02A0 0628 - 02A0 063C
02A0 0640
CCSTAT
-
EDMA3CC Status Register
02A0 0644 - 02A0 06FC
02A0 0700 - 02A0 07FC
02A0 0800
Reserved
-
Reserved
MPFAR
MPFSR
MPFCR
MPPA0
MPPA1
MPPA2
MPPA3
MPPA4
MPPA5
MPPA6
MPPA7
-
Memory Protection Fault Address Register
Memory Protection Fault Status Register
Memory Protection Fault Command Register
Memory Protection Page Attribute Register 0
Memory Protection Page Attribute Register 1
Memory Protection Page Attribute Register 2
Memory Protection Page Attribute Register 3
Memory Protection Page Attribute Register 4
Memory Protection Page Attribute Register 5
Memory Protection Page Attribute Register 6
Memory Protection Page Attribute Register 7
Reserved
02A0 0804
02A0 0808
02A0 080C
02A0 0810
02A0 0814
02A0 0818
02A0 081C
02A0 0820
02A0 0824
02A0 0828
02A0 082C - 02A0 0FFC
02A0 1000
ER
Event Register
02A0 1004
ERH
Event Register High
02A0 1008
ECR
Event Clear Register
02A0 100C
ECRH
ESR
Event Clear Register High
02A0 1010
Event Set Register
02A0 1014
ESRH
Event Set Register High
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
02A0 1018
ACRONYM
REGISTER NAME
CER
CERH
EER
Chained Event Register
Chained Event Register High
Event Enable Register
02A0 101C
02A0 1020
02A0 1024
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
02A0 1028
02A0 102C
02A0 1030
02A0 1034
02A0 1038
02A0 103C
02A0 1040
SERH
SECR
SECRH
-
02A0 1044
02A0 1048 - 02A0 104C
02A0 1050
IER
Interrupt Enable Register
Interrupt Enable High Register
Interrupt Enable Clear Register
Interrupt Enable Clear High Register
Interrupt Enable Set Register
Interrupt Enable Set High Register
Interrupt Pending Register
Interrupt Pending High Register
Interrupt Clear Register
02A0 1054
IERH
IECR
IECRH
IESR
IESRH
IPR
02A0 1058
02A0 105C
02A0 1060
02A0 1064
02A0 1068
02A0 106C
02A0 1070
IPRH
ICR
02A0 1074
ICRH
IEVAL
-
Interrupt Clear High Register
Interrupt Evaluate Register
Reserved
02A0 1078
02A0 107C
02A0 1080
QER
QDMA Event Register
02A0 1084
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 1088
02A0 108C
02A0 1090
02A0 1094
02A0 1098 - 02A0 1FFF
Shadow Region 0 Channel Registers
Event Register
02A0 2000
02A0 2004
02A0 2008
02A0 200C
02A0 2010
02A0 2014
02A0 2018
02A0 201C
02A0 2020
02A0 2024
02A0 2028
02A0 202C
02A0 2030
02A0 2034
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
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SPRS552H–OCTOBER 2008–REVISED APRIL 2011
Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 2038
02A0 203C
02A0 2040
SER
SERH
SECR
SECRH
-
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
02A0 2044
02A0 2048 - 02A0 204C
02A0 2050
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
02A0 2054
IERH
IECR
IECRH
IESR
IESRH
IPR
02A0 2058
02A0 205C
02A0 2060
02A0 2064
02A0 2068
02A0 206C
02A0 2070
IPRH
ICR
02A0 2074
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
02A0 2078
02A0 207C
02A0 2080
QER
QDMA Event Register
02A0 2084
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 2088
02A0 208C
02A0 2090
02A0 2094
02A0 2098 - 02A0 21FF
Shadow Region 1 Channel Registers
Event Register
02A0 2200
02A0 2204
02A0 2208
02A0 220C
02A0 2210
02A0 2214
02A0 2218
02A0 221C
02A0 2220
02A0 2224
02A0 2228
02A0 222C
02A0 2230
02A0 2234
02A0 2238
02A0 223C
02A0 2240
02A0 2244
02A0 2248 - 02A0 224C
02A0 2250
02A0 2254
02A0 2258
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
IERH
IECR
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
02A0 225C
02A0 2260
ACRONYM
REGISTER NAME
IECRH
IESR
IESRH
IPR
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
02A0 2264
02A0 2268
02A0 226C
02A0 2270
IPRH
ICR
02A0 2274
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
02A0 2278
02A0 227C
02A0 2280
QER
QDMA Event Register
02A0 2284
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 2288
02A0 228C
02A0 2290
02A0 2294
02A0 2298 - 02A0 23FF
Shadow Region 2 Channel Registers
Event Register
02A0 2400
02A0 2404
02A0 2408
02A0 240C
02A0 2410
02A0 2414
02A0 2418
02A0 241C
02A0 2420
02A0 2424
02A0 2428
02A0 242C
02A0 2430
02A0 2434
02A0 2438
02A0 243C
02A0 2440
02A0 2444
02A0 2448 - 02A0 244C
02A0 2450
02A0 2454
02A0 2458
02A0 245C
02A0 2460
02A0 2464
02A0 2468
02A0 246C
02A0 2470
02A0 2474
02A0 2478
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
IERH
IECR
IECRH
IESR
IESRH
IPR
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IPRH
ICR
ICRH
IEVAL
Interrupt Clear Register High
Interrupt Evaluate Register
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 247C
02A0 2480
-
Reserved
QER
QDMA Event Register
02A0 2484
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 2488
02A0 248C
02A0 2490
02A0 2494
02A0 2498 - 02A0 25FF
Shadow Region 3 Channel Registers
Event Register
02A0 2600
02A0 2604
02A0 2608
02A0 260C
02A0 2610
02A0 2614
02A0 2618
02A0 261C
02A0 2620
02A0 2624
02A0 2628
02A0 262C
02A0 2630
02A0 2634
02A0 2638
02A0 263C
02A0 2640
02A0 2644
02A0 2648 - 02A0 264C
02A0 2650
02A0 2654
02A0 2658
02A0 265C
02A0 2660
02A0 2664
02A0 2668
02A0 266C
02A0 2670
02A0 2674
02A0 2678
02A0 267C
02A0 2680
02A0 2684
02A0 2688
02A0 268C
02A0 2690
02A0 2694
02A0 2698 - 02A0 27FF
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
Shadow Region 4 Channel Registers
Event Register
02A0 2800
02A0 2804
02A0 2808
02A0 280C
02A0 2810
02A0 2814
02A0 2818
02A0 281C
02A0 2820
02A0 2824
02A0 2828
02A0 282C
02A0 2830
02A0 2834
02A0 2838
02A0 283C
02A0 2840
02A0 2844
02A0 2848 - 02A0 284C
02A0 2850
02A0 2854
02A0 2858
02A0 285C
02A0 2860
02A0 2864
02A0 2868
02A0 286C
02A0 2870
02A0 2874
02A0 2878
02A0 287C
02A0 2880
02A0 2884
02A0 2888
02A0 288C
02A0 2890
02A0 2894
02A0 2898 - 02A0 29FF
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
IERH
IECR
IECRH
IESR
IESRH
IPR
IPRH
ICR
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
QER
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
Shadow Region 5 Channel Registers
Event Register
02A0 2A00
02A0 2A04
02A0 2A08
02A0 2A0C
02A0 2A10
02A0 2A14
02A0 2A18
ER
ERH
ECR
ECRH
ESR
Event Register High
Event Clear Register
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 2A1C
02A0 2A20
CERH
EER
Chained Event Register Hig
Event Enable Register
02A0 2A24
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
02A0 2A28
02A0 2A2C
02A0 2A30
02A0 2A34
02A0 2A38
02A0 2A3C
02A0 2A40
SERH
SECR
SECRH
-
02A0 2A44
02A0 2A48 - 02A0 2A4C
02A0 2A50
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
02A0 2A54
IERH
IECR
IECRH
IESR
IESRH
IPR
02A0 2A58
02A0 2A5C
02A0 2A60
02A0 2A64
02A0 2A68
02A0 2A6C
02A0 2A70
IPRH
ICR
02A0 2A74
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
02A0 2A78
02A0 2A7C
02A0 2A80
QER
QDMA Event Register
02A0 2A84
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 2A88
02A0 2A8C
02A0 2A90
02A0 2A94
02A0 2A98 - 02A0 2BFF
Shadow Region 6 Channel Registers
Event Register
02A0 2C00
02A0 2C04
02A0 2C08
02A0 2C0C
02A0 2C10
02A0 2C14
02A0 2C18
02A0 2C1C
02A0 2C20
02A0 2C24
02A0 2C28
02A0 2C2C
02A0 2C30
02A0 2C34
02A0 2C38
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
02A0 2C3C
ACRONYM
REGISTER NAME
SERH
SECR
SECRH
-
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
02A0 2C40
02A0 2C44
02A0 2C48 - 02A0 2C4C
02A0 2C50
IER
Interrupt Enable Register
02A0 2C54
IERH
IECR
IECRH
IESR
IESRH
IPR
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
02A0 2C58
02A0 2C5C
02A0 2C60
02A0 2C64
02A0 2C68
02A0 2C6C
IPRH
ICR
02A0 2C70
02A0 2C74
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
02A0 2C78
02A0 2C7C
02A0 2C80
QER
QDMA Event Register
02A0 2C84
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 2C88
02A0 2C8C
02A0 2C90
02A0 2C94
02A0 2C98 - 02A0 2DFF
Shadow Region 7 Channel Registers
Event Register
02A0 2E00
02A0 2E04
02A0 2E08
02A0 2E0C
02A0 2E10
02A0 2E14
02A0 2E18
02A0 2E1C
02A0 2E20
02A0 2E24
02A0 2E28
02A0 2E2C
02A0 2E30
02A0 2E34
02A0 2E38
02A0 2E3C
02A0 2E40
02A0 2E44
02A0 2E48 - 02A0 2E4C
02A0 2E50
02A0 2E54
02A0 2E58
02A0 2E5C
ER
ERH
Event Register High
ECR
Event Clear Register
ECRH
ESR
Event Clear Register High
Event Set Register
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register Hig
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
-
IER
Interrupt Enable Register
IERH
IECR
IECRH
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
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Table 7-5. EDMA3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02A0 2E60
02A0 2E64
IESR
IESRH
IPR
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
02A0 2E68
02A0 2E6C
02A0 2E70
IPRH
ICR
02A0 2E74
ICRH
IEVAL
-
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
02A0 2E78
02A0 2E7C
02A0 2E80
QER
QDMA Event Register
02A0 2E84
QEER
QEECR
QEESR
QSER
QSECR
-
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
02A0 2E88
02A0 2E8C
02A0 2E90
02A0 2E94
02A0 2E98 - 02A0 2FFF
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Table 7-6. EDMA3 Parameter RAM
HEX ADDRESS
02A0 4000 - 02A0 401F
02A0 4020 - 02A0 403F
02A0 4040 - 02A0 405F
02A0 4060 - 02A0 407F
02A0 4080 - 02A0 409F
02A0 40A0 - 02A0 40BF
02A0 40C0 - 02A0 40DF
02A0 40E0 - 02A0 40FF
02A0 4100 - 02A0 411F
02A0 4120 - 02A0 413F
...
ACRONYM
REGISTER NAME
Parameter Set 0
Parameter Set 1
Parameter Set 2
Parameter Set 3
Parameter Set 4
Parameter Set 5
Parameter Set 6
Parameter Set 7
Parameter Set 8
Parameter Set 9
...
02A0 47E0 - 02A0 47FF
02A0 4800 - 02A0 481F
02A0 4820 - 02A0 483F
...
Parameter Set 63
Parameter Set 64
Parameter Set 65
...
02A0 5FC0 - 02A0 5FDF
02A0 5FE0 - 02A0 5FFF
Parameter Set 254
Parameter Set 255
Table 7-7. EDMA3 Transfer Controller 0 Registers
HEX ADDRESS RANGE
02A2 0000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A2 0004
TCCFG
-
02A2 0008 - 02A2 00FC
02A2 0100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A2 0104 - 02A2 011C
02A2 0120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A2 0124
Error Enable Register
02A2 0128
Error Clear Register
02A2 012C
Error Details Register
02A2 0130
Error Interrupt Command Register
Reserved
02A2 0134 - 02A2 013C
02A2 0140
RDRATE
-
Read Rate Register
02A2 0144 - 02A2 023C
02A2 0240
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A2 0244
02A2 0248
02A2 024C
02A2 0250
02A2 0254
02A2 0258
02A2 025C
02A2 0260
02A2 0264 - 02A2 027C
02A2 0280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A2 0284
02A2 0288
02A2 028C - 02A2 02FC
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Table 7-7. EDMA3 Transfer Controller 0 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
REGISTER NAME
02A2 0300
02A2 0304
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
02A2 0308
02A2 030C
02A2 0310
02A2 0314
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A2 0318 - 02A2 033C
02A2 0340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
02A2 0344
02A2 0348
02A2 034C
02A2 0350
02A2 0354
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A2 0358 - 02A2 037C
02A2 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
02A2 0384
02A2 0388
02A2 038C
02A2 0390
02A2 0394
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A2 0398 - 02A2 03BC
02A2 03C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
02A2 03C4
02A2 03C8
02A2 03CC
02A2 03D0
02A2 03D4
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A2 03D8 - 02A2 7FFC
Table 7-8. EDMA3 Transfer Controller 1 Registers
HEX ADDRESS RANGE
02A2 8000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A2 8004
TCCFG
-
02A2 8008 - 02A2 80FC
02A2 8100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A2 8104 - 02A2 811C
02A2 8120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A2 8124
Error Enable Register
Error Clear Register
02A2 8128
02A2 812C
Error Details Register
Error Interrupt Command Register
Reserved
02A2 8130
02A2 8134 - 02A2 813C
02A2 8140
RDRATE
-
Read Rate Register
02A2 8144 - 02A2 823C
02A2 8240
Reserved
SAOPT
SASRC
SACNT
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
02A2 8244
02A2 8248
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Table 7-8. EDMA3 Transfer Controller 1 Registers (continued)
HEX ADDRESS RANGE
02A2 824C
ACRONYM
SADST
REGISTER NAME
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A2 8250
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
02A2 8254
02A2 8258
02A2 825C
02A2 8260
02A2 8264 - 02A2 827C
02A2 8280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A2 8284
02A2 8288
02A2 828C - 02A2 82FC
02A2 8300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
02A2 8304
02A2 8308
02A2 830C
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
02A2 8310
02A2 8314
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A2 8318 - 02A2 833C
02A2 8340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
02A2 8344
02A2 8348
02A2 834C
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
02A2 8350
02A2 8354
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A2 8358 - 02A2 837C
02A2 8380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
02A2 8384
02A2 8388
02A2 838C
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
02A2 8390
02A2 8394
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A2 8398 - 02A2 83BC
02A2 83C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
02A2 83C4
02A2 83C8
02A2 83CC
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
02A2 83D0
02A2 83D4
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A2 83D8 - 02A2 FFFC
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Table 7-9. EDMA3 Transfer Controller 2 Registers
HEX ADDRESS RANGE
ACRONYM
PID
REGISTER NAME
02A3 0000
02A3 0004
Peripheral Identification Register
TCCFG
-
EDMA3TC Configuration Register
Reserved
02A3 0008 - 02A3 00FC
02A3 0100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A3 0104 - 02A3 011C
02A3 0120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A3 0124
Error Enable Register
02A3 0128
Error Clear Register
02A3 012C
Error Details Register
02A3 0130
Error Interrupt Command Register
Reserved
02A3 0134 - 02A3 013C
02A3 0140
RDRATE
-
Read Rate Register
02A3 0144 - 02A3 023C
02A3 0240
Reserved
SAOPT
SASRC
SACNT
SADST
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
02A3 0244
02A3 0248
02A3 024C
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A3 0250
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
02A3 0254
02A3 0258
02A3 025C
02A3 0260
02A3 0264 - 02A3 027C
02A3 0280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A3 0284
02A3 0288
02A3 028C - 02A3 02FC
02A3 0300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A3 0304
02A3 0308
02A3 030C
02A3 0310
02A3 0314
02A3 0318 - 02A3 033C
02A3 0340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A3 0344
02A3 0348
02A3 034C
02A3 0350
02A3 0354
02A3 0358 - 02A3 037C
02A3 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
Destination FIFO Memory Protection Proxy Register 2
02A3 0384
02A3 0388
02A3 038C
02A3 0390
02A3 0394
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Table 7-9. EDMA3 Transfer Controller 2 Registers (continued)
HEX ADDRESS RANGE
02A3 0398 - 02A3 03BC
02A3 03C0
ACRONYM
-
REGISTER NAME
Reserved
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A3 03C4
02A3 03C8
02A3 03CC
02A3 03D0
02A3 03D4
02A3 03D8 - 02A3 7FFC
Table 7-10. EDMA3 Transfer Controller 3 Registers
HEX ADDRESS RANGE
02A3 8000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A3 8004
TCCFG
-
02A3 8008 - 02A3 80FC
02A3 8100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A3 8104 - 02A3 811C
02A3 8120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A3 8124
Error Enable Register
02A3 8128
Error Clear Register
02A3 812C
Error Details Register
02A3 8130
Error Interrupt Command Register
Reserved
02A3 8134 - 02A3 813C
02A3 8140
RDRATE
-
Read Rate Register
02A3 8144 - 02A3 823C
02A3 8240
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A3 8244
02A3 8248
02A3 824C
02A3 8250
02A3 8254
02A3 8258
02A3 825C
02A3 8260
02A3 8264 - 02A3 827C
02A3 8280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A3 8284
02A3 8288
02A3 828C - 02A3 82FC
02A3 8300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A3 8304
02A3 8308
02A3 830C
02A3 8310
02A3 8314
02A3 8318 - 02A3 833C
02A3 8340
DFOPT1
DFSRC1
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
02A3 8344
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Table 7-10. EDMA3 Transfer Controller 3 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
REGISTER NAME
02A3 8348
02A3 834C
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A3 8350
02A3 8354
02A3 8358 - 02A3 837C
02A3 8380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A3 8384
02A3 8388
02A3 838C
02A3 8390
02A3 8394
02A3 8398 - 02A3 83BC
02A3 83C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A3 83C4
02A3 83C8
02A3 83CC
02A3 83D0
02A3 83D4
02A3 83D8 - 02A3 FFFC
Table 7-11. EDMA3 Transfer Controller 4 Registers
HEX ADDRESS RANGE
02A4 0000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A4 0004
TCCFG
-
02A4 0008 - 02A4 00FC
02A4 0100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A4 0104 - 02A4 011C
02A4 0120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A4 0124
Error Enable Register
02A4 0128
Error Clear Register
02A4 012C
Error Details Register
02A4 0130
Error Interrupt Command Register
Reserved
02A4 0134 - 02A4 013C
02A4 0140
RDRATE
-
Read Rate Register
02A4 0144 - 02A4 023C
02A4 0240
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A4 0244
02A4 0248
02A4 024C
02A4 0250
02A4 0254
02A4 0258
02A4 025C
02A4 0260
02A4 0264 - 02A4 027C
02A4 0280
DFCNTRLD
DFSRCBREF
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
02A4 0284
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Table 7-11. EDMA3 Transfer Controller 4 Registers (continued)
HEX ADDRESS RANGE
02A4 0288
ACRONYM
DFDSTBREF
-
REGISTER NAME
Destination FIFO Set Destination Address B Reference Register
Reserved
02A4 028C - 02A4 02FC
02A4 0300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A4 0304
02A4 0308
02A4 030C
02A4 0310
02A4 0314
02A4 0318 - 02A4 033C
02A4 0340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A4 0344
02A4 0348
02A4 034C
02A4 0350
02A4 0354
02A4 0358 - 02A4 037C
02A4 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A4 0384
02A4 0388
02A4 038C
02A4 0390
02A4 0394
02A4 0398 - 02A4 03BC
02A4 03C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A4 03C4
02A4 03C8
02A4 03CC
02A4 03D0
02A4 03D4
02A4 03D8 - 02A4 FFFC
Table 7-12. EDMA3 Transfer Controller 5 Registers
HEX ADDRESS RANGE
02A4 8000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A4 8004
TCCFG
-
02A4 8008 - 02A4 80FC
02A4 8100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A4 8104 - 02A4 811C
02A4 8120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A4 8124
Error Enable Register
Error Clear Register
Error Details Register
Error Interrupt Command Register
Reserved
02A4 8128
02A4 812C
02A4 8130
02A4 8134 - 02A4 813C
02A4 8140
RDRATE
-
Read Rate Register
Reserved
02A4 8144 - 02A4 823C
02A4 8240
SAOPT
Source Active Options Register
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Table 7-12. EDMA3 Transfer Controller 5 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
SASRC
REGISTER NAME
02A4 8244
02A4 8248
Source Active Source Address Register
Source Active Count Register
SACNT
02A4 824C
SADST
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A4 8250
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
02A4 8254
02A4 8258
02A4 825C
02A4 8260
02A4 8264 - 02A4 827C
02A4 8280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A4 8284
02A4 8288
02A4 828C - 02A4 82FC
02A4 8300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
02A4 8304
02A4 8308
02A4 830C
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
02A4 8310
02A4 8314
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A4 8318 - 02A4 833C
02A4 8340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
02A4 8344
02A4 8348
02A4 834C
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
02A4 8350
02A4 8354
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A4 8358 - 02A4 837C
02A4 8380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
02A4 8384
02A4 8388
02A4 838C
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
02A4 8390
02A4 8394
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A4 8398 - 02A4 83BC
02A4 83C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
02A4 83C4
02A4 83C8
02A4 83CC
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
02A4 83D0
02A4 83D4
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A4 83D8 - 02A4 FFFC
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7.6 Interrupts
7.6.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the device are configured through the C64x+ Megamodule Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU
interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 7-13 shows the mapping
of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the default interrupt
mapping of the device. The remaining events must be mapped using software. Table 7-14 lists the Chip
Interrupt Controller (CIC) registers. For more details on chip interrupt controller 0-2 (CIC0, CIC1, and
CIC2), see Section 7.6.2.
Table 7-13. Interrupts
EVENT CHANNEL
EVENT
EVT0
EVENT DESCRIPTION
Output of Event Combiner 0 for Events [31:4]
0
1
2
3
4
5
6
7
8
9
EVT1
Output of Event Combiner 1 for Events [63:32]
Output of Event Combiner 2 for Events [95:64]
Output of Event Combiner 3 for Events [127:96]
Semaphore Grant Interrupt
EVT2
EVT3
(1)
(2)
SEMINTn
MACINTn
Ethernet MAC Control Interrupt
(2)
(2)
MACRXINTn
MACTXINTn
Ethernet MAC Receive Interrupt
Ethernet MAC Transmit Interrupt
(2)
(3)
MACTHRESHn
EMU_DTDMAn
Ethernet MAC Receive Threshold Interrupt
ECM Interrupt for:
1. Host Scan Access
2. DTDMA Transfer Complete
3. AET Interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Unused
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMAINT0
IDMAINT1
FSEVT0
RTDX Receive Complete
RTDX Transmit Complete
IDMA Channel 0 Interrupt
IDMA Channel 1 Interrupt
Frame Synchronization Event 0
Frame Synchronization Event 1
Frame Synchronization Event 2
Frame Synchronization Event 3
Frame Synchronization Event 4
Frame Synchronization Event 5
Frame Synchronization Event 6
Frame Synchronization Event 7
Frame Synchronization Event 8
Frame Synchronization Event 9
Frame Synchronization Event 10
Frame Synchronization Event 11
Frame Synchronization Event 12
Frame Synchronization Event 13
FSEVT1
FSEVT2
FSEVT3
FSEVT4
FSEVT5
FSEVT6
FSEVT7
FSEVT8
FSEVT9
FSEVT10
FSEVT11
FSEVT12
FSEVT13
(1) C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive SEMINT0, SEMINT1, and SEMINT2,
respectively.
(2) EMAC interrupts, MACINTn, MACRXINTn, MACTXINTn, and MACTHRESHn are received by the C64x+ Megamodules, as follows:
•
•
•
C64x+ Megamodule Core 0 receives MACINT[0], MACRXINT[0], MACTXINT[0], and MACTHRESH[0]
C64x+ Megamodule Core 1 receives MACINT[1], MACRXINT[1], MACTXINT[1], and MACTHRESH[1]
C64x+ Megamodule Core 2 receives MACINT[2], MACRXINT[2], MACTXINT[2], and MACTHRESH[2]
(3) C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive EMU_DTDMA0, EMU_DTDMA1, and
EMU_DTDMA2, respectively.
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Table 7-13. Interrupts (continued)
EVENT CHANNEL
EVENT
FSEVT14
FSEVT15
FSEVT16
FSEVT17
TINT0L
EVENT DESCRIPTION
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
53
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Frame Synchronization Event 14
Frame Synchronization Event 15
Frame Synchronization Event 16
Frame Synchronization Event 17
Timer 0 Interrupt Low
TINT0H
Timer 0 Interrupt High
Timer 1 Interrupt Low
TINT1L
TINT1H
Timer 1 Interrupt High
Timer 2 Interrupt Low
TINT2L
TINT2H
Timer 2 Interrupt High
Timer 3 Interrupt Low
TINT3L
TINT3H
Timer 3 Interrupt High
Timer 4 Interrupt Low
TINT4L
TINT4H
Timer 4 Interrupt High
Timer 5 Interrupt Low
TINT5L
TINT5H
Timer 5 Interrupt High
GPIO Interrupt 0
GPINT0
GPINT1
GPIO Interrupt 1
GPINT2
GPIO Interrupt 2
GPINT3
GPIO Interrupt 3
GPINT4
GPIO Interrupt 4
GPINT5
GPIO Interrupt 5
GPINT6
GPIO Interrupt 6
GPINT7
GPIO Interrupt 7
GPINT8
GPIO Interrupt 8
GPINT9
GPIO Interrupt 9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
TPCC_GINT
TPCC_INT0
TPCC_INT1
TPCC_INT2
TPCC_INT3
TPCC_INT4
TPCC_INT5
TPCC_INT6
TPCC_INT7
Unused
GPIO Interrupt 10
GPIO Interrupt 11
GPIO Interrupt 12
GPIO Interrupt 13
GPIO Interrupt 14
GPIO Interrupt 15
EDMA Channel Global Completion Interrupt
TPCC Completion Interrupt - Mask 0
TPCC Completion Interrupt - Mask 1
TPCC Completion Interrupt - Mask 2
TPCC Completion Interrupt - Mask 3
TPCC Completion Interrupt - Mask 4
TPCC Completion Interrupt - Mask 5
TPCC Completion Interrupt - Mask 6
TPCC Completion Interrupt - Mask 7
Reserved
RIOINT (2n)(4)
RapidIO Interrupt (2n)
(4) RIOINT interrupts are received by the C64x+ Megamodules, as follows:
•
•
•
C64x+ Megamodule Core 0 receives RIOINT[1:0]
C64x+ Megamodule Core 1 receives RIOINT[3:2]
C64x+ Megamodule Core 2 receives RIOINT[5:4]
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Table 7-13. Interrupts (continued)
EVENT CHANNEL
EVENT
RIOINT (2n+1)
AIF_EVT0
AIF_EVT1
Unused
EVENT DESCRIPTION
(5)
72
73
RapidIO Interrupt (2n+1)
Error/Alarm Event 0
74
Error/Alarm Event 1
75
Reserved
76
IPC_LOCAL
Unused
Inter DSP Interrupt from IPCGRn
Reserved
77
78
Unused
Reserved
79
Unused
Reserved
80
CICn_EVT0
CICn_EVT1
CICn_EVT2
CICn_EVT3
CICn_EVT4
CICn_EVT5
CICn_EVT6
CICn_EVT7
CICn_EVT8
CICn_EVT9
CICn_EVT10
CICn_EVT11
CICn_EVT12
CICn_EVT13
Unused
System Event 0 (Combined) from Chip Interrupt Controller[n](6)
System Event 1 (Combined) from Chip Interrupt Controller[n]
System Event 2 from Chip Interrupt Controller[n]
System Event 3 from Chip Interrupt Controller[n]
System Event 4 from Chip Interrupt Controller[n]
System Event 5 from Chip Interrupt Controller[n]
System Event 6 from Chip Interrupt Controller[n]
System Event 7 from Chip Interrupt Controller[n]
System Event 8 from Chip Interrupt Controller[n]
System Event 9 from Chip Interrupt Controller[n]
System Event 10 from Chip Interrupt Controller[n]
System Event 11 from Chip Interrupt Controller[n]
System Event 12 from Chip Interrupt Controller[n]
System Event 13 from Chip Interrupt Controller[n]
Reserved
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Unused
Reserved
96
INTERR
Dropped CPU Interrupt Event
Invalid IDMA Parameters
97
EMC_IDMAERR
Unused
98
Reserved
99
Unused
Reserved
100
101
102-112
113
114-115
116
117
118
119
120
121
122
123
124
125
EFINTA
EFI Interrupt from Side A
EFIINTB
EFI Interrupt from Side B
Unused
Reserved
PMC_ED
Single Bit Error Detected during DMA Read
Reserved
Unused
UMC_ED1
UMC_ED2
PDC_INT
Corrected Bit Error Detected
Uncorrected Bit Error Detected
PDC Sleep Interrupt
SYS_CMPA
PMC_CMPA
PMC_DMPA
DMC_CMPA
DMC_DMPA
UMC_CMPA
UMC_DMPA
CPU Memory Protection Fault
CPU Memory Protection Fault
DMA Memory Protection Fault
CPU Memory Protection Fault
DMA Memory Protection Fault
CPU Memory Protection Fault
DMA Memory Protection Fault
(5) RIOINT interrupts are received by the C64x+ Megamodules, as follows:
•
•
•
C64x+ Megamodule Core 0 receives RIOINT[1:0]
C64x+ Megamodule Core 1 receives RIOINT[3:2]
C64x+ Megamodule Core 2 receives RIOINT[5:4]
(6) For more information on CICn events, see the TMS320C6474 DSP Chip Interrupt Controller (CIC) User's Guide (literature number
SPRUFK6).
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Table 7-13. Interrupts (continued)
EVENT CHANNEL
EVENT
EVENT DESCRIPTION
126
127
EMC_CMPA
EMC_BUSERR
CPU Memory Protection Fault
Bus Error Interrupt
Table 7-14. Chip Interrupt Controller Registers
HEX ADDRESS
ACRONYM
CIC0
REGISTER NAME
0288 0000
0288 0100
0288 0200
0288 0300
Chip Interrupt Controller 0 Registers
Chip Interrupt Controller 1 Registers
Chip Interrupt Controller 2 Registers
Chip Interrupt Controller 3 Registers
CIC1
CIC2
CIC3
7.6.2 System Event Routing
Additional system events are routed to each of the C64x+ Megamodules to provide chip-level events that
are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events.
Additionally, error-class events or infrequently used events are also routed through the system event
router to offload the C64x+ Megamodule interrupt selector. This is accomplished through Chip Interrupt
Controllers, CIC[2:0], with one controller per C64x+ Megamodule. This is clocked using CPU/6.
The event controllers consist of simple combination logic to provide sixteen events to each C64x+
Megamodule, plus the TPCC.
These events are routed to the C64x+ Megamodules for AET purposes, from those TPCC and FSYNC
events that are not otherwise provided to each C64x+ Megamodule. The event controllers each include
two event combiners to provide two combined events to each C64x+ Megamodule, for use. Each of the 16
event outputs from the controllers can select any of the 64 inputs, or either of the two combined events to
pass on to their respective C64x+ Megamodule.
Table 7-15 lists the system events that are available to each C64x+ Megamodule through their respective
event controllers. Note that n implies the event number matches the C64x+ Megamodule number to which
it is routed.
Table 7-15. C64x+ Megamodule Chip Interrupt Controller Event List CIC[2:0]
EVENT CHANNEL
EVENT
EVT0
EVENT DESCRIPTION
Output of Event Controller 0 for Events [31:2]
0
1
EVT1
Output of Event Controller 1 for Events [63:32]
Reserved
2-3
4
Unused
I2CINT
FSERR1
RIOINT7
FSERR2
VCPINT
TCPINT
RINT0
Error Interrupt
5
Error/Alarm Interrupt 1
6
RapidIO Interrupt 7
7
Error/Alarm Interrupt 2
8
Error Interrupt
9
Error Interrupt
10
11
12
13
14
15
16
17
McBSP0 Receive Interrupt
McBSP0 Transmit Interrupt
McBSP1 Receive Interrupt
McBSP1 Transmit Interrupt
McBSP0 Receive EDMA Event
McBSP0 Transmit EDMA Event
McBSP1 Receive EDMA Event
McBSP1 Transmit EDMA Event
XINT0
RINT1
XINT1
REVT0
XEVT0
REVT1
XEVT1
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Table 7-15. C64x+ Megamodule Chip Interrupt Controller Event List CIC[2:0] (continued)
EVENT CHANNEL
EVENT
IREVT
EVENT DESCRIPTION
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55-57
58
59-63
I2C Receive EDMA Event
I2C Transmit EDMA Event
FSYNC Event 18
IXEVT
FSEVT18
FSEVT19
FSYNC Event 19
FSEVT20
FSYNC Event 20
FSEVT21
FSYNC Event 21
FSEVT22
FSYNC Event 22
FSEVT23
FSYNC Event 23
FSEVT24
FSYNC Event 24
FSEVT25
FSYNC Event 25
FSEVT26
FSYNC Event 26
FSEVT27
FSYNC Event 27
FSEVT28
FSYNC Event 28
FSEVT29
FSYNC Event 28
VCPREVT
VCP Receive Event
VCP Transmit Event
TCP Receive Event
TCP Transmit Event
TPCC Error Interrupt
VCPXEVT
TCPREVT
TCPXEVT
TPCC_ERRINT
TPCC_MPINT
TPTC_ERRINT0
TPTC_ERRINT1
TPTC_ERRINT2
TPTC_ERRINT3
TPTC_ERRINT4
TPTC_ERRINT5
TPCC_AETEVT
AIF_EVT2
TPCC Memory Protection Interrupt
TPTC0 Error Interrupt
TPTC1 Error Interrupt
TPTC2 Error Interrupt
TPTC3 Error Interrupt
TPTC4 Error Interrupt
TPTC5 Error Interrupt
TPCC AET Event
AIF CPU Interrupt 2
AIF_EVT3
AIF CPU Interrupt 2
AIF_PSEVT0
AIF_PSEVT1
AIF_PSEVT2
AIF_PSEVT3
AIF_PSEVT4
AIF_PSEVT5
AIF_PSEVT6
AIF_BUFEVT
Unused
Packet Switched Transfer Event 0
Packet Switched Transfer Event 1
Packet Switched Transfer Event 2
Packet Switched Transfer Event 3
Packet Switched Transfer Event 4
Packet Switched Transfer Event 5
Packet Switched Transfer Event 6
AIF Capture Buffer Event.
Reserved
(1)
SEMERRn
Semaphore Error Event for C64x+ Megamodulen
Reserved
Unused
(1) C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive SEMERR0, SEMERR1, and
SEMERR2, respectively.
Another system event selector is present to route events to the TPCC. Most system events routed through
the event controller to the TPCC are CPU events that do not normally require DMA servicing, but may be
used to trigger a statistics capture. Several events are routed through the event controller that may be
used to trigger a DMA transaction in normal operation, but the programmer must make a resource tradeoff
to use these events. Table 7-16 lists all of the events routed through the TPCCs system event controller.
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Table 7-16. TPCC Interrupt Controller Event List (CIC3)
EVENT CHANNEL
EVENT
EVT0
EVENT DESCRIPTION
Output of Event Controller 0 for Events [31:2]
0
1
EVT1
Output of Event Controller 1 for Events [63:32]
Frame Synchronization Event 0
Frame Synchronization Event 1
Frame Synchronization Event 2
Frame Synchronization Event 3
Frame Synchronization Event 14
Frame Synchronization Event 15
Frame Synchronization Event 16
Frame Synchronization Event 17
Frame Synchronization Event 18
Frame Synchronization Event 19
Frame Synchronization Event 20
Frame Synchronization Event 21
Frame Synchronization Event 22
Frame Synchronization Event 23
Frame Synchronization Event 24
Frame Synchronization Event 25
Frame Synchronization Event 26
Frame Synchronization Event 27
Frame Synchronization Event 28
RapidIO Interrupt 0
2
FSEVT0
3
FSEVT1
4
FSEVT2
5
FSEVT3
6
FSEVT14
FSEVT15
FSEVT16
FSEVT17
FSEVT18
FSEVT19
FSEVT20
FSEVT21
FSEVT22
FSEVT23
FSEVT24
FSEVT25
FSEVT26
FSEVT27
FSEVT28
RIOINT0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40-42
43
44
45
46
47
48
RIOINT1
RapidIO Interrupt 1
RIOINT2
RapidIO Interrupt 2
RIOINT3
RapidIO Interrupt 3
RIOINT4
RapidIO Interrupt 4
RIOINT5
RapidIO Interrupt 5
RIOINT7
RapidIO Interrupt 7
MACINT[0]
MACRXINT[0]
MACTXINT[0]
MACINT[1]
MACRXINT[1]
MACTXINT[1]
MACINT[2]
MACRXINT[2]
MACTXINT[2]
SEMERR0
SEMERR1
SEMERR2
Unused
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Ethernet EMAC Interrupt
Semaphore Error Interrupt
Semaphore Error Interrupt
Semaphore Error Interrupt
Reserved
TINT3L
Timer Interrupt Low
TINT3H
Timer Interrupt High
TINT4L
Timer Interrupt Low
TINT4H
Timer Interrupt High
TINT5L
Timer Interrupt Low
TINT5H
Timer Interrupt High
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Table 7-16. TPCC Interrupt Controller Event List (CIC3) (continued)
EVENT CHANNEL
EVENT
AIF_BUFEVT
FSEVT29
EVENT DESCRIPTION
49
50
AIF Capture Buffer Event
Frame Synchronization Event 29
Reserved
51-52
53
Unused
GPINT0
GPIO Event
54
GPINT1
GPIO Event
55
GPINT2
GPIO Event
56
GPINT3
GPIO Event
57
GPINT4
GPIO Event
58
CIC0_EVT14
CIC0_EVT15
CIC1_EVT14
CIC1_EVT15
CIC2_EVT14
CIC2_EVT15
CIC_EVT_o[14] from Chip Interrupt Controller[0]
CIC_EVT_o[15] from Chip Interrupt Controller[0]
CIC_EVT_o[14] from Chip Interrupt Controller[1]
CIC_EVT_o[15] from Chip Interrupt Controller[1]
CIC_EVT_o[14] from Chip Interrupt Controller[2]
CIC_EVT_o[15] from Chip Interrupt Controller[2]
59
60
61
62
63
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7.6.3 External Interrupts Electrical Data/Timing
Table 7-17. Timing Requirements for External Interrupts(1)
(see Figure 7-5)
NO.
PARAMETERS
Width of the NMI interrupt pulse low
Width of the NMI interrupt pulse high
MIN
6P
MAX UNIT
1
2
tw(NMIL)
tw(NMIH)
ns
ns
6P
(1) P = 1/CPU clock frequency, in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
2
1
NMI
Figure 7-5. NMI Interrupt Timing
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7.7 Reset Controller
The reset controller detects the different type of resets supported on the device and manages the
distribution of those resets throughout the device.
The C6474 device has several types of resets: power-on reset, warm reset, system reset, and CPU reset.
Table 7-18 explains further the types of reset, the reset initiator, and the effects of each reset on the chip.
Table 7-18. Reset Types
TYPE
Power-on Reset
Warm Reset
INITIATOR
POR pin
EFFECT(S)
Resets the entire chip including the test and emulation logic.
XWRST pin
Resets everything except for the test and emulation logic PLL2, AIF, and FSYNC. Emulation
stays alive during warm reset.
System Reset
Emulator
Serial RapidIO
A system reset maintains memory contents and does not reset the test and emulation
circuitry. The device configuration pins are also not re-latched and the state of the
peripherals (enabled/disabled) are also not affected.
CPU Local Reset
Watchdog Timer
CPU local reset.
7.7.1 Power-on Reset (POR Pin)
Power-on Reset is a special reset needed when powering on the DSP. The device is globally reset
through the assertion of the active-low Power-on Reset (POR) input. The power-on reset is intended to be
asserted to the device while the system power supplies are ramped.
For power-on reset, the main PLL Controller comes up in bypass and the PLL is not enabled. Other resets
do not affect the state of the PLL or the dividers in the PLL Controller. For the secondary PLL Controller,
this is different as the PLL is enabled and clocking always when POR is not asserted.
The following sequence must be followed during a power-on reset.
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After
the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set
to their reset state and will remain at their reset state until otherwise configured by their respective
peripheral. All peripherals that are power managed, are disabled after a Power-on Reset and must be
enabled through the Device State Control registers (for more details, see Section 3.2, Peripheral
Selection After Device Reset.
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in
reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional 100
μs.
4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. PLL2 is
taken out of reset and begins its locking sequence, and all power-on device initialization also begins.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time,
PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of
both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their
respective system reference clocks. After the pause, the system clocks are restarted at their default
divide by settings.
6. The device is now out of reset and device execution begins as dictated by the selected boot mode.
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7.7.2 Warm Reset
A warm reset will reset everything on the chip except the AIF, FSYNC, PLLs, PLL Controllers, test, and
emulation logic. POR should also remain de-asserted during this time.
1. XWRST pin is pulled active low for a minimum of 24 CLKIN1 cycles. The reset signals flow to the
modules reset by warm reset and sends a tri-state signal to most the I/O pads, to prevent off chip
contention.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. XWRST pin can now be released. A minimal device initialization begins to occur. Note that
configuration pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
During warm reset, the DDR2 SDRAM memory content can be retained if the user places the DDR2
SDRAM in self-refresh mode before invoking the warm reset; however, warm reset will reset the DDR2
EMIF registers. The software needs to re-program all DDR2 EMIF registers to correct values after warm
reset.
7.7.3 System Reset
System reset is initiated by the emulator or by the RapidIO module. It is triggered by clicking on the
Debug → Advanced Resets → System Reset menu in Code Composer Studio using the emulator.
System reset is also triggered by RIOINT[6], which is connected to the reset controller. It is considered a
soft reset, meaning memory contents are maintained, it does not affect the clock logic, or the power
control logic of the peripherals.
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to
propagate through the system. Internal system clocks are not affected. PLLs also remain locked.
2. The boot sequence is started after the system clocks are restarted. Since the configuration pins
(including the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as
shown in the DEVSTAT register, are used to select the boot mode.
7.7.4 CPU Reset
(Timer 64 3, 4, and 5) can provide a local CPU reset if they are setup in watchdog mode. Timer64 3, 4,
and 5 are allowed to reset C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+
Megamodule Core 2, respectively.
7.7.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority
reset request. The reset request priorities are as follows (high to low):
•
•
•
•
Power-on Reset
Warm Reset
System Reset
CPU Reset
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7.7.6 Reset Controller Register
The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see
Table 7-19).
7.7.6.1 Reset Type Status Register Description
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The reset type status register is
shown in Figure 7-6 and described in Table 7-19.
31
15
16
Reserved
R-0
4
3
2
1
0
Reserved
R-0
SRST Rsvd WRST POR
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-6. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4]
Table 7-19. Reset Type Status Register (RSTYPE) Field Descriptions
BIT
31:4
3
FIELD
Reserved
VALUE
DESCRIPTION
Reserved. The reserved bit location is always read as 0. A value written to this field has not effect.
System Reset.
SRST
0
1
System Reset was not the last reset to occur.
System Reset was the last reset to occur.
Warm Reset.
1
WRST
0
1
Warm Reset was not the last reset to occur.
Warm Reset was the last reset to occur.
2
0
Reserved
POR
Reserved. The reserved bit location is always read as 0. A value written to this field has not effect.
Power-on Reset.
0
1
Power-on Reset was not the last reset to occur.
Power-on Reset was the last reset to occur.
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7.7.7 Reset Electrical Data/Timing
Table 7-20. Timing Requirements for Reset(1) (2)
(see Figure 7-7 and Figure 7-8)
NO.
MIN
100
100
24C
12C
MAX UNIT
1
2
4
7
th(SUPPLY-POR)
tsu(XWRSTH-PORH)
tw(XWRST)
Hold Time, POR low after supplies stable and input clocks valid
Setup Time, XWRSTx high to POR high
Pulse Duration, XWRST low
μs
μs
ns
ns
ts(BOOT)
Setup time, boot mode and configuration pins valid before POR
or XWRST high
8
th(BOOT)
Hold time, bootmode and configuration pins valid after POR or
XWRST high
12C
ns
(1) If CORECLKSEL = 0, C = 1/SYSCLK(N|P) frequency, in ns.
(2) If CORECLKSEL = 1, C = 1/ALTCORECLK(N|P) frequency, in ns.
Table 7-21. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 7-7 and Figure 7-8)
NO.
3
MIN
MAX UNIT
td(PORH-RSTATH)
Delay Time, POR high to RESETSTAT high
21000C
35C
ns
ns
5
td(XWRSTH-RSTATH) Delay Time, XWRST high to RESETSTAT high
(1) C = 1/CPU frequency, in ns.
Table 7-22. Switching Characteristics Over Recommended Operating Conditions for Warm Reset
(see Figure 7-9)
NO.
MIN
MAX UNIT
9
tsu(PORH-XWRSTL)
Setup time, POR high to XWRST low
1.34
ms
1
2
POR
XWRST
3
RESETSTAT
7
Boot and Device
Configuration Pins
8
Figure 7-7. Power-On Reset Timing
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POR
XWRST
4
5
RESETSTAT
Figure 7-8. Warm Reset Timing
POR
XWRST
9
Figure 7-9. Warm Reset Timing
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7.8 PLL1 and PLL1 Controller
This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUG09).
Note: The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320C6474 DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUG09) are supported on the C6474 device.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
The Main and DDR PLLs are controlled by standard PLL Controller peripherals. The PLL Controllers
manage the clock ratios, alignment, and gating for the system clocks to the chip. Figure 7-10 includes a
block diagram of the PLL Controller, and the two subsequent sections define the clocks and PLL
Controller parameters for each of the two standard PLLs.
The PLL controller logic is responsible for controlling all modes of the PLL through software, in terms
multiply factor within the PLL and post-division for each of the chip-level clocks from the PLL output. The
PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL
controller monitors the PLL status and provides an output signal indicating when the PLL is locked.
AIF SERDES 0
AVDD118
x12.5, 10, 4
AIF SERDES 1
SYS_CLK_(PIN)
x12.5, 10, 4
Main.PLL Controller
Main PLL
To L2 and L2 PDCTL
0
1
xM
/1
.
.
C64x+ Megamodule
Core 0
ALT_CORE_CLK_(PIN)
CORE_CLK_SEL
/2
/n
/4
.
.
C64x+ Megamodule
Core 1
.
.
C64x+ Megamodule
Core 2
.
.
/3
.
.
To Trace
Reserved
/6
.
.
/m
.
.
CHIP_CLK3
CHIP_CLK6
McBSP_CLKS
EMIF_PTV
To switch fabric
peripherals,
accelerators
/20
/20
.
.
Figure 7-10. PLL Controller Diagram
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7.8.1 PLL1 Controller Device-Specific Information
7.8.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive all of the cores, the switch fabric, and a majority of the peripheral clocks (all
but the DDR2 clocks) requires a PLL controller to manage the various clock divisions, gating, and
synchronization. The Main PLL controller has seven CPU/6 outputs that are listed below, along with the
clock description. Each CPU/6 has a corresponding divide that divides down the output clock of the PLL.
Note that dividers are not programmable unless explicitly mentioned in the description below.
•
•
•
•
SYSCLK1 - SYSCLK6: Reserved.
SYSCLK7: Full-rate clock for all C64x+ Megamodules.
SYSCLK8: Reserved.
SYSCLK9: 1/3-rate clock (chip_clk3) for the switch fabrics, CIC blocks, and fast peripherals (AIF,
SRIO, TCP, VCP, EDMA).
•
•
SYSCLK10: 1/6-rate clock (chip_clk6) for other peripherals (PLL Controllers, McBSPs, Timer64s,
Semaphore, EMAC, GPIO, I2C, PSC) and L3 ROM.
SYSCLK11: 1/n-rate clock (chip_clks) for an optional McBSP CLKS module input to drive the clock
generator. Default for this will be 1/10. This is programmable from /8 to /32, where this clock does not
violate the max clock of 100 MHz. This clock is also output to the SYSCLKOUT pin.
•
•
SYSCLK12: 1/2-rate clock used to clock the L2 and L2 Powerdown Controller.
SYSCLK13: 1/n-rate clock for trace. Default rate for this will be 1/6. This is programmable from /1 to
/32, where this clock does not violate the max of 333 MHz. Please note that the data rate on the trace
pins are 1/2 of this clock.
7.8.1.2 PLL1 Controller Operating Modes
The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is
generated from the device input clock CLKIN1 and the PLL multiplier PLLM. In bypass mode, CLKIN1 is
fed directly to SYSREFCLK.
All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A
mechanism must be in place such that the DSP notifies the host when the PLL configuration has
completed.
7.8.1.3 PLL1 Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device powerup. The PLL should not be operated until this stabilization time has
expired.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in
order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the
PLL1 reset time value, see Table 7-23.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1
with PLLEN = 0) to when the PLL controller can be switched to PLL mode (PLLEN = 1). The PLL1 lock
time is given in Table 7-24.
Table 7-23. PLL1 Stabilization, Lock, and Reset Times(1)
MIN
TYPE
MAX
UNIT
PLL1 Stabilization Time
PLL Lock Time
100
μS
2000P
PLL Reset Time
1000
ns
(1) P = CLKIN1 cycle time in ns.
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7.8.2 PLL1 Controller Memory Map
The memory map of the PLL1 controller is shown in Table 7-24. Note that only registers documented here
are accessible on the device. Other addresses in the PLL1 controller memory map should not be modified.
Table 7-24. PLL1 Controller Registers (Including Reset Controller)
HEX ADDRESS
029A 0000 - 029A 00E3
029A 00E4
029A 00E8 - 029A 00FF
029A 0100
029A 0104
029A 0108
029A 010C
029A 0110
029A 0114
029A 0118
029A 011C
029A 0120
029A 0124
029A 0128
029A 012C
029A 0130
029A 0134
029A 0138
029A 013C
029A 0140
029A 0144
029A 0148
029A 014C
029A 0150
029A 0154
029A 0158
029A 015C
029A 0160
029A 0164
029A 0168
029A 016C
029A 0170
029A 0174
029A 0178
029A 017C
029A 0180
029A 0184
029A 0188
029A 018C
ACRONYM
REGISTER NAME
-
Reserved
RSTYPE
Reset Type Status Register (Reset Controller)
-
Reserved
PLLCTL
PLL Control Register
-
Reserved
-
Reserved
-
Reserved
PLLM
PLL Multiplier Control Register
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PLLCMD
PLL Controller Command Register
PLLSTAT
PLL Controller Status Register
ALNCTL
PLL Controller Clock Align Control Register
DCHANGE
PLLDIV Ratio Change Status Register
-
Reserved
-
Reserved
SYSTAT
SYSCLK Status Register
Reserved
-
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
PLLDIV11
PLL Controller Divider 11 Register
Reserved
-
PLLDIV13
PLL Controller Divider 13 Register
Reserved
-
-
Reserved
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7.8.3 PLL1 Controller Register Descriptions
This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUG09).
NOTE: The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320C6474 DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUG09) are supported on the C6474 device.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
7.8.3.1 PLL1 Control Register
The PLL control register (PLLCTL) is shown in Figure 7-11 and described in Table 7-25.
31
15
16
Reserved
R-0
8
7
6
5
4
3
2
1
0
PLL
PWRDN
Reserved
Rsvd
Rsvd
Reserved
PLLRST
Rsvd
PLLEN
R-0
R/W-0
R-1
R/W-0
R/W-1
R-0
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-11. PLL1 Control Register (PLLCTL) [Hex Address: 029A 0100]
Table 7-25. PLL1 Control Register (PLLCTL) Field Descriptions
Bit
31:8
7
Field
Value Description
Reserved
Reserved
Reserved
Reserved
PLLRST
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. Writes to this register must keep this bit as 0.
6
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
5:4
3
Reserved. Writes to this register must keep this bit as 0.
PLL reset bit
0
1
PLL reset is released
PLL reset is asserted
2
1
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLLPWRDN
PLL power-down mode select bit
0
1
PLL is operational
PLL is placed in power-down state, i.e., all analog circuitry in the PLL is turned-off
PLL enable bit
0
PLLEN
0
1
Bypass mode. PLL is bypassed. All the system clocks (SYSCLKn) are divided down directly from
input reference clock.
PLL mode. PLL is not bypassed. PLL output path is enabled. All the system clocks (SYSCLKn) are
divided down from PLL output.
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7.8.3.2 PLL Multiplier Control Register
The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-26. The PLLM
register defines the input reference clock frequency multiplier.
31
15
16
Reserved
R-0
5
4
0
Reserved
R-0
PLLM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-12. PLL Multiplier Control Register (PLLM) [Hex Address: 029A 0110]
Table 7-26. PLL Multiplier Control Register (PLLM) Field Descriptions(1)
Bit
31:5
4:0
Field
Value Description
Reserved
PLLM
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
PLL multiplier bits. Defines the input reference clock frequency multiplier.
0h
3h
4h
Bypass
x4 multiplier rate
x5 multiplier rate
.
.
.
.
.
.
1Eh
1Fh
x31 multiplier rate
x32 multiplier rate
(1) For more information, see Section 7.8.4.
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7.8.3.3 PLL Controller Divider 11 Register
The PLL controller divider 11 register (PLLDIV11) is shown in Figure 7-13 and described in Table 7-27.
31
16
Reserved
R-0
15
14
5
4
0
D11EN
Reserved
RATIO
R/W-3
R/W-1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-13. PLL Controller Divider 11 Register (PLLDIV11) [Hex Address: 029A 017C]
Table 7-27. PLL Controller Divider 11 Register (PLLDIV11) Field Descriptions
Bit
Field
Value
Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
15
D11EN
Divider 11 enable bit.
0
1
0
Divider 11 is disabled. No clock output.
Divider 11 is enabled.
14:5
4:0
Reserved
RATIO(1)
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
0-1Fh
0h-4h
Divider ratio bits.
Reserved, do not use.
7h-31h
32h-1Fh
÷8 to ÷ 32. Divide frequency by 8 to divide frequency by 32.
Reserved, do not use.
(1) For more details, see SYSCLK11 description in Section 7.8.1.1.
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7.8.3.4 PLL Controller Divider 13 Register
The PLL controller divider 13 register (PLLDIV13) is shown in Figure 7-14 and described in Table 7-28.
31
16
Reserved
R-0
15
14
5
4
0
D13EN
Reserved
RATIO
R/W-3
R/W-1
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-14. PLL Controller Divider 13 Register (PLLDIV13) [Hex Address: 029A 0184]
Table 7-28. PLL Controller Divider 13 Register (PLLDIV13) Field Descriptions
Bit
Field
Value
Description
31:16 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
15
D13EN
Divider 13 enable bit.
0
1
0
Divider 13 is disabled. No clock output.
Divider 13 is enabled.
14:5
4:0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no
effect.
0-1Fh
0h-31h
32h-1Fh
Divider ratio bits.
÷1 to ÷32. Divide frequency by 1 to divide frequency by 32.
Reserved, do not use.
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7.8.3.5 PLL Controller Command Register
The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is
shown in Figure 7-15 and described in Table 7-29.
31
15
16
Reserved
R-0
2
1
0
Reserved
Rsvd GOSET
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
R/W-0 R/W-0
Figure 7-15. PLL Controller Command Register (PLLCMD) [Hex Address: 029A 0138]
Table 7-29. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit
31:2
1
Field
Value Description
Reserved
Reserved
GOSET
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0
GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
GO operations have completed.
0
1
No effect. Write of 0 clears bit to 0.
Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further
writes of 1 can initiate the GO operation.
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7.8.3.6 PLL Controller Status Register
The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in
Figure 7-16 and described in Table 7-30.
31
15
16
Reserved
R-0
1
0
Reserved
GOSTAT
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-16. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C]
Table 7-30. PLL Controller Status Register (PLLSTAT) Field Descriptions
Bit
31:1
0
Field
Value Description
Reserved
GOSTAT
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
GO operation status.
0
1
GO operation is not in progress. SYSCLK divide ratios are not being changed.
GO operation is in progress. SYSCLK divide ratios are being changed.
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7.8.3.7 PLL Controller Clock Align Control Register
The PLL controller clock align control register (ALNCTL) is shown in Figure 7-17 and described in
Table 7-31.
31
15
16
Reserved
R-0
14
13
Rsvd ALN13 Rsvd ALN11
R-1 R-1 R-1 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
12
11
10
9
0
Reserved
R-0
Reserved
R-1
Figure 7-17. PLL Controller Clock Align Control Register (ALNCTL) [Hex Address: 029A 0140]
Table 7-31. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
Field
Value Description
31:14 Reserved
0
1
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
13
12
Reserved
ALN13
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
SYSCLK13 alignment. Do not change the default values of these fields.
0
1
1
Do not align SYSCLK13 to other SYSCLKs during GO operation. If SYS13 in DCHANGE is set to
1, SYSCLK13 switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLK13 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
The SYSCLK13 ratio is set to the ratio programmed in the RATIO bit in PLLDIV13.
11
10
Reserved
ALN11
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
SYSCLK11 alignment. Do not change the default values of these fields.
0
1
1
Do not align SYSCLK11 to other SYSCLKs during GO operation. If SYS11 in DCHANGE is set to
1, SYSCLK11 switches to the new ratio immediately after the GOSET bit in PLLCMD is set.
Align SYSCLK11 to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set.
The SYSCLK11 ratio is set to the ratio programmed in the RATIO bit in PLLDIV11.
9:0
Reserved
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
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7.8.3.8 PLLDIV Divider Ratio Change Status Register
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the
PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only
change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be
automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in
Figure 7-18 and described in Table 7-32.
31
15
16
Reserved
R-0
13
12
SYS13 Rsvd SYS11
R/W-0 R-0 R/W-0
11
10
9
0
Reserved
R-0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-18. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]
Table 7-32. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
Field
Value Description
31:13 Reserved
0
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
12
SYS13
Identifies when the SYSCLK13 divide ratio has been modified.
0
1
0
SYSCLK13 ratio has not been modified. When GOSET is set, SYSCLK13 will not be affected.
SYSCLK13 ratio has been modified. When GOSET is set, SYSCLK13 will change to the new ratio.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Identifies when the SYSCLK11 divide ratio has been modified.
11
10
Reserved
SYS11
0
1
0
SYSCLK11 ratio has not been modified. When GOSET is set, SYSCLK11 will not be affected.
SYSCLK11 ratio has been modified. When GOSET is set, SYSCLK11 will change to the new ratio.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
2:0
Reserved
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7.8.3.9 SYSCLK Status Register
The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is
shown in Figure 7-19 and described in Table 7-33.
31
16
Reserved
R-1
15
7
13
5
12
SYS13ON
R-1
11
SYS12ON
R-1
10
SYS11ON
R-1
9
8
Reserved
R-1
SYS10ON
R-1
SYS9ON
R-1
6
0
SYS8ON
R-1
SYS7ON
R-1
Reserved
R-1
LEGEND: R = Read only; -n = value after reset
Figure 7-19. SYSCLK Status Register (SYSTAT) [Hex Address: 029A 0150]
Table 7-33. SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field
Value Description
31:13 Reserved
1
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
12:6
5:0
SYSnON
SYSCLKn on status.
0
1
1
SYSCLKn is gated.
SYSCLKn is on.
Reserved
Reserved. The reserved bit location is always read as 1. A value written to this field has no effect.
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7.8.4 PLL1 Controller Input and Output Electrical Data/Timing
Table 7-34. Timing Requirements for SYSCLK and ALTCORECLK(1)
(see Figure 7-20)
NO.
PARAMETERS
AIF Used, CORECLKSEL=0
Cycle time, SYSCLK(N|P)
MIN
MAX UNIT
1
2
3
4
5
tc(SYSCLK)
tw(SYSCLKH)
tw(SYSCLKL)
tt(SYSCLK)
tj(SYSCLK)
16.276
0.4C
0.4C
50
16.276
ns
ns
ns
ps
ps
Pulse duration, SYSCLK(N|P) high
Pulse duration, SYSCLK(N|P) low
Transition time, SYSCLK(N|P)
1300
4
Period Jitter (RMS), SYSCLK(N|P)
AIF Used, CORECLKSEL=1
1
2
3
4
5
tc(SYSCLK)
tw(SYSCLKH)
tw(SYSCLKL)
tt(SYSCLK)
tj(SYSCLK)
Cycle time, SYSCLK(N|P)
6.51
0.4C
0.4C
50
16.276
ns
ns
ns
ps
ps
Pulse duration, SYSCLK(N|P) high
Pulse duration, SYSCLK(N|P) low
Transition time, SYSCLK(N|P)
Period Jitter (RMS), SYSCLK(N|P)
1300
4
CORECLKSEL=1
1
2
3
4
5
tc(ALTCORECLK)
tw(ALTCORECLK)
tw(ALTCORECLKL)
tt(ALTCORECLK)
tj(ALTCORECLK)
Cycle time, ALTCORECLK(N|P)
Pulse duration, ALTCORECLK(N|P) high
Pulse duration, ALTCORECLK(N|P) low
Transition time, ALTCORECLK(N|P)
Period Jitter (peak-to-peak), ALTCORECLK(N|P)
SYSCLKOUT
16(2)
0.4C
0.4C
50
25.00
ns
ns
ns
ps
ps
1300
100
1
2
3
4
tc(CKO)
Cycle time, SYSCLKOUT
10C
4C - 0.7
4C - 0.7
32C
32C + 0.7
32C + 0.7
1
ns
ns
ns
ns
tw(CKOH)
tw(CKOL)
tt(CKO)
Pulse duration, SYSCLKOUT high
Pulse duration, SYSCLKOUT low
Transition time, SYSCLKOUT
(1) If CORECLKSEL = 0, C = 1/SYSCLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK frequency, in ns.
(2) For the 850-MHz device, the minimum ALTCORECLK(N|P) must initially be 18.83 ns due to the boot ROM setting the default PLL1
multiplier to x16, resulting in SYSCLKOUT = 850 MHz.
1
4
2
CLKIN
3
4
Figure 7-20. CLKIN Timing
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7.9 PLL2 and PLL2 Controller
The secondary PLL controller generates interface clocks for the DDR2 memory controller. The CLKIN2
input for PLL2 is DDRREFCLK. It is a differential clock input and is applied at the DDRREFCLKP and
DDRREFCLKN pins. When coming out of power-on reset, PLL2 is enabled and initialized.
As shown in Figure 7-21, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is
fixed to a x10 multiplier rate.
PLL2 power is supplied externally via the PLL2 power supply (AVDD218). An external PLL filter circuit must
be added to AVDD218 as shown in Figure 7-21. The 1.8-V supply for the EMI filter must be from the same
1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter manufacturer Murata.
For more information on the external PLL filter or the EMI filter, see the TMS320C6474 Hardware Design
Guide application report (literature number SPRAAW7).
All PLL external components (capacitors and the EMI filter) should be placed as close to the C64x+ DSP
device as possible. For the best performance, TI requires that all the PLL external components be on a
single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(capacitors and the EMI filter). The minimum CLKIN2 rise and fall times should also be observed.
DDR.PLL
AVDD218
PLLOUT
DDR2
PHY
÷ 2
x10
DDR.PLLController
Figure 7-21. PLL2 Block Diagram
7.9.1 PLL2 Controller Device-Specific Information
7.9.1.1 Internal Clocks and Maximum Operating Frequencies
As shown in Figure 7-21, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2
memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT0[P/N]
and DDR2CLKOUT1[P/N]. Note that, internally, the data bus interface of the DDR2 memory controller is
clocked by SYSCLK2 and PLL1 controller.
Note that there is a minimum and maximum operating frequency for DDRREFCLK and PLLOUT. The
clock generator and PLL multiplier must not be configured to exceed any of these constraints. For the PLL
clocks input and output frequency ranges, see Table 7-35. DDRREFCLK is a differential clock input to
PLL2 and is applied at the DDRREFCLKP and DDRREFCLKN pins.
Table 7-35. PLL2 Clock Frequency Ranges
MIN
40
MAX
66.7
667
UNIT
MHz
MHz
MHz
DDRREFCLK (PLLEN = 1)
PLLOUT
400
200
DDR2CLKOUT0[P/N] and DDR2CLKOUT1[P/N]
333
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7.9.1.2 PLL2 Controller Operating Modes
Unlike the PLL1 controller which can operate in by_pass and _PLL mode, the PLL2 controller only
operates in PLL mode. In this mode, SYSREFCLK is generated outside the PLL2 controller by dividing the
output by two.
The PLL2 controller is affected by power-on reset and warm reset. During these resets, the PLL2
controller registers get reset to their default values. The internal clocks of the PLL2 controller are also
affected as described in Section 7.7, Reset Controller.
PLL2 is only unlocked during the power-up sequence (see Section 7.7, Reset Controller) and is locked by
the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
7.9.2 PLL2 Controller Input and Output Electrical Data/Timing
Table 7-36. Timing Requirements for DDRREFCLK(N|P)(1)
(see Figure 7-22)
NO.
1
PARAMETERS
MIN
15
MAX UNIT
tc(DDRREFCLK)
tw(DDRREFCLKH)
tw(DDRREFCLKL)
tt(DDRREFCLK)
tj(DDRREFCLK)
Cycle time, DDRREFCLK(N|P)
25
ns
ns
ns
ps
ps
2
Pulse duration, DDRREFCLK(N|P) high
Pulse duration, DDRREFCLK(N|P) low
Transition time, DDRREFCLK(N|P)
Period jitter (peak-to-peak), DDRREFCLK(N|P)
0.4C
0.4C
50
3
4
1300
5
0.02 x
tc(DDRREFCLK)
(1) C=1/DDRREFCLK(N|P)
5
1
4
2
DDRREFCLK(N|P)
3
4
Figure 7-22. DDRREFCLK(N|P) Timing
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7.10 DDR2 Memory Controller
The 32-bit DDR2 Memory Controller bus of the C6474 device is used to interface to JESD79-2B
standard-compliant DDR2 SDRAM devices. The DDR2 bus is designed to sustain a throughput of up to
2.67 GBps at a 667-MHz data rate (333-MHz clock rate) as long as data requests are pending in the
DDR2 Memory Controller.
The DDR2 external bus only interfaces to DDR2 SDRAM devices; it does not share the bus with any other
types of peripherals.
7.10.1 DDR2 Memory Controller Device-Specific Information
The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces
such as McBSP. For these other interfaces the device timing was specified in terms of data manual
specifications and I/O buffer information specification (IBIS) models.
For the C6474 DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the
printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has
performed the simulation and system characterization to ensure all DDR2 interface timings in this solution
are met. The complete DDR2 system solution is documented in the TMS320C6474 DDR2 Implementation
Guidelines application report (literature number SPRAAW8).
TI only supports designs that follow the board design guidelines outlined in the SPRAAW8
application report.
The DDR2 memory controller on the C6474 device supports the following memory topologies:
•
•
32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.
16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.
A race condition may exist when certain masters write data to the DDR2 memory controller. For example,
if master A passes a software message via a buffer in external memory and does not wait for indication
that the write completes, when master B attempts to read the software message, then the master B read
may bypass the master A write and, thus, master B may read stale data and, therefore, receive an
incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for an indication that a write is complete, it must perform the following
workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2 memory controller module ID and revision register.
3. Perform a dummy read to the DDR2 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
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7.10.2 DDR2 Memory Controller Peripheral Register Description(s)
The memory map of the DDR2 controller is shown in Table 7-37.
Table 7-37. DDR2 Memory Controller Registers
HEX ADDRESS
7000 0000
ACRONYM
REGISTER NAME
DDR2 Memory Controller Module and Revision Register
DDR2 Memory Controller Status Register
DDR2 Memory Controller SDRAM Configuration Register
DDR2 Memory Controller SDRAM Refresh Control Register
DDR2 Memory Controller SDRAM Timing 1 Register
DDR2 Memory Controller SDRAM Timing 2 Register
Reserved
MIDR
7000 0004
DMCSTAT
7000 0008
SDCFG
7000 000C
SDRFC
7000 0010
SDTIM1
7000 0014
SDTIM2
7000 0018
-
7000 0020
BPRIO
DDR2 Memory Controller Burst Priority Register
Reserved
7000 0024 - 7000 004C
7000 0050 - 7000 0078
7000 007C - 7000 00BC
7000 00C0 - 7000 00E0
7000 00E4
-
-
Reserved
-
Reserved
-
Reserved
DMCCTL
-
DDR2 Memory Controller Control Register
Reserved
7000 00E8 - 7000 00EC
7000 00F0
DDR2IO
Control Register
DDR2 ODT control register is at 0x7000 00F0
Bits 1:0 are the ODT status, these bits are Read/Write
00 no termination
01 half termination
11 full termination
Bits 31:2 are Reserved
7000 00F4 - 7000 00FC
7000 0100 - 7FFF FFFF
-
-
Reserved
Reserved
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7.10.3 DDR2 Memory Controller Electrical Data/Timing
The TMS320C6474 DDR2 Implementation Guidelines application report (literature number SPRAAW8)
specifies a complete DDR2 interface solution for the C6474 device as well as a list of compatible DDR2
devices. TI has performed the simulation and system characterization to ensure all DDR2 interface timings
in this solution are met.
TI only supports designs that follow the board design guidelines outlined in the SPRAAW8
application report.
Table 7-38. Timing Requirements for DDRREFCLK(N|P)(1)
(see Figure 7-23)
NO.
1
PARAMETERS
MIN
15
MAX UNIT
tc(DDRREFCLK)
tw(DDRREFCLKH)
tw(DDRREFCLKL)
tt(DDRREFCLK)
tj(DDRREFCLK)
Cycle time, DDRREFCLK(N|P)
25
ns
ns
ns
ps
ps
2
Pulse duration, DDRREFCLK(N|P) high
Pulse duration, DDRREFCLK(N|P) low
Transition time, DDRREFCLK(N|P)
Period jitter (peak-to-peak), DDRREFCLK(N|P)
0.4C
0.4C
50
3
4
1300
5
0.02 x
tc(DDRREFCLK)
(1) C=1/DDRREFCLK(N|P)
5
1
4
2
DDRREFCLK(N|P)
3
4
Figure 7-23. DDRREFCLK(N|P) Timing
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7.11 I2C Peripheral
The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit
data to/from the DSP through the I2C module.
7.11.1 I2C Device-Specific Information
The C6474 device includes an I2C peripheral module (I2C). NOTE: when using the I2C module, ensure
there are external pullup resistors on the SDA and SCL pins.
The I2C modules on the C6474 may be used by the DSP to control local peripherals ICs (DACs, ADCs,
etc.) or may be used to communicate with other controllers in a system or to implement a user interface.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to remove noise 50 ns or less
7- and 10-Bit Device Addressing Modes
Multi-Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
Figure 7-24 is a block diagram of the I2C module.
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Figure 7-24. I2C Module Block Diagram
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7.11.2 I2C Peripheral Register Description(s)
The memory map of the I2C is shown in Table 7-39.
Table 7-39. I2C Registers
HEX ADDRESS
02B0 4000
ACRONYM
REGISTER NAME
ICOAR
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
ICPID1
ICPID2
-
I2C Own Address Register
02B0 4004
I2C Interrupt Mask/Status Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
02B0 4008
02B0 400C
02B0 4010
02B0 4014
02B0 4018
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
02B0 401C
02B0 4020
02B0 4024
02B0 4028
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
02B0 402C
02B0 4030
02B0 4034
I2C Peripheral Identification Register 1 [Value: 0x0000 0105]
I2C Peripheral Identification Register 2 [Value: 0x0000 0005]
Reserved
02B0 4038
02B0 403C - 02B0 405C
02B0 4060 - 02B0 407F
02B0 4080 - 02B3 FFFF
-
Reserved
-
Reserved
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7.11.3 I2C Electrical Data/Timing
Table 7-40. Timing Requirements for I2C Timings(1)
(see Figure 7-25)
NO.
STANDARD MODE
FAST MODE
UNIT
MIN
10
MAX
MIN
2.5
MAX
1
2
tc(SCL)
Cycle time, SCL
μs
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7
0.6
3
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
4
0.6
μs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
μs
μs
μs
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SDLH)
th(SDA-SDLL)
Setup time, SDA valid before SCL high
250
0(3)
Hold time, SDA valid after SCL low (for I2C
0
0.9(4)
bus™ devices)
8
tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions.
4.7
1.3
μs
9
tr(SDA)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
μs
10
11
12
13
tr(SCL)
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
0.6
tf(SDA)
tf(SCL)
300
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high (for
STOP condition)
4
14
15
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50
ns
(5)
Cb
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement, tsu(SDA-SCLH)≥ 250 ns, must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line, Tr max + Tsu(SDA-SCLH) = 1000 + 250 + 1250 ns
(according to the standard-mode I2C-bus specification), before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum, th(SDA-SCLL), has only to be met if the device does not stretch the low period, tw(SCLL), of the SCL signal.
(5) Cb = total capacitance of one bus line, in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 7-25. I2C Receive Timings
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(1)
Table 7-41. Switching Characteristics for I2C Timings
(see Figure 7-26)
NO.
STANDARD MODE
FAST MODE
UNIT
MIN
10
MAX
MIN
2.5
MAX
16
17
tc(SCL)
Cycle time, SCL
μs
μs
td(SCLH-SDAL)
Delay time, SCL high to SDA low (for a
repeated START condition)
4.7
0.6
18
td(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START
and a repeated START condition)
4
0.6
μs
19
20
21
22
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
ns
μs
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SDLH)
ttw(SDLL-SDAV)
Delay time, SDA valid to SCL high
250
0
Valid time, SDA valid after SCL low (for PC
bus devices)
0.9
23
Tw(SDAH)
Pulse duration, SDA high between STOP and
START conditions
4.7
1.3
μs
(1)
24
25
26
27
28
tr(SDA)
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
μs
(1)
(1)
(1)
tr(SDL)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
tf(SDA)
tf(SCL)
td(SCLH-SDAH)
Delay time, SCL high to SDA high (for STOP
condition)
4
0.6
29
Cp
Capacitance for each I2C pin
10
10
pF
(1) Cb = total capacitance of one bus line, in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 7-26. I2C Transmit Timings
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7.12 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
•
External shift clock or an internal, programmable frequency shift clock for data transfer
SPI operation in master mode only
For more detailed information on the McBSP peripheral, see the TMS320C6474 DSP Multichannel
Buffered Serial Port (McBSP) Reference Guide (literature number SPRUG17).
7.12.1 McBSP Device-Specific Information
The CLKS signal for MCBSP0 and MCBSP1 can be sourced from an external pin or by PLL Controller 1.
For details, see Section 7.8. If the clock from the PLL Controller 1 is used, the clock is shared between the
two McBSPs.Figure 7-27 shows the sample rate generator clock (CLKSRG) selection logical diagram.
Internal Clock Source
CPU/6
1
CLKSRG
0
CLKS
1
0
chip_clks
CPU/n,
Where n = 8 to 32
CLKSM
DEVCFG.CLKS0/1
A. For more details, see SYSCLK11 description in Section 7.8.1.1.
Figure 7-27. Sample Rate Generator Clock (CLKSRG)
7.12.2 McBSP Peripheral Register Descriptions
The memory map of the McBSP 0 registers is shown in Table 7-42.
Table 7-42. McBSP 0 Registers
HEX ADDRESS
ACRONYM
REGISTER NAME
028C 0000
DRR0
McBSP0 Data Receive Register via Configuration Bus.
Note: The CPU and EDMA3 controller can only read this register; they can not
write to it.
3000 0000
028C 0004
3000 0010
028C 0008
028C 000C
028C 0010
028C 0014
028C 0018
028C 001C
028C 0020
028C 0024
DRR0
DXR0
McBSP0 Data Receive Register via EDMA3 Bus
McBSP0 Data Transmit Register via Configuration Bus
McBSP0 Data Transmit register via EDMA bus
McBSP0 Serial Port Control Register
DXR0
SPCR0
RCR0
McBSP0 Receive Control Register
XCR0
McBSP0 Transmit Control Register
SRGR0
MCR0
McBSP0 Sample Rate Generator Register
McBSP0 Multichannel Control Register
RCERE00
XCERE00
PCR0
McBSP0 Enhanced Receive Channel Enable Register 0 Partition A/B
McBSP0 Enhanced Transmit Channel Enable Register 0 Partition A/B
McBSP0 Pin Control Register
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Table 7-42. McBSP 0 Registers (continued)
HEX ADDRESS
028C 0028
028C 002C
028C 0030
028C 0034
028C 0038
028C 003C
ACRONYM
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
-
REGISTER NAME
McBSP0 Enhanced Receive Channel Enable Register 0 Partition C/D
McBSP0 Enhanced Transmit Channel Enable Register 0 Partition C/D
McBSP0 Enhanced Receive Channel Enable Register 0 Partition E/F
McBSP0 Enhanced Transmit Channel Enable Register 0 Partition E/F
McBSP0 Enhanced Receive Channel Enable Register 0 Partition G/H
McBSP0 Enhanced Transmit Channel Enable Register 0 Partition G/H
Reserved
028C 0040 - 028C 00FF
The memory map of the McBSP 1 registers is shown in Table 7-43.
Table 7-43. McBSP 1 Registers
HEX ADDRESS
ACRONYM
REGISTER NAME
028D 0000
DRR1
McBSP1 Data Receive Register via Configuration Bus.
Note: The CPU and EDMA3 controller can only read this register; they can not
write to it.
3400 0000
028D 0004
DRR1
DXR1
McBSP1 Data Receive Register via EDMA3 Bus
McBSP1 Data Transmit Register via Configuration Bus
McBSP1 Data Transmit Register via EDMA Bus
McBSP1 Serial Port Control Register
3400 0010
DXR1
028D 0008
SPCR1
RCR1
028D 000C
028D 0010
McBSP1 Receive Control Register
XCR1
McBSP1 Transmit Control Register
028D 0014
SRGR1
MCR1
McBSP1 Sample Rate Generator Register
028D 0018
McBSP1 Multichannel Control Register
028D 001C
028D 0020
RCERE01
XCERE01
PCR1
McBSP1 Enhanced Receive Channel Enable Register 0 Partition A/B
McBSP1 Enhanced Transmit Channel Enable Register 0 Partition A/B
McBSP1 Pin Control Register
028D 0024
028D 0028
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE3
-
McBSP1 Enhanced Receive Channel Enable Register 0 Partition C/D
McBSP1 Enhanced Transmit Channel Enable Register 0 Partition C/D
McBSP1 Enhanced Receive Channel Enable Register 0 Partition E/F
McBSP1 Enhanced Transmit Channel Enable Register 0 Partition E/F
McBSP1 Enhanced Receive Channel Enable Register 0 Partition G/H
McBSP1 Enhanced Transmit Channel Enable Register 0 Partition G/H
Reserved
028D 002C
028D 0030
028D 0034
028D 0038
028D 003C
028D 0040 - 028D 00FF
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7.12.3 McBSP Electrical Data/Timing
Table 7-44. Timing Requirements for McBSP(1)
(see Figure 7-28)
NO.
MIN
MAX UNIT
2
3
5
tc(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
10P(2)
0.5t c(CKRX)-1(2)
ns
ns
ns
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low CLKR int
CLKR ext
9
1.3
6
6
7
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
ns
ns
ns
ns
ns
3
8
0.9
3
8
3.1
9
10
11
Setup time, external FSX high before CLKX low CLKR int
CLKR ext
1.3
6
Hold time, external FSX high after CLKX low
CLKR int
CLKR ext
3
(1) P = 1/CPU Clock in ns.
(2) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty
cycles.
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Table 7-45. Switching Characteristics Over Recommended Operating Conditions for McBSP(1) (2)
(see Figure 7-28)
NO.
MIN
MAX UNIT
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X
generated from CLKS input.(3)
1.4
10
ns
2
3
tc(CKRX)
tw(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
10P(4)
C - 1(5)
ns
ns
Pulse duration, CLKR/X high or
CLKR/X low
C + 1(5)
3
4
9
td(CKRH-FRV)
td(CKXH-FXV)
Delay time, CLKR high to internal CLKR int
FSR valid
-2.1
ns
ns
Delay time, CLKX high to internal CLKX int
FSX valid
-1.7
1.7
3
9
4
9
CLKX ext
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance CLKX int
following last data bit from CLKX
high
-3.9
2.1
ns
ns
CLKX ext
CLKX int
Delay time, CLKX high to DX valid CLKX ext (DXENA = 0)
CLKX ext (DXENA = 1)
-3.9 +D1(6)
2.1(6)
2.1 + D1(6)
-2.3 + D1(7)
1.9 + D1(7)
4 + D2(6)
9(6)
9 + D2(6)
5.6 + D2(7)
9 + D2(7)
13
14
td(CKXH-DXV)
Delay time, FSX high to DX valid
ONLY applies when in data delay
0 (XDATDLY = 00b)mode
FSX int
FSX ext
ns
td(FXH-DXV)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
(4) P = 1/CPU clock frequency, in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(5) C = H or L S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the
maximum limit (see (4) above).
(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 6P, D2 = 12P
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Figure 7-28. McBSP Timing
Table 7-46. Timing Requirements for FSR When GSYNC = 1
(see Figure 7-29)
NO.
MIN
4
MAX UNIT
1
2
tsu(FRH-CKSH)
th(CKSH-FRH)
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
4
CLKS
1
2
FSR External
CLKR/X
(No Need to Resync)
CLKR/X
(Needs to Resync)
Figure 7-29. FSR Timing When GSYNC = 1
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Table 7-47. Timing Requirements for McBSP as SPI Master: CLKSTP = 10b, CLKXP = 0(1)
(see Figure 7-30)
MASTER
SLAVE
MIN
NO.
UNIT
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 - 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-48. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master: CLKSTP = 10b, CLKXP = 0(1)
(see Figure 7-30)
MASTER(2)
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
T + 3
L + 3
4
MAX
1
2
3
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXH-DXV)
Hold time, FSX low after CLKX low(3)
Delay time, FSX low to CLKX high(4)
Delay time, CLKX high to DX valid
T - 2
ns
ns
ns
L - 2
-2
18P + 2.8
30P + 17
Disable time, DX high impedance following
last data bit from CLKX low
6
tdis(CKXL-DXHZ)
L - 2
L + 3
ns
Disable time, DX high impedance following
last data bit from FSX high
7
8
tdis(FXH-DXHZ)
td(FXL-DXV)
6P + 3
18P + 17
24P + 17
ns
ns
Delay time, FSX low to DX valid
12P + 2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(3) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
7
8
6
3
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
DX
DR
Bit 0
4
5
(n-2)
(n-3)
(n-4)
Bit 0
Figure 7-30. McBSP Timing as SPI Master: CLKSTP = 10b, CLKXP = 0
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Table 7-49. Timing Requirements for McBSP as SPI Master: CLKSTP = 11b, CLKXP = 0(1)
(see Figure 7-31)
MASTER
SLAVE
MIN
NO.
UNIT
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 - 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-50. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master: CLKSTP = 11b, CLKXP = 0(1)
(see Figure 7-31)
MASTER(2)
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
L + 3
T + 3
4
MAX
1
2
3
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXL-DXV)
Hold time, FSX low after CLKX low(3)
Delay time, FSX low to CLKX high(4)
Delay time, CLKX low to DX valid
L - 2
ns
ns
ns
T - 2
-2
18P + 2.8
18P + 3
12P + 2
30P + 17
30P + 17
24P + 17
Disable time, DX high impedance following
last data bit from CLKX low
6
7
tdis(CKXL-DXHZ)
td(FXL-DXV)
-2
4
ns
ns
Delay time, FSX low to DX valid
H - 2
H + 4
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(3) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
DX
6
7
3
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
4
5
(n-2)
(n-3)
(n-4)
DR
Bit 0
Figure 7-31. McBSP Timing as SPI Master: CLKSTP = 11b, CLKXP = 0
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Table 7-51. Timing Requirements for McBSP as SPI Master: CLKSTP = 10b, CLKXP = 1(1)
(see Figure 7-32)
MASTER
SLAVE
MIN
NO.
UNIT
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 - 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-52. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master: CLKSTP = 10b, CLKXP = 1(1)
(see Figure 7-32)
MASTER(2)
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
T + 3
H + 3
4
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXL-DXV)
Hold time, FSX low after CLKX high(3)
Delay time, FSX low to CLKX low(4)
Delay time, CLKX low to DX valid
T - 2
ns
ns
ns
H - 2
-2
18P + 2.8
30P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
tdis(CKXH-DXHZ)
H - 2
H + 3
ns
Disable time, DX high impedance following
last data bit from FSX high
7
8
tdis(FXH-DXHZ)
td(FXL-DXV)
6P + 3
18P + 17
24P + 17
ns
ns
Delay time, FSX low to DX valid
12P + 2
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(3) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
6
2
FSX
7
3
8
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
DX
DR
Bit 0
4
5
(n-2)
(n-3)
(n-4)
Bit 0
Figure 7-32. McBSP Timing as SPI Master: CLKSTP = 10b, CLKXP = 1
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Table 7-53. Timing Requirements for McBSP as SPI Master: CLKSTP = 11b, CLKXP = 1(1)
(see Figure 7-33)
MASTER
SLAVE
MIN
NO.
UNIT
MIN
12
4
MAX
MAX
4
5
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 - 18P
5 + 36P
ns
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
Table 7-54. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master: CLKSTP = 11b, CLKXP = 1(1)
(see Figure 7-33)
MASTER(2)
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
H + 3
T + 1
4
MAX
1
2
3
th(CKXH-FXL)
td(FXL-CKXL)
td(CKXH-DXV)
Hold time, FSX low after CLKX high(3)
Delay time, FSX low to CLKX low(4)
Delay time, CLKX high to DX valid
H - 2
ns
ns
ns
T - 2
-2
18P + 2.8
18P + 3
12P + 2
30P + 17
30P + 17
24P + 17
Disable time, DX high impedance following
last data bit from CLKX high
6
7
tdis(CKXH-DXHZ)
td(FXL-DXV)
-2
4
ns
ns
Delay time, FSX low to DX valid
L - 2
L + 4
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
(2) S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)
S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(3) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
(4) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
4
5
(n-2)
(n-3)
(n-4)
DR
Bit 0
Figure 7-33. McBSP Timing as SPI Master: CLKSTP = 11b, CLKXP = 1
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7.13 Ethernet MAC (EMAC)
The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6474
DSP core processor and the networked community. The EMAC supports 1000BaseT (1000 Mbps) in
full-duplex mode, with hardware flow control and quality-of-service (QOS) support.
The EMAC module conforms to the IEEE 802.3-2002 standard, describing the “Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications. The IEEE
802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).
Deviation from this standard, the EMAC module does not use the Transmit Coding Error signal MTXER.
Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will
intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame
will be detected as an error by the network.
The EMAC control module is the main interface between the device core processor, the MDIO module,
and the EMAC module. The relationship between these three components is shown in Figure 7-34. The
EMAC control module contains the necessary components to allow the EMAC to make efficient use of
device memory, plus it controls device interrupts. The EMAC control module incorporates 8K-bytes of
internal RAM to hold EMAC buffer descriptors.
Figure 7-34. EMAC, MDIO, and EMAC Control Modules
For more detailed information on the EMAC/MDIO, see the TMS320C6474 DSP EMAC/MDIO Module
Reference Guide (literature number SPRUG08).
7.13.1 EMAC Device-Specific Information
The EMAC module on the device supports Serial Gigabit Media Independent Interface (SGMII). The
SGMII interface conforms to version 1.8 of the industry standard specification.
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7.13.2 EMAC Peripheral Register Descriptions
The memory maps of the EMAC are shown in Table 7-55 to Table 7-57.
Table 7-55. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS
02C8 0000
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
02C8 0004
TXCONTROL
TXTEARDOWN
-
02C8 0008
Transmit Teardown register
02C8 000F
Reserved
02C8 0010
RXIDVER
Receive Identification and Version Register
Receive Control Register
02C8 0014
RXCONTROL
RXTEARDOWN
-
02C8 0018
Receive Teardown Register
02C8 001C
Reserved
02C8 0020 - 02C8 007C
02C8 0080
-
Reserved
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACE0IVECTOR
-
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
02C8 0084
02C8 0088
02C8 008C
02C8 0090
02C8 0094
MAC End of Interrupt Vector Register
Reserved
02C8 0098 - 02C8 019C
02C8 00A0
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
-
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Reserved
02C8 00A4
02C8 00A8
02C8 00AC
02C8 00B0
02C8 00B4
02C8 00B8
02C8 00BC
02C8 00C0 - 02C8 00FC
02C8 0100
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
02C8 0104
02C8 0108
02C8 010C
Receive Maximum Length Register
02C8 0110
RXBUFFEROFFSET
Receive Buffer Offset Register
02C8 0114
RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
02C8 0118 - 02C8 011C
02C8 0120
-
Reserved
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
02C8 0124
02C8 0128
02C8 012C
02C8 0130
02C8 0134
02C8 0138
02C8 013C
02C8 0140
02C8 0144
02C8 0148
02C8 014C
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Table 7-55. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
02C8 0150
02C8 0154
02C8 0158
02C8 015C
02C8 0160
02C8 0164
02C8 0168
02C8 016C
02C8 0170
02C8 0174
ACRONYM
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
EMCONTROL
FIFCONTROL
MACCONFIG
SOFTRESET
REGISTER NAME
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
Emulation Control Register
FIFO Control Register (Transmit and Receive)
MAC Configuration Register
Soft Reset Register
02C8 0178 - 02C8 01CC
02C8 01D0
02C8 01D4
02C8 01D8
02C8 01DC
02C8 01E0
02C8 01E4
02C8 01E8
02C8 01EC
02C8 01F0 - 02C8 01FC
02C8 0200
02C8 0204
02C8 0208
02C8 020C
02C8 0210
02C8 0214
02C8 0218
02C8 021C
02C8 0220
02C8 0224
02C8 0228
02C8 022C
02C8 0230
02C8 0234
02C8 0238
02C8 023C
02C8 0240
02C8 0244
02C8 0248
02C8 024C
02C8 0250
02C8 0254
02C8 0258
02C8 025C
02C8 0260
02C8 0264
02C8 0268
-
Reserved
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MAC Source Address Low Bytes Register (Lower 32-bits)
MAC Source Address High Bytes Register (Upper 32-bits)
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TRACETEST
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
RXPAUSE
TXPAUSE
Transmit Pause Timer Register
Reserved
-
RXGOODFRAMES
RXBCASTFRAMES
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Good Receive Frames Register
Broadcast Receive Frames Register
Multicast Receive Frames Register
Pause Receive Frames Register
Receive CRC Errors Register
RXALIGNCODEERRORS Receive Alignment/Code Errors Register
RXOVERSIZED
RXJABBER
Receive Oversized Frames Register
Receive Jabber Frames Register02C80220
Receive Undersized Frames Register
Receive Frame Fragments Register
Filtered Receive Frames Register
RXUNDERSIZED
RXFRAGMENTS
RXFILTERED
RXQOSFILTERED
RXOCTETS
Receive QOS Filtered Frames Register
Receive Octet Frames Register
TXGOODFRAMES
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
TXCOLLISION
Good Transmit Frames Register
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
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Table 7-55. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
02C8 0280
02C8 0284
02C8 0288
02C8 028C
ACRONYM
FRAME65T127
REGISTER NAME
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns
Register
02C8 0300 - 02C8 03FC
02C8 0400 - 02C8 04FC
02C8 0500
-
Reserved
Reserved
-
MACADDRLO
MAC Address Low Bytes Register (used in Receive Address
Matching)
02C8 0504
MACADDRHI
MAC Address High Bytes Register (used in Receive Address
Matching)
02C8 0508
02C8 050C - 02C8 05FC
02C8 0600
MACINDEX
-
MAC Index Register
Reserved
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive t Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive t Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive t Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive t Channel 7 DMA Head Descriptor Pointer Register
02C8 0604
02C8 0608
02C8 060C
02C8 0610
02C8 0614
02C8 0618
02C8 061C
02C8 0620
02C8 0624
02C8 0628
02C8 062C
02C8 0630
02C8 0634
02C8 0638
02C8 063C
02C8 0640
Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0644
02C8 0648
02C8 064C
02C8 0650
02C8 0654
02C8 0658
02C8 065C
TX1CP
TX2CP
TX3CP
TX4CP
TX5CP
TX6CP
TX7CP
Transmit Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Transmit Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
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Table 7-55. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02C8 0660
RX0CP
Receive Channel 0 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0664
02C8 0668
02C8 066C
02C8 0670
02C8 0674
02C8 0678
02C8 067C
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
RX7CP
Receive Channel 1 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 2 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 3 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 4 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 5 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 6 Completion Pointer (Interrupt Acknowledge)
Register
Receive Channel 7 Completion Pointer (Interrupt Acknowledge)
Register
02C8 0680 - 02C8 06FC
02C8 0700 - 02C8 077C
02C8 0780 - 02C8 0FFF
-
-
-
Reserved
Reserved
Reserved
Table 7-56. EMAC Statistics Registers
HEX ADDRESS
02C8 0200
ACRONYM
REGISTER NAME
RXGOODFRAMES
RXBCASTFRAMES
Good Receive Frames Register
02C8 0204
Broadcast Receive Frames Register (Total number of
Good Broadcast Frames Receive)
02C8 0208
RXMCASTFRAMES
Multicast Receive Frames Register (Total number of Good
Multicast Frames Received)
02C8 020C
02C8 0210
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register (Total number of Frames
Received with CRC Errors)
02C8 0214
02C8 0218
02C8 021C
02C8 0220
RXALIGNCODEERRORS
RXOVERSIZED
Receive Alignment/Code Errors register (Total number of
frames Received with alignment/code errors)
Receive Oversized Frames Register (Total number of
Oversized Frames Received)
RXJABBER
Receive Jabber Frames Register (Total number of Jabber
Frames Received)
RXUNDERSIZED
Receive Undersized Frames Register (Total number of
Undersized Frames Received)
02C8 0224
02C8 0228
02C8 022C
02C8 0230
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERERED
RXOCTETS
Receive Octet Frames Register (Total number of
Received Bytes in Good Frames)
02C8 0234
TXGOODFRAMES
Good Transmit Frames Register (Total number of Good
Frames Transmitted)
02C8 0238
02C8 023C
02C8 0240
02C8 0244
02C8 0248
02C8 024C
02C8 0250
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
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Table 7-56. EMAC Statistics Registers (continued)
HEX ADDRESS
02C8 0254
02C8 0258
02C8 025C
02C8 0260
02C8 0264
02C8 0268
02C8 026C
02C8 0270
02C8 0274
02C8 0278
02C8 027C
ACRONYM
TXEXCESSIVECOLL
TXLATECOLL
REGISTER NAME
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Under Run Error Register
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames
Register
02C8 0280
02C8 0284
02C8 0288
02C8 028C
NETOCTETS
Network Octet Frames Register
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame
Overruns Register
02C8 0290 - 02C8 02FC
-
Reserved
Table 7-57. EMAC Descriptor Memory
HEX ADDRESS
ACRONYM
REGISTER NAME
02C8 2000 - 02C8 3FFF
-
EMAC Descriptor Memory
Table 7-58. SGMII Control Registers
HEX ADDRESS
02C4 0000
ACRONYM
REGISTER NAME
Identification and Version Register
IDVER
02C4 0004
SOFT_RESET
Software Reset Register
Control Register
02C4 0010
CONTROL
02C4 0014
STATUS
Status Register
02C4 0018
MR_ADV_ABILITY
Advertised Ability Register
Reserved
02C4 001C
-
02C4 0020
MR_LP_ADV_ABILITY
Link Partner Advertised Ability Register
Reserved
02C4 0024
-
02C4 0030
TX_CFG
RX_CFG
AUX_CFG
-
Transmit Configuration Register
Receive Configuration Register
Auxiliary Configuration Register
Reserved
02C4 0034
02C4 0038
02C4 0040 - 02C4 0048
Table 7-59. EMAC Interrupt Control (EMIC) Registers
HEX ADDRESS
02C8 1000
02C8 1004
02C8 1008
02C8 100C
02C8 1010
02C8 1014
02C8 1018
ACRONYM
IDVER
REGISTER NAME
Identification and Version Register
Software Reset Register
SOFT_RESET
EM_CONTROL
INT_CONTROL
C0_RX_THREST_EN
C0_RX_EN
Emulation Control Register
Interrupt Control Register
Core 0 Receive Threshold Interrupt Enable Register
Core 0 Receive Interrupt Enable Register
Core 0 Transmit Interrupt Enable Register
C0_TX_EN
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Table 7-59. EMAC Interrupt Control (EMIC) Registers (continued)
HEX ADDRESS
02C8 101C
02C8 1020
02C8 1024
02C8 1028
02C8 102C
02C8 1030
02C8 1034
02C8 1038
02C8 103C
02C8 1040
02C8 1044
02C8 1048
02C8 104C
02C8 1050
02C8 1054
02C8 1058
02C8 105C
02C8 1060
02C8 1064
02C8 1068
02C8 106C
02C8 1070
02C8 1074
02C8 1078
02C8 107C
02C8 1080
02C8 1084
ACRONYM
C0_MISC_EN
C1_RX_THRESH_EN
C1_RX_EN
REGISTER NAME
Core 0 Miscellaneous Interrupt Enable Register
Core 1 Receive Threshold Interrupt Enable Register
Core 1 Receive Interrupt Enable Register
C1_RX_EN
Core 1 Transmit Interrupt Enable Register
Core 1 Miscellaneous Interrupt Enable Register
Core 2 Receive Threshold Interrupt Enable Register
Core 2 Receive Interrupt Enable Register
C1_MISC_EN
C2_RX_THRESH_EN
C2_RX_EN
C2_RX_EN
Core 2 Transmit Interrupt Enable Register
Core 2 Miscellaneous Interrupt Enable Register
C2_MISC_EN
C0_RX_THRESH_STAT Core 0 Receive Threshold Masked Interrupt Status Register
C0_RX_STAT
C0_TX_STAT
Core 0 Receive Interrupt Masked Interrupt Status Register
Core 0 Transmit Interrupt Masked Interrupt Status Register
Core 0 Miscellaneous Interrupt Masked Interrupt Status Register
C0_MISC_STAT
C1_RX_THRESH_STAT Core 1 Receive Threshold Masked Interrupt Status Register
C1_RX_STAT
C1_TX_STAT
Core 1 Receive Masked Interrupt Status Register
Core 1 Transmit Masked Interrupt Status Register
Core 1 Miscellaneous Masked Interrupt Status Register
C1_MISC_STAT
C2_RX_THRESH_STAT Core 2 Receive Threshold Masked Interrupt Status Register
C2_RX_STAT
C2_TX_STAT
C2_MISC_STAT
C0_RX_IMAX
C0_TX_IMAX
C1_RX_IMAX
C1_TX_IMAX
C2_RX_IMAX
C2_TX_IMAX
Core 2 Receive Masked Interrupt Status Register
Core 2 Transmit Masked Interrupt Status Register
Core 2 Miscellaneous Masked Interrupt Status Register
Core 0 Receive Interrupts Per Millisecond
Core 0 Transmit Interrupts Per Millisecond
Core 1 Receive Interrupts Per Millisecond
Core 1 Transmit Interrupts Per Millisecond
Core 2 Receive Interrupts Per Millisecond
Core 2 Transmit Interrupts Per Millisecond
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7.13.3 EMAC Electrical Data/Timing (SGMII)
The TMS320C6474 Hardware Design Guide application report (literature number SPRAAW7) specifies a
complete EMAC anc SGMII interface solutions for the C6474 device as well as a list of compatible EMAC
and SGMII devices. TI has performed the simulation and system characterization to ensure all EMAC and
SGMII interface timings in this solution are met.
TI only supports designs that follow the board design guidelines outlined in the SPRAAW7
application report.
Table 7-60. Timing Requirements for SRIOSGMIIREFCLK(N|P)(1)
(see Figure 7-35)
NO.
1
PARAMETERS
Cycle time, SRIOSGMIIREFCLK(N|P)
Pulse duration, CLK(N|P) high
Pulse duration, CLK(N|P) low
Transition time, CLK(N|P)
MIN
3.2
MAX UNIT
tc(SRIOSGMIIREFCLK)
tw(CLKH)
8
ns
ns
ns
ps
ps
2
0.4C
0.4C
50
3
tw(CLKL)
4
tt(CLK)
1300
4
5
tj(CLK)
Period Jitter (RMS), CLK(N|P)
(1) C=1/SRIOSGMIIREFCLK(N|P)
1
4
2
SRIOSGMIIREFCLK(N|P)
3
4
Figure 7-35. SRIOSGMIIREFCLK(N|P) Timing
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7.14 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY
attached to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC
module for correct operation. The module is designed to allow almost transparent operation of the MDIO
interface, with very little maintenance from the core processor.
The EMAC control module is the main interface between the device core processor, the MDIO module,
and the EMAC module. The relationship between these three components is shown in Figure 7-34.
For more detailed information on the EMAC/MDIO, see the TMS320C6474 DSP EMAC/MDIO Module
Reference Guide (literature number SPRUG08).
7.14.1 MDIO Peripheral Register Description(s)
The memory map of the MDIO is shown in Table 7-61.
Table 7-61. MDIO Registers
HEX ADDRESS
02C8 1800
ACRONYM
VERSION
REGISTER NAME
MDIO Version Register
MDIO Control Register
02C8 1804
CONTROL
02C8 1808
ALIVE
MDIO PHY Alive Status Register
02C8 180C
LINK
MDIO PHY Link Status Register
02C8 1810
LINKINTRAW
LINKINTMASKED
-
MDIO link Status Change Interrupt (unmasked) Register
MDIO link Status Change Interrupt (masked) Register
Reserved
02C8 1814
02C8 1818 - 02C8 181C
02C8 1820
USERINTRAW
USERINTMASKED
USERINTMASKSET
USERINTMASKCLEAR
-
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
02C8 1824
02C8 1828
02C8 182C
02C8 1830 - 02C8 187C
02C8 1880
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
-
MDIO User Access Register 0
02C8 1884
MDIO User PHY Select Register 0
02C8 1888
MDIO User Access Register 1
02C8 188C
MDIO User PHY Select Register 1
02C8 1890 - 02C8 1FFF
Reserved
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7.14.2 MDIO Electrical Data/Timing
Table 7-62. Timing Requirements for MDIO Inputs
(see Figure 7-36)
NO.
MIN
400
180
180
MAX UNIT
1
2a
2b
3
tc(MDCLK)
Cycle time, MDCLK
ns
ns
ns
tw(MDCLK)
Pulse duration, MDCLK high
tw(MDCLK)
Pulse duration, MDCLK low
tt(MDCLK)
Transition time, MDCLK
5
ns
ns
ns
4
tsu(MDIO-MDCLKH)
th(MDCLKH-MDIO)
Setup time, MDIO data input valid before MDCLK high
Hold time, MDIO data input valid after MDCLK high
10
10
5
1
MDCLK
4
5
MDIO
(input)
Figure 7-36. MDIO Input Timing
Table 7-63. Switching Characteristics Over Recommended Operating Conditions for MDIO Outputs
(see Figure 7-37)
NO.
MIN
MAX UNIT
100 ns
7
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
1
MDCLK
7
MDIO
(input)
Figure 7-37. MDIO Output Timing
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7.15 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send
synchronization event so the EDMA3 channel controller.
7.15.1 Timers Device-Specific Information
The device has six general purpose timers: Timer0 to Timer5, each of which can be configured as a
general purpose timer or a watchdog timer. When configured as a general-purpose timer, each timer can
be programmed as a 64-bit timer or as two separate 32-bit timers.
Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pinout is
described in the next section.
7.15.1.1 Timer I/O Selection
Not all timer inputs and outputs are pinned out of the device. The six timers have a flexible (e.g. software
controlled) selection of timer inputs and outputs. At the chip level there are four timer pins, two input pins
(TIMI[1:0]) and two output pins (TIMO[1:0]). Each timer input can be configured to be driven by either of
the timer input pins, or by an FSYNC event (FSEVT[3:2]). Each output pin can be driven by any of the
timer outputs. This is programmable through software via the Timer Pin Manager Block, as shown in the
Figure 7-38. Not shown in the figure is the logic that gates the timer resets that are routed to the PLL
controller, shown in Figure 7-39.
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FSEVT2
FSEVT3
TIMI0
TIMI1
SYSCLK/6
TIMO0
TIMO1
TINPHSEL 0
TINPLSEL 0
TINPHSEL 1
TINPLSEL 1
TINPHSEL 2
TINPLSEL 2
TINPHSEL 3
TINPLSEL 3
TINPHSEL 4
TINPLSEL 4
TINPHSEL 5
TINPLSEL 5
TOUTSEL 1
TOUTSEL 0
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3 4 5 6 7 8 91011
0 1 2 3 4 5 6 7 8 91011
Timer Pin Manager
(TPMGR)
Timer64
0
Timer64
1
Timer642
2
Timer64
3
Timer64
4
Timer64
5
32
CFG SCR
(SCR F)
vbusp
Figure 7-38. Timer Manager Block Diagram
Note that the TMS320C6474 DSP 64-Bit Timer User’s Guide (literature number SPRUG18) uses different
labels for its inputs and outputs. To avoid confusion with respect to numbering, a different convention is
used in this document, as shown in Table 7-64.
Table 7-64. Timer Pin Naming
TIMER
SIGNAL NAME
RENAMED TO
DESCRIPTION
n
TINP12
TINPLn
Timer n input event (low half). Used to drive lower 32-bit timer, 64-bit timer.
Used in watchdog mode.
n
n
n
TINP34
TOUT12
TOUT34
TINPHn
TOUTLn
TOUTHn
Timer n input event (high half). Used to drive upper 32-bit timer. Unused in
64-bit or watchdog modes.
Timer n output (low half). Driven by lower 32-bit timer, 64-bit timer, or
watchdog timer as either a pulse or waveform.
Timer n output (high half). Driven by upper 32-bit timer as either a pulse or
waveform. Unused in 64-bit or watchdog modes.
7.15.1.1.1 Timer Input Selection Register (TINPSEL)
Timer input selection is handled in the Timer input selection register (TINPSEL). The TINPSEL register is
shown in Figure 7-39 and described in Table 7-65.
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31
24
8
23
22
21
20
19
18
17
16
Reserved
TINPHSEL5
R/W-01
TINPLSEL5
R/W-00
TINPHSEL4
R/W-01
TINPLSEL4
R/W-00
R-00000000
15
14
13
12
11
10
9
7
6
5
4
3
2
1
0
TINPHSEL3
R/W-01
TINPLSEL3
R/W-00
TINPHSEL2
R/W-01
TINPLSEL2
R/W-00
TINPHSEL1
R/W-01
TINPLSEL1
R/W-00
TINPHSEL0
R/W-01
TINPLSEL0
R/W-00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-39. Timer Input Selection Register (TINPSEL)
Table 7-65. Timer Input Selection Register (TINPSEL) Field Descriptions
Bit
Field
Value Description
Reserved
31-24 Reserved
23:22 TINPHSEL5
Input Select for TIMER 5 High
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
21:20 TINPLSEL5
19:18 TINPHSEL4
17:16 TINPLSEL4
15:14 TINPHSEL3
13:12 TINPLSEL3
11:10 TINPHSEL2
Input Select for TIMER 5 Low
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 4 High
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 4 Low
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 3 High
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 3 Low
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 2 High
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
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Table 7-65. Timer Input Selection Register (TINPSEL) Field Descriptions (continued)
Bit
Field
Value Description
Input Select for TIMER 2 Low
TIMI0
9:8
TINPLSEL2
00
01
10
11
TIMI1
FSEVT2
FSEVT3
7:6
5:4
3:2
1:0
TINPHSEL1
TINPLSEL1
TINPHSEL0
TINPLSEL0
Input Select for TIMER 1 High
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 1 Low
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 0 High
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
Input Select for TIMER 0 Low
00
01
10
11
TIMI0
TIMI1
FSEVT2
FSEVT3
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7.15.1.1.2 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled in the Timer output selection register (TOUTPSEL). The TOUTPSEL
register is shown in Figure 7-40 and described in Table 7-66.
31
15
16
Reserved
R-000000000000000000000000
8
7
4
3
0
Reserved
TOUTPSEL1
R/W-0001
TOUTPSEL0
R/W-0000
R-000000000000000000000000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-40. Timer Output Selection Register (TOUTPSEL)
Table 7-66. Timer Output Selection Register (TOUTPSEL) Field Descriptions
Bit
31:8
7:4
Field
Value Description
Reserved
Reserved
TOUTPSEL1
Output Select for TIMI1
0000 TOUTL0
0001 TOUTH0
0010 TOUTL1
0011 TOUTH1
0100 TOUTL2
0101 TOUTH2
0110 TOUTL3
0111 TOUTH3
1000 TOUTL4
1001 TOUTH5
1010 TOUTL5
1011 TOUTH5
Other Reserved
Output Select for TIMO0
0000 TOUTL0
0001 TOUTH0
0010 TOUTL1
0011 TOUTH1
0100 TOUTL2
0101 TOUTH2
0110 TOUTL3
0111 TOUTH3
1000 TOUTL4
1001 TOUTH5
1010 TOUTL5
1011 TOUTH5
Other Reserved
3:0
TOUTPSEL0
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7.15.1.2 Timer Watchdog Select
As mentioned previously, the timers can operate in watchdog mode. When in watchdog mode, the event
output from the timer can optionally reset the CPU. When used in this type of mode, Timer3, Timer4, and
Timer 5 correspond to C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule
Core 2, respectively. In order for the event not to trigger the reset when this operation is not desired, the
Timer watchdog reset selection register (WDRSTSEL) is created to turn this feature on/off. The
WDRSTSEL register is shown in Figure 7-41 and described in Table 7-67.
31
8
Reserved
R-0 0000 0000 0000 0000 0000 0000 0000
7
3
2
1
0
Reserved
WDRSTSEL5
R/W-0
WDRSTSEL4
R/W-0
WDRSTSEL3
R/W-0
R-0 0000 0000 0000 0000 0000 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 7-41. Timer Watchdog Reset Selection Register (WDRSTSEL)
Table 7-67. Timer Watchdog Reset Selection Register (WDRSTSEL) Field Descriptions
Bit
31:3
2:2
Field
Value Description
Reserved
Reserved
WRDSTSELn
Reset Select for Watchdog Timer
0
1
TOUTnL does not cause WDRSTSEL to assert to the corresponding C64x+ megamodule
TOUTnL causes a reset of the corresponding C64x+ megamodule via the host reset port of the
LPSC
7.15.2 Timers Peripheral Description(s)
Table 7-68. Timer 0 Registers
HEX ADDRESS
0291 0000
ACRONYM
PID
REGISTER NAME
Peripheral ID Register
0291 0004
EMUMGT_CLKSPD
Timer 0 Emulation Management/Clock Speed Register
Reserved
0291 0008
-
-
0291 000C
Reserved
0291 0010
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 0 Counter Register Low
Timer 0 Counter Register High
Timer 0 Period Register Low
Timer 0 Period Register High
Timer 0 Control Register
Timer 0 Global Control Register
Timer 0 Watchdog Timer Control Register
Reserved
0291 0014
0291 0018
0291 001C
0291 0020
0291 0024
0291 0028
0291 002C
0291 0030
-
Reserved
0291 0034 - 0291 FFFF
-
Reserved
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Table 7-69. Timer 1 Registers
HEX ADDRESS
0292 0000
0292 0004
0292 0008
0292 000C
0292 0010
0292 0014
0292 0018
0292 001C
0292 0020
0292 0024
0292 0028
0292 002C
0292 0030
ACRONYM
REGISTER NAME
PID
Peripheral ID Register
EMUMGT_CLKSPD
Timer 1 Emulation Management/Clock Speed Register
Reserved
-
-
Reserved
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 1 Counter Register Low
Timer 1 Counter Register High
Timer 1 Period Register Low
Timer 1 Period Register High
Timer 1 Control Register
Timer 1 Global Control Register
Timer 1 Watchdog Timer Control Register
Reserved
-
Reserved
0292 0034 - 0292 FFFF
-
Reserved
Table 7-70. Timer 2 Registers
HEX ADDRESS
0293 0000
ACRONYM
REGISTER NAME
Peripheral ID Register
PID
0293 0004
EMUMGT_CLKSPD
Timer 2 Emulation Management/Clock Speed Register
Reserved
0293 0008
-
-
0293 000C
Reserved
0293 0010
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 2 Counter Register Low
Timer 2 Counter Register High
Timer 2 Period Register Low
Timer 2 Period Register High
Timer 2 Control Register
Timer 2 Global Control Register
Timer 2 Watchdog Timer Control Register
Reserved
0293 0014
0293 0018
0293 001C
0293 0020
0293 0024
0293 0028
0293 002C
0293 0030
-
Reserved
0293 0034 - 0293 FFFF
-
Reserved
Table 7-71. Timer 3 Registers
HEX ADDRESS
0294 0000
0294 0004
0294 0008
0294 000C
0294 0010
0294 0014
0294 0018
0294 001C
0294 0020
0294 0024
0294 0028
0294 002C
0294 0030
ACRONYM
REGISTER NAME
PID
Peripheral ID Register
EMUMGT_CLKSPD
Timer 3 Emulation Management/Clock Speed Register
Reserved
-
-
Reserved
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 3 Counter Register Low
Timer 3 Counter Register High
Timer 3 Period Register Low
Timer 3 Period Register High
Timer 3 Control Register
Timer 3 Global Control Register
Timer 3 Watchdog Timer Control Register
Reserved
-
Reserved
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Table 7-71. Timer 3 Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
0294 0034 - 0294 FFFF
-
Reserved
Table 7-72. Timer 4 Registers
HEX ADDRESS
0295 0000
ACRONYM
REGISTER NAME
PID
Peripheral ID Register
0295 0004
EMUMGT_CLKSPD
Timer 4 Emulation Management/Clock Speed Register
Reserved
0295 0008
-
-
0295 000C
Reserved
0295 0010
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 4 Counter Register Low
Timer 4 Counter Register High
Timer 4 Period Register Low
Timer 4 Period Register High
Timer 4 Control Register
Timer 4 Global Control Register
Timer 4 Watchdog Timer Control Register
Reserved
0295 0014
0295 0018
0295 001C
0295 0020
0295 0024
0295 0028
0295 002C
0295 0030
-
Reserved
0295 0034 - 0295 FFFF
-
Reserved
Table 7-73. Timer 5 Registers
HEX ADDRESS
0296 0000
ACRONYM
REGISTER NAME
Peripheral ID Register
PID
0296 0004
EMUMGT_CLKSPD
Timer 5 Emulation Management/Clock Speed Register
Reserved
0296 0008
-
-
0296 000C
Reserved
0296 0010
TIMLO
TIMHI
PRDLO
PRDHI
TCR
TGCR
WDTCR
-
Timer 5 Counter Register Low
Timer 5 Counter Register High
Timer 5 Period Register Low
Timer 5 Period Register High
Timer 5 Control Register
Timer 5 Global Control Register
Timer 5 Watchdog Timer Control Register
Reserved
0296 0014
0296 0018
0296 001C
0296 0020
0296 0024
0296 0028
0296 002C
0296 0030
-
Reserved
0296 0034 - 0296 FFFF
-
Reserved
Table 7-74. Timer Device-Specific Registers
HEX ADDRESS
0290 0000
ACRONYM
TINPSEL
REGISTER NAME
Timer Input Selection
0290 0004
TOUTPSEL
WDRSTSEL
Timer Output Selection
Watchdog Timer Reset Select
0290 0008
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7.15.3 Timers Electrical Data/Timing
Table 7-75. Timing Requirements for Timer Inputs(1)
(see Figure 7-42)
NO.
PARAMETER
MIN
12C
12C
MAX UNIT
1
2
tw(TIMH)
tw(TIMIL)
Pulse duration, TIMI high
Pulse duration, TIMI low
ns
ns
(1) C = 1/CPU Clock, in ns.
Table 7-76. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs(1)
(see Figure 7-42)
NO.
3
PARAMETER
Pulse duration, TIMO high
Pulse duration, TIMO low
MIN
12C - 3
12C - 3
MAX UNIT
tw(TIMOH)
tw(TIMOL)
ns
ns
4
(1) If CORECLKSEL = 0, C = 1/SYSCLK(NIP) frequency, in ns. If CORECLKSEL = 1, C = 1/ALTCORECLK (N|P) frequency, in ns.
Figure 7-42. Timer Timing
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7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)
7.16.1 VCP2 Device-Specific Information
The C6474 device has a high-performance embedded coprocessor Viterbi-Decoder Coprocessor (VCP2)
that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock
divided-by-3 can decode over 694 7.95-Kbps adaptive multi-rate (AMR)(K = 9, R = 1/3) voice channels.
The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and
flexible polynomials, while generating hard decisions or soft decisions. Communications between the
VCP2 and the CPU are carried out through the EDMA3 controller.
The VCP2 supports:
•
•
•
•
•
•
•
•
•
•
Unlimited frame sizes
Code rates 3/4, 1/2, 1/3, 1/4, and 1/5
Constraint lengths 5, 6, 7, 8, and 9
Programmable encoder polynomials
Programmable reliability and convergence lengths
Hard and soft decoded decisions
Tail and convergent modes
Yamamoto logic
Tail biting logic
Various input and output FIFO lengths
For more detailed information on the VCP2, see the TMS320C6474 DSP Viterbi-Decoder Coprocessor 2
(VCP2) Reference Guide (literature number SPRUG20).
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7.16.2 VCP2 Peripheral Register Description(s)
Table 7-77. VCP2 Registers
EDMA BUS HEX ADDRESS RANGE
CONFIGURATION BUS HEX
ACRONYM
REGISTER NAME
ADDRESS RANGE
5800 0000
5800 0004
-
VCPIC0
VCPIC1
VCPIC2
VCPIC3
VCPIC4
VCPIC5
-
VCP2 input configuration Register 0
VCP2 input configuration Register 1
VCP2 input configuration Register 2
VCP2 input configuration Register 3
VCP2 input configuration Register 4
VCP2 Input Configuration Register 5
Reserved
-
5800 0008
-
5800 000C
-
5800 0010
-
5800 0014
-
5800 0018 - 5800 0044
5800 0048
-
-
VCPOUT0
VCPOUT1
-
VCP2 output Register 0
5800 004C
-
-
VCP2 output Register 1
5800 0050 - 5800 007C
5800 0080
Reserved
N/A
VCPWBM
VCP2 branch metrics write FIFO
Register
5800 0084 - 5800 009C
-
-
VCPRDECS
VCPEXE
VCPEND
VCPSTAT0
VCPSTAT1
VCPERR
-
Reserved
5800 00C0
N/A
N/A
VCP2 decisions read FIFO Register
VCP2 execution Register
VCP2 Endian mode Register
VCP2 Status Register 0
VCP2 Status Register 1
VCP2 error Register
Reserved
02B8 0018
N/A
02B8 0020
N/A
02B8 0040
N/A
02B8 0044
N/A
02B8 0050
-
-
N/A
02B8 0060
VCPEMU
-
VCP2 emulation control Register
Reserved
N/A
02B8 0064 - 02B9 FFFF
5800 1000
5800 2000
5800 3000
5800 6000
5800 F000
-
-
-
-
-
BM
Branch metrics
SM
State metric
TBHD
Traceback hard decision
Traceback soft decision
Decoded bits
TBSD
IO
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7.17 Enhanced Turbo Decoder Coprocessor (TCP2)
7.17.1 TCP2 Device-Specific Information
The C6474 device has a high-performance embedded coprocessor Turbo-Decoder Coprocessor (TCP2)
that significantly speeds up channel-decoding operations on-chip. The TCP2 operating at CPU clock
divided-by-3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 6
iterations). The TCP2 implements the max* log-map algorithm and is designed to support all polynomials
and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable
frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping
criteria are also programmable. Communications between the TCP2 and the CPU are carried out through
the EDMA3 controller.
The TCP2 supports:
•
•
•
•
•
•
•
•
•
•
•
Parallel concatenated convolutional turbo decoding using the MAP algorithm
All turbo code rates greater than or equal to 1/5
3GPP and CDMA2000 turbo encoder trellis
3GPP and CDMA2000 block sizes in standalone mode
Larger block sizes in shared processing mode
Both max log MAP and log MAP decoding
Sliding windows algorithm with variable reliability and prolog lengths
The prolog reduction algorithm
Execution of a minimum and maximum number of iterations
The SNR stopping criteria algorithm
The CRC stopping criteria algorithm
For more detailed information on the TCP2, see the TMS320C6474 DSP Turbo-Decoder Coprocessor 2
(TCP2) Reference Guide (literature number SPRUG21).
7.17.2 TCP2 Peripheral Register Description(s)
Table 7-78. TCP2 Registers
EDMA BUS HEX ADDRESS RANGE
CONFIGURATION BUS HEX
ADDRESS RANGE
ACRONYM
REGISTER NAME
5000 0000
5000 0004
5000 0008
5000 000C
5000 0010
5000 0014
5000 0018
5000 001C
5000 0020
5000 0024
5000 0028
5000 002C
5000 0030
5000 0034
5000 0038
5000 003C
5000 0040
5000 0044
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TCPIC0
TCPIC1
TCPIC2
TCPIC3
TCPIC4
TCPIC5
TCPIC6
TCPIC7
TCPIC8
TCPIC9
TCPIC10
TCPIC11
TCPIC12
TCPIC13
TCPIC14
TCPIC15
TCPOUT0
TCPOUT1
TCP2 Input Configuration Register 0
TCP2 Input Configuration Register 1
TCP2 Input Configuration Register 2
TCP2 Input Configuration Register 3
TCP2 Input Configuration Register 4
TCP2 Input Configuration Register 5
TCP2 Input Configuration Register 6
TCP2 Input Configuration Register 7
TCP2 Input Configuration Register 8
TCP2 Input Configuration Register 9
TCP2 Input Configuration Register 10
TCP2 Input Configuration Register 11
TCP2 Input Configuration Register 12
TCP2 Input Configuration Register 13
TCP2 Input Configuration Register 14
TCP2 Input Configuration Register 15
TCP2 Output Parameters Register 0
TCP2 Output Parameters Register 1
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Table 7-78. TCP2 Registers (continued)
EDMA BUS HEX ADDRESS RANGE
CONFIGURATION BUS HEX
ADDRESS RANGE
ACRONYM
REGISTER NAME
5000 0048
5001 0000
5003 0000
5004 0000
5005 0000
5006 0000
5007 0000
5008 0000
5009 0000
500A 0000
500B 0000
N/A
-
N/A
TCPOUT2
X0
TCP2 Output Parameters Register 2
TCP2 Data/Sys and Parity Memory
TCP2 Extrinsic Mem 0
N/A
W0
N/A
W1
TCP2 Extrinsic Mem 1
N/A
I0
TCP2 Interleaver Memory
TCP2 Output/Decision Memory
TCP2 Scratch Pad Memory
TCP2 Beta State Memory
TCP2 CRC Memory
N/A
O0
N/A
S0
N/A
T0
N/A
C0
N/A
B0
TCP2 Beta Prolog Memory
TCP2 Alpha Prolog Memory
N/A
A0
02BA 0000
TCPPID
TCP2 Peripheral Identification
Register [Value: 0x0002 1101]
N/A
N/A
N/A
N/A
N/A
N/A
02BA 004C
02BA 0050
TCPEXE
TCPEND
TCPERR
TCPSTAT
TCPEMU
-
TCP2 Execute Register
TCP2 Endian Register
TCP2 Error Register
TCP2 Status Register
TCP2 Emulation Register
Reserved
02BA 0060
02BA 0068
02BA 0070
02BA 005C - 02BB FFFF
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7.18 Serial RapidIO (SRIO) Port
The SRIO Port on the C6474 device is a high-performance, low pin-count interconnect aimed for
embedded markets. RapidIO is based on the memory and device addressing concepts of processor buses
where the transaction processing is managed completely by hardware. This enables the RapidIO
interconnect to lower the system cost by providing lower latency, reduced overhead of packet data
processing, and higher system bandwidth, all of which are key for wireless interfaces. The RapidIO
interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per
second (Gbps) bidirectional links.
The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
The RapidIO interface should be designed to operate at a data rate up to 3.125 Gbps per differential pair.
7.18.1 SRIO Device-Specific Information
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
McBSP. For these other interfaces the device timing was specified in terms of data manual specifications
and I/O buffer information specification (IBIS) models.
For the SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing two
DSPs connected via a 1x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the TMS320C6474 DSP SERDES Implementation Guidelines application report
(literature number SPRAAW9).
TI only supports designs that follow the board design guidelines outlined in the SPRAAW9
application report.
The Serial RapidIO peripheral is a master peripheral in the C6474 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.
7.18.2 SRIO Register Description(s)
Table 7-79. RapidIO Control Registers
HEX ADDRESS
02D0 0000
ACRONYM
RIOPID
REGISTER NAME
RapidIO Peripheral Identification Register
RapidIO Peripheral Control Register
Reserved
02D0 0004
RIO_PCR
02D0 0008 - 02D0 001C
02D0 0020
-
RIO_PER_SET_CNTL
-
RapidIO Peripheral Settings Control Register
Reserved
02D0 0024 - 02D0 002C
02D0 0030
RIO_GBL_EN
RapidIO Peripheral Global Enable Register
RapidIO Peripheral Global Enable Status Register
RapidIO Block0 Enable Register
RapidIO Block0 Enable Status Register
RapidIO Block1 Enable Register
RapidIO Block1 Enable Status Register
RapidIO Block2 Enable Register
RapidIO Block2 Enable Status Register
RapidIO Block3 Enable Register
RapidIO Block3 Enable Status Register
RapidIO Block4 Enable Register
RapidIO Block4 Enable Status Register
RapidIO Block5 Enable Register
02D0 0034
RIO_GBL_EN_STAT
RIO_BLK0_EN
RIO_BLK0_EN_STAT
RIO_BLK1_EN
RIO_BLK1_EN_STAT
RIO_BLK2_EN
RIO_BLK2_EN_STAT
RIO_BLK3_EN
RIO_BLK3_EN_STAT
RIO_BLK4_EN
RIO_BLK4_EN_STAT
RIO_BLK5_EN
02D0 0038
02D0 003C
02D0 0040
02D0 0044
02D0 0048
02D0 004C
02D0 0050
02D0 0054
02D0 0058
02D0 005C
02D0 0060
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0064
02D0 0068
02D0 006C
02D0 0070
02D0 0074
02D0 0078
02D0 007C
02D0 0080
02D0 0084
02D0 0088
02D0 008C
02D0 0090
02D0 0094
02D0 0098
02D0 009C
02D0 00A0
02D0 00A4
02D0 00A8
02D0 00AC
ACRONYM
RIO_BLK5_EN_STAT
RIO_BLK6_EN
REGISTER NAME
RapidIO Block5 Enable Status Register
RapidIO Block6 Enable Register
RIO_BLK6_EN_STAT
RIO_BLK7_EN
RapidIO Block6 Enable Status Register
RapidIO Block7 Enable Register
RIO_BLK7_EN_STAT
RIO_BLK8_EN
RapidIO Block7 Enable Status Register
RapidIO Block8 Enable Register
RIO_BLK8_EN_STAT
RIO_DEVICEID_REG1
RIO_DEVICEID_REG2
RIO_DEVICEID_REG3
RIO_DEVICEID_REG4
PF_16B_CNTL0
RapidIO Block8 Enable Status Register
RapidIO Device ID Register 1
RapidIO Device ID Register 2
RapidIO Device ID Register 3
RapidIO Device ID Register 4
Packet Forwarding Register 0 for 16-Bit Device IDs
Packet Forwarding Register 0 for 8-Bit Device IDs
Packet Forwarding Register 1 for 16-Bit Device IDs
Packet Forwarding Register 1 for 8-Bit Device IDs
Packet Forwarding Register 2 for 16-Bit Device IDs
Packet Forwarding Register 2 for 8-Bit Device IDs
Packet Forwarding Register 3 for 16-Bit Device IDs
Packet Forwarding Register 3 for 8-Bit Device IDs
Reserved
PF_8B_CNTL0
PF_16B_CNTL1
PF_8B_CNTL1
PF_16B_CNTL2
PF_8B_CNTL2
PF_16B_CNTL3
PF_8B_CNTL3
02D0 00B0 - 02D0 00FC
02D0 0100
02D0 0104
02D0 0108
02D0 010C
02D0 0110
02D0 0114
02D0 0118
02D0 011C
02D0 0120
02D0 0124
02D0 0128
02D0 012C
02D0 0130 - 02D0 01FC
02D0 0200
02D0 0204
02D0 0208
02D0 020C
02D0 0210
02D0 0214
02D0 0218
02D0 021C
02D0 0220
02D0 0224
02D0 0228
02D0 022C
02D0 0230
02D0 0234
-
RIO_SERDES_CFGRX0_CNTL
RIO_SERDES_CFGRX1_CNTL
RIO_SERDES_CFGRX2_CNTL
RIO_SERDES_CFGRX3_CNTL
RIO_SERDES_CFGTX0_CNTL
RIO_SERDES_CFGTX1_CNTL
RIO_SERDES_CFGTX2_CNTL
RIO_SERDES_CFGTX3_CNTL
RIO_SERDS_CFG0_CNTL
RIO_SERDS_CFG1_CNTL
RIO_SERDS_CFG2_CNTL
RIO_SERDS_CFG3_CNTL
-
RapidIO SerDes RX Channel 0 CFG Register
RapidIO SerDes RX Channel 1 CFG Register
RapidIO SerDes RX Channel 2 CFG Register
RapidIO SerDes RX Channel 3 CFG Register
RapidIO SerDes TX Channel 0 CFG Register
RapidIO SerDes TX Channel 1 CFG Register
RapidIO SerDes TX Channel 2 CFG Register
RapidIO SerDes TX Channel 3 CFG Register
RapidIO SerDes Macro 0 CFG Control Register
RapidIO SerDes Macro 1 CFG Control Register
RapidIO SerDes Macro 2 CFG Control Register
RapidIO SerDes Macro 3 CFG Control Register
Reserved
DOORBELL0_ICSR
-
DOORBELL Interrupt Condition Status Register 0
Reserved
DOORBELL0_ICCR
-
DOORBELL Interrupt Condition Clear Register 0
Reserved
DOORBELL1_ICSR
-
DOORBELL Interrupt Condition Status Register 1
Reserved
DOORBELL1_ICCR
-
DOORBELL Interrupt Condition Clear Register 1
Reserved
DOORBELL2_ICSR
-
DOORBELL Interrupt Condition Status Register 2
Reserved
DOORBELL2_ICCR
-
DOORBELL Interrupt Condition Clear Register 2
Reserved
DOORBELL3_ICSR
-
DOORBELL Interrupt Condition Status Register 3
Reserved
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0238
02D0 023C
02D0 0240
02D0 0244
02D0 0248
02D0 024C
02D0 0250
02D0 0254
02D0 0258
02D0 025C
02D0 0260
02D0 0264
02D0 0268
02D0 026C
02D0 0270
ACRONYM
REGISTER NAME
DOORBELL3_ICCR
DOORBELL Interrupt Condition Clear Register 3
Reserved
-
RX_CPPI_ICSR
RX CPPI Interrupt Condition Status Register
Reserved
-
RX_CPPI_ICCR
RX CPPI Interrupt Condition Clear Register
Reserved
-
TX_CPPI_ICSR
TX CPPI Interrupt Condition Status Register
Reserved
-
TX_CPPI_ICCR
TX CPPI Interrupt Condition Clear Register
Reserved
-
LSU_ICSR
LSU Interrupt Condition Status Register
Reserved
-
LSU_ICCR
LSU Interrupt Condition Clear Register
Reserved
-
ERR_RST_EVNT_ICSR
Error, Reset, and Special Event Interrupt Condition Status
Register
02D0 0274
02D0 0278
-
Reserved
ERR_RST_EVNT_ICCR
Error, Reset, and Special Event Interrupt Condition Clear
Register
02D0 027C
02D0 0280
-
DOORBELL0_ICRR
DOORBELL0_ICRR2
-
Reserved
DOORBELL0 Interrupt Condition Routing Register
DOORBELL 0 Interrupt Condition Routing Register 2
Reserved
02D0 0284
02D0 0288 - 02D0 028C
02D0 0290
DOORBELL1_ICRR
DOORBELL1_ICRR2
-
DOORBELL1 Interrupt Condition Routing Register
DOORBELL 1 Interrupt Condition Routing Register 2
Reserved
02D0 0294
02D0 0298 - 02D0 029C
02D0 02A0
DOORBELL2_ICRR
DOORBELL2_ICRR2
-
DOORBELL2 Interrupt Condition Routing Register
DOORBELL 2 Interrupt Condition Routing Register 2
Reserved
02D0 02A4
02D0 02A8 - 02D0 02AC
02D0 02B4
DOORBELL3_ICRR2
-
DOORBELL 3 Interrupt Condition Routing Register 2
Reserved
02D0 02B8 - 02D0 02BC
02D0 02C0
RX_CPPI _ICRR
RX_CPPI _ICRR2
-
Receive CPPI Interrupt Condition Routing Register
Receive CPPI Interrupt Condition Routing Register 2
Reserved
02D0 02C4
02D0 02C8 - 02D0 02CC
02D0 02D0
TX_CPPI _ICRR
TX_CPPI _ICRR2
-
Transmit CPPI Interrupt Condition Routing Register
Transmit CPPI Interrupt Condition Routing Register 2
Reserved
02D0 02D4
02D0 02D8 - 02D0 02DC
02D0 02E0
LSU_ICRR0
LSU_ICRR1
LSU_ICRR2
LSU_ICRR3
ERR_RST_EVNT_ICRR
LSU Interrupt Condition Routing Register 0
LSU Interrupt Condition Routing Register 1
LSU Interrupt Condition Routing Register 2
LSU Interrupt Condition Routing Register 3
02D0 02E4
02D0 02E8
02D0 02EC
02D0 02F0
Error, Reset, and Special Event Interrupt Condition
Routing Register
02D0 02F4
02D0 02F8
ERR_RST_EVNT_ICRR2
ERR_RST_EVNT_ICRR3
Error, Reset, and Special Event Interrupt Condition
Routing Register 2
Error, Reset, and Special Event Interrupt Condition
Routing Register 3
02D0 02FC
02D0 0300
-
Reserved
INTDST0_DECODE
INTDST Interrupt Status Decode Register 0
174
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0304
02D0 0308
02D0 030C
02D0 0310
02D0 0314
02D0 0318
02D0 031C
02D0 0320
02D0 0324
02D0 0328
02D0 032C
02D0 0330
02D0 0334
02D0 0338
02D0 033C
ACRONYM
REGISTER NAME
INTDST1_DECODE
INTDST2_DECODE
RIO_INTDST3_Decode
RIO_INTDST4_Decode
RIO_INTDST5_Decode
RIO_INTDST6_Decode
RIO_INTDST7_Decode
RIO_INTDST0_Rate_CNTL
RIO_INTDST1_Rate_CNTL
RIO_INTDST2_Rate_CNTL
RIO_INTDST3_Rate_CNTL
RIO_INTDST4_Rate_CNTL
RIO_INTDST5_Rate_CNTL
RIO_INTDST6_Rate_CNTL
RIO_INTDST7_Rate_CNTL
-
INTDST Interrupt Status Decode Register 1
INTDST Interrupt Status Decode Register 2
RapidIO INTDST3 Interrupt Status Decode Register
RapidIO INTDST4 Interrupt Status Decode Register
RapidIO INTDST5 Interrupt Status Decode Register
RapidIO INTDST6 Interrupt Status Decode Register
RapidIO INTDST7 Interrupt Status Decode Register
RapidIO INTDST0 Interrupt Rate Control Register
RapidIO INTDST1 Interrupt Rate Control Register
RapidIO INTDST2 Interrupt Rate Control Register
RapidIO INTDST3 Interrupt Rate Control Register
RapidIO INTDST4 Interrupt Rate Control Register
RapidIO INTDST5 Interrupt Rate Control Register
RapidIO INTDST6 Interrupt Rate Control Register
RapidIO INTDST7 Interrupt Rate Control Register
Reserved
02D0 0340 - 02D0 03FC
02D0 0400
RIO_LSU1_Reg0
RapidIO LSU1 Control Reg0 Register
02D0 0404
RIO_LSU1_Reg1
RapidIO LSU1 Control Reg1 Register
02D0 0408
RIO_LSU1_Reg2
RapidIO LSU1 Control Reg2 Register
02D0 040C
RIO_LSU1_Reg3
RapidIO LSU1 Control Reg3 Register
02D0 0410
RIO_LSU1_Reg4
RapidIO LSU1 Control Reg4 Register
02D0 0414
RIO_LSU1_Reg5
RapidIO LSU1 Control Reg5 Register
02D0 0418
RIO_LSU1_Reg6
RapidIO LSU1 Control Reg6 Register
02D0 041C
RIO_LSU1_FLOW_MASKS
RapidIO Core0 LSU Congestion Control Flow Mask
Register
02D0 0420
02D0 0424
02D0 0428
02D0 042C
02D0 0430
02D0 0434
02D0 0438
02D0 043C
RIO_LSU2_Reg0
RIO_LSU2_Reg1
RapidIO LSU2 Control Reg0 Register
RapidIO LSU2 Control Reg1 Register
RapidIO LSU2 Control Reg2 Register
RapidIO LSU2 Control Reg3 Register
RapidIO LSU2 Control Reg4 Register
RapidIO LSU2 Control Reg5 Register
RapidIO LSU2 Control Reg6 Register
RIO_LSU2_Reg2
RIO_LSU2_Reg3
RIO_LSU2_Reg4
RIO_LSU2_Reg5
RIO_LSU2_Reg6
RIO_LSU2_FLOW_MASKS
RapidIO Core1 LSU Congestion Control Flow Mask
Register
02D0 0440
02D0 0444
02D0 0448
02D0 044C
02D0 0450
02D0 0454
02D0 0458
02D0 045C
RIO_LSU3_Reg0
RIO_LSU3_Reg1
RapidIO LSU3 Control Reg0 Register
RapidIO LSU3 Control Reg1 Register
RapidIO LSU3 Control Reg2 Register
RapidIO LSU3 Control Reg3 Register
RapidIO LSU3 Control Reg4 Register
RapidIO LSU3 Control Reg5 Register
RapidIO LSU3 Control Reg6 Register
RIO_LSU3_Reg2
RIO_LSU3_Reg3
RIO_LSU3_Reg4
RIO_LSU3_Reg5
RIO_LSU3_Reg6
RIO_LSU3_FLOW_MASKS
RapidIO Core2 LSU Congestion Control Flow Mask
Register
02D0 0460
02D0 0464
02D0 0468
02D0 046C
02D0 0470
RIO_LSU4_Reg0
RIO_LSU4_Reg1
RIO_LSU4_Reg2
RIO_LSU4_Reg3
RIO_LSU4_Reg4
RapidIO LSU4 Control Reg0 Register
RapidIO LSU4 Control Reg1 Register
RapidIO LSU4 Control Reg2 Register
RapidIO LSU4 Control Reg3 Register
RapidIO LSU4 Control Reg4 Register
Copyright © 2008–2011, Texas Instruments Incorporated
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0474
ACRONYM
RIO_LSU4_Reg5
REGISTER NAME
RapidIO LSU4 Control Reg5 Register
RapidIO LSU4 Control Reg6 Register
02D0 0478
RIO_LSU4_Reg6
02D0 047C
RIO_LSU4_FLOW_MASKS
RapidIO Core3 LSU Congestion Control Flow Mask
Register
02D0 0480 - 02D0 04FC
02D0 0500
-
Reserved
RIO_Queue0_TxDMA_HDP
RapidIO Queue0 TX DMA Head Descriptor Pointer
Register
02D0 0504
02D0 0508
02D0 050C
02D0 0510
02D0 0514
02D0 0518
02D0 051C
02D0 0520
02D0 0524
02D0 0528
02D0 052C
02D0 0530
02D0 0534
02D0 0538
02D0 053C
02D0 0540
02D0 0544
02D0 0548
02D0 054C
RIO_Queue1_TxDMA_HDP
RIO_Queue2_TxDMA_HDP
RIO_Queue3_TxDMA_HDP
RIO_Queue4_TxDMA_HDP
RIO_Queue5_TxDMA_HDP
RIO_Queue6_TxDMA_HDP
RIO_Queue7_TxDMA_HDP
RIO_Queue8_TxDMA_HDP
RIO_Queue9_TxDMA_HDP
RIO_Queue10_TxDMA_HDP
RIO_Queue11_TxDMA_HDP
RIO_Queue12_TxDMA_HDP
RIO_Queue13_TxDMA_HDP
RIO_Queue14_TxDMA_HDP
RIO_Queue15_TxDMA_HDP
RIO_Queue16_TxDMA_HDP
RIO_Queue17_TxDMA_HDP
RIO_Queue18_TxDMA_HDP
RIO_Queue19_TxDMA_HDP
RapidIO Queue1 TX DMA Head Descriptor Pointer
Register
RapidIO Queue2 TX DMA Head Descriptor Pointer
Register
RapidIO Queue3 TX DMA Head Descriptor Pointer
Register
RapidIO Queue4 TX DMA Head Descriptor Pointer
Register
RapidIO Queue5 TX DMA Head Descriptor Pointer
Register
RapidIO Queue6 TX DMA Head Descriptor Pointer
Register
RapidIO Queue7 TX DMA Head Descriptor Pointer
Register
RapidIO Queue8 TX DMA Head Descriptor Pointer
Register
RapidIO Queue9 TX DMA Head Descriptor Pointer
Register
RapidIO Queue10 TX DMA Head Descriptor Pointer
Register
RapidIO Queue11TX DMA Head Descriptor Pointer
Register
RapidIO Queue12 TX DMA Head Descriptor Pointer
Register
RapidIO Queue13 TX DMA Head Descriptor Pointer
Register
RapidIO Queue14 TX DMA Head Descriptor Pointer
Register
RapidIO Queue15 TX DMA Head Descriptor Pointer
Register
RapidIO Queue16 TX DMA Head Descriptor Pointer
Register
RapidIO Queue17 TX DMA Head Descriptor Pointer
Register
RapidIO Queue18 TX DMA Head Descriptor Pointer
Register
RapidIO Queue19 TX DMA Head Descriptor Pointer
Register
02D0 0550 - 02D0 057C
02D0 0580
-
Reserved
RIO_Queue0_TxDMA_CP
RIO_Queue1_TxDMA_CP
RIO_Queue2_TxDMA_CP
RIO_Queue3_TxDMA_CP
RIO_Queue4_TxDMA_CP
RIO_Queue5_TxDMA_CP
RIO_Queue6_TxDMA_CP
RIO_Queue7_TxDMA_CP
RapidIO Queue0 TX DMA Completion Pointer Register
RapidIO Queue1 TX DMA Completion Pointer Register
RapidIO Queue2 TX DMA Completion Pointer Register
RapidIO Queue3 TX DMA Completion Pointer Register
RapidIO Queue4 TX DMA Completion Pointer Register
RapidIO Queue5 TX DMA Completion Pointer Register
RapidIO Queue6 TX DMA Completion Pointer Register
RapidIO Queue7 TX DMA Completion Pointer Register
02D0 0584
02D0 0588
02D0 058C
02D0 0590
02D0 0594
02D0 0598
02D0 059C
176
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SPRS552H–OCTOBER 2008–REVISED APRIL 2011
Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 05A0
02D0 05A4
02D0 05A8
02D0 05AC
02D0 05B0
02D0 05B4
02D0 05B8
02D0 05BC
ACRONYM
REGISTER NAME
RIO_Queue8_TxDMA_CP
RIO_Queue9_TxDMA_CP
RIO_Queue10_TxDMA_CP
RIO_Queue11_TxDMA_CP
RIO_Queue12_TxDMA_CP
RIO_Queue13_TxDMA_CP
RIO_Queue14_TxDMA_CP
RIO_Queue15_TxDMA_CP
-
RapidIO Queue8 TX DMA Completion Pointer Register
RapidIO Queue9 TX DMA Completion Pointer Register
RapidIO Queue10 TX DMA Completion Pointer Register
RapidIO Queue11 TX DMA Completion Pointer Register
RapidIO Queue12 TX DMA Completion Pointer Register
RapidIO Queue13 TX DMA Completion Pointer Register
RapidIO Queue14 TX DMA Completion Pointer Register
RapidIO Queue15 TX DMA Completion Pointer Register
Reserved
02D0 05C0 - 02D0 05FC
02D0 0600
RIO_Queue0_RxDMA_HDP
RapidIO Queue0 RX DMA Head Descriptor Pointer
Register
02D0 0604
02D0 0608
02D0 060C
02D0 0610
02D0 0614
02D0 0618
02D0 061C
02D0 0620
02D0 0624
02D0 0628
02D0 062C
02D0 0630
02D0 0634
02D0 0638
02D0 063C
RIO_Queue1_RxDMA_HDP
RIO_Queue2_RxDMA_HDP
RIO_Queue3_RxDMA_HDP
RIO_Queue4_RxDMA_HDP
RIO_Queue5_RxDMA_HDP
RIO_Queue6_RxDMA_HDP
RIO_Queue7_RxDMA_HDP
RIO_Queue8_RxDMA_HDP
RIO_Queue9_RxDMA_HDP
RIO_Queue10_RxDMA_HDP
RIO_Queue11_RxDMA_HDP
RIO_Queue12_RxDMA_HDP
RIO_Queue13_RxDMA_HDP
RIO_Queue14_RxDMA_HDP
RIO_Queue15_RxDMA_HDP
RapidIO Queue1 RX DMA Head Descriptor Pointer
Register
RapidIO Queue2 RX DMA Head Descriptor Pointer
Register
RapidIO Queue3 RX DMA Head Descriptor Pointer
Register
RapidIO Queue4 RX DMA Head Descriptor Pointer
Register
RapidIO Queue5 RX DMA Head Descriptor Pointer
Register
RapidIO Queue6 RX DMA Head Descriptor Pointer
Register
RapidIO Queue7 RX DMA Head Descriptor Pointer
Register
RapidIO Queue8 RX DMA Head Descriptor Pointer
Register
RapidIO Queue9 RX DMA Head Descriptor Pointer
Register
RapidIO Queue10 RX DMA Head Descriptor Pointer
Register
RapidIO Queue11 RX DMA Head Descriptor Pointer
Register
RapidIO Queue12 RX DMA Head Descriptor Pointer
Register
RapidIO Queue13 RX DMA Head Descriptor Pointer
Register
RapidIO Queue14 RX DMA Head Descriptor Pointer
Register
RapidIO Queue15 RX DMA Head Descriptor Pointer
Register
02D0 0640 - 02D0 067C
02D0 0680
-
Reserved
RIO_Queue0_RxDMA_CP
RIO_Queue1_RxDMA_CP
RIO_Queue2_RxDMA_CP
RIO_Queue3_RxDMA_CP
RIO_Queue4_RxDMA_CP
RIO_Queue5_RxDMA_CP
RIO_Queue6_RxDMA_CP
RIO_Queue7_RxDMA_CP
RIO_Queue8_RxDMA_CP
RIO_Queue9_RxDMA_CP
RapidIO Queue0 RX DMA Completion Pointer Register
RapidIO Queue1 RX DMA Completion Pointer Register
RapidIO Queue2 RX DMA Completion Pointer Register
RapidIO Queue3 RX DMA Completion Pointer Register
RapidIO Queue4 RX DMA Completion Pointer Register
RapidIO Queue5 RX DMA Completion Pointer Register
RapidIO Queue6 RX DMA Completion Pointer Register
RapidIO Queue7 RX DMA Completion Pointer Register
RapidIO Queue8 RX DMA Completion Pointer Register
RapidIO Queue9 RX DMA Completion Pointer Register
02D0 0684
02D0 0688
02D0 068C
02D0 0690
02D0 0694
02D0 0698
02D0 069C
02D0 06A0
02D0 06A4
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0648
ACRONYM
RIO_Queue10_RxDMA_CP
RIO_Queue11_RxDMA_CP
RIO_Queue12_RxDMA_CP
RIO_Queue13_RxDMA_CP
RIO_Queue14_RxDMA_CP
RIO_Queue15_RxDMA_CP
-
REGISTER NAME
RapidIO Queue10 RX DMA Completion Pointer Register
RapidIO Queue11 RX DMA Completion Pointer Register
RapidIO Queue12 RX DMA Completion Pointer Register
RapidIO Queue13 RX DMA Completion Pointer Register
RapidIO Queue14 RX DMA Completion Pointer Register
RapidIO Queue15 RX DMA Completion Pointer Register
Reserved
02D0 06AC
02D0 06B0
02D0 06B4
02D0 06B8
02D0 06BC
02D0 06C0 - 02D0 06FC
02D0 0700
RIO_TXQUEUE_TEAR_DOWN
RIO_TX_CPPI_FLOW_MASKS0
RIO_TX_CPPI_FLOW_MASKS1
RIO_TX_CPPI_FLOW_MASKS2
RIO_TX_CPPI_FLOW_MASKS3
RIO_TX_CPPI_FLOW_MASKS4
-
RapidIO TX Queue Tear Down Register
RapidIO TX CPPI Support Flow Masks 0 Register
RapidIO TX CPPI Support Flow Masks 1 Register
RapidIO TX CPPI Support Flow Masks 2 Register
RapidIO TX CPPI Support Flow Masks 3 Register
RapidIO TX CPPI Support Flow Masks 4 Register
Reserved
02D0 0704
02D0 0708
02D0 070C
02D0 0710
02D0 0714
02D0 0718 - 02D0 073C
02D0 0740
RIO_RX_QUEUE_TEAR_DOWN
RIO_RX_CPPI_CNTL
-
RapidIO RX Queue Tear Down Register
RapidIO CPPI Control Register
02D0 0744
02D0 0748 - 02D0 07DC
02D0 07E0
Reserved
RIO_TX_QUEUE_CNTL0
RIO_TX_QUEUE_CNTL1
RIO_TX_QUEUE_CNTL2
RIO_TX_QUEUE_CNTL3
-
RapidIO TX Queue Control 0 Register
RapidIO TX Queue Control 1 Register
RapidIO TX Queue Control 2 Register
RapidIO TX Queue Control 3 Register
Reserved
02D0 07E4
02D0 07E8
02D0 07EC
02D0 07F0 - 02D0 07FC
02D0 0800
RXU_MAP_L0
Mailbox-to-Queue Mapping Register L0
Mailbox-to-Queue Mapping Register H0
Mailbox-to-Queue Mapping Register L1
Mailbox-to-Queue Mapping Register H1
Mailbox-to-Queue Mapping Register L2
Mailbox-to-Queue Mapping Register H2
Mailbox-to-Queue Mapping Register L3
Mailbox-to-Queue Mapping Register H3
Mailbox-to-Queue Mapping Register L4
Mailbox-to-Queue Mapping Register H4
Mailbox-to-Queue Mapping Register L5
Mailbox-to-Queue Mapping Register H5
Mailbox-to-Queue Mapping Register L6
Mailbox-to-Queue Mapping Register H6
Mailbox-to-Queue Mapping Register L7
Mailbox-to-Queue Mapping Register H7
Mailbox-to-Queue Mapping Register L8
Mailbox-to-Queue Mapping Register H8
Mailbox-to-Queue Mapping Register L9
Mailbox-to-Queue Mapping Register H9
Mailbox-to-Queue Mapping Register L10
Mailbox-to-Queue Mapping Register H10
Mailbox-to-Queue Mapping Register L11
Mailbox-to-Queue Mapping Register H11
Mailbox-to-Queue Mapping Register L12
02D0 0804
RXU_MAP_H0
02D0 0808
RXU_MAP_L1
02D0 080C
02D0 0810
RXU_MAP_H1
RXU_MAP_L2
02D0 0814
RXU_MAP_H2
02D0 0818
RXU_MAP_L3
02D0 081C
02D0 0820
RXU_MAP_H3
RXU_MAP_L4
02D0 0824
RXU_MAP_H4
02D0 0828
RXU_MAP_L5
02D0 082C
02D0 0830
RXU_MAP_H5
RXU_MAP_L6
02D0 0834
RXU_MAP_H6
02D0 0838
RXU_MAP_L7
02D0 083C
02D0 0840
RXU_MAP_H7
RXU_MAP_L8
02D0 0844
RXU_MAP_H8
02D0 0848
RXU_MAP_L9
02D0 084C
02D0 0850
RXU_MAP_H9
RXU_MAP_L10
02D0 0854
RXU_MAP_H10
02D0 0858
RXU_MAP_L11
02D0 085C
02D0 08560
RXU_MAP_H11
RXU_MAP_L12
178
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SPRS552H–OCTOBER 2008–REVISED APRIL 2011
Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0864
02D0 0868
02D0 086C
02D0 0870
02D0 0874
02D0 0878
02D0 087C
02D0 0880
02D0 0884
02D0 0888
02D0 088C
02D0 0890
02D0 0894
02D0 0898
02D0 089C
02D0 08A0
02D0 08A4
02D0 08A8
02D0 08AC
02D0 08B0
02D0 08B4
02D0 08B8
02D0 08BC
02D0 08C0
02D0 08C4
02D0 08C8
02D0 08CC
02D0 08D0
02D0 08D4
02D0 08D8
02D0 08DC
02D0 08E0
02D0 08E4
02D0 08E8
02D0 08EC
02D0 08F0
02D0 08F4
02D0 08F8
02D0 08FC
02D0 0900
02D0 0904
02D0 0908
02D0 090C
02D0 0910
02D0 0914
02D0 0918
02D0 091C
ACRONYM
REGISTER NAME
Mailbox-to-Queue Mapping Register H12
Mailbox-to-Queue Mapping Register L13
Mailbox-to-Queue Mapping Register H13
Mailbox-to-Queue Mapping Register L14
Mailbox-to-Queue Mapping Register H14
Mailbox-to-Queue Mapping Register L15
Mailbox-to-Queue Mapping Register H15
Mailbox-to-Queue Mapping Register L16
Mailbox-to-Queue Mapping Register H16
Mailbox-to-Queue Mapping Register L17
Mailbox-to-Queue Mapping Register H17
Mailbox-to-Queue Mapping Register L18
Mailbox-to-Queue Mapping Register H18
Mailbox-to-Queue Mapping Register L19
Mailbox-to-Queue Mapping Register H19
Mailbox-to-Queue Mapping Register L20
Mailbox-to-Queue Mapping Register H20
Mailbox-to-Queue Mapping Register L21
Mailbox-to-Queue Mapping Register H21
Mailbox-to-Queue Mapping Register L22
Mailbox-to-Queue Mapping Register H22
Mailbox-to-Queue Mapping Register L23
Mailbox-to-Queue Mapping Register H23
Mailbox-to-Queue Mapping Register L24
Mailbox-to-Queue Mapping Register H24
Mailbox-to-Queue Mapping Register L25
Mailbox-to-Queue Mapping Register H25
Mailbox-to-Queue Mapping Register L26
Mailbox-to-Queue Mapping Register H26
Mailbox-to-Queue Mapping Register L27
Mailbox-to-Queue Mapping Register H27
Mailbox-to-Queue Mapping Register L28
Mailbox-to-Queue Mapping Register H28
Mailbox-to-Queue Mapping Register L29
Mailbox-to-Queue Mapping Register H29
Mailbox-to-Queue Mapping Register L30
Mailbox-to-Queue Mapping Register H30
Mailbox-to-Queue Mapping Register L31
Mailbox-to-Queue Mapping Register H31
Flow Control Table Entry Register 0
RXU_MAP_H12
RXU_MAP_L13
RXU_MAP_H13
RXU_MAP_L14
RXU_MAP_H14
RXU_MAP_L15
RXU_MAP_H15
RXU_MAP_L16
RXU_MAP_H16
RXU_MAP_L17
RXU_MAP_H17
RXU_MAP_L18
RXU_MAP_H18
RXU_MAP_L19
RXU_MAP_H19
RXU_MAP_L20
RXU_MAP_H20
RXU_MAP_L21
RXU_MAP_H21
RXU_MAP_L22
RXU_MAP_H22
RXU_MAP_L23
RXU_MAP_H23
RXU_MAP_L24
RXU_MAP_H24
RXU_MAP_L25
RXU_MAP_H25
RXU_MAP_L26
RXU_MAP_H26
RXU_MAP_L27
RXU_MAP_H27
RXU_MAP_L28
RXU_MAP_H28
RXU_MAP_L29
RXU_MAP_H29
RXU_MAP_L30
RXU_MAP_H30
RXU_MAP_L31
RXU_MAP_H31
FLOW_CNTL0
FLOW_CNTL1
FLOW_CNTL2
FLOW_CNTL3
FLOW_CNTL4
FLOW_CNTL5
FLOW_CNTL6
FLOW_CNTL7
Flow Control Table Entry Register 1
Flow Control Table Entry Register 2
Flow Control Table Entry Register 3
Flow Control Table Entry Register 4
Flow Control Table Entry Register 5
Flow Control Table Entry Register 6
Flow Control Table Entry Register 7
Copyright © 2008–2011, Texas Instruments Incorporated
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 0920
ACRONYM
FLOW_CNTL8
FLOW_CNTL9
FLOW_CNTL10
FLOW_CNTL11
FLOW_CNTL12
FLOW_CNTL13
FLOW_CNTL14
FLOW_CNTL15
-
REGISTER NAME
Flow Control Table Entry Register 8
Flow Control Table Entry Register 9
Flow Control Table Entry Register 10
Flow Control Table Entry Register 11
Flow Control Table Entry Register 12
Flow Control Table Entry Register 13
Flow Control Table Entry Register 14
Flow Control Table Entry Register 15
Reserved
02D0 0924
02D0 0928
02D0 092C
02D0 0930
02D0 0934
02D0 0938
02D0 093C
02D0 0940 - 02D0 0FFC
02D0 1000
DEV_ID
Device Identity CAR
02D0 1004
DEV_INFO
ASBLY_ID
ASBLY_INFO
PE_FEAT
Device Information CAR
02D0 1008
Assembly Identity CAR
02D0 100C
Assembly Information CAR
Processing Element Features CAR
Reserved
02D0 1010
02D0 1014
-
02D0 1018
SRC_OP
Source Operations CAR
02D0 101C
DEST_OP
Destination Operations CAR
Reserved
02D0 1020 - 02D0 1048
02D0 104C
-
PE_LL_CTL
-
Processing Element Logical Layer Control CSR
Reserved
02D0 1050
02D0 1058
LCL_CFG_HBAR
LCL_CFG_BAR
BASE_ID
Local Configuration Space Base Address 0 CSR
Local Configuration Space Base Address 1
Base Device ID CSR
02D0 105C
02D0 1060
02D0 1064
-
Reserved
02D0 1068
HOST_BASE_ID_LOCK
COMP_TAG
-
Host Base Device ID Lock CSR
Component Tag CSR
02D0 106C
02D0 1070 - 02D0 10FC
02D0 1100
Reserved
SP_MB_HEAD
-
1x/4x LP_Serial Port Maintenance Block Header
Reserved
02D0 1104 - 02D0 111C
02D0 1120
SP_LT_CTL
SP_RT_CTL
-
Port Link Time-Out Control CSR
Port Response Time-Out Control CSR
Reserved
02D0 1124
02D0 1128 - 02D0 1138
02D0 113C
SP_GEN_CTL
SP0_LM_REQ
SP0_LM_RESP
SP0_ACKID_STAT
-
Port General Control CSR
Port 0 Link Maintenance Request CSR
Port 0 Link Maintenance Response CSR
Port 0 Local AckID Status CSR
Reserved
02D0 1140
02D0 1144
02D0 1148
02D0 114C - 02D0 1154
02D0 1158
SP0_ERR_STAT
SP0_CTL
Port 0 Error and Status CSR
Port 0 Control CSR
02D0 115C
02D0 1160
SP1_LM_REQ
SP1_LM_RESP
SP1_ACKID_STAT
-
Port 1 Link Maintenance Request CSR
Port 1 Link Maintenance Response CSR
Port 1 Local AckID Status CSR
Reserved
02D0 1164
02D0 1168
02D0 116C - 02D0 1174
02D0 1178
SP1_ERR_STAT
SP1_CTL
Port 1 Error and Status CSR
Port 1 Control CSR
02D0 117C
02D0 1180
SP2_LM_REQ
SP2_LM_RESP
Port 2 Link Maintenance Request CSR
Port 2 Link Maintenance Response CSR
02D0 1184
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
ACRONYM
SP2_ACKID_STAT
-
REGISTER NAME
Port 2 Local AckID Status CSR
02D0 1188
02D0 118C - 02D0 1194
02D0 1198
Reserved
SP2_ERR_STAT
SP2_CTL
Port 2 Error and Status CSR
Port 2 Control CSR
02D0 119C
02D0 11A0
SP3_LM_REQ
SP3_LM_RESP
SP3_ACKID_STAT
-
Port 3 Link Maintenance Request CSR
Port 3 Link Maintenance Response CSR
Port 3 Local AckID Status CSR
Reserved
02D0 11A4
02D0 11A8
02D0 11AC - 02D0 11B4
02D0 11B8
SP3_ERR_STAT
SP3_CTL
Port 3 Error and Status CSR
Port 3 Control CSR
02D0 11BC
02D0 11C0 - 02D0 1FFC
02D0 2000
-
Reserved
ERR_RPT_BH
-
Error Reporting Block Header
Reserved
02D0 2004
02D0 2008
ERR_DET
Logical/Transport Layer Error Detect CSR
Logical/Transport Layer Error Enable CSR
Logical/Transport Layer High Address Capture CSR
Logical/Transport Layer Address Capture CSR
Logical/Transport Layer Device ID Capture CSR
Logical/Transport Layer Control Capture CSR
Reserved
02D0 200C
ERR_EN
02D0 2010
H_ADDR_CAPT
ADDR_CAPT
02D0 2014
02D0 2018
ID_CAPT
02D0 201C
CTRL_CAPT
02D0 2020 - 02D0 2024
02D0 2028
-
PW_TGT_ID
Port-Write Target Device ID CSR
Reserved
02D0 202C - 02D0 203C
02D0 2040
-
SP0_ERR_DET
SP0_RATE_EN
SP0_ERR_ATTR_CAPT_DBG0
SP0_ERR_CAPT_DBG1
SP0_ERR_CAPT_DBG2
SP0_ERR_CAPT_DBG3
SP0_ERR_CAPT_DBG4
-
Port 0 Error Detect CSR
02D0 2044
Port 0 Error Enable CSR
02D0 2048
Port 0 Attributes Error Capture CSR 0
Port 0 Packet/Control Symbol Error Capture CSR 1
Port 0 Packet/Control Symbol Error Capture CSR 2
Port 0 Packet/Control Symbol Error Capture CSR 3
Port 0 Packet/Control Symbol Error Capture CSR 4
Reserved
02D0 204C
02D0 2050
02D0 2054
02D0 2058
02D0 205C - 02D0 2064
02D0 2068
SP0_ERR_RATE
SP0_ERR_THRESH
-
Port 0 Error Rate CSR 0
02D0 206C
Port 0 Error Rate Threshold CSR
Reserved
02D0 2070 - 02D0 207C
02D0 2080
SP1_ERR_DET
SP1_RATE_EN
SP1_ERR_ATTR_CAPT_DBG0
SP1_ERR_CAPT_DBG1
SP1_ERR_CAPT_DBG2
SP1_ERR_CAPT_DBG3
SP1_ERR_CAPT_DBG4
-
Port 1 Error Detect CSR
02D0 2084
Port 1 Error Enable CSR
02D0 2088
Port 1 Attributes Error Capture CSR 0
Port 1 Packet/Control Symbol Error Capture CSR 1
Port 1 Packet/Control Symbol Error Capture CSR 2
Port 1 Packet/Control Symbol Error Capture CSR 3
Port 1 Packet/Control Symbol Error Capture CSR 4
Reserved
02D0 208C
02D0 2090
02D0 2094
02D0 2098
02D0 209C - 02D0 20A4
02D0 20A8
SP1_ERR_RATE
SP1_ERR_THRESH
-
Port 1 Error Rate CSR
02D0 20AC
Port 1 Error Rate Threshold CSR
Reserved
02D0 20B0 - 02D0 20BC
02D0 20C0
SP2_ERR_DET
SP2_RATE_EN
SP2_ERR_ATTR_CAPT_DBG0
Port 2 Error Detect CSR
02D0 20C4
Port 2 Error Enable CSR
02D0 20C8
Port 2 Attributes Error Capture CSR 0
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
02D0 20CC
ACRONYM
SP2_ERR_CAPT_DBG1
SP2_ERR_CAPT_DBG2
SP2_ERR_CAPT_DBG3
SP2_ERR_CAPT_DBG4
-
REGISTER NAME
Port 2 Packet/Control Symbol Error Capture CSR 1
Port 2 Packet/Control Symbol Error Capture CSR 2
Port 2 Packet/Control Symbol Error Capture CSR 3
Port 2 Packet/Control Symbol Error Capture CSR 4
Reserved
02D0 20D0
02D0 20D4
02D0 20D8
02D0 20E0 - 02D0 20E4
02D0 20E8
SP2_ERR_RATE
SP2_ERR_THRESH
-
Port 2 Error Rate CSR
02D0 20EC
Port 2 Error Rate Threshold CSR
Reserved
02D0 20F0 - 02D0 20FC
02D0 2100
SP3_ERR_DET
SP3_RATE_EN
SP3_ERR_ATTR_CAPT_DBG0
SP3_ERR_CAPT_DBG1
SP3_ERR_CAPT_DBG2
SP3_ERR_CAPT_DBG3
SP3_ERR_CAPT_DBG4
-
Port 3 Error Detect CSR
02D0 2104
Port 3 Error Enable CSR
02D0 2108
Port 3 Attributes Error Capture CSR 0
Port 3 Packet/Control Symbol Error Capture CSR 1
Port 3 Packet/Control Symbol Error Capture CSR 2
Port 3 Packet/Control Symbol Error Capture CSR 3
Port 3 Packet/Control Symbol Error Capture CSR 4
Reserved
02D0 210C
02D0 2110
02D0 2114
02D0 2118
02D0 211C - 02D0 2124
02D0 2128
SP3_ERR_RATE
SP3_ERR_THRESH
-
Port 3 Error Rate CSR
02D0 212C
Port 3 Error Rate Threshold CSR
Reserved
02D0 2130 - 02D1 1FFC
02D1 2000
SP_IP_DISCOVERY_TIMER
SP_IP_MODE
Port IP Discovery Timer in 4x Mode
Port IP Mode CSR
02D1 2004
02D1 2008
IP_PRESCAL
Port IP Prescaler Register
02D1 200C
-
Reserved
02D1 2010
SP_IP_PW_IN_CAPT0
SP_IP_PW_IN_CAPT1
SP_IP_PW_IN_CAPT2
SP_IP_PW_IN_CAPT3
-
Port-Write-In Capture CSR Register 0
Port-Write-In Capture CSR Register 1
Port-Write-In Capture CSR Register 2
Port-Write-In Capture CSR Register 3
Reserved
02D1 2014
02D1 2018
02D1 201C
02D1 2020 - 02D1 3FFC
02D1 4000
SP0_RST_OPT
SP0_CTL_INDEP
SP0_SILENCE_TIMER
SP0_MULT_EVNT_CS
-
Port 0 Reset Option CSR
02D1 4004
Port 0 Control Independent Register
Port 0 Silence Timer Register
Port 0 Multicast-Event Control Symbol Request Register
Reserved
02D1 4008
02D1 400C
02D1 4010
02D1 4014
SP0_CS_TX
Port 0 Control Symbol Transmit Register
Reserved
02D1 4018 - 02D1 40FC
02D1 4100
-
SP1_RST_OPT
SP1_CTL_INDEP
SP1_SILENCE_TIMER
SP1_MULT_EVNT_CS
-
Port 1 Reset Option CSR
02D1 4104
Port 1 Control Independent Register
Port 1 Silence Timer Register
Port 1 Multicast-Event Control Symbol Request Register
Reserved
02D1 4108
02D1 410C
02D1 4110
02D1 4114
SP1_CS_TX
Port 1 Control Symbol Transmit Register
Reserved
02D1 4118 - 02D1 42FC
02D1 4200
-
SP2_RST_OPT
SP2_CTL_INDEP
SP2_SILENCE_TIMER
SP2_MULT_EVNT_CS
-
Port 2 Reset Option CSR
02D1 4204
Port 2 Control Independent Register
Port 2 Silence Timer Register
Port 2 Multicast-Event Control Symbol Request Register
Reserved
02D1 4208
02D1 420C
02D1 4210
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Table 7-79. RapidIO Control Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
Port 2 Control Symbol Transmit Register
Reserved
02D1 4214
SP2_CS_TX
02D1 4218 - 02D1 42FC
02D1 4300
-
SP3_RST_OPT
Port 3 Reset Option CSR
Port 3 Control Independent Register
Port 3 Silence Timer Register
Port 3 Multicast-Event Control Symbol Request Register
Reserved
02D1 4304
SP3_CTL_INDEP
02D1 4308
SP3_SILENCE_TIMER
02D1 430C
SP3_MULT_EVNT_CS
02D1 4310
-
02D1 4314
SP3_CS_TX
Port 3 Control Symbol Transmit Register
Reserved
02D1 4318 - 02D2 0FFF
02D2 1000 - 02DF FFFF
-
-
Reserved
7.18.3 Serial RapidIO Electrical Data/Timing
Serial RapidIO is electrically compliant with the RapidIO™ Interconnect Specification, Part VI: Physical
Layer 1x/4x LP-Serial Specification, Revision 1.2.
Table 7-80. Timing Requirements for SRIOSGMIIREFCLK(N|P)(1)
(see Figure 7-43)
NO.
1
PARAMETERS
Cycle time, SRIOSGMIIREFCLK(N|P)
Pulse duration, CLK(N|P) high
Pulse duration, CLK(N|P) low
Transition time, CLK(N|P)
MIN
3.2
MAX UNIT
tc(SRIOSGMIIREFCLK)
tw(CLKH)
8
ns
ns
ns
ps
ps
2
0.4C
0.4C
50
3
tw(CLKL)
4
tt(CLK)
1300
4
5
tj(CLK)
Period Jitter (RMS), CLK(N|P)
(1) C=1/SRIOSGMIIREFCLK(N|P)
1
4
2
SRIOSGMIIREFCLK(N|P)
3
4
Figure 7-43. SRIOSGMIIREFCLK(N|P) Timing
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7.19 General Purpose Input/Output (GPIO)
On the C6474 device, the GPIO peripheral pins GP[11:0] are used to latch configuration pins. These pins
are sampled at power-on reset and are functional as GPIO pins the remainder of the time. For more
detailed information on device/peripheral configuration and the C6474 device pin muxing, see Section 3,
Device Configuration.
7.19.1 GPIO Peripheral Register Description(s)
Table 7-81. GPIO Registers
HEX ADDRESS
02B0 0008
ACRONYM
BINTEN
-
REGISTER NAME
GPIO Interrupt per Bank Enable Register
02B0 000C
Reserved
02B0 0010
DIR
GPIO Direction Register
GPIO Output Data Register
GPIO Set Data Register
GPIO Clear Data Register
GPIO Input Data Register
02B0 0014
OUT_DATA
SET_DATA
CLR_DATA
IN_DATA
02B0 0018
02B0 001C
02B0 0020
02B0 0024
SET_RIS_TRIG GPIO Set Rising Edge Interrupt Register
CLR_RIS_TRIG GPIO Clear Rising Edge Interrupt Register
SET_FAL_TRIG GPIO Set Falling Edge Interrupt Register
CLR_FAL_TRIG GPIO Clear Falling Edge Interrupt Register
02B0 0028
02B0 002C
02B0 0030
02B0 008C
-
-
-
Reserved
Reserved
Reserved
02B0 0090 - 02B0 00FF
02B0 0100 - 02B0 3FFF
7.19.2 GPIO Electrical Data/Timing
Table 7-82. Timing Requirements for GPIO Inputs(1)
(see Figure 7-44)
NO.
PARAMETER
MIN
12C - 3
12C - 3
MAX UNIT
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
ns
ns
(1) C = 1/CPU CLK frequency, in ns.
Table 7-83. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs(1)
(see Figure 7-44)
NO.
1
PARAMETER
Pulse duration, GPOx high
Pulse duration, GPOx low
MIN
36C - 8
36C - 8
MAX UNIT
tw(GPOH)
tw(GPOL)
ns
ns
2
(1) C = 1/CPU CLK frequency, in ns.
2
1
GPIx
4
3
GPOx
Figure 7-44. GPIO Timing
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7.20 Emulation Features and Capability
7.20.1 Advanced Event Triggering (AET)
The C6474 device supports Advanced Event Triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides
the following capabilities:
•
Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
•
Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
•
•
Counters: count the occurrence of an event or cycles for performance monitoring.
State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
For more information on AET, see the following documents:
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report (literature
number SPRA753)
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems application report (literature number SPRA387)
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7.20.2 Trace
The C6474 device supports Trace. Trace is a debug technology that provides a detailed, historical
account of application code execution, timing, and data accesses. Trace collects, compresses, and
exports debug information for analysis. Trace works in real-time and does not impact the execution of the
system.
For more information on board design guidelines for Trace Advanced Emulation, see the 60-Pin Emulation
Header Technical Reference (literature number SPRU655).
Table 7-84. Timing Requirements for Trace
(see Figure 7-45)
NO.
1
PARAMETER
Pulse duration, EMUn high
tw(EMUnH) 90% Pulse duration, EMUn high detected at 90% VOH
MIN
3 - 0.6(1)
1.5
MAX UNITS
tw(EMUnH)
ns
ns
ns
ns
ns
ns
1
1a
1b
2
tw(TCKH)
tw(TCKL)
tw(EMUnL)
Pulse width time TCK high
Pulse width time TCK low
Pulse duration, EMUn low
8
8
3 - 0.6(1)
2
tw(EMUnL) 10% Pulse duration, EMUn low detected at 10% VOH
tsko(EMUn) Output Skew time, time delay difference between EMU pins configured as
1.5
3
-500
500
ps
trace.
4
tskp(EMUn)
Pulse Skew, magnitude of time difference between high-to-low (TPHL) and
low-to-high (TPLH) propagation delays.
600(1)
ps
(1) This parameter applies to the maximum trace export frequency operating in a 40/60 duty cycle.
A
tPHL
tPLH
1
2
B
C
3
Figure 7-45. Trace Timing
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7.20.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan
supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g. no EMU[1:0])
required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification
(IEEE1149.1), while all of the SerDes (Antenna Interface, RapidIO, and SGMII) support the AC coupled
net test defined in AC Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain
fashion, as per the specification. The JTAG interface uses 1.8-V buffers, compliant with the Power Supply
Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.20.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6474 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive
TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of
an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the
DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan
operations.
7.20.3.2 JTAG Electrical Data/Timing
Table 7-85. Timing Requirements for JTAG
(see Figure 7-46)
NO.
1
PARAMETER
MIN
20
8
MAX UNITS
tc(TCK)
Cycle time, TCK
ns
ns
ns
1a
1b
2
tw(TCKH)
Pulse width time TCK high
tw(TCKL)
Pulse width time TCK low
8
td(TCKL-TDOV)
tsu(TDIV-TCKH)
tsu(TMSV-TCKH)
th(TCKH-TDIV)
th(TCKH-TMSV)
Delay time, TCK low to TDO valid
Setup time, TDI valid before TCK high
Setup time, TMS valid before TCK high
Hold time, TDI valid after TCK high
Hold time, TMS valid after TCK high
0
8
ns
ns
ns
ns
ns
3a
3b
4a
4b
2
2
10
10
1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
Figure 7-46. JTAG Timing
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Table 7-86. Timing Requirements for HS-RTDX
(see Figure 7-47)
NO.
PARAMETER
MIN
20
1.5
1.5
3
MAX UNITS
1
2
3
4
5
6
tc(TCK)
Cycle time, TCK
ns
ns
ns
tsu(TCKH-EMUn)
th(TCKH-EMUn)
td(TCKH-EMUn)
tpoz(EMUn)
Setup time, EMUn input valid before TCK high
Hold time, EMUn input valid after TCK high
Delay time, TCK high to EMUn output valid
Propagation delay from output to high impedance
Propagation delay from high impedance to output
16.5
16.5
16.5
ns
ns
ns
3
tpzo (EMUn)
3
1
TCK
4
2
3
EMU[n]
Figure 7-47. HS-RTDX Timing
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7.21 Semaphore
The device contains the Semaphore module for the management of shared resources of the DSP cores.
The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write
sequence is not broken. The semaphore block has unique interrupts to each of the cores to identify when
that core has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software
requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports 3 masters and contains 32 semaphores to be used within the system.
There are two methods of accessing a semaphore resource:
•
Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted.
If not, the semaphore is not granted.
•
Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an
interrupt notifies the CPU that it is available.
7.21.1 Semaphore Register Description(s)
Table 7-87. Semaphore Registers
HEX ADDRESS
02B4 0000
02B4 000C
02B4 0100
02B4 0104
02B4 0108
02B4 010C
02B4 0110
02B4 0114
02B4 0118
02B4 011C
02B4 0120
02B4 0124
02B4 0128
02B4 012C
02B4 0130
02B4 0134
02B4 0138
02B4 013C
02B4 0140
02B4 0144
02B4 0148
02B4 014C
02B4 0150
02B4 0154
02B4 0158
02B4 015C
02B4 0160
02B4 0164
02B4 0168
02B4 016C
02B4 0170
ACRONYM
REGISTER NAME
Semaphore Peripheral Revision ID Register
Semaphore EOI Register
SEM_PID
SEM_EOI
SEM_DIRECT0
SEM_DIRECT1
SEM_DIRECT2
SEM_DIRECT3
SEM_DIRECT4
SEM_DIRECT5
SEM_DIRECT6
SEM_DIRECT7
SEM_DIRECT8
SEM_DIRECT9
SEM_DIRECT10
SEM_DIRECT11
SEM_DIRECT12
SEM_DIRECT13
SEM_DIRECT14
SEM_DIRECT15
SEM_DIRECT16
SEM_DIRECT17
SEM_DIRECT18
SEM_DIRECT19
SEM_DIRECT20
SEM_DIRECT21
SEM_DIRECT22
SEM_DIRECT23
SEM_DIRECT24
SEM_DIRECT25
SEM_DIRECT26
SEM_DIRECT27
SEM_DIRECT28
Semaphore Direct0 Register
Semaphore Direct1 Register
Semaphore Direct2 Register
Semaphore Direct3 Register
Semaphore Direct4 Register
Semaphore Direct5 Register
Semaphore Direct6 Register
Semaphore Direct7 Register
Semaphore Direct8 Register
Semaphore Direct9 Register
Semaphore Direct10 Register
Semaphore Direct11 Register
Semaphore Direct12 Register
Semaphore Direct13 Register
Semaphore Direct14 Register
Semaphore Direct15 Register
Semaphore Direct16 Register
Semaphore Direct17 Register
Semaphore Direct18 Register
Semaphore Direct19 Register
Semaphore Direct20 Register
Semaphore Direct21 Register
Semaphore Direct22 Register
Semaphore Direct23 Register
Semaphore Direct24 Register
Semaphore Direct25 Register
Semaphore Direct26 Register
Semaphore Direct27 Register
Semaphore Direct28 Register
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Table 7-87. Semaphore Registers (continued)
HEX ADDRESS
02B4 0174
02B4 0178
02B4 017C
02B4 0200
02B4 0204
02B4 0208
02B4 020C
02B4 0210
02B4 0214
02B4 0218
02B4 021C
02B4 0220
02B4 0224
02B4 0228
02B4 022C
02B4 0230
02B4 0234
02B4 0238
02B4 023C
02B4 0240
02B4 0244
02B4 0248
02B4 024C
02B4 0250
02B4 0254
02B4 0258
02B4 025C
02B4 0260
02B4 0264
02B4 0268
02B4 026C
02B4 0270
02B4 0274
02B4 0278
02B4 027C
02B4 0300
02B4 0304
02B4 0308
02B4 030C
02B4 0310
02B4 0314
02B4 0318
02B4 031C
02B4 0320
02B4 0324
02B4 0328
02B4 032C
ACRONYM
REGISTER NAME
Semaphore Direct29 Register
SEM_DIRECT29
SEM_DIRECT30
SEM_DIRECT31
SEM_INDIRECT0
SEM_INDIRECT1
SEM_INDIRECT2
SEM_INDIRECT3
SEM_INDIRECT4
SEM_INDIRECT5
SEM_INDIRECT6
SEM_INDIRECT7
SEM_INDIRECT8
SEM_INDIRECT9
SEM_INDIRECT10
SEM_INDIRECT11
SEM_INDIRECT12
SEM_INDIRECT13
SEM_INDIRECT14
SEM_INDIRECT15
SEM_INDIRECT16
SEM_INDIRECT17
SEM_INDIRECT18
SEM_INDIRECT19
SEM_INDIRECT20
SEM_INDIRECT21
SEM_INDIRECT22
SEM_INDIRECT23
SEM_INDIRECT24
SEM_INDIRECT25
SEM_INDIRECT26
SEM_INDIRECT27
SEM_INDIRECT28
SEM_INDIRECT29
SEM_INDIRECT30
SEM_INDIRECT31
SEM_QUERY0
Semaphore Direct30 Register
Semaphore Direct31 Register
Semaphore Indirect0 Register
Semaphore Indirect1 Register
Semaphore Indirect2 Register
Semaphore Indirect3 Register
Semaphore Indirect4 Register
Semaphore Indirect5 Register
Semaphore Indirect6 Register
Semaphore Indirect7 Register
Semaphore Indirect8 Register
Semaphore Indirect9 Register
Semaphore Indirect10 Register
Semaphore Indirect11 Register
Semaphore Indirect12 Register
Semaphore Indirect13 Register
Semaphore Indirect14 Register
Semaphore Indirect15 Register
Semaphore Indirect16 Register
Semaphore Indirect17 Register
Semaphore Indirect18 Register
Semaphore Indirect19 Register
Semaphore Indirect20 Register
Semaphore Indirect21 Register
Semaphore Indirect22 Register
Semaphore Indirect23 Register
Semaphore Indirect24 Register
Semaphore Indirect25 Register
Semaphore Indirect26 Register
Semaphore Indirect27 Register
Semaphore Indirect28 Register
Semaphore Indirect29 Register
Semaphore Indirect30 Register
Semaphore Indirect31 Register
Semaphore Query0 Register
Semaphore Query1 Register
Semaphore Query2 Register
Semaphore Query3 Register
Semaphore Query4 Register
Semaphore Query5 Register
Semaphore Query6 Register
Semaphore Query7 Register
Semaphore Query8 Register
Semaphore Query9 Register
Semaphore Query10 Register
Semaphore Query11 Register
SEM_QUERY1
SEM_QUERY2
SEM_QUERY3
SEM_QUERY4
SEM_QUERY5
SEM_QUERY6
SEM_QUERY7
SEM_QUERY8
SEM_QUERY9
SEM_QUERY10
SEM_QUERY11
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Table 7-87. Semaphore Registers (continued)
HEX ADDRESS
02B4 0330
02B4 0334
02B4 0338
02B4 033C
02B4 0340
02B4 0344
02B4 0348
02B4 034C
02B4 0350
02B4 0354
02B4 0358
02B4 035C
02B4 0360
02B4 0364
02B4 0368
02B4 036C
02B4 0370
02B4 0374
02B4 0378
02B4 037C
02B4 0400
02B4 0404
02B4 0408
ACRONYM
SEM_QUERY12
SEM_QUERY13
SEM_QUERY14
SEM_QUERY15
SEM_QUERY16
SEM_QUERY17
SEM_QUERY18
SEM_QUERY19
SEM_QUERY20
SEM_QUERY21
SEM_QUERY22
SEM_QUERY23
SEM_QUERY24
SEM_QUERY25
SEM_QUERY26
SEM_QUERY27
SEM_QUERY28
SEM_QUERY29
SEM_QUERY30
SEM_QUERY31
SEM_FLAG0
REGISTER NAME
Semaphore Query12 Register
Semaphore Query13 Register
Semaphore Query14 Register
Semaphore Query15 Register
Semaphore Query16 Register
Semaphore Query17 Register
Semaphore Query18 Register
Semaphore Query19 Register
Semaphore Query20 Register
Semaphore Query21 Register
Semaphore Query22 Register
Semaphore Query23 Register
Semaphore Query24 Register
Semaphore Query25 Register
Semaphore Query26 Register
Semaphore Query27 Register
Semaphore Query28 Register
Semaphore Query29 Register
Semaphore Query30 Register
Semaphore Query31 Register
Semaphore Flag0 Register (for C64x+ Core0)
Semaphore Flag1 Register (for C64x+ Core1)
Semaphore Flag2 Register (for C64x+ Core2)
Reserved
SEM_FLAG1
SEM_FLAG2
02B4 040C - 02B4 047C
02B4 0480
Reserved
SEM_FLAG_SET0
SEM_FLAG_SET1
SEM_FLAG_SET2
Reserved
Semaphore Flag Set0 Register (for C64x+ Core0)
Semaphore Flag Set1 Register (for C64x+ Core1)
Semaphore Flag Set2 Register (for C64x+ Core2)
Reserved
02B4 0484
02B4 0488
02B4 048C - 02B4 04FF
02B4 0500
SEM_ERR
Semaphore Error Register
02B4 0504
SEM_ERR_CLR
Reserved
Semaphore Error Clear Register
Reserved
02B4 050C - 02B4 07FF
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7.22 Antenna Interface Subsystem
The Antenna Interface Subsystem (AIF) consists of the Antenna Interface module and two SERDES
macros. The AIF relies on the performance SerDes macro (high-speed serial link) with a logic layer for the
OBSAI RP3 and CPRI protocols. The AIF is used to connect to the backplane for transmission and
reception of antenna data, as well as to additional device peripherals.
The AIF supports OBSAI/CPRI daisy chaining between DSPs:
•
•
OBSAI - 768Mbps, 1.536Gbps, 3.072Gbps link rates supported
CPRI - 614.4Mbps, 1.2288Gbps, 2.4576Gbps link rates supported
OBSAI and CPRI standards compliant antenna interface
•
6 configurable (Full Duplex) high-speed serial links in either OBSAI or CPRI modes that can support a
variety of data rates:
•
•
•
•
Supports star or daisy chain topologies.
Each link can be used for uplink or downlink.
Multiple slower links can be combined into faster speed links.
Controls Word content supplied via DSP software.
The AIF is a slave peripheral, accepting all transactions from the DMA switch fabric, providing uplink data
to device memory and transmitting downlink, delayed stream, and PIC data from device memory. Each
link of the antenna interface includes a differential receive and transmit signal pair.
Table 7-88. AIF Receive and Transmit Signal Pairs
PIN NAMES
AIFTXN [5:0]
AIFTXP [5:0]
AIFRXN [5:0]
AIFRXP [5:0]
I/O
OUT
OUT
IN
NUMBER
DESCRIPTION
6
6
6
6
Antenna Interface Links 0-5 Transmit (Neg) Data Lines.
Antenna Interface Links 0-5 Transmit (Pos) Data Lines.
Antenna Interface Links 0-5 Receive (Neg) Data Lines.
Antenna Interface Links 0-5 Receive (Pos) Data Lines.
IN
7.22.1 Antenna Interface System (AIF) Register Description(s)
Table 7-89. Antenna Interface System Registers
HEX ADDRESS
02BC 0000
ACRONYM
AIF_PD
REGISTER NAME
AI Peripheral ID
02BC 0004
AIF_GLOBAL_CFG
AIF_EMU_CNTL
VC_BUS_ERR
-
AI Global Configuration
AI Emulation Control
VC Bus Error Register
Reserved
02BC 0008
02BC 000C
02BC 0010 - 02BC 2FFC
02BC 3000
CD_OUT_MUX_SEL_CFG
Combiner - Decombiner Output Mux Select Config
Register 0
02BC 3004
02BC 3008
CD_CB_SRC_SEL_CFG
Combiner Source Select Config Register
Combiner Alignment Offset Config Register
Combiner Valid Window Config Register
Decombiner Source Select Config Register
Decombiner Destination Select Config Register
Reserved
CD_CB_OFFSET_CFG
02BC 300C
CD_CB_VALID_WIND_CFG
02BC 3010
CD_DC_SRC_SEL_CFG
02BC 3014
CD_DC_DST_SEL_CFG
02BC 3018 - 02BC 307C
02BC 3080
-
CD_STS
Combiner - Decombiner Status Register
Reserved
02BC 3084 - 02BC 3FFC
02BC 4000
-
LINK0_CFG
-
Link 0 Configuration Register
Reserved
02BC 4004 - 02BC 47FC
02BC 4800
LINK1_CFG
Link 1 Configuration Register
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02BC 4804 - 02BC 4FFC
02BC 5000
-
Reserved
LINK2_CFG
Link 2 Configuration Register
Reserved
02BC 5004 - 02BC 57FC
02BC 5800
-
LINK3_CFG
Link 3 Configuration Register
Reserved
02BC 5804 - 02BC 5FFC
02BC 6000
-
LINK4_CFG
-
Link 4 Configuration Register
Reserved
02BC 6004 - 02BC 67FC
02BC 6800
LINK5_CFG
Link 5 Configuration Register
02BC 6804 - 02BC 6FFC
02BC 7000
AIF_SERDES0_PLL_CFG
AIF_SERDES1_PLL_CFG
AIF_SERDES0_TST_CFG
AIF_SERDES1_TST_CFG
-
AI SerDes 0 PLL Configuration
AI SerDes 1 PLL Configuration
AI SerDes 0 Test Configuration
AI SerDes 1 Test Configuration
Reserved
02BC 7004
02BC 7008
02BC 700C
02BC 7010 - 02BC 707C
02BC 7080
SERDES_STS
SERDES Status Register
02BC 8000
RM_LINK0_CFG
RX MAC Link 0 Configuration Register
RX MAC Link 0 Pi Offset Register
RX MAC Link 0 LOS Threshold Register
RX MAC Link 1 Configuration Register
RX MAC Link 1 Pi Offset Register
RX MAC Link 1 LOS Threshold Register
RX MAC Link Status Register A
RX MAC Link Status Register B
RX MAC Link Status Register C
RX MAC Link Status Register D
Reserved
02BC 8004
RM_LINK0_PI_OFFSET_CFG
RM_LINK0_LOS_THOLD_CFG
RM_LINK1_CFG
02BC 8008
02BC 8800
02BC 8804
RM_LINK1_PI_OFFSET_CFG
RM_LINK1_LOS_THOLD_CFG
RM_LINK_STSA
02BC 8808
02BC 8880
02BC 8884
RM_LINK_STSB
02BC 8888
RM_LINK_STSC
02BC 888C
RM_LINK_STSD
02BC 8890 - 02BC 8FFC
02BC 9000
-
RM_LINK2_CFG
RX MAC Link 2 Configuration Register
RX MAC Link 2 Pi Offset Register
RX MAC Link 2 LOS Threshold Register
Reserved
02BC 9004
RM_LINK2_PI_OFFSET_CFG
RM_LINK2_LOS_THOLD_CFG
-
02BC 9008
02BC 900C - 02BC 97FC
02BC 9800
RM_LINK3_CFG
RX MAC Link 3 Configuration Register
RX MAC Link 3 Pi Offset Register
RX MAC Link 3 LOS Threshold Register
Reserved
02BC 9804
RM_LINK3_PI_OFFSET_CFG
RM_LINK3_LOS_THOLD_CFG
-
02BC 9808
02BC 980C - 02BC 9FFC
02BC A000
RM_LINK4_CFG
RX MAC Link 4 Configuration Register
RX MAC Link 4 LOS Threshold Register
RX MAC Link 5 Pi Offset Register
RX MAC Link 5 LOS Threshold Register
Reserved
02BC A008
RM_LINK4_LOS_THOLD_CFG
RM_LINK5_PI_OFFSET_CFG
RM_LINK5_LOS_THOLD_CFG
-
02BC A804
02BC A808
02BC A80C - 02BC AFFC
02BC B000
RM_ SYNC_CNT_CFG
RM_UNSYNC_CNT_CFG
-
RX MAC Common Sync Counter Register
RX MAC Unsync Count Configuration Register
Reserved
02BC B004
02BC B008 - 02BC BFFC
02BC C000
TM_LINK0_0CFG
TM_LINK0_1CFG
TM_LINK0_2CFG
-
TX MAC Link 0 Configuration Register 0
TX MAC Link 0 Configuration Register 1
TX MAC Link 0 Configuration Register 2
Reserved
02BC C004
02BC C008
02BC C00C - 02BC C07C
02BC C080
TM_LINK0_STS
TX MAC Link 0 Status Register
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
02BC C084 - 02BC C7FC
02BC C800
ACRONYM
REGISTER NAME
TM_LINK1_0CFG
TX MAC Link 1 Configuration Register 0
TX MAC Link 1 Configuration Register 1
TX MAC Link 1 Configuration Register 2
Reserved
02BC C804
TM_LINK1_1CFG
02BC C808
TM_LINK1_2CFG
02BC C80C - 02BC C87C
02BC C880
-
TM_LINK1_STS
TX MAC Link 1 Status Register
Reserved
02BC C884 - 02BC CFFC
02BC D000
-
TM_LINK2_0CFG
TX MAC Link 2 Configuration Register 0
TX MAC Link 2 Configuration Register 1
TX MAC Link 2 Configuration Register 2
Reserved
02BC D004
TM_LINK2_1CFG
02BC D008
TM_LINK2_2CFG
02BC D00C - 02BC D07C
02BC D080
-
TM_LINK2_STS
TX MAC Link 2 Status Register
Reserved
02BC D08C - 02BC D7FC
02BC D800
-
TM_LINK3_0CFG
TM_LINK3_1CFG
TM_LINK3_2CFG
-
TX MAC Link 3 Configuration Register 0
TX MAC Link 3 Configuration Register 1
TX MAC Link 3 Configuration Register 2
Reserved
02BC D804
02BC D808
02BC D80C - 02BC D87C
02BC D880
TM_LINK3_STS
-
TX MAC Link 3 Status Register
Reserved
02BC D884 - 02BC DFFC
02BC E000
TM_LINK4_0CFG
TM_LINK4_1CFG
TM_LINK4_2CFG
-
TX MAC Link 4 Configuration Register 0
TX MAC Link 4 Configuration Register 1
TX MAC Link 4 Configuration Register 2
Reserved
02BC E004
02BC E008
02BC E00C - 02BC E07C
02BC E080
TM_LINK4_STS
-
TX MAC Link 4 Status Register
Reserved
02BC E084 - 02BC E7FC
02BC E800
TM_LINK5_0CFG
TM_LINK5_1CFG
TM_LINK5_2CFG
-
TX MAC Link 5 Configuration Register 0
TX MAC Link 5 Configuration Register 1
TX MAC Link 5 Configuration Register 2
Reserved
02BC E804
02BC E808
02BC E80C - 02BC E87C
02BC E880
TM_LINK5_STS
-
TX MAC Link 5 Status Register
Reserved
02BC E884 - 02BC FFFC
02BD 0000 - 02BD 3FFC
02BD 4000
-
Reserved
AG_LINK0_CFG
AG_LINK0_STS
AG_LINK0_HDR_ERR_STSA
AG_LINK0_HDR_ERR_STSB
AG_LINK0_HDR_ERR_STSC
AG_LINK0_HDR_ERR_STSD
-
AG Link 0 Configuration Register
AG Link 0 Status Register
02BD 4004
02BD 4008
AG Link 0 Header Error Status Register 0
AG Link 0 Header Error Status Register 1
AG Link 0 Header Error Status Register 2
AG Link 0 Header Error Status Register 3
Reserved
02BD 400C
02BD 4010
02BD 4014
02BD 4018 - 02BD 47FC
02BD 4800
AG_LINK1_CFG
AG_LINK1_STS
AG_LINK1_HDR_ERR_STSA
AG_LINK1_HDR_ERR_STSB
AG_LINK1_HDR_ERR_STSC
AG_LINK1_HDR_ERR_STSD
-
AG Link 1 Configuration Register
AG Link 1 Status Register
02BD 4804
02BD 4808
AG Link 1 Header Error Status Register 0
AG Link 1 Header Error Status Register 1
AG Link 1 Header Error Status Register 2
AG Link 1 Header Error Status Register 3
Reserved
02BD 480C
02BD 4810
02BD 4814
02BD 4818 - 02BD 4FFC
02BD 5000
AG_LINK2_CFG
AG Link 2 Configuration Register
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
02BD 5004
02BD 5008
02BD 500C
02BD 5010
02BD 5014
ACRONYM
REGISTER NAME
AG Link 2 Status Register
AG_LINK2_STS
AG_LINK2_HDR_ERR_STSA
AG Link 2 Header Error Status Register 0
AG Link 2 Header Error Status Register 1
AG Link 2 Header Error Status Register 2
AG Link 2 Header Error Status Register 3
Reserved
AG_LINK2_HDR_ERR_STSB
AG_LINK2_HDR_ERR_STSC
AG_LINK2_HDR_ERR_STSD
02BD 5018 - 02BD 57FC
02BD 5800
-
AG_LINK3_CFG
AG Link 3 Configuration Register
AG Link 3 Status Register
AG Link 3 Header Error Status Register 0
AG Link 3 Header Error Status Register 1
AG Link 3 Header Error Status Register 2
AG Link 3 Header Error Status Register 3
Reserved
02BD 5804
AG_LINK3_STS
02BD 5808
AG_LINK3_HDR_ERR_STSA
02BD 580C
AG_LINK3_HDR_ERR_STSB
02BD 5810
AG_LINK3_HDR_ERR_STSC
02BD 5814
AG_LINK3_HDR_ERR_STSD
02BD 5818 - 02BD 5FFC
02BD 6000
-
AG_LINK4_CFG
AG Link 4 Configuration Register
AG Link 4 Status Register
AG Link 4 Header Error Status Register 0
AG Link 4 Header Error Status Register 1
AG Link 4 Header Error Status Register 2
AG Link 4 Header Error Status Register 3
Reserved
02BD 6004
AG_LINK4_STS
02BD 6008
AG_LINK4_HDR_ERR_STSA
02BD 600C
AG_LINK4_HDR_ERR_STSB
02BD 6010
AG_LINK4_HDR_ERR_STSC
02BD 6014
AG_LINK4_HDR_ERR_STSD
02BD 6018 - 02BD 67FC
02BD 6800
-
AG_LINK5_CFG
AG Link 5 Configuration Register
AG Link 5 Status Register
AG Link 5 Header Error Status Register 0
AG Link 5 Header Error Status Register 1
AG Link 5 Header Error Status Register 2
AG Link 5 Header Error Status Register 3
Reserved
02BD 6804
AG_LINK5_STS
02BD 6808
AG_LINK5_HDR_ERR_STSA
02BD 680C
AG_LINK5_HDR_ERR_STSB
02BD 6810
AG_LINK5_HDR_ERR_STSC
02BD 6814
AG_LINK5_HDR_ERR_STSD
02BD 6818 - 02BD 7FFC
02BD 8000
-
CI_LINK0_CFG
CI Link 0 Configuration Register
Reserved
02BD 8004 - 02BD 87FC
02BD 8800
-
CI_LINK1_CFG
CI Link 1 Configuration Register
Reserved
02BD 8804 - 02BD 8FFC
02BD 9000
-
CI_LINK2_CFG
CI Link 2 Configuration Register
Reserved
02BD 9004 - 02BD 97FC
02BD 9800
-
CI_LINK3_CFG
CI Link 3 Configuration Register
Reserved
02BD 9804 - 02BD 9FFC
02BD A000
-
CI_LINK4_CFG
CI Link 4 Configuration Register
Reserved
02BD A004 - 02BD A7FC
02BD A800
-
CI_LINK5_CFG
CI Link 5 Configuration Register
Reserved
02BD A804 - 02BD BFFC
02BD C000
-
CO_LINK0_CFG
CO Link 0 Configuration Register
Reserved
02BD C004 - 02BD C7FC
02BD C800
-
CO_LINK1_CFG
CO Link 1 Configuration Register
Reserved
02BD C804 - 02BD CFFC
02BD D000
-
CO_LINK2_CFG
CO Link 2 Configuration Register
Reserved
02BD D004 - 02BD D7FC
02BD D800
-
CO_LINK3_CFG
-
CO Link 3 Configuration Register
Reserved
02BD D804 - 02BD DFFC
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
02BD E000
ACRONYM
CO_LINK4_CFG
-
REGISTER NAME
CO Link 4 Configuration Register
02BD E004 - 02BD E7FC
02BD E800
Reserved
CO_LINK5_CFG
-
CO Link 5 Configuration Register
Reserved
02BD E804 - 02BE 3000
02BE 3004
DB_GENERIC_CFG
DB_DMA_QUE_CLR_CFG
DB_DMA_CNT_CLR_CFG
DB_OUT_PKTSW_EN_CFG
Data Buffer Configuration Register
Data Buffer DMA Depth Clear Register
Data Buffer DMA Count Clear Register
02BE 3008
02BE 300C
02BE 3010
Data Buffer Outbound Packet Switched FIFO Enable
Register
02BE 3014
02BE 3018
02BE 301C
DB_OUT_PKTSW_FLUSH_CFG
DB_IN_FIFO_EVNT_CFG
DB_IN_FIFO_SIZE_CFG
Data Buffer Inbound Packet Switched FIFO Flush Register
Data Buffer Inbound Packet Switched FIFO Flush Register
Data Buffer Inbound Packet Switched FIFO Depth
Register
02BE 3020
02BE 3024
DB_FORCE_SYSEVENT_CFG
Data Buffer Force System Events Register
DB_OUTB_TRK_AUTOSYNC_CFG Data Buffer PE Tracker Auto Sync Control Register
02BE 3028
DB_INB_TRK_AUTOSYNC_CFG
-
Data Buffer PD Tracker Auto Sync Control Register
Reserved
02BE 302C - 02BE 303C
02BE 3040
DB_IN_DMA_CNT0_STS
DB_IN_DMA_CNT1_STS
DB_IN_DMA_CNT2_STS
DB_OUT_DMA_CNT0_STS
DB_OUT_DMA_CNT1_STS
DB_OUT_DMA_CNT2_STS
DB_IN_DMA_DEPTH_STS
DB_OUT_DMA_DEPTH_STS
DB_OUT_PKTSW_STS
Data Buffer Inbound DMA Count 0 Register
Data Buffer Inbound DMA Count 1 Register
Data Buffer Inbound DMA Count 2 Register
Data Buffer Outbound DMA Count 0 Register
Data Buffer Outbound DMA Count 1 Register
Data Buffer Outbound DMA Count 2 Register
Data Buffer Inbound DMA Burst Available Register
Data Buffer Outbound DMA Burst Available Register
02BE 3044
02BE 3048
02BE 304C
02BE 3050
02BE 3054
02BE 3058
02BE 305C
02BE 3060
Data Buffer Outbound Packet Switched FIFO Status
Register
02BE 3064
02BE 3068
DB_OUT_PKTSW_DEPTH_STS
DB_OUT_PKTSW_NE_STS
Data Buffer Outbound Packet Switched FIFO Depth
Register
Data Buffer Outbound Packet Switched FIFO Not Empty
Register
02BE 306C - 02BE 307C
02BE 3080
-
Reserved
DB_OUT_PKTSW_HEAD0_STS
Data Buffer Outbound Packet Switched FIFO0 Head
Pointer
02BE 3084
02BE 3088
02BE 308C
02BE 3090
02BE 3094
02BE 3098
02BE 309C
02BE 30A0
02BE 30A4
DB_OUT_PKTSW_HEAD1_STS
DB_OUT_PKTSW_HEAD2_STS
DB_OUT_PKTSW_HEAD3_STS
DB_OUT_PKTSW_HEAD4_STS
DB_OUT_PKTSW_HEAD5_STS
DB_OUT_PKTSW_HEAD6_STS
DB_OUT_PKTSW_HEAD7_STS
DB_OUT_PKTSW_HEAD8_STS
DB_OUT_PKTSW_HEAD9_STS
Data Buffer Outbound Packet Switched FIFO1 Head
Pointer
Data Buffer Outbound Packet Switched FIFO2 Head
Pointer
Data Buffer Outbound Packet Switched FIFO3 Head
Pointer
Data Buffer Outbound Packet Switched FIFO4 Head
Pointer
Data Buffer Outbound Packet Switched FIFO5 Head
Pointer
Data Buffer Outbound Packet Switched FIFO6 Head
Pointer
Data Buffer Outbound Packet Switched FIFO7 Head
Pointer
Data Buffer Outbound Packet Switched FIFO8 Head
Pointer
Data Buffer Outbound Packet Switched FIFO9 Head
Pointer
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02BE 30A8
DB_OUT_PKTSW_HEAD10_STS
Data Buffer Outbound Packet Switched FIFO10 Head
Pointer
02BE 30AC
02BE 30B0
02BE 30B4
02BE 30B8
DB_OUT_PKTSW_HEAD11_STS
DB_OUT_PKTSW_HEAD12_STS
DB_OUT_PKTSW_HEAD13_STS
DB_OUT_PKTSW_HEAD14_STS
Data Buffer Outbound Packet Switched FIFO11 Head
Pointer
Data Buffer Outbound Packet Switched FIFO12 Head
Pointer
Data Buffer Outbound Packet Switched FIFO13 Head
Pointer
Data Buffer Outbound Packet Switched FIFO14 Head
Pointer
02BE 30BC
02BE 30C0
02BE 30C4
02BE 30C8
02BE 30CC
02BE 30D0
02BE 30D4
02BE 30D8
02BE 30DC
02BE 30E0
02BE 30E4
02BE 30E8
-
Reserved
DB_OUT_PKTSW_TAIL0_STS
DB_OUT_PKTSW_TAIL1_STS
DB_OUT_PKTSW_TAIL2_STS
DB_OUT_PKTSW_TAIL3_STS
DB_OUT_PKTSW_TAIL4_STS
DB_OUT_PKTSW_TAIL5_STS
DB_OUT_PKTSW_TAIL6_STS
DB_OUT_PKTSW_TAIL7_STS
DB_OUT_PKTSW_TAIL8_STS
DB_OUT_PKTSW_TAIL9_STS
DB_OUT_PKTSW_TAIL10_STS
Data Buffer Outbound Packet Switched FIFO0 Tail Pointer
Data Buffer Outbound Packet Switched FIFO1 Tail Pointer
Data Buffer Outbound Packet Switched FIFO2 Tail Pointer
Data Buffer Outbound Packet Switched FIFO3 Tail Pointer
Data Buffer Outbound Packet Switched FIFO4 Tail Pointer
Data Buffer Outbound Packet Switched FIFO5 Tail Pointer
Data Buffer Outbound Packet Switched FIFO6 Tail Pointer
Data Buffer Outbound Packet Switched FIFO7 Tail Pointer
Data Buffer Outbound Packet Switched FIFO8 Tail Pointer
Data Buffer Outbound Packet Switched FIFO9 Tail Pointer
Data Buffer Outbound Packet Switched FIFO10 Tail
Pointer
02BE 30EC
02BE 30F0
02BE 30F4
02BE 30F8
DB_OUT_PKTSW_TAIL11_STS
DB_OUT_PKTSW_TAIL12_STS
DB_OUT_PKTSW_TAIL13_STS
DB_OUT_PKTSW_TAIL14_STS
Data Buffer Outbound Packet Switched FIFO11 Tail
Pointer
Data Buffer Outbound Packet Switched FIFO12 Tail
Pointer
Data Buffer Outbound Packet Switched FIFO13 Tail
Pointer
Data Buffer Outbound Packet Switched FIFO14 Tail
Pointer
02BE 30FC - 02BE 3FFC
02BE 4000
-
Reserved
PD_LINK0_84CNT_LUT0_CFG
PD_LINK0_84CNT_LUT1_CFG
PD_LINK0_84CNT_LUT2_CFG
PD_LINK0_CPRI_SI_LUT0_CFG
PD_LINK0_CPRI_SI_LUT1_CFG
-
PD 84 Count Look-Up Table bits [31:0]
PD 84 Count Look-Up Table bits [63:32]
PD 84 Count Look-Up Table bits [83:64]
PD CPRI Stream Index LUT0 Register
PD CPRI Stream Index LUT1 Register
Reserved
02BE 4004
02BE 4008
02BE 400C
02BE 4010
02BE 4014 - 02BE 47FC
02BE 4800
PD_LINK1_84CNT_LUT0_CFG
PD_LINK1_84CNT_LUT1_CFG
PD_LINK1_84CNT_LUT2_CFG
PD_LINK1_CPRI_SI_LUT0_CFG
PD_LINK1_CPRI_SI_LUT1_CFG
-
PD 84 Count Look-Up Table bits [31:0]
PD 84 Count Look-Up Table bits [63:32]
PD 84 Count Look-Up Table bits [83:64]
PD CPRI Stream Index LUT0 Register
PD CPRI Stream Index LUT1 Register
Reserved
02BE 4804
02BE 4808
02BE 480C
02BE 4810
02BE 4814 - 02BE 4FFC
02BE 5000
PD_LINK2_84CNT_LUT0_CFG
PD_LINK2_84CNT_LUT1_CFG
PD_LINK2_84CNT_LUT2_CFG
PD_LINK2_CPRI_SI_LUT0_CFG
PD_LINK2_CPRI_SI_LUT1_CFG
-
PD 84 Count Look-Up Table bits [31:0]
PD 84 Count Look-Up Table bits [63:32]
PD 84 Count Look-Up Table bits [83:64]
PD CPRI Stream Index LUT0 Register
PD CPRI Stream Index LUT1 Register
Reserved
02BE 5004
02BE 5008
02BE 500C
02BE 5010
02BE 5014 - 02BE 57FC
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
02BE 5800
ACRONYM
REGISTER NAME
PD 84 Count Look-Up Table bits [31:0]
PD 84 Count Look-Up Table bits [63:32]
PD 84 Count Look-Up Table bits [83:64]
PD CPRI Stream Index LUT0 Register
PD CPRI Stream Index LUT1 Register
Reserved
PD_LINK3_84CNT_LUT0_CFG
PD_LINK3_84CNT_LUT1_CFG
PD_LINK3_84CNT_LUT2_CFG
PD_LINK3_CPRI_SI_LUT0_CFG
PD_LINK3_CPRI_SI_LUT1_CFG
-
02BE 5804
02BE 5808
02BE 580C
02BE 5810
02BE 5814 - 02BE 5FFC
02BE 6000
PD_LINK4_84CNT_LUT0_CFG
PD_LINK4_84CNT_LUT1_CFG
PD_LINK4_84CNT_LUT2_CFG
PD_LINK4_CPRI_SI_LUT0_CFG
PD_LINK4_CPRI_SI_LUT1_CFG
-
PD 84 Count Look-Up Table bits [31:0]
PD 84 Count Look-Up Table bits [63:32]
PD 84 Count Look-Up Table bits [83:64]
PD CPRI Stream Index LUT0 Register
PD CPRI Stream Index LUT1 Register
Reserved
02BE 6004
02BE 6008
02BE 600C
02BE 6010
02BE 6014 - 02BE 67FC
02BE 6800
PD_LINK5_84CNT_LUT0_CFG
PD_LINK5_84CNT_LUT1_CFG
PD_LINK5_84CNT_LUT2_CFG
PD_LINK5_CPRI_SI_LUT0_CFG
PD_LINK5_CPRI_SI_LUT1_CFG
-
PD 84 Count Look-Up Table bits [31:0]
PD 84 Count Look-Up Table bits [63:32]
PD 84 Count Look-Up Table bits [83:64]
PD CPRI Stream Index LUT0 Register
PD CPRI Stream Index LUT1 Register
Reserved
02BE 6804
02BE 6808
02BE 680C
02BE 6810
02BE 6814 - 02BE 6FFC
02BE 7000
PD_0_CFG
Protocol Decoder Configuration Register 0
Protocol Decoder Configuration Register 1
02BE 7004
PD_1_CFG
02BE 7008
PD_ADR_MUX_SEL_CFG
PD_TYPE_CIR_LUT_CFG
Protocol Decoder OBSAI Adr Mux Select Register
02BE 700C
Protocol Decoder Type CirSw Capture Enable LUT
Register
02BE 7010
PD_TYPE_PKT_LUT_CFG
Protocol Decoder Type PktSw Capture Enable LUT
Register
02BE 7014
02BE 7018 - 02BE 77FC
02BE 7800
PD_TYPE_ERR_LUT_CFG
Protocol Decoder Type Error Register
Reserved
-
PD_ADR_LUT
Protocol Decoder Address Look Up Table Register
Reserved
02BE 7804 - 02BE 7FFC
02BE 8000
-
PE_LINK0_84_EN_LUT0_CFG
PE_LINK0_84_EN_LUT1_CFG
PE_LINK0_84_EN_LUT2_CFG
PE_LINK0_TERM_CNT01_CFG
PE_LINK0_TERM_CNT23_CFG
-
PE 84 Count Message Enable bits [31:0]
PE 84 Count Message Enable bits [63:32]
PE 84 Count Message Enable bits [83:64]
PE Transmission Rule Terminal Count 0 and 1
PE Transmission Rule Terminal Count 2 and 3
Reserved
02BE 8004
02BE 8008
02BE 800C
02BE 8010
02BE 8014 - 02BE 81FC
02BE 8200 - 02BE 834C
02BE 8350 - 02BE 83FC
02BE 8400 - 02BE 8450
02BE 8454 - 02BE 84FC
02BE 8500 - 02BE 8550
02BE 8554 - 02BE 87FC
02BE 8800
PE_LINK0_84CNT_LUT
-
PE 84 Count LUT RAM
Reserved
PE_LINK0_ID_LUT0
-
PE Identity LUT Part 0 RAM
Reserved
PE_LINK0_ID_LUT1
-
PE Identity LUT Part 1 RAM
Reserved
PE_LINK1_84_EN_LUT0_CFG
PE_LINK1_84_EN_LUT1_CFG
PE_LINK1_84_EN_LUT2_CFG
PE_LINK1_TERM_CNT01_CFG
PE_LINK1_TERM_CNT23_CFG
-
PE 84 Count Message Enable bits [31:0]
PE 84 Count Message Enable bits [63:32]
PE 84 Count Message Enable bits [83:64]
PE Transmission Rule Terminal Count 0 and 1
PE Transmission Rule Terminal Count 2 and 3
Reserved
02BE 8804
02BE 8808
02BE 880C
02BE 8810
02BE 8814 - 02BE 89FC
02BE 8A00 - 02BE 8B4C
PE_LINK1_84CNT_LUT
PE 84 Count LUT RAM
198
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02BE 8B50 - 02BE 8BFC
02BE 8C00 - 02BE 8C50
02BE 8C54 - 02BE 8CFC
02BE 8D00 - 02BE 8D50
02BE 8D54 - 02BE 8FFC
02BE 9000
-
Reserved
PE_LINK1_ID_LUT0
PE Identity LUT Part 0 RAM
Reserved
-
PE_LINK1_ID_LUT1
PE Identity LUT Part 1 RAM
Reserved
-
PE_LINK2_84_EN_LUT0_CFG
PE 84 Count message Enable bits [31: 0]
PE 84 Count message Enable bits [63 : 32]
PE 84 Count message Enable bits [83 : 64]
PE Transmission Rule Terminal Count 0 and 1
PE Transmission Rule Terminal Count 2 and 3
Reserved
02BE 9004
PE_LINK2_84_EN_LUT1_CFG
02BE 9008
PE_LINK2_84_EN_LUT2_CFG
02BE 900C
PE_LINK2_TERM_CNT01_CFG
02BE 9010
PE_LINK2_TERM_CNT23_CFG
02BE 9014 - 02BE 91FC
02BE 9200 - 02BE 934C
02BE 9350 - 02BE 93FC
02BE 9400 - 02BE 9450
02BE 9454 - 02BE 94FC
02BE 9500 - 02BE 9550
02BE 9554 - 02BE 97FC
02BE 9800
-
PE_LINK2_84CNT_LUT
PE 84 Count LUT RAM
-
Reserved
PE_LINK2_ID_LUT0
PE Identity LUT Part 0 RAM
Reserved
-
PE_LINK2_ID_LUT1
PE Identity LUT Part 1 RAM
Reserved
-
PE_LINK3_84_EN_LUT0_CFG
PE 84 Count message Enable bits [31:0]
PE 84 Count message Enable bits [63:32]
PE 84 Count message Enable bits [83:64]
PE Transmission Rule Terminal Count 0 and 1
PE Transmission Rule Terminal Count 2 and 3
Reserved
02BE 9804
PE_LINK3_84_EN_LUT1_CFG
02BE 9808
PE_LINK3_84_EN_LUT2_CFG
02BE 980C
PE_LINK3_TERM_CNT01_CFG
02BE 9810
PE_LINK3_TERM_CNT23_CFG
02BE 9814 - 02BE 99FC
02BE 9A00 - 02BE 9B4C
02BE 9B50 - 02BE 9BFC
02BE 9C00 - 02BE 9C50
02BE 9C54 - 02BE 9CFC
02BE 9D00 - 02BE 9D50
02BE 9D54 - 02BE 9FFC
02BE A000
-
PE_LINK3_84CNT_LUT
PE 84 Count LUT RAM
-
Reserved
PE_LINK3_ID_LUT0
PE Identity LUT Part 0 RAM
Reserved
-
PE_LINK3_ID_LUT1
PE Identity LUT Part 1 RAM
Reserved
-
PE_LINK4_84_EN_LUT0_CFG
PE_LINK4_84_EN_LUT1_CFG
PE_LINK4_84_EN_LUT2_CFG
PE_LINK4_TERM_CNT01_CFG
PE_LINK4_TERM_CNT23_CFG
-
PE 84 Count Message Enable bits [31:0]
PE 84 Count Message Enable bits [63:32]
PE 84 Count Message Enable bits [83:64]
PE Transmission Rule Terminal Count 0 and 1
PE Transmission Rule Terminal Count 2 and 3
Reserved
02BE A004
02BE A008
02BE A00C
02BE A010
02BE A014 - 02BE A1FC
02BE A200 - 02BE A34C
02BE A350 - 02BE A3FC
02BE A400 - 02BE A450
02BE A454 - 02BE A4FC
02BE A500 - 02BE A550
02BE A554 - 02BE A7FC
02BE A800
PE_LINK4_84CNT_LUT
-
PE 84 Count LUT RAM
Reserved
PE_LINK4_ID_LUT0
-
PE Identity LUT Part 0 RAM
Reserved
PE_LINK4_ID_LUT1
-
PE Identity LUT Part 1 RAM
Reserved
PE_LINK5_84_EN_LUT0_CFG
PE_LINK5_84_EN_LUT1_CFG
PE_LINK5_84_EN_LUT2_CFG
PE_LINK5_TERM_CNT01_CFG
PE_LINK5_TERM_CNT23_CFG
-
PE 84 Count Message Enable bits [31:0]
PE 84 Count Message Enable bits [63:32]
PE 84 Count Message Enable bits [83:64]
PE Transmission Rule Terminal Count 0 and 1
PE Transmission Rule Terminal Count 2 and 3
Reserved
02BE A804
02BE A808
02BE A80C
02BE A810
02BE A814 - 02BE A9FC
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
02BE AA00 - 02BE AB4C
02BE AB50 - 02BE ABFC
02BE AC00 - 02BE AC50
02BE AC54 - 02BE ACFC
02BE AD00 - 02BE AD50
02BE AD54 - 02BE AFFC
02BE B000
ACRONYM
REGISTER NAME
PE 84 Count LUT RAM
PE_LINK5_84CNT_LUT
-
Reserved
PE_LINK5_ID_LUT0
PE Identity LUT Part 0 RAM
Reserved
-
PE_LINK5_ID_LUT1
-
PE Identity LUT Part 1 RAM
Reserved
PE_CFG
Protocol Encoder Configuration Register
Reserved
02BE B004 -02BE FFFC
02BF 0000
-
EE_LINK0_IRS_A
EE_LINK0_IRS_B
EE_LINK0_IMS_A_EV0
EE Link 0 Interrupt Source Raw Status Register A
EE Link 0 Interrupt Source Raw Status Register B
02BF 0004
02BF 0008
EE Link 0 AI_EVENT[0] Interrupt Source Masked Status
Register A
02BF 000C
02BF 0010
02BF 0014
02BF 0018
02BF 001C
02BF 0020
02BF 0024
02BF 0028
02BF 002C
02BF 0030
02BF 0034
EE_LINK0_IMS_B_EV0
EE_LINK0_IMS_A_EV1
EE Link 0 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 0 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE_LINK0_IMS_B_EV1
EE Link 0 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE_LINK0_MSK_SET_A_EV0
EE_LINK0_MSK_SET_B_EV0
EE_LINK0_MSK_SET_A_EV1
EE_LINK0_MSK_SET_B_EV1
EE_LINK0_MSK_CLR_A_EV0
EE_LINK0_MSK_CLR_B_EV0
EE_LINK0_MSK_CLR_A_EV1
EE_LINK0_MSK_CLR_B_EV1
EE Link 0 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 0 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 0 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 0 AI_EVENT[1] Interrupt Source Mask Set
Register B
EE Link 0 AI_EVENT[0] Interrupt Source Mask Clear
Register A
EE Link 0 AI_EVENT[0] Interrupt Source Mask
ClearRegister B
EE Link 0 AI_EVENT[1] Interrupt Source Mask Clear
Register A
EE Link 0 AI_EVENT[1] Interrupt Source Mask Clear
Register B
02BF 0038 - 02BF 07FC
02BF 0800
-
Reserved
EE_LINK1_IRS_A
EE_LINK1_IRS_B
EE_LINK1_IMS_A_EV0
EE Link 1 Interrupt Source Raw Status Register A
EE Link 1 Interrupt Source Raw Status Register B
02BF 0804
02BF 0808
EE Link 1 AI_EVENT[0] Interrupt Source Masked Status
Register A
02BF 080C
02BF 0810
02BF 0814
02BF 0818
02BF 081C
02BF 0820
02BF 0824
EE_LINK1_IMS_B_EV0
EE_LINK1_IMS_A_EV1
EE Link 1 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 1 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE_LINK1_IMS_B_EV1
EE Link 1 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE_LINK1_MSK_SET_A_EV0
EE_LINK1_MSK_SET_B_EV0
EE_LINK1_MSK_SET_A_EV1
EE_LINK1_MSK_SET_B_EV1
EE Link 1 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 1 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 1 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 1 AI_EVENT[1] Interrupt Source Mask Set
RegisterB
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02BF 0828
EE_LINK1_MSK_CLR_A_EV0
EE Link 1 AI_EVENT[0] Interrupt Source Mask Clear
Register A
02BF 082C
02BF 0830
02BF 0834
EE_LINK1_MSK_CLR_B_EV0
EE_LINK1_MSK_CLR_A_EV1
EE_LINK1_MSK_CLR_B_EV1
EE Link 1 AI_EVENT[0] Interrupt Source Mask Clear
Register B
EE Link 1 AI_EVENT[1] Interrupt Source Mask Clear
Register A
EE Link 1 AI_EVENT[1] Interrupt Source Mask Clear
Register B
02BF 0838 - 02BF 0FFC
02BF 1000
-
Reserved
EE_LINK2_IRS_A
EE_LINK2_IRS_B
EE_LINK2_IMS_A_EV0
EE Link 2 Interrupt Source Raw Status Register A
EE Link 2 Interrupt Source Raw Status Register B
02BF 1004
02BF 1008
EE Link 2 AI_EVENT[0] Interrupt Source Masked Status
Register A
02BF 100C
02BF 1010
02BF 1014
02BF 1018
02BF 101C
02BF 1020
02BF 1024
02BF 1028
02BF 102C
02BF 1030
02BF 1034
EE_LINK2_IMS_B_EV0
EE_LINK2_IMS_A_EV1
EE Link 2 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 2 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE_LINK2_IMS_B_EV1
EE Link 2 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE_LINK2_MSK_SET_A_EV0
EE_LINK2_MSK_SET_B_EV0
EE_LINK2_MSK_SET_A_EV1
EE_LINK2_MSK_SET_B_EV1
EE_LINK2_MSK_CLR_A_EV0
EE_LINK2_MSK_CLR_B_EV0
EE_LINK2_MSK_CLR_A_EV1
EE_LINK2_MSK_CLR_B_EV1
EE Link 2 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 2 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 2 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 2 AI_EVENT[1] Interrupt Source Mask Set
Register B
EE Link 2 AI_EVENT[0] Interrupt Source Mask Clear
Register A
EE Link 2 AI_EVENT[0] Interrupt Source Mask Clear
Register B
EE Link 2 AI_EVENT[1] Interrupt Source Mask Clear
Register A
EE Link 2 AI_EVENT[1] Interrupt Source Mask Clear
Register B
02BF 1038 - 02BF 17FC
02BF 1800
-
Reserved
EE_LINK3_IRS_A
EE_LINK3_IRS_B
EE_LINK3_IMS_A_EV0
EE Link 3 Interrupt Source Raw Status Register A
EE Link 3 Interrupt Source Raw Status Register B
02BF 1804
02BF 1808
EE Link 3 AI_EVENT[0] Interrupt Source Masked Status
Register A
02BF 180C
02BF 1810
02BF 1814
02BF 1818
02BF 181C
02BF 1820
02BF 1824
EE_LINK3_IMS_B_EV0
EE_LINK3_IMS_A_EV1
EE Link 3 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 3 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE_LINK3_IMS_B_EV1
EE Link 3 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE_LINK3_MSK_SET_A_EV0
EE_LINK3_MSK_SET_B_EV0
EE_LINK3_MSK_SET_A_EV1
EE_LINK3_MSK_SET_B_EV1
EE Link 3 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 3 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 3 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 3 AI_EVENT[1] Interrupt Source Mask Set
Register B
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Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02BF 1828
EE_LINK3_MSK_CLR_A_EV0
EE Link 3 AI_EVENT[0] Interrupt Source Mask Clear
Register A
02BF 182C
02BF 1830
02BF 1834
EE_LINK3_MSK_CLR_B_EV0
EE_LINK3_MSK_CLR_A_EV1
EE_LINK3_MSK_CLR_B_EV1
EE Link 3 AI_EVENT[0] Interrupt Source Mask Clear
Register B
EE Link 3 AI_EVENT[1] Interrupt Source Mask Clear
Register A
EE Link 3 AI_EVENT[1] Interrupt Source Mask Clear
Register B
02BF 1838 - 02BF 1FFC
02BF 2000
-
Reserved
EE_LINK4_IRS_A
EE_LINK4_IRS_B
EE_LINK4_IMS_A_EV0
EE Link 4 Interrupt Source Raw Status Register A
EE Link 4 Interrupt Source Raw Status Register B
02BF 2004
02BF 2008
EE Link 4 AI_EVENT[0] Interrupt Source Masked Status
Register A
02BF 200C
02BF 2010
02BF 2014
02BF 2018
02BF 201C
02BF 2020
02BF 2024
02BF 2028
02BF 202C
02BF 2030
02BF 2034
EE_LINK4_IMS_B_EV0
EE_LINK4_IMS_A_EV1
EE Link 4 AI_EVENT[0] Interrupt Source Masked Status
Register B
EE Link 4 AI_EVENT[1] Interrupt Source Masked Status
Register A
EE_LINK4_IMS_B_EV1
EE Link 4 AI_EVENT[1] Interrupt Source Masked Status
Register B
EE_LINK4_MSK_SET_A_EV0
EE_LINK4_MSK_SET_B_EV0
EE_LINK4_MSK_SET_A_EV1
EE_LINK4_MSK_SET_B_EV1
EE_LINK4_MSK_CLR_A_EV0
EE_LINK4_MSK_CLR_B_EV0
EE_LINK4_MSK_CLR_A_EV1
EE_LINK4_MSK_CLR_B_EV1
EE Link 4 AI_EVENT[0] Interrupt Source Mask Set
Register A
EE Link 4 AI_EVENT[0] Interrupt Source Mask Set
Register B
EE Link 4 AI_EVENT[1] Interrupt Source Mask Set
Register A
EE Link 4 AI_EVENT[1] Interrupt Source Mask Set
Register B
EE Link 4 AI_EVENT[0] Interrupt Source Mask Clear
Register A
EE Link 4 AI_EVENT[0] Interrupt Source Mask Clear
Register B
EE Link 4 AI_EVENT[1] Interrupt Source Mask Clear
Register A
EE Link 4 AI_EVENT[1] Interrupt Source Mask Clear
Register B
02BF 2038 - 02BF 27FC
02BF 2800 - 02BF 2FFC
02BF 3000
-
Reserved
-
Reserved
EE_CFG
Exception Event Configuration Register
Exception Event AI_EVENT[2] Link Select Register A
Exception Event AI_EVENT[2] Link Select Register B
Exception Event AI_EVENT[3] Link Select Register A
Exception Event AI_EVENT[3] Link Select Register B
Exception Event End of Interrupt Register
Reserved
02BF 3004
EE_LINK_SEL_EV2A
EE_LINK_SEL_EV2B
EE_LINK_SEL_EV3A
EE_LINK_SEL_EV3B
EE_INT_END
-
02BF 3008
02BF 300C
02BF 3010
02BF 3014
02BF 3018 - 02BF 307C
02BF 3080
EE_AI_RUN
-
Event Enable AI Running Register
Reserved
02BF 3084 - 02BF 30FC
02BF 3100
EE_COMMON_IRS
Event Enable Common Interrupt Source Raw Status
Register
02BF 3104
02BF 3108
02BF 310C
EE_COMMON_IMS_EV0
EE_COMMON_IMS_EV1
EE_EV2_LINK_IMS_A
Event Enable Common Interrupt Event 0 Masked Status
Register
Event Enable Common Interrupt Event 1 Masked Status
Register
Event Enable Event 2 Interrupt Source Masked Status
Register A
202
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SPRS552H–OCTOBER 2008–REVISED APRIL 2011
Table 7-89. Antenna Interface System Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
02BF 3110
EE_EV2_LINK_IMS_B
Event Enable Event 2 Interrupt Source Masked Status
Register B
02BF 3114
02BF 3118
02BF 311C
02BF 3120
EE_COMMON_IMS_EV2
EE_EV3_LINK_IMS_A
EE_EV3_LINK_IMS_B
EE_COMMON_IMS_EV3
Event Enable Common Interrupt Event 2 Masked Status
Register
Event Enable Event 3 Interrupt Source Masked Status
Register A
Event Enable Event 3 Interrupt Source Masked Status
Register B
Event Enable Common Interrupt Event 3 Masked Status
Register
02BF 3124
02BF 3128
02BF 312C
02BF 3130
02BF 3134
02BF 3138
02BF 313C
02BF 3140
02BF 3144
02BF 3148
02BF 314C
02BF 3150
02BF 3154
02BF 3158
02BF 315C
02BF 3160
EE_COMMON_MSK_SET_EV0
EE_COMMON_MSK_SET_EV1
EE_EV2_LINK_MSK_SET_A
EE_EV2_LINK_MSK_SET_B
EE_COMMON_MSK_SET_EV2
EE_EV3_LINK_MSK_SET_A
EE_EV3_LINK_MSK_SET_B
EE_COMMON_MSK_SET_EV3
EE_COMMON_MSK_CLR_EV0
EE_COMMON_MSK_CLR_EV1
EE_EV2_LINK_MSK_CLR_A
EE_EV2_LINK_MSK_CLR_B
EE_COMMON_MSK_CLR_EV2
EE_EV3_LINK_MSK_CLR_A
EE_EV3_LINK_MSK_CLR_B
EE_COMMON_MSK_CLR_EV3
-
Event Enable 0 Common Interrupt Mask Set Register
Event Enable 1 Common Interrupt Mask Set Register
Event 2 Link Interrupt Source Mask Set Register A
Event 2 Link Interrupt Source Mask Set Register B
Event Enable 2 Common Interrupt Mask Set Register
Event 3 Link Interrupt Source Mask Set Register A
Event 3 Link Interrupt Source Mask Set Register B
Event Enable 3 Common Interrupt Mask Set Register
Event Enable 0 Common Interrupt Mask Clear Register
Event Enable 1 Common Interrupt Mask Clear Register
Event 2 Link Interrupt Mask Clear Register A
Event 2 Link Interrupt Mask Clear Register B
Event Enable 2 Common Interrupt Mask Clear Register
Event 3 Link Interrupt Mask Clear Register A
Event 3 Link Interrupt Mask Clear Register B
Event Enable 3 Common Interrupt Mask Clear Register
Reserved
02BF 3164 - 02BF 31FC
02BF 3200
EE_INT_VECT_EV0
Event Enable Interrupt Vector Register for AI_EVENT0
Event Enable Interrupt Vector Register for AI_EVENT1
Event Enable Interrupt Vector Register for AI_EVENT2
Event Enable Interrupt Vector Register for AI_EVENT3
Reserved
02BF 3204
EE_INT_VECT_EV1
02BF 3208
EE_INT_VECT_EV2
02BF 320C
EE_INT_VECT_EV3
02BF 3210 - 02BF BFFC
02BF C000
-
VD_RD_BUSERR
VBUSP DMA Read Bus Interface Status Registers
VBUSP DMA Write Bus Interface Status Registers
02BF C004
VD_WR_BUSERR
7.22.2 Antenna Electrical Data/Timing
The TMS320C6474 Hardware Design Guide application report (literature number SPRAAW7) specifies a
complete AIF interface solution for the C6474 device as well as a list of compatible AIF devices. TI has
performed the simulation and system characterization to ensure all AIF interface timings in this solution
are met; therefore, no electrical data/timing information is supplied here for this interface.
TI only supports designs that follow the board design guidelines outlined in the SPRAAW7
application report.
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7.23 Frame Synchronization
Frame synchronization handles timing and time alignment on the device by coordinating timing between
the DSP cores. Up to 30 programmable events based on RP3 or system timer. One output is used for
exporting frame alignment to aid in synchronizing external components.
Frame synchronization assists with synchronization of clock inputs:
•
•
•
OBSAI RP1 compliant input for frame burst data.
UMTS frame synchronization boundary used as an alternative to RP1 for frame burst data.
System timer synchronization used as an alternative to RP1.
The user may select between the OBSAI RP1-compliant FSYNCCLK(P|N) and FRAMEBURST(P|N)
signals or the alternate, single-ended ALTFSYNCCLK and ALTFSYNCPULSE inputs to drive the timers.
Table 7-90. FSYNC Event Connections
C64x+
MEGAMODULE
CORE 0
C64x+
MEGAMODULE
CORE 1
C64x+
MEGAMODULE
CORE 2
MODULE EVENTS
CIC0
CIC1
CIC2
TPCC
CIC3
TIMER
AIF
FSEVT0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FSEVT1
X
FSEVT2
X
X
FSEVT3
FSEVT4
X
X
X
X
X
X
X
X
X
X
FSEVT5
FSEVT6
FSEVT7
FSEVT8
FSEVT9
FSEVT10
FSEVT11
FSEVT12
FSEVT13
FSEVT14
FSEVT15
FSEVT16
FSEVT17
FSEVT18
FSEVT19
FSEVT20
FSEVT21
FSEVT22
FSEVT23
FSEVT24
FSEVT25
FSEVT26
FSEVT27
FSEVT28
FSEVT29
FS_ERR_Alarm0
FS_ERR_Alarm1
FS_AIFFrameSync
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
204
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7.23.1 Frame Synchronization (FSYNC) Register Description(s)
Table 7-91. Frame Synchronization (FSYNC) Registers
HEX ADDRESS
0280 0000
0280 00A0
0280 00A4
0280 00A8
0280 00AC
0280 00B0
0280 00B4
0280 00B8
0280 00BC
0280 00C0
0280 00C4
0280 00C8
0280 00CC
0280 00D0
0280 0080
0280 0084
0280 0088
0280 008C
0280 0090
0280 0094
0280 0098
0280 009C
0280 0100
0280 0128
0280 012C
0280 0130
0280 0134
0280 0138
0280 013C
0280 0140
0280 0168
0280 016C
0280 0170
0280 0174
0280 0178
0280 017C
0280 0200
0280 0258
0280 0280
0280 0300
0280 0358
0280 0380
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
FSYNC ERR INT MASK 1 Register
FSYNC ERR INT SET Register
ERR_INT_MASK_1
ERR_INT_SET
ERR_INT_CLEAR
ERR_END_OF_INT
SCRATCH
FSYNC ERR INT CLEAR Register
FSYNC ERR END 0F INT Register
FSYNC Scratch Register
CTL1
FSYNC Control Register 1
CTL2
FSYNC Control Register 2
EMUCTL
FSYNC Emulation Control Register
FSYNC Emulation Mask Register
FSYNC RP1 Type Select Register
FSYNC Update Register
EMUMASK
RP1TS
UPDATE
RP3INIT
FSYNC RP3 Init Register
SYSINIT
FSYNC System Init Register
ERR_INT_SRC_RAW
ERR_MASK_STAT_0
ERR_MASK_STAT_1
ERR_SET_MASK_0
ERR_SET_MASK_1
ERR_CLEAR_MASK_0
ERR_CLEAR_MASK_1
ERR_INT_MASK_0
RP3TC
FSYNC ERR INT SRC RAW Register
FSYNC ERR MASK STATUS 0 Register
FSYNC ERR MASK STATUS 1 Register
FSYNC ERR SET MASK 0 Register
FSYNC ERR SET MASK 1 Register
FSYNC ERR CLEAR MASK 0 Register
FSYNC ERR CLEAR MASK 1 Register
FSYNC ERR INT MASK 0 Register
FSYNC RP3 Terminal Count Entry
FSYNC TOD Capture Register 1
FSYNC TOD Capture Register 2
FSYNC RP3 Capture Register 1
FSYNC RP3 Capture Register 2
FSYNC SYS Capture Register 1
FSYNC SYS Capture Register 2
FSYNC System Terminal Count Entry
FSYNC System Terminal Count Register
FSYNC RP3 Terminal Count Register
FSYNC Type Capture Register
TOD1
FSYNC_TOD2
RP31
RP32
SYS1
SYS2
SYSTC_RAM
SYSTC
RP3TC
TYPE
TODVAL
FSYNC TOD VAL Register
RP3VAL
FSYNC RP3 VAL Register
SYSVAL
FSYNC System VAL Register
EGMCTRL
FSYNC Mask Event Generator Control Register
FSYNC Counter Event Generator Control Register
FSYNC Mask Event Generator Mask
FSYNC Mask Event Generator Offset Value
FSYNC Counter Event Generator Control Register
FSYNC Event Force Register
EGCCTRL
EGMMASK
EGMOFFSET
EGMCTCOUNT
EVTFORCE
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7.23.2 FSYNC Electrical Data/Timing
Table 7-92. Timing Requirements for FSYNC
(see Figure 7-48, Figure 7-49, and Figure 7-50)
NO.
1
PARAMETER
MIN
MAX UNIT
tc(FSCLK)
tc(FSCLK)
tu(FSPLS)
th(FSPLS)
tj(FSCLK)
Cycle time
8.1388
ns
2
Pulse duration, ALTSYNCCLK high or low
Setup time, ALTFSYNCPULSE high before ALTFSYNCCLK high
Hold time, ALTFSYNCPULSE low after ALTFSYNCCLK high
Period Jitter (peak-to-peak) FSYNCCLK(N|P)
0.4 tc(FSCLK)
0.6 tc(FSCLK)
ns
ns
ns
ns
3
2
2
4
5
0.025 x tc
1
2
2
FSYNCCLK(N|P)
FRAMEBURST
3
4
Figure 7-48. FSYNC Clock and Synchronization Timing
1
2
2
ALTFSYNCCLK
ALTFSYNCPULSE
3
4
Figure 7-49. Alternate FSYNC Clock and Synchronization Timing
1
2
2
TRTCLK
TRT
3
4
Figure 7-50. TRT Clock and Synchronization Timing
206
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TMS320C6474
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Table 7-93. Switching Characteristics Over Recommended Operating Conditions for SMFRAMECLK(1)
(see Figure 7-51)
NO.
PARAMETER
MIN
MAX UNIT
2
tc(FSCLK)
Pulse duration, SMFRAMECLK high or low
4C
ns
(1) C = FSCLK.
2
2
SMFRAMECLK
Figure 7-51. SMFRAMECLK Timing
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8 Mechanical Data
8.1 Thermal Data
Table 8-1 shows the thermal resistance characteristics for the PBGA—CUN/GUN/ZUN—mechanical
package.
Table 8-1. Thermal Resistance Characteristics (PBGA Package) [CUN/GUN/ZUN](1)
AIR FLOW
NO.
PARAMETER
°C/W
(m/s)(2)
N/A
1
2
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0.30
6.5
N/A
(1) A heatsink is required for proper device operation.
(2) m/s = meters per second
8.2 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
208
Mechanical Data
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2012
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Samples
Drawing
(1)
(2)
(3)
(Requires Login)
TMS320C6474FGUN
TMS320C6474FGUN2
TMS320C6474FGUNA
TMS320C6474FZUN
TMS320C6474FZUN2
ACTIVE
ACTIVE
ACTIVE
NRND
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
GUN
GUN
GUN
ZUN
ZUN
561
561
561
561
561
60
60
60
60
60
TBD
TBD
TBD
TBD
SNPB
SNPB
Level-4-220C-72 HR
Level-4-220C-72 HR
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NRND
Pb-Free (RoHS
Exempt)
SNAGCU
Level-4-245C-72HR
TMS320C6474FZUN8
TMS320C6474FZUNA
TMS320C6474FZUNA2
NRND
NRND
NRND
FCBGA
FCBGA
FCBGA
ZUN
ZUN
ZUN
561
561
561
60
1
Pb-Free (RoHS
Exempt)
SNAGCU
SNAGCU
SNAGCU
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Pb-Free (RoHS
Exempt)
60
Pb-Free (RoHS
Exempt)
TMS320C6474GUN
TMS320C6474ZUN
TMX320C6474GUN
OBSOLETE
OBSOLETE
OBSOLETE
FCBGA
FCBGA
FCBGA
GUN
ZUN
GUN
561
561
561
TBD
TBD
TBD
Call TI
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Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2012
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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