TMS320C6678XCYPA [TI]
Multicore Fixed and Floating-Point Digital Signal Processor; 多核固定和浮点数字信号处理器
| 型号： | TMS320C6678XCYPA |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Multicore Fixed and Floating-Point Digital Signal Processor |
| 文件： | 总242页 (文件大小：2088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS691D
April 2013
TMS320C6678
Data Manual
SPRS691D—April 2013
www.ti.com
Release History
Revision Date
Description/Comments
SPRS691D April 2013
• Added Initial Startup row for CVDD in Recommended Operating Conditions table
• Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table
• Added CVDD and SmartReflex voltage parameter in SmartReflex switching table
• Added HOUT timing diagram in Host Interrupt Output section
• Added MPU Registers Reset Values section
• Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns
• Corrected Reserved to be Assert local reset to all CorePacs in LRESET and NMI decoding table
• Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet.
• Updated the Timer numbering across the whole document
• Updated DDR3 PLL initialization sequence
SPRS691C February 2012 • Added TeraNet connection figures and added bridge numbers to the connection tables
• Changed TPCC to EDMA3CC and TPTC to EDMA3TC
• Changed chip level interrupt controller name from INTC to CIC
• Added the DDR3 PLL and PASS PLL Initialization Sequence
• Added DEVSPEED Register section
• Updated device frequency in the feature section
• Corrected the SPI, DDR3, and Hyperbridge config/data memory map addresses
• Restricted Output Divide of SECCTL Register to max value of divide by 2
SPRS691B August 2011
• Updated the timing and electrical sections of several peripherals
• Updated the core-specific and general-purpose timer numbers
• Updated the connection matrix tables in chapter 4 “System Interconnection”
• Updated device boot configuration tables and figures
• Updated DDR3 and PASS PLL timing figures
• Removed section 7.1 “Parameter Information”
SPRS691A July 2011
• Added sections: NMI and LRSET
• Added Pin Map diagrams
• Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers
• Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL
• Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns
• Corrected items in the Memory Map Summary table
• Changed all occurrences of PA_SS to Network Coprocessor
• Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR
SPRS691
November
2010
Initial release
For detailed revision information, see ‘‘Revision History’’ on page A-233.
2
Release History
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Contents
1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
1.1 KeyStone Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 DSP Core Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.5 Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.5.3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.5.4 PLL Boot Configuration Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.7.1 Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.7.2 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
2.9 Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
2.10 Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
3.3.2 Device Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3.3.5 DSP Boot Address (DSP_BOOT_ADDRn) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3.3.6 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
3.3.7 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
3.3.8 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
3.3.9 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
3.3.10 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
3.3.11 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
3.3.12 NMI Event Generation to CorePac (NMIGRx) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
3.3.13 IPC Generation (IPCGRx) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
3.3.14 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
3.3.15 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
3.3.16 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.3.17 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
3.3.18 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
3.3.19 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3.3.20 Device Speed (DEVSPEED) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
4.1 Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
4.2 Switch Fabric Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
4.3 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Copyright 2013 Texas Instruments Incorporated
Contents
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.1.4 MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
5.2 Memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.5 C66x CorePac Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.6 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.4 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.1 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.2 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.2.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.2.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.2.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.2.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
7.3 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.3.1 Power Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.3.2 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.3.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
7.4 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.4.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
7.4.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.4.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.4.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.4.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.4.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.4.7 Reset Electrical Data / Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.5 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
7.5.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.5.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.5.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
7.5.4 Main PLL and PLL Controller Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.5.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.6 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.6.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.6.2 DDR3 PLL Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.6.3 DDR3 PLL Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.6.4 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.7 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.7.1 PASS PLL Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.7.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.7.3 PASS PLL Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.7.4 PASS PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
7.8.2 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.8.3 EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.8.4 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.9.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.9.2 CIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.9.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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Contents
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.9.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.9.5 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.9.6 Host Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
7.10 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
7.10.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
7.10.2 MPU Programmable Range Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
7.11 DDR3 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.11.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.11.2 DDR3 Memory Controller Race Condition Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
7.11.3 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.12 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.12.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.12.2 I2C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.12.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.13 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.13.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.14 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.14.1 HyperLink Device-Specific Interrupt Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.14.2 HyperLink Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.15 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.16 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7.17 TSIP Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.17.1 TSIP Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.18 EMIF16 Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.18.1 EMIF16 Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.19 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7.20 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
7.21 Gigabit Ethernet (GbE) Switch Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
7.22 Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.23 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.23.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
7.23.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.24 Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.25 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.25.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.25.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.26 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.27 Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.27.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.27.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.27.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
B.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
B.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
A
B
Copyright 2013 Texas Instruments Incorporated
Contents
5
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
List of Figures
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-7
Figure 2-8
Figure 2-9
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
DSP Core Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
No Boot/ EMIF16 Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Serial Rapid I/O Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Ethernet (SGMII) Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PCI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
I2C Master Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I2C Passive Mode Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPI Device Configuration Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 2-10 HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 2-11 CYP 841-Pin BGA Package (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 2-12 Pin Map Quadrants (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 2-13 Upper Left Quadrant—A (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 2-14 Upper Right Quadrant—B (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 2-15 Lower Right Quadrant—C (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 2-16 Lower Left Quadrant—D (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 2-17 C66x DSP Device Nomenclature (including the TMS320C6678). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 3-1
Figure 3-2
Figure 3-3
Figure 3-4
Figure 3-5
Figure 3-6
Figure 3-7
Figure 3-8
Figure 3-9
Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
DSP BOOT Address Register (DSP_BOOT_ADDRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 3-10 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 3-11 NMI Generation Register (NMIGRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Figure 3-12 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 3-13 IPC Acknowledgement Registers (IPCARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 3-14 IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Figure 3-15 IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 3-16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 3-17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Figure 3-18 Reset Mux Register RSTMUXx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Figure 3-19 Device Speed Register (DEVSPEED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
TeraNet 2A for C6678. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
TeraNet 3A for C6678. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
TeraNet 3P_A & B for C6678. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
TeraNet 6P_B and 3P_Tracer for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
CorePac Revision ID Register (MM_REVID) Address - 0181 2000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
RESETFULL Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
6
List of Figures
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-5
Soft/Hard-Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Figure 7-11 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Figure 7-12 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Figure 7-13 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Figure 7-14 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Figure 7-15 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Figure 7-16 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Figure 7-17 Main PLL Control Register 0 (MAINPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Figure 7-18 Main PLL Control Register 1 (MAINPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Figure 7-19 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 7-20 Main PLL Clock Input Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 7-21 DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Figure 7-22 DDR3 PLL Control Register 0 (DDR3PLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Figure 7-23 DDR3 PLL Control Register 1 (DDR3PLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Figure 7-24 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Figure 7-25 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Figure 7-26 PASS PLL Control Register 0 (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Figure 7-27 PASS PLL Control Register 1 (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Figure 7-28 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
Figure 7-29 TMS320C6678 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164
Figure 7-30 NMI and Local Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Figure 7-31 HOUT Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
Figure 7-32 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Figure 7-33 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
Figure 7-34 Programmable Range n End Address Register (PROGn_MPEAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
Figure 7-35 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
Figure 7-36 I2C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Figure 7-37 I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Figure 7-38 I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Figure 7-39 SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Figure 7-40 SPI Additional Timings for 4 Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Figure 7-41 HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
Figure 7-42 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
Figure 7-43 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
Figure 7-44 UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
Figure 7-45 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
Figure 7-46 UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Figure 7-47 UART RTS (Request-to-Send Output) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Figure 7-48 TSIP 2x Timing Diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Figure 7-49 TSIP 1x Timing Diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Figure 7-50 EMIF16 Asynchronous Memory Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Figure 7-51 EMIF16 Asynchronous Memory Write Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
Figure 7-52 EMIF16 EM_WAIT Read Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Figure 7-53 EMIF16 EM_WAIT Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Figure 7-54 MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Figure 7-55 MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
Figure 7-56 CPTS_RFTCLK_SEL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
Figure 7-57 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Figure 7-58 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Copyright 2013 Texas Instruments Incorporated
List of Figures
7
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-59 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
Figure 7-60 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
Figure 7-61 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
Figure 7-62 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
8
List of Figures
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
List of Tables
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 2-21
Table 2-22
Table 2-23
Table 2-24
Table 2-25
Table 2-26
Table 2-27
Table 2-28
Table 2-29
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table 3-10
Table 3-11
Table 3-12
Table 3-13
Table 3-14
Table 3-15
Table 3-16
Table 3-17
Table 3-18
Table 3-19
Table 3-20
Table 3-21
Table 4-1
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Bootloader section in L2 SRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Extended Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
No Boot / EMIF16 Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Serial Rapid I/O Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Ethernet (SGMII) Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
PCI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I2C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
I2C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Boot Parameter Table Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
EMIF16 Boot Mode Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
SRIO Boot Mode Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Ethernet Boot Mode Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
PCIe Boot Mode Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I2C Boot Mode Parameter Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SPI Boot Mode Parameter Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
HyperLink Boot Mode Parameter Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DDR3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
C66x DSP System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Terminal Functions — Signals and Control by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Terminal Functions — Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Terminal Functions — By Ball Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
TMS320C6678 Device Configuration Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
DSP BOOT Address Register (DSP_BOOT_ADDRn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Reset Status Register (RESET_STAT) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Boot Complete Register (BOOTCOMPLETE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Power State Control Register (PWRSTATECTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
NMI Generation Register (NMIGRx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
IPC Generation Registers (IPCGRx) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
IPC Acknowledgement Registers (IPCARx) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
IPC Generation Registers (IPCGRH) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
IPC Acknowledgement Register (IPCARH) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Timer Input Selection Field Description (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Timer Output Selection Field Description (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Device Speed Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Switch Fabric Connection Matrix Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Copyright 2013 Texas Instruments Incorporated
List of Tables
9
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 4-2
Table 4-3
Table 4-4
Table 5-1
Table 5-2
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
Table 7-22
Table 7-23
Table 7-24
Table 7-25
Table 7-26
Table 7-27
Table 7-28
Table 7-29
Table 7-30
Table 7-31
Table 7-32
Table 7-33
Table 7-34
Table 7-35
Table 7-36
Table 7-37
Table 7-38
Table 7-39
Table 7-40
Table 7-41
Table 7-42
Table 7-43
Table 7-44
Table 7-45
Switch Fabric Connection Matrix Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Switch Fabric Connection Matrix Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Power Supply Rails on TMS320C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
PSC Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Reset Switching Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
PLL Secondary Control Register (SECCTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
PLL Controller Divider Register (PLLDIVn) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
SYSCLK Status Register (SYSTAT) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Reset Type Status Register (RSTYPE) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
Reset Control Register (RSTCTRL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Reset Configuration Register (RSTCFG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Reset Isolation Register (RSISO) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
DDR3 PLL Control Register 0 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
DDR3 PLL Control Register 1 Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
PASS PLL Control Register 0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
PASS PLL Control Register 1 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
PASS PLL Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
EDMA3 Transfer Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
EDMA3CC0 Events for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
EDMA3CC1 Events for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
EDMA3CC2 Events for C6678 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
CIC1 Event Inputs (Secondary Interrupts for C66x CorePacs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
CIC0/CIC1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
CIC2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
CIC3 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
10
List of Tables
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-46
IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
LRESET and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
NMI and Local Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
HOUT Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
Configuration Register (CONFIG) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions . . . . . . . . . . . .199
Programmable Range n Registers Reset Values for MPU0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Programmable Range n Registers Reset Values for MPU1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Programmable Range n Registers Reset Values for MPU2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Programmable Range n Registers Reset Values for MPU3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
I2C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
I2C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
HyperLink Events for C6678. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216
UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
Timing Requirements for TSIP 2x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Timing Requirements for TSIP 1x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
EMIF16 Asynchronous Memory Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
CPTS_RFTCLK_SEL Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
MDIO Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
DSP Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
STM Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
Thermal Resistance Characteristics (PBGA Package) [CYP]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Table 7-47
Table 7-48
Table 7-49
Table 7-50
Table 7-51
Table 7-52
Table 7-53
Table 7-54
Table 7-55
Table 7-56
Table 7-57
Table 7-58
Table 7-59
Table 7-60
Table 7-61
Table 7-62
Table 7-63
Table 7-64
Table 7-65
Table 7-66
Table 7-67
Table 7-68
Table 7-69
Table 7-70
Table 7-71
Table 7-72
Table 7-73
Table 7-74
Table 7-75
Table 7-76
Table 7-77
Table 7-78
Table 7-79
Table 7-80
Table 7-81
Table 7-82
Table 7-83
Table 7-84
Table 7-85
Table 7-86
Table 7-87
Table 7-88
Table 7-89
Table 7-90
Table 7-91
Table 2-1
Copyright 2013 Texas Instruments Incorporated
List of Tables 11
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
12
List of Tables
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
1 Features
•
Eight TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each with
•
Peripherals
– Four Lanes of SRIO 2.1
– 1.0 GHz or 1.25 GHz C66x Fixed/Floating-Point
›
1.24/2.5/3.125/5 GBaud Operation Supported
Per Lane
CPU Core
›
›
40 GMAC/Core for Fixed Point @ 1.25 GHz
20 GFLOP/Core for Floating Point @ 1.25 GHz
›
›
Supports Direct I/O, Message Passing
Supports Four 1×, Two 2×, One 4×, and Two 1× +
One 2× Link Configurations
– Memory
›
›
›
32K Byte L1P Per Core
32K Byte L1D Per Core
512K Byte Local L2 Per Core
•
Multicore Shared Memory Controller (MSMC)
– 4096KB MSM SRAM Memory Shared by Eight DSP
C66x CorePacs
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
•
•
Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
– 16-Bit EMIF
– Two Telecom Serial Ports (TSIP)
Network Coprocessor
– Packet Accelerator Enables Support for
›
›
Supports 1024 DS0s Per TSIP
Supports 2/4/8 Lanes at 32.768/16.384/8.192
Mbps Per Lane
›
›
›
Transport Plane IPsec, GTP-U, SCTP, PDCP
L2 User Plane PDCP (RoHC, Air Ciphering)
1-Gbps Wire-Speed Throughput at 1.5 MPackets
Per Second
– UART Interface
– I2C Interface
– 16 GPIO Pins
– Security Accelerator Engine Enables Support for
›
IPSec, SRTP, 3GPP, WiMAX Air Interface, and
SSL/TLS Security
– SPI Interface
›
ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
– Semaphore Module
– Sixteen 64-Bit Timers
– Three On-Chip PLLs
›
Up to 2.8 Gbps Encryption Speed
•
•
Commercial Temperature:
– 0°C to 85°C
Extended Temperature:
– - 40°C to 100°C
Copyright 2013 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
1.1 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores
with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.2 Device Description
The TMS320C6678 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore
architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to
1.25 GHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and
automation, and other applications requiring high performance, TI's TMS320C6678 DSP offers 10 GHz cumulative
DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with
all existing C6000 family of fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory
subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize
intra-device and inter-device communication that allows the various DSP resources to operate efficiently and
seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data
management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and
contention-free internal data movement. The multicore shared memory controller allows access to shared and
external memory directly without drawing from switch fabric capacity.
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition,
the C66x core integrates floating point capability and the per core raw computational performance is an
industry-leading 40 GMACS/core and 20GFLOPS/core (@1.25 GHz operating frequency). It can execute 8 single
precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is
IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for
floating point and vector math oriented processing. These enhancements yield sizeable performance improvements
in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is
backwards code compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring
software portability and shortened software development cycles for applications migrating to faster hardware.
The C6678 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache,
there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also
integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All
L2 memories incorporate error detection and error correction. For fast access to external memory, this device
includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.
14
Features
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and
Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I2C, UART, Telecom Serial Interface Port
(TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication
between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding
to the network awareness of this device is a network co-processor that includes both packet and optional security
acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for
the entire multicore C6678 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities.
The C6678 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source
code execution.
Copyright 2013 Texas Instruments Incorporated
Features 15
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the TMS320C6678 device.
Figure 1-1
Functional Block Diagram
Memory Subsystem
4MB
MSM
SRAM
64-Bit
DDR3 EMIF
MSMC
Debug & Trace
Boot ROM
Semaphore
C66x
CorePac
Power
Management
PLL
32KB L1
P-Cache
32KB L1
D-Cache
´ 3
´ 3
512KB L2 Cache
EDMA
8 Cores @ up to 1.25 GHz
HyperLink
TeraNet
Multicore Navigator
Queue
Manager
Packet
DMA
Security
Accelerator
Packet
Accelerator
Network Coprocessor
16
Features
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2 Device Overview
2.1 Device Characteristics
Table 2-1 shows the significant features of the device.
Table 2-1
Device Characteristics
HARDWARE FEATURES
TMS320C6678
DDR3 Memory Controller (64-bit bus width) [1.5 V I/O]
(clock source = DDRREFCLKN|P)
1
EDMA3 (16 independent channels) [DSP/2 clock rate]
1
2
1
1
2
1
1
1
2
1
1
1
EDMA3 (64 independent channels) [DSP/3 clock rate]
High-speed 1×/2x/4× Serial RapidIO Port (4 lanes)
PCIe (2 lanes)
10/100/1000 Ethernet
Management Data Input/Output (MDIO)
HyperLink
Peripherals
EMIF16
TSIP
SPI
UART
I2C
64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency)
Sixteen 64-bit (each configurable as two32-bit
timers)
General-Purpose Input/Output Port (GPIO)
Packet Accelerator
16
1
Accelerators
(1)
Security Accelerator
1
Size (Bytes)
8832KB
256KB L1 Program Memory [SRAM/Cache]
256KB L1 Data Memory [SRAM/Cache]
4096KB L2 Unified Memory/Cache
4096KB MSM SRAM
On-Chip Memory
Organization
128KB L3 ROM
C66x CorePac
Revision ID
See Section 5.5 ‘‘C66x CorePac Revision’’ on
page 115.
CorePac Revision ID Register (address location: 0181 2000h)
JTAGID register (address location: 0262 0018h)
See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register
Description’’ on page 80
JTAG BSDL_ID
Frequency
1250 (1.25 GHz)
MHz
ns
1000 (1.0 GHz)
0.8 ns (1.25 GHz)
1 ns (1.0 GHz)
Cycle Time
Voltage
Core (V)
SmartReflex variable supply
1.0 V, 1.5 V, and 1.8 V
0.040 m
I/O (V)
Process Technology
BGA Package
Product Status (2)
m
24 mm × 24 mm
841-Pin Flip-Chip Plastic BGA (CYP)
PD
Product Preview (PP), Advance Information (AI), or Production Data (PD)
End of Table 2-1
1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
2
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright 2013 Texas Instruments Incorporated
Device Overview 17
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.2 DSP Core Description
The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through
enhancements and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data.
On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions.
C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to
perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also
supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process
multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g
execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP
programmers through the use of TI's optimized C/C++ compiler.
The C66x DSP consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The
two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The
general-purpose registers can be used for data or can be data address pointers. The data types supported include
packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data.
40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and
the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data
values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the
remaining 96 MSBs in the next 3 upper registers.
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.
Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit
multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies
with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field
multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding
capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with
rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions
that multiply a complex number with a complex conjugate of another number with rounding capability.
Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable
of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability.
A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.
Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes
one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a
mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an
operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The
C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing
one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x
.M unit can also perform one the following floating-point operations each clock cycle: one, two, or four
single-precision multiplies or a complex single-precision multiply.
The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic,
logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were
added yielding performance enhancements of the floating point addition and subtraction instructions, including the
ability to perform one double precision addition or subtraction per cycle. Conversion to/from integer and
single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger
18
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
operands, instructions were also added to double the number of these conversions that can be done. The .L unit also
has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of
complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the
conjugate of a complex number.
The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a DSP stall
until the completion of all the DSP-triggered memory transactions, including:
•
•
•
•
•
•
Cache line fills
Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints
Victim write backs
Block or global coherence operations
Cache mode changes
Outstanding XMC prefetch requests
This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides
ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that
depend on ordering, and manual coherence operations.
For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following
documents:
•
C66x CPU and Instruction Set Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on
page 73.
•
•
C66x DSP Cache User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Copyright 2013 Texas Instruments Incorporated
Device Overview 19
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 2-1 shows the DSP core functional units and data paths.
Figure 2-1
DSP Core Data Paths
Note:
src1
Default bus width
is 64 bits
(i.e. a register pair)
.L1
.S1
Register
File A
(A0, A1, A2,
...A31)
src2
dst
ST1
src1
src2
dst
src1
Data Path A
src1_hi
src2
.M1
src2_hi
dst2
dst1
LD1
DA1
32
src1
dst
32
32
.D1
32
src2
32
2
´
´
1
Register
File B
(B0, B1, B2,
...B31)
32
src2
32
32
DA2
LD2
.D2
32
dst
32
src1
32
dst1
dst2
src2_hi
.M2
src2
src1_hi
src1
Data Path B
dst
src2
.S2
src1
ST2
dst
src2
.L2
src1
32
32
Control
Register
20
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.3 Memory Map Summary
Table 2-2 shows the memory map address ranges of the TMS320C6678 device.
Table 2-2
Memory Map Summary (Part 1 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
8M
Description
Reserved
00000000
00800000
00880000
00E00000
00E08000
00F00000
00F08000
01800000
01C00000
01D00000
01D00080
01D08000
01D08080
01D10000
01D10080
01D18000
01D18080
01D20000
01D20080
01D28000
01D28080
01D30000
01D30080
01D38000
01D38080
01D40000
01D40080
01D48000
01D48080
01D50000
01D50080
01D58000
01D58080
01D60000
01D60080
01D68000
01D68080
01D70000
01D70080
01D78000
007FFFFF
0087FFFF
00DFFFFF
00E07FFF
00EFFFFF
00F07FFF
017FFFFF
01BFFFFF
01CFFFFF
01D0007F
01D07FFF
01D0807F
01D0FFFF
01D1007F
01D17FFF
01D1807F
01D1FFFF
01D2007F
01D27FFF
01D2807F
01D2FFFF
01D3007F
01D37FFF
01D3807F
01D3FFFF
01D4007F
01D47FFF
01D4807F
01D4FFFF
01D5007F
01D57FFF
01D5807F
01D5FFFF
01D6007F
01D67FFF
01D6807F
01D6FFFF
01D7007F
01D77FFF
01D7807F
0 00000000
0 00800000
0 00880000
0 00E00000
0 00E08000
0 00F00000
0 00F08000
0 01800000
0 01C00000
0 01D00000
0 01D00080
0 01D08000
0 01D08080
0 01D10000
0 01D10080
0 01D18000
0 01D18080
0 01D20000
0 01D20080
0 01D28000
0 01D28080
0 01D30000
0 01D30080
0 01D38000
0 01D38080
0 01D40000
0 01D40080
0 01D48000
0 01D48080
0 01D50000
0 01D50080
0 01D58000
0 01D58080
0 01D60000
0 01D60080
0 01D68000
0 01D68080
0 01D70000
0 01D70080
0 01D78000
0 007FFFFF
0 0087FFFF
0 00DFFFFF
0 00E07FFF
0 00EFFFFF
0 00F07FFF
0 017FFFFF
0 01BFFFFF
0 01CFFFFF
0 01D0007F
0 01D07FFF
0 01D0807F
0 01D0FFFF
0 01D1007F
0 01D17FFF
0 01D1807F
0 01D1FFFF
0 01D2007F
0 01D27FFF
0 01D2807F
0 01D2FFFF
0 01D3007F
0 01D37FFF
0 01D3807F
0 01D3FFFF
0 01D4007F
0 01D47FFF
0 01D4807F
0 01D4FFFF
0 01D5007F
0 01D57FFF
0 01D5807F
0 01D5FFFF
0 01D6007F
0 01D67FFF
0 01D6807F
0 01D6FFFF
0 01D7007F
0 01D77FFF
0 01D7807F
512K
Local L2 SRAM
Reserved
5M+512K
32K
Local L1P SRAM
Reserved
1M-32K
32K
Local L1D SRAM
Reserved
9M-32K
4M
C66x CorePac Registers
Reserved
1M
128
Tracer_MSMC_0
Reserved
32K-128
128
Tracer_MSMC_1
Reserved
32K-128
128
Tracer_MSMC_2
Reserved
32K-128
128
Tracer_MSMC_3
Reserved
32K-128
128
Tracer_QM_DMA
Reserved
32K-128
128
Tracer_DDR
Reserved
32K-128
128
Tracer_SM
32K-128
128
Reserved
Tracer_QM_CFG
Reserved
32K-128
128
Tracer_CFG
Reserved
32K-128
128
Tracer_L2_0
Reserved
32K-128
128
Tracer_L2_1
Reserved
32K-128
128
Tracer_L2_2
Reserved
32K-128
128
Tracer_L2_3
Reserved
32K-128
128
Tracer_L2_4
Reserved
32K-128
128
Tracer_L2_5
Reserved
32K-128
128
Tracer_L2_6
Copyright 2013 Texas Instruments Incorporated
Device Overview 21
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-2
Memory Map Summary (Part 2 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
32K-128
128
Description
01D78080
01D80000
01D80080
01E00000
01E40000
01E80000
01EC0000
02000000
01D7FFFF
01D8007F
01DFFFFF
01E3FFFF
01E7FFFF
01EBFFFF
01FFFFFF
020FFFFF
0 01D78080
0 01D80000
0 01D80080
0 01E00000
0 01E40000
0 01E80000
0 01EC0000
0 02000000
0 01D7FFFF
0 01D8007F
0 01DFFFFF
0 01E3FFFF
0 01E7FFFF
0 01EBFFFF
0 01FFFFFF
0 020FFFFF
Reserved
Tracer_L2_7
512K-128
256K
Reserved
Telecom Serial Interface Port (TSIP) 0
Reserved
256K
256K
Telecom Serial Interface Port (TSIP) 1
Reserved
1M +256K
1M
Network Coprocessor (Packet Accelerator, Gigabit Ethernet
Switch Subsystem and Security Accelerator)
02100000
02200000
02200080
02210000
02210080
02220000
02220080
02230000
02230080
02240000
02240080
02250000
02250080
02260000
02260080
02270000
02270080
02280000
02280080
02290000
02290080
022A0000
022A0080
022B0000
022B0080
022C0000
022C0080
022D0000
022D0080
022E0000
022E0080
022F0000
022F0080
02300000
021FFFFF
0220007F
0220FFFF
0221007F
0221FFFF
0222007F
0222FFFF
0223007F
0223FFFF
0224007F
0224FFFF
0225007F
0225FFFF
0226007F
0226FFFF
0227007F
0227FFFF
0228007F
0228FFFF
0229007F
0229FFFF
022A007F
022AFFFF
022B007F
022BFFFF
022C007F
022CFFFF
022D007F
022DFFFF
022E007F
022EFFFF
022F007F
022FFFFF
0230FFFF
0 02100000
0 02200000
0 02200080
0 02210000
0 02210080
0 02220000
0 02220080
0 02230000
0 02230080
0 02240000
0 02240080
0 02250000
0 02250080
0 02260000
0 02260080
0 02270000
0 02270080
0 02280000
0 02280080
0 02290000
0 02290080
0 022A0000
0 022A0080
0 022B0000
0 022B0080
0 022C0000
0 022C0080
0 022D0000
0 022D0080
0 022E0000
0 022E0080
0 022F0000
0 022F0080
0 02300000
0 021FFFFF
0 0220007F
0 0220FFFF
0 0221007F
0 0221FFFF
0 0222007F
0 0222FFFF
0 0223007F
0 0223FFFF
0 0224007F
0 0224FFFF
0 0225007F
0 0225FFFF
0 0226007F
0 0226FFFF
0 0227007F
0 0227FFFF
0 0228007F
0 0228FFFF
0 0229007F
0 0229FFFF
0 022A007F
0 022AFFFF
0 022B007F
0 022BFFFF
0 022C007F
0 022CFFFF
0 022D007F
0 022DFFFF
0 022E007F
0 022EFFFF
0 022F007F
0 022FFFFF
0 0230FFFF
1M
Reserved
Timer0
128
64K-128
128
Reserved
Timer1
64K-128
128
Reserved
Timer2
64K-128
128
Reserved
Timer3
64K-128
128
Reserved
Timer4
64K-128
128
Reserved
Timer5
64K-128
128
Reserved
Timer6
64K-128
128
Reserved
Timer7
64K-128
128
Reserved
Timer8
64K-128
128
Reserved
Timer9
64K-128
128
Reserved
Timer10
Reserved
Timer11
Reserved
Timer12
Reserved
Timer13
Reserved
Timer14
Reserved
Timer15
Reserved
Reserved
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
128
64K-128
64K
22
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-2
Memory Map Summary (Part 3 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
512
Description
02310000
02310200
02320000
02320100
02330000
02330400
02350000
02351000
02360000
02360400
02368000
02368400
02370000
02370400
02378000
02378400
02400000
02440000
02444000
02450000
02454000
02460000
02464000
02470000
02474000
02480000
02484000
02490000
02494000
024A0000
024A4000
024B0000
024B4000
024C0000
02530000
02530080
02540000
02540400
02550000
02600000
02602000
02604000
02606000
023101FF
0231FFFF
023200FF
0232FFFF
023303FF
0234FFFF
02350FFF
0235FFFF
023603FF
02367FFF
023683FF
0236FFFF
023703FF
02377FFF
023783FF
023FFFFF
0243FFFF
02443FFF
0244FFFF
02453FFF
0245FFFF
02463FFF
0246FFFF
02473FFF
0247FFFF
02483FFF
0248FFFF
02493FFF
0249FFFF
024A3FFF
024AFFFF
024B3FFF
024BFFFF
0252FFFF
0253007F
0253FFFF
0254003F
0254FFFF
025FFFFF
02601FFF
02603FFF
02605FFF
02607FFF
0 02310000
0 02310200
0 02320000
0 02320100
0 02330000
0 02330400
0 02350000
0 02351000
0 02360000
0 02360400
0 02368000
0 02368400
0 02370000
0 02370400
0 02378000
0 02378400
0 02400000
0 02440000
0 02444000
0 02450000
0 02454000
0 02460000
0 02464000
0 02470000
0 02474000
0 02480000
0 02484000
0 02490000
0 02494000
0 024A0000
0 024A4000
0 024B0000
0 024B4000
0 024C0000
0 02530000
0 02530080
0 02540000
0 02540400
0 02550000
0 02600000
0 02602000
0 02604000
0 02606000
0 023101FF
0 0231FFFF
0 023200FF
0 0232FFFF
0 023303FF
0 0234FFFF
0 02350FFF
0 0235FFFF
0 023603FF
0 02367FFF
0 023683FF
0 0236FFFF
0 023703FF
0 02377FFF
0 023783FF
0 023FFFFF
0 0243FFFF
0 02443FFF
0 0244FFFF
0 02453FFF
0 0245FFFF
0 02463FFF
0 0246FFFF
0 02473FFF
0 0247FFFF
0 02483FFF
0 0248FFFF
0 02493FFF
0 0249FFFF
0 024A3FFF
0 024AFFFF
0 024B3FFF
0 024BFFFF
0 0252FFFF
0 0253007F
0 0253FFFF
0 0254003F
0 0254FFFF
0 025FFFFF
0 02601FFF
0 02603FFF
0 02605FFF
0 02607FFF
PLL Controller
64K-512
256
Reserved
GPIO
64K-256
1K
Reserved
SmartReflex
127K
4K
Reserved
Power Sleep Controller (PSC)
Reserved
64K-4K
1K
Memory Protection Unit (MPU) 0
Reserved
31K
1K
Memory Protection Unit (MPU) 1
Reserved
31K
1K
Memory Protection Unit (MPU) 2
Reserved
31K
1K
Memory Protection Unit (MPU) 3
Reserved
543K
256K
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
16K
48K
448K
128
Debug Subsystem Configuration
DSP trace formatter 0
Reserved
DSP trace formatter 1
Reserved
DSP trace formatter 2
Reserved
DSP trace formatter 3
Reserved
DSP trace formatter 4
Reserved
DSP trace formatter 5
Reserved
DSP trace formatter 6
Reserved
DSP trace formatter 7
Reserved
Reserved
I2C data & control
64K-128
64
Reserved
UART
64K-64
704K
8K
Reserved
Reserved
Chip Interrupt Controller (CIC) 0
Reserved
8K
8K
Chip Interrupt Controller (CIC) 1
Reserved
8K
Copyright 2013 Texas Instruments Incorporated
Device Overview 23
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-2
Memory Map Summary (Part 4 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
8K
Description
02608000
0260A000
0260C000
0260E000
02620000
02620800
02640000
02640800
02650000
02700000
02708000
02720000
02728000
02740000
02748000
02760000
02760400
02768000
02768400
02770000
02770400
02778000
02778400
02780000
02780400
02788000
02788400
02790000
02790400
02798000
02798400
027A0000
027A0400
027A8000
027A8400
027B0000
027D0000
027D1000
027E0000
027E1000
027F0000
027F1000
02800000
02609FFF
0260BFFF
0260DFFF
0261FFFF
026207FF
0263FFFF
026407FF
0264FFFF
026FFFFF
02707FFF
0271FFFF
02727FFF
0273FFFF
02747FFF
0275FFFF
027603FF
02767FFF
027683FF
0276FFFF
027703FF
02777FFF
027783FF
0277FFFF
027803FF
02787FFF
027883FF
0278FFFF
027903FF
02797FFF
027983FF
0279FFFF
027A03FF
027A7FFF
027A83FF
027AFFFF
027CFFFF
027D0FFF
027DFFFF
027E0FFF
027EFFFF
027F0FFF
027FFFFF
02800FFF
0 02608000
0 0260A000
0 0260C000
0 0260E000
0 02620000
0 02620800
0 02640000
0 02640800
0 02650000
0 02700000
0 02708000
0 02720000
0 02728000
0 02740000
0 02748000
0 02760000
0 02760400
0 02768000
0 02768400
0 02770000
0 02770400
0 02778000
0 02778400
0 02780000
0 02780400
0 02788000
0 02788400
0 02790000
0 02790400
0 02798000
0 02798400
0 027A0000
0 027A0400
0 027A8000
0 027A8400
0 027B0000
0 027D0000
0 027D1000
0 027E0000
0 027E1000
0 027F0000
0 027F1000
0 02800000
0 02609FFF
0 0260BFFF
0 0260DFFF
0 0261FFFF
0 026207FF
0 0263FFFF
0 026407FF
0 0264FFFF
0 026FFFFF
0 02707FFF
0 0271FFFF
0 02727FFF
0 0273FFFF
0 02747FFF
0 0275FFFF
0 027603FF
0 02767FFF
0 027683FF
0 0276FFFF
0 027703FF
0 02777FFF
0 027783FF
0 0277FFFF
0 027803FF
0 02787FFF
0 027883FF
0 0278FFFF
0 027903FF
0 02797FFF
0 027983FF
0 0279FFFF
0 027A03FF
0 027A7FFF
0 027A83FF
0 027AFFFF
0 027CFFFF
0 027D0FFF
0 027DFFFF
0 027E0FFF
0 027EFFFF
0 027F0FFF
0 027FFFFF
0 02800FFF
Chip Interrupt Controller (CIC) 2
8K
Reserved
8K
Chip Interrupt Controller (CIC) 3
72K
2K
Reserved
Chip-Level Registers
126K
2K
Reserved
Semaphore
64K-2K
704K
32K
96K
32K
96K
32K
96K
1K
Reserved
Reserved
EDMA3 Channel Controller (EDMA3CC) 0
Reserved
EDMA3 Channel Controller (EDMA3CC) 1
Reserved
EDMA3 Channel Controller (EDMA3CC) 2
Reserved
EDMA3CC0 Transfer Controller (EDMA3TC) 0
31K
1K
Reserved
EDMA3CC0 Transfer Controller (EDMA3TC) 1
31K
1K
Reserved
EDMA3CC1 Transfer Controller (EDMA3TC) 0
31K
1K
Reserved
EDMA3CC1 Transfer Controller (EDMA3TC) 1
31K
1K
Reserved
EDMA3CC1 Transfer Controller (EDMA3TC) 2
31K
1K
Reserved
EDMA3CC1 Transfer Controller (EDMA3TC) 3
31K
1K
Reserved
EDMA3PCC2 Transfer Controller (EDMA3TC) 0
31K
1K
Reserved
EDMA3CC2 Transfer Controller (EDMA3TC) 1
31K
1K
Reserved
EDMA3CC2 Transfer Controller (EDMA3TC) 2
31K
1K
Reserved
EDMA3CC2 Transfer Controller (EDMA3TC) 3
31K
128K
4K
Reserved
Reserved
TI embedded trace buffer (TETB) - CorePac0
Reserved
60K
4K
TI embedded trace buffer (TETB) - CorePac1
Reserved
60K
4K
TI embedded trace buffer (TETB) - CorePac2
Reserved
60K
4K
TI embedded trace buffer (TETB) - CorePac3
24
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-2
Memory Map Summary (Part 5 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
60K
Description
02801000
02810000
02811000
02820000
02821000
02830000
02831000
02840000
02841000
02850000
02858000
02860000
02900000
02921000
02A00000
02C00000
08000000
08010000
0BC00000
0BD00000
0C000000
0C400000
10800000
10880000
10900000
10E00000
10E08000
10F00000
10F08000
11800000
11880000
11900000
11E00000
11E08000
11F00000
11F08000
12800000
12880000
12900000
12E00000
12E08000
12F00000
12F08000
0280FFFF
02810FFF
0281FFFF
02820FFF
0282FFFF
02830FFF
0283FFFF
02840FFF
0284FFFF
02857FFF
0285FFFF
028FFFFF
02920FFF
029FFFFF
02BFFFFF
07FFFFFF
0800FFFF
0BBFFFFF
0BCFFFFF
0BFFFFFF
0C3FFFFF
107FFFFF
1087FFFF
108FFFFF
10DFFFFF
10E07FFF
10EFFFFF
10F07FFF
117FFFFF
1187FFFF
118FFFFF
11DFFFFF
11E07FFF
11EFFFFF
11F07FFF
127FFFFF
1287FFFF
128FFFFF
12DFFFFF
12E07FFF
12EFFFFF
12F07FFF
137FFFFF
0 02801000
0 02810000
0 02811000
0 02820000
0 02821000
0 02830000
0 02831000
0 02840000
0 02841000
0 02850000
0 02858000
0 02860000
0 02900000
0 02921000
0 02A00000
0 02C00000
0 08000000
0 08010000
0 0BC00000
0 0BD00000
0 0C000000
0 0C400000
0 10800000
0 10880000
0 10900000
0 10E00000
0 10E08000
0 10F00000
0 10F08000
0 11800000
0 11880000
0 11900000
0 11E00000
0 11E08000
0 11F00000
0 11F08000
0 12800000
0 12880000
0 12900000
0 12E00000
0 12E08000
0 12F00000
0 12F08000
0 0280FFFF
0 02810FFF
0 0281FFFF
0 02820FFF
0 0282FFFF
0 02830FFF
0 0283FFFF
0 02840FFF
0 0284FFFF
0 02857FFF
0 0285FFFF
0 028FFFFF
0 02920FFF
0 029FFFFF
0 02BFFFFF
0 07FFFFFF
0 0800FFFF
0 0BBFFFFF
0 0BCFFFFF
0 0BFFFFFF
0 0C3FFFFF
0 107FFFFF
0 1087FFFF
0 108FFFFF
0 10DFFFFF
0 10E07FFF
0 10EFFFFF
0 10F07FFF
0 117FFFFF
0 1187FFFF
0 118FFFFF
0 11DFFFFF
0 11E07FFF
0 11EFFFFF
0 11F07FFF
0 127FFFFF
0 1287FFFF
0 128FFFFF
0 12DFFFFF
0 12E07FFF
0 12EFFFFF
0 12F07FFF
0 137FFFFF
Reserved
4K
TI embedded trace buffer (TETB) - CorePac4
60K
Reserved
4K
TI embedded trace buffer (TETB) - CorePac5
60K
Reserved
4K
TI embedded trace buffer (TETB) - CorePac6
60K
Reserved
4K
TI embedded trace buffer (TETB) - CorePac7
60K
Reserved
32K
TI embedded trace buffer (TETB) — system
32K
Reserved
640K
132K
1M-132K
2M
Reserved
Serial RapidIO (SRIO) configuration
Reserved
Queue manager subsystem configuration
84M
64K
Reserved
Extended memory controller (XMC) configuration
60M-64K
1M
Reserved
Multicore shared memory controller (MSMC) config
Reserved
3M
4M
Multicore shared memory (MSM)
Reserved
68 M
512K
512K
5M
CorePac0 L2 SRAM
Reserved
Reserved
32K
CorePac0 L1P SRAM
Reserved
1M-32K
32K
CorePac0 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac1 L2 SRAM
Reserved
Reserved
32K
CorePac1 L1P SRAM
Reserved
1M-32K
32K
CorePac1 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac2 L2 SRAM
Reserved
Reserved
32K
CorePac2 L1P SRAM
Reserved
1M-32K
32K
CorePac2 L1D SRAM
Reserved
9M-32K
Copyright 2013 Texas Instruments Incorporated
Device Overview 25
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-2
Memory Map Summary (Part 6 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
512K
512K
5M
Description
CorePac3 L2 SRAM
Reserved
13800000
13880000
13900000
13E00000
13E08000
13F00000
13F08000
14800000
14880000
14900000
14E00000
14E08000
14F00000
14F08000
15800000
15880000
15900000
15E00000
15E08000
15F00000
15F08000
16800000
16880000
16900000
16E00000
16E08000
16F00000
16F08000
17800000
17880000
17900000
17E00000
17E08000
17F00000
17F08000
20000000
20100000
20B00000
20B20000
20BF0000
20BF0200
20C00000
20C00100
1387FFFF
138FFFFF
13DFFFFF
13E07FFF
13EFFFFF
13F07FFF
147FFFFF
1487FFFF
148FFFFF
14DFFFFF
14E07FFF
14EFFFFF
14F07FFF
157FFFFF
1587FFFF
158FFFFF
15DFFFFF
15E07FFF
15EFFFFF
15F07FFF
167FFFFF
1687FFFF
168FFFFF
16DFFFFF
16E07FFF
16EFFFFF
16F07FFF
177FFFFF
1787FFFF
178FFFFF
17DFFFFF
17E07FFF
17EFFFFF
17F07FFF
1FFFFFFF
200FFFFF
20AFFFFF
20B1FFFF
20BEFFFF
20BF01FF
20BFFFFF
20C000FF
20FFFFFF
0 13800000
0 13880000
0 13900000
0 13E00000
0 13E08000
0 13F00000
0 13F08000
0 14800000
0 14880000
0 14900000
0 14E00000
0 14E08000
0 14F00000
0 14F08000
0 15800000
0 15880000
0 15900000
0 15E00000
0 15E08000
0 15F00000
0 15F08000
0 16800000
0 16880000
0 16900000
0 16E00000
0 16E08000
0 16F00000
0 16F08000
0 17800000
0 17880000
0 17900000
0 17E00000
0 17E08000
0 17F00000
0 17F08000
0 20000000
0 20100000
0 20B00000
0 20B20000
0 20BF0000
0 20BF0200
0 20C00000
0 20C00100
0 1387FFFF
0 138FFFFF
0 13DFFFFF
0 13E07FFF
0 13EFFFFF
0 13F07FFF
0 147FFFFF
0 1487FFFF
0 148FFFFF
0 14DFFFFF
0 14E07FFF
0 14EFFFFF
0 14F07FFF
0 157FFFFF
0 1587FFFF
0 158FFFFF
0 15DFFFFF
0 15E07FFF
0 15EFFFFF
0 15F07FFF
0 167FFFFF
0 1687FFFF
0 168FFFFF
0 16DFFFFF
0 16E07FFF
0 16EFFFFF
0 16F07FFF
0 177FFFFF
0 1787FFFF
0 178FFFFF
0 17DFFFFF
0 17E07FFF
0 17EFFFFF
0 17F07FFF
0 1FFFFFFF
0 200FFFFF
0 20AFFFFF
0 20B1FFFF
0 20BEFFFF
0 20BF01FF
0 20BFFFFF
0 20C000FF
0 20FFFFFF
Reserved
32K
CorePac3 L1P SRAM
Reserved
1M-32K
32K
CorePac3 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac4 L2 SRAM
Reserved
Reserved
32K
CorePac4 L1P SRAM
Reserved
1M-32K
32K
CorePac4 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac5 L2 SRAM
Reserved
Reserved
32K
CorePac5 L1P SRAM
Reserved
1M-32K
32K
CorePac5 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac6 L2 SRAM
Reserved
Reserved
32K
CorePac6 L1P SRAM
Reserved
1M-32K
32K
CorePac6 L1D SRAM
Reserved
9M-32K
512K
512K
5M
CorePac7 L2 SRAM
Reserved
Reserved
32K
CorePac7 L1P SRAM
Reserved
1M-32K
32K
CorePac7 L2 SRAM
Reserved
129M-32K
1M
System trace manager (STM) configuration
Reserved
10M
128K
832K
512
Boot ROM
Reserved
SPI
64K-512
256
Reserved
EMIF16 config
Reserved
12M - 256
26
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-2
Memory Map Summary (Part 7 of 7)
Logical 32-bit Address
Physical 36-bit Address
Start
End
Start
End
Bytes
512
Description
21000000
21000200
21400000
21400100
21800000
21808000
34000000
34200000
40000000
50000000
60000000
70000000
74000000
78000000
7C000000
80000000
End of Table 2-2
210001FF
213FFFFF
214000FF
217FFFFF
21807FFF
33FFFFFF
341FFFFF
3FFFFFFF
4FFFFFFF
5FFFFFFF
6FFFFFFF
73FFFFFF
77FFFFFF
7BFFFFFF
7FFFFFFF
FFFFFFFF
1 00000000
0 21000200
0 21400000
0 21400100
0 21800000
0 21808000
0 34000000
0 34200000
0 40000000
0 50000000
0 60000000
0 70000000
0 74000000
0 78000000
0 7C000000
8 00000000
1 000001FF
0 213FFFFF
0 214000FF
0 217FFFFF
0 21807FFF
0 33FFFFFF
0 341FFFFF
0 3FFFFFFF
0 4FFFFFFF
0 5FFFFFFF
0 6FFFFFFF
0 73FFFFFF
0 77FFFFFF
0 7BFFFFFF
0 7FFFFFFF
8 7FFFFFFF
DDR3 EMIF configuration
4M-512
256
Reserved
HyperLink config
4M-256
32K
Reserved
PCIe config
296M-32K
2M
Reserved
Queue manager subsystem data
190M
256M
256M
256M
64M
Reserved
HyperLink data
Reserved
PCIe data
EMIF16 CE0 data space, supports NAND, NOR or SRAM memory(1)
EMIF16 CE1 data space, supports NAND, NOR or SRAM memory(1)
EMIF16 CE2 data space, supports NAND, NOR or SRAM memory(1)
EMIF16 CE3 data space, supports NAND, NOR or SRAM memory(1)
DDR3 EMIF data (2)
64M
64M
64M
2G
1 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. The 32MB and 16MB size restrictions do not apply to NAND.
2 The memory map only shows the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access (up to 8GB), please refer to the MPAX
configuration details in C66x CorePac User Guide and Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 73.
2.4 Boot Sequence
The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect
the state of the hardware boot controller on the device. For more details on the initiators of the resets, see section
7.4 ‘‘Reset Controller’’ on page 132. The bootloader uses a section of the L2 SRAM (start address 0x0087 2DC0 and
end address 0x0087 FFFF) during initial booting of the device. For more details on the type of configurations stored
in this reserved L2 section see Table 2-3.
Table 2-3
Bootloader section in L2 SRAM (Part 1 of 2)
Start Address (Hex)
0x00872DC0
0x00872E00
0x00873200
0x008732E0
0x00873300
0x00873400
0x00873420
0x00873500
0x00873600
0x00873680
0x00873700
0x00878000
Size (Hex Bytes)
0x40
Description
ROM boot version string (Unreserved)
Boot code stack
0x400
0xE0
Boot log
0x20
Boot progress register stack (copies of boot program on mode change)
Boot Internal Stats
0x100
0x20
Boot table arguments
0xE0
ROM boot FAR data
0x100
0x80
DDR configuration table
RAM table
0x80
Boot parameter table
0x4900
0x7F80
Clear text packet scratch
Ethernet/SRIO packet/message/descriptor memory
Copyright 2013 Texas Instruments Incorporated
Device Overview 27
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 2-3
Bootloader section in L2 SRAM (Part 2 of 2)
Start Address (Hex)
0x0087FF80
Size (Hex Bytes)
Description
Small stack
0x40
0x3C
0x4
0x0087FFC0
Not used
0x0087FFFC
Boot magic address
End of Table 2-3
The C6678 supports several boot processes that begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software-driven and use
the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be
completed. For more details on Boot Sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
2.5 Boot Modes Supported and PLL Settings
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:
•
Public ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base
address. After performing the boot process (e.g., from I2C ROM, Ethernet, or RapidIO), C66x CorePac0 then
begins execution from the provided boot entry point, other C66x CorePac’s are released from reset and begin
executing an IDLE from the L3 ROM. They are then released from IDLE based on interrupts generated by
C66x CorePac0. See the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 73 for more details.
•
Secure ROM Boot - On secure devices, the C66x CorePac0 is released from reset and begin executing from
secure ROM. Software in the secure ROM will free up internal RAM pages, after which C66x CorePac0
initiates the boot process. The C66x CorePac0 performs any authentication and decryption required on the
bootloaded image prior to beginning execution.
The boot process performed by the C66x CorePac0 in public ROM boot and secure ROM boot are determined by
the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the
associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0].
Figure 2-2
Boot Mode Pin Decoding
Boot Mode Pins
6
12
11
10
9
8
7
5
4
3
2
1
0
PLL Mult I2C /SPI Ext Dev Cfg
Device Configuration
Boot Device
28
Device Overview
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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2.5.1 Boot Device Field
The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-4 shows the supported boot
modes.
Table 2-4
Boot Mode Pins: Boot Device Values
Description
Bit
Field
Boot Device
2-0
Device boot mode
0 = EMIF16 / No Boot
1 = Serial Rapid I/O
2 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as CORECLK(P|N); BOOTMODE[12:10] values drive
the PASS PLL configuration during boot)
3 = Ethernet (SGMII) (PASS PLL configuration assumes input rate same as SRIOSGMIICLK(P|N); BOOTMODE[9:8] values
drive the PASS PLL configuration during boot)
4 = PCIe
5 = I2C
6 = SPI
7 = HyperLink
End of Table 2-4
Internally this boot mode are translated by RBL into the extended boot mode value that is used in the boot parameter
table. Table 2-5 shows the details of extended boot mode values.
Table 2-5
Boot Type
Extended Boot Modes
Extended Boot Mode Value (Decimal)
Ethernet Boot Mode
SRIO Boot Mode
10
20
30
40
41
50
60
70
100
PCIe Boot Mode
I2C Master Boot Mode
I2C Passive Boot Mode
SPI Boot Mode
HyperLink Boot Mode
EMIF 16 Boot Mode
Sleep Boot Mode
Copyright 2013 Texas Instruments Incorporated
Device Overview 29
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Multicore Fixed and Floating-Point Digital Signal Processor
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2.5.2 Device Configuration Field
The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit
definitions depend on the boot mode
2.5.2.1 No Boot/ EMIF16 Boot Device Configuration
Figure 2-3
9
No Boot/ EMIF16 Configuration Fields
8
7
6
5
4
3
Sub-Mode
Wait Enable
Reserved
Table 2-6
No Boot / EMIF16 Configuration Field Descriptions
Description
Bit
Field
Sub-Mode
9-8
Sub mode selection.
0 = No boot
1 = EMIF16 boot
2 -3 = Reserved
7
Wait Enable
Reserved
Extended Wait mode for EMIF16.
0 = Wait enable disabled (EMIF16 sub mode)
1 = Wait enable enabled (EMIF16 sub mode)
6-3
Reserved
End of Table 2-6
2.5.2.2 Serial Rapid I/O Boot Device Configuration
The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.
Figure 2-4
Serial Rapid I/O Device Configuration Fields
9
8
7
6
5
4
3
Lane Setup
Data Rate
Ref Clock
Reserved
Table 2-7
Serial Rapid I/O Configuration Field Descriptions
Field Description
Bit
9
Lane Setup
SRIO port and lane configuration
0 = Port Configured as 4 ports each 1 lane wide (4 -1× ports)
1 = Port Configured as 2 ports 2 lanes wide (2 – 2× ports)
8-7
6-5
4-3
Data Rate
SRIO data rate configuration
0 = 1.25 GBaud
1 = 2.5 GBaud
2 = 3.125 GBaud
3 = 5.0 GBaud
Ref Clock
Reserved
SRIO reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
Reserved
End of Table 2-7
In SRIO boot mode, the message mode will be enabled by default. If use of the memory reserved for received
messages is required and reception of messages cannot be prevented, the master can disable the message mode by
writing to the boot table and generating a boot restart.
30
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Multicore Fixed and Floating-Point Digital Signal Processor
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2.5.2.3 Ethernet (SGMII) Boot Device Configuration
Figure 2-5
9
Ethernet (SGMII) Device Configuration Fields
8
7
6
5
4
3
SerDes Clock Mult
Ext connection
Device ID
Table 2-8
Ethernet (SGMII) Configuration Field Descriptions
Bit
Field Description
9-8
SerDes Clock Mult
Ext connection
Device ID
SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.
0 = ×8 for input clock of 156.25 MHz
1 = ×5 for input clock of 250 MHz
2 = ×4 for input clock of 312.5 MHz
3 = Reserved
7-6
External connection mode
0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave, and MAC to PHY
2 = MAC to MAC, forced link
3 = MAC to fiber connection
5-3
This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.
End of Table 2-8
Note—Both of the SGMII ports have been initialized for boot. The device can boot through either of the
ports. If only one SGMII port is used, then the other port will time out before the boot process completes.
2.5.2.4 PCI Boot Device Configuration
Extra device configuration is provided by the PCI bits in the DEVSTAT register.
Figure 2-6
PCI Device Configuration Fields
9
8
7
6
5
4
3
Reserved
BAR Config
Reserved
Table 2-9
PCI Device Configuration Field Descriptions
Field Description
Bit
9
Reserved
Reserved
8-5
BAR Config
PCIe BAR registers configuration
This value can range from 0 to 0xf. See Table 2-10.
Reserved
4-3
Reserved
End of Table 2-9
Copyright 2013 Texas Instruments Incorporated
Device Overview 31
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Multicore Fixed and Floating-Point Digital Signal Processor
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Table 2-10
BAR Config / PCIe Window Sizes
32-Bit Address Translation
64-Bit Address Translation
BAR cfg
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
BAR0
BAR1
32
16
16
32
16
16
32
32
64
4
BAR2
32
BAR3
32
BAR4
32
BAR5
BAR2/3
BAR4/5
16
32
64
32
32
64
32
32
64
16
64
64
32
64
64
Clone of BAR4
32
64
64
32
64
128
256
128
256
256
PCIe MMRs
64
128
128
128
256
128
128
128
4
4
0b1100
0b1101
0b1110
0b1111
256
256
512
512
1024
2048
1024
2048
End of Table 2-10
2.5.2.5 I2C Boot Device Configuration
2.5.2.5.1 I2C Master Mode
In master mode, the I2C device configuration uses ten bits of device configuration instead of seven as used in other
boot modes. In this mode, the device will make the initial read of the I2C EEPROM while the PLL is in bypass mode.
The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.
Figure 2-7
I2C Master Mode Device Configuration Bit Fields
12
11
10
9
8
7
6
5
4
3
Reserved
Speed
Address
Mode
Parameter Index
Table 2-11
I2C Master Mode Device Configuration Field Descriptions
Bit
12
11
Field
Description
Reserved
Speed
Reserved
I2C data rate configuration
0 = I2C slow mode. Initial data rate is CORECLK/5000 until PLLs and clocks are programmed
1 = I2C fast mode. Initial data rate is CORECLK/250 until PLLs and clocks are programmed
10
Address
Mode
I2C bus address configuration
0 = Boot from I2C EEPROM at I2C bus address 0x50
1 = Boot from I2C EEPROM at I2C bus address 0x51
9-8
I2C operation mode
0 = Master mode
3 = Passive mode (see section 2.5.2.5.2 ‘‘I2C Passive Mode’’)
Others = Reserved
7-3
Parameter Index
Identifies the index of the configuration table initially read from the I2C EEPROM
This value can range from 0 to 31.
End of Table 2-11
32
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Multicore Fixed and Floating-Point Digital Signal Processor
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2.5.2.5.2 I2C Passive Mode
In passive mode, the device does not drive the clock, but simply acks data received on the specified address.
Figure 2-8
9
I2C Passive Mode Device Configuration Bit Fields
8
7
6
5
4
3
Mode
Receive I2C Address
Reserved
Table 2-12
I2C Passive Mode Device Configuration Field Descriptions
Bit
Field
Description
9-8
Mode
I2C operation mode
0 = Master mode (see section 2.5.2.5.1 ‘‘I2C Master Mode’’)
3 = Passive mode
Others = Reserved
7-5
4-3
Receive I2C Address
Reserved
I2C bus address configuration
0 - 7h= The I2C Bus address the device will listen to for data
The actual value on the bus is 0x19 plus the value in bits [7:5]. For Ex. if bits[7:5] = 0 then the device will listen to I2C
bus address 0x19.
Reserved
End of Table 2-12
2.5.2.6 SPI Boot Device Configuration
In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.
Figure 2-9
SPI Device Configuration Bit Fields
12
11
10
9
8
7
6
5
4
3
Mode
4, 5 Pin
Addr Width
Chip Select
Parameter Table Index
Table 2-13
SPI Device Configuration Field Descriptions
Bit
Field
Description
12-11
Mode
Clk Pol / Phase
0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data
is latched on the rising edge of SPICLK.
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data
is latched on the falling edge of SPICLK.
10
9
4, 5 Pin
SPI operation mode configuration
0 = 4-pin mode used
1 = 5-pin mode used
Addr Width
Chip Select
SPI address width configuration
0 = 16-bit address values are used
1 = 24-bit address values are used
8-7
6-3
The chip select field value
Parameter Table Index Specifies which parameter table is loaded
End of Table 2-13
Copyright 2013 Texas Instruments Incorporated
Device Overview 33
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Multicore Fixed and Floating-Point Digital Signal Processor
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2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10
HyperLink Boot Device Configuration Fields
9
8
7
6
5
4
3
Reserved
Data Rate
Ref Clock
Reserved
Table 2-14
HyperLink Boot Device Configuration Field Descriptions
Bit
9
Field
Description
Reserved
Reserved
8-7
Data Rate
Ref Clocks
Reserved
HyperLink data rate configuration
0 = 1.25 GBaud
1 = 3.125 GBaud
2 = 6.25 GBaud
3 = Reserved
6-5
HyperLink reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
4-3
Reserved
End of Table 2-14
2.5.3 Boot Parameter Table
The ROM Bootloader (RBL) uses a set of tables to carry out the boot process. The boot parameter table is the
most common format the RBL employs to determine the boot flow. These boot parameter tables have certain
parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The
common entries in the boot parameter table are shown in the table below:
Table 2-15
Boot Parameter Table Common Parameters
Byte
Offset
Name
Description
0
2
Length
The length of the table, including the length field, in bytes.
Checksum
The 16 bits ones complement of the ones complement of the entire table. A value of 0 will disable checksum verification
of the table by the boot ROM.
4
Boot Mode
Port Num
Internal values used by RBL for different boot modes.
Identifies the device port number to boot from, if applicable
PLL configuration, MSW
6
8
SW PLL, MSW
SW PLL, LSW
10
PLL configuration, LSW
End of Table 2-15
2.5.3.1 EMIF16 Boot Parameter Table
Table 2-16
Byte
EMIF16 Boot Mode Parameter Table
Configured Through Boot
Configuration Pins
Offset
Name
Description
12
Options
Option for EMIF16 boot (currently none)
-
-
-
-
14
Type
Only boot from NOR flash is supported for C6678
Most significant bit for Branch address (depends on chip select)
Least significant bit for Branch address (depends on chip select)
16
Branch Address MSW
Branch Address LSW
18
34
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Multicore Fixed and Floating-Point Digital Signal Processor
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Table 2-16
EMIF16 Boot Mode Parameter Table
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
20
Chip Select
Chip Select for the NOR flash
Memory width of the Emif16 bus (16 bits)
-
22
Memory Width
Wait Enable
-
24
Extended wait mode enabled
0 = Wait enable is disabled
1 = Wait enable is enabled
YES
End of Table 2-16
2.5.3.2 SRIO Boot Parameter Table
Table 2-17
SRIO Boot Mode Parameter Table
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
12
Options
Bit 0 Tx enable
-
0 = SRIO Transmit disable
1 = SRIO Transmit Enable
Bit 1 Mailbox Enable
0 = Mailbox mode disabled. SRIO boot is in DirectIO mode).
1 = Mailbox mode enabled. SRIO boot is in Messaging mode).
Bit 2 Bypass Configuration
0 = Configure the SRIO
1 = Bypass SRIO configuration
Bit 15-3 Reserved
14
16
Lane Setup
SRIO lane setup
YES
0 = SRIO configured as 4 1x ports
1 = SRIO configured as 3 ports (2x, 1x, 1x)
2 = SRIO configured as 3 ports (1x, 1x, 2x)
3 = SRIO configured as 2 ports (2x, 2x)
4 = SRIO configured as 1 4x port
Others = Reserved
(but not all lane setup are
possible through the boot
configuration pins)
Config Index
Specifies the template used for RapidIO configuration.
Must be 0 for KeyStone Architecture
The node ID value to set for this device
The SerDes reference clock frequency, in 1/100 MHZ
Link rate, MHz
-
18
20
22
24
26
Node ID
-
SerDes ref clk
Link Rate
PF Low
YES
YES
Packet forward address range, low value
Packet Forward address range, high value
-
-
PF High
End of Table 2-17
Copyright 2013 Texas Instruments Incorporated
Device Overview 35
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Multicore Fixed and Floating-Point Digital Signal Processor
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2.5.3.3 Ethernet Boot Parameter Table
Table 2-18
Ethernet Boot Mode Parameter Table (Part 1 of 2)
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
12
Options
Bits 2-0 Interface
101b = SGMII
-
Others = Reserved
Bit 3 Half or Full duplex
0 = Half Duplex
1 = Full Duplex
Bit 4 Skip TX
0 = Send Ethernet Ready Frame every 3 seconds
1 = Don't send Ethernet Ready Frame
Bits 6-5 Initialize Config
00b = Switch, SerDes, SGMII and PASS are configured
01b = Only SGMII and PASS are configured
10b= Reserved
11b = None of the Ethernet system is configured.
Bits 15-7 Reserved
14
16
18
20
22
24
26
MAC High
The 16 MSBs of the MAC address to receive during boot
The 16 middle bits of the MAC address to receive during boot
The 16 LSBs of the MAC address to receive during boot
The 16 MSBs of the multi-cast MAC address to receive during boot
The 16 middle bits of the multi-cast MAC address to receive during boot
The 16 LSBs of the multi-cast MAC address to receive during boot
The source UDP port to accept boot packets from.
A value of 0 will accept packets from any UDP port
The destination port to accept boot packets on.
-
-
-
-
-
-
-
MAC Med
MAC Low
Multi MAC High
Multi MAC Med
Multi MAC Low
Source Port
28
30
Dest Port
-
-
Device ID 12
The first two bytes of the device ID.
This is typically a string value, and is sent in the Ethernet ready frame
The 2nd two bytes of the device ID.
32
34
Device ID 34
-
-
Dest MAC High
The 16 MSBs of the MAC destination address used
for the Ethernet ready frame. Default is broadcast.
36
38
40
Dest MAC Med
Dest MAC Low
SGMII Config
The 16 middle bits of the MAC destination address
The 16 LSBs of the MAC destination address
Bits 3-0 are the config index
-
-
-
Bit 4 set if direct config used
Bit 5 set if no configuration done
Bits 15-6 Reserved
42
44
46
48
50
52
54
56
SGMII Control
The SGMII control register value
-
-
-
-
-
-
-
-
SGMII Adv Ability
SGMII TX Cfg High
SGMII TX Cfg Low
SGMII RX Cfg High
SGMII RX Cfg Low
SGMII Aux Cfg High
SGMII Aux Cfg Low
The SGMII ADV Ability register value
The 16 MSBs of the SGMII Tx config register
The 16 LSBs of the SGMII Tx config register
The 16 MSBs of the SGMII Rx config register
The 16 LSBs of the SGMII Rx config register
The 16 MSBs of the SGMII Aux config register
The 16 LSBs of the SGMII Aux config register
36
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 2-18
Ethernet Boot Mode Parameter Table (Part 2 of 2)
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
58
60
PKT PLL Cfg MSW
PKT PLL CFG LSW
The packet subsystem PLL configuration, MSW
The packet subsystem PLL configuration, LSW
-
-
End of Table 2-18
2.5.3.4 PCIe Boot Parameter Table
Table 2-19
PCIe Boot Mode Parameter Table
Byte
Offset
Configured Through Boot
Configuration Pins
Name
Description
12
Options
-
Bit 0 Mode
0 = Host Mode (Direct boot mode)
1 = Boot Table Boot Mode
Bit 1 Configuration of PCIe
0 = PCIe is configured by RBL
1 = PCIe is not configured by RBL
Bits 3-2 Reserved
Bit 4 Multiplier
0 = SERDES PLL configuration is done based on SERDES register values
1 = SERDES PLL configuration based on the reference clock values
Bits 15-5 Reserved
14
16
18
Address Width
Link Rate
PCI address width, can be 32 or 64
SerDes frequency, in Mbps. Can be 2500 or 5000
-
-
-
Reference clock
Reference clock frequency, in units of 10 kHz. Value values are 10000
(100 MHz), 12500 (125 MHz), 15625 (156.25 MHz), 25000 (250 MHz), and 31250
(312.5 MHz). A value of 0 means that value is already in the SerDes
configuration parameters and will not be computed by the boot ROM.
20
22
24
26
28
30
32
34
36
38
40
42
44
46
Window 1 Size
Window 1 size.
YES
Window 2 Size
Window 2 size.
YES
Window 3 Size
Window 3 size. Valid only if address width is 32.
Window 4 Size. Valid only if the address width is 32.
Vendor ID
YES
Window 4 Size
YES
Vendor ID
-
-
-
-
-
-
-
-
-
-
Device ID
Device ID
Class code Rev ID MSW
Class code Rev ID LSW
SerDes Cfg MSW
SerDes Cfg LSW
Class code revision ID MSW
Class code revision ID LSW
PCIe SerDes config word, MSW
PCIe SerDes config word, LSW
SerDes lane config word, MSW, lane 0
SerDes lane config word, LSW, lane 0
SerDes lane config word, MSW, lane 1
SerDes lane config word, LSW, lane 1
SerDes lane 0 Cfg MSW
SerDes lane 0 Cfg LSW
SerDes lane 1 Cfg MSW
SerDes lane 1 Cfg LSW
End of Table 2-19
Copyright 2013 Texas Instruments Incorporated
Device Overview 37
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Multicore Fixed and Floating-Point Digital Signal Processor
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2.5.3.5 I2C Boot Parameter Table
Table 2-20
I2C Boot Mode Parameter Table
Configured Through Boot
Configuration Pins
Byte Offset Name
Description
12
Option
Bits 1-0 Mode
YES
00b = Boot Parameter Table Mode
01b = Boot Table Mode
10b = Boot Config Mode
11b = Slave Receive Boot Config
Bits 15-2 Reserved
14
16
18
20
22
24
26
28
Boot Dev Addr
Boot Dev Addr Ext
Broadcast Addr
Local Address
Device Freq
The I2C device address to boot from
YES
Extended boot device address
YES
I2C address used to send data in the I2C master broadcast mode.
The I2C address of this device
-
-
The operating frequency of the device (MHz)
The desired I2C data rate (kHz)
-
Bus Frequency
Next Dev Addr
Next Dev Addr Ext
YES
The next device address to boot (Used only if boot config option is selected)
-
-
The extended next device address to boot (Used only if boot config option is
selected)
30
Address Delay
The number of CPU cycles to delay between writing the address to an I2C
EEPROM and reading data.
-
End of Table 2-20
2.5.3.6 SPI Boot Parameter Table
Table 2-21
SPI Boot Mode Parameter Table
Configured Through Boot
Configuration Pins
Byte Offset Name
Description
12
Options
Bits 1-0 Modes
-
00b = Load a boot parameter table from the SPI (Default mode)
01b = Load boot records from the SPI (boot tables)
10b = Load boot config records from the SPI (boot config tables)
11b = Reserved
Bits 15-2 Reserved
14
16
18
20
22
24
26
28
30
32
28
30
32
Address Width
NPin
The number of bytes in the SPI device address. Can be 16 or 24 bit
The operational mode, 4or 5pin
YES
YES
Chipsel
The chip select used (valid in 4 pin mode only). Can be 0-3.
Standard SPI mode (0-3)
YES
Mode
YES
C2Delay
Setup time between chip assert and transaction
The speed of the CPU, in MHz
-
CPU Freq MHz
Bus Freq, MHz
Bus Freq, kHz
Read Addr MSW
Read Addr LSW
Next Chip Select
Next Read Addr MSW
Next Read Addr LSW
-
The MHz portion of the SPI bus frequency. Default = 5 MHz
The kHz portion of the SPI buf frequency. Default = 0
The first address to read from, MSW (valid for 24 bit address width only)
The first address to read from, LSW
-
-
YES
YES
Next Chip Select to be used (Used only in boot Config mode)
The Next read address (used in boot config mode only)
The Next read address (used in boot config mode only)
-
-
-
End of Table 2-21
38
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.5.3.7 HyperLink Boot Parameter Table
Table 2-22
HyperLink Boot Mode Parameter Table
Configured Through Boot
Configuration Pins
Byte Offset Name
Description
12
Options
Bit 0 Mode
-
0 = Host Mode (Direct boot mode)
1 = Boot Table Boot Mode
Bit 1 Configuration of PCIe
0 = PCIe is configured by RBL
1 = PCIe is not configured by RBL
Bits 15-2 Reserved
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Number of Lanes
SerDes cfg msw
SerDes cfg lsw
Number of Lanes to be configured
HyperLink SerDes config word, MSW
HyperLink SerDes config word, LSW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SerDes CFG RX lane 0 cfg msw SerDes RX lane config word, msw lane 0
SerDes CFG RXlane 0 cfg lsw
SerDes CFG TX lane 0 cfg msw
SerDes CFG TXlane 0 cfg lsw
SerDes RX lane config word, lsw, lane 0
SerDes TX lane config word, msw lane 0
SerDes TX lane config word, lsw, lane 0
SerDes CFG RX lane 1 cfg msw SerDes RX lane config word, msw lane 1
SerDes CFG RXlane 1 cfg lsw
SerDes CFG TX lane 1 cfg msw
SerDes CFG TXlane 1 cfg lsw
SerDes RX lane config word, lsw, lane 1
SerDes TX lane config word, msw lane 1
SerDes TX lane config word, lsw, lane 1
SerDes CFG RX lane 2 cfg msw SerDes RX lane config word, msw lane 2
SerDes CFG RXlane 2 cfg lsw
SerDes CFG TX lane 2 cfg msw
SerDes CFG TXlane 2 cfg lsw
SerDes RX lane config word, lsw, lane 2
SerDes TX lane config word, msw lane 2
SerDes TX lane config word, lsw, lane 2
SerDes CFG RX lane 3 cfg msw SerDes RX lane config word, msw lane 3
SerDes CFG RXlane 3 cfg lsw
SerDes CFG TX lane 3 cfg msw
SerDes CFG TXlane 3 cfg lsw
SerDes RX lane config word, lsw, lane 3
SerDes TX lane config word, msw lane 3
SerDes TX lane config word, lsw, lane 3
End of Table 2-22
Copyright 2013 Texas Instruments Incorporated
Device Overview 39
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.5.3.8 DDR3 Configuration Table
The ROM Bootloader (RBL) also provides an option to configure the DDR table before loading the image into the
external memory. More information on how to configure the DDR3, See the Bootloader for the C66x DSP User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 73 for more details. The configuration table for DDR3
is shown below:
Table 2-23
DDR3 Boot Parameter Table
Configured Through Boot
Configuration Pins
Byte Offset Name
Description
0
configselect
Selecting the configuration register below that to be set. Each filed below
is represented by one bit each.
-
4
pllprediv
PLL pre divider value (Should be the exact value not value -1)
PLL Multiplier value (Should be the exact value not value -1)
PLL post divider value (Should be the exact value not value -1)
SDRAM config register
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
8
pllMult
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84
88
92
96
100
104
108
pllPostDiv
sdRamConfig
sdRamConfig2
sdRamRefreshctl
sdRamTiming1
sdRamTiming2
sdRamTiming3
IpDfrNvmTiming
powerMngCtl
iODFTTestLogic
performcountCfg
performCountMstRegSel
readIdleCtl
SDRAM Config register
SDRAM Refresh Control Register
SDRAM Timing 1 Register
SDRAM Timing 2 Register
SDRAM Timing 3 Register
LP DDR2 NVM Timing Register
Power management Control Register
IODFT Test Logic Global Control Register
Performance Counter Config Register
Performance Counter Master Region Select Register
Read IDLE counter Register
sysVbusmIntEnSet
sdRamOutImpdedCalcfg
tempAlertCfg
ddrPhyCtl1
System Interrupt Enable Set Register
SDRAM Output Impedance Calibration Config Register
Temperature Alert Configuration Register
DDR PHY Control Register 1
ddrPhyCtl2
DDR PHY Control Register 1
proClassSvceMap
mstId2ClsSvce1Map
mstId2ClsSvce2Map
eccCtl
Priority to Class of Service mapping Register
Master ID to Class of Service Mapping 1 Register
Master ID to Class of Service Mapping 2Register
ECC Control Register
eccRange1
ECC Address Range1 Register
eccRange2
ECC Address Range2 Register
rdWrtExcThresh
Read Write Execution Threshold Register
End of Table 2-23
40
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.5.4 PLL Boot Configuration Settings
The PLL default settings are determined by the BOOTMODE[12:10] bits. The table below shows settings for various
input clock frequencies.
Table 2-24
C66x DSP System PLL Configuration (1)
800 MHz Device
1000 MHz Device
1200 MHz Device
1250 MHz Device
PASS PLL = 350 MHz (2)
BOOTMODE Input Clock
[12:10]
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
Freq (MHz)
50.00
0
0
0
0
31
23
19
15
800
0
0
0
0
4
0
4
39
29
24
19
63
7
1000
1000.05
1000
1000
1000
1000
1000
0
0
0
0
47
35
29
23
1200
0
1
3
0
0
0
0
2
49
74
1250
0
41
1050
66.67
800.04
800
1200.06
1200
1250.06
1
62
1050.053
1050
80.00
124 1250
3
104
20
100.00
156.25
250.00
312.50
122.88
800
1200
24
15
9
1250
1250
1250
1250
0
1050
24 255 800
31 800
24 383 1200
47 1200
24 191 1200
24
4
335
41
1050
4
4
1050
24 127 800
47 624 800
31
7
24
167
204
1050
28 471 999.989 31 624 1200
60
1249.28 11
1049.6
End of Table 2-24
1 The PLL boot configuration of initial silicon 1.0 may only support 800MHz, 1000MHz and 1200MHz frequencies by default.
2 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting
for the device (with OUTPUT_DIVIDE=2, by default).
CLK = CLKIN × ((PLLM+1) ÷ (OUTPUT_DIVIDE × (PLLD+1)))
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet
boot mode is selected with the input clock set to match the main PLL clock (not the PASS clock). See Table 2-4 for
details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip divider to
reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after the chip
divider (=3), feeds 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL and PASS PLL are
controlled by chip level MMRs. For details on how to set up the PLL see section 7.5 ‘‘Main PLL and PLL Controller’’
on page 139. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
2.6 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.
Copyright 2013 Texas Instruments Incorporated
Device Overview 41
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.7 Terminals
2.7.1 Package Terminals
Figure 2-11 shows the TMS320C6678CYP ball grid area (BGA) package (bottom view).
Figure 2-11
CYP 841-Pin BGA Package (Bottom View)
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25 27 29
10 12 14 16 18 20 22 24 26 28
2
4
6
8
2.7.2 Pin Map
Figure 2-13 through Figure 2-16 show the TMS320C6678 pin assignments in four quadrants (A, B, C, and D).
Figure 2-12
Pin Map Quadrants (Bottom View)
A B
D
C
42
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 2-13
1
Upper Left Quadrant—A (Bottom View)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SRIOSGMII
CLKN
VSS
DVDD18
RSV05
PASSCLKN PASSCLKP
VSS
PCIERXP1 PCIERXN1
VSS
RIORXN0
RIORXP0
VSS
RIORXP3
RIORXN3
AJ
DVDD18
RSV04
SPISCS1
RSV25
RSV24
PCIECLKN
VSS
PCIERXN0 PCIERXP0
VSS
RIORXN1
VSS
RIORXP1
RIOTXN1
RIOTXP0
VSS
VSS
RIOTXP1
VSS
RIORXP2
VSS
RIORXN2
RIOTXP2
RIOTXN3
VDDR4
VSS
RIOTXN2
VSS
AH
SRIOSGMII
CLKP
SPISCS0
CORECLKP CORECLKN PCIECLKP
VSS
PCIETXP1 PCIETXN1
AG
RSV22
CORESEL0
RSV20
VSS
DVDD18
VSS
PCIETXP0 PCIETXN0
VSS
VSS
RIOTXN0
VDDR2
RIOTXP3
VSS
AF
BOOT
COMPLETE
SPICLK
SYSCLKOUT PACLKSEL CORESEL3 CORESEL2
VSS
VSS
RSV15
VSS
AE
UARTRXD
SPIDIN
VSS
SCL
CORESEL1 AVDDA3
VSS
AVDDA2
VSS
VDDT2
VSS
VSS
VDDT2
VSS
VDDT2
RSV16
VDDT2
VSS
VDDT2
VSS
VDDT2
VSS
VSS
VDDT2
VSS
VDDT2
VSS
VSS
VDDT2
VSS
VDDT2
VSS
AD
UARTTXD
DVDD18
UARTCTS
SDA
VSS
VSS
AC
SPIDOUT
UARTRTS
DVDD18
DVDD18
VDDT2
VDDT2
VDDT2
AB
MCMTX
MCMTX
PMCLK
MCMTX
FLDAT
MCMTX
PMDAT
VSS
DVDD18
VSS
VSS
DVDD18
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
AA
FLCLK
MCMREF
CLKOUTP
MCMRX
PMCLK
MCMRX
PMDAT
MCMCLKN
MCMCLKP
RSV12
RSV13
Y
MCMREF
CLKOUTN
MCMRX
FLCLK
MCMRX
FLDAT
RSV14
CVDD
CVDD
CVDD1
CVDD1
W
VSS
VSS
VSS
VSS
VSS
VSS
VDDR1
VSS
VSS
VDDT1
VSS
VDDT1
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD1
VSS
CVDD1
VSS
VSS
CVDD1
VSS
CVDD1
VSS
V
VSS
MCMRXN0
MCMTXP1
U
MCMRXN1 MCMRXP0
MCMTXN1 MCMTXP2
VDDT1
CVDD
CVDD
CVDD
CVDD
T
A
Copyright 2013 Texas Instruments Incorporated
Device Overview 43
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 2-14
16
Upper Right Quadrant—B (Bottom View)
17
18
19
20
21
22
23
24
25
26
27
28
29
VSS
SGMII0RXP SGMII0RXN
VSS
TR15
TR13
FSB1
CLKA1
TX02
TR01
FSA0
EMU16
DVDD18
VSS
AJ
AH
AG
AF
AE
AD
AC
SGMII1RXP SGMII1RXN
VSS
RSV08
VSS
TX16
TX14
TX17
TX15
HOUT
POR
TR16
TR17
TR14
DVDD18
VSS
CLKB1
FSA1
TX04
TX03
TR05
TR00
FSB0
EMU18
EMU15
RSV01
EMU14
EMU11
EMU08
EMU05
EMU01
DVDD18
VSS
DVDD18
EMU12
EMU09
EMU07
EMU04
EMU00
VSS
SGMII0TXP SGMII0TXN
CLKB0
SGMII1TXP SGMII1TXN
VSS
VDDT2
VSS
RSV09
VSS
TX10
TX07
TX05
CLKA0
DVDD18
VSS
EMU17
VDDR3
VSS
VSS
VDDT2
VSS
TX13
TR10
TX11
TX12
VSS
TX06
TX00
TR07
EMU10
RSV17
VSS
TR11
TR02
TR03
TX01
EMU13
EMU03
EMIFD14
EMIFD06
EMIFD03
EMIFA17
EMIFA11
DVDD18
VSS
EMU06
VDDT2
VSS
VDDT2
VSS
TR12
TR04
TR06
EMIFD15
EMIFD09
EMIFD07
EMIFD08
EMIFA18
EMIFA12
EMIFA06
EMIFA03
EMU02
VDDT2
VSS
DVDD18
VSS
VSS
DVDD18
RSV0A
CVDD
VSS
EMIFD12
VSS
EMIFD13
EMIFD10
EMIFD11
EMIFA19
EMIFA13
EMIFA07
EMIFA01
EMIFD05
EMIFD04
EMIFD00
EMIFA15
EMIFA10
EMIFA04
EMIFD01
EMIFD02
EMIFA21
EMIFA16
EMIFA09
EMIFA02
AB
AA
Y
CVDD
VSS
CVDD
VSS
RSV0B
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
DVDD18
EMIFA20
DVDD18
EMIFA23
DVDD18
EMIFA22
EMIFA14
EMIFA08
EMIFA05
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
W
V
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
U
CVDD
CVDD
CVDD
EMIFA00 EMIFWAIT1 EMIFWAIT0
T
B
44
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 2-15
Lower Right Quadrant—C (Bottom View)
C
CVDD1
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
EMIFBE1
DVDD18
RSV03
EMIFBE0
EMIFWE
RSV02
EMIFCE3
EMIFCE0
EMIFOE
EMIFRW
LRESET
EMIFCE1
TDI
EMIFCE2
TRST
TDO
TMS
TCK
R
VSS
CVDD
VSS
P
CVDD
CVDD
CVDD1
CVDD1
RESETFULL
RESETSTAT
DVDD18
N
LRESET
NMIEN
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
RSV26
RSV27
NMI
TIMO1
VSS
RESET
M
L
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD1
VSS
VSS
CVDD
VSS
CVDD1
RSV10
RSV11
VCNTL0
VCNTL1
VCNTL2
TIMI0
TIMO0
GPIO13
GPIO04
TIMI1
GPIO15
GPIO07
GPIO05
GPIO11
GPIO08
GPIO01
GPIO12
GPIO10
GPIO02
GPIO14
GPIO06
GPIO09
GPIO03
K
J
CVDD
CVDD
CVDD
DDRSL
RATE1
VSS
CVDD
VSS
VSS
CVDD
VSS
VSS
CVDD
VSS
AVDDA1
PTV15
VCNTL3
DVDD15
DVDD18
VSS
GPIO00
RSV21
MDCLK
MDIO
RSV06
RSV07
DDRCLKN
DDRCLKP
H
DDRSL
RATE0
DVDD15
DVDD15
DVDD15
G
F
VSS
DVDD15
DDRA12
DDRA14
DDRA15
VSS
DVDD15
DDRCB00
DDRCB02
DDRCB04
DDRD25
VSS
DDRD27
DDRD26
DDRD24
DDRD29
DDRD17
DDRD23
DDRD28
DDRD31
DDRD16
DDRD19
DVDD15
VSS
DDRD08
DDRD09
DDRD18
DDRD22
DDRD07
DDRD10
DDRD11
DVDD15
DVDD15
DDRD06
DDRD12
DDRD13
VSS
DVDD15
DDRD00
DDRD03
VSS
DDRA10
DDRA11
DDRA13
DDRCKE1
VSS
DDRD02
DDRD04
DDRDQM0
DDRD01
E
DVDD15
DDRCB01
D
C
DDRCB05
DDRDQM1 DDRDQS0P DDRDQS0N
DDRCLK
OUTN1
VSS
DVDD15
17
DDRCB06 DDRDQS8N DDRCB03 DDRDQS3N DDRD30
DDRCB07 DDRDQS8P DDRDQM8 DDRDQS3P DDRDQM3
DDRD21 DDRDQS2N
VSS
DDRD14 DDRDQS1N DDRD05
DVDD15
VSS
B
A
DDRCLK
OUTP1
DDRD20
DDRDQS2P DDRDQM2
DDRD15
DDRDQS1P DVDD15
16
18
19
20
21
22
23
24
25
26
27
28
29
Copyright 2013 Texas Instruments Incorporated
Device Overview 45
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 2-16
Lower Left Quadrant—D (Bottom View)
D
MCMRXP1
VSS
VSS
VSS
VSS
MCMTXN2
VSS
VDDT1
VSS
VSS
VDDT1
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD
VSS
VSS
CVDD
VSS
CVDD1
VSS
VSS
CVDD
VSS
CVDD1
VSS
VSS
CVDD
VSS
R
VSS
MCMRXN3
MCMTXP3
P
MCMRXP2 MCMRXP3
VSS
MCMTXN3 MCMTXP0
VDDT1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
N
M
L
MCMRXN2
VSS
VSS
VSS
VSS
VSS
VSS
MCMTXN0
VSS
VDDT1
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
VSS
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CVDD1
VSS
CVDD1
VSS
CVDD
VSS
CVDD1
VSS
CVDD1
VSS
K
J
VSS
VSS
VSS
VSS
VSS
VSS
CVDD1
VSS
CVDD
VSS
CVDD
VSS
CVDD1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
H
G
F
VSS
DVDD15
DDRD60
DDRD58
VSS
DVDD15
DDRD56
DDRD53
DDRD52
DDRD54
VSS
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
DVDD15
DDRA02
DDRD63
DDRD62
DDRD61
DVDD15
VSS
DVDD15
VSS
VSS
DVDD15
DDRD42
DDRD41
DDRD43
DVDD15
DDRD36
DDRD35
DDRD37
DVDD15
DDRA03
DDRA08
DDRA09
DDRA07
DDRA05
DDRD45
DDRD46
DDRD47
DDRD39
DVDD15
VSS
DDRD32 DDRRESET
DDRWE
DDRCAS
DDRCE1
DDRODT1 VREFSSTL
E
DDRDQS7P DDRD57
DDRDQS7N DDRD59
DVDD15
DDRD48
DDRD33
DDRRAS
DDRCKE0
DDRCE0
DDRODT0
DDRBA2
VSS
D
C
DDRD55
DVDD15
DDRCLK
OUTN0
DVDD15 DDRDQM7 DDRDQS6P DDRD50 DDRDQM6 DDRDQS5P DDRD44
DDRD38 DDRDQS4N DDRD34
VSS
DDRBA1
DDRBA0
13
DDRA01
DDRA00
14
DDRA06
DDRA04
15
B
A
DDRCLK
OUTP0
VSS
DVDD15 DDRDQS6N DDRD51
DDRD49 DDRDQS5N DDRD40 DDRDQM5 DDRDQS4P DDRDQM4 DVDD15
1
2
3
4
5
6
7
8
9
10
11
12
46
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.8 Terminal Functions
The terminal functions table (Table 2-26) identifies the external signal names, the associated pin (ball) numbers, the
pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin
descriptions. This table is arranged by function. The power terminal functions table (Table 2-27) lists the various
power supply pins and ground pins and gives functional pin descriptions. Table 2-28 shows all pins arranged by
signal name. Table 2-29 shows all pins arranged by ball number.
There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated
with a dagger (†).
For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and
pullup/pulldown resistors, see section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 97.
Use the symbol definitions in Table 2-25 when reading Table 2-26.
Table 2-25
I/O Functional Symbol Definitions
Functional
Symbol
Table 2-26
Column Heading
Definition
Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-k resistor can
be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and
situations in which external pulldown/pullup resistors are required, see Hardware Design Guide for
KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 73.
IPD or IPU
IPD/IPU
A
Analog signal
Type
Type
Type
Type
Type
Type
GND
Ground
I
Input terminal
O
Output terminal
Supply voltage
S
Z
Three-state terminal or high impedance
End of Table 2-25
Table 2-26
Signal Name
Terminal Functions — Signals and Control by Function (Part 1 of 12)
Ball No. Type IPD/IPU Description
Boot Configuration Pins
LENDIAN †
H25
J28
J29
J26
J25
J27
J24
K27
K28
K26
K29
L28
L29
K25
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
UP
Endian configuration pin (Pin shared with GPIO[0])
BOOTMODE00 †
BOOTMODE01†
BOOTMODE02 †
BOOTMODE03 †
BOOTMODE04 †
BOOTMODE05 †
BOOTMODE06 †
BOOTMODE07 †
BOOTMODE08 †
BOOTMODE09 †
BOOTMODE10 †
BOOTMODE11 †
BOOTMODE12 †
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
See Section 2.5 ‘‘Boot Modes Supported and PLL Settings’’ on page 28 for more details
(Pins shared with GPIO[1:13])
Copyright 2013 Texas Instruments Incorporated
Device Overview 47
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 2 of 12)
Ball No. Type IPD/IPU Description
Signal Name
PCIESSMODE0 †
PCIESSMODE1 †
PCIESSEN †
K24
L27
L24
IOZ
IOZ
I
Down
Down
Down
PCIe Mode selection pins (Pins shared with GPIO[14:15])
PCIe module enable (Pin shared with TIMI0)
Clock / Reset
CORECLKP
CORECLKN
SRIOSGMIICLKP
SRIOSGMIICLKN
DDRCLKP
DDRCLKN
PCIECLKP
PCIECLKN
MCMCLKP
MCMCLKN
PASSCLKP
PASSCLKN
AVDDA1
AG3
AG4
AG6
AJ6
I
Core Clock Input to main PLL.
I
I
RapidIO/SGMII Reference Clock to drive the RapidIO and SGMII SerDes
DDR Reference Clock Input to DDR PLL (
I
G29
H29
AG5
AH5
W2
I
I
I
PCIe Clock Input to drive PCIe SerDes
I
I
HyperLink Reference Clock to drive the HyperLink SerDes
Network Coprocessor (PASS PLL) Reference Clock
Y2
I
AJ5
I
AJ4
I
H22
AC6
AD5
AE3
AE4
AD20
M25
N26
M27
AF2
AD4
AE6
AE5
N25
M29
AC20
N27
AE2
G22
P
SYS_CLK PLL Power Supply Pin
AVDDA2
P
DDR_CLK PLL Power Supply Pin
AVDDA3
P
PASS_CLK PLL Power Supply Pin
SYSCLKOUT
PACLKSEL
HOUT
OZ
Down
Down
UP
System Clock Output to be used as a general purpose output clock for debug purposes
PA clock select to choose between core clock and PASSCLK pins
Interrupt output pulse created by IPCGRH
Non-maskable Interrupt
I
OZ
NMI
I
UP
LRESET
I
UP
Warm Reset
LRESETNMIEN
CORESEL0
CORESEL1
CORESEL2
CORESEL3
RESETFULL
RESET
I
UP
Enable for core selects
I
Down
Down
Down
Down
UP
I
Select for the target core for LRESET and NMI. For more details see Table 7-48‘‘NMI and Local Reset
Timing Requirements’’ on page 188
I
I
I
Full Reset
I
UP
Warm Reset of non isolated portion on the IC
Power-on Reset
POR
I
RESETSTAT
BOOTCOMPLETE
PTV15
O
OZ
A
UP
Reset Status Output
Down
Boot progress indication output
PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15 pin
and ground is used to closely tune the output impedance of the DDR interface drivers to 50ohms.
Presently the recommended value for this 1% resistor is 45.3 ohms.
48
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 3 of 12)
Signal Name
Ball No. Type IPD/IPU Description
DDR
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
DDRDQS0P
DDRDQS0N
DDRDQS1P
DDRDQS1N
DDRDQS2P
DDRDQS2N
DDRDQS3P
DDRDQS3N
DDRDQS4P
DDRDQS4N
DDRDQS5P
DDRDQS5N
DDRDQS6P
DDRDQS6N
DDRDQS7P
DDRDQS7N
DDRDQS8P
DDRDQS8N
DDRCB00
E29
C27
A25
A22
A10
A8
OZ
OZ
OZ
OZ
OZ
DDR EMIF Data Masks
OZ
B5
OZ
B2
OZ
A20
C28
C29
A27
B27
A24
B24
A21
B21
A9
OZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
DDR EMIF Data Strobe
B9
B6
A6
B3
A3
D1
C1
A19
B19
E19
C20
D19
B20
C19
C18
B18
A18
DDRCB01
DDRCB02
DDRCB03
DDR EMIF Check Bits
DDRCB04
DDRCB05
DDRCB06
DDRCB07
Copyright 2013 Texas Instruments Incorporated
Device Overview 49
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 4 of 12)
Ball No. Type IPD/IPU Description
Signal Name
DDRD00
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
DDRD06
DDRD07
DDRD08
DDRD09
DDRD10
DDRD11
DDRD12
DDRD13
DDRD14
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD39
DDRD40
DDRD41
E28
D29
E27
D28
D27
B28
E26
F25
F24
E24
E25
D25
D26
C26
B26
A26
F23
F22
D24
E23
A23
B23
C24
E22
D21
F20
E21
F21
D22
C21
B22
C22
E10
D10
B10
D9
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
DDR EMIF Data Bus
DDR EMIF Data Bus
E9
C9
B8
E8
A7
D7
50
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 5 of 12)
Signal Name
DDRD42
DDRD43
DDRD44
DDRD45
DDRD46
DDRD47
DDRD48
DDRD49
DDRD50
DDRD51
DDRD52
DDRD53
DDRD54
DDRD55
DDRD56
DDRD57
DDRD58
DDRD59
DDRD60
DDRD61
DDRD62
DDRD63
DDRCE0
DDRCE1
DDRBA0
DDRBA1
DDRBA2
DDRA00
DDRA01
DDRA02
DDRA03
DDRA04
DDRA05
DDRA06
DDRA07
DDRA08
DDRA09
DDRA10
DDRA11
DDRA12
DDRA13
DDRA14
DDRA15
DDRCAS
Ball No. Type IPD/IPU Description
E7
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
C7
B7
E6
D6
C6
C5
A5
B4
A4
D4
DDR EMIF Data Bus
E4
C4
C3
F4
D2
E2
C2
F2
F3
E1
F1
C11
C12
A13
B13
C13
A14
B14
F14
F13
A15
C15
B15
D15
F15
E15
E16
D16
E17
C16
D17
C17
D12
DDR EMIF Chip Enables
DDR EMIF Bank Address
DDR EMIF Address Bus
DDR EMIF Column Address Strobe
Copyright 2013 Texas Instruments Incorporated
Device Overview 51
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 6 of 12)
Ball No. Type IPD/IPU Description
Signal Name
DDRRAS
C10
E12
D11
E18
A12
B12
A16
B16
D13
E13
E11
G27
H27
E14
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
I
DDR EMIF Row Address Strobe
DDR EMIF Write Enable
DDR EMIF Clock Enable
DDR EMIF Clock Enable
DDRWE
DDRCKE0
DDRCKE1
DDRCLKOUTP0
DDRCLKOUTN0
DDRCLKOUTP1
DDRCLKOUTN1
DDRODT0
DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs
DDR Reset signal
DDRODT1
DDRRESET
DDRSLRATE0
DDRSLRATE1
VREFSSTL
Down
Down
DDR Slew rate control
I
P
Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)
EMIF16
EMIFRW
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
EMIFOE
P26
P25
R27
R28
R25
R26
P24
R24
R23
T29
T28
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
I
UP
UP
UP
UP
UP
UP
EMIF16 Control Signals
EMIFWE
UP
EMIFBE0
EMIFBE1
EMIFWAIT0
EMIFWAIT1
UP
UP
Down
Down
I
52
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 7 of 12)
Signal Name
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFD00
EMIFD01
EMIFD02
EMIFD03
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
Ball No. Type IPD/IPU Description
T27
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
T24
U29
T25
U27
U28
U25
U24
V28
V29
V27
V26
EMIF16 Address
V25
V24
W28
W27
W29
W26
W25
W24
W23
Y29
Y28
U23
Y27
AB29
AA29
Y26
AA27
AB27
AA26
AA25
Y25
EMIF16 Data
AB25
AA24
Y24
AB23
AB24
AB26
AC25
Copyright 2013 Texas Instruments Incorporated
Device Overview 53
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Signal Name
Terminal Functions — Signals and Control by Function (Part 8 of 12)
Ball No. Type IPD/IPU Description
EMU
EMU00
EMU01
EMU02
EMU03
EMU04
EMU05
EMU06
EMU07
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
AC29
AC28
AC27
AC26
AD29
AD28
AD27
AE29
AE28
AF29
AE27
AF28
AG29
AD26
AG28
AG27
AJ27
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
UP
Emulation and Trace Port
AF27
AH27
General Purpose Input/Output (GPIO)
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
H25
J28
J29
J26
J25
J27
J24
K27
K28
K26
K29
L28
L29
K25
K24
L27
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
IOZ
UP
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
General Purpose Input/Output
These GPIO pins have secondary functions assigned to them as mentioned in the ‘‘Boot
Configuration Pins’’ on page 47.
54
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 9 of 12)
Signal Name
Ball No. Type IPD/IPU Description
HyperLink
MCMRXN0
U2
T2
I
MCMRXP0
I
MCMRXN1
T1
I
MCMRXP1
R1
I
Serial HyperLink Receive Data
MCMRXN2
M1
N1
P2
I
MCMRXP2
I
MCMRXN3
I
MCMRXP3
N2
M5
N5
T4
I
MCMTXN0
O
O
O
O
O
O
O
O
O
O
I
MCMTXP0
MCMTXN1
MCMTXP1
U4
R5
Serial HyperLink Transmit Data
MCMTXN2
MCMTXP2
T5
MCMTXN3
N4
P4
MCMTXP3
MCMRXFLCLK
MCMRXFLDAT
MCMTXFLCLK
MCMTXFLDAT
MCMRXPMCLK
MCMRXPMDAT
MCMTXPMCLK
MCMTXPMDAT
MCMREFCLKOUTP
MCMREFCLKOUTN
W3
W4
AA1
AA3
Y3
Down
Down
Down
Down
Down
Down
Down
Down
I
Serial HyperLink Sideband Signals
I
Y4
I
AA2
AA4
Y1
O
O
O
O
HyperLink Reference clock output for daisy chain connection
W1
I2C
SCL
AD3
AC4
IOZ
IOZ
I2C Clock
I2C Data
SDA
JTAG
TCK
TDI
N29
P27
R29
P29
P28
I
UP
JTAG Clock Input
JTAG Data Input
JTAG Data Output
JTAG Test Mode Input
JTAG Reset
I
UP
TDO
TMS
TRST
OZ
UP
I
I
UP
Down
MDIO
MDIO
G26
H26
IOZ
O
UP
MDIO Data
MDCLK
Down
MDIO Clock
Copyright 2013 Texas Instruments Incorporated
Device Overview 55
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Signal Name
Terminal Functions — Signals and Control by Function (Part 10 of 12)
Ball No. Type IPD/IPU Description
PCIe
PCIERXN0
PCIERXP0
PCIERXN1
PCIERXP1
PCIETXN0
PCIETXP0
PCIETXN1
PCIETXP1
AH7
AH8
AJ9
I
I
PCIexpress Receive Data (2 links)
I
AJ8
I
AF8
AF7
AG9
AG8
O
O
O
O
PCIexpress Transmit Data (2 links)
Serial RapidIO
RIORXN0
RIORXP0
RIORXN1
RIORXP1
RIORXN2
RIORXP2
RIORXN3
RIORXP3
RIOTXN0
RIOTXP0
RIOTXN1
RIOTXP1
RIOTXN2
RIOTXP2
RIOTXN3
RIOTXP3
AJ11
AJ12
AH10
AH11
AH14
AH13
AJ15
AJ14
AF10
AF11
AG11
AG12
AG15
AG14
AF14
AF13
I
I
Serial RapidIO Receive Data (2 links)
I
I
I
I
Serial RapidIO Receive Data (2 links)
Serial RapidIO Transmit Data (2 links)
Serial RapidIO Transmit Data (2 links)
I
I
O
O
O
O
O
O
O
O
SGMII
SGMII0RXN
SGMII0RXP
SGMII0TXN
SGMII0TXP
SGMII1RXN
SGMII1RXP
SGMII1TXN
SGMII1TXP
AJ18
AJ17
AG18
AG17
AH17
AH16
AF17
AF16
I
Ethernet MAC SGMII Receive Data
I
O
O
I
Ethernet MAC SGMII Transmit Data
Ethernet MAC SGMII Receive Data
I
O
O
Ethernet MAC SGMII Transmit Data
SmartReflex
VCNTL0
VCNTL1
VCNTL2
VCNTL3
L23
K23
J23
H23
OZ
OZ
OZ
OZ
Voltage Control Outputs to variable core power supply
56
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 11 of 12)
Signal Name
Ball No. Type IPD/IPU Description
SPI
SPI Interface Enable 0
SPISCS0
SPISCS1
SPICLK
AG1
AG2
AE1
AD2
AB1
OZ
OZ
OZ
I
UP
UP
SPI Interface Enable 1
SPI Clock
Down
Down
Down
SPIDIN
SPI Data In
SPIDOUT
OZ
SPI Data Out
Timer
TIMI0
TIMI1
TIMO0
TIMO1
L24
L26
L25
M26
I
Down
Down
Down
Down
Timer Inputs
I
OZ
OZ
Timer Outputs
TSIP
CLKA0
CLKB0
FSA0
FSB0
TR00
TR01
TR02
TR03
TR04
TR05
TR06
TR07
TX00
TX01
TX02
TX03
TX04
TX05
TX06
TX07
CLKA1
CLKB1
FSA1
FSB1
TR10
TR11
TR12
TR13
TR14
TR15
TR16
TR17
AF25
AG25
AJ26
AG26
AH26
AJ25
AD23
AD24
AC23
AH25
AC24
AE25
AE24
AD25
AJ24
AG24
AH24
AF24
AE23
AF23
AJ23
AH23
AG23
AJ22
AE22
AD21
AC21
AJ21
AH22
AJ20
AH21
AG21
I
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
TSIP0 external clock A
TSIP0 external clock B
TSIP0 frame sync A
TSIP0 frame sync B
I
I
I
I
I
I
I
TSIP0 receive data
I
I
I
I
OZ
OZ
OZ
OZ
TSIP0 transmit data
OZ
OZ
OZ
OZ
I
I
I
I
I
I
I
I
I
I
I
I
TSIP1 external clock A
TSIP1 external clock B
TSIP1 frame sync A
TSIP1 frame sync B
TSIP1 receive data
Copyright 2013 Texas Instruments Incorporated
Device Overview 57
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-26
Terminal Functions — Signals and Control by Function (Part 12 of 12)
Ball No. Type IPD/IPU Description
Signal Name
TX10
AF21
AD22
AC22
AE21
AG20
AE20
AH20
AF20
OZ
OZ
OZ
OZ
OZ
OZ
OZ
OZ
Down
Down
Down
Down
Down
Down
Down
Down
TX11
TX12
TX13
TSIP1 transmit data
UART Serial Data In
TX14
TX15
TX16
TX17
UART
UARTRXD
UARTTXD
UARTCTS
UARTRTS
AD1
AC1
AB3
AB2
I
Down
Down
Down
Down
OZ
I
UART Serial Data Out
UART Clear To Send
UART Request To Send
OZ
Reserved
RSV01
RSV02
RSV03
RSV04
RSV05
RSV06
RSV07
RSV08
RSV09
RSV10
RSV11
RSV12
RSV13
RSV14
RSV15
RSV16
RSV17
RSV20
RSV21
RSV22
RSV24
RSV25
RSV26
RSV27
RSV0A
RSV0B
End of Table 2-26
AH28
N24
N23
AH2
AJ3
IOZ
OZ
OZ
O
Down
Down
Down
Reserved - Pullup to DVDD18
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - Connect to GND
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
Reserved - leave unconnected
O
H28
G28
AH19
AF19
K22
O
O
A
A
A
J22
A
Y5
A
W5
A
W6
A
AE12
AC9
AD19
AF3
A
A
A
OZ
OZ
OZ
O
Down
Down
Down
G25
AF1
AH4
AH3
M23
M24
AA21
AA20
O
IOZ
IOZ
A
A
58
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-27
Terminal Functions — Power and Ground
Supply
AVDDA1
AVDDA2
AVDDA3
CVDD
Ball No.
H22
Volts Description
1.8
1.8
1.8
PLL Supply - CORE_PLL
AC6
PLL Supply - DDR3_PLL
AD5
PLL Supply - PASS_PLL
H7, H9, H11, H13, H15, H17, H19, H21, J10, J12, J16, J18, J20, K11, K17, K19, K21, L10, L12, L16, 0.9
L18, M11, M13, M15, M17, M19, N8, N10, N12, N14, N16, N18, P9, P11, P13, P15, P17, P19, to
SmartReflex core supply voltage
P21, R8, R10, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U18, U20, U22, V9, V11, 1.1
V17, V19, V21, W8, W10, W18, W20, W22, Y9, Y11, Y13, Y15, Y17, Y19, Y21, AA8, AA10, AA12,
AA14, AA16, AA18, AA22
CVDD1
J8, J14, K7, K9, K13, K15, L8, L14, L20, L22, M9, M21, N20, N22, R12, R14, R16, U12, U14, U16, 1.0
V13, V15, W12, W14, W16
Fixed core supply voltage for
memory array
DVDD15
DVDD18
A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19, F26, F28, 1.5
G2, G4, G8, G10, G12, G14, G16, G18, G20, G23
DDR IO supply
H24, N28, P23, T23, U26, V23, Y7, Y23, AA6, AB5, AB7, AB19, AB21, AB28, AC3, AF5, AF26,
AG22, AH1, AH29, AJ2, AJ28
1.8
IO supply
VDDR1
VDDR2
VDDR3
VDDR4
VDDT1
V5
1.5
1.5
1.5
1.5
1.0
HyperLink SerDes regulator supply
PCIe SerDes regulator supply
SGMII SerDes regulator supply
SRIO SerDes regulator supply
AE10
AE16
AE14
M7, N6, P7, R6, T7, U6, V7
HyperLink SerDes termination
supply
VDDT2
AB9, AB11, AB13, AB15, AB17, AC8, AC10, AC12, AC14, AC16, AC18, AD7, AD9, AD11, AD13, 1.0
AD15, AD17, AE18
SGMII/SRIO/PCIe SerDes
termination supply
VREFSSTL
VSS
E14
0.75 DDR3 reference voltage
A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F27, F29, G1, GND Ground
G3, G5, G6, G7, G9, G11, G13, G15, G17, G19, G21, G24, H1, H2, H3, H4, H5, H6, H8, H10, H12,
H14, H16, H18, H20, J1, J2, J3, J4, J5, J6, J7, J9, J11, J13, J15, J17, J19, J21, K1, K2, K3, K4, K5, K6,
K8, K10, K12, K14, K16, K18, K20, L1, L2, L3, L4, L5, L6, L7, L9, L11, L13, L15, L17, L19, L21, M2,
M3, M4, M6, M8, M10, M12, M14, M16, M18, M20, M22, M28, N3, N7, N9, N11, N13, N15, N17,
N19, N21, P1, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, R2, R3, R4, R7, R9, R11, R13,
R15, R17, R19, R21, T3, T6, T8, T10, T12, T14, T16, T18, T20, T22, T26, U1, U3, U5, U7, U9, U11,
U13, U15, U17, U19, U21, V1, V2, V3, V4, V6, V8, V10, V12, V14, V16, V18, V20, V22, W7, W9,
W11, W13, W15, W17, W19, W21, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20, Y22, AA5, AA7, AA9,
AA11, AA13, AA15, AA17, AA19, AA23, AA28, AB4, AB6, AB8, AB10, AB12, AB14, AB16, AB18,
AB20, AB22, AC2, AC5, AC7, AC11, AC13, AC15, AC17, AC19, AD6, AD8, AD10, AD12, AD14,
AD16, AD18, AE7, AE8, AE9, AE11, AE13, AE15, AE17, AE19, AE26, AF4, AF6, AF9, AF12, AF15,
AF18, AF22, AG7, AG10, AG13, AG16, AG19, AH6, AH9, AH12, AH15, AH18, AJ1, AJ7, AJ10,
AJ13, AJ16, AJ19, AJ29
End of Table 2-27
Copyright 2013 Texas Instruments Incorporated
Device Overview 59
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-28
Terminal Functions
— By Signal Name
(Part 2 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 3 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 1 of 12)
Signal Name
Ball Number
Signal Name
DDRCLKP
DDRD00
DDRD01
DDRD02
DDRD03
DDRD04
DDRD05
DDRD06
DDRD07
DDRD08
DDRD09
DDRD10
DDRD11
DDRD12
DDRD13
DDRD14
DDRD15
DDRD16
DDRD17
DDRD18
DDRD19
DDRD20
DDRD21
DDRD22
DDRD23
DDRD24
DDRD25
DDRD26
DDRD27
DDRD28
DDRD29
DDRD30
DDRD31
DDRD32
DDRD33
DDRD34
DDRD35
DDRD36
DDRD37
DDRD38
DDRD39
DDRD40
Ball Number
G29
E28
D29
E27
D28
D27
B28
E26
F25
F24
E24
E25
D25
D26
C26
B26
A26
F23
F22
D24
E23
A23
B23
C24
E22
D21
F20
E21
F21
D22
C21
B22
C22
E10
D10
B10
D9
Signal Name
AVDDA1
Ball Number
H22
AC6
AD5
AE2
CVDD1
J8, J14, K7, K9, K13,
K15, L8, L14, L20,
L22, M9, M21, N20,
N22, R12, R14, R16,
U12, U14, U16, V13,
V15, W12, W14,
W16
AVDDA2
AVDDA3
BOOTCOMPLETE
BOOTMODE00 †
BOOTMODE01†
BOOTMODE02 †
BOOTMODE03 †
BOOTMODE04 †
BOOTMODE05 †
BOOTMODE06 †
BOOTMODE07 †
BOOTMODE08 †
BOOTMODE09 †
BOOTMODE10 †
BOOTMODE11 †
BOOTMODE12 †
CLKA0
J28
DDRA00
A14
B14
F14
F13
A15
C15
B15
D15
F15
E15
E16
D16
E17
C16
D17
C17
A13
B13
C13
D12
E19
C20
D19
B20
C19
C18
B18
A18
C11
C12
D11
E18
H29
B12
B16
A12
A16
J29
DDRA01
J26
DDRA02
J25
DDRA03
J27
DDRA04
J24
DDRA05
K27
DDRA06
K28
DDRA07
K26
DDRA08
K29
DDRA09
L28
DDRA10
L29
DDRA11
K25
DDRA12
AF25
AJ23
AG25
AH23
AG4
AG3
AF2
DDRA13
CLKA1
DDRA14
CLKB0
DDRA15
CLKB1
DDRBA0
CORECLKN
DDRBA1
CORECLKP
DDRBA2
CORESEL0
DDRCAS
CORESEL1
AD4
AE6
DDRCB00
DDRCB01
DDRCB02
DDRCB03
DDRCB04
DDRCB05
DDRCB06
DDRCB07
DDRCE0
CORESEL2
CORESEL3
AE5
CVDD
H7, H9, H11, H13,
H15, H17, H19, H21,
J10, J12, J16, J18,
J20, K11, K17, K19,
K21, L10, L12, L16,
L18, M11, M13,
M15, M17, M19, N8,
N10, N12, N14,
CVDD
CVDD
N16, N18, P9, P11,
P13, P15, P17, P19,
P21, R8, R10, R18,
R20, R22, T9, T11,
T13, T15, T17, T19,
T21, U8, U10, U18,
U20, U22, V9, V11,
V17, V19, V21, W8,
DDRCE1
DDRCKE0
DDRCKE1
DDRCLKN
DDRCLKOUTN0
DDRCLKOUTN1
DDRCLKOUTP0
DDRCLKOUTP1
E9
C9
W10, W18, W20,
W22, Y9, Y11, Y13,
Y15, Y17, Y19, Y21,
AA8, AA10, AA12,
AA14, AA16, AA18,
AA22
B8
E8
A7
60
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-28
Terminal Functions
— By Signal Name
(Part 4 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 5 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 6 of 12)
Signal Name
DDRD41
Ball Number
D7
Signal Name
DDRDQS5N
DDRDQS5P
DDRDQS6N
DDRDQS6P
DDRDQS7N
DDRDQS7P
DDRDQS8N
DDRDQS8P
DDRODT0
DDRODT1
DDRRAS
Ball Number
A6
Signal Name
EMIFA17
EMIFA18
EMIFA19
EMIFA20
EMIFA21
EMIFA22
EMIFA23
EMIFBE0
EMIFBE1
EMIFCE0
EMIFCE1
EMIFCE2
EMIFCE3
EMIFD00
EMIFD01
EMIFD02
EMIFD03
EMIFD04
EMIFD05
EMIFD06
EMIFD07
EMIFD08
EMIFD09
EMIFD10
EMIFD11
EMIFD12
EMIFD13
EMIFD14
EMIFD15
EMIFOE
Ball Number
W26
W25
W24
W23
Y29
DDRD42
E7
B6
DDRD43
C7
A3
DDRD44
B7
B3
DDRD45
E6
C1
DDRD46
D6
D1
Y28
DDRD47
C6
B19
A19
D13
E13
C10
E11
G27
H27
E12
U23
DDRD48
C5
R24
DDRD49
A5
R23
DDRD50
B4
P25
DDRD51
A4
R27
DDRD52
D4
DDRRESET
DDRSLRATE0
DDRSLRATE1
DDRWE
R28
DDRD53
E4
R25
DDRD54
C4
Y27
DDRD55
C3
AB29
AA29
Y26
DDRD56
F4
DVDD15
A2, A11, A17, A28,
B1, B29, C14, C25,
D5, D8, D20, D23,
E3, F5, F7, F9, F11,
F17, F19, F26, F28,
G2, G4, G8, G10,
G12, G14, G16, G18,
G20, G23
DDRD57
D2
DDRD58
E2
AA27
AB27
AA26
AA25
Y25
DDRD59
C2
DDRD60
F2
DDRD61
F3
DVDD18
H24, N28, P23, T23,
U26, V23, Y7, Y23,
AA6, AB5, AB7,
AB19, AB21, AB28,
AC3, AF5, AF26,
AG22, AH1, AH29,
AJ2, AJ28
DDRD62
E1
DDRD63
F1
AB25
AA24
Y24
DDRDQM0
DDRDQM1
DDRDQM2
DDRDQM3
DDRDQM4
DDRDQM5
DDRDQM6
DDRDQM7
DDRDQM8
DDRDQS0N
DDRDQS0P
DDRDQS1N
DDRDQS1P
DDRDQS2N
DDRDQS2P
DDRDQS3N
DDRDQS3P
DDRDQS4N
DDRDQS4P
E29
C27
A25
A22
A10
A8
AB23
AB24
AB26
AC25
R26
EMIFA00
EMIFA01
EMIFA02
EMIFA03
EMIFA04
EMIFA05
EMIFA06
EMIFA07
EMIFA08
EMIFA09
EMIFA10
EMIFA11
EMIFA12
EMIFA13
EMIFA14
EMIFA15
EMIFA16
T27
T24
U29
T25
U27
U28
U25
U24
V28
V29
V27
V26
V25
V24
W28
W27
W29
B5
B2
EMIFRW
EMIFWAIT0
EMIFWAIT1
EMIFWE
EMU00
P26
A20
C29
C28
B27
A27
B24
A24
B21
A21
B9
T29
T28
P24
AC29
AC28
AC27
AC26
AD29
AD28
AD27
AE29
EMU01
EMU02
EMU03
EMU04
EMU05
EMU06
A9
EMU07
Copyright 2013 Texas Instruments Incorporated
Device Overview 61
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-28
Terminal Functions
— By Signal Name
(Part 7 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 8 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 9 of 12)
Signal Name
EMU08
EMU09
EMU10
EMU11
EMU12
EMU13
EMU14
EMU15
EMU16
EMU17
EMU18
FSA0
Ball Number
AE28
AF29
AE27
AF28
AG29
AD26
AG28
AG27
AJ27
AF27
AH27
AJ26
AG23
AG26
AJ22
H25
Signal Name
MCMRXN1
MCMRXN2
MCMRXN3
MCMRXP0
MCMRXP1
MCMRXP2
MCMRXP3
MCMRXPMCLK
MCMRXPMDAT
MCMTXFLCLK
MCMTXFLDAT
MCMTXN0
MCMTXN1
MCMTXN2
MCMTXN3
MCMTXP0
MCMTXP1
MCMTXP2
MCMTXP3
MCMTXPMCLK
MCMTXPMDAT
MDCLK
Ball Number
T1
Signal Name
RESETFULL
RESETSTAT
RESET
Ball Number
N25
M1
N27
P2
M29
AJ11
AH10
AH14
AJ15
AJ12
AH11
AH13
AJ14
AF10
AG11
AG15
AF14
AF11
AG12
AG14
AF13
AH28
N24
T2
RIORXN0
RIORXN1
RIORXN2
RIORXN3
RIORXP0
RIORXP1
RIORXP2
RIORXP3
RIOTXN0
RIOTXN1
RIOTXN2
RIOTXN3
RIOTXP0
RIOTXP1
RIOTXP2
RIOTXP3
RSV01
R1
N1
N2
Y3
Y4
AA1
AA3
M5
FSA1
T4
FSB0
R5
FSB1
N4
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
HOUT
N5
J28
U4
J29
T5
J26
P4
J25
AA2
AA4
H26
G26
M25
AE4
AJ4
AJ5
AH5
AG5
AH7
AJ9
AH8
AJ8
K24
L27
L24
AF8
AG9
AF7
AG8
AC20
G22
J27
RSV02
J24
RSV03
N23
K27
MDIO
RSV04
AH2
K28
NMI
RSV05
AJ3
K26
PACLKSEL
PASSCLKN
PASSCLKP
PCIECLKN
PCIECLKP
RSV06
H28
K29
RSV07
G28
L28
RSV08
AH19
AF19
AA21
AA20
K22
L29
RSV09
K25
RSV0A
K24
PCIERXN0
PCIERXN1
PCIERXP0
RSV0B
L27
RSV10
AD20
H25
RSV11
J22
LENDIAN †
LRESETNMIEN
LRESET
MCMCLKN
MCMCLKP
PCIERXP1
RSV12
Y5
M27
N26
PCIESSMODE0 †
PCIESSMODE1 †
PCIESSEN †
PCIETXN0
PCIETXN1
PCIETXP0
RSV13
W5
RSV14
W6
Y2
RSV15
AE12
AC9
W2
RSV16
MCMREFCLKOUTN
MCMREFCLKOUTP
MCMRXFLCLK
MCMRXFLDAT
MCMRXN0
W1
Y1
RSV17
AD19
AF3
RSV20
W3
W4
U2
PCIETXP1
RSV21
G25
POR
RSV22
AF1
PTV15
RSV24
AH4
62
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-28
Terminal Functions
— By Signal Name
(Part 10 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 11 of 12)
Table 2-28
Terminal Functions
— By Signal Name
(Part 12 of 12)
Signal Name
RSV25
Ball Number
AH3
Signal Name
TR17
Ball Number
AG21
P28
Signal Name
Ball Number
VSS
H1, H2, H3, H4, H5,
H6, H8, H10, H12,
H14, H16, H18, H20,
J1, J2, J3, J4, J5, J6,
J7, J9, J11, J13, J15,
J17, J19, J21, K1, K2,
K3, K4, K5, K6, K8,
K10, K12, K14, K16,
SCL
AD3
TRST
SDA
AC4
TX00
AE24
AD25
AJ24
AG24
AH24
AF24
AE23
AF23
AF21
AD22
AC22
AE21
AG20
AE20
AH20
AF20
AB3
SGMII0RXN
SGMII0RXP
SGMII0TXN
SGMII0TXP
SGMII1RXN
SGMII1RXP
SGMII1TXN
SGMII1TXP
SPICLK
SPIDIN
SPIDOUT
SPISCS0
SPISCS1
SRIOSGMIICLKN
SRIOSGMIICLKP
SYSCLKOUT
TCK
AJ18
AJ17
AG18
AG17
AH17
AH16
AF17
AF16
AE1
TX01
TX02
TX03
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K18, K20, L1, L2, L3,
L4, L5, L6, L7, L9,
L11, L13, L15, L17,
L19, L21, M2, M3,
M4, M6, M8, M10,
M12, M14, M16,
M18, M20, M22,
M28, N3, N7, N9,
TX04
TX05
TX06
TX07
TX10
TX11
N11, N13, N15, N17,
N19, N21, P1, P3,
P5, P6, P8, P10, P12,
P14, P16, P18, P20,
P22, R2, R3, R4, R7,
R9, R11, R13, R15,
R17, R19, R21, T3,
T6, T8, T10, T12,
AD2
TX12
AB1
TX13
AG1
TX14
AG2
TX15
AJ6
TX16
T14, T16, T18, T20,
T22, T26, U1, U3,
U5, U7, U9, U11,
U13, U15, U17, U19,
U21, V1, V2, V3, V4,
V6, V8, V10, V12,
V14, V16, V18, V20,
V22, W7, W9, W11,
AG6
TX17
AE3
UARTCTS
UARTRTS
UARTRXD
UARTTXD
VCNTL0
VCNTL1
VCNTL2
VCNTL3
VDDR1
VDDR2
VDDR3
VDDR4
VDDT1
N29
AB2
TDI
P27
AD1
TDO
R29
AC1
TIMI0
L24
L23
W13, W15, W17,
W19, W21, Y6, Y8,
Y10, Y12, Y14, Y16,
Y18, Y20, Y22, AA5,
AA7, AA9, AA11,
AA13, AA15, AA17,
AA19, AA23, AA28,
AB4, AB6, AB8,
TIMI1
L26
K23
TIMO0
L25
J23
TIMO1
M26
H23
TMS
P29
V5
TR00
AH26
AJ25
AD23
AD24
AC23
AH25
AC24
AE25
AE22
AD21
AC21
AJ21
AH22
AJ20
AH21
AE10
AE16
AE14
AB10, AB12, AB14,
AB16, AB18, AB20,
AB22, AC2, AC5,
AC7, AC11, AC13,
AC15, AC17, AC19,
AD6, AD8, AD10,
AD12, AD14, AD16,
AD18, AE7, AE8,
TR01
TR02
TR03
M7, N6, P7, R6, T7,
U6, V7
TR04
VDDT2
AB9, AB11, AB13,
AB15, AB17, AC8,
AC10, AC12, AC14,
AC16, AC18, AD7,
AD9, AD11, AD13,
AD15, AD17, AE18
TR05
TR06
AE9, AE11, AE13,
AE15, AE17, AE19,
AE26, AF4, AF6,
AF9, AF12, AF15,
AF18, AF22AG7,
AG10, AG13, AG16,
AG19, AH6, AH9,
AH12, AH15, AH18,
TR07
TR10
VREFSSTL
VSS
E14
TR11
A1, A29, B11, B17,
B25, C8, C23, D3,
D14, D18, E5, E20,
F6, F8, F10, F12,
F16, F18, F27, F29,
G1, G3, G5, G6, G7,
G9, G11, G13, G15,
G17, G19, G21, G24,
TR12
TR13
AJ1, AJ7, AJ10,
AJ13, AJ16, AJ19,
AJ29
TR14
TR15
TR16
End of Table 2-28
Copyright 2013 Texas Instruments Incorporated
Device Overview 63
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 2 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 3 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 1 of 21)
Ball Number
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
C1
Signal Name
DDRA01
DDRA06
DDRCLKOUTN1
VSS
Ball Number
C27
C28
C29
D1
Signal Name
DDRDQM1
DDRDQS0P
DDRDQS0N
DDRDQS7P
DDRD57
VSS
Ball Number
A1
Signal Name
VSS
A2
DVDD15
A3
DDRDQS6N
DDRD51
A4
DDRCB06
DDRDQS8N
DDRCB03
DDRDQS3N
DDRD30
DDRD21
DDRDQS2N
VSS
D2
A5
DDRD49
D3
A6
DDRDQS5N
DDRD40
D4
DDRD52
DVDD15
DDRD46
DDRD41
DVDD15
DDRD35
DDRD33
DDRCKE0
DDRCAS
DDRODT0
VSS
A7
D5
A8
DDRDQM5
DDRDQS4P
DDRDQM4
DVDD15
D6
A9
D7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
B1
D8
D9
DDRCLKOUTP0
DDRBA0
DDRD14
DDRDQS1N
DDRD05
DVDD15
DDRDQS7N
DDRD59
DDRD55
DDRD54
DDRD48
DDRD47
DDRD43
VSS
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
E1
DDRA00
DDRA04
DDRCLKOUTP1
DVDD15
C2
DDRA07
DDRA11
DDRA14
VSS
DDRCB07
DDRDQS8P
DDRDQM8
DDRDQS3P
DDRDQM3
DDRD20
C3
C4
C5
C6
DDRCB02
DVDD15
DDRD24
DDRD28
DVDD15
DDRD18
DDRD11
DDRD12
DDRD04
DDRD03
DDRD01
DDRD62
DDRD58
DVDD15
DDRD53
VSS
C7
C8
DDRDQS2P
DDRDQM2
DDRD15
C9
DDRD37
DDRRAS
DDRCE0
DDRCE1
DDRBA2
DVDD15
DDRA05
DDRA13
DDRA15
DDRCB05
DDRCB04
DDRCB01
DDRD29
DDRD31
VSS
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
DDRDQS1P
DVDD15
VSS
DVDD15
B2
DDRDQM7
DDRDQS6P
DDRD50
B3
B4
E2
B5
DDRDQM6
DDRDQS5P
DDRD44
E3
B6
E4
B7
E5
B8
DDRD38
E6
DDRD45
DDRD42
DDRD39
DDRD36
DDRD32
B9
DDRDQS4N
DDRD34
E7
B10
B11
B12
B13
DDRD22
DVDD15
DDRD13
E8
VSS
E9
DDRCLKOUTN0
DDRBA1
E10
64
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 4 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 5 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 6 of 21)
Ball Number
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
F1
Signal Name
DDRRESET
DDRWE
DDRODT1
VREFSSTL
DDRA09
DDRA10
DDRA12
DDRCKE1
DDRCB00
VSS
Ball Number
F24
F25
F26
F27
F28
F29
G1
Signal Name
DDRD08
DDRD07
DVDD15
VSS
Ball Number
H8
Signal Name
VSS
H9
CVDD
VSS
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H25
H26
H27
H28
H29
J1
CVDD
VSS
DVDD15
VSS
CVDD
VSS
VSS
G2
DVDD15
VSS
CVDD
VSS
G3
G4
DVDD15
VSS
CVDD
VSS
DDRD26
DDRD23
DDRD19
DDRD09
DDRD10
DDRD06
DDRD02
DDRD00
DDRDQM0
DDRD63
DDRD60
DDRD61
DDRD56
DVDD15
VSS
G5
G6
VSS
CVDD
VSS
G7
VSS
G8
DVDD15
VSS
CVDD
AVDDA1
VCNTL3
DVDD18
GPIO00
LENDIAN †
MDCLK
DDRSLRATE1
RSV06
DDRCLKN
VSS
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
H1
DVDD15
VSS
DVDD15
VSS
DVDD15
VSS
F2
F3
DVDD15
VSS
F4
F5
DVDD15
VSS
F6
J2
VSS
F7
DVDD15
VSS
DVDD15
VSS
J3
VSS
F8
J4
VSS
F9
DVDD15
VSS
PTV15
DVDD15
VSS
J5
VSS
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
J6
VSS
DVDD15
VSS
J7
VSS
RSV21
MDIO
DDRSLRATE0
RSV07
DDRCLKP
VSS
J8
CVDD1
VSS
DDRA03
DDRA02
DDRA08
VSS
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
CVDD
VSS
CVDD
VSS
DVDD15
VSS
H2
VSS
CVDD1
VSS
DVDD15
DDRD25
DDRD27
DDRD17
DDRD16
H3
VSS
H4
VSS
CVDD
VSS
H5
VSS
H6
VSS
CVDD
VSS
H7
CVDD
Copyright 2013 Texas Instruments Incorporated
Device Overview 65
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 7 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 8 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 9 of 21)
Ball Number
J20
J21
J22
J23
J24
J24
J25
J25
J26
J26
J27
J27
J28
J28
J29
J29
K1
Signal Name
CVDD
Ball Number
K25
K26
K26
K27
K27
K28
K28
K29
K29
L1
Signal Name
BOOTMODE12 †
GPIO09
BOOTMODE08 †
GPIO07
BOOTMODE06 †
GPIO08
BOOTMODE07 †
GPIO10
BOOTMODE09 †
VSS
Ball Number
M1
Signal Name
MCMRXN2
VSS
VSS
M2
RSV11
M3
VSS
VCNTL2
GPIO06
BOOTMODE05 †
GPIO04
BOOTMODE03 †
GPIO03
BOOTMODE02 †
GPIO05
BOOTMODE04 †
GPIO01
BOOTMODE00 †
GPIO02
BOOTMODE01†
VSS
M4
VSS
M5
MCMTXN0
VSS
M6
M7
VDDT1
VSS
M8
M9
CVDD1
VSS
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M25
M26
M27
M28
M29
N1
L2
VSS
CVDD
VSS
L3
VSS
L4
VSS
CVDD
VSS
L5
VSS
L6
VSS
CVDD
VSS
L7
VSS
L8
CVDD1
VSS
CVDD
VSS
K2
VSS
L9
K3
VSS
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L24
L25
L26
L27
L27
L28
L28
L29
L29
CVDD
CVDD
VSS
K4
VSS
VSS
K5
VSS
CVDD
CVDD1
VSS
K6
VSS
VSS
K7
CVDD1
VSS
CVDD1
VSS
NMI
K8
TIMO1
LRESETNMIEN
VSS
K9
CVDD1
VSS
CVDD
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K24
K25
VSS
CVDD
CVDD
RESET
MCMRXP2
MCMRXP3
VSS
VSS
VSS
CVDD1
VSS
CVDD1
VSS
N2
N3
CVDD1
VSS
CVDD1
VCNTL0
TIMI0
N4
MCMTXN3
MCMTXP0
VDDT1
VSS
N5
CVDD
N6
VSS
PCIESSEN †
TIMO0
N7
CVDD
N8
CVDD
VSS
VSS
TIMI1
N9
CVDD
GPIO15
PCIESSMODE1 †
GPIO11
BOOTMODE10 †
GPIO12
BOOTMODE11 †
N10
N11
N12
N13
N14
N15
CVDD
VSS
RSV10
VCNTL1
GPIO14
PCIESSMODE0 †
GPIO13
CVDD
VSS
CVDD
VSS
66
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 10 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 11 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 12 of 21)
Ball Number
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
P1
Signal Name
CVDD
VSS
Ball Number
P29
R1
Signal Name
TMS
Ball Number
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
U1
Signal Name
CVDD
VSS
MCMRXP1
VSS
CVDD
VSS
R2
CVDD
VSS
R3
VSS
CVDD1
VSS
R4
VSS
CVDD
VSS
R5
MCMTXN2
VDDT1
VSS
CVDD1
RSV03
RSV02
RESETFULL
LRESET
RESETSTAT
DVDD18
TCK
R6
CVDD
VSS
R7
R8
CVDD
VSS
CVDD
VSS
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
T1
CVDD
VSS
DVDD18
EMIFA01
EMIFA03
VSS
CVDD1
VSS
VSS
CVDD1
VSS
EMIFA00
EMIFWAIT1
EMIFWAIT0
VSS
P2
MCMRXN3
VSS
P3
CVDD1
VSS
P4
MCMTXP3
VSS
P5
CVDD
VSS
U2
MCMRXN0
VSS
P6
VSS
U3
P7
VDDT1
VSS
CVDD
VSS
U4
MCMTXP1
VSS
P8
U5
P9
CVDD
VSS
CVDD
EMIFBE1
EMIFBE0
EMIFCE3
EMIFOE
EMIFCE1
EMIFCE2
TDO
U6
VDDT1
VSS
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
U7
CVDD
VSS
U8
CVDD
VSS
U9
CVDD
VSS
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
CVDD
VSS
CVDD
VSS
CVDD1
VSS
CVDD
VSS
MCMRXN1
MCMRXP0
VSS
CVDD1
VSS
T2
CVDD
VSS
T3
CVDD1
VSS
T4
MCMTXN1
MCMTXP2
VSS
CVDD
VSS
T5
CVDD
VSS
T6
DVDD18
EMIFWE
EMIFCE0
EMIFRW
TDI
T7
VDDT1
VSS
CVDD
VSS
T8
T9
CVDD
VSS
CVDD
EMIFA23
EMIFA07
EMIFA06
T10
T11
T12
CVDD
VSS
TRST
Copyright 2013 Texas Instruments Incorporated
Device Overview 67
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 13 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 14 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 15 of 21)
Ball Number
U26
U27
U28
U29
V1
Signal Name
DVDD18
EMIFA04
EMIFA05
EMIFA02
VSS
Ball Number
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
Y1
Signal Name
CVDD
Ball Number
Y23
Signal Name
DVDD18
EMIFD11
EMIFD08
EMIFD03
EMIFD00
EMIFA22
EMIFA21
MCMTXFLCLK
MCMTXPMCLK
MCMTXFLDAT
MCMTXPMDAT
VSS
VSS
Y24
CVDD1
VSS
Y25
Y26
CVDD1
VSS
Y27
V2
VSS
Y28
V3
VSS
CVDD1
VSS
Y29
V4
VSS
AA1
V5
VDDR1
VSS
CVDD
AA2
V6
VSS
AA3
V7
VDDT1
VSS
CVDD
AA4
V8
VSS
AA5
V9
CVDD
CVDD
AA6
DVDD18
VSS
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
W1
VSS
EMIFA20
EMIFA19
EMIFA18
EMIFA17
EMIFA15
EMIFA14
EMIFA16
MCMREFCLKOUTP
MCMCLKN
MCMRXPMCLK
MCMRXPMDAT
RSV12
VSS
AA7
CVDD
AA8
CVDD
VSS
AA9
VSS
CVDD1
VSS
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AB1
CVDD
VSS
CVDD1
VSS
CVDD
VSS
CVDD
CVDD
VSS
Y2
VSS
CVDD
Y3
CVDD
VSS
Y4
VSS
CVDD
Y5
CVDD
VSS
Y6
VSS
DVDD18
EMIFA13
EMIFA12
EMIFA11
EMIFA10
EMIFA08
EMIFA09
MCMREFCLKOUTN
MCMCLKP
MCMRXFLCLK
MCMRXFLDAT
RSV13
Y7
DVDD18
VSS
RSV0B
Y8
RSV0A
Y9
CVDD
CVDD
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
VSS
VSS
CVDD
EMIFD10
EMIFD07
EMIFD06
EMIFD04
VSS
VSS
CVDD
VSS
W2
CVDD
W3
VSS
EMIFD02
SPIDOUT
UARTRTS
UARTCTS
VSS
W4
CVDD
W5
VSS
AB2
W6
RSV14
CVDD
AB3
W7
VSS
VSS
AB4
W8
CVDD
CVDD
AB5
DVDD18
VSS
W9
VSS
VSS
AB6
68
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 16 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 17 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 18 of 21)
Ball Number
AB7
Signal Name
DVDD18
VSS
Ball Number
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
AC28
AC29
AD1
Signal Name
POR
Ball Number
AE4
Signal Name
PACLKSEL
CORESEL3
CORESEL2
VSS
AB8
TR12
AE5
AB9
VDDT2
VSS
TX12
AE6
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AC1
TR04
AE7
VDDT2
VSS
TR06
AE8
VSS
EMIFD15
EMU03
EMU02
EMU01
EMU00
UARTRXD
SPIDIN
SCL
AE9
VSS
VDDT2
VSS
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AF1
VDDR2
VSS
VDDT2
VSS
RSV15
VSS
VDDT2
VSS
VDDR4
VSS
AD2
DVDD18
VSS
AD3
VDDR3
VSS
AD4
CORESEL1
AVDDA3
VSS
DVDD18
VSS
AD5
VDDT2
VSS
AD6
EMIFD12
EMIFD13
EMIFD09
EMIFD14
EMIFD05
DVDD18
EMIFD01
UARTTXD
VSS
AD7
VDDT2
VSS
TX15
AD8
TX13
AD9
VDDT2
VSS
TR10
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AE1
TX06
VDDT2
VSS
TX00
TR07
VDDT2
VSS
VSS
EMU10
EMU08
EMU07
RSV22
CORESEL0
RSV20
VSS
AC2
VDDT2
VSS
AC3
DVDD18
SDA
AC4
VDDT2
VSS
AC5
VSS
AF2
AC6
AVDDA2
VSS
RSV17
HOUT
AF3
AC7
AF4
AC8
VDDT2
RSV16
VDDT2
VSS
TR11
AF5
DVDD18
VSS
AC9
TX11
AF6
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
TR02
AF7
PCIETXP0
PCIETXN0
VSS
TR03
AF8
VDDT2
VSS
TX01
AF9
EMU13
EMU06
EMU05
EMU04
SPICLK
BOOTCOMPLETE
SYSCLKOUT
AF10
AF11
AF12
AF13
AF14
AF15
AF16
RIOTXN0
RIOTXP0
VSS
VDDT2
VSS
VDDT2
VSS
RIOTXP3
RIOTXN3
VSS
VDDT2
VSS
AE2
AE3
SGMII1TXP
Copyright 2013 Texas Instruments Incorporated
Device Overview 69
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 2-29
Terminal Functions
— By Ball Number
(Part 19 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 20 of 21)
Table 2-29
Terminal Functions
— By Ball Number
(Part 21 of 21)
Ball Number
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AG1
Signal Name
SGMII1TXN
VSS
Ball Number
AH1
Signal Name
DVDD18
RSV04
Ball Number
AJ14
Signal Name
RIORXP3
RIORXN3
VSS
AH2
AJ15
RSV09
AH3
RSV25
AJ16
TX17
AH4
RSV24
AJ17
SGMII0RXP
SGMII0RXN
VSS
TX10
AH5
PCIECLKN
VSS
AJ18
VSS
AH6
AJ19
TX07
AH7
PCIERXN0
PCIERXP0
VSS
AJ20
TR15
TX05
AH8
AJ21
TR13
CLKA0
AH9
AJ22
FSB1
DVDD18
EMU17
EMU11
EMU09
SPISCS0
SPISCS1
CORECLKP
CORECLKN
PCIECLKP
SRIOSGMIICLKP
VSS
AH10
AH11
AH12
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AH29
AJ1
RIORXN1
RIORXP1
VSS
AJ23
CLKA1
TX02
AJ24
AJ25
TR01
RIORXP2
RIORXN2
VSS
AJ26
FSA0
AJ27
EMU16
DVDD18
VSS
AG2
AJ28
AG3
SGMII1RXP
SGMII1RXN
VSS
AJ29
AG4
End of Table 2-29
AG5
AG6
RSV08
AG7
TX16
AG8
PCIETXP1
PCIETXN1
VSS
TR16
AG9
TR14
AG10
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG27
AG28
AG29
CLKB1
RIOTXN1
RIOTXP1
VSS
TX04
TR05
TR00
RIOTXP2
RIOTXN2
VSS
EMU18
RSV01
DVDD18
VSS
SGMII0TXP
SGMII0TXN
VSS
AJ2
DVDD18
RSV05
AJ3
TX14
AJ4
PASSCLKN
PASSCLKP
SRIOSGMIICLKN
VSS
TR17
AJ5
DVDD18
FSA1
AJ6
AJ7
TX03
AJ8
PCIERXP1
PCIERXN1
VSS
CLKB0
AJ9
FSB0
AJ10
AJ11
AJ12
AJ13
EMU15
EMU14
EMU12
RIORXN0
RIORXP0
VSS
70
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.9 Development and Support
2.9.1 Development Support
In case the customer would like to develop their own features and software on the C6678 device, TI offers an
extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of C6000™ DSP-based applications:
•
Software Development Tools:
–
Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly
Code Generation, and Debug plus additional development tools.
–
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
•
Hardware Development Tools:
–
–
Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
EVM (Evaluation Module)
2.9.2 Device Support
2.9.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices
and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g.,
TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
•
•
TMX: Experimental device that is not necessarily representative of the final device's electrical specifications
TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification
•
TMS: Fully qualified production device
Support tool development evolutionary flow:
•
TMDX: Development-support product that has not yet completed Texas Instruments internal qualification
testing.
•
TMDS: Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
Copyright 2013 Texas Instruments Incorporated
Device Overview 71
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for
example, CYP), the temperature range (for example, blank is the default case temperature range), and the device
speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).
For device part numbers and further ordering information for TMS320C6678 in the CYP package type, see the TI
website www.ti.com or contact your TI sales representative.
Figure 2-17 provides a legend for reading the complete device name for any C66x KeyStone device.
Figure 2-17
C66x DSP Device Nomenclature (including the TMS320C6678)
TMS 320 ( ) ( ) ( ) ( )
C6678
CYP
PREFIX
TMX = Experimental device
TMS = Qualified device
DEVICE SPEED RANGE
Blank = 1 GHz
25 = 1.25 GHz
DEVICE FAMILY
320 = TMS320 DSP family
TEMPERATURE RANGE
Blank = 0°C to +85°C (default case temperature)
A = Extended temperature range
(-40°C to +100°C)
DEVICE
C66x DSP: C6678
PACKAGE TYPE
CYP = 841-pin plastic ball grid array,
with Pb-free solder balls
SILICON REVISION
Blank = Initial Silicon 1.0
A = Silicon Revision 2.0
ENCRYPTION
Blank = Encryption NOT enabled
X = Encryption enabled
72
Device Overview
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
2.10 Related Documentation from Texas Instruments
These documents describe the TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor. Copies
of these documents are available on the Internet at www.ti.com
64-bit Timer (Timer 64) for KeyStone Devices User Guide
Bootloader for the C66x DSP User Guide
SPRUGV5
SPRUGY5
SPRUGW0
SPRUGH7
SPRUGY8
SPRABI1
C66x CorePac User Guide
C66x CPU and Instruction Set Reference Guide
C66x DSP Cache User Guide
DDR3 Design Guide for KeyStone Devices
DDR3 Memory Controller for KeyStone Devices User Guide
DSP Power Consumption Summary for KeyStone Devices
Embedded Trace for KeyStone Devices User Guide
SPRUGV8
SPRABL4
SPRUGZ2
SPRU655
SPRUGS5
SPRUGZ3
SPRUGV1
SPRUGV9
SPRABI2
Emulation and Trace Headers Technical Reference
Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide
External Memory Interface (EMIF16) for KeyStone Devices User Guide
General Purpose Input/Output (GPIO) for KeyStone Devices User Guide
Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide
Hardware Design Guide for KeyStone Devices
HyperLink for KeyStone Devices User Guide
SPRUGW8
SPRUGV3
SPRUGW4
SPRUGW5
SPRUGR9
SPRUGW7
SPRUGZ6
SPRUGS4
SPRUGS6
SPRUGV2
SPRUGV4
SPRUGY6
SPRUGS3
SPRUGP2
SPRUGW1
SPRUGY4
SPRUGP1
SPRA387
SPRA753
SPRA839
Inter Integrated Circuit (I2C) for KeyStone Devices User Guide
Chip Interrupt Controller (CIC) for KeyStone Devices User Guide
Memory Protection Unit (MPU) for KeyStone Devices User Guide
Multicore Navigator for KeyStone Devices User Guide
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide
Network Coprocessor (NETCP) for KeyStone Devices User Guide
Packet Accelerator (PA) for KeyStone Devices User Guide
Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide
Phase Locked Loop (PLL) for KeyStone Devices User Guide
Power Sleep Controller (PSC) for KeyStone Devices User Guide
Security Accelerator (SA) for KeyStone Devices User Guide
Semaphore2 Hardware Module for KeyStone Devices User Guide
Serial Peripheral Interface (SPI) for KeyStone Devices User Guide
Serial RapidIO (SRIO) for KeyStone Devices User Guide
Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs
Using IBIS Models for Timing Analysis
Copyright 2013 Texas Instruments Incorporated
Device Overview 73
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3 Device Configuration
On the TMS320C6678 device, certain device configurations like boot mode and endianess, are selected at device
power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.
3.1 Device Configuration at Device Reset
Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device
configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors
or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The device
configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid
contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a
control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP
can be taken out of reset.
Also, please note that most of the device configuration pins are shared with other function pins
(LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and PCIESSEN/TIMI0),
some time must be given following the rising edge of reset in order to drive these device configuration input pins
before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that
needs to be noted is that systems using TIMI0 (pin shared with PCIESSEN) as a clock input must assure that the
clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.
Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal
pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external
pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in
which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on
page 97.
Table 3-1
TMS320C6678 Device Configuration Pins
(1)
Configuration Pin
Pin No.
IPD/IPU
Functional Description
LENDIAN(1) (2)
H25
IPU
Device endian mode (LENDIAN).
0 = Device operates in big endian mode
1 = Device operates in little endian mode
BOOTMODE[12:0] (1) (2)
PCIESSMODE[1:0] (1) (2)
J28, J29, J26, J25,
J27, J24, K27, K28,
K26, K29, L28, L29,
K25
IPD
IPD
Method of boot.
Some pins may not be used by bootloader and can be used as general purpose config
pins. Refer to the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from
Texas Instruments’’ on page 73 for how to determine the device enumeration ID value.
L27, K24
PCIe Subsystem mode selection.
00 = PCIe in end point mode
01 = PCIe legacy end point (support for legacy INTx)
10 = PCIe in root complex mode
11 = Reserved
PCIESSEN (1) (2)
PACLKSEL(1)
L24
AE4
IPD
IPD
PCIe subsystem enable/disable.
0 = PCIE Subsystem is disabled
1 = PCIE Subsystem is enabled
Network Coprocessor (PASS PLL) input clock select.
0 = CORECLK is used as the input to PASS PLL
1 = PASSCLK is used as the input to PASS PLL
End of Table 3-1
1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-k resistor can be used to oppose the IPD/IPU. For more detailed information on
pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 97.
2 These signal names are the secondary functions of these pins.
74
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.2 Peripheral Selection After Device Reset
Several of the peripherals on the TMS320C6678 are controlled by the Power Sleep Controller (PSC). By default, the
PCIe, SRIO, and HyperLink are held in reset and clock-gated. The memories in these modules are also in a
low-leakage sleep mode. Software is required to turn these memories on. The software enables the modules (turns
on clocks and de-asserts reset) before these modules can be used.
If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.
All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
3.3 Device State Control Registers
The TMS320C6678 device has a set of registers that are used to provide the status or configure certain parts of its
peripherals. These registers are shown in Table 3-2.
Table 3-2
Device State Control Registers (Part 1 of 4)
Address Start
0x02620000
0x02620008
0x02620018
0x0262001C
0x02620020
0x02620024
0x02620038
0x0262003C
0x02620040
0x02620044
0x02620048
0x0262004C
0x02620050
0x02620054
0x02620058
0x0262005C
0x02620060
0x026200E0
0x02620110
Address End
0x02620007
0x02620017
0x0262001B
0x0262001F
0x02620023
0x02620037
0x0262003B
0x0262003F
0x02620043
0x02620047
0x0262004B
0x0262004F
0x02620053
0x02620057
0x0262005B
0x0262005F
0x026200DF
0x0262010F
0x02620117
Size
8B
16B
4B
Field
Description
Reserved
Reserved
JTAGID
See section 3.3.3
See section 3.3.1
See section 3.3.4
4B
4B
Reserved
DEVSTAT
20B
4B
Reserved
KICK0
4B
4B
4B
4B
4B
4B
4B
4B
4B
KICK1
DSP_BOOT_ADDR0
DSP_BOOT_ADDR1
DSP_BOOT_ADDR2
DSP_BOOT_ADDR3
DSP_BOOT_ADDR4
DSP_BOOT_ADDR5
DSP_BOOT_ADDR6
DSP_BOOT_ADDR7
The boot address for C66x DSP CorePac0, see section 3.3.5
The boot address for C66x DSP CorePac1, see section 3.3.5
The boot address for C66x DSP CorePac2, see section 3.3.5
The boot address for C66x DSP CorePac3, see section 3.3.5
The boot address for C66x DSP CorePac4, see section 3.3.5
The boot address for C66x DSP CorePac5, see section 3.3.5
The boot address for C66x DSP CorePac6, see section 3.3.5
The boot address for C66x DSP CorePac7, see section 3.3.5
128B Reserved
48B
8B
Reserved
MACID
See section 7.21 ‘‘Gigabit Ethernet (GbE) Switch Subsystem’’ on
page 223
0x02620118
0x02620130
0x02620134
0x02620138
0x0262013C
0x02620140
0x02620144
0x02620148
0x0262014C
0x0262012F
0x02620133
0x02620137
0x0262013B
0x0262013F
0x02620143
0x02620147
0x0262014B
0x0262014F
24B
4B
4B
4B
4B
4B
4B
4B
4B
Reserved
LRSTNMIPINSTAT_CLR
RESET_STAT_CLR
Reserved
See section 3.3.7
See section 3.3.9
BOOTCOMPLETE
Reserved
See section 3.3.10
RESET_STAT
See section 3.3.8
See section 3.3.6
See section 3.3.2
LRSTNMIPINSTAT
DEVCFG
Copyright 2013 Texas Instruments Incorporated
Device Configuration 75
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-2
Device State Control Registers (Part 2 of 4)
Address Start
0x02620150
0x02620154
0x02620158
0x0262015C
0x02620160
0x02620164
0x02620168
0x0262016C
0x02620180
0x02620184
0x02620190
0x02620194
0x02620198
0x0262019C
0x026201A0
0x026201A4
0x026201A8
0x026201AC
0x026201B0
0x026201B4
0x026201B8
0x026201BC
0x026201C0
0x026201C4
0x026201C8
0x026201CC
0x026201D0
0x02620200
0x02620204
0x02620208
0x0262020C
0x02620210
0x02620214
0x02620218
0x0262021C
0x02620220
0x02620240
0x02620244
0x02620248
0x0262024C
0x02620250
0x02620254
0x02620258
0x0262025C
Address End
0x02620153
0x02620157
0x0262015B
0x0262015F
0x02620163
0x02620167
0x0262016B
0x0262017F
0x02620183
0x0262018F
0x02620193
0x02620197
0x0262019B
0x0262019F
0x026201A3
0x026201A7
0x026201AB
0x026201AF
0x026201B3
0x026201B7
0x026201BB
0x026201BF
0x026201C3
0x026201C7
0x026201CB
0x026201CF
0x026201FF
0x02620203
0x02620207
0x0262020B
0x0262020F
0x02620213
0x02620217
0x0262021B
0x0262021F
0x0262023F
0x02620243
0x02620247
0x0262024B
0x0262024F
0x02620253
0x02620257
0x0262025B
0x0262025F
Size
4B
4B
4B
4B
4B
4B
4B
20B
4B
12B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
48B
4B
4B
4B
4B
4B
4B
4B
4B
32B
4B
4B
4B
4B
4B
4B
4B
4B
Field
Description
PWRSTATECTL
SRIO_SERDES_STS
SMGII_SERDES_STS
PCIE_SERDES_STS
HYPERLINK_SERDES_STS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
NMIGR0
See section 3.3.11
See ‘‘Related Documentation from Texas Instruments’’ on page 73
See section 3.3.12
NMIGR1
NMIGR2
NMIGR3
NMIGR4
NMIGR5
NMIGR6
NMIGR7
Reserved
IPCGR0
See section 3.3.13
IPCGR1
IPCGR2
IPCGR3
IPCGR4
IPCGR5
IPCGR6
IPCGR7
76
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-2
Device State Control Registers (Part 3 of 4)
Address Start
0x02620260
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202BC
0x026202C0
0x02620300
0x02620304
0x02620308
0x0262030C
0x02620310
0x02620314
0x02620318
0x0262031C
0x02620320
0x02620324
0x02620328
0x0262032C
0x02620330
0x02620334
0x02620338
0x0262033C
Address End
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202BB
0x026202BF
0x026202FF
0x02620303
0x02620307
0x0262030B
0x0262030F
0x02620313
0x02620317
0x0262031B
0x0262031F
0x02620323
0x02620327
0x0262032B
0x0262032F
0x02620333
0x02620337
0x0262033B
0x0262033F
Size
28B
4B
4B
4B
4B
4B
4B
4B
4B
4B
28B
4B
64B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
Field
Description
Reserved
IPCGRH
See section 3.3.15
See section 3.3.14
IPCAR0
IPCAR1
IPCAR2
IPCAR3
IPCAR4
IPCAR5
IPCAR6
IPCAR7
Reserved
IPCARH
See section 3.3.16
Reserved
TINPSEL
See section 3.3.17
See section 3.3.18
TOUTPSEL
RSTMUX0
RSTMUX1
RSTMUX2
RSTMUX3
RSTMUX4
RSTMUX5
RSTMUX6
RSTMUX7
MAINPLLCTL0
MAINPLLCTL1
DDR3PLLCTL0
DDR3PLLCTL1
PASSPLLCTL0
PASSPLLCTL1
See section 3.3.19
See section 7.5 ‘‘Main PLL and PLL Controller’’ on page 139
See section 7.6 ‘‘DD3 PLL’’ on page 151
See section 7.7 ‘‘PASS PLL’’ on page 154
Copyright 2013 Texas Instruments Incorporated
Device Configuration 77
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-2
Device State Control Registers (Part 4 of 4)
Address Start
0x02620340
0x02620344
0x02620348
0x0262034C
0x02620350
0x02620354
0x02620358
0x0262035C
0x02620360
0x02620364
0x02620368
0x0262036C
0x02620370
0x02620374
0x02620378
0x0262037C
0x02620380
0x02620384
0x02620388
0x026203B0
0x026203B4
0x026203B8
0x026203BC
0x026203C0
0x026203C4
0x026203C8
0x026203CC
0x026203D0
0x026203D4
0x026203D8
0x026203DC
0x026203F8
0x026203FC
0x02620400
0x02620404
End of Table 3-2
Address End
0x02620343
0x02620347
0x0262034B
0x0262034F
0x02620353
0x02620357
0x0262035B
0x0262035F
0x02620363
0x02620367
0x0262036B
0x0262036F
0x02620373
0x02620377
0x0262037B
0x0262037F
0x02620383
0x02620387
0x026203AF
0x026203B3
0x026203B7
0x026203BB
0x026203BF
0x026203C3
0x026203C7
0x026203CB
0x026203CF
0x026203D3
0x026203D7
0x026203DB
0x026203F7
0x026203FB
0x026203FF
0x02620403
0x02620467
Size
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
28B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
4B
28B
4B
4B
4B
Field
Description
See ‘‘Related Documentation from Texas Instruments’’ on page 73
SGMII_SERDES_CFGPLL
SGMII_SERDES_CFGRX0
SGMII_SERDES_CFGTX0
SGMII_SERDES_CFGRX1
SGMII_SERDES_CFGTX1
Reserved
PCIE_SERDES_CFGPLL
Reserved
SRIO_SERDES_CFGPLL
SRIO_SERDES_CFGRX0
SRIO_SERDES_CFGTX0
SRIO_SERDES_CFGRX1
SRIO_SERDES_CFGTX1
SRIO_SERDES_CFGRX2
SRIO_SERDES_CFGTX2
SRIO_SERDES_CFGRX3
SRIO_SERDES_CFGTX3
Reserved
Reserved
Reserved
HYPERLINK_SERDES_CFGPLL
HYPERLINK_SERDES_CFGRX0
HYPERLINK_SERDES_CFGTX0
HYPERLINK_SERDES_CFGRX1
HYPERLINK_SERDES_CFGTX1
HYPERLINK_SERDES_CFGRX2
HYPERLINK_SERDES_CFGTX2
HYPERLINK_SERDES_CFGRX3
HYPERLINK_SERDES_CFGTX3
Reserved
See ‘‘Related Documentation from Texas Instruments’’ on page 73
Reserved
DEVSPEED
See section 3.3.20
Reserved
PKTDMA_PRI_ALLOC
See section 4.3 ‘‘Bus Priorities’’ on page 107
100B Reserved
78
Device Configuration
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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3.3.1 Device Status Register
The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR or
RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device Status Register is
shown in Figure 3-1 and described in Table 3-3.
Figure 3-1
Device Status Register
31
18
17
PACLKSEL
16
PCIESSEN
R-x
15
14
13
1
0
Reserved
R-0
PCIESSMODE[1:0
R/W-xx
BOOTMODE[12:0]
R/W-xxxxxxxxxxxx
LENDIAN
R-x (1)
Legend: R = Read only; RW = Read/Write; -n = value after reset
1 x indicates the bootstrap value latched via the external pin
Table 3-3
Device Status Register Field Descriptions
Bit
Field
Description
31-18 Reserved
Reserved. Read only, writes have no effect.
17
PACLKSEL
PA Clock select to select the reference clock for PA Sub-System PLL
0 = Selects CORECLK(P/N)
1 = Selects PASSCLK(P/N)
16
PCIESSEN
PCIe module enable
0 = PCIe module disabled
1 = PCIe module enabled
15-14 PCIESSMODE[1:0] PCIe Mode selection pins
00b = PCIe in End-point mode
01b = PCIe in Legacy End-point mode (support for legacy INTx)
10b = PCIe in Root complex mode
11b = Reserved
13-1
0
BOOTMODE[12:0] Determines the bootmode configured for the device. For more information on bootmode, refer to Section 2.5 ‘‘Boot
Modes Supported and PLL Settings’’ on page 28 and see the Bootloader for the C66x DSP User Guide in 2.10 ‘‘Related
Documentation from Texas Instruments’’ on page 73
LENDIAN
Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little
Endian mode.
0 = System is operating in Big Endian mode
1 = System is operating in Little Endian mode
End of Table 3-3
Copyright 2013 Texas Instruments Incorporated
Device Configuration 79
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.2 Device Configuration Register
The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets
and is locked after the first write. The Device Configuration Register is shown in Figure 3-2 and described in
Table 3-4.
Figure 3-2
Device Configuration Register (DEVCFG)
31
1
0
Reserved
R-0
SYSCLKOUTEN
R/W-1
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-4
Device Configuration Register Field Descriptions
Bit
31-1
0
Field
Description
Reserved
Reserved. Read only, writes have no effect.
SYSCLKOUTEN
SYSCLKOUT Enable
0 = No clock output
1 = Clock output enabled (default)
End of Table 3-4
3.3.3 JTAG ID (JTAGID) Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the
JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in Figure 3-3 and
described in Table 3-5.
Figure 3-3
JTAG ID (JTAGID) Register
31
28
27
12
11
1
0
VARIANT
R-xxxxb
PART NUMBER
MANUFACTURER
0000 0010 111b
LSB
R-1
R-0000 0000 1001 1110b
Legend: RW = Read/Write; R = Read only; -n = value after reset
Table 3-5
JTAG ID Register Field Descriptions
Bit
Field
Value
Description
Variant (4-Bit) value.
31-28 VARIANT
xxxxb
27-12 PART NUMBER
0000 0000 1001 1110b Part Number for boundary scan
11-1
0
MANUFACTURER
LSB
0000 0010 111b
1b
Manufacturer
This bit is read as a 1 for TMS320C6678
End of Table 3-5
Note—The value of the VARIANT and PART NUMBER fields depend on the silicon revision being used.
See the Silicon Errata for details.
80
Device Configuration
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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3.3.4 Kicker Mechanism (KICK0 and KICK1) Register
The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are
writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with
exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on
page 75 for the address location. Once released then all the Bootcfg MMRs having “write” permissions are writable
(the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0.
Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to
Bootcfg MMRs.
The kicker mechanism is unlocked by the ROM code. Do not write any other different values afterward to these
registers because that will lock the kicker mechanism and block any writes to Bootcfg registers.
3.3.5 DSP Boot Address (DSP_BOOT_ADDRn) Register
The DSP_BOOT_ADDRn register stores the initial boot fetch address of CorePac_n (n = core number). The fetch
address is the public ROM base address (for any boot mode) by default. DSP_BOOT_ADDRn register access should
be permitted to any master or emulator when the device is non-secure. CorePac will boot from that address when a
reset is performed. The DSP_BOOT_ADDRn register is shown in and described in .
Figure 3-4
DSP BOOT Address Register (DSP_BOOT_ADDRn)
31
10
9
0
DSP_BOOT_ADDR
Reserved
R-0
RW-0010000010110000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-6
DSP BOOT Address Register (DSP_BOOT_ADDRn) Field Descriptions
Bit
Field
Description
31-10 DSP_BOOT_ADDR Boot address of CorePac. CorePac will boot from that address when a reset is performed.
The reset value is 22 MSBs of ROM base address = 0x20B00000.
9-0
Reserved
Reserved
End of Table 3-6
3.3.6 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register
The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on
CORESEL. The LRESETNMI PIN Status Register is shown in Figure 3-5 and described in Table 3-7.
Figure 3-5
LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
R, +0000 0000 0000 0000
Legend: R = Read only; -n = value after reset
NMI7 NMI6 NMI5 NMI4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
Copyright 2013 Texas Instruments Incorporated
Device Configuration 81
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-7
LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions
Bit
Field
Description
31-16 Reserved
Reserved
15
14
13
12
11
10
9
NMI7
NMI6
NMI5
NMI4
NMI3
NMI2
NMI1
NMI0
LR7
CorePac7 in NMI
CorePac6 in NMI
CorePac5 in NMI
CorePac4 in NMI
CorePac3 in NMI
CorePac2 in NMI
CorePac1 in NMI
8
CorePac0 in NMI
7
CorePac7 in local reset
CorePac6 in local reset
CorePac5 in local reset
CorePac4 in local reset
CorePac3 in local reset
CorePac2 in local reset
CorePac1 in local reset
CorePac0 in local reset
6
LR6
5
LR5
4
LR4
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 3-7
3.3.7 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register
The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on CORESEL. The
LRESETNMI PIN Status Clear Register is shown in Figure 3-6 and described in Table 3-8
Figure 3-6
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
R, +0000 0000 0000 0000
NMI7 NMI6 NMI5 NMI4 NMI3 NMI2 NMI1 NMI0 LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
WC,
+0
WC,
+0
WC,
+0
WC,
+0
WC,
+0
WC, WC, WC, WC, WC, WC, WC, WC, WC, WC, WC,
+0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0
Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear
82
Device Configuration
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-8
LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions
Bit
Field
Description
31-16 Reserved
Reserved
15
14
13
12
11
10
9
NMI7
NMI6
NMI5
NMI4
NMI3
NMI2
NMI1
NMI0
LR7
CorePac7 in NMI clear
CorePac6 in NMI clear
CorePac5 in NMI clear
CorePac4 in NMI clear
CorePac3 in NMI clear
CorePac2 in NMI clear
CorePac1 in NMI clear
CorePac0 in NMI clear
CorePac7 in local reset clear
CorePac6 in local reset clear
CorePac5 in local reset clear
CorePac4 in local reset clear
CorePac3 in local reset clear
CorePac2 in local reset clear
CorePac1 in local reset clear
CorePac0 in local reset clear
8
7
6
LR6
5
LR5
4
LR4
3
LR3
2
LR2
1
LR1
0
LR0
End of Table 3-8
Copyright 2013 Texas Instruments Incorporated
Device Configuration 83
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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3.3.8 Reset Status (RESET_STAT) Register
The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.
•
In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.
•
In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is
asserted.
The Reset Status Register is shown in Figure 3-7 and described in Table 3-9.
Figure 3-7
Reset Status Register (RESET_STAT)
31
GR
30
8
7
6
5
4
3
2
1
0
Reserved
LR7
R,+0
LR6
R,+0
LR5
R,+0
LR4
R,+0
LR3
R,+0
LR2
R,+0
LR1
R,+0
LR0
R,+0
R, +1
R, + 000 0000 0000 0000 0000 0000
Legend: R = Read only; -n = value after reset
Table 3-9
Reset Status Register (RESET_STAT) Field Descriptions
Description
Bit
Field
GR
31
Global reset status
0 = Device has not received a global reset.
1 = Device received a global reset.
30-8
7
Reserved
LR7
Reserved
CorePac7 reset status
0 = CorePac7 has not received a local reset.
1 = CorePac7 received a local reset.
6
5
4
3
2
1
0
LR6
LR5
LR4
LR3
LR2
LR1
LR0
CorePac6 reset status
0 = CorePac6 has not received a local reset.
1 = CorePac6 received a local reset.
CorePac5 reset status
0 = CorePac5 has not received a local reset.
1 = CorePac5 received a local reset.
CorePac4 reset status
0 = CorePac4 has not received a local reset.
1 = CorePac4 received a local reset.
CorePac3 reset status
0 = CorePac3 has not received a local reset.
1 = CorePac3 received a local reset.
CorePac2 reset status
0 = CorePac2 has not received a local reset.
1 = CorePac2 received a local reset.
CorePac1 reset status
0 = CorePac1 has not received a local reset.
1 = CorePac1 received a local reset.
CorePac0 reset status
0 = CorePac0 has not received a local reset.
1 = CorePac0 received a local reset.
End of Table 3-9
84
Device Configuration
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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3.3.9 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in Figure 3-8 and described in Table 3-10.
Figure 3-8
Reset Status Clear Register (RESET_STAT_CLR)
31
GR
30
8
7
6
5
4
3
2
1
0
Reserved
LR7
LR6
LR5
LR4
LR3
LR2
LR1
LR0
RW, +0
R, + 000 0000 0000 0000 0000 0000
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-10
Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
Description
Bit
Field
31
GR
Global reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
30-8
7
Reserved
LR7
Reserved.
CorePac7 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
6
5
4
3
2
1
0
LR6
LR5
LR4
LR3
LR2
LR1
LR0
CorePac6 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
CorePac5 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
CorePac4 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
CorePac3 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.
CorePac2 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register.
CorePac1 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.
CorePac0 reset clear bit
0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
End of Table 3-10
Copyright 2013 Texas Instruments Incorporated
Device Configuration 85
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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3.3.10 Boot Complete (BOOTCOMPLETE) Register
The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the
completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-9 and described in
Table 3-11.
Figure 3-9
Boot Complete Register (BOOTCOMPLETE)
31
8
7
6
5
4
3
2
1
0
Reserved
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R, + 0000 0000 0000 0000 0000 0000
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-11
Boot Complete Register (BOOTCOMPLETE) Field Descriptions
Description
Bit
31-8
7
Field
Reserved
Reserved.
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
CorePac7 boot status
0 = CorePac7 boot NOT complete
1 = CorePac7 boot complete
6
5
4
3
2
1
0
CorePac6 boot status
0 = CorePac6 boot NOT complete
1 = CorePac6 boot complete
CorePac5 boot status
0 = CorePac5 boot NOT complete
1 = CorePac5 boot complete
CorePac4 boot status
0 = CorePac4 boot NOT complete
1 = CorePac4 boot complete
CorePac3 boot status
0 = CorePac3 boot NOT complete
1 = CorePac3 boot complete
CorePac2 boot status
0 = CorePac2 boot NOT complete
1 = CorePac2 boot complete
CorePac1 boot status
0 = CorePac1 boot NOT complete
1 = CorePac1 boot complete
CorePac0 boot status
0 = CorePac0 boot NOT complete
1 = CorePac0 boot complete
End of Table 3-11
The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is
they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.
Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before
branching to the predefined location in memory.
86
Device Configuration
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Multicore Fixed and Floating-Point Digital Signal Processor
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3.3.11 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this
register to differentiate between the various power saving modes. This register is cleared only by POR and will
survive all other device resets. See the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from
Texas Instruments’’ on page 73 for more information. The Power State Control Register is shown in Figure 3-10 and
described in Table 3-12.
Figure 3-10
Power State Control Register (PWRSTATECTL)
31
3
2
1
0
GENERAL_PURPOSE
HIBERNATION_MODE
RW,+0
HIBERNATION
RW,+0
STANDBY
RW,+0
RW, +0000 0000 0000 0000 0000 0000 0000 0
Legend: RW = Read/Write; -n = value after reset
Table 3-12
Power State Control Register (PWRSTATECTL) Field Descriptions
Description
Bit
Field
31-3
GENERAL_PURPOSE
Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
2
1
0
HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.
0 = Hibernation mode 1
1 = Hibernation mode 2
HIBERNATION
STANDBY
Indicates whether the device is in hibernation mode or not.
0 = Not in hibernation mode
1 = Hibernation mode
Indicates whether the device is in standby mode or not.
0 = Not in standby mode
1 = Standby mode
End of Table 3-12
3.3.12 NMI Event Generation to CorePac (NMIGRx) Register
NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6678 has
eight NMIGRx registers (NMIGR0 through NMIGR7). The NMIGR0 register generates an NMI event to CorePac0,
the NMIGR1 register generates an NMI event to CorePac1, and so on. Writing a 1 to the NMIG field generates a
NMI pulse. Writing a 0 has no effect and reads return 0 and have no other effect. The NMI Even Generation to
CorePac Register is shown in Figure 3-11 and described in Table 3-13.
Figure 3-11
NMI Generation Register (NMIGRx)
31
1
0
Reserved
R, +0000 0000 0000 0000 0000 0000 0000 000
NMIG
RW,+0
Legend: RW = Read/Write; -n = value after reset
Copyright 2013 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 3-13
NMI Generation Register (NMIGRx) Field Descriptions
Description
Bit
31-1
0
Field
Reserved
NMIG
Reserved
NMI pulse generation.
Reads return 0
Writes:
0 = No effect
1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.
End of Table 3-13
3.3.13 IPC Generation (IPCGRx) Registers
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The C6678 has eight IPCGRx registers (IPCGR0 through IPCGR7). These registers can be used by external hosts or
CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an
interrupt pulse to CorePacx (0 <= x <= 7).
These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.
Allocation of source bits to source processor and meaning is entirely based on software convention. The register field
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is
completely controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Generation Register is shown in Figure 3-12 and described in Table 3-14.
Figure 3-12
IPC Generation Registers (IPCGRx)
31
30
29
28
27
8
7
6
5
4
3
1
0
SRCS27 SRCS26 SRCS25 SRCS24
RW +0 RW +0 RW +0 RW +0
SRCS23 – SRCS4
SRCS3
RW +0
SRCS2
RW +0
SRCS1
RW +0
SRCS0
RW +0
Reserved
R, +000
IPCG
RW +0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-14
IPC Generation Registers (IPCGRx) Field Descriptions
Bit
Field
SRCSx
Description
31-4
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
IPCG
Reserved
Inter-DSP interrupt generation.
Reads return 0.
Writes:
0 = No effect
1 = Creates an Inter-DSP interrupt.
End of Table 3-14
88
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.14 IPC Acknowledgement (IPCARx) Registers
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
The C6678 has eight IPCARx registers (IPCAR0 through IPCAR7). These registers also provide a Source ID facility
by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and
meaning is entirely based on software convention. The register field descriptions are shown in the following tables.
Virtually anything can be a source for these registers as this is completely controlled by software. Any master that
has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in
Figure 3-13 and described in Table 3-15.
Figure 3-13
IPC Acknowledgement Registers (IPCARx)
31
30
29
28
27
8
7
6
5
4
3
0
SRCC27 SRCC26 SRCC25 SRCC24
RW +0 RW +0 RW +0 RW +0
SRCC23 – SRCC4
SRCC3
RW +0
SRCC2
RW +0
SRCC1
RW +0
SRCC0
RW +0
Reserved
R, +0000
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-15
IPC Acknowledgement Registers (IPCARx) Field Descriptions
Bit
Field
SRCCx
Description
31-4
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-15
3.3.15 IPC Generation Host (IPCGRH) Register
The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same
as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin
HOUT.
The host interrupt output pulse is stretched so that it is asserted for four bootcfg clock (CPU/6) cycles followed by a
deassertion of four bootcfg clock cycles. Generating the pulse results in a pulse-blocking window that is eight
CPU/6-cycles long. Back to back writes to the IPCRGH register with the IPCG bit (bit 0) set, generates only one pulse
if the back-to-back writes to IPCGRH are less than the eight CPU/6 cycle window -- the pulse blocking window. In
order to generate back-to-back pulses, the back-to-back writes to the IPCGRH register must be greater than eight
CPU/6 cycle window. The IPC Generation Host Register is shown in Figure 3-14 and described in Table 3-16.
Figure 3-14
IPC Generation Registers (IPCGRH)
31
30
29
28
27
8
7
6
5
4
3
1
0
SRCS27 SRCS26 SRCS25 SRCS24
RW +0 RW +0 RW +0 RW +0
SRCS23 – SRCS4
SRCS3
RW +0
SRCS2
RW +0
SRCS1
RW +0
SRCS0
RW +0
Reserved
R, +000
IPCG
RW +0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Copyright 2013 Texas Instruments Incorporated
Device Configuration 89
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-16
IPC Generation Registers (IPCGRH) Field Descriptions
Bit
Field
SRCSx
Description
31-4
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.
3-1
0
Reserved
IPCG
Reserved
Host interrupt generation.
Reads return 0.
Writes:
0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)
End of Table 3-16
3.3.16 IPC Acknowledgement Host (IPCARH) Register
IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-15 and described in
Table 3-17.
Figure 3-15
IPC Acknowledgement Register (IPCARH)
31
30
29
28
27
8
7
6
5
4
3
0
SRCC27 SRCC26 SRCC25 SRCC24
RW +0 RW +0 RW +0 RW +0
SRCC23 – SRCC4
SRCC3
RW +0
SRCC2
RW +0
SRCC1
RW +0
SRCC0
RW +0
Reserved
R, +0000
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-17
IPC Acknowledgement Register (IPCARH) Field Descriptions
Bit
Field
SRCCx
Description
31-4
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
3-0
Reserved
Reserved
End of Table 3-17
90
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.17 Timer Input Selection Register (TINPSEL)
Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown
in Figure 3-16 and described in Table 3-18
Figure 3-16
Timer Input Selection Register (TINPSEL)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL
SEL15 SEL15 SEL14 SEL14 SEL13 SEL13 SEL12 SEL12 SEL11 SEL11 SEL10 SEL10 SEL9 SEL9 SEL8 SEL8
RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +1 RW, +1 RW, +0
spacer
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL
SEL7 SEL7 SEL6 SEL6 SEL5 SEL5 SEL4 SEL4 SEL3 SEL3 SEL2 SEL2 SEL1 SEL1 SEL0 SEL0
RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +1 RW, +1 RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-18
Timer Input Selection Field Description (TINPSEL) (Part 1 of 3)
Description
Bit
Field
TINPHSEL15
31
Input select for TIMER15 high.
0 = TIMI0
1 = TIMI1
30
29
28
27
26
25
24
23
22
21
TINPLSEL15
TINPHSEL14
TINPLSEL14
TINPHSEL13
TINPLSEL13
TINPHSEL12
TINPLSEL12
TINPHSEL11
TINPLSEL11
TINPHSEL10
Input select for TIMER15 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER14 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER14 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER13 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER13 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER12 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER12 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER11 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER11 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER10 high.
0 = TIMI0
1 = TIMI1
Copyright 2013 Texas Instruments Incorporated
Device Configuration 91
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-18
Timer Input Selection Field Description (TINPSEL) (Part 2 of 3)
Description
Bit
Field
TINPLSEL10
20
Input select for TIMER10 low.
0 = TIMI0
1 = TIMI1
19
18
17
16
15
14
13
12
11
10
9
TINPHSEL9
TINPLSEL9
TINPHSEL8
TINPLSEL8
TINPHSEL7
TINPLSEL7
TINPHSEL6
TINPLSEL6
TINPHSEL5
TINPLSEL5
TINPHSEL4
TINPLSEL4
TINPHSEL3
TINPLSEL3
TINPHSEL2
TINPLSEL2
Input select for TIMER9 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER9 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER8 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER8 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER7 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER7 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER6 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER6 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER5 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER5 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER4 high.
0 = TIMI0
1 = TIMI1
8
Input select for TIMER4 low.
0 = TIMI0
1 = TIMI1
7
Input select for TIMER3 high.
0 = TIMI0
1 = TIMI1
6
Input select for TIMER3 low.
0 = TIMI0
1 = TIMI1
5
Input select for TIMER2 high.
0 = TIMI0
1 = TIMI1
4
Input select for TIMER2 low.
0 = TIMI0
1 = TIMI1
92
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 3-18
Timer Input Selection Field Description (TINPSEL) (Part 3 of 3)
Bit
Field
Description
3
TINPHSEL1
TINPLSEL1
TINPHSEL0
TINPLSEL0
Input select for TIMER1 high.
0 = TIMI0
1 = TIMI1
2
1
0
Input select for TIMER1 low.
0 = TIMI0
1 = TIMI1
Input select for TIMER0 high.
0 = TIMI0
1 = TIMI1
Input select for TIMER0 low.
0 = TIMI0
1 = TIMI1
Copyright 2013 Texas Instruments Incorporated
Device Configuration 93
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.18 Timer Output Selection Register (TOUTPSEL)
The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-17 and described in Table 3-19.
Figure 3-17
Timer Output Selection Register (TOUTPSEL)
31
10
9
5
4
0
Reserved
TOUTPSEL1
RW,+00001
TOUTPSEL0
RW,+00000
R,+000000000000000000000000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-19
Timer Output Selection Field Description (TOUTPSEL)
Bit
Field
Description
31-10
9-5
Reserved
Reserved
TOUTPSEL1
Output select for TIMO1
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000: TOUTL4
01001: TOUTH4
01010: TOUTL5
01011: TOUTH5
01100: TOUTL6
01101: TOUTH6
01110: TOUTL7
01111: TOUTH7
10000: TOUTL8
10001: TOUTH8
10010: TOUTL9
10011: TOUTH9
10100: TOUTL10
10101: TOUTH10
10110: TOUTL11
10111: TOUTH11
11000: TOUTL12
11001: TOUTH12
11010: TOUTL13
11011: TOUTH13
11100: TOUTL14
11101: TOUTH14
11110: TOUTL15
11111: TOUTH15
4-0
TOUTPSEL0
Output select for TIMO0
00000: TOUTL0
00001: TOUTH0
00010: TOUTL1
00011: TOUTH1
00100: TOUTL2
00101: TOUTH2
00110: TOUTL3
00111: TOUTH3
01000: TOUTL4
01001: TOUTH4
01010: TOUTL5
01011: TOUTH5
01100: TOUTL6
01101: TOUTH6
01110: TOUTL7
01111: TOUTH7
10000: TOUTL8
10001: TOUTH8
10010: TOUTL9
10011: TOUTH9
10100: TOUTL10
10101: TOUTH10
10110: TOUTL11
10111: TOUTH11
11000: TOUTL12
11001: TOUTH12
11010: TOUTL13
11011: TOUTH13
11100: TOUTL14
11101: TOUTH14
11110: TOUTL15
11111: TOUTH15
End of Table 3-19
94
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.19 Reset Mux (RSTMUXx) Register
The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through
RSTMUX7 for each of the eight CorePacs on the C6678. These registers are located in Bootcfg memory space. The
Reset Mux Register is shown in Figure 3-18 and described in Table 3-20.
Figure 3-18
Reset Mux Register RSTMUXx
31
10
9
8
7
5
4
3
1
0
Reserved
R, +0000 0000 0000 0000 0000 00
EVTSTATCLR
RC, +0
Reserved
R, +0
DELAY
RW, +100
EVTSTAT
R, +0
OMODE
RW, +000
LOCK
RW, +0
Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear
Table 3-20
Reset Mux Register Field Descriptions
Bit
Field
Description
31-10 Reserved
9
Reserved
EVTSTATCLR
Clear event status
0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit
8
Reserved
DELAY
Reserved
7-5
Delay cycles between NMI & local reset
000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)
101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
4
EVTSTAT
OMODE
Event status.
0 = No event received (Default)
1 = WD timer event received by Reset Mux block
3-1
Timer event operation mode
000b = WD timer event input to the reset mux block does not cause any output event (default)
001b = Reserved
010b = WD timer event input to the reset mux block causes local reset input to CorePac
011b = WD timer event input to the reset mux block causes NMI input to CorePac
100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to CorePac. Delay
between NMI and local reset is set in DELAY bit field.
101b = WD timer event input to the reset mux block causes device reset to C6678
110b = Reserved
111b = Reserved
0
LOCK
Lock register fields
0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset
End of Table 3-20
Copyright 2013 Texas Instruments Incorporated
Device Configuration 95
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.3.20 Device Speed (DEVSPEED) Register
The Device Speed Register depicts the device speed grade. The Device Speed Register is shown below.
Figure 3-19
Device Speed Register (DEVSPEED)
31
23
22
0
DEVSPEED
R-n
Reserved
R-n
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-21
Device Speed Register Field Descriptions
Description
Bit
Field
31-23 DEVSPEED
Indicates the speed of the device (read only)
0000 0000 0b = 800 MHz
0000 0000 1b = 1000 MHz
0000 0001 xb = 1200 MHz
0000 001x xb = 1250 MHz
0000 01xx xb = Reserved
0000 1xxx xb = Reserved
0001 xxxx xb = 1250 MHz
001x xxxx xb = 1200 MHz
01xx xxxx xb = 1000 MHz
1xxx xxxx xb = 800 MHz
22-0
Reserved
Reserved. Read only
End of Table 3-21
96
Device Configuration
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
3.4 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This
may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown
(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown
resistor to pull the signal to the opposite rail.
For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state),
it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing
external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In
addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user
in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown
resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of all inputs
connected to the net. For a pullup resistor, this should be above the highest VIH level of all inputs on the net.
A reasonable choice would be to target the VOL or VOH levels for the logic family of the limiting device; which,
by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the
target pulled value when maximum current from all devices on the net is flowing through the resistor. The
current to be considered includes leakage current plus, any other internal and external pullup/pulldown
resistors on the net.
For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the
external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to
the opposite logic level (including margin).
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the DVDD rail.
For most systems:
•
A 1-k resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this
resistor value is correct for their specific application.
•
A 20-k resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the
above criteria. Users should confirm this resistor value is correct for their specific application.
For more detailed information on input current (II), and the low-level/high-level input voltages (VIL and VIH) for
the TMS320C6678 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 118.
To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-26 ‘‘Terminal
Functions — Signals and Control by Function’’ on page 47.
Copyright 2013 Texas Instruments Incorporated
Device Configuration 97
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
4 System Interconnect
On the TMS320C6678 device, the C66x CorePacs, the EDMA3 transfer controllers, and the system peripherals are
interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contention-free
internal data movement. The TeraNet allows for low-latency, concurrent data transfers between master peripherals
and slave peripherals. The TeraNet also allows for seamless arbitration between the system masters when accessing
system slaves.
4.1 Internal Buses and Switch Fabrics
Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus
and a configuration bus interface, while others have only one type of interface. Further, the bus interface width and
speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a
peripheral and the data buses are used mainly for data transfers.
The C66x CorePacs, the EDMA3 traffic controllers, and the various system peripherals can be classified into two
categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely
on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the masters to perform transfers to and
from them. Examples of masters include the EDMA3 traffic controllers, SRIO, and Network Coprocessor packet
DMA. Examples of slaves include the SPI, UART, and I2C.
The masters and slaves in the device are communicating through the TeraNet (switch fabric). The device contains
two switch fabrics. The data switch fabric (data TeraNet) and the configuration switch fabric (configuration
TeraNet). The data TeraNet, is a high-throughput interconnect mainly used to move data across the system. The
data TeraNet connects masters to slaves via data buses. Some peripherals require a bridge to connect to the data
TeraNet. The configuration TeraNet, is mainly used to access peripheral registers. The configuration TeraNet
connects masters to slaves via configuration buses. As with the data TeraNet, some peripherals require the use of a
bridge to interface to the configuration TeraNet. Note that the data TeraNet also connects to the configuration
TeraNet. For more details see 4.2 ‘‘Switch Fabric Connections’’.
98
System Interconnect
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
4.2 Switch Fabric Connections
The following figures show the connections between masters and slaves on TeraNet 2A and TeraNet 3A.
Figure 4-1
TeraNet 2A for C6678
XMC ´ n*
M
S
Bridge_5
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
SES
SMS
S
S
DDR3
MSMC
M
Tracer_MSMC0
Tracer_MSMC1
Tracer_MSMC2
Tracer_MSMC3
Tracer_DDR
From TeraNet_3_A
HyperLink
M
TC_0
TC_1
HyperLink
M
M
S
EDMA
CC0
Bridge_1
Bridge_2
Bridge_3
Bridge_4
To TeraNet_3_A
* n varies with the number of CorePacs present in the specific device.
Copyright 2013 Texas Instruments Incorporated
System Interconnect 99
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 4-2
TeraNet 3A for C6678
Bridge_1
Bridge_2
Bridge_3
Bridge_4
From TeraNet_2_A
CorePac_n*
S
S
S
S
S
S
S
Tracer_L2_n*
PCIe
SRIO_M
M
M
MPU_1
QM_SS
PCIe
Tracer_QM_M
SRIO
Packet DMA
M
M
M
SRIO
SPI
NETCP
TNet_6P_A
CPU/3
Boot_ROM
QM_SS
Packet DMA
EMIF16
QM_SS
Second
M
TNet_3_D
CPU/3
Bridge_5
Bridge_6
Bridge_7
Bridge_8
Bridge_9
Bridge_10
Debug_SS
TSIP0
M
M
M
TNet_3_C
CPU/3
To TeraNet_2_A
TSIP1
TC_0
TC_1
M
M
M
M
EDMA
CC1
TC_2
TC_3
Bridge_12
Bridge_13
Bridge_14
TC_0
TC_1
TC_2
TC_3
M
M
M
M
To TeraNet_3P_A
EDMA
CC2
* n varies with the number of CorePacs present in the specific device.
100
System Interconnect
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Allowed connections on TeraNet 2A and TeraNet 3A are summarized in the table below.
Intersecting cells may contain one of the following:
•
•
•
Y — There is a direct connection between this master and that slave.
- — There is NO connection between this master and that slave.
n — A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 4-1
Switch Fabric Connection Matrix Section 1
Slaves
Masters
HyperLink_Master
EDMA3CC0_TC0_RD
EDMA3CC0_TC0_WR
EDMA3CC0_TC1_RD
EDMA3CC0_TC1_WR
EDMA3CC1_TC0_RD
EDMA3CC1_TC0_WR
EDMA3CC1_TC1_RD
EDMA3CC1_TC1_WR
EDMA3CC1_TC2_RD
EDMA3CC1_TC2_WR
EDMA3CC1_TC3_RD
EDMA3CC1_TC3_WR
EDMA3CC2_TC0_RD
EDMA3CC2_TC0_WR
EDMA3CC2_TC1_RD
EDMA3CC2_TC1_WR
EDMA3CC2_TC2_RD
EDMA3CC2_TC2_WR
EDMA3CC2_TC3_RD
EDMA3CC2_TC3_WR
SRIO packet DMA
SRIO_Master
-
Y
Y
Y
Y
5
5
6
6
7
7
8
8
9
9
10
10
5
5
6
6
-
Y
Y
Y
Y
Y
5
Y
Y
Y
Y
Y
5
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
4
Y
Y
Y
Y
Y
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
1
2
-
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
1
2
2
3
3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
1
-
-
3
-
-
-
Y
-
-
5
5
-
6
6
Y
-
Y
Y
-
6
6
7
7
Y
-
7
7
-
8
8
Y
-
-
8
8
-
9
9
Y
-
-
9
9
-
10
10
5
10
10
5
Y
-
Y
Y
-
Y
-
5
5
-
6
6
Y
-
-
6
6
-
9
9
-
Y
Y
Y
Y
4
Y
-
9
7
-
9
9
-
-
Y
Y
-
-
PCIe_Master
7
7
-
-
-
NETCP packet DMA
MSMC_Data_Master
QM packet DMA
10
-
10
-
-
-
-
Y
8
8
10
-
4
-
4
-
4
-
4
-
4
-
8
8
QM_Second
8
8
-
-
-
-
-
DebugSS_Master
TSIP0_Master
10
5
10
5
Y
-
Y
-
Y
-
Y
-
Y
-
Y
-
TSIP1_Master
-
5
5
-
-
-
-
-
-
End of Table 4-1
Copyright 2013 Texas Instruments Incorporated
System Interconnect 101
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
The following figure shows the connection between masters and slaves on TeraNet 3P and TeraNet 6P.
Figure 4-3
TeraNet 3P_A & B for C6678
MPU (× 4)
S
S
S
Bridge_12
TC (× 2)
From TeraNet_3_A
TNet_2P
CPU/2
Bridge_13
Bridge_14
CC0
TC (× 4)
S
S
TNet_3P_C
CPU/3
CC1
CorePac_n*
M
TC (× 4)
S
S
TNet_3P_D
CPU/3
CC2
MPU_2
MPU_3
QM_SS
S
S
Tracer_QM_CFG
Tracer_SM
Semaphore
TETB (Debug_SS)
TETB (for core)
To TeraNet_3P_Tracer
MPU_0
Tracer_CFG
SRIO
S
Tracer
S
NETCP
S
TSIP0
S
TSIP1
S
To TeraNet_6P_B
Bridge_20
* n varies with the number of CorePacs present in the specific device.
102
System Interconnect
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 4-4
TeraNet 6P_B and 3P_Tracer for C6678
From TeraNet_3P_A
Tracer_
MSMC_0
M
M
M
M
Tracer_
MSMC_1
Tracer_
MSMC_2
Debug_SS
STM
S
Tracer_
MSMC_3
Tracer_CFG
Tracer_DDR
Tracer_SM
M
M
M
Debug_SS
TETB
S
Tracer_
QM_M
M
Tracer_
QM_P
M
M
Tracer_L2_n*
SmartReflex
S
Bridge_20
GPIO
From TeraNet_3P_B
S
I2C
S
UART
S
BOOTCFG
S
PSC
S
PLL_CTL
S
Debug_SS
S
CIC
S
Timer
S
* n varies with the number of CorePacs present in the specific device.
Copyright 2013 Texas Instruments Incorporated
System Interconnect 103
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Allowed connections on TeraNet 3P and TeraNet 6P are summarized in the tables below.
Intersecting cells may contain one of the following:
•
•
•
Y — There is a direct connection between this master and that slave.
- — There is NO connection between this master and that slave.
n — A numeric value indicates that the path between this master and that slave goes through bridge n.
Table 4-2
Switch Fabric Connection Matrix Section 2 (Part 1 of 2)
Slave
Masters
HyperLink_Master
EDMA3CC0_TC0_RD
EDMA3CC0_TC0_WR
EDMA3CC0_TC1_RD
EDMA3CC0_TC1_WR
EDMA3CC1_TC0_RD
EDMA3CC1_TC0_WR
EDMA3CC1_TC1_RD
EDMA3CC1_TC1_WR
EDMA3CC1_TC2_RD
EDMA3CC1_TC2_WR
EDMA3CC1_TC3_RD
EDMA3CC1_TC3_WR
EDMA3CC2_TC0_RD
EDMA3CC2_TC0_WR
EDMA3CC2_TC1_RD
EDMA3CC2_TC1_WR
EDMA3CC2_TC2_RD
EDMA3CC2_TC2_WR
EDMA3CC2_TC3_RD
EDMA3CC2_TC3_WR
SRIO packet DMA
SRIO_Master
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12
2,12
2,12
3,12
3,12
12
12
13
13
14
14
12
12
12
12
13
13
12
12
14
14
-
1,12 1,12 1,12 1,12
1,12
1,12
1,12 1,12 1,12 1,12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
PCIe_Master
NETCP packet DMA
MSMC_Data_Master
QM packet DMA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
QM_Second
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DebugSS_Master
TSIP0_Master
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
TSIP1_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC0
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
104
System Interconnect
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 4-2
Switch Fabric Connection Matrix Section 2 (Part 2 of 2)
Slave
Masters
EDMA3CC1
-
-
-
-
Y
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC2
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
-
-
-
-
-
-
-
-
-
-
CorePac0_CFG
CorePac1_CFG
CorePac2_CFG
CorePac3_CFG
CorePac4_CFG
CorePac5_CFG
CorePac6_CFG
CorePac7_CFG
End of Table 4-2
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Table 4-3
Switch Fabric Connection Matrix Section 3 (Part 1 of 2)
Slave
Masters
HyperLink_Master
1,12 1,12 1,12
1,12
-
1,12
-
1,12 1,12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC0_TC0_RD
EDMA3CC0_TC0_WR
EDMA3CC0_TC1_RD
EDMA3CC0_TC1_WR
EDMA3CC1_TC0_RD
EDMA3CC1_TC0_WR
EDMA3CC1_TC1_RD
EDMA3CC1_TC1_WR
EDMA3CC1_TC2_RD
EDMA3CC1_TC2_WR
EDMA3CC1_TC3_RD
EDMA3CC1_TC3_WR
EDMA3CC2_TC0_RD
EDMA3CC2_TC0_WR
EDMA3CC2_TC1_RD
EDMA3CC2_TC1_WR
EDMA3CC2_TC2_RD
EDMA3CC2_TC2_WR
EDMA3CC2_TC3_RD
-
-
-
-
-
-
-
-
-
-
2,12
-
-
-
-
-
-
2,12
2,12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3,12
-
-
-
3,12
3,12
-
-
-
-
-
-
-
-
12
-
-
-
-
-
12
-
-
12
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
-
-
-
-
-
-
-
-
-
-
-
13
-
13
-
-
-
-
-
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
14
-
-
-
-
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
12
12
12
-
12
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
12
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
-
13
-
13
-
-
-
-
-
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
-
-
-
-
-
12
-
12
-
-
-
-
-
-
-
-
-
-
-
-
14
14
-
-
-
14
Copyright 2013 Texas Instruments Incorporated
System Interconnect 105
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 4-3
Switch Fabric Connection Matrix Section 3 (Part 2 of 2)
Slave
Masters
EDMA3CC2_TC3_WR
SRIO packet DMA
SRIO_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
12
12
-
PCIe_Master
NETCP packet DMA
MSMC_Data_Master
QM packet DMA
QM_Second
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DebugSS_Master
TSIP0_Master
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
12
-
TSIP1_Master
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EDMA3CC2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CorePac0_CFG
CorePac1_CFG
CorePac2_CFG
CorePac3_CFG
CorePac4_CFG
CorePac5_CFG
CorePac6_CFG
CorePac7_CFG
End of Table 4-3
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
106
System Interconnect
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Multicore Fixed and Floating-Point Digital Signal Processor
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4.3 Bus Priorities
The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means
higher priority - PRI = 000b = urgent, PRI = 111b = low.
All other masters provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMA-based
peripherals also have internal registers to define the priority level of their initiated transactions.
The packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-5 and
Table 4-4.
Figure 4-5
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)
31
3
2
0
Reserved
PKTDMA_PRI
RW-000
R/W-00000000000000000000001000011
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 4-4
Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions
Bit
Field
Description
31-3
2-0
Reserved
Reserved.
PKDTDMA_PRI
Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.
End of Table 4-4
For all other modules, see the respective User Guides in “Related Documentation from Texas Instruments” on
page 73 for programmable priority registers.
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5 C66x CorePac
The C66x CorePac consists of several components:
•
•
•
•
•
•
•
•
•
The C66x DSP and associated C66x CorePac core
Level-one and level-two memories (L1P, L1D, L2)
Data Trace Formatter (DTF)
Embedded Trace Buffer (ETB)
Interrupt Controller
Power-down controller
External Memory Controller
Extended Memory Controller
A dedicated power/sleep controller (LPSC)
The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the
C66x CorePac) and address extension. Figure 5-1 shows a block diagram of the C66x CorePac.
Figure 5-1
C66x CorePac Block Diagram
32KB L1P
Program Memory Controller (PMC) With
Memory Protect/Bandwidth Mgmt
L2 Cache/
SRAM
512KB
C66x DSP Core
Instruction Fetch
16-/32-bit Instruction Dispatch
Control Registers
MSM
SRAM
4096KB
In-Circuit Emulation
Boot
Controller
Instruction Decode
Data Path A
Data Path B
DDR3
SRAM
A Register File
B Register File
PLLC
LPSC
GPSC
A31-A16
A15-A0
B31-B16
B15-B0
DMA Switch
Fabric
.M1
.L1 .S1 xx .D1
xx
.M2
.D2 xx .S2 .L2
xx
Data Memory Controller (DMC) With
Memory Protect/Bandwidth Mgmt
CFG Switch
Fabric
32KB L1D
For more detailed information on the TMS320C66x CorePac on the C6678 device, see the C66x CorePac User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 73.
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5.1 Memory Architecture
Each C66x CorePac of the TMS320C6678 device contains a 512KB level-2 memory (L2), a 32KB level-1 program
memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 4096KB multicore shared memory
(MSM). All memory on the C6678 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map
Summary’’ on page 21.
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be
reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the
L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way
set-associative cache, while L1P is a direct-mapped cache.
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader
for the C66x DSP User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
5.1.1 L1P Memory
The L1P memory configuration for the C6678 device is as follows:
•
32K bytes with no wait states
Figure 5-2 shows the available SRAM/cache configurations for L1P.
Figure 5-2
L1P Memory Configurations
L1P mode bits
010
Block base
address
00E0 0000h
000
001
011
100
L1P memory
16K bytes
1/2
SRAM
3/4
SRAM
7/8
SRAM
direct
mapped
cache
All
SRAM
00E0 4000h
00E0 6000h
8K bytes
direct
mapped
cache
4K bytes
4K bytes
direct
mapped
cache
00E0 7000h
00E0 8000h
dm
cache
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5.1.2 L1D Memory
The L1D memory configuration for the C6678 device is as follows:
•
32K bytes with no wait states
Figure 5-3 shows the available SRAM/cache configurations for L1D.
Figure 5-3
L1D Memory Configurations
L1D mode bits
010
Block base
address
00F0 0000h
000
001
011
100
L1D memory
16K bytes
1/2
SRAM
3/4
SRAM
7/8
SRAM
All
SRAM
2-way
cache
00F0 4000h
00F0 6000h
8K bytes
2-way
cache
4K bytes
4K bytes
2-way
cache
00F0 7000h
00F0 8000h
2-way
cache
110
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5.1.3 L2 Memory
The L2 memory configuration for the C6678 device is as follows:
•
•
•
Total memory size is 4096KB
Each core contains 512KB of memory
Local starting address for each core is 0080 0000h
L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2
memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register
(L2CFG) of the C66x CorePac. Figure 5-4 shows the available SRAM/cache configurations for L2. By default, L2 is
configured as all SRAM after device reset.
Figure 5-4
L2 Memory Configurations
L2 Mode Bits
Block Base
Address
000
001
010
011
100
101
L2 Memory
0080 0000h
ALL
SRAM
15/16
SRAM
7/8
SRAM
3/4
SRAM
1/2
SRAM
ALL
Cache
256Kbytes
4-Way
Cache
0084 0000h
0086 0000h
128Kbytes
64Kbytes
4-Way
Cache
4-Way
Cache
0087 0000h
0087 8000h
0087 FFFFh
32Kbytes
32Kbytes
4-Way
Cache
4-Way
Cache
Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by
the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled
within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address
location 0x10800000 is the global base address for C66x CorePac Core 0's L2 memory. C66x CorePac Core 0 can
access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000
only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.
For C66x CorePac Core 0, as mentioned, this is equivalent to 0x10800000, for C66x CorePac Core 1 this is equivalent
to 0x11800000, and for C66x CorePac Core 2 this is equivalent to 0x12800000. Local addresses should be used only
for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core,
or a memory region allocated during run-time by a particular core should always use the global address only.
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5.1.4 MSM SRAM
The MSM SRAM configuration for the C6678 device is as follows:
•
•
•
•
Memory size is 4096KB
The MSM SRAM can be configured as shared L2 and/or shared L3 memory
Allows extension of external addresses from 2GB to up to 8GB
Has built in memory protection features
The MSM SRAM is always configured as all SRAM. When configured as a shared L2, its contents can be cached in
L1P and L1D. When configured in shared L3 mode, it’s contents can be cached in L2 also. For more details on
external memory address extension and memory protection features, see the Multicore Shared Memory Controller
(MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
5.1.5 L3 Memory
The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement
to block accesses from this portion to the ROM.
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5.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2
memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB
each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in
the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In
addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct
DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by
other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a
secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether
memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 5-1.
Table 5-1
Available Memory Page Protection Schemes
AIDx Bit
Local Bit
Description
0
0
1
0
1
No access to memory page is permitted.
0
Only direct access by DSP is permitted.
1
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
All accesses permitted.
1
End of Table 5-1
Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
•
•
•
Block the access — reads return zero, writes are ignored
Capture the initiator in a status register — ID, address, and access type are stored
Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
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5.3 Bandwidth Management
When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to
the highest priority requestor. The following four resources are managed by the Bandwidth Management control
hardware:
•
•
•
•
Level 1 Program (L1P) SRAM/Cache
Level 1 Data (L1D) SRAM/Cache
Level 2 (L2) SRAM/Cache
Memory-mapped registers configuration bus
The priority level for operations initiated within the C66x CorePac are declared through registers in the C66x
CorePac. These operations are:
•
•
•
DSP-initiated transfers
User-programmed cache coherency operations
IDMA-initiated transfers
The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the
Priority Allocation Register (PRI_ALLOC), see section 4.3 ‘‘Bus Priorities’’ on page 107 for more details. System
peripherals with no fields in the PRI_ALLOC have their own registers to program their priorities.
More information on the bandwidth management features of the C66x CorePac can be found in the C66x CorePac
User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
5.4 Power-Down Control
The C66x CorePac supports the ability to power down various parts of the C66x CorePac. The power down
controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and
the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power
requirements.
Note—The C6678 does not support power-down modes for the L2 memory at this time.
More information on the power-down features of the C66x CorePac can be found in the TMS320C66x CorePac
Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
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5.5 C66x CorePac Revision
The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register (MM_REVID)
located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table 5-2. The
C66x CorePac revision is dependant on the silicon revision being used.
Figure 5-5
CorePac Revision ID Register (MM_REVID) Address - 0181 2000h
31
16 15
0
VERSION
R-n
REVISION
R-n
Legend: R = Read; -n = value after reset
Table 5-2
CorePac Revision ID Register (MM_REVID) Field Descriptions
Bit
Field
Description
31-16 VERSION
Version of the C66x CorePac implemented on the device.
15-0
REVISION
Revision of the C66x CorePac version implemented on the device.
End of Table 5-2
5.6 C66x CorePac Register Descriptions
See the C66x CorePac Reference Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73 for register
offsets and definitions.
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6 Device Operating Conditions
6.1 Absolute Maximum Ratings
Table 6-1
Absolute Maximum Ratings (1)
Over Operating Case Temperature Range (Unless Otherwise Noted)
CVDD
-0.3 V to 1.3 V
-0.3 V to 1.3 V
CVDD1
DVDD15
DVDD18
-0.3 V to 2.45 V
-0.3 V to 2.45 V
Supply voltage range (2)
:
VREFSSTL
0.49 × DVDD15 to 0.51 × DVDD15
-0.3 V to 1.3 V
VDDT1, VDDT2
VDDR1, VDDR2, VDDR3, VDDR4
-0.3 V to 2.45 V
AVDDA1, AVDDA2, AVDDA3
-0.3 V to 2.45 V
VSS Ground
LVCMOS (1.8V)
DDR3
0 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 2.45 V
I2C
-0.3 V to 2.45 V
Input voltage (VI) range:
LVDS
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.3 V
LJCB
SerDes
-0.3 V to CVDD1+0.3 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 2.45 V
LVCMOS (1.8V)
DDR3
Output voltage (VO) range:
I2C
-0.3 V to 2.45 V
SerDes
-0.3 V to CVDD1+0.3 V
0°C to 85°C
Commercial
Extended
Operating case temperature range, TC:
-40°C to 100°C
HBM (human body model) (4)
CDM (charged device model) (5)
1000 V
(3)
ESD stress voltage, VESD
Overshoot/undershoot (6)
:
250 V
LVCMOS (1.8V)
20% Overshoot/Undershoot for 20% of
Signal Duty Cycle
DDR3
I2C
Storage temperature range, Tstg
:
-65°C to 150°C
End of Table 6-1
1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
2 All voltage values are with respect to VSS
.
3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
4
5
Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD
control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control
process. Pins listed as 250 V may actually have higher performance.
6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and
maximum undershoot value would be VSS - 0.20 × DVDD18
116
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6.2 Recommended Operating Conditions
Table 6-2
Recommended Operating Conditions (1) (2)
Min
1.045
Nom
1.1 (3)
Max Unit
Initial Startup
1.155
CVDD
SR Core Supply
1000MHz - Device
1250MHz - Device
SRVnom (4) × 0.95
SRVnom × 0.95
0.95
0.85-1.1
SRVnom × 1.05
V
0.9-1.1
SRVnom × 1.05
CVDD1
Core supply voltage for memory array
1.8-V supply I/O voltage
1.5-V supply I/O voltage
DDR3 reference voltage
SerDes regulator supply
PLL analog supply
1
1.05
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
DVDD18
DVDD15
VREFSSTL
1.71
1.8
1.89
1.425
1.5
1.575
0.49 × DVDD15
1.425
0.5 × DVDD15
0.51 × DVDD15
(5)
VDDRx
1.5
1.8
1
1.575
1.89
1.05
0
VDDAx
VDDTx
VSS
1.71
SerDes termination supply
Ground
0.95
0
0
LVCMOS (1.8 V)
I2C
0.65 × DVDD18
0.7 × DVDD18
VREFSSTL + 0.1
VIH
High-level input voltage
DDR3 EMIF
LVCMOS (1.8 V)
DDR3 EMIF
I2C
0.35 × DVDD18
VREFSSTL - 0.1
0.3 × DVDD18
85
VIL
TC
Low-level input voltage
-0.3
Commercial
Extended
0
Operating case temperature
-40
100
End of Table 6-2
1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI Electrical Specification, IEEE
802.3ae-2002.
2 All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.
3 The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on VCNTL pins. This is required to maintain
full power functionality and reliability targets guaranteed by TI.
4 SRVnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.
5 Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.
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6.3 Electrical Characteristics
Table 6-3
Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Parameter
LVCMOS (1.8 V)
Test Conditions (1)
O = IOH
Min
DVDD18 - 0.45
DVDD15 - 0.4
Typ
Max Unit
I
I
VOH High-level output voltage
DDR3
I2C (2)
V
LVCMOS (1.8 V)
O = IOL
0.45
VOL Low-level output voltage
DDR3
I2C
0.4
0.4
V
IO = 3 mA, pulled up to 1.8 V
No IPD/IPU
-5
50
5
LVCMOS (1.8 V)
Internal pullup
100
170 (4)
(3)
II
Input current [DC]
A
Internal pulldown
-170
-100
-50
0.1 × DVDD18 V < VI < 0.9 ×
DVDD18 V
I2C
-10
10
-6
LVCMOS (1.8 V)
IOH
IOL
IOZ
High-level output current [DC] DDR3
I2C (5)
-8 mA
LVCMOS (1.8 V)
6
Low-level output current [DC] DDR3
I2C
8
3
2
2
2
mA
LVCMOS (1.8 V)
DDR3
I2C
-2
-2
-2
(6)
Off-state output current [DC]
A
End of Table 6-3
1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
2 I2C uses open collector IOs and does not have a VOH Minimum.
3 II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and
off-state (Hi-Z) output leakage current.
4 For RESETSTAT, max DC input current is 300 A.
5 I2C uses open collector IOs and does not have a IOH Maximum.
6 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
118
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6.4 Power Supply to Peripheral I/O Mapping
(1) (2)
Table 6-4
Power Supply to Peripheral I/O Mapping
Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
Power Supply I/O Buffer Type
Associated Peripheral
CORECLK(P|N) PLL input buffer
SRIOSGMIICLK(P|N) SerDes PLL input buffer
DDRCLK(P|N) PLL input buffer
CVDD
Supply Core Voltage
LJCB
PCIECLK(P|N) SERDES PLL input buffer
MCMCLK(P|N) SERDES PLL input buffer
PASSCLK(P|N) PLL input buffer
DVDD15 1.5-V supply I/O voltage
DDR3 (1.5 V)
All DDR3 memory controller peripheral I/O buffer
All GPIO peripheral I/O buffer
All JTAG and EMU peripheral I/O buffer
All Timer peripheral I/O buffer
All SPI peripheral I/O buffer
All RESETs, NMI, Control peripheral I/O buffer
All SmartReflex peripheral I/O buffer
All Hyperlink sideband peripheral I/O buffer
All MDIO peripheral I/O buffer
LVCMOS (1.8 V)
DVDD18 1.8-V supply I/O voltage
All UART peripheral I/O buffer
All TSIP0 and TSIP1 peripheral I/O buffer
All EMIF16 peripheral I/O buffer
Open-drain (1.8V) All I2C peripheral I/O buffer
VDDT1
VDDT2
Hyperlink SerDes termination and analogue front-end supply
SerDes/CML
Hyperlink SerDes CML IO buffer
SRIO/SGMII/PCIE SerDes termination and analogue front-end
supply
SerDes/CML
SRIO/SGMII/PCIE SerDes CML IO buffer
End of Table 6-4
1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and
clock input buffers.
2 Please see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 73 for more information about individual
peripheral I/O.
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7 Peripheral Information and Electrical Specifications
This chapter covers the various peripherals on the TMS320C6678 DSP. Peripheral-specific information, timing
diagrams, electrical specifications, and register memory maps are described in this chapter.
7.1 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
7.2 Power Supplies
The following sections describe the proper power-supply sequencing and timing needed to properly power on the
C6678. The various power supply rails and their primary function is listed in Table 7-1.
Table 7-1
Power Supply Rails on TMS320C6678
Name
CVDD
CVDD1
Primary Function
Voltage Notes
0.9 - 1.1 V Includes core voltage for DDR3 module
SmartReflex core supply voltage
Core supply voltage for memory
array
1.0 V
1.0 V
1.0 V
1.5 V
Fixed supply at 1.0 V
VDDT1
VDDT2
HyperLink SerDes termination
supply
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
HyperLink is not in use.
SGMII/SRIO/PCIE SerDes
termination supply
Filtered version of CVDD1. Special considerations for noise. Filter is not needed if
SGMII/SRIO/PCIE is not in use.
DVDD15
VDDR1
1.5-V DDR3 IO supply
Fixed supply at 1.5V
HyperLink SerDes regulator supply 1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
HyperLink is not in use.
VDDR2
VDDR3
VDDR4
PCIE SerDes regulator supply
SGMII SerDes regulator supply
SRIO SerDes regulator supply
1.5 V
1.5 V
1.5 V
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIe
is not in use.
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if
SGMII is not in use.
Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SRIO
is not in use.
DVDD18
AVDDA1
AVDDA2
AVDDA3
VREFSSTL
VSS
1.8-V IO supply
1.8V
Fixed supply at 1.8V
Main PLL supply
DDR3 PLL supply
PASS PLL supply
0.75-V DDR3 reference voltage
Ground
1.8 V
1.8 V
1.8 V
0.75 V
GND
Filtered version of DVDD18. Special considerations for noise.
Filtered version of DVDD18. Special considerations for noise.
Filtered version of DVDD18. Special considerations for noise.
Should track the 1.5-V supply. Use 1.5 V as source.
Ground
End of Table 7-1
120
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.2.1 Power-Supply Sequencing
This section defines the requirements for a power up sequencing from a power-on reset condition. There are two
acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO
voltages as shown below.
1. CVDD
2. CVDD1, VDDT1-2
3. DVDD18, AVDD1, AVDD2
4. DVDD15, VDDR1-4
The second sequence provides compatibility with other TI processors with the IO voltage starting before the core
voltages as shown below.
1. DVDD18, AVDD1, AVDD2
2. CVDD
3. CVDD1, VDDT1-2
4. DVDD15, VDDR1-4
The clock input buffers for CORECLK, DDRCLK, PASSCLK, SRIOSGMIICLK, PCIECLK and MCMCLK
use CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until
CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the
device. Once CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either
high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the
clock inputs should be removed from the high impedance state shortly after CVDD is present.
If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled to ground
through a 1K ohm resistor. The P leg should be tied to CVDD to ensure it won't have any voltage present until
CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be
driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could
cause damage to the device.
The device initialization is broken into two phases. The first phase consists of the time period from the activation of
the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the
sequencing scenarios described above can be implemented during this phase. The figures below show both the
core-before-IO voltage sequence and the IO-before-core voltage sequence. POR must be held low for the entire
power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of RESETFULL
will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must
always go inactive before RESETFULL goes inactive as described below. REFCLK in the following section refers to
the clock input that has been selected as the source for the main PLL and SYSCLK1 refers to the main PLL output
that is used by the CorePac, see Figure 7-7 for more details.
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Multicore Fixed and Floating-Point Digital Signal Processor
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7.2.1.1 Core-Before-IO Power Sequencing
Figure 7-1 shows the power sequencing and reset control of TMS320C6678 for device initialization. POR may be
removed after the power has been stable for the required 100 μsec. RESETFULL must be held low for a period after
the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the
GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified.
REFCLK must always be active before POR can be removed. Core-before-IO power sequencing is defined in
Table 7-2.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20ms.
Figure 7-1
Core Before IO Power Sequencing
Power Stabilization Phase Device Initialization Phase
POR
7
RESETFULL
8
GPIO Config
Bits
4b
9
10
RESET
CVDD
2c
1
6
2a
CVDD1
3
DVDD18
4a
DVDD15
5
REFCLKP&N
DDRCLKP&N
2b
RESETSTAT
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Table 7-2
Core Before IO Power Sequencing
Time
System State
1
Begin Power Stabilization Phase
• CVDD (core AVS) ramps up.
• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset (created from
POR) is put into the reset state.
• Once enabled, the power supply should ramp to its valid voltage level within 20 ms.
2a
• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is
permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will
ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core
constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.
• The maximum duration is 100ms.
2b
2c
3
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or be held in a static state with one leg high and one leg low.
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t6.
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin
before DVDD18 is valid could cause damage to the device.
4a
4b
5
• DVDD15 (1.5 V) supply is ramped up after DVDD18 is valid. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the
voltage for DVDD15 must never exceed DVDD18.
• RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before POR is driven
high.
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
6
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec, so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
7
8
• RESETFULL must be held low for at least 24 transitions of the REFCLK after POR has stabilized at a high level.
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
9
• GPIO configuration bits must be valid for at least 12 transitions of the REFCLK before the rising edge of RESETFULL
• GPIO configuration bits must be held valid for at least 12 transitions of the REFCLK after the rising edge of RESETFULL
10
End of Table 7-2
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Peripheral Information and Electrical Specifications 123
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.2.1.2 IO-Before-Core Power Sequencing
The timing diagram for IO-before-core power sequencing is shown in Figure 7-2 and defined in Table 7-3.
Note—TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail
in the sequence starting to ramp. Each supply must ramp monotonically and must reach a stable valid level
within 20ms.
Figure 7-2
IO Before Core Power Sequencing
Power Stabilization Phase Device Initialization Phase
POR
5
7
RESETFULL
8
GPIO Config
Bits
2a
9
10
RESET
CVDD
3c
2b
6
3a
CVDD1
1
DVDD18
4
DVDD15
3b
REFCLKP&N
DDRCLKP&N
RESETSTAT
124
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-3
IO Before Core Power Sequencing
Time
System State
Begin Power Stabilization Phase
1
• Because POR is low, all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must
remain low through Power Stabilization Phase.
• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.
• RESETSTAT is driven low once the DVDD18 supply is available.
• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before
DVDD18 could cause damage to the device.
• Once enabled, the power supply should ramp to its valid voltage level within 20 ms.
2a
2b
• RESET may be driven high anytime after DVDD18 is at a valid level.
• CVDD (core AVS) ramps up.
• The maximum duration is 100ms.
3a
• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the
voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.
• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure
that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant)
ramps up before CVDD (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1.
3b
3c
• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be
driven with a valid clock or held in a static state with one leg high and one leg low.
• The DDRCLK and REFCLK may begin to toggle anytime between when CVDD is at a valid level and the setup time before POR goes high
specified by t6.
4
5
• DVDD15 (1.5 V) supply is ramped up after CVDD1 is valid.
• POR must continue to remain low for at least 100 μs after power has stabilized.
End Power Stabilization Phase
6
Begin Device Initialization
• Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33.33 nsec so a delay
of an additional 16 μs is required before a rising edge of POR. The clock must be active during the entire 16 μs.
• POR must remain low.
7
8
• RESETFULL is held low for at least 24 transitions of the REFCLK after POR has stabilized at a high level.
• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.
• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000
clock cycles.
End Device Initialization Phase
9
• GPIO configuration bits must be valid for at least 12 transitions of the REFCLK before the rising edge of RESETFULL
• GPIO configuration bits must be held valid for at least 12 transitions of the REFCLK after the rising edge of RESETFULL
10
End of Table 7-3
7.2.1.3 Prolonged Resets
Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of
the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for
more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the
reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation
state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the
device.
7.2.1.4 Clocking During Power Sequencing
Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the
clocks is contingent on the state of the boot configuration pins. Table 7-4 describes the clock sequencing and the
conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until
CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the
other connected to CVDD.
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Multicore Fixed and Floating-Point Digital Signal Processor
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Table 7-4
Clock Sequencing
Clock
Condition
None
Sequencing
DDRCLK
CORECLK
Must be present 16 μsec before POR transitions high.
CORECLK used to clock the core PLL. It must be present 16 μsec before POR transitions high.
PASSCLK is not used and should be tied to a static state.
None
PASSCLKSEL = 0
PASSCLKSEL = 1
PASSCLK
PASSCLK is used as a source for the PASS PLL. It must be present before the PASS PLL is removed from
reset and programmed.
An SGMII port will be used.
SRIOSGMIICLK must be present 16 μsec before POR transitions high.
SGMII will not be used. SRIO SRIOSGMIICLK must be present 16 μsec before POR transitions high.
will be used as a boot device.
SRIOSGMIICLK
SGMII will not be used. SRIO SRIOSGMIICLK is used as a source to the SRIO SERDES PLL. It must be present before the SRIO is
will be used after boot.
removed from reset and programmed.
SGMII will not be used. SRIO SRIOSGMIICLK is not used and should be tied to a static state.
will not be used.
PCIE will be used as a boot
device.
PCIECLK must be present 16 μsec before POR transitions high.
PCIECLK
PCIE will be used after boot. PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from
reset and programmed.
PCIE will not be used.
PCIECLK is not used and should be tied to a static state.
HyperLink will be used as a
boot device.
MCMCLK must be present 16usec before POR transitions high.
MCMCLK
HyperLink will be used after MCMCLK is used as a source to the MCM SERDES PLL. It must be present before the HyperLink is
boot. removed from reset and programmed.
HyperLink will not be used. MCMCLK is not used and should be tied to a static state.
End of Table 7-4
7.2.2 Power-Down Sequence
The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a
large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the
supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail,
POR should transition to low to prevent over-current conditions that could possibly impact device reliability.
A system power monitoring solution is needed to shut down power to the board if a power supply fails. Long-term
exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability
of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an
active reset can also affect long term reliability.
7.2.3 Power Supply Decoupling and Bulk Capacitors
In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are
required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or
bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply
Decoupling and Bulk capacitors see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation
from Texas Instruments’’ on page 73.
126
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Multicore Fixed and Floating-Point Digital Signal Processor
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www.ti.com
7.2.4 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor structures
responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the
leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios.
This static power consumption is mainly determined by transistor type and process technology. Higher clock rates
also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a
specific usage scenario, clock rates, and I/O activity.
Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the TMS320C6678 device is a feature that allows the core
voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each
TMS320C6678 device.
To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required
to be implemented whenever the TMS320C6678 device is used. The voltage selection is done using 4 VCNTL pins,
which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices application
report and the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’
on page 73.
Table 7-5
(see Figure 7-3)
SmartReflex 4-Pin VID Interface Switching Characteristics
No.
Parameter
Delay Time - VCNTL[2:0] valid after VCNTL[3] low
Min
Max
300.00
Unit
ns
1
2
3
4
5
td(VCNTL[2:0]-VCNTL[3])
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low
0.07 172020C (1)
ms
ns
td(VCNTL[2:0]-VCNTL[3])
Delay Time - VCNTL[2:0] valid after VCNTL[3] high
300.00
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high
VCNTL being valid to CVDD being switched to SmartReflex Voltage (2)
0.07
172020C
10
ms
ms
End of Table 7-5
1
C = 1/SYSCLK1 frequency in ms
2 SmartReflex voltage needs to be set before execution of application code
Figure 7-3
SmartReflex 4-Pin VID Interface Timing
1.1 V
SRV*
* SRV = Smart Reflex Voltage
CVDD
4
5
VCNTL[3]
1
3
VCNTL[2:0]
LSB VID[2:0]
MSB VID[5:3]
2
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7.3 Power Sleep Controller (PSC)
The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating
off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several
important power and clock operations.
For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
7.3.1 Power Domains
The device has several power domains that can be turned on for operation or off to minimize power dissipation. The
global power/sleep controller (GPSC) is used to control the power gating of various power domains.
Table 7-6 shows the TMS320C6678 power domains.
Table 7-6
Power Domains
Domain
Block(s)
Note
Power Connection
Always on
0
Most peripheral logic
Per-core TETB and System TETB
Packet Coprocessor
PCIe
Cannot be disabled
RAMs can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Logic can be powered down
Reserved
1
Software control
Software control
Software control
Software control
Software control
Reserved
2
3
4
SRIO
5
HyperLink
6
Reserved
7
MSMC RAM
MSMC RAM can be powered down
L2 RAMs can sleep
Software control
8
C66x CorePac0, L1/L2 RAMs
C66x CorePac1, L1/L2 RAMs
C66x CorePac2, L1/L2 RAMs
C66x CorePac3, L1/L2 RAMs
C66x CorePac4, L1/L2 RAMs
C66x CorePac5, L1/L2 RAMs
C66x CorePac6, L1/L2 RAMs
C66x CorePac7, L1/L2 RAMs
9
L2 RAMs can sleep
10
11
12
13
14
15
L2 RAMs can sleep
L2 RAMs can sleep
Software control via C66x core. For details, see the
C66x CorePac Reference Guide.
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
L2 RAMs can sleep
End of Table 7-6
128
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Multicore Fixed and Floating-Point Digital Signal Processor
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7.3.2 Clock Domains
Cock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module. For
modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and
disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls
the clock gating.
Table 7-7 shows the TMS320C6678 clock domains.
Table 7-7
Clock Domains
Module(s)
LPSC Number
Notes
0
Shared LPSC for all peripherals other than those listed in this table
Always on
1
SmartReflex
Always on
2
DDR3 EMIF
Always on
3
EMIF16 and SPI
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Software control
Reserved
4
TSIP
5
Debug Subsystem and Tracers
Per-core TETB and System TETB
Packet Accelerator
Ethernet SGMIIs
6
7
8
9
Security Accelerator
PCIe
10
11
SRIO
12
HyperLink
13
Reserved
14
MSMC RAM
Software control
Always on
15
C66x CorePac0 and Timer 0
C66x CorePac1 and Timer 1
C66x CorePac2 and Timer 2
C66x CorePac3 and Timer 3
C66x CorePac4 and Timer 4
C66x CorePac5 and Timer 5
C66x CorePac6 and Timer 6
C66x CorePac7 and Timer 7
Bootcfg, PSC, and PLL controller
16
Always on
17
Always on
18
Always on
19
Always on
20
Always on
21
Always on
22
Always on
No LPSC
These modules do not use LPSC
End of Table 7-7
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Multicore Fixed and Floating-Point Digital Signal Processor
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7.3.3 PSC Register Memory Map
Table 7-8 shows the PSC Register memory map.
Table 7-8
PSC Register Memory Map (Part 1 of 3)
Offset
0x000
Register
PID
Description
Peripheral Identification Register
0x004 - 0x010
0x014
Reserved
VCNTLID
Reserved
PTCMD
Reserved
Voltage Control Identification Register (1)
0x018 - 0x11C
0x120
Reserved
Power Domain Transition Command Register
Reserved
0x124
Reserved
PTSTAT
0x128
Power Domain Transition Status Register
Reserved
0x12C - 0x1FC
0x200
Reserved
PDSTAT0
PDSTAT1
PDSTAT2
PDSTAT3
PDSTAT4
PDSTAT5
PDSTAT6
PDSTAT7
PDSTAT8
PDSTAT9
PDSTAT10
PDSTAT11
PDSTAT12
PDSTAT13
PDSTAT14
PDSTAT15
Reserved
PDCTL0
Power Domain Status Register 0 (AlwaysOn)
Power Domain Status Register 1 (Per-core TETB and System TETB)
Power Domain Status Register 2 (Packet Coprocessor)
Power Domain Status Register 3 (PCIe)
0x204
0x208
0x20C
0x210
Power Domain Status Register 4 (SRIO)
Power Domain Status Register 5 (HyperLink)
Power Domain Status Register 6 (Reserved)
Power Domain Status Register 7 (MSMC RAM)
Power Domain Status Register 8 (C66x CorePac0)
Power Domain Status Register 9 (C66x CorePac1)
Power Domain Status Register 10 (C66x CorePac2)
Power Domain Status Register 11 (C66x CorePac3)
Power Domain Status Register 12 (C66x CorePac4)
Power Domain Status Register 13 (C66x CorePac5)
Power Domain Status Register 14 (C66x CorePac6)
Power Domain Status Register 15 (C66x CorePac7)
Reserved
0x214
0x218
0x21C
0x220
0x224
0x228
0x22C
0x230
0x234
0x238
0x23C
0x240 - 0x2FC
0x300
Power Domain Control Register 0 (AlwaysOn)
Power Domain Control Register 1 (Per-core TETB and System TETB)
Power Domain Control Register 2 (Packet Coprocessor)
Power Domain Control Register 3 (PCIe)
Power Domain Control Register 4 (SRIO)
Power Domain Control Register 5 (HyperLink)
Power Domain Control Register 6 (Reserved)
Power Domain Control Register 7 (MSMC RAM)
Power Domain Control Register 8 (C66x CorePac0)
Power Domain Control Register 9 (C66x CorePac1)
Power Domain Control Register 10 (C66x CorePac2)
Power Domain Control Register 11 (C66x CorePac3)
Power Domain Control Register 12 (C66x CorePac4)
Power Domain Control Register 13 (C66x CorePac5)
Power Domain Control Register 14 (C66x CorePac6)
Power Domain Control Register 15 (C66x CorePac7)
0x304
PDCTL1
0x308
PDCTL2
0x30C
PDCTL3
0x310
PDCTL4
0x314
PDCTL5
0x318
PDCTL6
0x31C
PDCTL7
0x320
PDCTL8
0x324
PDCTL9
0x328
PDCTL10
PDCTL11
PDCTL12
PDCTL13
PDCTL14
PDCTL15
0x32C
0x330
0x334
0x338
0x33C
130
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Table 7-8
PSC Register Memory Map (Part 2 of 3)
Offset
0x340 - 0x7FC
0x800
0x804
0x808
0x80C
0x810
0x814
0x818
0x81C
0x820
0x824
0x828
0x82C
0x830
0x834
0x838
0x83C
0x840
0x844
0x848
0x84C
0x850
0x854
0x858
0x85C - 0x9FC
0xA00
0xA04
0xA08
0xA0C
0xA10
0xA14
0xA18
0xA1C
0xA20
0xA24
0xA28
0xA2C
0xA30
0xA34
0xA38
0xA3C
0xA40
0xA44
0xA48
Register
Description
Reserved
MDSTAT0
MDSTAT1
MDSTAT2
MDSTAT3
MDSTAT4
MDSTAT5
MDSTAT6
MDSTAT7
MDSTAT8
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
MDSTAT13
MDSTAT14
MDSTAT15
MDSTAT16
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
Reserved
MDCTL0
Reserved
Module Status Register 0 (Never Gated)
Module Status Register 1 (SmartReflex)
Module Status Register 2 (DDR3 EMIF)
Module Status Register 3 (EMIF16 and SPI)
Module Status Register 4 (TSIP)
Module Status Register 5 (Debug Subsystem and Tracers)
Module Status Register 6 (Per-core TETB and System TETB)
Module Status Register 7 (Packet Accelerator)
Module Status Register 8 (Ethernet SGMIIs)
Module Status Register 9 (Security Accelerator)
Module Status Register 10 (PCIe)
Module Status Register 11 (SRIO)
Module Status Register 12 (HyperLink)
Module Status Register 13 (Reserved)
Module Status Register 14 (MSMC RAM)
Module Status Register 15 (C66x CorePac0 and Timer 0)
Module Status Register 16 (C66x CorePac1 and Timer 1)
Module Status Register 17 (C66x CorePac2 and Timer 2)
Module Status Register 18 (C66x CorePac3 and Timer 3)
Module Status Register 19 (C66x CorePac4 and Timer 4)
Module Status Register 20 (C66x CorePac5 and Timer 5)
Module Status Register 21 (C66x CorePac6 and Timer 6)
Module Status Register 22 (C66x CorePac7 and Timer 7)
Reserved
Module Control Register 0 (Never Gated)
Module Control Register 1 (SmartReflex)
MDCTL1
MDCTL2
Module Control Register 2 (DDR3 EMIF)
MDCTL3
Module Control Register 3 (EMIF16 and SPI)
Module Control Register 4 (TSIP)
MDCTL4
MDCTL5
Module Control Register 5 (Debug Subsystem and Tracers)
Module Control Register 6 (Per-core TETB and System TETB)
Module Control Register 7 (Packet Accelerator)
Module Control Register 8 (Ethernet SGMIIs)
Module Control Register 9 (Security Accelerator)
Module Control Register 10 (PCIe)
MDCTL6
MDCTL7
MDCTL8
MDCTL9
MDCTL10
MDCTL11
MDCTL12
MDCTL13
MDCTL14
MDCTL15
MDCTL16
MDCTL17
MDCTL18
Module Control Register 11 (SRIO)
Module Control Register 12 (HyperLink)
Module Control Register 13 (Reserved)
Module Control Register 14 (MSMC RAM)
Module Control Register 15 (C66x CorePac0 and Timer 0)
Module Control Register 16 (C66x CorePac1 and Timer 1)
Module Control Register 17 (C66x CorePac2 and Timer 2)
Module Control Register 18 (C66x CorePac3 and Timer 3)
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Table 7-8
PSC Register Memory Map (Part 3 of 3)
Offset
Register
MDCTL19
MDCTL20
MDCTL21
MDCTL22
Reserved
Description
0xA4C
Module Control Register 19 (C66x CorePac4 and Timer 4)
Module Control Register 20 (C66x CorePac5 and Timer 5)
Module Control Register 21 (C66x CorePac6 and Timer 6)
Module Control Register 22 (C66x CorePac7 and Timer 7)
Reserved
0xA50
0xA54
0xA58
0xA5C - 0xFFC
End of Table 7-8
1 VCNTLID register is available for debug purpose only.
7.4 Reset Controller
The reset controller detects the different type of resets supported on the TMS320C6678 device and manages the
distribution of those resets throughout the device.
The device has several types of resets:
•
•
•
•
Power-on reset
Hard reset
Soft reset
CPU local reset
Table 7-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section ‘‘Reset Electrical Data /
Timing’’ on page 137
Table 7-9
Reset Types
Reset Type
Initiator
Effect on Device When Reset Occurs
RESETSTAT Pin Status
POR (Power On Reset) POR pin active low
RESETFULL pin active low
Total reset of the chip. Everything on the device is reset to its default
state in response to this. Activates the POR signal on chip, which is used
to reset test/emu logic. Boot configurations are latched. ROM boot
process is initiated.
Toggles RESETSTAT pin
Hard Reset
RESET pin active low
Resets everything except for test/emu logic and reset isolation
modules. Emulator and reset Isolation modules stay alive during this
reset. This reset is also different from POR in that the PLLCTL assumes
power and clocks are stable when device reset is asserted. Boot
configurations are not latched. ROM boot process is initiated.
Toggles RESETSTAT pin
Toggles RESETSTAT pin
Emulation
PLLCTL register (RSCTRL)
Watchdog timers
Soft Reset
RESET pin active low
PLLCTL register (RSCTRL)
Watchdog timers
Software can program these initiators to be hard or soft. Hard reset is
the default, but can be programmed to be soft reset. Soft reset will
behave like hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs, the
sticky bits in PCIe MMRs, and external memory contents are retained.
Boot configurations are not latched. ROM boot process is initiated.
C66x CorePac
local reset
Software (through
LPSC MMR)
MMR bit in LPSC controls C66x CorePac local reset. Used by watchdog Does not toggle
timers (in the event of a timeout) to reset C66x CorePac. Can also be
initiated by LRESET device pin. C66x CorePac memory system and slave
DMA port are still alive when C66x CorePac is in local reset. Provides a
local reset of the C66x CorePac, without destroying clock alignment or
memory contents. Does not initiate ROM boot process.
RESETSTAT pin
Watchdog timers
LRESET pin
End of Table 7-9
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7.4.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device
including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR,
RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on
reset, the Main PLL Controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the
state of the PLL or the dividers in the PLL controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are
power managed, are disabled after a Power-on Reset and must be enabled through the Device State Control
registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 75).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional time for the
Chip level PLLs to lock.
4. The POR pin can now be de-asserted. Reset sampled pin values are latched at this point. The Chip level PLLs
is taken out of reset and begins its locking sequence, and all power-on device initialization also begins.
5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, DDR3
PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL
controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system
reference clocks. After the pause, the system clocks are restarted at their default divide by settings.
6. The device is now out of reset and device execution begins as dictated by the selected boot mode.
Note—To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted
(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period
of the POR pin, most of the device will remain in reset. The RESET pin should not be tied together with the
POR pin.
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7.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules.
POR should also remain de-asserted during this time.
Hard reset is initiated by the following
•
•
•
•
RESET pin
RSCTRL register in PLLCTL
Watchdog timer
Emulation
All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can
be configured as soft resets in the RSCFG register in PLLCTL.
The following sequence must be followed during a hard reset:
1. The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is
able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules
affected by RESET, to prevent off-chip contention during the warm reset.
2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
together with the POR pin.
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7.4.3 Soft Reset
A soft reset will behave like a hard reset except that EMIF16 MMRs, DDR3 EMIF MMRs and the PCIe MMRs sticky
bits, and external memory contents are retained. POR should also remain de-asserted during this time.
Soft reset is initiated by the following
•
•
•
RESET pin
RSCTRL register in PLLCTL
Watchdog timer
All the above initiators by default are configured to act as hard reset. Except emulation, all the other 3 initiators can
be configured as soft resets in the RSCFG register in PLLCTL.
In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore,
the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers
are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in
self-refresh mode before invoking the soft reset.
During a soft reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate
through the system. Internal system clocks are not affected. PLLs also remain locked.
2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the PLL
controllers pause their system clocks for about 8 cycles.
At this point:
›
›
›
The state of the peripherals before the soft reset is not changed.
The I/O pins are controlled as dictated by the DEVSTAT register.
The DDR3 MMRs and the PCIe MMRs sticky bits retain their previous values. Only the DDR3
Memory Controller and PCIe state machines are reset by the soft reset.
›
The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.
The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with
a System Reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.
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7.4.4 Local Reset
The local reset can be used to reset a particular CorePac without resetting any other chip components.
Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) for KeyStone Devices User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73:
•
•
LRESET pin
Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and RSTCFG
register in the PLL controller. See ‘‘Reset Configuration Register (RSTCFG)’’ on page 147 and ‘‘CIC Registers’’
on page 181:
–
–
–
–
Local reset
NMI
NMI followed by a time delay and then a local reset for the CorePac selected
Hard Reset by requesting reset via PLLCTL
•
LPSC MMRs (memory-mapped registers)
7.4.5 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request.
The reset request priorities are as follows (high to low):
•
•
Power-on reset
Hard/soft reset
7.4.6 Reset Controller Register
The reset controller register are part of the PLLCTL MMRs. All C6678 device-specific MMRs are covered in Section
7.5.3 ‘‘Main PLL Control Register’’ on page 148. For more details on these registers and how to program them, see
the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 73.
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7.4.7 Reset Electrical Data / Timing
Table 7-10
Reset Timing Requirements (1)
(see Figure 7-4 and Figure 7-5)
No.
Min
Max Unit
RESETFULL Pin Reset
Pulse width - Pulse width RESETFULL low
Soft/Hard-Reset
Pulse width - Pulse width RESET low
1
2
tw(RESETFULL)
tw(RESET)
500C
500C
ns
ns
End of Table 7-10
1
C = 1/SYSCLK1 frequency in ns.
Table 7-11
Reset Switching Characteristics Over Recommended Operating Conditions (1)
(see Figure 7-4 and Figure 7-5)
No.
Parameter
RESETFULL Pin Reset
Min
Max Unit
3
4
td(RESETFULLH-RESETSTATH)
td(RESETH-RESETSTATH)
Delay time - RESETSTAT high after RESETFULL high
50000C ns
50000C ns
Soft/Hard Reset
Delay time - RESETSTAT high after RESET high
End of Table 7-11
1
C = 1/SYSCLK1 frequency in ns.
Figure 7-4
RESETFULL Reset Timing
POR
RESETFULL
RESET
1
3
RESETSTAT
Figure 7-5
Soft/Hard-Reset Timing
POR
RESETFULL
2
RESET
4
RESETSTAT
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Table 7-12
(See Figure 7-6)
Boot Configuration Timing Requirements (1)
No.
Min
12C
12C
Max Unit
1
2
tsu(GPIOn-RESETFULL)
th(RESETFULL-GPIOn)
Setup time - GPIO valid before RESETFULL asserted
ns
ns
Hold time - GPIO valid after RESETFULL asserted
End of Table 7-12
1 C = 1/SYSCLK1 frequency in ns.
Figure 7-6
Boot Configuration Timing
POR
1
RESETFULL
GPIO[15:0]
2
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7.5 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL Controller. For details on the operation of the PLL
Controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation
from Texas Instruments’’ on page 73.
The Main PLL is controlled by the standard PLL Controller. The PLL controller manages the clock ratios, alignment,
and gating for the system clocks to the device. Figure 7-7 shows a block diagram of the main PLL and the PLL
Controller.
Figure 7-7
Main PLL and PLL Controller
PLL
PLLD xPLLM /2
CORECLK(N|P)
0
1
PLLOUT
OUTPUT
DIVIDE
BYPASS
PLL Controller
/1
1
0
SYSCLK1
C66x
CorePac
PLLDIV1
/x
/2
/3
/y
1
0
0
PLLDIV2
PLLDIV3
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
PLLDIV8
PLLDIV9
PLLDIV10
PLLDIV11
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
SYSCLK8
SYSCLK9
SYSCLK10
SYSCLK11
PLLEN
PLLENSRC
/64
/6
To Switch Fabric,
Peripherals,
Accelerators
/z
/12
/3
/6
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Note—The Main PLL Controller registers can be accessed by any master in the device. The PLLM[5:0] bits
of the multiplier are controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are
controlled by the chip-level MAINPLLCTL0 register. The Output Divide and Bypass logic of the PLL are
controlled by fields in the SECCTL register in the PLL controller. Only PLLDIV2, PLLDIV5, and PLLDIV8
are programmable on the C6678 device. See the Phase Locked Loop (PLL) for KeyStone Devices User Guide
in ‘‘Related Documentation from Texas Instruments’’ on page 73 for more details on how to program the
PLL controller.
The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are
determined by a combination of this PLL and the PLL Controller. The PLL controller also controls reset propagation
through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an
output signal indicating when the PLL is locked.
Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 73 for detailed recommendations. For the best performance, TI
recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces
and the PLL external components (C1, C2, and the EMI Filter).
The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see
Section 7.5.5 ‘‘Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing’’.
CAUTION—The PLL controller module as described in the see the Phase Locked Loop (PLL) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73 includes a superset of
features, some of which are not supported on the TMS320C6678 device. The following sections describe the
registers that are supported; it should be assumed that any registers not included in these sections is not
supported by the device. Furthermore, only the bits within the registers described here are supported. Avoid
writing to any reserved memory location or changing the value of reserved bits.
7.5.1 Main PLL Controller Device-Specific Information
7.5.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the
DDR3 and the network coprocessor (PASS)) requires a PLL controller to manage the various clock divisions, gating,
and synchronization. The Main PLL Controller has several SYSCLK outputs that are listed below, along with the
clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note
that dividers are not programmable unless explicitly mentioned in the description below.
•
•
SYSCLK1: Full-rate clock for the CorePacs.
SYSCLK2: 1/x-rate clock for CorePac (emulation). Default rate for this will be 1/3. This is programmable from
/1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.
•
•
•
SYSCLK3: 1/2-rate clock used to clock the MSMC, HyperLink, CPU/2 TeraNet, DDR EMIF and CPU/2
EDMA.
SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs will use this as
well.
SYSCLK5: 1/y-rate clock for system trace module only. Default rate for this will be 1/5. It is configurable and
the max configurable clock is 210 MHz and min configuration clock is 32 MHz. The SYSCLK5 can be turned
off by software.H
•
SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT compensated buffers for DDR3
EMIF.
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•
•
SYSCLK7: 1/6-rate clock for slow peripherals and sources the SYSCLKOUT output pin.
SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclk in the system. Default for this will be 1/64. This is
programmable from /24 to /80.
•
•
•
SYSCLK9: 1/12-rate clock for SmartReflex.
SYSCLK10: 1/3-rate clock for SRIO only.
SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on theTMS320C6678 device.
Note—In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then SYSCLK8
(SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the
system.
7.5.1.2 Main PLL Controller Operating Modes
The Main PLL Controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by BYPASS bit of the PLL Secondary control register (SECCTL). In PLL mode, SYSCLK1 is generated
from the PLL output using the values set in PLLM and PLLD bit fields in the MAINPLLCTL0 register. In bypass
mode, PLL input is fed directly out as SYSCLK1.
All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must
be in place such that the DSP notifies the host when the PLL configuration has completed.
7.5.1.3 Main PLL Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become
stable after device powerup. The PLL should not be operated until this stabilization time has elapsed.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the
PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the Main PLL reset time value,
see Table 7-13.
The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1) to when to
when the PLL Controller can be switched to PLL mode. The Main PLL lock time is given in Table 7-13.
Table 7-13
Main PLL Stabilization, Lock, and Reset Times
Min
Typ
Max
Unit
PLL stabilization time
PLL lock time
100
μs
(2)
500×(PLLD (1)+1)×C
PLL reset time
1000
ns
End of Table 7-13
1 PLLD is the value in PLLD bit fields of MAINPLLCTL0 register
2 C = SYSCLK1 cycle time in ns.
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7.5.2 PLL Controller Memory Map
The memory map of the PLL Controller is shown in Table 7-14. TMS320C6678-specific PLL Controller register
definitions can be found in the sections following Table 7-14. For other registers in the table, see the Phase Locked
Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
CAUTION—Note that only registers documented here are accessible on the TMS320C6678. Other addresses
in the PLL Controller memory map including the reserved registers should not be modified. Furthermore,
only the bits within the registers described here are supported. Avoid writing to any reserved memory
location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to
make any changes to the valid bits in the register.
Table 7-14
PLL Controller Registers (Including Reset Controller) (Part 1 of 2)
Hex Address Range
0231 0000 - 0231 00E3
0231 00E4
Field
-
Register Name
Reserved
RSTYPE
RSTCTRL
RSTCFG
RSISO
-
Reset Type Status Register (Reset Controller)
Software Reset Control Register (Reset Controller)
Reset Configuration Register (Reset Controller)
Reset Isolation Register (Reset Controller)
Reserved
0231 00E8
0231 00EC
0231 00F0
0231 00F0 - 0231 00FF
0231 0100
PLLCTL
-
PLL Control Register
Reserved
0231 0104
0231 0108
SECCTL
-
PLL Secondary Control Register
Reserved
0231 010C
0231 0110
PLLM
-
PLL Multiplier Control Register
Reserved
0231 0114
0231 0118
PLLDIV1
PLLDIV2
PLLDIV3
-
Reserved
0231 011C
PLL Controller Divider 2 Register
Reserved
0231 0120
0231 0124
Reserved
0231 0128
-
Reserved
0231 012C - 0231 0134
0231 0138
-
Reserved
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
CKSTAT
SYSTAT
-
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
0231 013C
0231 0140
0231 0144
0231 0148
0231 014C
Reserved
0231 0150
SYSCLK Status Register
Reserved
0231 0154 - 0231 015C
0231 0160
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
PLLDIV8
Reserved
0231 0164
PLL Controller Divider 5 Register
Reserved
0231 0168
0231 016C
Reserved
0231 0170
PLL Controller Divider 8 Register
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Table 7-14
PLL Controller Registers (Including Reset Controller) (Part 2 of 2)
Hex Address Range
0231 0174 - 0231 0193
0231 0194 - 0231 01FF
End of Table 7-14
Field
Register Name
Reserved
PLLDIV9 - PLLDIV16
-
Reserved
7.5.2.1 PLL Secondary Control Register (SECCTL)
The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in Figure 7-8 and
described in Table 7-15.
Figure 7-8
PLL Secondary Control Register (SECCTL))
31
24
23
22
19
18
0
Reserved
BYPASS
RW-0
OUTPUT DIVIDE
RW-0001
Reserved
RW-001 0000 0000 0000 0000
R-0000 0000
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-15
PLL Secondary Control Register (SECCTL) Field Descriptions
Description
Bit
Field
Reserved
31-24
23
Reserved
BYPASS
Main PLL Bypass Enable
0 = Main PLL Bypass disabled
1 = Main PLL Bypass enabled
22-19
OUTPUT DIVIDE
Output Divider ratio bits.
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h - Fh = Reserved.
18-0
Reserved
Reserved
End of Table 7-15
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7.5.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
The PLL controller divider registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in Figure 7-9 and described in
Table 7-16. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and PLLDIV8 are different and
mentioned in the footnote of Figure 7-9.
Figure 7-9
PLL Controller Divider Register (PLLDIVn)
31
16
15
14
8
7
0
Reserved
R-0
Dn (1) EN
Reserved
R-0
RATIO
R/W-1
R/W-n (2)
Legend: R/W = Read/Write; R = Read only; -n = value after reset
1 D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
2 n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8
Table 7-16
PLL Controller Divider Register (PLLDIVn) Field Descriptions
Description
Bit
Field
Reserved
31-16
15
Reserved.
DnEN
Divider Dn enable bit. (see footnote of Figure 7-9)
0 = Divider n is disabled.
1 = No clock output. Divider n is enabled.
14-8
7-0
Reserved
RATIO
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits. (see footnote of Figure 7-9)
0h = ÷1. Divide frequency by 1.
1h = ÷2. Divide frequency by 2.
2h = ÷3. Divide frequency by 3.
3h = ÷4. Divide frequency by 4.
4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.
End of Table 7-16
7.5.2.3 PLL Controller Clock Align Control Register (ALNCTL)
The PLL Controller clock align control register (ALNCTL) is shown in Figure 7-10 and described in Table 7-17.
Figure 7-10
PLL Controller Clock Align Control Register (ALNCTL)
31
8
7
6
5
4
3
2
1
0
Reserved
R-0
ALN8
R/W-1
Reserved
R-0
ALN5
R/W-1
Reserved
R-0
ALN2
R/W-1
Reserved
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-17
PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions
Bit
31-8
6-5
3-2
0
Field Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
ALN8
ALN5
ALN2
SYSCLKn alignment. Do not change the default values of these fields.
0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new
ratio immediately after the GOSET bit in PLLCMD is set.
1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1.
The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.
4
1
End of Table 7-17
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7.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
Whenever a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE
status register. During the GO operation, the PLL Controller will change only the divide ratio of the SYSCLKs with
the bit set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other
clocks. The PLLDIV divider ratio change status register is shown in Figure 7-11 and described in Table 7-18.
Figure 7-11
PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
8
7
6
5
4
3
2
1
0
Reserved
R-0
SYS8
R/W-0
Reserved
R-0
SYS5
R/W-0
Reserved
R-0
SYS2
R/W-0
Reserved
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-18
PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
31-8
6-5
3-2
0
Field Description
Reserved
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7
SYS8
SYS5
SYS2
Identifies when the SYSCLKn divide ratio has been modified.
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
4
1
End of Table 7-18
7.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in Figure 7-12 and
described in Table 7-19.
Figure 7-12
SYSCLK Status Register (SYSTAT)
31
11
10
SYS11ON SYS10ON SYS9ON SYS8ON SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON
R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1 R-1
9
8
7
6
5
4
3
2
1
0
Reserved
R-n
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-19
SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
Field Description
31-11
10-0
Reserved
SYS[N (1)]ON
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK[N] on status.
0 = SYSCLK[N] is gated.
1 = SYSCLK[N] is on.
End of Table 7-19
1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)
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7.5.2.6 Reset Type Status Register (RSTYPE)
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The Reset Type Status Register is shown in
Figure 7-13 and described in Table 7-20.
Figure 7-13
Reset Type Status Register (RSTYPE)
31
29
28
EMU-RST
R-0
27
12
11
8
7
3
2
1
0
Reserved
R-0
Reserved
R-0
WDRST[N]
R-0
Reserved
R-0
PLLCTRLRST
R-0
RESET
R-0
POR
R-0
Legend: R = Read only; -n = value after reset
Table 7-20
Reset Type Status Register (RSTYPE) Field Descriptions
Bit
Field
Description
31-29 Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
28
EMU-RST
Reset initiated by emulation.
0 = Not the last reset to occur.
1 = The last reset to occur.
27-12 Reserved
Reserved. Read only. Always reads as 0. Writes have no effect.
11
10
9
WDRST3
WDRST2
WDRST1
WDRST0
Reserved
PLLCTLRST
Reset initiated by watchdog timer[N].
0 = Not the last reset to occur.
1 = The last reset to occur.
8
7-3
2
Reserved. Read only. Always reads as 0. Writes have no effect.
Reset initiated by PLLCTL.
0 = Not the last reset to occur.
1 = The last reset to occur.
1
0
RESET
POR
RESET reset.
0 = RESET was not the last reset to occur.
1 = RESET was the last reset to occur.
Power-on reset.
0 = Power-on reset was not the last reset to occur.
1 = Power-on reset was the last reset to occur.
End of Table 7-20
7.5.2.7 Reset Control Register (RSTCTRL)
This register contains a key that enables writes to the MSB of this register and the RSTCFG register. The key value
is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the RSTCTRL or the RSTCFG
is written, the key is invalidated. Every write must be set up with a valid key. The Software Reset Control Register
(RSTCTRL) is shown in Figure 7-14 and described in Table 7-21.
Figure 7-14
Reset Control Register (RSTCTRL)
31
17
16
15
0
Reserved
R-0x0000
SWRST
R/W-0x (1)
KEY
R/W-0x0003
Legend: R = Read only; -n = value after reset;
1 Writes are conditional based on valid key.
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Table 7-21
Reset Control Register (RSTCTRL) Field Descriptions
Bit
Field
Description
31-17 Reserved
Reserved.
16
SWRST
Software reset
0 = Reset
1 = Not reset
15-0
KEY
Key used to enable writes to RSTCTRL and RSTCFG.
End of Table 7-21
7.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL Controller’s
RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets will be hard resets. The Reset
Configuration Register (RSTCFG) is shown in Figure 7-15 and described in Table 7-22.
Figure 7-15
Reset Configuration Register (RSTCFG)
31
14
13
12
11
4
3
0
(1)
Reserved
R-0
PLLCTLRSTTYPE
R/W-0 (2)
RESETTYPE
R/W-02
Reserved
R-0
WDTYPE[N
R/W-02
]
Legend: R = Read only; R/W = Read/Write; -n = value after reset
1 Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)
2 Writes are conditional based on valid key. For details, see Section 7.5.2.7 ‘‘Reset Control Register (RSTCTRL)’’.
Table 7-22
Reset Configuration Register (RSTCFG) Field Descriptions
Bit
Field
Description
31-14 Reserved
Reserved.
13
PLLCTLRSTTYPE PLL Controller initiates a software-driven reset of type:
0 = Hard reset (default)
1 = Soft reset
12
RESETTYPE
RESET initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset
11-4
Reserved
WDTYPE3
WDTYPE2
WDTYPE1
WDTYPE0
Reserved.
3
2
1
0
Watchdog timer [N] initiates a reset of type:
0 = Hard reset (default)
1 = Soft reset
End of Table 7-22
7.5.2.9 Reset Isolation Register (RSISO)
This register is used to select the module clocks that must maintain their clocking without pausing through non
power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current
values of PLL multiplier, divide ratios and other settings. Along with setting module specific bit in RSISO, the
corresponding MDCTLx[12] bit also needs to be set in PSC to reset isolate a particular module. For more
information on MDCTLx register see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in ‘‘Related
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Documentation from Texas Instruments’’ on page 73. The Reset Isolation Register (RSTCTRL) is shown in
Figure 7-16 and described in Table 7-23.
Figure 7-16
Reset Isolation Register (RSISO)
31
10
9
8
7
0
Reserved
R-0
SRIOISO
R/W-0
SRISO
R/W-0
Reserved
R-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 7-23
Reset Isolation Register (RSISO) Field Descriptions
Bit
Field
Description
31-10 Reserved
Reserved.
9
SRIOISO
Isolate SRIO module
0 = Not reset isolated
1 = Reset Isolated
8
SRISO
Isolate SmartReflex
0 = Not reset isolated
1 = Reset Isolated
7-0
Reserved
Reserved.
End of Table 7-23
Note—The boot ROM code will enable the reset isolation for both SRIO and SmartReflex modules during
boot with the Reset Isolation Register. It is up to the user application to disable.
7.5.3 Main PLL Control Register
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL Controller
for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go
through an un-locking sequence using KICK0/KICK1 registers. For valid configurable values into the
MAINPLLCTL0 and MAINPLLCTL1 registers see Section 2.5.4 ‘‘PLL Boot Configuration Settings’’ on page 41. See
section 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on page 81 for the address location of the registers
and locking and unlocking sequences for accessing the registers. The registers are reset on POR only.
Figure 7-17
Main PLL Control Register 0 (MAINPLLCTL0)
31
24
23
19
18
12
11
Reserved
RW-000000
6
5
0
BWADJ[7:0]
RW-0000 0101
Legend: RW = Read/Write; -n = value after reset
Reserved
PLLM[12:6]
PLLD
RW-000000
RW-0000 0
RW-0000000
Table 7-24
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions (Part 1 of 2)
Bit
Field Description
31-24
BWADJ[7:0]
BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM=15, then BWADJ=7
23-19
18-12
Reserved
Reserved
PLLM[12:6]
A 13-bit bus that selects the values for the multiplication factor (see Note below)
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Table 7-24
Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions (Part 2 of 2)
Bit
Field
Description
11-6
5-0
Reserved
PLLD
Reserved
A 6-bit bus that selects the values for the reference divider
End of Table 7-24
Figure 7-18
Main PLL Control Register 1 (MAINPLLCTL1)
31
7
6
5
4
3
0
Reserved
ENSAT
RW-0
Reserved
RW-00
BWADJ[11:8]
RW-0000
RW-0000000000000000000000000
Legend: RW = Read/Write; -n = value after reset
Table 7-25
Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
Description
Bit
31-7
6
Field
Reserved
Reserved
ENSAT
Needs to be set to 1 for proper operation of PLL
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in MAINPLLCTL0 and MAINPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM=15, then BWADJ=7
End of Table 7-25
Note—PLLM[5:0] bits of the multiplier is controlled by the PLLM register inside the PLL Controller
and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The MAINPLLCTL0 register
PLLM[12:6] bits should be written just before writing to the PLLM register PLLM[5:0] bits in the controller
to have the complete 13 bit value latched when the GO operation is initiated in the PLL controller. See the
Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 73 for the recommended programming sequence. Output divide ratio and Bypass
enable/disable of the Main PLL is controlled by the SECCTL register in the PLL Controller. See the
7.5.2.1 ‘‘PLL Secondary Control Register (SECCTL)’’ for more details.
7.5.4 Main PLL and PLL Controller Initialization Sequence
See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 73 for details on the initialization sequence for Main PLL and PLL Controller.
7.5.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
Table 7-26
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 1 of 3)
(see Figure 7-19 and Figure 7-20)
No.
Min
Max Unit
CORECLK[P:N]
1
1
3
2
2
tc(CORCLKN)
tc(CORECLKP)
tw(CORECLKN)
tw(CORECLKN)
tw(CORECLKP)
Cycle time _ CORECLKN cycle time
Cycle time _ CORECLKP cycle time
Pulse width _ CORECLKN high
Pulse width _ CORECLKN low
Pulse width _ CORECLKP high
3.2
3.2
25
25
ns
ns
ns
ns
ns
0.45*tc(CORECLKN)
0.45*tc(CORECLKN)
0.45*tc(CORECLKP)
0.55*tc(CORECLKN)
0.55*tc(CORECLKN)
0.55*tc(CORECLKP)
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Table 7-26
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 2 of 3)
(see Figure 7-19 and Figure 7-20)
No.
Min
Max Unit
3
4
tw(CORECLKP)
Pulse width _ CORECLKP low
0.45*tc(CORECLKP)
0.55*tc(CORECLKP)
ns
tr(CORECLK_250mv)
Transition time _ CORECLK differential rise time
(250mV)
50
50
350
ps
4
5
5
tf(CORECLK_250mv)
tj(CORECLKN)
Transition time _ CORECLK differential fall time (250mV)
Jitter, peak_to_peak _ periodic CORECLKN
Jitter, peak_to_peak _ periodic CORECLKP
SRIOSGMIICLK[P:N]
350
0.02*tc(CORECLKN)
0.02*tc(CORECLKP)
ps
ps
ps
tj(CORECLKP)
1
1
3
2
2
3
4
tc(SRIOSGMIICLKN)
tc(SRIOSGMIICLKP)
tw(SRIOSGMIICLKN)
tw(SRIOSGMIICLKN)
tw(SRIOSGMIICLKP)
tw(SRIOSGMIICLKP)
Cycle time _ SRIOSGMIICLKN cycle time
Cycle time _ SRIOSGMIICLKP cycle time
Pulse width _ SRIOSGMIICLKN high
Pulse width _ SRIOSGMIICLKN low
3.2 or 4 or 6.4
3.2 or 4 or 6.4
ns
ns
ns
ns
ns
ns
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
0.45*tc(SRIOSGMIICLKN) 0.55*tc(SRIOSGMIICLKN)
0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)
0.45*tc(SRIOSGMIICLKP) 0.55*tc(SRIOSGMIICLKP)
Pulse width _ SRIOSGMIICLKP high
Pulse width _ SRIOSGMIICLKP low
tr(SRIOSGMIICLK_
250mv)
Transition time _ SRIOSGMIICLK differential rise time
(250 mV)
50
50
350
ps
4
tf(SRIOSGMIICLK_
250mv)
Transition time _ SRIOSGMIICLK differential fall time
(250 mV)
350
ps
5
5
5
tj(SRIOSGMIICLKN)
tj(SRIOSGMIICLKP)
tj(SRIOSGMIICLKN)
Jitter, peak_to_peak _ periodic SRIOSGMIICLKN
Jitter, peak_to_peak _ periodic SRIOSGMIICLKP
4 (2) ps,RMS
4 (2) ps,RMS
Jitter, peak_to_peak _ periodic SRIOSGMIICLKN (SRIO
not used)
8 (2) ps,RMS
8 (2) ps,RMS
5
tj(SRIOSGMIICLKP)
Jitter, peak_to_peak _ periodic SRIOSGMIICLKP (SRIO
not used)
HyperLinkCLK[P:N]
Cycle time _ MCMCLKN cycle time
Cycle time _ MCMCLKP cycle time
Pulse width _ MCMCLKN high
1
1
3
2
2
3
4
4
5
5
tc(MCMCLKN)
tc(MCMCLKP)
3.2 or 4 or 6.4
3.2 or 4 or 6.4
ns
ns
tw(MCMCLKN)
tw(MCMCLKN)
tw(MCMCLKP)
tw(MCMCLKP)
tr(MCMCLK_250mv)
tf(MCMCLK_250mv)
tj(MCMCLKN)
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
ns
ns
ns
ns
ps
ps
Pulse width _ MCMCLKN low
0.45*tc(MCMCLKN)
0.55*tc(MCMCLKN)
0.55*tc(MCMCLKP)
0.55*tc(MCMCLKP)
350
Pulse width _ MCMCLKP high
0.45*tc(MCMCLKP)
Pulse width _ MCMCLKP low
0.45*tc(MCMCLKP)
Transition time _ MCMCLK differential rise time (250mV)
Transition time _ MCMCLK differential fall time (250mV)
Jitter, peak_to_peak _ periodic MCMCLKN
Jitter, peak_to_peak _ periodic MCMCLKP
PCIECLK[P:N]
50
50
350
4 (2) ps,RMS
4 (2) ps,RMS
tj(MCMCLKP)
1
1
3
2
2
3
4
4
tc(PCIECLKN)
Cycle time _ PCIECLKN cycle time
3.2 or 4 or 6.4 or 10
3.2 or 4 or 6.4 or 10
0.45*tc(PCIECLKN) 0.55*tc(PCIECLKN)
ns
ns
tc(PCIECLKP)
Cycle time _ PCIECLKP cycle time
tw(PCIECLKN)
tw(PCIECLKN)
tw(PCIECLKP)
Pulse width _ PCIECLKN high
ns
ns
ns
ns
ps
ps
Pulse width _ PCIECLKN low
0.45*tc(PCIECLKN)
0.45*tc(PCIECLKP)
0.45*tc(PCIECLKP)
50
0.55*tc(PCIECLKN)
0.55*tc(PCIECLKP)
0.55*tc(PCIECLKP)
350
Pulse width _ PCIECLKP high
tw(PCIECLKP)
Pulse width _ PCIECLKP low
tr(PCIECLK_250mv)
tf(PCIECLK_250mv)
Transition time _ PCIECLK differential rise time (250 mV)
Transition time _ PCIECLK differential fall time (250 mV)
50
350
150
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Table 7-26
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements (1) (Part 3 of 3)
(see Figure 7-19 and Figure 7-20)
No.
Min
Max Unit
4 (2) ps,RMS
4 (2) ps,RMS
5
5
tj(PCIECLKN)
tj(PCIECLKP)
Jitter, peak_to_peak _ periodic PCIECLKN
Jitter, peak_to_peak _ periodic PCIECLKP
End of Table 7-26
1 See the Hardware Design Guide for KeyStone devices in ‘‘Related Documentation from Texas Instruments’’ on page 73 for detailed recommendations.
2 The jitter frequency mask shown in the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation from Texas Instruments’’ on page 73 must also be met for
the specific operating mode chosen.
Figure 7-19
Figure 7-20
Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing
1
2
3
5
<CLK_NAME>CLKN
<CLK_NAME>CLKP
4
Main PLL Clock Input Transition Time
peak-to-peak differential input
250 mV peak-to-peak
0
voltage (250 mV to 2 V)
TR = 50 ps min to 350 ps max (10% to 90 %)
for the 250 mV peak-to-peak centered at zero crossing
7.6 DD3 PLL
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset,
DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.
DDR3 PLL power is supplied externally via the DDR3 PLL power-supply pin (AVDDA2). An external EMI filter
circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices in ‘‘Related
Documentation from Texas Instruments’’ on page 73. For the best performance, TI recommends that all the PLL
external components be on a single side of the board without jumpers, switches, or components other than those
shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL external
components (C1, C2, and the EMI filter).
Figure 7-21 shows the DDR3 PLL.
Figure 7-21
DDR3 PLL Block Diagram
DDR3 PLL
PLLD xPLLM /2
0
1
DDRCLK(N|P)
PLLOUT
DDR3
PHY
BYPASS
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7.6.1 DDR3 PLL Control Register
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. DDR3 PLL can
be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 registers located in the Bootcfg module. These MMRs
(memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through
an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.4 ‘‘PLL Boot
Configuration Settings’’ on page 41. See section 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on
page 81 for the address location of the registers and locking and unlocking sequences for accessing the registers. This
register is reset on POR only
.
Figure 7-22
DDR3 PLL Control Register 0 (DDR3PLLCTL0) (1)
31
24
23
22
Reserved
RW,+0001
19
18
6
5
0
BWADJ[7:0]
RW,+0000 1001
BYPASS
RW,+0
PLLM
PLLD
RW,+000000
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
Table 7-27
DDR3 PLL Control Register 0 Field Descriptions
Description
Bit
Field
BWADJ[7:0]
31-24
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM=15, then BWADJ=7
23
BYPASS
Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
22-19
18-6
5-0
Reserved
PLLM
Reserved
A 13-bit bus that selects the values for the multiplication factor
A 6-bit bus that selects the values for the reference divider
PLLD
End of Table 7-27
Figure 7-23
DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31
14
13
12
7
6
5
4
3
0
Reserved
RW-000000000000000000
Legend: RW = Read/Write; -n = value after reset
PLLRST
RW-0
Reserved
ENSAT
RW-0
Reserved
R-0
BWADJ[11:8]
RW-0000
RW-000000
Table 7-28
DDR3 PLL Control Register 1 Field Descriptions
Description
Bit
Field
Reserved
31-14
13
Reserved
PLLRST
PLL reset bit.
0 = PLL reset is released.
1 = PLL reset is asserted.
12-7
6
Reserved
ENSAT
Reserved
Needs to be set to 1 for proper operation of PLL
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM=15, then BWADJ=7
End of Table 7-28
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7.6.2 DDR3 PLL Device-Specific Information
As shown in Figure 7-21, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3 memory
controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3
PLL are affected as described in Section 7.4 ‘‘Reset Controller’’ on page 132. DDR3 PLL is unlocked only during the
power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the
other resets.
7.6.3 DDR3 PLL Initialization Sequence
See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 73 for details on the initialization sequence for DDR3 PLL.
Note—DDR3 interface needs to reset every time the DDR3 PLL is re-programmed.
7.6.4 DDR3 PLL Input Clock Electrical Data/Timing
Table 7-29
DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
(see Figure 7-24 and Figure 7-20)
No.
Min
Max Unit
DDRCLK[P:N]
1
1
3
2
2
3
4
4
5
5
tc(DDRCLKN)
tc(DDRCLKP)
Cycle time _ DDRCLKN cycle time
Cycle time _ DDRCLKP cycle time
Pulse width _ DDRCLKN high
Pulse width _ DDRCLKN low
Pulse width _ DDRCLKP high
Pulse width _ DDRCLKP low
3.2
3.2
25
25
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
tw(DDRCLKN)
tw(DDRCLKN)
tw(DDRCLKP)
tw(DDRCLKP)
tr(DDRCLK_250mv)
tf(DDRCLK_250mv)
tj(DDRCLKN)
0.45*tc(DDRCLKN)
0.45*tc(DDRCLKN)
0.45*tc(DDRCLKP)
0.45*tc(DDRCLKP)
50
0.55*tc(DDRCLKN)
0.55*tc(DDRCLKN)
0.55*tc(DDRCLKP)
0.55*tc(DDRCLKP)
350
Transition time _ DDRCLK differential rise time (250 mV)
Transition time _ DDRCLK differential fall time (250 mV)
Jitter, peak_to_peak _ periodic DDRCLKN
50
350
0.02*tc(DDRCLKN)
0.02*tc(DDRCLKP)
tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKP
End of Table 7-29
Figure 7-24
DDR3 PLL DDRCLK Timing
1
2
3
5
DDRCLKN
DDRCLKP
4
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7.7 PASS PLL
The PASS PLL generates interface clocks for the Network Coprocessor. Using the PACLKSEL pin the user can select
the input source of PASS PLL as either the output of CORECLK clock reference sources or the PASSCLK clock
reference sources. When coming out of power-on reset, PASS PLL comes out in a bypass mode and needs to be
programmed to a valid frequency before being enabled and used.
PASS PLL power is supplied via the PASS PLL power-supply pin (AVDDA3). An external EMI filter circuit must be
added to all PLL supplies. Please see the Hardware Design Guide for KeyStone Devices in ‘‘Related Documentation
from Texas Instruments’’ on page 73. for detailed recommendations. For the best performance, TI recommends that
all the PLL external components be on a single side of the board without jumpers, switches, or components other
than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the PLL
external components (C1, C2, and the EMI Filter).
Figure 7-25 shows the PASS PLL.
Figure 7-25
PASS PLL Block Diagram
PLLOUT
SYSCLKn
PLL
Controller
C66x
CorePac
PLL
SYSCLK1
PASS PLL
/3
PLLD xPLLM /2
Network
Coprocessor
CORECLK(P|N)
0
PASSCLK(P|N)
PACLKSEL
PLLOUT
1
BYPASS
PLLSELECT
7.7.1 PASS PLL Control Register
The PASS PLL, which is used to drive the Network Coprocessor, does not use a PLL controller. The PASS PLL can
be controlled using the PASSPLLCTL0 and PASSPLLCTL1 registers located in Bootcfg module. These MMRs
(memory-mapped registers) exist inside the Bootcfg space. To write to these registers, software should go through
an un-locking sequence using KICK0/KICK1 registers. For suggested configurable values see 2.5.4 ‘‘PLL Boot
Configuration Settings’’ on page 41. See section 3.3.4 ‘‘Kicker Mechanism (KICK0 and KICK1) Register’’ on
page 81 for the address location of the registers and locking and unlocking sequences for accessing the registers. This
register is reset on POR only.
.
Figure 7-26
PASS PLL Control Register 0 (PASSPLLCTL0) (1)
31
24
23
22
Reserved
RW,+0001
19
18
6
5
0
BWADJ[7:0]
RW,+0000 1001
BYPASS
RW,+0
PLLM
PLLD
RW,+000000
RW,+0000000010011
Legend: RW = Read/Write; -n = value after reset
1 This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common
pll0_ctrl_to_pll_pwrdn.
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Table 7-30
PASS PLL Control Register 0 Field Descriptions
Bit
Field
Description
31-24
BWADJ[7:0]
BYPASS
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM = 15, then BWADJ = 7.
23
Enable bypass mode
0 = Bypass disabled
1 = Bypass enabled
22-19
18-6
5-0
Reserved
PLLM
Reserved
A 13-bit bus that selects the values for the multiplication factor
A 6-bit bus that selects the values for the reference divider
PLLD
End of Table 7-30
Figure 7-27
PASS PLL Control Register 1 (PASSPLLCTL1)
31
15
14
PLLRST PLLSELECT
RW-0 RW-0
Legend: RW = Read/Write; -n = value after reset
13
12
7
6
5
4
3
0
Reserved
RW-00000000000000000
Reserved
ENSAT
RW-0
Reserved
R-0
BWADJ[11:8]
RW-0000
RW-000000
Table 7-31
PASS PLL Control Register 1 Field Descriptions
Description
Bit
Field
Reserved
31-15
14
Reserved
PLLRST
PLL reset bit.
0 = PLL reset is released
1 = PLL reset is asserted
13
PLLSELECT
PASS PLL select bit. Please note that this bit must be set before the Ethernet subsystem is configured and used.
0 = Reserved
1 = PASS PLL output clock is used as the input to PASS
12-7
6
Reserved
ENSAT
Reserved
Must be set to 1 for proper operation of the PLL
Reserved
5-4
3-0
Reserved
BWADJ[11:8]
BWADJ[11:8] and BWADJ[7:0] are located in PASSPLLCTL0 and PASSPLLCTL1 registers. The combination (BWADJ[11:0])
should be programmed to a value equal to half of PLLM[12:0] value (round down if PLLM has an odd value). Example:
PLLM=15, then BWADJ=7.
End of Table 7-31
7.7.2 PASS PLL Device-Specific Information
As shown in Figure 7-25, the output of PASS PLL (PLLOUT) is divided by 2 and directly fed to the Network
Coprocessor. The PASS PLL is affected by power-on reset. During power-on resets, the internal clocks of the PASS
PLL are affected as described in Section 7.4 ‘‘Reset Controller’’ on page 132. The PASS PLL is unlocked only during
the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of
the other resets.
7.7.3 PASS PLL Initialization Sequence
See the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas
Instruments’’ on page 73 for details on the initialization sequence for PASS PLL.
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7.7.4 PASS PLL Input Clock Electrical Data/Timing
Table 7-32
PASS PLL Timing Requirements
(See Figure 7-28 and Figure 7-20)
No.
Min
Max
Unit
PASSCLK[P:N]
1
1
3
2
2
3
4
4
5
5
tc(PASSCLKN)
tc(PASSCLKP)
Cycle Time _ PASSCLKN cycle time
Cycle Time _ PASSCLKP cycle time
Pulse Width _ PASSCLKN high
Pulse Width _ PASSCLKN low
Pulse Width _ PASSCLKP high
Pulse Width _ PASSCLKP low
3.2
3.2
25
25
ns
ns
ns
ns
ns
ns
ps
ps
tw(PASSCLKN)
tw(PASSCLKN)
tw(PASSCLKP)
tw(PASSCLKP)
tr(PASSCLK_250mv)
tf(PASSCLK_250mv)
tj(PASSCLKN)
0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN)
0.45*tc(PASSCLKN) 0.55*tc(PASSCLKN)
0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP)
0.45*tc(PASSCLKP) 0.55*tc(PASSCLKP)
Transition time _ PASSCLK differential rise time (250 mV)
Transition time _ PASSCLK differential fall time (250 mV)
Jitter, peak_to_peak _ periodic PASSCLKN
50
50
350
350
0.02*tc(PASSCLKN) ps, pk-pk
0.02*tc(PASSCLKP) ps, pk-pk
tj(PASSCLKP)
Jitter, peak_to_peak _ periodic PASSCLKP
Figure 7-28
PASS PLL Timing
1
2
3
5
PASSCLKN
PASSCLKP
4
7.8 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped
slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between
external memory and internal memory), performs sorting or subframe extraction of various data structures, services
event driven peripherals, and offloads data transfers from the device CPU.
There are 3 EDMA Channel Controllers on the C6678 DSP, EDMA3CC0, EDMA3CC1, and EDMA3CC2.
•
•
•
EDMA3CC0 has two transfer controllers: EDMA3TC1 and EDMA3TC2.
EDMA3CC1 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.
EDMA3CC2 has four transfer controllers: EDMA3TC0, EDMA3TC1, EDMA3TC2, and EDMA3TC3.
In the context of this document, EDMA3TCx associated with EDMA3CCy, and is referred to as EDMA3CCy TCx.
Each of the transfer controllers has a direct connection to the switch fabric. Section 4.2 ‘‘Switch Fabric Connections’’
lists the peripherals that can be accessed by the transfer controllers.
EDMA3CC0 is optimized to be used for transfers to/from/within the MSMC and DDR-3 Subsytems. The others are
to be used for the remaining traffic.
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Each EDMA3 Channel Controller includes the following features:
•
Fully orthogonal transfer description
–
Three transfer dimensions:
›
›
›
Array (multiple bytes)
Frame (multiple arrays)
Block (multiple frames)
–
–
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
•
•
Flexible transfer definition:
–
–
Increment or FIFO transfer addressing modes
Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
–
Chaining allows multiple transfers to execute with one event
128 PaRAM entries for EDMA3CC0, 512 each for EDMA3CC1 and EDMA3CC2
–
–
Used to define transfer context for channels
Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
•
•
16 DMA channels for EDMA3CC0, 64 each for EDMA3CC1 and EDMA3CC2
–
Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
8 Quick DMA (QDMA) channels per EDMA 3 Channel Controller
–
–
Used for software-driven transfers
Triggered upon writing to a single PaRAM set entry
•
Two transfer controllers and two event queues with programmable system-level priority for EDMA3CC0, four
transfer controllers and four event queues with programmable system-level priority per channel controller for
EDMA3CC1 and EDMA3CC2
•
•
Interrupt generation for transfer completion and error conditions
Debug visibility
–
–
Queue watermarking/threshold allows detection of maximum usage of event queues
Error and status recording to facilitate debug
7.8.1 EDMA3 Device-Specific Information
The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant
addressing mode is applicable to a very limited set of use cases; for most applications increment mode must be used.
On the C6678 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder
Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP). Constant addressing mode is not
supported by any other peripheral or internal memory in the DSP. Note that increment mode is supported by all
peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct
Memory Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 73.
For the range of memory addresses that include EDMA3 channel controller (EDMA3CC) control registers and
EDMA3 transfer controller (EDMA3TC) control register see Section Table 2-2‘‘Memory Map Summary’’ on
page 21. For memory offsets and other details on EDMA3CC and EDMA3TC control registers entries, see the
Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide in ‘‘Related Documentation from
Texas Instruments’’ on page 73.
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7.8.2 EDMA3 Channel Controller Configuration
Table 7-33 provides the configuration for each of the EDMA3 channel controllers present on the device.
Table 7-33
Description
EDMA3 Channel Controller Configuration
EDMA3 CC0 EDMA3 CC1 EDMA3 CC2
Number of DMA channels in Channel Controller
Number of QDMA channels
16
8
64
8
64
8
Number of interrupt channels
Number of PaRAM set entries
16
128
2
64
512
4
64
512
4
Number of event queues
Number of Transfer Controllers
Memory Protection Existence
Number of Memory Protection and Shadow Regions
End of Table 7-33
2
4
4
Yes
8
Yes
8
Yes
8
7.8.3 EDMA3 Transfer Controller Configuration
Each transfer controller on a device is designed differently based on considerations like performance requirements,
system topology (like main TeraNet bus width, external memory bus width), etc. The parameters that determine the
transfer controller configurations are:
•
FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data.
The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored
and subsequently written out to the destination endpoint by the TC write controller.
•
•
•
BUSWIDTH: The width of the read and write data buses in bytes, for the TC read and write controller,
respectively. This is typically equal to the bus width of the main TeraNet interface.
Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a
transfer controller.
DSTREGDEPTH: This determines the number of destination FIFO register set. The number of destination
FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.
All four parameters listed above are fixed by the design of the device.
Table 7-34 provides the configuration for each of the EDMA3 transfer controllers present on the device.
Table 7-34
EDMA3 Transfer Controller Configuration
EDMA3 CC0
TC1
EDMA3 CC1
TC2
EDMA3 CC2
TC2
Parameter
FIFOSIZE
TC0
TC0
TC1
TC3
TC0
TC1
TC3
1024 bytes 1024 bytes 1024 bytes 512 bytes 1024 bytes 512 bytes 1024 bytes 512 bytes 512 bytes 1024 bytes
BUSWIDTH
32 bytes
32 bytes
4 entries
128 bytes
16 bytes
4 entries
128 bytes
16 bytes
4 entries
64 bytes
16 bytes
4 entries
128 bytes
16 bytes
4 entries
64 bytes
16 bytes
4 entries
128 bytes
16 bytes
4 entries
64 bytes
16 bytes
4 entries
64 bytes
16 bytes
4 entries
128 bytes
DSTREGDEPTH 4 entries
DBS 128 bytes
End of Table 7-34
7.8.4 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 16 DMA channels for EDMA3CC0, 64 each for EDMA3CC1 and EDMA3CC2 that can
be used to service system peripherals and to move data between system memories. DMA channels can be triggered
by synchronization events generated by system peripherals. The following tables lists the source of the
synchronization event associated with each of the EDMA EDMA3CC DMA channels. On the C6678, the association
of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
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For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed,
prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Table 7-35
EDMA3CC0 Events for C6678
Event Number
Event
Event Description
0
TINT8L
Timer interrupt low
1
TINT8H
Timer interrupt high
2
TINT9L
Timer interrupt low
3
TINT9H
Timer interrupt high
4
TINT10L
Timer interrupt low
5
TINT10H
TINT11L
Timer interrupt high
6
Timer interrupt low
7
TINT11H
CIC3_OUT0
CIC3_OUT1
CIC3_OUT2
CIC3_OUT3
CIC3_OUT4
CIC3_OUT5
CIC3_OUT6
CIC3_OUT7
Timer interrupt high
8
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
9
10
11
12
13
14
15
End of Table 7-35
Table 7-36
EDMA3CC1 Events for C6678 (Part 1 of 2)
Event Number
Event
Event Description
SPI interrupt
0
SPIINT0
SPIINT1
SPIXEVT
SPIREVT
I2CREVT
I2CXEVT
GPINT0
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
SEMINT0
SEMINT1
SEMINT2
SEMINT3
SEMINT4
SEMINT5
SEMINT6
1
SPI interrupt
2
Transmit event
3
Receive event
4
I2C receive event
I2C transmit event
GPIO interrupt
5
6
7
GPIO interrupt
8
GPIO interrupt
9
GPIO interrupt
10
11
12
13
14
15
16
17
18
19
20
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
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Table 7-36
EDMA3CC1 Events for C6678 (Part 2 of 2)
Event Number
Event
Event Description
21
SEMINT7
Semaphore interrupt
22
TINT8L
Timer interrupt low
23
TINT8H
Timer interrupt high
24
TINT9L
Timer interrupt low
25
TINT9H
Timer interrupt high
26
TINT10L
Timer interrupt low
27
TINT10H
Timer interrupt high
28
TINT11L
Timer interrupt low
29
TINT11H
Timer interrupt high
30
TINT12L
Timer interrupt low
31
TINT12H
Timer interrupt high
32
TINT13L
Timer interrupt low
33
TINT13H
Timer interrupt high
34
TINT14L
Timer interrupt low
35
TINT14H
Timer interrupt high
36
TINT15L
Timer interrupt low
37
TINT15L
Timer interrupt high
38
CIC2_OUT44
CIC2_OUT45
CIC2_OUT46
CIC2_OUT47
CIC2_OUT0
CIC2_OUT1
CIC2_OUT2
CIC2_OUT3
CIC2_OUT4
CIC2_OUT5
CIC2_OUT6
CIC2_OUT7
CIC2_OUT8
CIC2_OUT9
CIC2_OUT10
CIC2_OUT11
CIC2_OUT12
CIC2_OUT13
CIC2_OUT14
CIC2_OUT15
CIC2_OUT16
CIC2_OUT17
CIC2_OUT18
CIC2_OUT19
CIC2_OUT20
CIC2_OUT21
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
End of Table 7-36
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Table 7-37
EDMA3CC2 Events for C6678 (Part 1 of 2)
Event Number
Event
Event Description
SPI interrupt
0
SPIINT0
1
SPIINT1
SPI interrupt
2
SPIXEVT
SPIREVT
I2CREVT
I2CXEVT
GPINT0
Transmit event
3
Receive event
4
I2C receive event
5
I2C transmit event
GPIO interrupt
6
7
GPINT1
GPIO interrupt
8
GPINT2
GPIO Interrupt
9
GPINT3
GPIO interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
GPINT4
GPIO interrupt
GPINT5
GPIO interrupt
GPINT6
GPIO interrupt
GPINT7
GPIO interrupt
SEMINT0
SEMINT1
SEMINT2
SEMINT3
SEMINT4
SEMINT5
SEMINT6
SEMINT7
TINT8L
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Interrupt Controller output
Interrupt Controller output
UART receive event
UART transmit event
Interrupt Controller output
Interrupt Controller output
TINT8H
TINT9L
TINT9H
TINT10L
TINT10H
TINT11L
TINT11H
TINT12L
TINT12H
TINT13L
TINT13H
TINT14L
TINT14H
TINT15L
TINT15H
CIC2_OUT48
CIC2_OUT49
URXEVT
UTXEVT
CIC2_OUT22
CIC2_OUT23
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-37
EDMA3CC2 Events for C6678 (Part 2 of 2)
Event Number
Event
Event Description
44
CIC2_OUT24
CIC2_OUT25
CIC2_OUT26
CIC2_OUT27
CIC2_OUT28
CIC2_OUT29
CIC2_OUT30
CIC2_OUT31
CIC2_OUT32
CIC2_OUT33
CIC2_OUT34
CIC2_OUT35
CIC2_OUT36
CIC2_OUT37
CIC2_OUT38
CIC2_OUT39
CIC2_OUT40
CIC2_OUT41
CIC2_OUT42
CIC2_OUT43
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
End of Table 7-37
7.9 Interrupts
7.9.1 Interrupt Sources and Interrupt Controller
The CPU interrupts on the C6678 device are configured through the C66x CorePac Interrupt Controller. The
interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs
(CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system
events consist of both internally-generated events (within the CorePac) and chip-level events.
Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required
as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class
events or infrequently used events are also routed through the system event router to offload the C66x CorePac
interrupt selector. This is accomplished through chip interrupt controller (CIC) blocks. This is clocked using CPU/6.
The event controllers consist of simple combination logic to provide additional events to each C66x CorePac, plus
the EDMA3CC, CIC0, and CIC1 provide 17 additional events as well as 8 broadcast events to each of the C66x
CorePacs, CIC2 provides 26 and 24 additional events to EDMA3CC1 and EDMA3CC2 respectively, and CIC3
provides 8 and 32 additional events to EDMA3CC0 and HyperLink respectively.
There are a large number of events at the chip level. The chip level CIC provides a flexible way to combine and remap
those events. Multiple events can be combined to a single event through chip level CIC. However, an event can only
be mapped to a single event output from the chip level CIC. The chip level CIC also allows the software to trigger
system event through memory writes. The broadcast events to C66x CorePacs can be used for synchronization
among multiple cores or inter-processor communication purpose and etc. For more details on the CIC features,
162
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
please refer to the Chip Interrupt Controller (CIC) for KeyStone Devices User Guide in ‘‘Related Documentation from
Texas Instruments’’ on page 73.
Note—Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and EOI handshaking
interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Figure 7-29 shows the C6678 interrupt topology.
Figure 7-29
TMS320C6678 Interrupt Topology
98 Primary Events
17 Secondary Events
Core0
Core1
Core2
Core3
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
8 Reserved Secondary Events
5 Reserved Primary Events
89 Core-only Secondary Events
63 Common Events
CIC0
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
8 Broadcast Events from CIC0
98 Primary Events
17 Secondary Events
Core4
Core5
Core6
Core7
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
8 Reserved Secondary Events
89 Core-only Secondary Events
63 Common Events
5 Reserved Primary Events
CIC1
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
98 Primary Events
17 Secondary Events
5 Reserved Primary Events
8 Broadcast Events from CIC1
38 Primary Events
63 Common Events
EDMA3
CC1
26 Secondary Events
9 Reserved Secondary Events
CIC2
40 Primary Events
EDMA3
CC2
88 EDMA3CC-only
Secondary Events
24 Secondary Events
32 Primary Events
HyperLink
17 Reserved Secondary Events
63 Events
32 Secondary Events
CIC3
8 Primary Events
EDMA3
CC0
8 Secondary Events
164
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-38 shows the mapping of system events. For more information on the Interrupt Controller, see the C66x
CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Table 7-38
TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts (Part 1 of 4)
Event Number
Interrupt Event
EVT0
Description
0
1
2
3
4
5
6
7
8
9
Event combiner 0 output
Event combiner 1 output
Event combiner 2 output
Event combiner 3 output
TETB is half full
EVT1
EVT2
EVT3
TETBHFULLINTn (1)
(1)
TETBFULLINTn
TETB is full
TETBACQINTn (1)
TETBOVFLINTn (1)
TETBUNFLINTn (1)
EMU_DTDMA
Acquisition has been completed
Overflow condition interrupt
Underflow condition interrupt
ECM interrupt for:
1. Host scan access
2. DTDMA transfer complete
3. AET interrupt
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
MSMC_mpf_errorn (2)
Memory protection fault indicators for local core
RTDX receive complete
EMU_RTDXRX
EMU_RTDXTX
RTDX transmit complete
IDMA0
IDMA channel 0 interrupt
IDMA1
SEMERRn (3)
SEMINTn (3)
PCIExpress_MSI_INTn (4)
TSIP0_ERRINT[n] (5)
TSIP1_ERRINT[n] (5)
INTDST(n+16) (6)
CIC0_OUT(32+0+11*n) (7) Or CIC1_OUT(32+0+11*(n-4)) (7)
CIC0_OUT(32+1+11*n) (7) Or CIC1_OUT(32+1+11*(n-4)) (7)
CIC0_OUT(32+2+11*n) (7) Or CIC1_OUT(32+2+11*(n-4)) (7)
CIC0_OUT(32+3+11*n) (7) Or CIC1_OUT(32+3+11*(n-4)) (7)
CIC0_OUT(32+4+11*n) (7) Or CIC1_OUT(32+4+11*(n-4)) (7)
CIC0_OUT(32+5+11*n) (7) Or CIC1_OUT(32+5+11*(n-4)) (7)
CIC0_OUT(32+6+11*n) (7) Or CIC1_OUT(32+6+11*(n-4)) (7)
CIC0_OUT(32+7+11*n) (7) Or CIC1_OUT(32+7+11*(n-4)) (7)
CIC0_OUT(32+8+11*n) (7) Or CIC1_OUT(32+8+11*(n-4)) (7)
CIC0_OUT(32+9+11*n) (7) Or CIC1_OUT(32+9+11*(n-4)) (7)
CIC0_OUT(32+10+11*n) (7) Or CIC1_OUT(32+10+11*(n-4)) (7)
QM_INT_LOW_0
IDMA channel 1 interrupt
Semaphore error interrupt
Semaphore interrupt
Message signaled interrupt mode
TSIP0 receive/transmit error interrupt
TSIP1 receive/transmit error interrupt
SRIO Interrupt
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
QM Interrupt for 0~31 Queues
QM Interrupt for 32~63 Queues
QM Interrupt for 64~95 Queues
QM Interrupt for 96~127 Queues
QM Interrupt for 128~159 Queues
QM Interrupt for 160~191 Queues
QM Interrupt for 192~223 Queues
QM_INT_LOW_1
QM_INT_LOW_2
QM_INT_LOW_3
QM_INT_LOW_4
QM_INT_LOW_5
QM_INT_LOW_6
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-38
TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts (Part 2 of 4)
Event Number
Interrupt Event
QM_INT_LOW_7
QM_INT_LOW_8
QM_INT_LOW_9
QM_INT_LOW_10
QM_INT_LOW_11
QM_INT_LOW_12
QM_INT_LOW_13
QM_INT_LOW_14
QM_INT_LOW_15
QM_INT_HIGH_n (8)
QM_INT_HIGH_(n+8) (8)
QM_INT_HIGH_(n+16) (8)
QM_INT_HIGH_(n+24) (8)
TSIP0_RFSINT[n] (5)
TSIP0_RSFINT[n] (5)
TSIP0_XFSINT[n] (5)
TSIP0_XSFINT[n] (5)
TSIP1_RFSINT[n] (5)
TSIP1_RSFINT[n] (5)
TSIP1_XFSINT[n] (5)
TSIP1_XSFINT[n] (5)
Reserved
Description
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
QM Interrupt for 224~255 Queues
QM Interrupt for 256~287 Queues
QM Interrupt for 288~319 Queues
QM Interrupt for 320~351 Queues
QM Interrupt for 352~383 Queues
QM Interrupt for 384~415 Queues
QM Interrupt for 416~447 Queues
QM Interrupt for 448~479 Queues
QM Interrupt for 480~511 Queues
QM Interrupt for Queue 704+n8
QM Interrupt for Queue 712+n8
QM Interrupt for Queue 720+n8
QM Interrupt for Queue 728+n8
TSIP0 receive frame sync interrupt
TSIP0 receive super frame interrupt
TSIP0 transmit frame sync interrupt
TSIP0 transmit super frame interrupt
TSIP1 receive frame sync interrupt
TSIP1 receive super frame interrupt
TSIP1 transmit frame sync interrupt
TSIP1 transmit super frame interrupt
Reserved
CIC0_OUT(2+8*n)7 Or CIC1_OUT(2+8*(n-4))7
CIC0_OUT(3+8*n)7 Or CIC1_OUT(3+8*(n-4))7
TINTLn (9)
Interrupt Controller output
Interrupt Controller output
Local timer interrupt low
Local timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Timer interrupt low
Timer interrupt high
Local GPIO interrupt
TINTHn (9)
TINT8L
TINT8H
TINT9L
TINT9H
TINT10L
TINT10H
TINT11L
TINT11H
TINT12L
TINT12H
TINT13L
TINT13H
TINT14L
TINT14H
TINT15L
TINT15H
GPINT8
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Multicore Fixed and Floating-Point Digital Signal Processor
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Table 7-38
TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts (Part 3 of 4)
Event Number
83
Interrupt Event
Description
GPINT9
Local GPIO interrupt
84
GPINT10
Local GPIO interrupt
85
GPINT11
Local GPIO interrupt
86
GPINT12
Local GPIO interrupt
87
GPINT13
Local GPIO interrupt
88
GPINT14
Local GPIO interrupt
89
GPINT15
Local GPIO interrupt
90
GPINTn (10)
Local GPIO interrupt
91
IPC_LOCAL
Inter DSP interrupt from IPCGRn
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Dropped CPU interrupt event
Invalid IDMA parameters
92
CIC0_OUT(4+8*n) (7) Or CIC1_OUT(4+8*(n-4)) (7)
CIC0_OUT(5+8*n) (7) Or CIC1_OUT(5+8*(n-4)) (7)
CIC0_OUT(6+8*n) (7) Or CIC1_OUT(6+8*(n-4)) (7)
CIC0_OUT(7+8*n) (7) Or CIC1_OUT(7+8*(n-4)) (7)
INTERR
93
94
95
96
97
EMC_IDMAERR
98
Reserved
99
Reserved
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
EFIINTA
EFI Interrupt from side A
EFI Interrupt from side B
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
VbusM error event
EFIINTB
CIC0_OUT0 or CIC1_OUT0
CIC0_OUT1 or CIC1_OUT1
CIC0_OUT8 or CIC1_OUT8
CIC0_OUT9 or CIC1_OUT9
CIC0_OUT16 or CIC1_OUT16
CIC0_OUT17 or CIC1_OUT17
CIC0_OUT24 or CIC1_OUT24
CIC0_OUT25 or CIC1_OUT25
MDMAERREVT
Reserved
EDMA3CC0_EDMACC_AETEVT
PMC_ED
EDMA3CC0 AET event
Single bit error detected during DMA read
EDMA3CC1 AET Event
EDMA3CC1_EDMACC_AETEVT
EDMA3CC2_EDMACC_AETEVT
UMC_ED1
EDMA3CC2 AET Event
Corrected bit error detected
UMC_ED2
Uncorrected bit error detected
PDC_INT
Power down sleep interrupt
SYS_CMPA
SYS CPU memory protection fault event
PMC CPU memory protection fault event
PMC DMA memory protection fault event
DMC CPU memory protection fault event
DMC DMA memory protection fault event
UMC CPU memory protection fault event
UMC DMA memory protection fault event
PMC_CMPA
PMC_DMPA
DMC_CMPA
DMC_DMPA
UMC_CMPA
UMC_DMPA
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SPRS691D—April 2013
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Table 7-38
TMS320C6678 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)
Event Number
Interrupt Event
EMC_CMPA
Description
126
EMC CPU memory protection fault event
EMC bus error interrupt
127
EMC_BUSERR
End of Table 7-38
1 CorePac[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn.
2 CorePac[n] will receive MSMC_mpf_errorn.CIC.
3 CorePac[n] will receive SEMINTn and SEMERRn.
4 CorePac[n] will receive PCIEXpress_MSI_INTn.
5 CorePac[n] will receive TSIPx_xxx[n].
6 CorePac[n] will receive INTDST(n+16).
7 n is core number.
8 n is core number.
9 CorePac[n] will receive TINTLn and TINTHn.
10 CorePac[n] will receive GPINTn.
Table 7-39
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 1 of 5)
Input Event# on CIC
System Interrupt
Description
0
EDMA3CC1 CC_ERRINT
EDMA3CC1 CC_MPINT
EDMA3CC1 TC_ERRINT0
EDMA3CC1 TC_ERRINT1
EDMA3CC1 TC_ERRINT2
EDMA3CC1 TC_ERRINT3
EDMA3CC1 CC_GINT
Reserved
EDMA3CC1 error interrupt
EDMA3CC1 memory protection interrupt
EDMA3CC1 TC0 error interrupt
EDMA3CC1 TC1 error interrupt
EDMA3CC1 TC2 error interrupt
EDMA3CC1 TC3 error interrupt
EDMA3CC1 GINT
1
2
3
4
5
6
7
8
EDMA3CC1 CCINT0
EDMA3CC1 CCINT1
EDMA3CC1 CCINT2
EDMA3CC1 CCINT3
EDMA3CC1 CCINT4
EDMA3CC1 CCINT5
EDMA3CC1 CCINT6
EDMA3CC1 CCINT7
EDMA3CC2 CC_ERRINT
EDMA3CC2 CC_MPINT
EDMA3CC2 TC_ERRINT0
EDMA3CC2 TC_ERRINT1
EDMA3CC2 TC_ERRINT2
EDMA3CC2 TC_ERRINT3
EDMA3CC2 CC_GINT
Reserved
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC2 error interrupt
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
EDMA3CC2 memory protection interrupt
EDMA3CC2 TC0 error interrupt
EDMA3CC2 TC1 error interrupt
EDMA3CC2 TC2 error interrupt
EDMA3CC2 TC3 error interrupt
EDMA3CC2 GINT
EDMA3CC2 CCINT0
EDMA3CC2 CCINT1
EDMA3CC2 CCINT2
EDMA3CC2 CCINT3
EDMA3CC2 CCINT4
EDMA3CC2 CCINT5
EDMA3CC2 CCINT6
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
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Table 7-39
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 5)
Input Event# on CIC
System Interrupt
EDMA3CC2 CCINT7
EDMA3CC0 CC_ERRINT
EDMA3CC0 CC_MPINT
EDMA3CC0 TC_ERRINT0
EDMA3CC0 TC_ERRINT1
EDMA3CC0 CC_GINT
Reserved
Description
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
EDMA3CC2 individual completion interrupt
EDMA3CC0 error interrupt
EDMA3CC0 memory protection interrupt
EDMA3CC0 TC0 error interrupt
EDMA3CC0 TC1 error interrupt
EDMA3CC0 GINT
EDMA3CC0 CCINT0
EDMA3CC0 CCINT1
EDMA3CC0 CCINT2
EDMA3CC0 CCINT3
EDMA3CC0 CCINT4
EDMA3CC0 CCINT5
EDMA3CC0 CCINT6
EDMA3CC0 CCINT7
Reserved
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
QM_INT_PASS_TXQ_PEND_12
PCIEXpress_ERR_INT
PCIEXpress_PM_INT
PCIEXpress_Legacy_INTA
PCIEXpress_Legacy_INTB
PCIEXpress_Legacy_INTC
PCIEXpress_Legacy_INTD
SPIINT0
Queue manager pend event
Protocol error interrupt
Power management interrupt
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
SPI interrupt0
SPIINT1
SPI interrupt1
SPIXEVT
Transmit event
SPIREVT
Receive event
I2C interrupt
I2C receive event
I2C transmit event
I2CINT
I2CREVT
I2CXEVT
Reserved
Reserved
TETBHFULLINT
TETB is half full
TETBFULLINT
TETB is full
TETBACQINT
Acquisition has been completed
Overflow condition occur
TETBOVFLINT
TETBUNFLINT
Underflow condition occur
MDIO_LINK_INTR0
MDIO_LINK_INTR1
MDIO_USER_INTR0
MDIO_USER_INTR1
MISC_INTR
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MISC interrupt
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
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Table 7-39
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 5)
Input Event# on CIC
System Interrupt
Description
75
76
77
78
79
80
81
81
82
84
85
86
87
88
89
90
TRACER_CORE_2_INTD
TRACER_CORE_3_INTD
TRACER_DDR_INTD
TRACER_MSMC_0_INTD
TRACER_MSMC_1_INTD
TRACER_MSMC_2_INTD
TRACER_MSMC_3_INTD
TRACER_CFG_INTD
TRACER_QM_CFG_INTD
TRACER_QM_DMA_INTD
TRACER_SM_INTD
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave
Tracer sliding time window interrupt for semaphore
Power/sleep controller interrupt
PSC_ALLINT
MSMC_SCRUB_CERROR
BOOTCFG_INTD
Correctable (1-bit) soft error detected during scrub cycle
Chip-level MMR error register
Reserved
MPU0_INTD (MPU0_ADDR_ERR_INT and MPU0 addressing violation interrupt and protection violation interrupt.
MPU0_PROT_ERR_INT combined)
91
92
QM_INT_PASS_TXQ_PEND_13
Queue manager pend event
MPU1_INTD (MPU1_ADDR_ERR_INT and MPU1 addressing violation interrupt and protection violation interrupt.
MPU1_PROT_ERR_INT combined)
93
94
QM_INT_PASS_TXQ_PEND_14
Queue manager pend event
MPU2_INTD (MPU2_ADDR_ERR_INT and MPU2 addressing violation interrupt and protection violation interrupt.
MPU2_PROT_ERR_INT combined)
95
96
QM_INT_PASS_TXQ_PEND_15
Queue manager pend event
MPU3_INTD (MPU3_ADDR_ERR_INT and MPU3 addressing violation interrupt and protection violation interrupt.
MPU3_PROT_ERR_INT combined)
97
QM_INT_PASS_TXQ_PEND_16
MSMC_dedc_cerror
MSMC_dedc_nc_error
MSMC_scrub_nc_error
Reserved
Queue manager pend event
98
Correctable (1-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected during scrub cycle
99
100
101
102
103
104
105
105
107
108
109
110
111
112
113
114
115
MSMC_mpf_error8
MSMC_mpf_error9
MSMC_mpf_error10
MSMC_mpf_error11
MSMC_mpf_error12
MSMC_mpf_error13
MSMC_mpf_error14
MSMC_mpf_error15
DDR3_ERR
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
DDR3 EMIF error interrupt
VUSR_INT_O
HyperLink interrupt
INTDST0
RapidIO interrupt
INTDST1
RapidIO interrupt
INTDST2
RapidIO interrupt
INTDST3
RapidIO interrupt
170
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-39
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 5)
Input Event# on CIC
System Interrupt
INTDST4
Description
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
RapidIO interrupt
INTDST5
RapidIO interrupt
INTDST6
RapidIO interrupt
INTDST7
RapidIO interrupt
INTDST8
RapidIO interrupt
INTDST9
RapidIO interrupt
INTDST10
INTDST11
INTDST12
INTDST13
INTDST14
INTDST15
EASYNCERR
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
EMIF16 error interrupt
TRACER_CORE_4_INTD
TRACER_CORE_5_INTD
TRACER_CORE_6_INTD
TRACER_CORE_7_INTD
QM_INT_PKTDMA_0
QM_INT_PKTDMA_1
RapidIO_INT_PKTDMA_0
PASS_INT_PKTDMA_0
SmartReflex_intrreq0
SmartReflex_intrreq1
SmartReflex_intrreq2
SmartReflex_intrreq3
VPNoSMPSAck
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Queue manager Interrupt for packet DMA starvation
Queue manager Interrupt for packet DMA starvation
RapidIO Interrupt for packet DMA starvation
Network coprocessor Interrupt for packet DMA starvation
SmartReflex sensor interrupt
SmartReflex sensor interrupt
SmartReflex sensor interrupt
SmartReflex sensor interrupt
VPVOLTUPDATE has been asserted but SMPS has not been responded to in a
defined time interval
142
VPEqValue
SRSINTERUPTZ is asserted, but the new voltage is not different from the
current SMPS voltage
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
VPMaxVdd
The new voltage required is equal to or greater than MaxVdd.
The new voltage required is equal to or less than MinVdd.
The FSM of Voltage processor is in idle.
VPMinVdd
VPINIDLE
VPOPPChangeDone
Reserved
The average frequency error is within the desired limit.
UARTINT
UART interrupt
URXEVT
UART receive event
UTXEVT
UART transmit event
QM_INT_PASS_TXQ_PEND_17
QM_INT_PASS_TXQ_PEND_18
QM_INT_PASS_TXQ_PEND_19
QM_INT_PASS_TXQ_PEND_20
QM_INT_PASS_TXQ_PEND_21
QM_INT_PASS_TXQ_PEND_22
QM_INT_PASS_TXQ_PEND_23
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 171
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-39
CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 5 of 5)
Input Event# on CIC
System Interrupt
Description
158
QM_INT_PASS_TXQ_PEND_24
QM_INT_PASS_TXQ_PEND_25
Queue manager pend event
Queue manager pend event
159
End of Table 7-39
Table 7-40
CIC1 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 1 of 4)
Input Event# on CIC
System Interrupt
Description
0
EDMA3CC1 CC_ERRINT
EDMA3CC1 CC_MPINT
EDMA3CC1 TC_ERRINT0
EDMA3CC1 TC_ERRINT1
EDMA3CC1 TC_ERRINT2
EDMA3CC1 TC_ERRINT3
EDMA3CC1 CC_GINT
Reserved
EDMA3CC1 error interrupt
EDMA3CC1 memory protection interrupt
EDMA3CC1 TC0 error interrupt
EDMA3CC1 TC1 error interrupt
EDMA3CC1 TC2 error interrupt
EDMA3CC1 TC3 error interrupt
EDMA3CC1 GINT
1
2
3
4
5
6
7
8
EDMA3CC1 CCINT0
EDMA3CC1 CCINT1
EDMA3CC1 CCINT2
EDMA3CC1 CCINT3
EDMA3CC1 CCINT4
EDMA3CC1 CCINT5
EDMA3CC1 CCINT6
EDMA3CC1 CCINT7
EDMA3CC2 CC_ERRINT
EDMA3CC2 CC_MPINT
EDMA3CC2 TC_ERRINT0
EDMA3CC2 TC_ERRINT1
EDMA3CC2 TC_ERRINT2
EDMA3CC2 TC_ERRINT3
EDMA3CC2 CC_GINT
Reserved
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC1 individual completion interrupt
EDMA3CC2 error interrupt
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
EDMA3CC2 memory protection interrupt
EDMA3CC2 TC0 error interrupt
EDMA3CC2 TC1 error interrupt
EDMA3CC2 TC2 error interrupt
EDMA3CC2 TC3 error interrupt
EDMA3CC2 GINT
EDMA3CC2 CCINT0
EDMA3CC2 CCINT1
EDMA3CC2 CCINT2
EDMA3CC2 CCINT3
EDMA3CC2 CCINT4
EDMA3CC2 CCINT5
EDMA3CC2 CCINT6
EDMA3CC2 CCINT7
EDMA3CC0 CC_ERRINT
EDMA3CC0 CC_MPINT
EDMA3CC0 TC_ERRINT0
EDMA3CC0 TC_ERRINT1
EDMA3CC0 CC_GINT
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC2 individual completion interrupt
EDMA3CC0 error interrupt
EDMA3CC0 memory protection interrupt
EDMA3CC0 TC0 error interrupt
EDMA3CC0 TC1 error interrupt
EDMA3CC0 GINT
172
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-40
CIC1 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 2 of 4)
Input Event# on CIC
System Interrupt
Reserved
Description
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
EDMA3CC0 CCINT0
EDMA3CC0 CCINT1
EDMA3CC0 CCINT2
EDMA3CC0 CCINT3
EDMA3CC0 CCINT4
EDMA3CC0 CCINT5
EDMA3CC0 CCINT6
EDMA3CC0 CCINT7
Reserved
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
EDMA3CC0 individual completion interrupt
QM_INT_PASS_TXQ_PEND_18
PCIEXpress_ERR_INT
PCIEXpress_PM_INT
PCIEXpress_Legacy_INTA
PCIEXpress_Legacy_INTB
PCIEXpress_Legacy_INTC
PCIEXpress_Legacy_INTD
SPIINT0
Queue manager pend event
Protocol error interrupt
Power management interrupt
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
SPI interrupt0
SPIINT1
SPI interrupt1
SPIXEVT
Transmit event
SPIREVT
Receive event
I2C interrupt
I2C receive event
I2C transmit event
I2CINT
I2CREVT
I2CXEVT
Reserved
Reserved
TETBHFULLINT
TETB is half full
TETBFULLINT
TETB is full
TETBACQINT
Acquisition has been completed
TETBOVFLINT
Overflow condition occur
TETBUNFLINT
Underflow condition occur
MDIO_LINK_INTR0
MDIO_LINK_INTR1
MDIO_USER_INTR0
MDIO_USER_INTR1
MISC_INTR
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MISC Interrupt
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
TRACER_CORE_2_INTD
TRACER_CORE_3_INTD
TRACER_DDR_INTD
TRACER_MSMC_0_INTD
TRACER_MSMC_1_INTD
TRACER_MSMC_2_INTD
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 173
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-40
CIC1 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 3 of 4)
Input Event# on CIC
System Interrupt
TRACER_MSMC_3_INTD
TRACER_CFG_INTD
TRACER_QM_CFG_INTD
TRACER_QM_DMA_INTD
TRACER_SM_INTD
PSC_ALLINT
Description
81
82
83
84
85
86
87
88
89
90
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave
Tracer sliding time window interrupt for semaphore
Power/sleep controller interrupt
MSMC_SCRUB_CERROR
BOOTCFG_INTD
Correctable (1-bit) soft error detected during scrub cycle
BOOTCFG Interrupt BOOTCFG_ERR and BOOTCFG_PROT
Reserved
MPU0_INTD (MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
MPU0 addressing violation interrupt and protection violation interrupt.
91
92
QM_INT_PASS_TXQ_PEND_19
Queue manager pend event
MPU1_INTD (MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
MPU1 addressing violation interrupt and protection violation interrupt.
93
94
QM_INT_PASS_TXQ_PEND_20
Queue manager pend event
MPU2_INTD (MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
MPU2 addressing violation interrupt and protection violation interrupt.
95
96
QM_INT_PASS_TXQ_PEND_21
Queue manager pend event
MPU3_INTD (MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
MPU3 addressing violation interrupt and protection violation interrupt.
97
QM_INT_PASS_TXQ_PEND_22
MSMC_dedc_cerror
MSMC_dedc_nc_error
MSMC_scrub_nc_error
Reserved
Queue manager pend event
98
Correctable (1-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected during scrub cycle
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
MSMC_mpf_error8
MSMC_mpf_error9
MSMC_mpf_error10
MSMC_mpf_error11
MSMC_mpf_error12
MSMC_mpf_error13
MSMC_mpf_error14
MSMC_mpf_error15
DDR3_ERR
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
DDR3 EMIF error interrupt
VUSR_INT_O
HyperLink interrupt
INTDST0
RapidIO interrupt
INTDST1
RapidIO interrupt
INTDST2
RapidIO interrupt
INTDST3
RapidIO interrupt
INTDST4
RapidIO interrupt
INTDST5
RapidIO interrupt
INTDST6
RapidIO interrupt
INTDST7
RapidIO interrupt
INTDST8
RapidIO interrupt
INTDST9
RapidIO interrupt
174
Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-40
CIC1 Event Inputs (Secondary Interrupts for C66x CorePacs) (Part 4 of 4)
Input Event# on CIC
System Interrupt
INTDST10
Description
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
RapidIO interrupt
INTDST11
RapidIO interrupt
INTDST12
RapidIO interrupt
INTDST13
RapidIO interrupt
INTDST14
RapidIO interrupt
INTDST15
RapidIO interrupt
EASYNCERR
EMIF16 error interrupt
TRACER_CORE_4_INTD
TRACER_CORE_5_INTD
TRACER_CORE_6_INTD
TRACER_CORE_7_INTD
QM_INT_PKTDMA_0
QM_INT_PKTDMA_1
RapidIO_INT_PKTDMA_0
PASS_INT_PKTDMA_0
SmartReflex_intrreq0
SmartReflex_intrreq1
SmartReflex_intrreq2
SmartReflex_intrreq3
VPNoSMPSAck
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Queue manager interrupt for PKTDMA starvation
Queue manager interrupt for PKTDMA starvation
RapidIO interrupt for PKTDMA starvation
Network coprocessor interrupt for PKTDMA starvation
SmartReflex sensor interrupt
SmartReflex sensor interrupt
SmartReflex sensor interrupt
SmartReflex sensor interrupt
VPVOLTUPDATE has been asserted but SMPS has not been responded in a
defined time interval
142
VPEqValue
SRSINTERUPTZ is asserted, but the new voltage is not different from the
current SMPS voltage
143
VPMaxVdd
The new voltage required is equal to or greater than MaxVdd
The new voltage required is equal to or less than MinVdd
Indicating that the FSM of Voltage Processor is in idle
144
VPMinVdd
145
VPINIDLE
146
VPOPPChangeDone
Reserved
Indicating that the average frequency error is within the desired limit.
147
148
UARTINT
UART interrupt
149
URXEVT
UART receive event
150
UTXEVT
UART transmit event
151
QM_INT_PASS_TXQ_PEND_23
QM_INT_PASS_TXQ_PEND_24
QM_INT_PASS_TXQ_PEND_25
QM_INT_PASS_TXQ_PEND_26
QM_INT_PASS_TXQ_PEND_27
QM_INT_PASS_TXQ_PEND_28
QM_INT_PASS_TXQ_PEND_29
QM_INT_PASS_TXQ_PEND_30
QM_INT_PASS_TXQ_PEND_31
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
152
153
154
155
156
157
158
159
End of Table 7-40
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 175
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-41
CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 1 of 4)
Input Event # on CIC System Interrupt
Description
0
GPINT8
GPIO interrupt
1
GPINT9
GPIO interrupt
2
GPINT10
GPIO interrupt
3
GPINT11
GPIO interrupt
4
GPINT12
GPIO interrupt
5
GPINT13
GPIO interrupt
6
GPINT14
GPIO interrupt
7
GPINT15
GPIO interrupt
8
TETBHFULLINT
TETBFULLINT
System TETB is half full
System TETB is full
System TETB acquisition has been completed
TETB0 is half full
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
TETBACQINT
TETBHFULLINT0
TETBFULLINT0
TETBACQINT0
TETBHFULLINT1
TETBFULLINT1
TETBACQINT1
TETBHFULLINT2
TETBFULLINT2
TETBACQINT2
TETBHFULLINT3
TETBFULLINT3
TETBACQINT3
Reserved
TETB0 is full
TETB0 acquisition has been completed
TETB1 is half full
TETB1 is full
TETB1 acquisition has been completed
TETB2 is half full
TETB2 is full
TETB2 acquisition has been completed
TETB3 is half full
TETB3 is full
TETB3 acquisition has been completed
QM_INT_HIGH_16
QM_INT_HIGH_17
QM_INT_HIGH_18
QM_INT_HIGH_19
QM_INT_HIGH_20
QM_INT_HIGH_21
QM_INT_HIGH_22
QM_INT_HIGH_23
QM_INT_HIGH_24
QM_INT_HIGH_25
QM_INT_HIGH_26
QM_INT_HIGH_27
QM_INT_HIGH_28
QM_INT_HIGH_29
QM_INT_HIGH_30
QM_INT_HIGH_31
MDIO_LINK_INTR0
MDIO_LINK_INTR1
MDIO_USER_INTR0
MDIO_USER_INTR0
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
QM interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
Network coprocessor MDIO interrupt
176
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Copyright 2013 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-41
CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 2 of 4)
Input Event # on CIC System Interrupt
Description
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MISC_INTR
Network coprocessor MISC interrupt
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
TRACER_CORE_2_INTD
TRACER_CORE_3_INTD
TRACER_DDR_INTD
TRACER_MSMC_0_INTD
TRACER_MSMC_1_INTD
TRACER_MSMC_2_INTD
TRACER_MSMC_3_INTD
TRACER_CFG_INTD
TRACER_QM_CFG_INTD
TRACER_QM_DMA_INTD
TRACER_SM_INTD
SEMERR0
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for DDR3 EMIF
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave port
Tracer sliding time window interrupt for semaphore
Semaphore interrupt
SEMERR1
Semaphore interrupt
SEMERR2
Semaphore interrupt
SEMERR3
Semaphore interrupt
BOOTCFG_INTD
BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT
Network coprocessor interrupt for packet DMA starvation
MPU0 addressing violation interrupt and protection violation interrupt.
PASS_INT_PKTDMA_0
MPU0_INTD (MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
65
66
MSMC_scrub_cerror
Correctable (1-bit) soft error detected during scrub cycle
MPU1_INTD (MPU1_ADDR_ERR_INT and
MPU1_PROT_ERR_INT combined)
MPU1 addressing violation interrupt and protection violation interrupt.
67
68
RapidIO_INT_PKTDMA_0
RapidIO interrupt for packet DMA starvation
MPU2_INTD (MPU2_ADDR_ERR_INT and
MPU2_PROT_ERR_INT combined)
MPU2 addressing violation interrupt and protection violation interrupt.
69
70
QM_INT_PKTDMA_0
QM interrupt for packet DMA starvation
MPU3_INTD (MPU3_ADDR_ERR_INT and
MPU3_PROT_ERR_INT combined)
MPU3 addressing violation interrupt and protection violation interrupt.
71
72
73
74
75
76
77
78
79
80
81
82
83
84
QM_INT_PKTDMA_1
MSMC_dedc_cerror
MSMC_dedc_nc_error
MSMC_scrub_nc_error
Reserved
QM interrupt for packet DMA starvation
Correctable (1-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected on SRAM read
Non-correctable (2-bit) soft error detected during scrub cycle
MSMC_mpf_error0
MSMC_mpf_error1
MSMC_mpf_error2
MSMC_mpf_error3
MSMC_mpf_error4
MSMC_mpf_error5
MSMC_mpf_error6
MSMC_mpf_error7
MSMC_mpf_error8
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 177
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-41
CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 3 of 4)
Input Event # on CIC System Interrupt
Description
85
MSMC_mpf_error9
MSMC_mpf_error10
MSMC_mpf_error11
MSMC_mpf_error12
MSMC_mpf_error13
MSMC_mpf_error14
MSMC_mpf_error15
Reserved
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
Memory protection fault indicators for each system master PrivID
86
87
88
89
90
91
92
93
INTDST0
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
RapidIO interrupt
EMIF16 error interrupt
TETB4 is half full
94
INTDST1
95
INTDST2
96
INTDST3
97
INTDST4
98
INTDST5
99
INTDST6
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
INTDST7
INTDST8
INTDST9
INTDST10
INTDST11
INTDST12
INTDST13
INTDST14
INTDST15
INTDST16
INTDST17
INTDST18
INTDST19
INTDST20
INTDST21
INTDST22
INTDST23
EASYNCERR
TETBHFULLINT4
TETBFULLINT4
TETBACQINT4
TETBHFULLINT5
TETBFULLINT5
TETBACQINT5
TETBHFULLINT6
TETBFULLINT6
TETBACQINT6
TETBHFULLINT7
TETBFULLINT7
TETB4 is full
TETB4 acquisition has been completed
TETB5 is half full
TETB5 is full
TETB5 acquisition has been completed
TETB6 is half full
TETB6 is full
TETB6 acquisition has been completed
TETB7 is half full
TETB7 is full
178
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-41
CIC2 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2) (Part 4 of 4)
Input Event # on CIC System Interrupt
Description
129
TETBACQINT7
TETB7 acquisition has been completed
130
TRACER_CORE_4_INTD
TRACER_CORE_5_INTD
TRACER_CORE_6_INTD
TRACER_CORE_7_INTD
SEMERR4
Tracer sliding time window interrupt for individual core
131
Tracer sliding time window interrupt for individual core
132
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
Semaphore error interrupt
QM interrupt
133
134
135
SEMERR5
136
SEMERR6
137
SEMERR7
138
QM_INT_HIGH_0
QM_INT_HIGH_1
QM_INT_HIGH_2
QM_INT_HIGH_3
QM_INT_HIGH_4
QM_INT_HIGH_5
QM_INT_HIGH_6
QM_INT_HIGH_7
QM_INT_HIGH_8
QM_INT_HIGH_9
QM_INT_HIGH_10
QM_INT_HIGH_11
QM_INT_HIGH_12
QM_INT_HIGH_13
QM_INT_HIGH_14
QM_INT_HIGH_15
Reserved
139
QM interrupt
140
QM interrupt
141
QM interrupt
142
QM interrupt
143
QM interrupt
144
QM interrupt
145
QM interrupt
146
QM interrupt
147
QM interrupt
148
QM interrupt
149
QM interrupt
150
QM interrupt
151
QM interrupt
152
QM interrupt
153
QM interrupt
154-159
End of Table 7-41
Table 7-42
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 1 of 3)
Input Event # on CIC
System Interrupt
GPINT0
Description
0
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
GPIO interrupt
1
GPINT1
2
GPINT2
3
GPINT3
4
GPINT4
5
GPINT5
6
GPINT6
7
GPINT7
8
GPINT8
9
GPINT9
10
11
12
13
GPINT10
GPINT11
GPINT12
GPINT13
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-42
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 2 of 3)
Input Event # on CIC
System Interrupt
GPINT14
Description
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
GPIO interrupt
GPINT15
GPIO interrupt
TETBHFULLINT
System TETB is half full
TETBFULLINT
System TETB is full
TETBACQINT
System TETB acquisition has been completed
TETB0 is half full
TETBHFULLINT0
TETBFULLINT0
TETB0 is full
TETBACQINT0
TETB0 acquisition has been completed
TETB1 is half full
TETBHFULLINT1
TETBFULLINT1
TETB1 is full
TETBACQINT1
TETB1 acquisition has been completed
TETB2 is half full
TETBHFULLINT2
TETBFULLINT2
TETB2 is full
TETBACQINT2
TETB2 acquisition has been completed
TETB3 is half full
TETBHFULLINT3
TETBFULLINT3
TETB3 is full
TETBACQINT3
TETB3 acquisition has been completed
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave port
Tracer sliding time window interrupt for semaphore
HyperLink interrupt
TRACER_CORE_0_INTD
TRACER_CORE_1_INTD
TRACER_CORE_2_INTD
TRACER_CORE_3_INTD
TRACER_DDR_INTD
TRACER_MSMC_0_INTD
TRACER_MSMC_1_INTD
TRACER_MSMC_2_INTD
TRACER_MSMC_3_INTD
TRACER_CFG_INTD
TRACER_QM_CFG_INTD
TRACER_QM_DMA_INTD
TRACER_SM_INTD
VUSR_INT_O
TETBHFULLINT4
TETBFULLINT4
TETB4 is half full
TETB4 is full
TETBACQINT4
TETB4 acquisition has been completed
TETB5 is half full
TETBHFULLINT5
TETBFULLINT5
TETB5 is full
TETBACQINT5
TETB5 acquisition has been completed
TETB6 is half full
TETBHFULLINT6
TETBFULLINT6
TETB6 is full
TETBACQINT6
TETB6 acquisition has been completed
TETB7 is half full
TETBHFULLINT7
TETBFULLINT7
TETB7 is full
TETBACQINT7
TETB7 acquisition has been completed
Tracer sliding time window interrupt for individual core
TRACER_CORE_4_INTD
180
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-42
CIC3 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) (Part 3 of 3)
Input Event # on CIC
System Interrupt
TRACER_CORE_5_INTD
TRACER_CORE_6_INTD
TRACER_CORE_7_INTD
DDR3_ERR
Description
58
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core
DDR3 EMIF Error interrupt
59
60
61
62-79
Reserved
End of Table 7-42
7.9.2 CIC Registers
This section includes the offsets for CIC registers. The base addresses for interrupt control registers are CIC0 -
0x0260 0000, CIC1 - 0x0260 4000, CIC2 - 0x0260 8000, and CIC3 - 0x0260 C000.
7.9.2.1 CIC0/CIC1 Register Map
Table 7-43
CIC0/CIC1 Register
Address Offset
0x0
Register Mnemonic
REVISION_REG
Register Name
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
ENA_STATUS_REG0
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENABLE_REG0
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
0x20
0x24
0x28
0x2C
0x34
0x38
0x200
0x204
0x208
0x20C
0x210
0x280
0x284
0x288
0x28c
0x290
0x300
0x304
0x308
0x30c
0x310
0x380
0x384
0x388
0x38c
0x390
0x400
0x404
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enable Register 0
ENABLE_REG1
Enable Register 1
ENABLE_REG2
Enable Register 2
ENABLE_REG3
Enable Register 3
ENABLE_REG4
Enable Register 4
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
CH_MAP_REG0
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
CH_MAP_REG1
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-43
CIC0/CIC1 Register
Address Offset
0x408
0x40c
0x410
0x414
0x418
0x41c
0x420
0x424
0x428
0x42c
0x430
0x434
0x438
0x43c
0x440
0x444
0x448
0x44c
0x450
0x454
0x458
0x45c
0x460
0x464
0x468
0x46c
0x470
0x474
0x478
0x47c
0x480
0x484
0x488
0x48c
0x490
0x494
0x498
0x49c
0x800
0x804
0x808
0x80c
0x810
0x814
Register Mnemonic
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
CH_MAP_REG5
CH_MAP_REG6
CH_MAP_REG7
CH_MAP_REG8
CH_MAP_REG9
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
CH_MAP_REG16
CH_MAP_REG17
CH_MAP_REG18
CH_MAP_REG19
CH_MAP_REG20
CH_MAP_REG21
CH_MAP_REG22
CH_MAP_REG23
CH_MAP_REG24
CH_MAP_REG25
CH_MAP_REG26
CH_MAP_REG27
CH_MAP_REG28
CH_MAP_REG29
CH_MAP_REG30
CH_MAP_REG31
CH_MAP_REG32
CH_MAP_REG33
CH_MAP_REG34
CH_MAP_REG35
CH_MAP_REG36
CH_MAP_REG37
CH_MAP_REG38
CH_MAP_REG39
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
Register Name
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
Interrupt Channel Map Register for 20 to 20+3
Interrupt Channel Map Register for 24 to 24+3
Interrupt Channel Map Register for 28 to 28+3
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Interrupt Channel Map Register for 64 to 64+3
Interrupt Channel Map Register for 68 to 68+3
Interrupt Channel Map Register for 72 to 72+3
Interrupt Channel Map Register for 76 to 76+3
Interrupt Channel Map Register for 80 to 80+3
Interrupt Channel Map Register for 84 to 84+3
Interrupt Channel Map Register for 88 to 88+3
Interrupt Channel Map Register for 92 to 92+3
Interrupt Channel Map Register for 96 to 96+3
Interrupt Channel Map Register for 100 to 100+3
Interrupt Channel Map Register for 104 to 104+3
Interrupt Channel Map Register for 108 to 108+3
Interrupt Channel Map Register for 112 to 112+3
Interrupt Channel Map Register for 116 to 116+3
Interrupt Channel Map Register for 120 to 120+3
Interrupt Channel Map Register for 124 to 124+3
Interrupt Channel Map Register for 128 to 128+3
Interrupt Channel Map Register for 132 to 132+3
Interrupt Channel Map Register for 136 to 136+3
Interrupt Channel Map Register for 140 to 140+3
Interrupt Channel Map Register for 144 to 144+3
Interrupt Channel Map Register for 148 to 148+3
Interrupt Channel Map Register for 152 to 152+3
Interrupt Channel Map Register for 156 to 156+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
182
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-43
CIC0/CIC1 Register
Address Offset
0x818
Register Mnemonic
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
HINT_MAP_REG13
HINT_MAP_REG14
HINT_MAP_REG15
HINT_MAP_REG16
HINT_MAP_REG17
HINT_MAP_REG18
ENABLE_HINT_REG0
ENABLE_HINT_REG1
ENABLE_HINT_REG2
Register Name
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Interrupt Map Register for 52 to 52+3
Host Interrupt Map Register for 56 to 56+3
Host Interrupt Map Register for 60 to 60+3
Host Interrupt Map Register for 64 to 64+3
Host Interrupt Map Register for 68 to 68+3
Host Interrupt Map Register for 72 to 72+3
Host Int Enable Register 0
0x81c
0x820
0x824
0x828
0x82c
0x830
0x834
0x838
0x83c
0x840
0x844
0x848
0x1500
0x1504
0x1508
Host Int Enable Register 1
Host Int Enable Register 2
End of Table 7-43
7.9.2.2 CIC2 Register Map
Table 7-44
CIC2 Register
Address Offset
0x0
Register Mnemonic
Register Name
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
ENA_STATUS_REG0
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENABLE_REG0
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enable Register 0
0x20
0x24
0x28
0x2c
0x34
0x38
0x200
0x204
0x208
0x20c
0x210
0x280
0x284
0x288
0x28c
0x290
0x300
0x304
0x308
0x30c
ENABLE_REG1
Enable Register 1
ENABLE_REG2
Enable Register 2
ENABLE_REG3
Enable Register 3
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-44
CIC2 Register
Address Offset
0x310
0x380
0x384
0x388
0x38c
0x390
0x400
0x404
0x408
0x40c
0x410
0x414
0x418
0x41c
0x420
0x424
0x428
0x42c
0x430
0x434
0x438
0x43c
0x440
0x444
0x448
0x44c
0x450
0x454
0x458
0x45c
0x460
0x464
0x468
0x46c
0x470
0x474
0x478
0x47c
0x480
0x484
0x488
0x48c
0x490
0x494
Register Mnemonic
Register Name
ENABLE_REG4
Enable Register 4
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
CH_MAP_REG0
CH_MAP_REG1
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
CH_MAP_REG5
CH_MAP_REG6
CH_MAP_REG7
CH_MAP_REG8
CH_MAP_REG9
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
CH_MAP_REG16
CH_MAP_REG17
CH_MAP_REG18
CH_MAP_REG19
CH_MAP_REG20
CH_MAP_REG21
CH_MAP_REG22
CH_MAP_REG23
CH_MAP_REG24
CH_MAP_REG25
CH_MAP_REG26
CH_MAP_REG27
CH_MAP_REG28
CH_MAP_REG29
CH_MAP_REG30
CH_MAP_REG31
CH_MAP_REG32
CH_MAP_REG33
CH_MAP_REG34
CH_MAP_REG35
CH_MAP_REG36
CH_MAP_REG37
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
Interrupt Channel Map Register for 20 to 20+3
Interrupt Channel Map Register for 24 to 24+3
Interrupt Channel Map Register for 28 to 28+3
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Interrupt Channel Map Register for 64 to 64+3
Interrupt Channel Map Register for 68 to 68+3
Interrupt Channel Map Register for 72 to 72+3
Interrupt Channel Map Register for 76 to 76+3
Interrupt Channel Map Register for 80 to 80+3
Interrupt Channel Map Register for 84 to 84+3
Interrupt Channel Map Register for 88 to 88+3
Interrupt Channel Map Register for 92 to 92+3
Interrupt Channel Map Register for 96 to 96+3
Interrupt Channel Map Register for 100 to 100+3
Interrupt Channel Map Register for 104 to 104+3
Interrupt Channel Map Register for 108 to 108+3
Interrupt Channel Map Register for 112 to 112+3
Interrupt Channel Map Register for 116 to 116+3
Interrupt Channel Map Register for 120 to 120+3
Interrupt Channel Map Register for 124 to 124+3
Interrupt Channel Map Register for 128 to 128+3
Interrupt Channel Map Register for 132 to 132+3
Interrupt Channel Map Register for 136 to 136+3
Interrupt Channel Map Register for 140 to 140+3
Interrupt Channel Map Register for 144 to 144+3
Interrupt Channel Map Register for 148 to 148+3
184
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-44
CIC2 Register
Address Offset
0x498
Register Mnemonic
Register Name
CH_MAP_REG38
CH_MAP_REG39
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
HINT_MAP_REG10
HINT_MAP_REG11
HINT_MAP_REG12
ENABLE_HINT_REG0
ENABLE_HINT_REG1
Interrupt Channel Map Register for 152 to 152+3
Interrupt Channel Map Register for 156 to 156+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Interrupt Map Register for 40 to 40+3
Host Interrupt Map Register for 44 to 44+3
Host Interrupt Map Register for 48 to 48+3
Host Int Enable Register 0
0x49c
0x800
0x804
0x808
0x80c
0x810
0x814
0x818
0x81c
0x820
0x824
0x828
0x82c
0x830
0x1500
0x1504
End of Table 7-44
Host Int Enable Register 1
7.9.2.3 CIC3 Register Map
Table 7-45
CIC3 Register
Address Offset
0x0
Register Mnemonic
Register Name
REVISION_REG
Revision Register
0x10
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
ENA_STATUS_REG0
ENA_STATUS_REG1
ENABLE_REG0
Global Host Int Enable Register
Status Set Index Register
0x20
0x24
Status Clear Index Register
Enable Set Index Register
0x28
0x2c
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
0x34
0x38
0x200
0x204
0x280
0x284
0x300
0x304
0x380
0x384
0x400
0x404
0x408
0x40c
0x410
Raw Status Register 1
Enabled Status Register 0
Enabled Status Register 1
Enable Register 0
ENABLE_REG1
Enable Register 1
ENABLE_CLR_REG0
ENABLE_CLR_REG1
CH_MAP_REG0
Enable Clear Register 0
Enable Clear Register 1
Interrupt Channel Map Register for 0 to 0+3
Interrupt Channel Map Register for 4 to 4+3
Interrupt Channel Map Register for 8 to 8+3
Interrupt Channel Map Register for 12 to 12+3
Interrupt Channel Map Register for 16 to 16+3
CH_MAP_REG1
CH_MAP_REG2
CH_MAP_REG3
CH_MAP_REG4
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-45
CIC3 Register
Address Offset
0x414
Register Mnemonic
Register Name
CH_MAP_REG5
Interrupt Channel Map Register for 20 to 20+3
Interrupt Channel Map Register for 24 to 24+3
Interrupt Channel Map Register for 28 to 28+3
Interrupt Channel Map Register for 32 to 32+3
Interrupt Channel Map Register for 36 to 36+3
Interrupt Channel Map Register for 40 to 40+3
Interrupt Channel Map Register for 44 to 44+3
Interrupt Channel Map Register for 48 to 48+3
Interrupt Channel Map Register for 52 to 52+3
Interrupt Channel Map Register for 56 to 56+3
Interrupt Channel Map Register for 60 to 60+3
Host Interrupt Map Register for 0 to 0+3
Host Interrupt Map Register for 4 to 4+3
Host Interrupt Map Register for 8 to 8+3
Host Interrupt Map Register for 12 to 12+3
Host Interrupt Map Register for 16 to 16+3
Host Interrupt Map Register for 20 to 20+3
Host Interrupt Map Register for 24 to 24+3
Host Interrupt Map Register for 28 to 28+3
Host Interrupt Map Register for 32 to 32+3
Host Interrupt Map Register for 36 to 36+3
Host Int Enable Register 0
0x418
CH_MAP_REG6
0x41c
CH_MAP_REG7
0x420
CH_MAP_REG8
0x424
CH_MAP_REG9
0x428
CH_MAP_REG10
CH_MAP_REG11
CH_MAP_REG12
CH_MAP_REG13
CH_MAP_REG14
CH_MAP_REG15
HINT_MAP_REG0
HINT_MAP_REG1
HINT_MAP_REG2
HINT_MAP_REG3
HINT_MAP_REG4
HINT_MAP_REG5
HINT_MAP_REG6
HINT_MAP_REG7
HINT_MAP_REG8
HINT_MAP_REG9
ENABLE_HINT_REG0
ENABLE_HINT_REG1
0x42c
0x430
0x434
0x438
0x43c
0x800
0x804
0x808
0x80c
0x810
0x814
0x818
0x81c
0x820
0x824
0x1500
0x1504
End of Table 7-45
Host Int Enable Register 1
7.9.3 Inter-Processor Register Map
Table 7-46
IPC Generation Registers (IPCGRx) (Part 1 of 2)
Address Start
0x02620200
0x02620204
0x02620208
0x0262020C
0x02620210
0x02620214
0x02620218
0x0262021C
0x02620220
0x02620240
0x02620244
0x02620248
0x0262024C
0x02620250
0x02620254
Address End
0x02620203
0x02620207
0x0262020B
0x0262020F
0x02620213
0x02620217
0x0262021B
0x0262021F
0x0262023F
0x02620243
0x02620247
0x0262024B
0x0262024F
0x02620253
0x02620257
Size
4B
4B
4B
4B
4B
4B
4B
4B
32B
4B
4B
4B
4B
4B
4B
Register Name
Description
NMIGR0
NMIGR1
NMIGR2
NMIGR3
NMIGR4
NMIGR5
NMIGR6
NMIGR7
Reserved
IPCGR0
IPCGR1
IPCGR2
IPCGR3
IPCGR4
IPCGR5
NMI Event Generation Register for CorePac0
NMI Event Generation Register for CorePac1
NMI Event Generation Register for CorePac2
NMI Event Generation Register for CorePac3
NMI Event Generation Register for CorePac4
NMI Event Generation Register for CorePac5
NMI Event Generation Register for CorePac6
NMI Event Generation Register for CorePac7
Reserved
IPC Generation Register for CorePac0
IPC Generation Register for CorePac1
IPC Generation Register for CorePac2
IPC Generation Register for CorePac3
IPC Generation Register for CorePac4
IPC Generation Register for CorePac5
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Table 7-46
IPC Generation Registers (IPCGRx) (Part 2 of 2)
Address Start
0x02620258
0x0262025C
0x02620260
0x0262027C
0x02620280
0x02620284
0x02620288
0x0262028C
0x02620290
0x02620294
0x02620298
0x0262029C
0x026202A0
0x026202BC
End of Table 7-46
Address End
0x0262025B
0x0262025F
0x0262027B
0x0262027F
0x02620283
0x02620287
0x0262028B
0x0262028F
0x02620293
0x02620297
0x0262029B
0x0262029F
0x026202BB
0x026202BF
Size
4B
Register Name
IPCGR6
Description
IPC Generation Register for CorePac6
IPC Generation Register for CorePac7
Reserved
4B
IPCGR7
28B
4B
Reserved
IPCGRH
IPCAR0
IPC Generation Register for Host
4B
IPC Acknowledgement Register for CorePac0
IPC Acknowledgement Register for CorePac1
IPC Acknowledgement Register for CorePac2
IPC Acknowledgement Register for CorePac3
IPC Acknowledgement Register for CorePac4
IPC Acknowledgement Register for CorePac5
IPC Acknowledgement Register for CorePac6
IPC Acknowledgement Register for CorePac7
Reserved
4B
IPCAR1
4B
IPCAR2
4B
IPCAR3
4B
IPCAR4
4B
IPCAR5
4B
IPCAR6
4B
IPCAR7
28B
4B
Reserved
IPCARH
IPC Acknowledgement Register for Host
7.9.4 NMI and LRESET
Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by
software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One
NMI pin and one LRESET pin are shared by all CorePacs on the device. The CORESEL[3:0] pins can be configured
to select between the CorePacs available as shown in Table 7-47.
Table 7-47
LRESET and NMI Decoding (Part 1 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
XXXX
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
0000
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No local reset or NMI assertion.
Assert local reset to CorePac0
Assert local reset to CorePac1
Assert local reset to CorePac2
Assert local reset to CorePac3
Assert local reset to CorePac4
Assert local reset to CorePac5
Assert local reset to CorePac6
Assert local reset to CorePac7
Assert local reset to all CorePacs
De-assert local reset & NMI to CorePac0
De-assert local reset & NMI to CorePac1
De-assert local reset & NMI to CorePac2
De-assert local reset & NMI to CorePac3
De-assert local reset & NMI to CorePac4
De-assert local reset & NMI to CorePac5
De-assert local reset & NMI to CorePac6
De-assert local reset & NMI to CorePac7
De-assert local reset & NMI to all CorePacs
Assert NMI to CorePac0
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Table 7-47
LRESET and NMI Decoding (Part 2 of 2)
CORESEL[3:0] Pin Input LRESET Pin Input NMI Pin Input LRESETNMIEN Pin Input Reset Mux Block Output
0001
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Assert NMI to CorePac1
Assert NMI to CorePac2
Assert NMI to CorePac3
Assert NMI to CorePac4
Assert NMI to CorePac5
Assert NMI to CorePac6
Assert NMI to CorePac7
Assert NMI to all CorePacs
0010
0011
0100
0101
0110
0111
1xxx
End of Table 7-47
7.9.5 External Interrupts Electrical Data/Timing
Table 7-48
(see Figure 7-30)
NMI and Local Reset Timing Requirements (1)
No.
Min
12*P
12*P
12*P
12*P
12*P
12*P
12*P
Max Unit
1
1
1
2
2
2
3
tsu(LRESET-LRESETNMIENL)
Setup Time - LRESET valid before LRESETNMIEN low
Setup Time - NMI valid before LRESETNMIEN low
Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
Hold Time - LRESET valid after LRESETNMIEN high
Hold Time - NMI valid after LRESETNMIEN high
Hold Time - CORESEL[2:0] valid after LRESETNMIEN high
Pulse Width - LRESETNMIEN low width
ns
ns
ns
ns
ns
ns
ns
tsu(NMI-LRESETNMIENL)
tsu(CORESELn-LRESETNMIENL)
th(LRESETNMIENL-LRESET)
th(LRESETNMIENL-NMI)
th(LRESETNMIENL-CORESELn)
tw(LRESETNMIEN)
End of Table 7-48
1 P = 1/SYSCLK1 frequency in ns.
Figure 7-30
NMI and Local Reset Timing
1
2
CORESEL[3:0]/
LRESET/
NMI
3
LRESETNMIEN
7.9.6 Host Interrupt Output
The C66x CorePac can assert an event to the external host processor using HOUT. Table 7-49 provides the timing
for the HOUT pulse. For more details, see section 3.3.15 .
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Table 7-49
(see Figure 7-31)
HOUT Switching Characteristics
No.
Min
24*P (1)
Max
Unit
ns
1
2
tw(HOUTH)
tw(HOUTL)
HOUT pulse duration high
HOUT pulse duration low
24*P
ns
End of Table 7-49
1 P = 1/SYSCLK1 frequency in ns.
Figure 7-31
HOUT Timing
1
2
HOUT
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7.10 Memory Protection Unit (MPU)
The C6678 supports four MPUs:
•
•
One MPU is used to protect
main CORE/3 CFG TeraNet
(CFG space of all slave devices
•
One MPU is used for
Semaphore.
registers, see the Memory Protection
Unit (MPU) for KeyStone Devices User
Guide in ‘‘Related Documentation
on the TeraNet is protected by This section contains MPU register from Texas Instruments’’ on page 73.
the MPU).
map and details of device-specific
MPU registers only. For MPU
The following tables show the
configuration of each MPU and the
memory regions protected by each
MPU.
Two MPUs are used for QM_SS
(one for DATA PORT port and
another is for CFG PORT port).
features and details of generic MPU
Table 7-50
Setting
MPU Default Configuration
MPU0
MPU1
MPU2
(QM_SS CFG PORT)
MPU3
(Semaphore)
(Main CFG TeraNet) (QM_SS DATA PORT)
Default permission
Assume allowed
Assume allowed
Assume allowed
Assume allowed
Number of allowed IDs supported
Number of programmable ranges supported
Compare width
16
16
16
16
16
5
16
1
1KB granularity
1KB granularity
1KB granularity
1KB granularity
End of Table 7-50
Table 7-51
MPU Memory Regions
Memory Protection
Main CFG TeraNet
QM_SS DATA PORT
QM_SS CFG PORT
Semaphore
Start Address
0x01D00000
0x34000000
0x02A00000
0x02640000
End Address
0x026207FF
0x340BFFFF
0x02ABFFFF
0x026407FF
MPU0
MPU1
MPU2
MPU3
Table 7-52 shows the privilege ID of each CORE and every mastering peripheral. Table 7-52 also shows the privilege
level (supervisor vs. user), security level (secure vs. non-secure), and access type (instruction read vs. data/DMA read
or write) of each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 7-52
Privilege ID Settings (Part 1 of 2)
Privilege ID Master
Privilege Level
Security Level
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
SW dependant
Non-secure
Access Type
DMA
0
1
2
3
4
5
6
7
8
CorePac0
CorePac1
CorePac2
CorePac3
CorePac4
CorePac5
CorePac6
CorePac7
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
SW dependant, driven by MSMC
User
DMA
DMA
DMA
DMA
DMA
DMA
DMA
Network Coprocessor
Packet DMA
DMA
9
SRIO Packet DMA/SRIO_M User/Driven by SRIO block, User mode and supervisor mode is
determined on a per-transaction basis. Only the transaction with
source ID matching the value in the SupervisorID register is granted
supervisor mode.
Non-secure
DMA
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Table 7-52
Privilege ID Settings (Part 2 of 2)
Privilege ID Master
Privilege Level
Security Level
Access Type
10
QM_SS Packet
DMA/QM_SS Second
User
Non-secure
DMA
11
12
13
14
15
PCIe
Driven by PCIe module
Driven by Debug_SS
Driven by HyperLink
Supervisor
Non-secure
DMA
Debug_SS
HyperLink
HyperLink
TSIP0/1
Driven by Debug_SS DMA
Non-secure
Non-secure
Non-secure
DMA
DMA
DMA
User
End of Table 7-52
Table 7-53 shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine
allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters,
master IDs are unique to each master.
Table 7-53
Master ID Settings (Part 1 of 2) (1)
Master ID
Master
0
CorePac0
1
CorePac1
2
CorePac2
3
CorePac3
4
CorePac4
5
CorePac5
6
CorePac6
7
CorePac7
8
CorePac0_CFG
CorePac1_CFG
CorePac2_CFG
CorePac3_CFG
CorePac4_CFG
CorePac5_CFG
CorePac6_CFG
CorePac7_CFG
EDMA0_TC0 read
EDMA0_TC0 write
EDMA0_TC1 read
EDMA0_TC1 write
EDMA1_TC0 read
EDMA1_TC0 write
EDMA1_TC1 read
EDMA1_TC1 write
EDMA1_TC2 read
EDMA1_TC2 write
EDMA1_TC3 read
EDMA1_TC3 write
EDMA2_TC0 read
EDMA2_TC0 write
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
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Table 7-53
Master ID Settings (Part 2 of 2) (1)
Master ID
Master
30
EDMA2_TC1 read
EDMA2_TC1 write
EDMA2_TC2 read
EDMA2_TC2 write
EDMA2_TC3 read
EDMA2_TC3 write
Reserved
31
32
33
34
35
36 - 37
38 - 39
40 - 47
48
SRIO Packet DMA
Reserved
Debug SS
49
EDMA3CC0
50
EDMA3CC1
51
EDMA3CC2
52
MSMC (2)
53
PCIe
54
SRIO_Master
55
HyperLink
56 - 59
60 - 85
86
Network Coprocessor Packet DMA
Reserved
TSIP0
87
TSIP1
88 - 91
92 - 93
94 - 127
128
Queue Manager Packet DMA
Queue Manager Second
Reserved
Tracer_core_0 (3)
Tracer_core_1
Tracer_core_2
Tracer_core_3
Tracer_core_4
Tracer_core_5
Tracer_core_6
Tracer_core_7
Tracer_MSMC0
Tracer_MSMC1
Tracer_MSMC2
Tracer_MSMC3
Tracer_DDR
129
130
131
132
133
134
135
136
137
138
139
140
141
Tracer_SM
142
Tracer_QM_CFG
Tracer_QM_DMA
Tracer_CFG
143
144
End of Table 7-53
1 Some of the Packet DMA-based peripherals require multiple master IDs. Queue Manager Packet DMA is assigned with 88,89,90,91, but only 88-89 are actually used. For
Network Coprocessor Packet DMA port, 56,57,58,59 are assigned while only 1 (56) is actually used. There are two master ID values are assigned for the Queue Manager
Second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses.
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2 The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.
3 All Traces are set to the same master ID and bit 7 of the master ID needs to be 1.
7.10.1 MPU Registers
This section includes the offsets for MPU registers and definitions for device specific MPU registers.
7.10.1.1 MPU Register Map
Table 7-54
MPU0 Registers (Part 1 of 2)
Offset
0h
Name
Description
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
204h
208h
210h
214h
218h
220h
224h
228h
230h
234h
238h
240h
244h
248h
250h
254h
258h
260h
264h
268h
270h
274h
278h
280h
284h
288h
290h
294h
298h
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPA
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPA
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPA
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPA
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
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Table 7-54
MPU0 Registers (Part 2 of 2)
Offset
2A0h
2A4h
2A8h
2B0h
2B4h
2B8h
2C0h
2C4h
2C8h
2D0h
2D4h
2Dh
Name
Description
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPA
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPA
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPA
PROG13_MPSAR
PROG13_MPEAR
PROG13_MPPA
PROG14_MPSAR
PROG14_MPEAR
PROG14_MPPA
PROG15_MPSAR
PROG15_MPEAR
PROG15_MPPA
FLTADDRR
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Programmable range 13, start address
Programmable range 13, end address
Programmable range 13, memory page protection attributes
Programmable range 14, start address
Programmable range 14, end address
Programmable range 14, memory page protection attributes
Programmable range 15, start address
Programmable range 15, end address
Programmable range 15, memory page protection attributes
Fault address
2E0h
2E4h
2E8h
2F0h
2F4h
2F8h
300h
304h
308h
FLTSTAT
Fault status
FLTCLR
Fault clear
End of Table 7-54
Table 7-55
MPU1 Registers (Part 1 of 2)
Offset
0h
Name
Description
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
204h
208h
210h
214h
218h
220h
224h
228h
230h
234h
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPA
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
PROG3_MPSAR
PROG3_MPEAR
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Programmable range 3, start address
Programmable range 3, end address
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Table 7-55
MPU1 Registers (Part 2 of 2)
Offset
238h
240h
244h
248h
300h
304h
308h
Name
Description
PROG3_MPPA
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
FLTADDRR
FLTSTAT
Programmable range 3, memory page protection attributes
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Fault address
Fault status
FLTCLR
Fault clear
End of Table 7-55
Table 7-56
MPU2 Registers (Part 1 of 2)
Offset
0h
Name
Description
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
Interrupt raw status/set
14h
IENSTAT
Interrupt enable status/clear
18h
IENSET
Interrupt enable
1Ch
IENCLR
Interrupt enable clear
20h
EOI
End of interrupt
200h
204h
208h
210h
214h
218h
220h
224h
228h
230h
234h
238h
240h
244h
248h
250h
254h
258h
260h
264h
268h
270h
274h
278h
280h
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPA
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
PROG4_MPSAR
PROG4_MPEAR
PROG4_MPPA
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPA
PROG8_MPSAR
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Programmable range 8, start address
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Table 7-56
MPU2 Registers (Part 2 of 2)
Offset
284h
288h
290h
294h
298h
2A0h
2A4h
2A8h
2B0h
2B4h
2B8h
2C0h
2C4h
2C8h
2D0h
2D4h
2Dh
Name
Description
PROG8_MPEAR
PROG8_MPPA
PROG9_MPSAR
PROG9_MPEAR
PROG9_MPPA
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPA
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPA
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPA
PROG13_MPSAR
PROG13_MPEAR
PROG13_MPPA
PROG14_MPSAR
PROG14_MPEAR
PROG14_MPPA
PROG15_MPSAR
PROG15_MPEAR
PROG15_MPPA
FLTADDRR
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Programmable range 9, start address
Programmable range 9, end address
Programmable range 9, memory page protection attributes
Programmable range 10, start address
Programmable range 10, end address
Programmable range 10, memory page protection attributes
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Programmable range 13, start address
Programmable range 13, end address
Programmable range 13, memory page protection attributes
Programmable range 14, start address
Programmable range 14, end address
Programmable range 14, memory page protection attributes
Programmable range 15, start address
Programmable range 15, end address
Programmable range 15, memory page protection attributes
Fault address
2E0h
2E4h
2E8h
2F0h
2F4h
2F8h
300h
304h
308h
FLTSTAT
Fault status
FLTCLR
Fault clear
End of Table 7-56
Table 7-57
MPU3 Registers (Part 1 of 2)
Offset
0h
Name
Description
REVID
Revision ID
4h
CONFIG
Configuration
10h
IRAWSTAT
IENSTAT
Interrupt raw status/set
Interrupt enable status/clear
Interrupt enable
14h
18h
IENSET
1Ch
20h
IENCLR
Interrupt enable clear
EOI
End of interrupt
200h
204h
208h
300h
PROG0_MPSAR
PROG0_MPEAR
PROG0_MPPA
FLTADDRR
Programmable range 0, start address
Programmable range 0, end address
Programmable range 0, memory page protection attributes
Fault address
196
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Table 7-57
MPU3 Registers (Part 2 of 2)
Offset
304h
Name
Description
Fault status
Fault clear
FLTSTAT
FLTCLR
308h
End of Table 7-57
7.10.1.2 Device-Specific MPU Registers
7.10.1.2.1 Configuration Register (CONFIG)
The configuration register (CONFIG) contains the configuration value of the MPU.
Figure 7-32
Configuration Register (CONFIG)
31
24
23
20
19
16
15
12
11
1
0
ADDR_WIDTH
NUM_FIXED
NUM_PROG
R-16
NUM_AIDS
R-16
Reserved
R-0
ASSUME_ALLOWED
MPU0
MPU1
MPU2
MPU3
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-1
R-1
R-1
R-1
R-5
R-16
R-0
Reset Values
R-16
R-16
R-0
R-1
R-16
R-0
Legend: R = Read only; -n = value after reset
Table 7-58
Configuration Register (CONFIG) Field Descriptions
Bit
Field Description
31 – 24 ADDR_WIDTH
Address alignment for range checking
0 = 1KB alignment
6 = 64KB alignment
23 – 20 NUM_FIXED
19 – 16 NUM_PROG
15 – 12 NUM_AIDS
Number of fixed address ranges
Number of programmable address ranges
Number of supported AIDs
11 – 1
0
Reserved
Reserved. These bits will always reads as 0.
ASSUME_ALLOWED
Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the
transfer is assumed to be allowed or not.
0 = Assume disallowed
1 = Assume allowed
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7.10.2 MPU Programmable Range Registers
7.10.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
The programmable address start register holds the start address for the range. This register is writeable by a
supervisor entity only. If NS = 0 (non-secure mode) in the associated MPPA register, then the register is also
writeable only by a secure entity.
The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines
the width of the address field in MPSAR and MPEAR.
Figure 7-33
Programmable Range n Start Address Register (PROGn_MPSAR)
31
10
9
0
START_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-59
Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions
Bit
Field
Description
31 – 10
9 – 0
START_ADDR
Reserved
Start address for range n.
Reserved and these bits always read as 0.
End of Table 7-59
7.10.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
The programmable address end register holds the end address for the range. This register is writeable by a supervisor
entity only. If NS = 0 (non-secure mode) in the associated MPPA register then the register is also only writeable by
a secure entity.
The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page
size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field
in MPSAR and MPEAR
Figure 7-34
Programmable Range n End Address Register (PROGn_MPEAR)
31
10
9
0
END_ADDR
R/W
Reserved
R
Legend: R = Read only; R/W = Read/Write
Table 7-60
Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions
Bit
Field
Description
31 – 10
9 – 0
END_ADDR
Reserved
End address for range n.
Reserved and these bits always read as 3FFh.
End of Table 7-60
198
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Multicore Fixed and Floating-Point Digital Signal Processor
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7.10.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
The programmable address memory protection page attribute register holds the permissions for the region. This
register is writeable only by a non-debug supervisor entity. If NS = 0 (secure mode) then the register is also only
writeable by a non-debug secure entity. The NS bit is only writeable by a non-debug secure entity. For debug accesses
the register is writeable only when NS = 1 or EMU = 1.
Figure 7-35
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
31
26
25
24
23
22
21
20
19
18
17
16
15
Reserved
R
AID15 AID14 AID13 AID12 AID11 AID10
AID9
R/W
AID8
R/W
AID7
R/W
AID6
R/W
AID5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AID4
R/W
AID3
R/W
AID2
R/W
AID1
R/W
AID0
R/W
AIDX
R/W
Reserved
R
NS
EMU
R/W
SR
SW
R/W
SX
UR
UW
R/W
UX
R/W
R/W
R/W
R/W
R/W
Legend: R = Read only; R/W = Read/Write
Table 7-61
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 1 of 2)
Bit
Field
Description
31 – 26
25
Reserved
AID15
Reserved. These bits will always reads as 0.
Controls permission check of ID = 15
0 = AID is not checked for permissions
1 = AID is checked for permissions
24
23
22
21
20
19
18
17
16
AID14
AID13
AID12
AID11
AID10
AID9
Controls permission check of ID = 14
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 13
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 12
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 11
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 10
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 9
0 = AID is not checked for permissions
1 = AID is checked for permissions
AID8
Controls permission check of ID = 8
0 = AID is not checked for permissions
1 = AID is checked for permissions
AID7
Controls permission check of ID = 7
0 = AID is not checked for permissions
1 = AID is checked for permissions
AID6
Controls permission check of ID = 6
0 = AID is not checked for permissions
1 = AID is checked for permissions
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Table 7-61
Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field Descriptions
(Part 2 of 2)
Bit
Field
Description
15
AID5
AID4
AID3
AID2
AID1
AID0
AIDX
Controls permission check of ID = 5
0 = AID is not checked for permissions
1 = AID is checked for permissions
14
13
12
11
10
9
Controls permission check of ID = 4
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 3
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 2
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 1
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID = 0
0 = AID is not checked for permissions
1 = AID is checked for permissions
Controls permission check of ID > 15
0 = AID is not checked for permissions
1 = AID is checked for permissions
8
7
Reserved
NS
Always reads as 0.
Non-secure access permission
0 = Only secure access allowed.
1 = Non-secure access allowed.
6
5
4
3
2
1
0
EMU
SR
Emulation (debug) access permission. This bit is ignored if NS = 1
0 = Debug access not allowed.
1 = Debug access allowed.
Supervisor Read permission
0 = Access not allowed.
1 = Access allowed.
SW
SX
Supervisor Write permission
0 = Access not allowed.
1 = Access allowed.
Supervisor Execute permission
0 = Access not allowed.
1 = Access allowed.
UR
User Read permission
0 = Access not allowed.
1 = Access allowed
UW
UX
User Write permission
0 = Access not allowed.
1 = Access allowed.
User Execute permission
0 = Access not allowed.
1 = Access allowed.
End of Table 7-611
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7.10.2.4 MPU Registers Reset Values
Table 7-62
Programmable Range n Registers Reset Values for MPU0
MPU0 (Main CFG TeraNet)
Programmable Start Address
Range
End Address
Memory Page Protection
Attribute (PROGn_MPPA)
(PROGn_MPSAR)
0x01D0_0000
0x01F0_0000
0x0200_0000
0x01E0_0000
0x021C_0000
0x021F_0000
0x0220_0000
0x0231_0000
0x0232_0000
0x0233_0000
0x0235_0000
0x0240_0000
0x0250_0000
0x0253_0000
0x0260_0000
0x0262_0000
(PROGn_MPEAR)
0x01D8_03FF
0x01F7_FFFF
0x0209_FFFF
0x01EB_FFFF
0x021E_0FFF
0x021F_7FFF
0x022F_03FF
0x0231_03FF
0x0232_03FF
0x0233_03FF
0x0235_0FFF
0x024B_3FFF
0x0252_03FF
0x0254_03FF
0x0260_FFFF
0x0262_07FF
Memory Protection
PROG0
0x03FF_FCB6
0x03FF_FC80
0x03FF_FCB6
0x03FF_FCB6
0x03FF_FC80
0x03FF_FC80
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB6
0x03FF_FCB4
0x03FF_FCB4
Tracers
PROG1
Reserved
PROG2
NETCP
PROG3
TSIP
PROG4
Reserved
PROG5
Reserved
PROG6
Timers
PROG7
PLL
PROG8
GPIO
PROG9
SmartReflex
PROG10
PROG11
PROG12
PROG13
PROG14
PROG15
End of Table 7-62
PSC
DEBUG_SS, Tracer Formatters
Reserved
I2C, UART
CICs
Chip-level Registers
Table 7-63
Programmable Range n Registers Reset Values for MPU1
MPU1 (QM_SS DATA PORT)
Programmable Start Address
End Address
(PROGn_MPEAR)
Memory Page Protection
Attribute (PROGn_MPPA)
Range
(PROGn_MPSAR)
0x3400_0000
0x3402_0000
0x3406_0000
0x3406_8000
0x340B_8000
Memory Protection
PROG0
0x3401_FFFF
0x3405_FFFF
0x3406_7FFF
0x340B_7FFF
0x340B_FFFF
0x03FF_FC80
0x000F_FCB6
0x03FF_FCB4
0x03FF_FC80
0x03FF_FCB6
Queue Manager subsystem
data
PROG1
PROG2
PROG3
PROG4
End of Table 7-63
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Table 7-64
Programmable Range n Registers Reset Values for MPU2
MPU2 (QM_SS CFG PORT)
Memory Page Protection
Programmable Start Address
End Address
Range
(PROGn_MPSAR)
0x02A0_0000
0x02A2_0000
0x02A4_0000
0x02A6_0000
0x02A6_8000
0x02A6_9000
0x02A6_A000
0x02A6_B000
0x02A6_C000
0x02A6_E000
0x02A8_0000
0x02A9_0000
0x02AA_0000
0x02AA_8000
0x02AB_0000
0x02AB_8000
(PROGn_MPEAR)
Attribute (PROGn_MPPA)
0x03FF_FCA4
0x000F_FCB6
0x000F_FCB6
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCA4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB4
0x03FF_FCB6
Memory Protection
PROG0
0x02A1_FFFF
0x02A3_FFFF
0x02A5_FFFF
0x02A6_7FFF
0x02A6_8FFF
0x02A6_9FFF
0x02A6_AFFF
0x02A6_BFFF
0x02A6_DFFF
0x02A6_FFFF
0x02A8_FFFF
0x02A9_FFFF
0x02AA_7FFF
0x02AA_FFFF
0x02AB_7FFF
0x02AB_FFFF
Queue Manager subsystem
configuration
PROG1
PROG2
PROG3
PROG4
PROG5
PROG6
PROG7
PROG8
PROG9
PROG10
PROG11
PROG12
PROG13
PROG14
PROG15
End of Table 7-64
Table 7-65
Programmable Range n Registers Reset Values for MPU3
MPU3 (Semaphore)
Programmable Start Address
End Address
(PROGn_MPEAR)
Memory Page Protection
Attributes (PROGn_MPPA)
Range
(PROGn_MPSAR)
Memory Protection
PROG0
0x0264_0000
0x0264_07FF
0x0003_FCB6
Semaphore
End of Table 7-65
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7.11 DDR3 Memory Controller
The 64-bit DDR3 Memory Controller bus of the TMS320C6678 is used to interface to JEDEC standard-compliant
DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus
with any other types of peripherals.
7.11.1 DDR3 Memory Controller Device-Specific Information
The TMS320C6678 includes one 64-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate
at 800 Mega Transfers per Second (MTS), 1066 MTS, 1333 MTS, and 1600 MTS.
Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit,
32-bit, or 64-bit interface.
The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C. Standard DDR3
SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the
interface:
•
•
•
•
•
•
•
•
•
•
72-bit: Five 16-bit SDRAMs (including 8 bits of ECC)
72-bit: Nine 8-bit SDRAMs (including 8 bits of ECC)
36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)
36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)
64-bit: Four 16-bit SDRAMs
64-bit: Eight 8-bit SDRAMs
32-bit: Two 16-bit SDRAMs
32-bit: Four 8-bit SDRAMs
16-bit: One 16-bit SDRAM
16-bit: Two 8-bit SDRAM
The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as
I2C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O
buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible
DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.
7.11.2 DDR3 Memory Controller Race Condition Consideration
A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if
master A passes a software message via a buffer in external memory and does not wait for an indication that the write
completes, before signaling to master B that the message is ready, when master B attempts to read the software
message, then the master B read may bypass the master A write and, thus, master B may read stale data and,
therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to
complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write to DDR3 memory space.
2. Perform a dummy write to the DDR3 memory controller module ID and revision register.
3. Perform a dummy read to the DDR3 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of
the read in step 3 ensures that the previous write was done.
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7.11.3 DDR3 Memory Controller Electrical Data/Timing
The KeyStone DSP DDR3 Implementation Guidelines in ‘‘Related Documentation from Texas Instruments’’ on
page 73 specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3
electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the
simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no
electrical data/timing information is supplied here for this interface.
Note—TI supports only designs that follow the board design guidelines outlined in the application report.
7.12 I2C Peripheral
The inter-integrated circuit (I2C) module provides an interface between DSP and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by way of an I2C bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module.
7.12.1 I2C Device-Specific Information
The TMS320C6678 device includes an I2C peripheral module.
Note—When using the I2C module, ensure there are external pullup resistors on the SDA and SCL pins.
The I2C modules on the C6678 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may
be used to communicate with other controllers in a system or to implement a user interface.
The I2C port is compatible with Philips I2C specification revision 2.1 (January 2000) and supports:
•
•
•
•
•
•
Fast mode up to 400 Kbps (no fail-safe I/O buffers)
Noise filter to remove noise 50 ns or less
7-bit and 10-bit device addressing modes
Multi-master (transmit/receive) and slave (transmit/receive) functionality
Events: DMA, interrupt, or polling
Slew-rate limited open-drain output buffers
204
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Multicore Fixed and Floating-Point Digital Signal Processor
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www.ti.com
Figure 7-36 shows a block diagram of the I2C module.
Figure 7-36
I2C Module Block Diagram
I2C Module
Clock
Prescale
Peripheral Clock
(CPU/6)
I2CPSC
Control
Bit Clock
Own
I2COAR
I2CSAR
I2CMDR
I2CCNT
I2CEMDR
Generator
Address
SCL
Noise
Filter
I2C Clock
I2CCLKH
I2CCLKL
Slave
Address
Mode
Data
Count
Transmit
I2CXSR
Transmit
Shift
Extended
Mode
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIMR
Noise
Filter
I2C Data
Interrupt
Mask/Status
Receive
I2CDRR
Receive
Buffer
Interrupt
Status
I2CSTR
Interrupt
Vector
I2CRSR
I2CIVR
Receive
Shift
Shading denotes control/status registers.
7.12.2 I2C Peripheral Register Description(s)
Table 7-66
I2C Registers (Part 1 of 2)
Hex Address Range
0253 0000
0253 0004
0253 0008
0253 000C
0253 0010
0253 0014
0253 0018
0253 001C
0253 0020
0253 0024
0253 0028
0253 002C
0253 0030
Register
ICOAR
ICIMR
Register Name
I2C Own Address Register
I2C Interrupt Mask/Status Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
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Table 7-66
I2C Registers (Part 2 of 2)
Hex Address Range
0253 0034
Register
ICPID1
ICPID2
-
Register Name
I2C Peripheral Identification Register 1 [Value: 0x0000 0105]
I2C Peripheral Identification Register 2 [Value: 0x0000 0005]
Reserved
0253 0038
0253 003C - 0253 007F
End of Table 7-66
7.12.3 I2C Electrical Data/Timing
7.12.3.1 Inter-Integrated Circuits (I2C) Timing
Table 7-67
(see Figure 7-37)
I2C Timing Requirements (1)
Standard Mode
Fast Mode
No.
Min
Max
Min
Max Units
1
2
tc(SCL)
tsu(SCLH-SDAL)
th(SDAL-SCLL)
Cycle time, SCL
10
2.5
μs
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
4
0.6
0.6
μs
μs
3
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
4
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100 (2)
0 (3)
μs
μs
ns
5
tw(SCLH)
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
tr(SDA)
Pulse duration, SCL high
6
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (For I2C bus devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
250
0 (3)
4.7
7
3.45
0.9 (4)
μs
μs
ns
ns
ns
ns
μs
ns
pF
8
1.3
(5)
9
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
(5)
(5)
(5)
10
11
12
13
14
15
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
50
(5)
Cb
400
400
End of Table 7-67
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down
2 A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH) 250 ns must then be met. This will automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
3 A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge
of SCL.
4 The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
5 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-37
I2C Receive Timings
11
9
SDA
SCL
8
6
14
4
10
13
5
1
3
12
7
2
3
Stop
Start
Repeated
Start
Stop
Table 7-68
(see Figure 7-38)
I2C Switching Characteristics (1)
Standard Mode
Fast Mode
Min
No.
Parameter
Min
Max
Max Unit
16
17
tc(SCL)
Cycle time, SCL
10
2.5
ms
Setup time, SCL high to SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
ms
18
Hold time, SDA low after SCL low (for a START and a repeated
START condition)
th(SDAL-SCLL)
ms
19
20
21
22
23
24
25
26
27
28
29
tw(SCLL)
tw(SCLH)
td(SDAV-SDLH)
tv(SDLL-SDAV)
tw(SDAH)
tr(SDA)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
ms
ms
Pulse duration, SCL high
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I2C bus devices)
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
250
0
ns
0.9 ms
ms
4.7
1.3
(1)
1000
1000
300
20 + 0.1Cb
300 ns
300 ns
300 ns
300 ns
ms
(1)
(1)
(1)
tr(SCL)
Rise time, SCL
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
10
10 pF
End of Table 7-68
1 Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Copyright 2013 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-38
I2C Transmit Timings
26
24
SDA
23
21
19
28
20
25
SCL
16
18
17
27
22
18
Stop
Start
Repeated
Start
Stop
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.13 SPI Peripheral
The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPI-compliant
devices. The primary intent of this interface is to allow for connection to a SPI ROM for boot. The SPI module on
C6678 is supported only in Master mode. Additional chip-level components can also be included, such as
temperature sensors or an I/O expander.
The C6678 SPI supports two modes, 3-pin and 4-pin. For the 4-pin chip-select mode, the C6678 supports up to two
chip selects.
7.13.1 SPI Electrical Data/Timing
7.13.1.1 SPI Timing
Table 7-69
See Figure 7-39)
SPI Timing Requirements
No.
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
7
7
7
7
8
8
8
8
tsu(SDI-SPC)
tsu(SDI-SPC)
tsu(SDI-SPC)
tsu(SDI-SPC)
th(SPC-SDI)
th(SPC-SDI)
th(SPC-SDI)
th(SPC-SDI)
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0
Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0
Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1
2
2
2
2
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
End of Table 7-69
Table 7-70
SPI Switching Characteristics (Part 1 of 2)
(See Figure 7-39 and Figure 7-40)
No.
Parameter
Min
Max
Unit
Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
2
3
4
tc(SPC)
Cycle Time, SPICLK, All Master Modes
3*P2 (1)
ns
tw(SPCH)
tw(SPCL)
td(SDO-SPC)
Pulse Width High, SPICLK, All Master Modes
Pulse Width Low, SPICLK, All Master Modes
0.5*tc - 1
0.5*tc - 1
ns
ns
ns
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 0.
5
5
5
5
2
2
2
2
4
4
4
5
5
5
5
td(SDO-SPC)
td(SDO-SPC)
td(SDO-SPC)
td(SPC-SDO)
td(SPC-SDO)
td(SPC-SDO)
td(SPC-SDO)
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 1.
ns
ns
ns
ns
ns
ns
ns
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 0
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK
Polarity = 1, Phase = 1
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 0 Phase = 0
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 0 Phase = 1
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 1 Phase = 0
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK
Polarity = 1 Phase = 1
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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Table 7-70
SPI Switching Characteristics (Part 2 of 2)
(See Figure 7-39 and Figure 7-40)
No.
Parameter
Min
Max
Unit
6
6
6
6
toh(SPC-SDO)
toh(SPC-SDO)
toh(SPC-SDO)
toh(SPC-SDO)
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 0 Phase = 0
ns
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 0 Phase = 1
ns
ns
ns
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 1 Phase = 0
Output hold time, SPIDOUT valid after receive edge of SPICLK except for final 0.5*tc - 2
bit. Polarity = 1 Phase = 1
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
19 td(SCS-SPC)
19 td(SCS-SPC)
19 td(SCS-SPC)
19 td(SCS-SPC)
20 td(SPC-SCS)
Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 0
Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 1
Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 0
Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 1
2*P2 - 5
2*P2 + 5
ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
2*P2 - 5 2*P2 + 5 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
1*P2 - 5 1*P2 + 5 ns
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0
Phase = 0
20 td(SPC-SCS)
20 td(SPC-SCS)
20 td(SPC-SCS)
tw(SCSH)
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
1*P2 - 5 1*P2 + 5 ns
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
2*P2 - 5 ns
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1
Phase = 0
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1
Phase = 1
Minimum inactive time on SPISCS[n] pin between two transfers when
SPISCS[n] is not held using the CSHOLD feature.
End of Table 7-70
1 P2 = 1/SYSCLK7
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-39
SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode
1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPICLK
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
SPIDOUT
SPIDIN
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPICLK
SPIDOUT
SPIDIN
6
5
5
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPICLK
SPIDOUT
SPIDIN
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPICLK
SPIDOUT
SPIDIN
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 7-40
SPI Additional Timings for 4 Pin Master Mode with Chip Select Option
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPICLK
SPIDOUT
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
SPIDIN
SPISCSx
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7.14 HyperLink Peripheral
The TMS320C6678 includes the HyperLink bus for companion chip/die interfaces. This is a four-lane SerDes
interface designed to operate at up to 12.5 Gbaud per lane. The supported data rates include 1.25 Gbaud,
3.125 Gbaud, 6.25 Gbaud, 10 Gbaud and 12.5 Gbaud. The interface is used to connect with external accelerators.
The HyperLink links must be connected with DC coupling.
The interface includes the Serial Station Management Interfaces used to send power management and flow messages
between devices. This consists of four LVCMOS inputs and four LVCMOS outputs configured as two 2-wire output
buses and two 2-wire input buses. Each 2-wire bus includes a data signal and a clock signal.
7.14.1 HyperLink Device-Specific Interrupt Event
The HyperLink has 64 input events. Events 0 to 31come from the chip level interrupt controller and events 32 to 63
are from queue-pending signals from the Queue Manager to monitor some of the transmission queue status.
Table 7-71
HyperLink Events for C6678 (Part 1 of 2)
Event Number
Event
Event Description
0
CIC3_OUT8
CIC3_OUT9
CIC3_OUT10
CIC3_OUT11
CIC3_OUT12
CIC3_OUT13
CIC3_OUT14
CIC3_OUT15
CIC3_OUT16
CIC3_OUT17
CIC3_OUT18
CIC3_OUT19
CIC3_OUT20
CIC3_OUT21
CIC3_OUT22
CIC3_OUT23
CIC3_OUT24
CIC3_OUT25
CIC3_OUT26
CIC3_OUT27
CIC3_OUT28
CIC3_OUT29
CIC3_OUT30
CIC3_OUT31
CIC3_OUT32
CIC3_OUT33
CIC3_OUT34
CIC3_OUT35
CIC3_OUT36
CIC3_OUT37
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
Interrupt Controller output
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
212
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SPRS691D—April 2013
www.ti.com
Table 7-71
HyperLink Events for C6678 (Part 2 of 2)
Event Number
Event
Event Description
30
CIC3_OUT38
Interrupt Controller output
Interrupt Controller output
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
Queue manager pend event
31
CIC3_OUT39
32
QM_INT_PEND_864
QM_INT_PEND_865
QM_INT_PEND_866
QM_INT_PEND_867
QM_INT_PEND_868
QM_INT_PEND_869
QM_INT_PEND_870
QM_INT_PEND_871
QM_INT_PEND_872
QM_INT_PEND_873
QM_INT_PEND_874
QM_INT_PEND_875
QM_INT_PEND_876
QM_INT_PEND_877
QM_INT_PEND_878
QM_INT_PEND_879
QM_INT_PEND_880
QM_INT_PEND_881
QM_INT_PEND_882
QM_INT_PEND_883
QM_INT_PEND_884
QM_INT_PEND_885
QM_INT_PEND_886
QM_INT_PEND_887
QM_INT_PEND_888
QM_INT_PEND_889
QM_INT_PEND_890
QM_INT_PEND_891
QM_INT_PEND_892
QM_INT_PEND_893
QM_INT_PEND_894
QM_INT_PEND_895
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
End of Table 7-71
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Peripheral Information and Electrical Specifications 213
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SPRS691D—April 2013
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7.14.2 HyperLink Electrical Data/Timing
The tables and figure below describe the timing requirements and switching characteristics of HyperLink peripheral.
Table 7-72
HyperLink Peripheral Timing Requirements
See Figure 7-41,Figure 7-42,Figure 7-43
No.
Min
Max
Unit
FL Interface
Clock period - MCMTXFLCLK (C1)
1
2
3
6
7
6
7
tc(MCMTXFLCLK)
6.4
ns
tw(MCMTXFLCLKH)
High pulse width - MCMTXFLCLK
0.4*C1 0.6*C1 ns
0.4*C1 0.6*C1 ns
tw(MCMTXFLCLKL)
Low pulse width - MCMTXFLCLK
tsu(MCMTXFLDAT-MCMTXFLCLKH)
th(MCMTXFLCLKH-MCMTXFLDAT)
tsu(MCMTXFLDAT-MCMTXFLCLKL)
th(MCMTXFLCLKL-MCMTXFLDAT)
Setup time - MCMTXFLDAT valid before MCMTXFLCLK high
Hold time - MCMTXFLDAT valid after MCMTXFLCLK high
Setup time - MCMTXFLDAT valid before MCMTXFLCLK low
Hold time - MCMTXFLDAT valid after MCMTXFLCLK low
PM Interface
1
1
1
1
ns
ns
ns
ns
1
2
3
6
7
6
7
tc(MCMRXPMCLK)
tw(MCMRXPMCLK)
tw(MCMRXPMCLK)
Clock period - MCMRXPMCLK (C3)
6.4
ns
High pulse width - MCMRXPMCLK
0.4*C3 0.6*C3 ns
0.4*C3 0.6*C3 ns
Low pulse width - MCMRXPMCLK
tsu(MCMRXPMDAT-MCMRXPMCLKH) Setup time - MCMRXPMDAT valid before MCMRXPMCLK high
th(MCMRXPMCLKH-MCMRXPMDAT) Hold time - MCMRXPMDAT valid after MCMRXPMCLK high
tsu(MCMRXPMDAT-MCMRXPMCLKL) Setup time - MCMRXPMDAT valid before MCMRXPMCLK low
th(MCMRXPMCLKL-MCMRXPMDAT) Hold time - MCMRXPMDAT valid after MCMRXPMCLK low
1
1
1
1
ns
ns
ns
ns
End of Table 7-72
Table 7-73
HyperLink Peripheral Switching Characteristics
See Figure 7-41,Figure 7-42,Figure 7-43
No.
Parameter
FL Interface
Min
Max
Unit
1
2
3
4
5
4
5
tc(MCMRXFLCLK)
Clock period - MCMRXFLCLK (C2)
6.4
ns
tw(MCMRXFLCLKH)
High pulse width - MCMRXFLCLK
0.4*C2 0.6*C2 ns
0.4*C2 0.6*C2 ns
tw(MCMRXFLCLKL)
Low pulse width - MCMRXFLCLK
tosu(MCMRXFLDAT-MCMRXFLCLKH)
toh(MCMRXFLCLKH-MCMRXFLDAT)
tosu(MCMRXFLDAT-MCMRXFLCLKL)
toh(MCMRXFLCLKL-MCMRXFLDAT)
Setup time - MCMRXFLDAT valid before MCMRXFLCLK high
Hold time - MCMRXFLDAT valid after MCMRXFLCLK high
Setup time - MCMRXFLDAT valid before MCMRXFLCLK low
Hold time - MCMRXFLDAT valid after MCMRXFLCLK low
PM Interface
0.25*C2-0.4
ns
ns
ns
ns
0.25*C2-0.4
0.25*C2-0.4
0.25*C2-0.4
1
2
3
4
5
4
5
tc(MCMTXPMCLK)
tw(MCMTXPMCLK)
tw(MCMTXPMCLK)
Clock period - MCMTXPMCLK (C4)
6.4
ns
High pulse width - MCMTXPMCLK
0.4*C4 0.6*C4 ns
0.4*C4 0.6*C4 ns
Low pulse width - MCMTXPMCLK
tosu(MCMTXPMDAT-MCMTXPMCLKH) Setup time - MCMTXPMDAT valid before MCMTXPMCLK high
toh(MCMTXPMCLKH-MCMTXPMDAT) Hold time - MCMTXPMDAT valid after MCMTXPMCLK high
tosu(MCMTXPMDAT-MCMTXPMCLKL) Setup time - MCMTXPMDAT valid before MCMTXPMCLK low
toh(MCMTXPMCLKL-MCMTXPMDAT) Hold time - MCMTXPMDAT valid after MCMTXPMCLK low
0.25*C4-0.4
ns
ns
ns
ns
0.25*C4-0.4
0.25*C4-0.4
0.25*C4-0.4
End of Table 7-73
214
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-41
HyperLink Station Management Clock Timing
1
2
3
Figure 7-42
HyperLink Station Management Transmit Timing
4
5
4
5
MCMTX<xx>CLK
MCMTX<xx>DAT
<xx> represents the interface that is being used: PM or FL
Figure 7-43
HyperLink Station Management Receive Timing
6
7
6
7
MCMRX<xx>CLK
MCMRX<xx>DAT
<xx> represents the interface that is being used: PM or FL
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7.15 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and
UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550
asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally
similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate
FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per
byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial
conversion on data received from the DSP. The DSP can read the UART status at any time. The UART includes
control capability and a processor interrupt system that can be tailored to minimize software management of the
communications link. For more information on UART, see the Universal Asynchronous Receiver/Transmitter
(UART) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Table 7-74
UART Timing Requirements
(see Figure 7-44 and Figure 7-45)
No.
Min
Max
Unit
Receive Timing
4
5
5
6
6
6
tw(RXSTART)
tw(RXH)
Pulse width, receive start bit
0.96U (1)
0.96U
1.05U
ns
ns
ns
ns
ns
ns
Pulse width, receive data/parity bit high
Pulse width, receive data/parity bit low
Pulse width, receive stop bit 1
1.05U
1.05U
1.05U
tw(RXL)
0.96U
tw(RXSTOP1)
tw(RXSTOP15)
tw(RXSTOP2)
0.96U
Pulse width, receive stop bit 1.5
Pulse width, receive stop bit 2
1.5*(0.96U) 1.5*(1.05U)
2*(0.96U)
2*(1.05U)
Autoflow Timing Requirements
Delay time, CTS asserted to START bit transmit
8
td(CTSL-TX)
P (2)
5P
ns
End of Table 7-74
1 U = UART baud time = 1/programmed baud rate
2 P = 1/SYSCLK7
Figure 7-44
UART Receive Timing Waveform
5
5
6
4
RXD
Start
Bit 0
Bit 1
Bit N-1
Bit N
Parity
Stop
Idle
Start
Stop/Idle
Figure 7-45
UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
8
TXD
CTS
Bit N-1
Bit N
Stop
Start
Bit 0
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Table 7-75
UART Switching Characteristics
(See Figure 7-46 and Figure 7-47)
No.
Parameter
Min
U (1) - 2
Max
Unit
Transmit Timing
1
2
2
3
3
3
tw(TXSTART)
tw(TXH)
Pulse width, transmit start bit
U + 2
ns
ns
ns
ns
ns
ns
Pulse width, transmit data/parity bit high
Pulse width, transmit data/parity bit low
Pulse width, transmit stop bit 1
U - 2
U - 2
U - 2
U + 2
U + 2
U + 2
tw(TXL)
tw(TXSTOP1)
tw(TXSTOP15)
tw(TXSTOP2)
Pulse width, transmit stop bit 1.5
Pulse width, transmit stop bit 2
1.5 * (U - 2) 1.5 * ('U + 2)
2 * (U - 2)
2 * ('U + 2)
Autoflow Timing Requirements
Delay time, STOP bit received to RTS deasserted
7
td(RX-RTSH)
P (2)
5P
ns
End of Table 7-75
1 U = UART baud time = 1/programmed baud rate
2 P = 1/SYSCLK7
Figure 7-46
UART Transmit Timing Waveform
2
2
3
1
TXD
Start
Bit 0
Bit 1
Bit N-1
Bit N
Parity
Stop
Idle
Start
Stop/Idle
Figure 7-47
UART RTS (Request-to-Send Output) — Autoflow Timing Waveform
7
RXD
CTS
Bit N-1
Bit N
Stop
Start
7.16 PCIe Peripheral
The two-lane PCI express (PCIe) module on the device provides an interface between the DSP and other
PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed data
transfer at rates of 5.0 GBaud per lane on the serial links. For more information, see the Peripheral Component
Interconnect Express (PCIe) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 73. The PCIe electrical requirements are fully specified in the PCI Express Base Specification Revision 2.0
of PCI-SIG. TI has performed the simulation and system characterization to ensure all PCIe interface timings in this
solution are met; therefore, no electrical data/timing information is supplied here for this interface.
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7.17 TSIP Peripheral
The telecom serial interface port (TSIP) module provides a glueless interface to common telecom serial data streams.
For more information, see the Telecom Serial Interface Port (TSIP) for the C66x DSP User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
7.17.1 TSIP Electrical Data/Timing
Table 7-76
(see Figure 7-48)
Timing Requirements for TSIP 2x Mode (1)
No.
Min
61 (2)
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
tc(CLK)
Cycle time, CLK rising edge to next CLK rising edge
2
tw(CLKL)
Pulse duration, CLK low
0.4×tc(CLK)
0.4×tc(CLK)
3
tw(CLKH)
Pulse duration, CLK high
4
tt(CLK)
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
Disable time, CLK low to TX Hi-Z
2
5
tsu(FS-CLK)
th(CLK-FS)
tsu(TR-CLK)
th(CLK-TR)
td(CLKL-TX)
tdis(CLKH-TXZ)
5
5
5
5
1
2
6
7
8
9
12
10
10
End of Table 7-76
1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 1b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 0. If the polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 30.5 ns and 15.2 ns, respectively.
Figure 7-48
TSIP 2x Timing Diagram(1)
1
2
3
CLKA/B
6
5
FSA/B
8
7
TR[n]
TX[n]
ts127-3
ts127-2
ts127-2
ts127-1
ts127-1
ts127-0
ts000-7
ts000-7
ts000-6
ts000-5
ts000-5
ts000-4
ts000-4
ts000-3
ts000-3
ts000-2
ts000-2
ts000-1
ts000-1
ts000-0
ts000-0
9
ts127-3
ts127-0
ts000-6
1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0
through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1 and a XMTDATD=1
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Table 7-77
(see Figure 7-49)
Timing Requirements for TSIP 1x Mode (1)
No.
Min
122.1 (2)
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
13
14
15
16
17
18
19
20
tc(CLK)
Cycle time, CLK rising edge to next CLK rising edge
tw(CLKL)
Pulse duration, CLK low
0.4×tc(CLK)
0.4×tc(CLK)
tw(CLKH)
Pulse duration, CLK high
tt(CLK)
Transition time, CLK high to low or CLK low to high
Setup time, FS valid before rising CLK
Hold time, FS valid after rising CLK
Setup time, TR valid before rising CLK
Hold time, TR valid after rising CLK
Delay time, CLK low to TX valid
Disable time, CLK low to TX Hi-Z
2
tsu(FS-CLK)
th(CLK-FS)
tsu(TR-CLK)
th(CLK-TR)
td(CLKL-TX)
tdis(CLKH-TXZ)
5
5
5
5
1
2
12
10
End of Table 7-77
1 Polarities of XMTFSYNCP = 0b, XMTFCLKP = 0, XMTDCLKP = 0b, RCVFSYNCP = 0, RCVFCLKP = 0, RCVDCLKP = 1. If the polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
2 Timing shown is for 8.192 Mbps links. Timing for 16.384 Mbps and 32.768 Mbps links is 61 ns and 30.5 ns, respectively.
Figure 7-49
CLKA/B
TSIP 1x Timing Diagram(1)
11
12 13
16
15
FSA/B
17
18
TR[n]
TX[n]
ts127-3
ts127-2
ts127-2
ts127-1
ts127-1
ts127-0
ts127-0
ts000-7
ts000-6
ts000-5
ts000-5
ts000-4
ts000-4
ts000-3
ts000-3
ts000-2
ts000-2
ts000-1
ts000-1
ts000-0
ts000-0
19
ts127-3
ts000-7
ts000-6
1 Example timeslot numbering shown is for 8.192 Mbps links; 16.384 Mbps links have timeslots numbered 0 through 255 and 32.768 Mbps links have timeslots numbered 0
through 511. The data timing shown relative to the clock and frame sync signals would require a RCVDATD=1023 and a XMTDATD=1023.
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7.18 EMIF16 Peripheral
The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For
more information, see the External Memory Interface (EMIF16) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
7.18.1 EMIF16 Electrical Data/Timing
Table 7-78
EMIF16 Asynchronous Memory Timing Requirements (1) (2)
(see Figure 7-50 and Figure 7-51)
No.
Min
Max
Unit
General Timing
2
tw(WAIT)
Pulse duration, WAIT assertion and deassertion minimum time
Setup time, WAIT asserted before WE high
Setup time, WAIT asserted before OE high
2E ns
28
14
td(WAIT-WEH)
td(WAIT-OEH)
4E + 3
4E + 3
ns
ns
Read Timing
3
3
EMIF read cycle time when ew = 0, meaning not in extended wait mode
(RS+RST+RH+3)* (RS+RST+RH+3)* ns
E-3 E+3
tC(CEL)
tC(CEL)
EMIF read cycle time when ew =1, meaning extended wait mode enabled
(RS+RST+WAIT+ (RS+RST+WAIT+
ns
RH+3)* E-3
(RS+1) * E - 3
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E - 3
(RS+1) * E - 3
(RH+1) * E - 3
(RST+1) * E - 3
(RST+1) * E - 3
RH+3)* E+3
(RS+1) * E + 3
(RH+1) * E + 3
(RS+1) * E + 3
(RH+1) * E + 3
(RS+1) * E + 3
(RH+1) * E + 3
(RS+1) * E + 3
(RH+1) * E + 3
(RST+1) * E + 3
(RST+1) * E + 3
4E + 3
4
t
osu(CEL-OEL)
Output setup time from CE low to OE low. SS = 0, not in select strobe mode
Output hold time from OE high to CE high. SS = 0, not in select strobe mode
Output setup time from CE low to OE low in select strobe mode, SS = 1
Output hold time from OE high to CE high in select strobe mode, SS = 1
Output setup time from BA valid to OE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
toh(OEH-CEH)
tosu(CEL-OEL)
toh(OEH-CEH)
tosu(BAV-OEL)
toh(OEH-BAIV)
tosu(AV-OEL)
toh(OEH-AIV)
tw(OEL)
4
5
6
7
Output hold time from OE high to BA invalid
8
Output setup time from A valid to OE low
9
Output hold time from OE high to A invalid
10
10
11
12
13
OE active time low, when ew = 0. Extended wait mode is disabled.
OE active time low, when ew = 1. Extended wait mode is enabled.
Delay time from WAIT deasserted to OE# high
tw(OEL)
td(WAITH-OEH)
tsu(D-OEH)
Input setup time from D valid to OE high
3
th(OEH-D)
Input hold time from OE high to D invalid
0.5
Write Timing
15
15
EMIF write cycle time when ew = 0, meaning not in extended wait mode
(WS+WST+WH+ (WS+WST+WH+
3)* E-3 3)* E+3
ns
ns
tc(CEL)
tc(CEL)
EMIF write cycle time when ew =1., meaning extended wait mode is enabled (WS+WST+WAIT (WS+WST+WAIT
+WH+3)* E-3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WST+1) * E - 3
+WH+3)* E+3
16
17
16
17
18
19
20
21
22
23
24
t
osu(CEL-WEL)
Output setup time from CE low to WE low. SS = 0, not in select strobe mode
Output hold time from WE high to CE high. SS = 0, not in select strobe mode
Output setup time from CE low to WE low in select strobe mode, SS = 1
Output hold time from WE high to CE high in select strobe mode, SS = 1
Output setup time from RNW valid to WE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
toh(WEH-CEH)
tosu(CEL-WEL)
toh(WEH-CEH)
tosu(RNW-WEL)
toh(WEH-RNW)
tosu(BAV-WEL)
toh(WEH-BAIV)
tosu(AV-WEL)
toh(WEH-AIV)
tw(WEL)
Output hold time from WE high to RNW invalid
Output setup time from BA valid to WE low
Output hold time from WE high to BA invalid
Output setup time from A valid to WE low
Output hold time from WE high to A invalid
WE active time low, when ew = 0. Extended wait mode is disabled.
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Table 7-78
EMIF16 Asynchronous Memory Timing Requirements (1) (2)
(see Figure 7-50 and Figure 7-51)
No.
Min
Max
Unit
ns
24
26
27
25
tw(WEL)
WE active time low, when ew = 1. Extended wait mode is enabled.
Output setup time from D valid to WE low
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
tosu(DV-WEL)
toh(WEH-DIV)
ns
Output hold time from WE high to D invalid
ns
td(WAITH-WEH) Delay time from WAIT deasserted to WE# high
4E + 3
ns
End of Table 7-78
1 E = 1/SYSCLK7, RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold.
2 WAIT = number of cycles wait is asserted between the programmed end of the strobe period and wait de-assertion.
Figure 7-50
EMIF16 Asynchronous Memory Read Timing Diagram
3
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
4
9
7
6
8
5
10
EM_OE
12
13
EM_D[15:0]
EM_WE
Figure 7-51
EMIF16 Asynchronous Memory Write Timing Diagram
15
EM_CE[3:0]
EM_R/W
EM_BA[1:0]
EM_A[21:0]
16
18
20
22
19
21
23
17
24
EM_WE
26
27
EM_D[15:0]
EM_OE
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Figure 7-52
EMIF16 EM_WAIT Read Timing Diagram
Setup Strobe
Extended Due to EM_WAIT
Strobe
Hold
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_OE
14
11
2
2
EM_WAIT
Deasserted
Asserted
Figure 7-53
EMIF16 EM_WAIT Write Timing Diagram
Setup Strobe
Extended Due to EM_WAIT
Strobe
Hold
EM_CE[3:0]
EM_BA[1:0]
EM_A[21:0]
EM_D[15:0]
EM_WE
28
25
2
2
Deasserted
EM_WAIT
Asserted
7.19 Packet Accelerator
The packet accelerator provides L2 to L4 classification functionalities. It supports classification for Ethernet, VLAN,
MPLS over Ethernet, IPv4/6, GRE over IP, and other session identification over IP such as TCP and UDP ports. It
maintains 8K multiple-in, multiple-out hardware queues. It also provides checksum capability as well as some QoS
capabilities. It enables a single IP address to be used for a multi-core device. It can process up to 1.5 M pps. The
packet accelerator is coupled with the network coprocessor. For more information, see the Packet Accelerator (PA)
for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
7.20 Security Accelerator
The security accelerator provides wire-speed processing on 1-Gbps Ethernet traffic on IPSec, SRTP, and 3GPP Air
interface security protocols. It functions on the packet level with the packet and the associated security context being
one of these above three types. The security accelerator is coupled with network coprocessor, and receives the packet
descriptor containing the security context in the buffer descriptor, and the data to be encrypted/decrypted in the
linked buffer descriptor. For more information, see the Security Accelerator (SA) for KeyStone Devices User Guide in
‘‘Related Documentation from Texas Instruments’’ on page 73.
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7.21 Gigabit Ethernet (GbE) Switch Subsystem
The Gigabit Ethernet (GbE) switch subsystem provide an efficient interface between the TMS320C6678 DSP and the
networked community. The GbE switch subsystem supports 10Base-T (10 Mbits/second [Mbps]), and 100BaseTX
(100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in full-duplex mode, with hardware flow
control and quality-of-service (QOS) support. The GbE switch subsystem is coupled with network coprocessor. For
more information, see the Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
Each device has a unique MAC address. There are two registers to hold these values, MACID1 (0x02620110) and
MACID2 (0x02620114). All bits of these registers are defined as follows:
Figure 7-54
MACID1 Register
31
0
MACID[31:0]
R,+xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 7-79
MACID1 Register Field Descriptions
Bit
Field
MAC ID[31-0]
Description
MAC ID. A range will be assigned to this device. Each device will consume only one MAC address.
31-0
End of Table 7-79
Figure 7-55
MACID2 Register
31
24
23
18
17
FLOW BCAST
R,+z R,+y
16
15
0
Reserved
Reserved
R,+0
MACID[47:32]
R+, xxxx xxxx
R,+xxxx xxxx xxxx xxxx
Legend: R = Read only; -x, value is indeterminate
Table 7-80
MACID2 Register Field Descriptions
Description
Bit
Field
Reserved
31-24
23-18
17
Reserved. Values will vary.
Reserved. Read as 0.
Reserved
FLOW
MAC flow control
0 = Off
1 = On
16
BCAST
Default m/b-cast reception
0 = Broadcast
1 = Disabled
15-0
MAC ID[47-0]
MAC ID
End of Table 7-80
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There is one Time Synchronization (CPTS) submodule in the Ethernet switch module for Time Synchronization.
Programming this register selects the clock source for the CPTS_RCLK. Please see the Gigabit Ethernet (GbE) Switch
Subsystem for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73 for the
register address and other details about the Time Synchronization module. The register CPTS_RFTCLK_SEL for
reference clock selection of Time Synchronization submodule is shown in Figure 7-56.
Figure 7-56
CPTS_RFTCLK_SEL Register
31
3
2
0
Reserved
R - 0
CPTS_RFTCLK_SEL
RW - 0
Legend: R = Read only; -x, value is indeterminate
Table 7-81
CPTS_RFTCLK_SEL Register Field Descriptions
Description
Bit
Field
Reserved
31-3
2-0
Reserved. Read as 0.
CPTS_RFTCLK_SEL Reference Clock Select. This signal is used to control an external multiplexer that selects one of 8 clocks for time sync
reference (RFTCLK). This CPTS_RFTCLK_SEL value can be written only when the CPTS_EN bit is cleared to 0 in the
TS_CTL register.
000 = SYSCLK2
001 = SYSCLK3
010 = TIMI0
011 = TIMI1
100 = TSIP0 CLK_A
101 = TSIP0 CLK_B
110 = TSIP1 CLK_A
111 = TSIP1 CLK_B
End of Table 7-81
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7.22 Management Data Input/Output (MDIO)
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus. Application
software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the GbE
switch subsystem, retrieve the negotiation results, and configure required parameters in the GbE switch subsystem
module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface,
with very little maintenance from the core processor. For more information, see the Gigabit Ethernet (GbE) Switch
Subsystem for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
Table 7-82
See Figure 7-57
MDIO Timing Requirements
No.
Min
Max
Unit
1
2
3
4
5
tc(MDCLK)
tw(MDCLKH)
tw(MDCLKL)
Cycle time, MDCLK
400
180
180
10
ns
ns
ns
ns
ns
ns
Pulse duration, MDCLK high
Pulse duration, MDCLK low
tsu(MDIO-MDCLKH) Setup time, MDIO data input valid before MDCLK high
th(MDCLKH-MDIO)
tt(MDCLK)
Hold time, MDIO data input valid after MDCLK high
Transition time, MDCLK
0
5
End of Table 7-82
Figure 7-57
MDIO Input Timing
MDCLK
2
3
4
5
MDIO
(Input)
Table 7-83
MDIO Switching Characteristics
Parameter
See Figure 7-58
No.
Min
Max
Unit
6
td(MDCLKL-MDIO)
Delay time, MDCLK low to MDIO data output valid
100
ns
End of Table 7-83
Figure 7-58
MDIO Output Timing
1
MDCLK
6
MDIO
(Ouput)
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7.23 Timers
The timers can be used to: time events, count events, generate pulses, interrupt the CPU and send synchronization
events to the EDMA3 channel controller.
7.23.1 Timers Device-Specific Information
The TMS320C6678 device has sixteen 64-bit timers in total. Timer0 through Timer7 are dedicated to each of the
eight CorePacs as a watchdog timer and can also be used as general-purpose timers. Each of the other eight timers
can also be configured as a general-purpose timer only, with each timer programmed as a 64-bit timer or as two
separate 32-bit timers.
When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge)
and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a software-programmable
period.
When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two
32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low
counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.
When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement
that software writes to the timer before the count expires, after which the count begins again. If the count ever
reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming ‘‘Reset
Type Status Register (RSTYPE)’’ on page 146 and the type of reset initiated can set by programming ‘‘Reset
Configuration Register (RSTCFG)’’ on page 147. For more information, see the 64-bit Timer (Timer 64) for KeyStone
Devices User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
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7.23.2 Timers Electrical Data/Timing
The tables and figure below describe the timing requirements and switching characteristics of Timer0 through
Timer15 peripherals.
Table 7-84
(see Figure 7-59)
Timer Input Timing Requirements (1)
No.
Min
12C
12C
Max
Unit
ns
1
2
tw(TINPH)
tw(TINPL)
Pulse duration, high
Pulse duration, low
ns
End of Table 7-84
1
C = 1/SYSCLK1 frequency in ns.
Table 7-85
(see Figure 7-59)
Timer Output Switching Characteristics (1)
No.
Parameter
Pulse duration, high
Min
12C - 3
12C - 3
Max
Unit
ns
3
4
tw(TOUTH)
tw(TOUTL)
Pulse duration, low
ns
End of Table 7-85
1
C = 1/SYSCLK1 frequency in ns.
Figure 7-59
TIMIx
Timer Timing
1
2
4
3
TIMOx
7.24 Serial RapidIO (SRIO) Port
The SRIO port on the TMS320C6678 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the RapidIO interconnect in a baseband board design can create a homogeneous
interconnect environment, providing even more connectivity and control among the components. RapidIO is based
on the memory and device addressing concepts of processor buses where the transaction processing is managed
completely by hardware. This enables the RapidIO interconnect to lower the system cost by providing lower latency,
reduced overhead of packet data processing, and higher system bandwidth, all of which are key for wireless
interfaces. For more information, see the Serial RapidIO (SRIO) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 73.
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 227
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.25 General-Purpose Input/Output (GPIO)
7.25.1 GPIO Device-Specific Information
On the TMS320C6678, the GPIO peripheral pins GP[15:0] are also used to latch configuration pins. For more
detailed information on device/peripheral configuration and the C6678 device pin muxing, see ‘‘Device
Configuration’’ on page 74. For more information on GPIO, see the General Purpose Input/Output (GPIO) for
KeyStone Devices User Guide ‘‘Related Documentation from Texas Instruments’’ on page 73.
7.25.2 GPIO Electrical Data/Timing
Table 7-86
No.
GPIO Input Timing Requirements
Min
12C (1)
12C
Max Unit
1
2
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
ns
ns
End of Table 7-86
1
C = 1/SYSCLK1 frequency in ns.
Table 7-87
No.
GPIO Output Switching Characteristics
Parameter
Pulse duration, GPOx high
Pulse duration, GPOx low
Min
36C (1) - 8
36C - 8
Max Unit
3
4
tw(GPOH)
tw(GPOL)
ns
ns
End of Table 7-87
1
C = 1/SYSCLK1 frequency in ns.
Figure 7-60
GPIx
GPIO Timing
1
2
4
3
GPOx
228
Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.26 Semaphore2
The device contains an enhanced Semaphore module for the management of shared resources of the DSP C66x
CorePacs. The Semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write
sequence is not broken. The semaphore block has unique interrupts to each of the cores to identify when that core
has acquired the resource.
Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to
allocate semaphore resources to the hardware resource(s) to be arbitrated.
The Semaphore module supports 8 masters and contains 32 semaphores to be used within the system.
The Semaphore module is accessible only by masters with privilege ID (privID) 0 to 7, which means only CorePac
0 to 7 or the EDMA transactions initiated by CorePac 0 to 7 can access the Semaphore module.
If the remote device wants to access the Semaphore module, the HyperLink configuration register needs to be
appropriately configured, so the remote device can send transactions with the desired privID value to the local
Semaphore module. For more information on HyperLink configuration, see the HyperLink for KeyStone Devices
User Guide in ‘‘Related Documentation from Texas Instruments’’ on page 73.
There are two methods of accessing a semaphore resource:
•
Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the
semaphore is not granted.
•
Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt
notifies the CPU that it is available.
7.27 Emulation Features and Capability
7.27.1 Advanced Event Triggering (AET)
The TMS320C6678 device supports Advanced Event Triggering (AET). This capability can be used to debug
complex problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
•
Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting
the processor or triggering the trace capture.
•
Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events
such as halting the processor or triggering the trace capture.
•
•
Counters: count the occurrence of an event or cycles for performance monitoring.
State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely
generate events for complex sequences.
For more information on AET, see the following documents in ‘‘Related Documentation from Texas Instruments’’
on page 73:
•
•
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs application report
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor
Systems application report
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 229
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
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7.27.2 Trace
The C6678 device supports Trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information
for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the 60-Pin Emulation Header
Technical Reference in ‘‘Related Documentation from Texas Instruments’’ on page 73.
7.27.2.1 Trace Electrical Data/Timing
(1)
Table 7-88
(see Figure 7-61)
DSP Trace Switching Characteristics
No.
Parameter
Pulse duration, EMUn high detected at 50% Voh
tw(EMUnH)90% Pulse duration, EMUn high detected at 90% Voh
Min Max Unit
1
1
2
2
3
tw(EMUnH)
2.4
1.5
2.4
1.5
-1
ns
ns
tw(EMUnL)
Pulse duration, EMUn low detected at 50% Voh
Pulse duration, EMUn low detected at 10% Voh
Output skew time, time delay difference between EMUn pins configured as trace
Output slew rate EMUn
ns
tw(EMUnL)10%
tsko(EMUn)
ns
1
ns
t
sldp_(EMUn)
3.3
V/ns
End of Table 7-88
1 Over recommended operating conditions.
(1)
Table 7-89
(see Figure 7-61)
STM Trace Switching Characteristics
No.
Parameter
Min Max Unit
1
1
2
2
3
tw(EMUnH)
Pulse duration, EMUn high detected at 50% Voh with 60/40 duty cycle
Pulse duration, EMUn high detected at 90% Voh
4
3.5
4
ns
ns
tw(EMUnH)90%
tw(EMUnL)
Pulse duration, EMUn low detected at 50% Voh with 60/40 duty cycle
Pulse duration, EMUn low detected at 10% Voh
ns
tw(EMUnL)10%
tsko(EMUn)
3.5
-1
ns
Output skew time, time delay difference between EMUn pins configured as trace
Output slew rate EMUn
1
ns
t
sldp_(EMUn)
3.3
V/ns
End of Table 7-89
1 Over recommended operating conditions.
Figure 7-61
Trace Timing
1
2
EMUx
3
EMUy
3
EMUz
EMUx represents the EMU output pin configured as the trace clock output.
EMUy and EMUz represent all of the trace output data pins.
230
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
7.27.3 IEEE 1149.1 JTAG
The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported
allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary
scan. Most interfaces on the device follow the Boundary Scan Test Specification (IEEE1149.1), while all of the SerDes
(SRIO and SGMII) support the AC-coupled net test defined in AC-Coupled Net Test Specification (IEEE1149.6).
It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in
accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power
Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).
7.27.3.1 IEEE 1149.1 JTAG Compatibility Statement
For maximum reliability, the C6678 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST
high before attempting any emulation or boundary scan operations.
7.27.3.2 JTAG Electrical Data/Timing
Table 7-90
(see Figure 7-62)
JTAG Test Port Timing Requirements
No.
Min
34
Max Unit
1
tc(TCK)
Cycle time, TCK
ns
ns
ns
ns
ns
ns
ns
1a
1b
3
tw(TCKH)
tw(TCKL)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low(40% of tc)
13.6
13.6
3.4
3.4
17
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
input setup time, TDI valid to TCK high
input setup time, TMS valid to TCK high
input hold time, TDI valid from TCK high
input hold time, TMS valid from TCK high
3
4
4
17
End of Table 7-90
Table 7-91
JTAG Test Port Switching Characteristics (1)
Parameter
(see Figure 7-62)
No.
Min
Max Unit
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
13.6
ns
End of Table 7-91
1 Over recommended operating conditions.
Copyright 2013 Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 231
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Figure 7-62
JTAG Test-Port Timing
1
1a
1b
TCK
2
TDO
4
3
TDI / TMS
232
Peripheral Information and Electrical Specifications
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
A Revision History
Revision D
Corrected NMI7-0 from bit fields 23-16 to bit fields 15-8 in LRSTNMIPINSTAT and LRSTNMIPINSTAT_CLR registers (Page 81)
Added Extended Boot Mode table in Boot Device Field section (Page 29)
Updated event "PO_VP_SMPSACK_INTR" to be Reserved in CIC3 event table (Page 181)
Updated Trace Electrical Timing tables and Timing diagrams (Page 230)
Updated event "PO_VCON_SMPSERR_INTR" be Reserved in CIC0/1 Event Inputs table (Page 170)
Added Boot Parameter Table section (Page 34)
Added new section "DDR3 Memory Controller Race Condition Consideration" to include the last 3 paragraphs originally in section 7.11.1
(Page 203)
Added REFCLK description in power sequencing section (Page 121)
Added table of Bootloader section in L2 SRAM in Boot Sequence section (Page 27)
Updated SYSCLK1 to REFCLK in power sequencing section to refer to the clock source of main PLL (Page 122)
Updated note in power sequencing that each supply must ramp monotonically and must reach a stable valid level within 20 ms.
(Page 122)
Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffers (Page 150)
Changed all footnote references from CORECLK to SYSCLK1 (Page 228)
Updated PCIe privilege level from "Supervisor" to "Driven by PCIe module" (Page 191)
Corrected "Reserved" to be "Assert local reset to all CorePacs" in LRESET and NMI Decoding table (Page 187)
Added MPU Registers Reset Values section (Page 201)
Added "Initial Startup" row for CVDD in Recommended Operating Conditions table (Page 117)
Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table (Page 77)
Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements table (Page 149)
Corrected tj(CORECLKN/P) max value from 100 to 0.02*tc(CORECLKN/P) (Page 150)
Corrected tj(DDRCLKN/P) max value from 0.025*tc(DDRCLKN/P) to 0.02*tc(DDRCLKN/P) (Page 153)
Corrected tj(PASSCLKN/P) max value from 100 to 0.02*tc(PASSCLKN/P) (Page 156)
Updated the descriptions of how Semaphore module is accessible (Page 229)
Added Debug Subsystem Configuration region to memory map table (Page 23)
Added HOUT timing diagram in Host Interrupt Output section (Page 188)
Added note to DDR3 PLL initialization sequence (Page 153)
Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FF (Page 190)
Revised IPCGRH register description (Page 89)
Corrected DDR3 transfer rate from 1033 MTS to 1066 MTS (Page 203)
Added CVDD and SmartReflex voltage parameter in SmartReflex switching table (Page 127)
Removed DDR3 PLL initialization sequence from data manual to PLL controller user guide (Page 153)
Removed PASS PLL initialization sequence from data manual to PLL controller user guide (Page 155)
Updated chip select from CS[5:2] to CE[3:0] in EMIF16 Peripheral section (Page 220)
Updated EMIF chip select from CS[5:2] to CE[3:0] in Memory Map Summary table (Page 27)
Updated DDR3 PLL initialization sequence (Page 153)
Added footnote for DDR3 EMIF data in memory map summary table (Page 27)
Updated Tracer descriptions across the data manual (Page 21)
Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns (Page 156)
Updated the Timer numbering across the whole document (Page 22)
Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet. (Page 29)
Added clarification for RESETSTATz input current (Page 118)
Added note for VCNTLID register that it is available for debug purpose only (Page 130)
Added STM Trace Switching Characteristics table (Page 230)
Removed the incorrect description of 16-Bit EMIF in Features section (Page 13)
Updated th(MDCLKH-MDIO) value from 10 ns to 0 ns in MDIO Timing Requirements table (Page 225)
Updated the description of NAND in the footnote of memory map summary table (Page 27)
Updated tw(DPnH) and tw(DPnL) descriptions in Trace Switching Characteristics tables (Page 230)
Updated I2C master mode table that bits[9:8] are used for mode selection (Page 32)
Updated the I2C passive mode table that bits[9:8] are used for mode selection and actual value on the bus is 0x19+bits[7:5] (Page 33)
Copyright 2013 Texas Instruments Incorporated
Revision History 233
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Updated I2C data rate configuration descriptions in I2C Master Mode Configuration table (Page 32)
Added PLLSELECT bit to PASSPLLCTL1 Register (Page 155)
Updated PASS PLL Block Diagram to reflect the mux selected by PASSPLLCTL1[13] (Page 154)
Added SPI device-specific support details (Page 209)
Corrected that only the sticky bits in PCIe MMRs will be retained after soft reset (Page 135)
Revision C
Added note stating that both SGMII ports can be used for boot (Page 31)
Updated the DDR3 MMR descriptions and deleted the unrelated PCIe MMR descriptions for soft reset. (Page 135)
Corrected physical 36-bit addresses of DDR3 EMIF configuration/data (Page 27)
Added TeraNet connection figures and added bridge numbers to the connection tables. (Page 99)
Restricted Output Divide of SECCTL register to max value of divide by 2 (Page 143)
Updated DEVSPEED register for both silicon rev1.0 and 2.0 (Page 96)
Removed RESETFULLz parameter from 4b timing description (Page 123)
Added supported data rates for HyperLink (Page 212)
Changed chip level interrupt controller name from INTC to CIC (Page 162)
Changed TPCC to EDMA3CC and TPTC to EDMA3TC (Page 156)
Added PLLRST bit to DDR3PLLCTL1 register (Page 152)
Added PLLRST bit to PASSPLLCTL1 register (Page 155)
Deleted INTC0 register map address offset 0x4 and 0x8, which are Reserved (Page 181)
Corrected the SGMII SerDes clock to PASS clock in PASS PLL configuration description (Page 41)
Corrected PASS PLL clock from SRIOSGMIICLK to PASSCLK in the boot device values table for Ethernet. (Page 29)
Corrected the SPI and DDR3/HyperLink Config end addressed (Page 27)
Added the DDR3 PLL Initialization Sequence (Page 153)
Added the Main PLL and PLL Controller Initialization Sequence (Page 149)
Added the PASS PLL Initialization Sequence (Page 155)
Added HyperLink interrupt event section (Page 212)
Added events #144-159 to INTC2 event input table (Page 176)
Added DEVSPEED Register section. (Page 96)
Added more description to Boot Sequence section (Page 27)
Corrected a typo, changed DDRCLKN to DDRCLKP (Page 153)
Revision B
Removed section 7.1 Parameter Information (Page 120)
Corrected PASS PLL clock source description from Main PLL mux to CORECLK clock reference sources (Page 154)
Corrected MACID2 address from 0x02600114 to 0x02620114 (Page 223)
Added EMIF16 Electrical Data/Timing section (Page 220)
Added TSIP Electrical Data/Timing section (Page 218)
Updated SPI Timing section (Page 209)
Changed Data Rate 3 to Reserved from 12.5GBs in HyperLink configuration field table (Page 34)
Corrected the Device ID field to be bits 5 to 3 in Ethernet Configuration Field figure and table (Page 31)
Corrected the field bits of No Boot/EMIF16 configuration field figure and table (Page 30)
Revision A
Added note to RSISO register that both SRIOISO and SRISO will be set by boot ROM code during boot (Page 147)
Modified PCIe peripherals introduction in Features section (Page 13)
Removed AIF2ISO from Reset Isolation Register (Page 147)
Added information of on-chip divider (=3) for PA in the PLL Boot Configuration Settings section (Page 41)
Changed "no support for MSI" to "support for legacy INTx" for PCIe in legacy EP mode description in Device Status Register Field Descrip-
tions table (Page 79)
Changed "no support for MSI" to "support for legacy INTx" for PCIe legacy end point description in Device Configuration Pins table
(Page 74)
Added "The packet accelerator is coupled with network coprocessor" in the Packet Accelerator section (Page 222)
Added Network Coprocessor document link (Page 73)
234
Revision History
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Changed 2 to OUTPUT_DIVIDE in the clock formula in PLL Boot Configuration Settings section (Page 41)
Changed EMAC to GbE switch subsystem (Page 223)
Changed EMAC to Gigabit Ethernet (GbE) Switch Subsystem (Page 225)
Changed EMAC to Gigabit Ethernet Switch (Page 73)
Changed EMAC to Network Coprocessor Packet DMA (Page 98)
Changed Ethernet MAC Subsystem to Gigabit Ethernet Switch Subsystem in Features (Page 13)
Changed PA_SS into Network Coprocessor Packet DMA in Device Master Settings table (Page 190)
Changed PA_SS into PASS in the Clock Sequencing table (Page 126)
Changed Packet Accelerator into Network Coprocessor and corrected the memory address in the memory map summary table (Page 21)
Changed Packet Accelerator into network coprocessor in Security Accelerator section (Page 222)
Changed Packet Accelerator into Network Coprocessor in the Device Configuration Pins table. (Page 74)
Changed Packet Accelerator subsystem into Network Coprocessor (Page 154)
Changed Packet Subsystem to Network Coprocessor (PASS PLL) in Terminal Functions table (Page 47)
Changed PASS into Network Coprocessor (PASS) (Page 140)
Changed PS_SS_CLK PLL to PASS_CLK PLL in Terminal Functions table (Page 47)
Deleted section 5.5 "C66x CorePac Resets" to avoid confusion and the reset details are covered in "Reset Controller" section (Page 108)
Removed EMAC in Characteristics of the device Processor table (Page 17)
Added BGA Package row into Characteristics of Processor table (Page 17)
Corrected End and Bytes of DDR3 EMIF Configuration section in Memory Map Summary table (Page 21)
Corrected BAR number from BAR1/2 to BAR2/3 and BAR3/4 to BAR4/5 in PCIe Window Sizes table (Page 32)
Deleted EDMA3 Peripheral Register Description section, which is covered in EDMA user guide (Page 156)
Added SERDES PLL Status and Config registers (Page 75)
Added "to DDR3 memory space" to the first step of workaround (Page 203)
Added "with TCCMOD=0" after "e.g. EDMA3 transfer controllers" (Page 203)
Added CPTS_RFTCLK_SEL register in GbE Switch Subsystem section (Page 223)
Changed "DSP/2" to "CPU/2" and "DSP/3" to "CPU/3" (Page 98)
Changed the word "can" to "must" in the sentence "for most applications increment mode can be used" to specify it is a hard rule.
(Page 157)
Corrected the tw(RXSTOP15) and tw(RXSTOP2) values in UART Timing Requirements table (Page 216)
Changed "sleep boot" to "No boot" in Sub-Mode field of No boot/EMIF16 Configuration Bit Field Descriptions table (Page 30)
Changed Section 2.5.2.1 title from "Sleep/EMIF16" to "No Boot/EMIF16" (Page 30)
Corrections Applied to I2C Passive Mode Device Configuration Bit Fields (Page 33)
Corrections Applied to I2C Passive Mode Device Configuration Field Descriptions (Page 33)
Modified description of value 0 to EMIF16/No Boot in Boot Device Values table (Page 29)
Corrected SRIO configuration memory map from 0x02900000~0x02907FFF to 0x02900000~0x02920FFF (Page 21)
Added thermal values into the Thermal Resistance Characteristics table. (Page 237)
Added DDR3PLLCTL1 register and field description table (Page 152)
Added more description to pin PTV15 in the Terminal Functions table (Page 48)
Added PASSPLLCTL1 register and field descriptions (Page 155)
Added Master ID Settings table. (Page 191)
Added the table of Power Supply to Peripheral I/O Mapping (Page 119)
Changed PROGn_MPEAR register table format and reset value format (Page 198)
Changed PROGn_MPSAR registers table format and reset value format (Page 198)
Modified the figure of SmartReflex 4-Pin VID Interface Timing (Page 127)
Modified the table of SmartReflex 4-Pin VID Interface Switching Characteristics (Page 127)
Added PROG4 registers set into MPU1 Registers table (Page 194)
Changed number of programmable ranges supported from 4 to 5 for MPU1 (Page 190)
Modified reset values in MPU Configuration Register table (Page 197)
Modified Table 2-13 to include 1000 MHz and 1250 MHz columns. (Page 41)
Added BWADJ[11:8] to MAINPLLCTL1 register table and description. (Page 149)
Changed Privilege ID from the second column to the first column (Page 190)
Changed PROG3_MPEA to PROG3_MPEAR in MPU1 Registers table (Page 194)
Changed Programmable range enumeration from 1-N based to 0-N based in MPU Register Map. (Page 193)
Changed SRIO_CPPI and SRIO_M rows to the single row (Page 190)
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Revision History 235
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Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
Changed the master from Reserved to HyperLink with Privilege ID 13 and 14 (Page 190)
Modified BWADJ descriptions in MAINPLLCTL0 and MAINPLLCTL1 registers (Page 148)
Modified SECCTL register reference place in the note. (Page 149)
Corrected Clock Sequencing table - Removed ALTCORECLK reference, Corrected SYSCLK as CORECLK. (Page 126)
Corrections Applied to I2C Boot Device Configuration Bit Fields (Page 32)
Corrections Applied to Sleep / EMIF16 Boot Device Configuration Bit Fields (Page 30)
Updated Device Configuration Pins Table; PACLKSEL Functional Description (Page 74)
Updated Reset Electrical Data / Timing section. Included updated reset requirements. (Page 137)
Updated Reset Electrical Data; Included updated Reset Requirements. (Page 137)
Updated Table 2-3 Boot Mode Pins: Boot Device Values description of the Ethernet (SGMII) boots. (Page 29)
Removed the SRIOSMGIICLK, MCMCLK, and PCIECLK transition timing values with respect to VOH and VOL within the Main PLL Controller
timing requirements. (Page 149)
Updated Terminal Descriptions of TSIP Pins (Page 57)
Updated EMIF16 timing requirements table (Page 220)
Added MAINPLLCTL1, Renamed DDR3PLLCTL0 to DDR3PLLCT, Renamed PAPLLCTL0 to PAPLLCTL (Page 75)
Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 21)
Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 21)
Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR (Page 121)
Added section NMI and LRSET. (Page 187)
Corrected Extended Temperature range - Changed 105C to 100C for the top end. (Page 13)
Added BWADJ bit field to DDR3 PLL Control Register. (Page 152)
Added BWADJ bit field to PASS PLL Control Register. (Page 154)
Added MAINPLLCTL1 register table and description. (Page 148)
Added more detailed information on valid levels for CLKs and IOs during the power sequencing. (Page 121)
Added Note on level interrupts and use of EOI handshaking. (Page 163)
Corrected Address Range of I2C MMRs (Page 205)
Corrected PACLKSEL bitfield description. (Page 79)
Corrected RSV01 should be pulled up to 1.8 V and RSV08 should be tied to GND (Page 58)
Changed CVDD Range; Corrected CVDD and CVDD1 Descriptions (CVDD: Core Supply -> SR Core Supply) (CVDD1: SR Core Supply -> Core
Supply) (Page 117)
Added more detailed information on valid levels for CLKs and IOs during the power sequencing. (Page 121)
Added to table "Terminal Functions - Signals and Control by Function", signals - RSV0A and RSV0B. (Page 47)
Corrected the timing pointers to point the correct figure (Page 137)
Changed incorrect reserved address in Memory Map Summary - 02780400 -> 02778400 (Page 21)
Corrected Commercial Temperature range - Changed 100C to 85C for the top end. (Page 13)
236
Revision History
Copyright 2013 Texas Instruments Incorporated
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
B Mechanical Data
B.1 Thermal Data
Table 2-1 shows the thermal resistance characteristics for the PBGA - CYP mechanical package.
Table 2-1
No.
Thermal Resistance Characteristics (PBGA Package) [CYP]
°C/W
0.18
3.71
1
2
RJC
RJB
Junction-to-case
Junction-to-board
End of Table 2-1
B.2 Packaging Information
The following packaging information reflects the most current released data available for the designated device(s).
This data is subject to change without notice and without revision of this document.
Copyright 2013 Texas Instruments Incorporated
Mechanical Data 237
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691D—April 2013
www.ti.com
238
Mechanical Data
Copyright 2013 Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2013
PACKAGING INFORMATION
Orderable Device
TMS320C6678ACYP
TMS320C6678ACYP25
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
FCBGA
FCBGA
CYP
841
841
44
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-4-245C-72HR
TMS320C6678CYP
@2010 TI
ACTIVE
ACTIVE
ACTIVE
CYP
CYP
CYP
44
44
44
Green (RoHS
& no Sb/Br)
Level-4-245C-72HR
0 to 85
TMS320C6678CYP
@2010 TI
1.25GHZ
TMS320C6678ACYPA
FCBGA
FCBGA
841
841
Green (RoHS
& no Sb/Br)
SNAGCU
Call TI
Level-4-245C-72HR
Call TI
TMS320C6678CYP
@2010 TI
A
TMS320C6678ACYPA25
TBD
-40 to 100
TMS320C6678CYP
@2010 TI
A1.25GHZ
TMS320C6678AXCYP
ACTIVE
ACTIVE
FCBGA
FCBGA
CYP
CYP
841
841
44
44
Green (RoHS
& no Sb/Br)
SNAGCU
SNAGCU
Level-4-245C-72HR
Level-4-245C-72HR
TMS320C6678XCYP
@2010 TI
TMS320C6678AXCYP25
Green (RoHS
& no Sb/Br)
0 to 85
TMS320C6678XCYP
@2010 TI
1.25GHZ
TMS320C6678AXCYPA
ACTIVE
FCBGA
CYP
841
44
Green (RoHS
& no Sb/Br)
SNAGCU
Level-4-245C-72HR
TMS320C6678XCYP
@2010 TI
A
TMS320C6678CYP
ACTIVE
ACTIVE
FCBGA
FCBGA
CYP
CYP
841
841
Green (RoHS
& no Sb/Br)
Call TI
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
0 to 85
0 to 85
TMS320C6678CYP
@2010 TI
TMS320C6678CYP25
Green (RoHS
& no Sb/Br)
TMS320C6678CYP
@2010 TI
1.25GHZ
TMS320C6678CYPA
ACTIVE
FCBGA
CYP
841
Green (RoHS
& no Sb/Br)
Call TI
Level-4-245C-72HR
-40 to 100
TMS320C6678CYP
@2010 TI
A1GHZ
TMS320C6678XCYP
TMS320C6678XCYP25
TMS320C6678XCYPA
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
CYP
CYP
CYP
841
841
841
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
0 to 85
0 to 85
-40 to 100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2013
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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