TMS320C6726RFP225 [TI]
Floating-Point Digital Signal Processors;
| 型号： | TMS320C6726RFP225 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Floating-Point Digital Signal Processors |
| 文件： | 总114页 (文件大小：944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
www.ti.com
SPRS268E–MAY 2005–REVISED JANUARY 2007
1 TMS320C6727, TMS320C6726, TMS320C6722 DSPs
1.1 Features
•
•
C672x: 32-/64-Bit 300-MHz Floating-Point DSPs
•
Three Multichannel Audio Serial Ports
–
–
–
–
Transmit/Receive Clocks up to 50 MHz
Six Clock Zones and 16 Serial Data Pins
Supports TDM, I2S, and Similar Formats
DIT-Capable (McASP2)
Upgrades to C67x+ CPU From C67x™ DSP
Generation:
–
–
–
2X CPU Registers [64 General-Purpose]
New Audio-Specific Instructions
Compatible With the C67x CPU
•
•
Universal Host-Port Interface (UHPI)
–
–
32-Bit-Wide Data Bus for High Bandwidth
Muxed and Non-Muxed Address and Data
•
•
Enhanced Memory System
–
–
–
–
256K-Byte Unified Program/Data RAM
384K-Byte Unified Program/Data ROM
Single-Cycle Data Access From CPU
Large Program Cache (32K Byte) Supports
RAM, ROM, and External Memory
Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin
Options
•
•
•
•
Two Inter-Integrated Circuit (I2C) Ports
Real-Time Interrupt Counter/Watchdog
Oscillator- and Software-Controlled PLL
Applications:
External Memory Interface (EMIF) Supports
–
–
100-MHz SDRAM (16- or 32-Bit)
Asynchronous NOR Flash, SRAM (8-,16-, or
32-Bit)
–
Professional Audio
•
•
•
•
•
•
•
Mixers
Effects Boxes
–
NAND Flash (8- or 16-Bit)
•
•
Enhanced I/O System
Audio Synthesis
Instrument/Amp Modeling
Audio Conferencing
Audio Broadcast
Audio Encoder
–
–
–
High-Performance Crossbar Switch
Dedicated McASP DMA Bus
Deterministic I/O Performance
dMAX (Dual Data Movement Accelerator)
Supports:
–
–
–
–
Emerging Audio Applications
Biometrics
Medical
–
–
16 Independent Channels
Concurrent Processing of Two Transfer
Requests
Industrial
–
1-, 2-, and 3-Dimensional
Memory-to-Memory and
•
•
Commercial or Extended Temperature
Memory-to-Peripheral Data Transfers
144-Pin, 0.5-mm, PowerPAD™ Thin Quad
Flatpack (TQFP) [RFP Suffix]
–
–
Circular Addressing Where the Size of a
Circular Buffer (FIFO) is not Limited to 2n
Table-Based Multi-Tap Delay Read and
Write Transfers From/To a Circular Buffer
•
256-Terminal, 1.0-mm, 16x16 Array Plastic Ball
Grid Array (PBGA) [GDH and ZDH Suffixes]
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
Philips is a registered trademark of Koninklijki Philips Electronics N.V.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
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SPRS268E–MAY 2005–REVISED JANUARY 2007
1.2 Description
The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance
32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727,
TMS320C6726, and TMS320C6722 devices.(1)
Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x
DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and
floating-point performance per clock cycle. At 300 MHz, the CPU is capable of a maximum performance of
2400 MIPS/1800 MFLOPS by executing up to eight instructions (six of which are floating-point
instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision
floating-point, and 64-bit double-precision floating-point arithmetic.
Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte
ROM as unified program/data memory. Development is simplified since there is no fixed division between
program and data memory size as on some other devices.
The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM.
Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are
supported:
•
•
•
Two 64-bit data accesses from the C67x+ CPU
One 256-bit program fetch from the core and program cache
One 32-bit data access from the peripheral system (either dMAX or UHPI)
The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most
program/data access conflicts to the on-chip memory. It also enables effective program execution from an
off-chip memory such as an SDRAM.
High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub between
the different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). The
crossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheral
connections).
Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus
masters for a particular target. When a conflict does occur, the arbitration is a simple and deterministic
fixed-priority scheme.
The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followed
next by the UHPI, and finally by the CPU.
dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement
Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers
between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX
allows movement of data to/from any addressable memory space including internal memory, peripherals,
and external memory.
The dMAX controller includes features such as the capability to perform three-dimensional data transfers
for advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFO
with delay-tap based reading and writing of data. The dMAX controller is capable of concurrently
processing two transfer requests (provided that they are to/from different source/destinations).
External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on the
C672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF data
width is 16 bits wide on the C6726 and C6722, and 32 bits wide on the C6727.
SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.
The C6726 and C6722 support SDRAM devices up to 128M bits.
(1) Throughout the remainder of the document, TMS320C6727 (or C6727), TMS320C6726 (or C6726), and/or TMS320C6722 (or C6722)
will be referred to as TMS320C672x (or C672x).
2
TMS320C6727, TMS320C6726, TMS320C6722 DSPs
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The C6727 extends SDRAM support to 256M-bit and 512M-bit devices.
Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device
that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the
dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.
The asynchronous memory interface can also be configured to support 8- or 16-bit-wide NAND flash. It
includes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to
512 bytes.
Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface
(UHPI) is a parallel interface through which an external host CPU can access memories on the DSP.
Three modes are supported by the C672x UHPI:
•
•
•
Multiplexed Address/Data - Half-Word (16-bit-wide) Mode (similar to C6713)
Multiplexed Address/Data - Full Word (32-bit-wide) Mode
Non-Multiplexed Mode - 16-bit Address and 32-bit Data Bus
The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the
address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows
the UHPI to be used for high-speed data transfers even in systems where security is an important
requirement.
The UHPI is only available on the C6727.
Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 Stereo Channels I2S.
The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and other
devices. It supports the ubiquitous IIS format as well as many variations of this format, including time
division multiplex (TDM) formats with up to 32 time slots.
Each McASP includes a transmit and receive section which may operate independently or synchronously;
furthermore, each section includes its own flexible clock generator and extensive error-checking logic.
As data passes through the McASP, it can be realigned so that the fixed-point representation used by the
application code can be independent of the representation used by the external devices without requiring
any CPU overhead to make the conversion.
The McASP is a configurable module and supports between 2 and 16 serial data pins. It also has the
option of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status and
user data memory.
McASP2 is not available on the C6722.
Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C)
serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interface
microcontroller. The other I2C serial port may then be used by the C672x DSP to control external
peripheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSP
device.
The two I2C serial ports are pin-multiplexed with the SPI0 serial port.
Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSP
also includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured as
a slave to control the DSP while the other SPI serial port is used by the DSP to control external
peripherals.
The SPI ports support a basic 3-pin mode as well as optional 4- and 5-pin modes. The optional pins
include a slave chip-select pin and an enable pin which implements handshaking automatically in
hardware for maximum SPI throughput.
The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port is
pin-multiplexed with five of the serial data pins from McASP0 and McASP1.
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Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:
•
•
•
•
Two 32-bit counter/prescaler pairs
Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)
Four compares with automatic update capability
Digital Watchdog (optional) for enhanced system robustness
Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals
in the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKIN
pin.
The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three
different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL
output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by
the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.
1.2.1 Device Compatibility
The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is
code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant
enhancements including additional floating-point instructions. See Section 2.2
4
TMS320C6727, TMS320C6726, TMS320C6722 DSPs
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1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the C672x device.
Program/Data
RAM
256K Bytes
JTAG EMU
32
256
D1
Data
R/W
McASP0
16 Serializers
64
64
C67x+ CPU
32
32
Program/Data
ROM Page0
256K Bytes
D2
Data
R/W
256
Memory
Controller
32
32
McASP1
6 Serializers
Program
Fetch
Program/Data
ROM Page1
128K Bytes
I/O
INT
256
32
McASP2
2 Serializers
+ DIT
32
32
32
32
32
32
32
32
32
CSP
PMP DMP
32 32
32
Program
Cache
32K Bytes
SPI1
SPI0
I2C0
I2C1
RTI
256
High-Performance
Crossbar Switch
32
32
32
32
32
I/O Interrupts MAX0
Out
CONTROL
dMAX
MAX1
Events
In
UHPI
PLL
EMIF
Peripheral Interrupt and DMA Events
A. UHPI is available only on the C6727. McASP2 is not available on the C6722.
Figure 1-1. C672x DSP Block Diagram
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Contents
1
2
TMS320C6727, TMS320C6726, TMS320C6722
4.3 Recommended Operating Conditions............... 33
4.4 Electrical Characteristics ............................ 34
4.5 Parameter Information .............................. 35
4.6 Timing Parameter Symbology....................... 36
4.7 Power Supplies...................................... 37
4.8 Reset ................................................ 38
DSPs........................................................ 1
1.1 Features .............................................. 1
1.2 Description............................................ 2
1.2.1 Device Compatibility ................................. 4
1.3 Functional Block Diagram ............................ 5
Device Overview ......................................... 7
2.1 Device Characteristics................................ 7
2.2 Enhanced C67x+ CPU ............................... 8
2.3 CPU Interrupt Assignments........................... 9
2.4 Internal Program/Data ROM and RAM.............. 10
2.5 Program Cache...................................... 11
2.6 High-Performance Crossbar Switch................. 12
2.7 Memory Map Summary ............................. 15
2.8 Boot Modes.......................................... 16
2.9 Pin Assignments .................................... 19
2.10 Development ........................................ 26
Device Configurations................................. 30
3.1 Device Configuration Registers ..................... 30
3.2 Peripheral Pin Multiplexing Options................. 30
3.3 Peripheral Pin Multiplexing Control ................. 31
Peripheral and Electrical Specifications........... 33
4.1 Electrical Specifications ............................. 33
4.2 Absolute Maximum Ratings ......................... 33
4.9
Dual Data Movement Accelerator (dMAX) .......... 39
4.10 External Interrupts................................... 44
4.11 External Memory Interface (EMIF) .................. 45
4.12 Universal Host-Port Interface (UHPI) [C6727 Only]. 55
4.13 Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2)........................................ 68
4.14 Serial Peripheral Interface Ports (SPI0, SPI1) ...... 80
4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) ... 93
4.16 Real-Time Interrupt (RTI) Timer With Digital
Watchdog............................................ 97
4.17 External Clock Input From Oscillator or CLKIN Pin 100
4.18 Phase-Locked Loop (PLL) ......................... 102
Application Example ................................. 105
Revision History ...................................... 106
Mechanical Data....................................... 107
3
4
5
6
7
7.1
Package Thermal Resistance Characteristics ..... 107
Supplementary Information About the 144-Pin RFP
7.2
PowerPAD™ Package............................. 108
7.3 Packaging Information ............................. 109
6
Contents
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2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the C672x DSPs. The table shows significant features of each device,
including the capacity of on-chip memory, the peripherals, the execution time, and the package type with
pin count.
Table 2-1. Characteristics of the C672x Processors
HARDWARE FEATURES
C6727
C6726
C6722
dMAX
EMIF
UHPI
1
1 (32-bit)
1 (16-bit)
1 (16-bit)
Peripherals
1
3
0
0
2
Not all peripheral pins are
available at the same time.
(For more details, see the
Device Configurations section.)
McASP
SPI
3 (McASP2 DIT only)
2
2
1
I2C
RTI
32KB Program Cache 32KB Program Cache 32KB Program Cache
On-Chip Memory
Size (KB)
256KB RAM
384KB ROM
256KB RAM
384KB ROM
128KB RAM
384KB ROM
Control Status Register
(CSR.[31:16])
CPU ID + CPU Rev ID
Frequency
0x0300
MHz
300, 250
250, 225
250, 225, 200
3.3 ns (C6727-300)
4 ns (C6727A-250 and
C6727-250)
4 ns (C6722-250)
4.4 ns (C6722A-225)
5 ns (C6722-200)
4 ns (C6726-250)
4.4 ns (C6726A-225)
Cycle Time
Voltage
ns
Core (V)
I/O (V)
1.2 V
3.3 V
Prescaler
Multiplier
Postscaler
/1, /2, /3, ..., /32
x4, x5, x6, ..., x25
/1, /2, /3, ..., /32
Clock Generator Options
Packages (see Section 7)
256-Terminal PBGA
(GDH)
256-Terminal Green
PBGA (ZDH)
17 x 17 mm
–
–
144-Pin PowerPAD
Green TQFP (RFP)
144-Pin PowerPAD
Green TQFP (RFP)
20 x 20 mm
µm
–
Process Technology
Product Status(1)
0.13 µm
Product Preview (PP),
Advance Information (AI), or
Production Data (PD)
PD
(1) Advance Information concerns new products in the sampling or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
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2.2 Enhanced C67x+ CPU
The TMS320C672x floating-point digital signal processors are based on the new C67x+ CPU. This core is
code-compatible with the C67x CPU core used on the TMS320C671x DSPs, but with significant
enhancements including an increase in core operating frequency from 225 MHz to 300 MHz(2) while
operating at 1.2 V.
The CPU fetches 256-bit-wide advanced very-long instruction word (VLIW) fetch packets that are
composed of variable-length execute packets. The execute packets can supply from one to eight 32-bit
instructions to the eight functional units during every clock cycle. The variable-length execute packets are
a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. Additionally,
execute packets can now span fetch packets, providing a code size improvement over the C67x CPU
core.
The CPU features two data paths, shown in Figure 2-1, each composed of four functional units (.D, .M, .S,
and .L) and a register file. The .D unit in each data path is a data-addressing unit that is responsible for all
data transfers between the register files and the memory. The .M functional units are dedicated for
multiplies, and the .S and .L functional units perform a general set of arithmetic, logical, and branch
functions. All instructions operate on registers as opposed to data in memory, but results stored in the
32-bit registers can be subsequently moved to memory as bytes, half-words, or words.
Data Path A
Data Path B
Cross
Paths
Register File A
Register File B
.D1
.M1
.S1
.L1
.D2
.M2
.S2
.L2
Figure 2-1. CPU Data Paths
The register file in each data path contains 32 32-bit registers for a total of 64 general-purpose registers.
This doubles the number of registers found on the C67x CPU core, allowing the optimizing C compiler to
pipeline more complex loops by decreasing register pressure significantly.
The four functional units in each data path of the CPU can freely share the 32 registers belonging to that
data path. Each data path also features a single cross path connected to the register file on the opposing
data path. This allows each data path to source one cross-path operand per cycle from the opposing
register file. On the C67x+ CPU, this single cross-path operand can be used by two functional units per
cycle, an improvement over the C67x CPU in which only one functional unit could use the cross-path
operand. In addition, the cross-path register read(s) are not counted as part of the limit of four reads of the
same register in a single cycle.
The C67x+ CPU executes all C67x instructions plus new floating-point instructions to improve
performance specifically during audio processing. These new instructions are listed in Table 2-2.
(2) CPU speed is device-dependent. See Table 2-1.
8
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Table 2-2. New Floating-Point Instructions for C67x+ CPU
FLOATING-POINT
OPERATION(1)
INSTRUCTION
MPYSPDP
IMPROVES
SP x DP → DP
Faster than MPYDP.
Improves high Q biquads (bass management) and FFT.
MPYSP2DP
SP x SP → DP
Faster than MPYDP.
Improves Long FIRs (EQ).
ADDSP (new to CPU “S” Unit)
ADDDP (new to CPU “S” Unit)
SUBSP (new to CPU “S” Unit)
SUBDP (new to CPU “S” Unit)
SP + SP → SP
DP + DP → DP
SP – SP → SP
DP – DP → DP
Now up to four floating-point add and subtract operations in parallel.
Improves FFT performance and symmetric FIR.
(1) SP means IEEE Single-Precision (32-bit) operations and DP means IEEE Double-Precision (64-bit) operations.
Finally, two new registers, which are dedicated to communication with the dMAX unit, have been added to
the C67x+ CPU. These registers are the dMAX Event Trigger Register (DETR) and the dMAX Event
Status Register (DESR). They allow the CPU and dMAX to communicate without requiring any accesses
to the memory system.
2.3 CPU Interrupt Assignments
Table 2-3 lists the interrupt channel assignments on the C672x device. If more than one source is listed,
the interrupt channel is shared and an interrupt on this channel could have come from any of the enabled
peripherals on that channel.
The dMAX peripheral has two CPU interrupts dedicated to reporting FIFO status (INT7) and transfer
completion (INT8). In addition, the dMAX can generate interrupts to the CPU on lines INT9–13 and INT15
in response to peripheral events. To enable this functionality, the associated Event Entry within the dMAX
can be programmed so that a CPU interrupt is generated when the peripheral event is received.
Table 2-3. CPU Interrupt Assignments
CPU INTERRUPT
INT0
INTERRUPT SOURCE
RESET
INT1
NMI (From dMAX or EMIF Interrupt)
INT2
Reserved
INT3
Reserved
INT4
RTI Interrupt 0
INT5
RTI Interrupts 1, 2, 3, and RTI Overflow Interrupts 0 and 1.
UHPI CPU Interrupt (from External Host MCU)
FIFO status notification from dMAX
INT6
INT7
INT8
Transfer completion notification from dMAX
dMAX event (0x2 specified in the dMAX interrupt event entry)
dMAX event (0x3 specified in the dMAX interrupt event entry)
dMAX event (0x4 specified in the dMAX interrupt event entry)
dMAX event (0x5 specified in the dMAX interrupt event entry)
dMAX event (0x6 specified in the dMAX interrupt event entry)
I2C0, I2C1, SPI0, SPI1 Interrupts
INT9
INT10
INT11
INT12
INT13
INT14
INT15
dMAX event (0x7 specified in the dMAX interrupt event entry)
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2.4 Internal Program/Data ROM and RAM
The organization of program/data ROM and RAM on C672x is simple and efficient. ROM is organized as
two 256-bit-wide pages with four 64-bit-wide banks. RAM is organized as a single 256-bit-wide page with
eight 32-bit-wide banks.
The internal memory organization is illustrated in Figure 2-2 (ROM) and Figure 2-3 (RAM).
ROM Page 1
Base Address
0x0004 0000
ROM Page 0
Base Address
0x0000 0000
Bank
0
Bank
1
Bank
2
Bank
3
Figure 2-2. Program/Data ROM Organization
RAM Page 0
Base Address
0x1000 0000
Bank
0
Bank
1
Bank
2
Bank
3
Bank
4
Bank
5
Bank
6
Bank
7
Figure 2-3. Program/Data RAM Organization
The C672x memory controller supports up to three parallel accesses to the internal RAM and ROM from
three of the following four sources as long as there are no bank conflicts:
•
•
•
Two 64-bit data accesses from the C67x+ CPU
One 256-bit-wide program fetch from the program cache
One 32-bit data access from the peripheral system (either dMAX or UHPI)
A program cache miss is 256 bits wide and conflicts only with data accesses to the same page. Multiple
data accesses to different pages, or to the same page but different banks will occur without conflict.
The organization of the C672x internal memory system into multiple pages (3 total) and a large number of
banks (16 total) means that it is straightforward to optimize DSP code to avoid data conflicts. Several
factors, including the large program cache and the partitioning of the memory system into multiple pages,
minimize the number of program versus data conflicts.
The result is an efficient memory system which allows easy tuning towards the maximum possible CPU
performance.
The C672x ROM consists of a software bootloader plus additional software. Please refer to the
C9230C100 TMS320C672x Floating-Point Digital Signal Processors ROM Data Manual (literature number
SPRS277) for more details on the ROM contents.
10
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2.5 Program Cache
The C672x DSP executes code directly from a large on-chip 32K-byte program cache. The program cache
has these key features:
•
•
•
•
•
•
•
Wide 256-bit path to internal ROM/RAM
Single-cycle access on cache hits
2-cycle miss penalty to internal ROM/RAM
Caches external memory as well as ROM/RAM
Direct-mapped
Modes: Enable, Freeze, Bypass
Software invalidate to support code overlay
The program cache line size is 256 bits wide and is matched with a 256-bit-wide path between cache and
internal memory. This allows the program cache to fill an entire line (corresponding to eight C67x+ CPU
instructions) with only a single miss penalty of 2 cycles.
The program cache control registers are listed in Table 2-4.
Table 2-4. Program Cache Control Registers
REGISTER NAME
L1PISAR
L1PICR
BYTE ADDRESS
0x2000 0000
DESCRIPTION
L1P Invalidate Start Address
L1P Invalidate Control Register
0x2000 0004
CAUTION
Any application which modifies the contents of program RAM (for example, a program
overlay) must invalidate the addresses from program cache to maintain coherency by
explicitly writing to the L1PISAR and L1PICR registers.
The Cache Mode (Enable, Freeze, Bypass) is configured through a CPU internal register (CSR, bits 7:5).
These options are listed in Table 2-5. Typically, only the Cache Enable Mode is used. But advanced users
may utilize Freeze and Bypass modes to tune performance.
Table 2-5. Cache Modes Set Through PCC Field of CSR CPU Register on C672x
CPU CSR[7:5]
CACHE MODE
000b
010b
011b
100b
Enable (Deprecated - Means direct mapped RAM on some C6000 devices)
Enable - Cache is enabled, cache misses cause a line fill.
Freeze - Cache is enabled, but contents are unchanged by misses.
Bypass - Forces cache misses, cache contents frozen.
Reserved - Not Supported
Other Values
CAUTION
Although the reset value of CSR[7:5] (PCC field) is 000b, the value may be modified
during the boot process by the ROM code. Refer to the appropriate ROM data sheet
for more details. However, note that the cache may be disabled when control is
actually passed to application code. Therefore, it may be necessary to write '010b' to
the PCC field to explicitly enable the cache at the start of application code.
CAUTION
Changing the cache mode through CSR[7:5] does not invalidate any lines already in
the cache. To invalidate the cache after modifications are made to program space, the
control registers L1PISAR and L1PICR must be used.
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2.6 High-Performance Crossbar Switch
The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus
masters and targets. Figure 2-4 illustrates the connectivity of the crossbar switch.
Program
Cache
ROM
RAM
CPU
PLL
RTI SPI0 SPI1 I2C0 I2C1
EMIF
External
Memory
SDRAM/
Flash
Memory Controller
T2
Data
Master
Port
CPU
Slave
Port
Program
Master
Port
Peripheral Configuration Bus
T3
(DMP)
(CSP)
(PMP)
Priority
BR4
M1
T1
M2
2
1
McASP0 McASP1 McASP2
BR1
BR2
BR3
SYSCLK1
SYSCLK2
SYSCLK1
SYSCLK3
SYSCLK1
SYSCLK3
SYSCLK2
McASP DMA Bus
T4
SYSCLK2
Priority
2
Priority
Priority
2
Priority
1
3
1
2
3
4
1
3
1
2
dMAX MAX0 Unit Master Port − High Priority
dMAX MAX1 Unit Master Port − Second Priority
Memory Controller DMP − Data Read/Write by CPU
UHPI Master Interface (External Host CPU)
M5
1
2
3
Crossbar
Priority
M3
MAX0 MAX1
M4
T5
External
Host MCU
Config
UHPI
Universal Host-Port
Interface
Config
dMAX
Figure 2-4. Block Diagram of Crossbar Switch
As shown in Figure 2-4, there are five bus masters:
M1
M2
M3
M4
M5
Memory controller DMP for CPU data accesses to peripherals and EMIF.
Memory controller PMP for program cache fills from the EMIF.
dMAX HiMAX master port for high-priority DMA accesses.
dMAX LoMAX master port for lower-priority DMA accesses.
UHPI master port for an external MCU to access on-chip and off-chip memories.
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The five bus masters arbitrate for five different target groups:
T1
T2
T3
T4
T5
On-chip memories through the CPU Slave Port (CSP).
Memories on the external memory interface (EMIF).
Peripheral registers through the peripheral configuration bus.
McASP serializers through the dedicated McASP DMA bus.
dMAX registers.
The crossbar switch supports parallel accesses from different bus masters to different targets. When two
or more bus masters contend for the same target beginning at the same cycle, then the highest-priority
master is given ownership of the target while the other master(s) are stalled. However, once ownership of
the target is given to a bus master, it is allowed to complete its access before ownership is arbitrated
again. Following are two examples.
Example 1: Simultaneous accesses without conflict
•
•
•
•
dMAX HiMAX accesses McASP Data Port for transfer of audio data.
dMAX LoMAX accesses SPI port for control processing.
UHPI accesses internal RAM through the CSP.
CPU fills program cache from EMIF.
Example 2: Conflict over a shared resource
•
•
dMAX HiMAX accesses RTI port for McASP sample rate measurement.
dMAX LoMAX accesses SPI port for control processing.
In Example 2, both masters contend for the same target, the peripheral configuration bus. The HiMAX
access will be given priority over the LoMAX access.
The master priority is illustrated in Figure 2-4 by the numbers 1 through 4 in the bus arbiter symbols. Note
that the EMIF arbitration is distributed so that only one bridge crossing is necessary for PMP accesses.
The effect is that PMP has 5th priority to the EMIF but lower latency.
A bus bridge is needed between masters and targets which run at different clock rates. The bus bridge
contains a small FIFO to allow the bridge to accept an incoming (burst) access at one clock rate and pass
it through the bridge to a target running at a different rate. Table 2-6 lists the FIFO properties of the four
bridges (BR1, BR2, BR3, and BR4) in Figure 2-4.
Table 2-6. Bus Bridges
LABEL
BR1
BRIDGE DESCRIPTION
DMP Bridge to peripherals, dMAX, EMIF
dMAX, UHPI to ROM/RAM (CSP)
PMP to EMIF
MASTER CLOCK
SYSCLK1
TARGET CLOCK
SYSCLK2
BR2
SYSCLK2
SYSCLK1
BR3
SYSCLK1
SYSCLK3
BR4
CPU, UHPI, and dMAX to EMIF
SYSCLK2
SYSCLK3
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Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and Table 2-7
contains a description of the bits.
31
15
16
Reserved
1
0
Reserved
CSPRST
R/W, 1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024)
Table 2-7. CFGBRIDGE Register Bit Field Description (0x4000 0024)
BIT NO.
31:1
0
NAME
Reserved
CSPRST
RESET VALUE
READ WRITE
N/A
DESCRIPTION
N/A
1
Reads are indeterminate. Only 0s should be written to these bits.
R/W
Resets the CSP Bridge (BR2 in Figure 2-4).
1 = Bridge Reset Asserted
0 = Bridge Reset Released
CAUTION
The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1
and SYSCLK2 and must be released before any accesses to the CSP bridge occur
from either the dMAX or the UHPI.
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2.7 Memory Map Summary
A high-level memory map of the C672x DSP appears in Table 2-8. The base address of each region is
listed. Any address past the end address must not be read or written. The table also lists whether the
regions are word-addressable or byte- and word-addressable.
Table 2-8. C672x Memory Map
DESCRIPTION
Internal ROM Page 0 (256K Bytes)
Internal ROM Page 1 (128K Bytes)
Internal RAM Page 0 (256K Bytes)
Memory and Cache Control Registers
Emulation Control Registers (Do Not Access)
Device Configuration Registers
PLL Control Registers
BASE ADDRESS
0x0000 0000
0x0004 0000
0x1000 0000
0x2000 0000
0x3000 0000
0x4000 0000
0x4100 0000
0x4200 0000
0x4300 0000
0x4400 0000
0x4500 0000
0x4600 0000
0x4700 0000
0x4800 0000
0x4900 0000
0x4A00 0000
0x5400 0000
0x5500 0000
0x5600 0000
0x6000 0000
0x6100 8000
0x6100 8080
0x6100 80A0
0x6200 8000
0x6200 8080
0x6200 80A0
0x8000 0000
0x9000 0000
0xF000 0000
END ADDRESS
0x0003 FFFF
0x0005 FFFF
0x1003 FFFF
0x2000 001F
0x3FFF FFFF
0x4000 0083
0x4100 015F
0x4200 00A3
0x4300 0043
0x4400 02BF
0x4500 02BF
0x4600 02BF
0x4700 007F
0x4800 007F
0x4900 007F
0x4A00 007F
0x54FF FFFF
0x55FF FFFF
0x56FF FFFF
0x6000 008F
0x6100 807F
0x6100 809F
0x6100 81FF
0x6200 807F
0x6200 809F
0x6200 81FF
0x8FFF FFFF
0x9FFF FFFF
0xF000 00BF
BYTE- OR WORD-ADDRESSABLE
Byte and Word
Byte and Word
Byte and Word
Word Only
Word Only
Word Only
Word Only
Real-time Interrupt (RTI) Control Registers
Universal Host-Port Interface (UHPI) Registers
McASP0 Control Registers
Word Only
Word Only
Word Only
McASP1 Control Registers
Word Only
McASP2 Control Registers
Word Only
SPI0 Control Registers
Word Only
SPI1 Control Registers
Word Only
I2C0 Control Registers
Word Only
I2C1 Control Registers
Word Only
McASP0 DMA Port (any address in this range)
McASP1 DMA Port (any address in this range)
McASP2 DMA Port (any address in this range)
dMAX Control Registers
Word Only
Word Only
Word Only
Word Only
MAX0 (HiMAX) Event Entry Table
Reserved
Byte and Word
MAX0 (HiMAX) Transfer Entry Table
MAX1 (LoMAX) Event Entry Table
Reserved
Byte and Word
Byte and Word
MAX1 (LoMAX) Transfer Entry Table
External SDRAM space on EMIF
External Asynchronous / Flash space on EMIF
EMIF Control Registers
Byte and Word
Byte and Word
Byte and Word
Word Only(1)
(1) The upper byte of the EMIF’s SDRAM Configuration Register (SDCR[31:24]) is byte-addressable to support placing the EMIF into the
Self-Refresh State without triggering the SDRAM Initialization Sequence.
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2.8 Boot Modes
The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM
starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader
stored in ROM. The software bootloader uses the CFGPIN0 and CFGPIN1 registers, which capture the
state of various device pins at reset, to determine which mode to enter. Note that in practice, only a few
pins are used by the software.
CAUTION
Only an externally applied RESET causes the CFGPIN0 and CFGPIN1 registers to
recapture their associated pin values. Neither an emulator reset nor a RTI reset
causes these registers to update.
The ROM bootmodes include:
•
•
•
•
Parallel Flash on EM_CS[2]
SPI0 or I2C1 master mode from serial EEPROM
SPI0 or I2C1 slave mode from external MCU
UHPI from an external MCU
Table 2-9 describes the required boot pin settings at device reset for each bootmode.
Table 2-9. Required Boot Pin Settings at Device Reset
BOOT MODE
UHPI_HCS
SPI0_SOMI
SPI0_SIMO
SPI0_CLK
UHPI
0
1
1
1
1
1
BYTEAD(1)
FULL(1)
NMUX(1)
Parallel Flash
SPI0 Master
SPI0 Slave
I2C1 Master
I2C1 Slave
0
0
0
1
1
1
0
1
0
1
0
1
1
1
1
(1) When UHPI_HCS is 0, the state of the SPI0_SOMI, SPI0_SIMO, and SPI0_CLK pins is copied into the specified bits in the CFGHPI
register described in Table 4-12.
Refer to the C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual
(literature number SPRS277) for details on supported bootmodes and their implementation.
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Figure 2-6 shows the bit layout of the CFGPIN0 register and Table 2-10 contains a description of the bits.
31
8
Reserved
7
6
5
4
3
2
1
0
PINCAP7
PINCAP6
PINCAP5
PINCAP4
PINCAP3
PINCAP2
PINCAP1
PINCAP0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000)
Table 2-10. CFGPIN0 Register Bit Field Description (0x4000 0000)
BIT NO.
NAME
DESCRIPTION
31:8
7
Reserved
PINCAP7
PINCAP6
PINCAP5
PINCAP4
PINCAP3
PINCAP2
PINCAP1
PINCAP0
Reads are indeterminate. Only 0s should be written to these bits.
SPI0_SOMI/I2C0_SDA pin state captured on rising edge of RESET pin.
SPI0_SIMO pin state captured on rising edge of RESET pin.
6
5
SPI0_CLK/I2C0_SCL pin state captured on rising edge of RESET pin.
SPI0_SCS/I2C1_SCL pin state captured on rising edge of RESET pin.
SPI0_ENA/I2C1_SDA pin state captured on rising edge of RESET pin.
AXR0[8]/AXR1[5]/SPI1_SOMI pin state captured on rising edge of RESET pin.
AXR0[9]/AXR1[4]/SPI1_SIMO pin state captured on rising edge of RESET pin.
AXR0[7]/SPI1_CLK pin state captured on rising edge of RESET pin.
4
3
2
1
0
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Figure 2-7 shows the bit layout of the CFGPIN1 register and Table 2-11 contains a description of the bits.
31
8
Reserved
7
6
5
4
3
2
1
0
PINCAP15
PINCAP14
PINCAP13
PINCAP12
PINCAP11
PINCAP10
PINCAP9
PINCAP8
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004)
Table 2-11. CFGPIN1 Register Bit Field Description (0x4000 0004)
BIT NO.
NAME
DESCRIPTION
Reads are indeterminate. Only 0s should be written to these bits.
AXR0[5]/SPI1_SCS pin state captured on rising edge of RESET pin.
AXR0[6]/SPI1_ENA pin state captured on rising edge of RESET pin.
UHPI_HCS pin state captured on rising edge of RESET pin.
UHPI_HD[0] pin state captured on rising edge of RESET pin.
EM_D[16]/UHPI_HA[0] pin state captured on rising edge of RESET pin.
AFSX0 pin state captured on rising edge of RESET pin.
31:8
7
Reserved
PINCAP15
PINCAP14
PINCAP13
PINCAP12
PINCAP11
PINCAP10
PINCAP9
PINCAP8
6
5
4
3
2
1
AFSR0 pin state captured on rising edge of RESET pin.
0
AXR0[0] pin state captured on rising edge of RESET pin.
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2.9 Pin Assignments
2.9.1 Pin Maps
Figure 2-8 and Figure 2-9 show the pin assignments on the 256-terminal GDH/ZDH package and the
144-pin RFP package, respectively.
EM_WE_
DQM[1]
T
R
P
N
M
L
V
DV
EM_WE EM_D[7] EM_D[5] EM_D[3]
V
EM_D[0] EM_D[14]
V
EM_D[11] EM_D[9]
EM_CKE
DV
V
SS
SS
DD
SS
SS
DD
EM_D[23]
/UHPI_ EM_CAS
HA[7]
EM_WE_
DQM[0]
EM_WE_
DQM[3]
DV
EM_D[6] EM_D[4] EM_D[2] EM_D[1] EM_D[15] EM_D[13] EM_D[12] EM_D[10] EM_D[8] EM_CLK
DV
DD
DD
EM_D[21] EM_D[20] EM_D[19] EM_D[17] EM_D[31]
/UHPI_
HA[15]
EM_D[28] EM_D[26] EM_D[24]
/UHPI_
HA[12]
UHPI_
HD[24]
EM_WE_ UHPI_
HD[7]
TCK
EMU[1]
EMU[0]
TDI
/UHPI_
HA[5]
/UHPI_
HA[4]
/UHPI_
HA[3]
/UHPI_
HA[1]
DV
DD
/UHPI_
HA[10]
/UHPI_ EM_A[12]
HA[8]
EM_A[11] EM_A[9]
EM_A[8] EM_A[7]
EM_A[6] EM_A[5]
EM_A[4] EM_A[3]
DQM[2]
EM_D[22]
/UHPI_
HA[6]
EM_D[18] EM_D[16] EM_D[30] EM_D[29] EM_D[27] EM_D[25]
/UHPI_
HA[11]
UHPI_
HD[25]
UHPI_
HD[26]
UHPI_
HD[5]
UHPI_
HD[6]
DV
DD
/UHPI_
HA[2]
/UHPI_
HA[0]
/UHPI_
HA[14]
/UHPI_
HA[13]
/UHPI_
HA[9]
DV
DD
UHPI_
HD[27]
UHPI_
HD[2]
TDO
DV
V
V
CV
CV
CV
DD
CV
DD
CV
CV
V
V
DV
DD
DD
SS
DD
DD
DD
DD
SS
UHPI_
HD[30]
UHPI_
HD[28]
UHPI_
HD[29]
UHPI_
HD[3]
UHPI_
HD[4]
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
UHPI_
HD[0]
UHPI_
HD[1]
K
J
V
PLLHV
TMS
TRST
CV
CV
CV
CV
CV
CV
CV
CV
EM_A[2]
V
SS
SS
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
DD
DD
DD
DD
UHPI_
HD[15]
OSCV
OSCIN OSCOUT OSCV
DV
DD
EM_A[1] EM_A[0]
EM_A[10] EM_BA[1]
SS
DD
UHPI_
HD[16]
/HHWIL
UHPI_
HD[31]
UHPI_
HD[14]
UHPI_
HD[13]
H
G
F
CLKIN
RESET
AFSX1
V
SS
UHPI_
HD[17]
UHPI_
HD[18]
UHPI_
HD[12]
UHPI_
HD[11]
V
EM_BA[0]
V
SS
SS
UHPI_
HD[19]
UHPI_
HD[20]
UHPI_
HD[10]
UHPI_
HD[9]
AFSR1
V
V
V
V
EM_CS[0] EM_RAS
SS
SS
UHPI_
HD[8]
UHPI_
HD[21]
E
D
C
B
A
ACLKR1 ACLKX1
AHCLKX1 AMUTE1
DV
CV
DD
CV
CV
DD
CV
DD
CV
CV
DV
EM_CS[2] EM_RW
SPI0_ENA
DD
DD
SS
DD
DD
DD
SS
DD
DD
UHPI_
HD[22]
UHPI_
HRDY
UHPI_
HDS[1]
UHPI_
HRW
UHPI_ AMUTE2/
HINT
DV
DV
ACLKX2
AFSX2
DV
DV
EM_WAIT EM_OE
/I2C1_
SDA
DD
DD
HCNTL[0]
SPI0_SCS SPI0_CLK
/I2C0_
SCL
AHCLKX0
AMUTE0
UHPI_
/AHCLKX2 HD[23]
UHPI_
HBE[2]
UHPI_
HBE[1]
UHPI_
HBE[0]
UHPI_
HDS[2]
UHPI_
HCS
UHPI_
HAS
UHPI_
HCNTL[1]
AFSR2
ACLKR2 AHCLKR2 /I2C1_
SCL
AXR0[8]
/AXR1[5]
/SPI1_
SPI0_
AXR0[7] AXR0[5]
/SPI1_
SCS
UHPI_ AHCLKR0
HBE[3]
AXR0[15] AXR0[13] AXR0[12] AXR0[10]
/AXR2[0] /AXR1[0]
/AXR1[1] /AXR1[3]
SPI0_
SIMO
SOMI
/I2C0_
SDA
DV
AFSR0
/SPI1_
CLK
AXR0[3] AXR0[1]
DV
DD
DD
/AHCLKR1
SOMI
AXR0[9]
/AXR1[4]
/SPI1_
AXR0[6]
/SPI1_
ENA
AXR0[14]
/AXR2[1]
AXR0[11]
/AXR1[2]
V
DV
DD
AFSX0
3
ACLKX0 ACLKR0
V
V
AXR0[4] AXR0[2] AXR0[0]
DV
DD
V
SS
SS
SS
7
SS
SIMO
1
2
4
5
6
8
9
10
11
12
13
14
15
16
Figure 2-8. 256-Terminal Ball Grid Array (GDH/ZDH Suffix)—Bottom View
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109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
V
V
SS
EM_CKE
EM_CLK
SS
SPI0_SIMO
SPI0_SOMI/I2C0_SDA
DV
DD
AXR0[0]
V
SS
DV
DD
V
EM_WE_DQM[1]
EM_D[8]
SS
AXR0[1]
AXR0[2]
AXR0[3]
CV
DD
EM_D[9]
EM_D[10]
V
SS
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
V
SS
EM_D[11]
DV
DD
EM_D[12]
EM_D[13]
CV
DD
EM_D[14]
EM_D[15]
CV
DD
V
SS
DV
DD
AXR0[8]/AXR1[5]/SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO
V
SS
CV
CV
DD
DD
V
EM_D[0]
EM_D[1]
SS
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
DV
DD
EM_D[2]
EM_D[3]
CV
V
DD
SS
V
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
SS
EM_D[4]
EM_D[5]
DV
DD
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR0
CV
DD
EM_D[6]
DV
DD
EM_D[7]
V
SS
AFSR0
ACLKX0
AHCLKR0/AHCLKR1
AFSX0
V
SS
EM_WE_DQM[0]
EM_WE
EM_CAS
A. Actual size of Thermal Pad is 5.4 mm × 5.4 mm. See Section 7.3.
Figure 2-9. 144-Pin Low-Profile Quad Flatpack (RFP Suffix)—Top View
20
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2.9.2 Terminal Functions
Table 2-12, the Terminal Functions table, identifies the external signal names, the associated pin/ball
numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the
pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO
mode, and a functional pin description.
Table 2-12. Terminal Functions
GDH/
ZDH
SIGNAL NAME
RFP
TYPE(1) PULL(2)
GPIO(3)
DESCRIPTION
External Memory Interface (EMIF) Address and Control
EM_A[0]
91
89
88
86
84
83
80
79
76
75
93
74
-
J16
J15
K15
L16
L15
M16
M15
N16
N15
P16
H15
P15
P12
G15
H16
F15
E15
R3
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EM_A[1]
-
EM_A[2]
-
EM_A[3]
-
EM_A[4]
-
EM_A[5]
-
EM_A[6]
-
EMIF Address Bus
EM_A[7]
-
EM_A[8]
-
EM_A[9]
-
EM_A[10]
EM_A[11]
EM_A[12]
EM_BA[0]
EM_BA[1]
EM_CS[0]
EM_CS[2]
EM_CAS
-
-
IPD
96
94
97
100
37
98
38
71
70
39
67
-
-
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
-
-
SDRAM Chip Select
-
Asynchronous Memory Chip Select
SDRAM Column Address Strobe
SDRAM Row Address Strobe
-
EM_RAS
F16
T3
-
EM_WE
-
SDRAM/Asynchronous Write Enable
SDRAM Clock Enable
EM_CKE
T14
R14
R4
-
EM_CLK
-
EMIF Output Clock
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_WE_DQM[2]
EM_WE_DQM[3]
EM_OE
-
Write Enable or Byte Enable for EM_D[7:0]
Write Enable or Byte Enable for EM_D[15:8]
Write Enable or Byte Enable for EM_D[23:16]
Write Enable or Byte Enable for EM_D[31:24]
SDRAM/Asynchronous Output Enable
Asynchronous Memory Read/not Write
T13
P13
R15
D15
E16
-
IPU
IPU
-
-
104
102
EM_RW
-
Asynchronous Wait Input (Programmable Polarity) or
Interrupt (NAND)
EM_WAIT
-
D14
I
IPU
N
(1) TYPE column refers to pin direction in functional mode. If a pin has more than one function with different directions, the functions are
separated with a slash (/).
(2) PULL column:
IPD = Internal Pulldown resistor
IPU = Internal Pullup resistor
(3) If the GPIO column is 'Y', then in GPIO mode, the pin is configurable as an IO unless otherwise marked.
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Table 2-12. Terminal Functions (continued)
GDH/
ZDH
SIGNAL NAME
RFP
TYPE(1) PULL(2)
GPIO(3)
DESCRIPTION
External Memory Interface (EMIF) Data Bus / Universal Host-Port Interface (UHPI) Address Bus Option
EM_D[0]
52
51
49
48
46
45
43
41
66
64
63
61
59
58
56
55
-
T8
R8
IO
IO
-
-
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
EM_D[1]
EM_D[2]
R7
IO
-
EM_D[3]
T6
IO
-
EM_D[4]
R6
IO
-
EM_D[5]
T5
IO
-
EM_D[6]
R5
IO
-
EM_D[7]
T4
IO
-
EMIF Data Bus [Lower 16 Bits]
EM_D[8]
R13
T12
R12
T11
R11
R10
T9
IO
-
EM_D[9]
IO
-
EM_D[10]
IO
-
EM_D[11]
IO
-
EM_D[12]
IO
-
EM_D[13]
IO
-
EM_D[14]
IO
-
EM_D[15]
R9
IO
-
EM_D[16]/UHPI_HA[0]
EM_D[17]/UHPI_HA[1]
EM_D[18]/UHPI_HA[2]
EM_D[19]/UHPI_HA[3]
EM_D[20]/UHPI_HA[4]
EM_D[21]/UHPI_HA[5]
EM_D[22]/UHPI_HA[6]
EM_D[23]/UHPI_HA[7]
EM_D[24]/UHPI_HA[8]
EM_D[25]/UHPI_HA[9]
EM_D[26]/UHPI_HA[10]
EM_D[27]/UHPI_HA[11]
EM_D[28]/UHPI_HA[12]
EM_D[29]/UHPI_HA[13]
EM_D[30]/UHPI_HA[14]
EM_D[31]/UHPI_HA[15]
N7
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IO/I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
-
P6
-
N6
-
P5
-
P4
-
P3
-
N4
-
R2
EMIF Data Bus [Upper 16 Bits (IO)] or
UHPI Address Input (I)
-
P11
N11
P10
N10
P9
-
-
-
-
-
N9
-
N8
-
P7
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Table 2-12. Terminal Functions (continued)
GDH/
ZDH
SIGNAL NAME
RFP
TYPE(1) PULL(2)
GPIO(3)
DESCRIPTION
Universal Host-Port Interface (UHPI) Data and Control
UHPI_HD[0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
K13
K14
M14
L13
L14
N13
N14
P14
E14
F14
F13
G14
G13
H14
H13
J13
H1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
UHPI_HD[1]
UHPI_HD[2]
UHPI_HD[3]
UHPI_HD[4]
UHPI_HD[5]
UHPI_HD[6]
UHPI_HD[7]
UHPI_HD[8]
UHPI_HD[9]
UHPI_HD[10]
UHPI_HD[11]
UHPI_HD[12]
UHPI_HD[13]
UHPI_HD[14]
UHPI_HD[15]
UHPI_HD[16]/HHWIL
UHPI_HD[17]
UHPI_HD[18]
UHPI_HD[19]
UHPI_HD[20]
UHPI_HD[21]
UHPI_HD[22]
UHPI_HD[23]
UHPI_HD[24]
UHPI_HD[25]
UHPI_HD[26]
UHPI_HD[27]
UHPI_HD[28]
UHPI_HD[29]
UHPI_HD[30]
UHPI_HD[31]
UHPI Data Bus [Lower 16 Bits]
G3
G4
F3
F4
UHPI Data Bus [Upper 16 Bits (IO)] in the following
modes:
E3
•
•
Fullword Multiplexed Address and Data
Fullword Non-Multiplexed
D3
C3
UHPI_HHWIL (I) on pin UHPI_HD[16]/HHWIL and GPIO
on other pins in the following mode:
P2
N2
•
Half-word Multiplexed Address and Data
N3
In this mode, UHPI_HHWIL indicates whether the high or
low half-word is being addressed.
M3
L3
L4
L2
H4
Universal Host-Port Interface (UHPI) Control
UHPI_HBE[0]
UHPI_HBE[1]
UHPI_HBE[2]
UHPI_HBE[3]
UHPI_HCNTL[0]
UHPI_HCNTL[1]
-
-
-
-
-
-
C6
C5
I
I
I
I
I
I
IPD
IPD
IPD
IPD
IPD
IPD
Y
Y
Y
Y
Y
Y
UHPI Byte Enable for UHPI_HD[7:0]
UHPI Byte Enable for UHPI_HD[15:8]
UHPI Byte Enable for UHPI_HD[23:16]
UHPI Byte Enable for UHPI_HD[31:24]
C4
B2
D9
UHPI Control Inputs Select Access Mode
C10
UHPI Host Address Strobe for Hosts with Multiplexed
Address/Data bus
UHPI_HAS
-
C9
I
IPD
Y
UHPI_HRW
UHPI_HDS[1]
UHPI_HDS[2]
UHPI_HCS
-
-
-
-
-
D8
D7
C7
C8
D6
I
I
IPD
IPU
IPU
IPU
IPD
Y
Y
Y
Y
Y
UHPI Read/not Write Input
UHPI Select Signals which create the internal HSTROBE
active when:
I
(UHPI_HCS == '0') & (UHPI_HDS[1] != UHPI_HDS[2])
UHPI Ready Output
I
UHPI_HRDY
O
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Table 2-12. Terminal Functions (continued)
GDH/
ZDH
SIGNAL NAME
RFP
TYPE(1) PULL(2)
GPIO(3)
DESCRIPTION
McASP0, McASP1, McASP2, and SPI1 Serial Ports
AHCLKR0/AHCLKR1
ACLKR0
143
139
141
2
B3
A5
IO
IO
IO
IO
IO
IO
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
McASP0 and McASP1 Receive Master Clock
McASP0 Receive Bit Clock
AFSR0
B4
McASP0 Receive Frame Sync (L/R Clock)
McASP0 and McASP2 Transmit Master Clock(4)
McASP0 Transmit Bit Clock
AHCLKX0/AHCLKX2
ACLKX0
C2
142
144
3
A4
AFSX0
A3
McASP0 Transmit Frame Sync (L/R Clock)
McASP0 MUTE Output
AMUTE0
C1
AXR0[0]
113
115
116
117
119
120
121
122
A14
B13
A13
B12
A12
B11
A11
B10
IO
IO
IO
IO
IO
IO
IO
IO
McASP0 Serial Data 0
AXR0[1]
McASP0 Serial Data 1
AXR0[2]
McASP0 Serial Data 2
AXR0[3]
McASP0 Serial Data 3
AXR0[4]
McASP0 Serial Data 4
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
McASP0 Serial Data 5 or SPI1 Slave Chip Select
McASP0 Serial Data 6 or SPI1 Enable (Ready)
McASP0 Serial Data 7 or SPI1 Serial Clock
AXR0[8]/AXR1[5]/
SPI1_SOMI
McASP0 Serial Data 8 or McASP1 Serial Data 5 or SPI1
Data Pin Slave Out Master In
126
127
B9
A9
IO
IO
-
-
Y
Y
AXR0[9]/AXR1[4]/
SPI1_SIMO
McASP0 Serial Data 9 or McASP1 Serial Data 4 or SPI1
Data Pin Slave In Master Out
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR1
130
131
134
135
137
138
9
B8
A8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
-
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
McASP0 Serial Data 10 or McASP1 Serial Data 3
McASP0 Serial Data 11 or McASP1 Serial Data 2
McASP0 Serial Data 12 or McASP1 Serial Data 1
McASP0 Serial Data 13 or McASP1 Serial Data 0
McASP0 Serial Data 14 or McASP2 Serial Data 1(4)
McASP0 Serial Data 15 or McASP2 Serial Data 0(4)
McASP1 Receive Bit Clock
-
B7
-
B6
-
A6
-
B5
-
-
E1
AFSR1
12
5
F1
-
McASP1 Receive Frame Sync (L/R Clock)
McASP1 Transmit Master Clock
AHCLKX1
D1
-
ACLKX1
7
E2
-
McASP1 Transmit Bit Clock
AFSX1
11
4
F2
-
McASP1 Transmit Frame Sync (L/R Clock)
McASP1 MUTE Output
AMUTE1
D2
-
AHCLKR2
-
C14
C13
C12
D11
C11
D10
IO
IO
IO
IO
IO
O
IPD
IPD
IPD
IPD
IPD
IPD
McASP2 Receive Master Clock
ACLKR2
-
McASP2 Receive Bit Clock
AFSR2
-
McASP2 Receive Frame Sync (L/R Clock)
McASP2 Transmit Bit Clock
ACLKX2
-
AFSX2
-
McASP2 Transmit Frame Sync (L/R Clock)
McASP2 MUTE Output or UHPI Host Interrupt
AMUTE2/HINT
-
SPI0, I2C0, and I2C1 Serial Port Pins
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
111
110
108
107
105
B14
B15
C16
C15
D16
IO
IO
IO
IO
IO
-
-
-
-
-
Y
Y
Y
Y
Y
SPI0 Data Pin Slave Out Master In or I2C0 Serial Data
SPI0 Data Pin Slave In Master Out
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
SPI0 Serial Clock or I2C0 Serial Clock
SPI0 Slave Chip Select or I2C1 Serial Clock
SPI0 Enable (Ready) or I2C1 Serial Data
(4) McASP2 is not available on the C6722.
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Table 2-12. Terminal Functions (continued)
GDH/
ZDH
SIGNAL NAME
RFP
TYPE(1) PULL(2)
GPIO(3)
DESCRIPTION
Clocks
OSCIN
23
24
25
22
17
27
J2
J3
J4
J1
H2
K2
I
-
-
-
-
-
-
N
N
N
N
N
N
1.2-V Oscillator Input
OSCOUT
OSCVDD
OSCVSS
CLKIN
O
1.2-V Oscillator Output
PWR
PWR
I
Oscillator 1.2-V VDD tap point (for filter only)
Oscillator VSS tap point (for filter only)
Alternate clock input (3.3-V LVCMOS Input)
PLL 3.3-V Supply Input (requires external filter)
PLLHV
PWR
Device Reset
RESET
14
G2
I
-
N
Device reset pin
Emulation/JTAG Port
TCK
35
19
28
29
21
32
34
P1
K3
L1
I
I
IPU
IPU
IPU
IPU
IPD
IPU
IPU
N
N
N
N
N
N
N
Test Clock
TMS
Test Mode Select
Test Data In
TDI
I
TDO
M2
K4
M1
N1
OZ
I
Test Data Out
Test Reset
TRST
EMU[0]
EMU[1]
IO
IO
Emulation Pin 0
Emulation Pin 1
Power Pins - 256-Terminal GDH/ZDH Package
Core Supply (CVDD
)
E6, E7, E8, E9, E10, E11, G5, G12, H5, H12, J5, J12, K5, K12, M6, M7, M8, M9, M10, M11
A2, A15, B1, B16, D4, D5, D12, D13, E4, E13, J14, M4, M13, N5, N12, P8, R1, R16, T2, T15
IO Supply (DVDD
)
A1, A7, A10, A16, E5, E12, F5, F6, F7, F8, F9, F10, F11, F12, G1, G6, G7, G8, G9, G10, G11, G16, H3, H6,
H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, J11, K1, K6, K7, K8, K9, K10, K11, K16, L5, L6, L7, L8, L9, L10,
L11, L12, M5, M12, T1, T7, T10, T16
Ground (VSS
)
Power Pins - 144-Pin RFP Package
Core Supply (CVDD
IO Supply (DVDD
Ground (VSS
)
8, 16, 20, 33, 44, 53, 57, 65, 77, 85, 90, 101, 123, 128, 132
)
10, 31, 42, 50, 60, 68, 73, 81, 92, 103, 112, 125, 136
)
1, 6, 13, 15, 18, 26, 30, 36, 40, 47, 54, 62, 69, 72, 78, 82, 87, 95, 99, 106, 109, 114, 118, 124, 129, 133, 140
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2.10 Development
2.10.1 Development Support
TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000™ DSP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
2.10.2 Device Support
2.10.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320C6727GDH250). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX / TMDX) through fully qualified production
devices/tools (TMS / TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
Fully-qualified production device
Support tool development evolutionary flow:
TMDX
Development support product that has not yet completed Texas Instruments internal
qualification testing
TMDS
Fully qualified development support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
“Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, GDH), the temperature range (for example, “A” is the extended temperature
range), and the device speed range in megahertz (for example, -300 is 300 MHz). Figure 2-10 provides a
legend for reading the complete device name for any TMS320C6000™ DSP platform member.
The ZDH package, like the GDH package, is a 256-ball plastic BGA, but Green.
For device part numbers and further ordering information for TMS320C672x in the GDH, ZDH, and RFP
package types, see the Texas Instruments (TI) website at http://www.ti.com or contact your TI sales
representative.
A
TMS 320 C6727 GDH
250
PREFIX
DEVICE SPEED RANGE
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
300 (300-MHz CPU)
250 (250-MHz CPU)
225 (225-MHz CPU)
200 (200-MHz CPU)
†
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
= −40°C to 105°C, extended temperature
DEVICE FAMILY
320 = TMS320t DSP family
§
‡
PACKAGE TYPE
GDH = 256-terminal plastic BGA
ZDH = 256-terminal Green plastic BGA
RFP = 144-pin PowerPAD Green TQFP
¶
DEVICE
C672x DSP:
6727
6726
6722
†
‡
§
¶
The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices. For
more details, see the recommended operating conditions portion of this data sheet.
BGA
= Ball Grid Array
TQFP = Thin Quad Flatpack
The ZDH mechanical package designator represents the Green version of the GDH package. For more detailed information, see the
Mechanical Data section of this document.
For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
Figure 2-10. TMS320C672x DSP Device Nomenclature
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2.10.2.2 Documentation Support
Extensive documentation supports the TMS320™ DSP family of devices from product announcement
through applications development. The types of documentation available include: data manuals, such as
this document, with design specifications; complete user's reference guides for all devices and tools;
technical briefs; development-support tools; on-line help; and hardware and software applications. The
following is a brief, descriptive list of support documentation specific to the C672x DSP devices:
SPRS277
C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual.
Describes the features of the C9230C100 TMS320C672x digital signal processor ROM.
SPRZ232
TMS320C6727, TMS320C6726, TMS320C6722 Digital Signal Processors Silicon Errata.
Describes the known exceptions to the functional specifications for the TMS320C6727,
TMS320C6726, and TMS320C6722 digital signal processors (DSPs).
SPRU723
SPRU877
SPRU795
TMS320C672x DSP Peripherals Overview Reference Guide. This document provides an
overview and briefly describes the peripherals available on the TMS320C672x digital signal
processors (DSPs) of the TMS320C6000 DSP platform.
TMS320C672x DSP Inter-Integrated Circuit (I2C) Module Reference Guide. This
document describes the inter-integrated circuit (I2C) module in the TMS320C672x digital
signal processors (DSPs) of the TMS320C6000 DSP platform.
TMS320C672x DSP Dual Data Movement Accelerator (dMAX) Reference Guide. This
document provides an overview and describes the common operation of the data movement
accelerator (dMAX) controller in the TMS320C672x digital signal processors (DSPs) of the
TMS320C6000 DSP platform. This document also describes operations and registers unique
to the dMAX controller.
SPRAA78 TMS320C6713 to TMS320C672x Migration. This document describes the issues related to
migrating from the TMS320C6713 to TMS320C672x digital signal processor (DSP).
SPRU711
SPRU718
TMS320C672x DSP External Memory Interface (EMIF) User's Guide. This document
describes the operation of the external memory interface (EMIF) in the TMS320C672x digital
signal processors (DSPs) of the TMS320C6000 DSP platform.
TMS320C672x DSP Serial Peripheral Interface (SPI) Reference Guide. This reference
guide provides the specifications for a 16-bit configurable, synchronous serial peripheral
interface. The SPI is
a programmable-length shift register, used for high speed
communication between external peripherals or other DSPs.
SPRU719
SPRU878
SPRU879
TMS320C672x DSP Universal Host Port Interface (UHPI) Reference Guide. This
document provides an overview and describes the common operation of the universal host
port interface (UHPI).
TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide. This
document describes the multichannel audio serial port (McASP) in the TMS320C672x digital
signal processors (DSPs) of the TMS320C6000 DSP platform.
TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller
Reference Guide. This document describes the operation of the software-programmable
phase-locked loop (PLL) controller in the TMS320C672x digital signal processors (DSPs) of
the TMS320C6000 DSP platform.
SPRU733
TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C67x and TMS320C67x+
digital signal processors (DSPs) of the TMS320C6000 DSP platform. The C67x/C67x+ DSP
generation comprises floating-point devices in the C6000 DSP platform. The C67x+ DSP is
an enhancement of the C67x DSP with added functionality and an expanded instruction set.
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SPRAA69 Using the TMS320C672x Bootloader Application Report. This document describes the
design details about the TMS320C672x bootloader. This document also addresses parallel
flash and HPI boot to the extent relevant.
SPRU301
SPRU198
TMS320C6000 Code Composer Studio Tutorial. This tutorial introduces you to some of
the key features of Code Composer Studio. Code Composer Studio extends the capabilities
of the Code Composer Integrated Development Environment (IDE) to include full awareness
of the DSP target by the host and real-time analysis tools. This tutorial assumes that you
have Code Composer Studio, which includes the TMS320C6000 code generation tools along
with the APIs and plug-ins for both DSP/BIOS and RTDX. This manual also assumes that
you have installed a target board in your PC containing the DSP device.
TMS320C6000 Programmer's Guide. Reference for programming the TMS320C6000 digital
signal processors (DSPs). Before you use this manual, you should install your code
generation and debugging tools. Includes a brief description of the C6000 DSP architecture
and code development flow, includes C code examples and discusses optimization methods
for the C code, describes the structure of assembly code and includes examples and
discusses optimizations for the assembly code, and describes programming considerations
for the C64x DSP.
SPRU186
SPRU187
TMS320C6000 Assembly Language Tools v6.0 Beta User's Guide. Describes the
assembly language tools (assembler, linker, and other tools used to develop assembly
language code), assembler directives, macros, common object file format, and symbolic
debugging directives for the TMS320C6000 platform of devices (including the C64x+ and
C67x+ generations). NOTE: The enhancements to tools release v5.3 to support the
C672x devices are documented in the tools v6.0 documentation.
TMS320C6000 Optimizing Compiler v6.0 Beta User's Guide. Describes the
TMS320C6000 C compiler and the assembly optimizer. This C compiler accepts ANSI
standard
C source code and produces assembly language source code for the
TMS320C6000 platform of devices (including the C64x+ and C67x+ generations). The
assembly optimizer helps you optimize your assembly code. NOTE: The enhancements to
tools release v5.3 to support the C672x devices are documented in the tools v6.0
documentation.
SPRA839
Using IBIS Models for Timing Analysis. Describes how to properly use IBIS models to
attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio™ Integrated
Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
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3 Device Configurations
3.1 Device Configuration Registers
The C672x DSP includes several device-level configuration registers, which are listed in Table 3-1. These
registers need to be programmed as part of the device initialization procedure. See Section 3.2.
Table 3-1. Device-Level Configuration Registers
REGISTER NAME
CFGPIN0
BYTE ADDRESS
0x4000 0000
DESCRIPTION
DEFINED
Table 2-10
Captures values of eight pins on rising edge of RESET pin.
Captures values of eight pins on rising edge of RESET pin.
Controls enable of UHPI and selection of its operating mode.
CFGPIN1
0x4000 0004
Table 2-11
Table 4-12
Table 4-13
CFGHPI
0x4000 0008
CFGHPIAMSB
0x4000 000C
Controls upper byte of UHPI address into C672x address space in
Non-Multiplexed Mode or if explicitly enabled for security purposes.
CFGHPIAUMB
CFGRTI
0x4000 0010
0x4000 0014
Controls upper middle byte of UHPI address into C672x address space Table 4-14
in Non-Multiplexed Mode or if explicitly enabled for security purposes.
Selects the sources for the RTI Input Captures from among the six
McASP DMA events.
Table 4-37
CFGMCASP0
CFGMCASP1
CFGMCASP2(1)
CFGBRIDGE
0x4000 0018
0x4000 001C
0x4000 0020
0x4000 0024
Selects the peripheral pin to be used as AMUTEIN0.
Selects the peripheral pin to be used as AMUTEIN1.
Selects the peripheral pin to be used as AMUTEIN2.
Table 4-19
Table 4-20
Table 4-21
Controls reset of the bridge BR2 in Figure 2-4. This bridge must be reset Table 2-7
explicitly after any change to the PLL controller affecting SYSCLK1 and
SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port
(CSP).
(1) CFGMCASP2 is reserved on the C6722.
3.2 Peripheral Pin Multiplexing Options
This section describes the options for configuring peripherals which share pins on the C672x DSP.
Table 3-2 lists the options for configuring the SPI0, I2C0, and I2C1 peripheral pins.
Table 3-2. Options for Configuring SPI0, I2C0, and I2C1
CONFIGURATION
OPTION 1
OPTION 2
OPTION 3
PERIPHERAL
PINS
SPI0
3-, 4,- or 5-pin mode 3-pin mode
disabled
enabled
enabled
I2C0_SDA
I2C0
disabled
disabled
I2C1
disabled
enabled
SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_SOMI
SPI0_SIMO
SPI0_CLK
SPI0_SCS
SPI0_ENA
SPI0_SOMI
SPI0_SIMO
SPI0_CLK
I2C1_SCL
I2C1_SDA
GPIO through SPI0_SIMO pin control
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
I2C0_SCL
I2C1_SCL
I2C1_SDA
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Table 3-3 lists the options for configuring the SPI1, McASP0, and McASP1 pins. Note that there are
additional finer grain options when selecting which McASP controls the particular AXR serial data pins but
these options are not listed here and can be made on a pin by pin basis.
Table 3-3. Options for Configuring SPI1, McASP0, and McASP1 Data Pins
CONFIGURATION
OPTION 1
5-pin mode
11
OPTION 2
4-pin mode
12
OPTION 3
4-pin mode
12
OPTION 4
3-pin mode
13
OPTION 5
disabled
PERIPHERAL
SPI1
McASP0
16
(max data pins)
McASP1
4
4
4
4
6
(max data pins)
PINS
AXR0[5]/
SPI1_SCS
SPI1_SCS
SPI1_ENA
SPI1_CLK
SPI1_SOMI
SPI1_SIMO
SPI1_SCS
AXR0[6]
SPI1_CLK
SPI1_SOMI
SPI1_SIMO
AXR0[5]
SPI1_ENA
SPI1_CLK
SPI1_SOMI
SPI1_SIMO
AXR0[5]
AXR0[6]
SPI1_CLK
SPI1_SOMI
SPI1_SIMO
AXR0[5]
AXR0[6]/
SPI1_ENA
AXR0[6]
AXR0[7]/
SPI1_CLK
AXR0[7]
AXR0[8]/AXR1[5]/
SPI1_SOMI
AXR0[8] or AXR1[5]
AXR0[9] or AXR1[4]
AXR0[9]/AXR1[4]/
SPI1_SIMO
Table 3-4 lists the options for configuring the shared EMIF and UHPI pins.
Table 3-4. Options for Configuring EMIF and UHPI (C6727 Only)
CONFIGURATION
OPTION 1
OPTION 2
PERIPHERAL
PINS
UHPI
EMIF
Multiplexed Address/Data Mode, Fullword, or Non-Multiplexed Address/Data Mode
Half-Word
Fullword
32-bit EMIF Data
EM_D[31:16]
16-bit EMIF Data
UHPI_HA[15:0]
EM_D[31:16]/
UHPI_HA[15:0]
3.3 Peripheral Pin Multiplexing Control
While Section 3.2 describes at a high level the most common pin multiplexing options, the control of pin
multiplexing is largely determined on an individual pin-by-pin basis. Typically, each peripheral that shares
a particular pin has internal control registers to determine the pin function and whether it is an input or an
output.
The C672x device determines whether a particular pin is an input or output based upon the following
rules:
•
The pin will be configured as an output if it is configured as an output in any of the peripherals sharing
the pin.
•
It is recommended that only one peripheral configure a given pin as an output. If more than one
peripheral does configure a particular pin as an output, then the output value is controlled by the
peripheral with highest priority for that pin. The priorities for each pin are given in Table 3-5.
•
The value input on the pin is passed to all peripherals sharing the pin for input simultaneously.
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Table 3-5. Priority of Control of Data Output on Multiplexed Pins
PIN
FIRST PRIORITY
SPI0_SOMI
SECOND PRIORITY
I2C0_SDA
THIRD PRIORITY
SPI0_SOMI/I2C0_SDA
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
AXR0[8]/AXR1[5]/SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO
AXR0[10]/AXR1[3]
SPI0_CLK
SPI0_SCS
SPI0_ENA
AXR0[5]
I2C0_SCL
I2C1_SCL
I2C1_SDA
SPI1_SCS
SPI1_ENA
SPI1_CLK
AXR1[5]
AXR0[6]
AXR0[7]
AXR0[8]
SPI1_SOMI
SPI1_SIMO
AXR0[9]
AXR1[4]
AXR0[10]
AXR0[11]
AXR0[12]
AXR0[13]
AXR0[14]
AXR0[15]
AHCLKR0
AHCLKX0
AMUTE2
HD[16]
AXR1[3]
AXR0[11]/AXR1[2]
AXR1[2]
AXR0[12]/AXR1[1]
AXR1[1]
AXR0[13]/AXR1[0]
AXR1[0]
AXR0[14]/AXR2[1]
AXR2[1]
AXR0[15]/AXR2[0]
AXR2[0]
AHCLKR0/AHCLKR1
AHCLKX0/AHCLKX2
AMUTE2/HINT
AHCLKR1
AHCLKX2
HINT
HD[16]/HHWIL
HHWIL
EM_D[31:16]/UHPI_HA[15:0](1)
EM_D[31:16] (Disabled if
CFGHPI.NMUX=1)
UHPI_HA[15:0] (Input Only)
(1) When using the UHPI in non-multiplexed mode, ensure EM_D[31:16] are configured as inputs so that these pins may be used as
UHPI_HA[15:0]. To ensure this, you must set the CFGHPI.NMUX bit to a '1' before the EMIF SDRAM initialization completes;
otherwise, a drive conflict will occur. [The EMIF bus parking function drives the data bus in between accesses.]
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4 Peripheral and Electrical Specifications
4.1 Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320C672x DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
4.2 Absolute Maximum Ratings(1)(2)
Over Operating Case Temperature Range (Unless Otherwise Noted)
UNIT
(3)
Supply voltage range, CVDD, OSCVDD
Supply voltage range, DVDD , PLLHV
Input Voltage Range
–0.3 to 1.8
V
V
–0.3 to 4
All pins except OSCIN
OSCIN pin
–0.3 to DVDD + 0.5
–0.3 to CVDD + 0.5
–0.3 to DVDD + 0.5
–0.3 to CVDD + 0.5
±20
V
Output Voltage Range
All pins except OSCOUT
OSCOUT pin
V
Clamp Current
mA
°C
°C
Operating case temperature range TC
Default
0 to 90
A version
–40 to 105
Storage temperature range, Tstg
–65 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with referenced to VSS unless otherwise specified.
(3) If OSCVDD and OSCVSS pins are used as filter pins for reduced oscillator jitter, they should not be connected to CVDD and VSS
externally.
4.3 Recommended Operating Conditions(1)
MIN
1.14
3.13
0
NOM
1.2
MAX UNIT
CVDD
DVDD
TC
Core Supply Voltage
1.32
3.47
90
V
V
I/O Supply Voltage
3.3
Operating Case Temperature Range
Default
°C
A version
–40
105
(1) All voltage values are with referenced to VSS unless otherwise specified.
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4.4 Electrical Characteristics
Over Operating Case Temperature Range (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VOH
VOL
IOH
High Level Output Voltage
Low Level Output Voltage
High-Level Output Current
Low-Level Output Current
High-Level Input Voltage
Low-Level Input Voltage
Input Hysterisis
IO = –100 µA
DVDD – 0.2
IO = 100 µA
0.2
–8
V
VO = 0.8 DVDD
VO = 0.22 DVDD
mA
mA
V
IOL
8
VIH
2
0
DVDD
0.8
VIL
V
VHYS
II, IOZ
0.13 DVDD
V
Input Current and Off State Output
Current
Pins without pullup or pulldown
Pins with internal pullup
±10
–170
170
25
–50
50
µA
Pins with internal pulldown
ttr
Input Transition Time
Input Capacitance
Output Capacitance
CVDD Supply(1)
ns
pF
pF
CI
7
CO
IDD2V
7
GDH, CVDD = 1.2 V,
CPU clock = 300 MHz
658
555
76
mA
mA
RFP, CVDD = 1.2 V,
CPU clock = 250 MHz
IDD3V
DVDD Supply(1)
GDH, DVDD = 3.3 V,
32-bit EMIF speed = 100 MHz
RFP, DVDD = 3.3 V,
58
16-bit EMIF speed = 100 MHz
(1) Assumes the following conditions: 25°C case temperature; 60% CPU utilization; EMIF at 50% utilization (100 MHz), 50% writes, (32 bits
for GDH, 16 bits for RFP), 50% bit switching; two 10-MHz SPI at 100% utilization, 50% bit switching.
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C672x Power
Consumption Summary Application Report (literature number SPRAAA4).
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4.5 Parameter Information
4.5.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not neccessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 4-1. Test Load Circuit for AC Timing Measurements
4.5.1.1 Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.
V
ref
= 1.5 V
Figure 4-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOL MAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 4-3. Rise and Fall Transition Time Voltage Reference Levels
4.5.1.2 Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
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4.6 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and
other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don't care level
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4.7 Power Supplies
For more information regarding TI’s power management products and suggested devices to power TI
DSPs, visit www.ti.com/dsppower.
4.7.1 Power-Supply Sequencing
This device does not require specific power-up sequencing between the DVDD and CVDD voltage rails;
however, there are some considerations that the system designer should take into account:
1. Neither supply should be powered up for an extended period of time (>1 second) while the other
supply is powered down.
2. The I/O buffers powered from the DVDD rail also require the CVDD rail to be powered up in order to be
controlled; therefore, an I/O pin that is supposed to be 3-stated by default may actually drive
momentarily until the CVDD rail has powered up. Systems should be evaluated to determine if there is
a possibility for contention that needs to be addressed. In most systems where both the DVDD and
CVDD supplies ramp together, as long as CVDD tracks DVDD closely, any contention is also mitigated by
the fact that the CVDD rail would reach its specified operating range well before the DVDD rail has fully
ramped.
4.7.2 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. The core supply caps can be placed in the interior space of the package and
the I/O supply caps can be placed around the exterior space of the package. For the BGA package, it is
recommended that both the core and I/O supply caps be placed on the underside of the PCB. For the
TQFP package, it is recommended that the core supply caps be placed on the underside of the PCB and
the I/O supply caps be placed on the top side of the PCB.
Both core and I/O decoupling can be accomplished by alternating small (0.1 µF) low ESR ceramic bypass
caps with medium (0.220 µF) low ESR ceramic bypass caps close to the DSP power pins and adding
large tantalum or ceramic caps (ranging from 10 µF to 100 µF) further away. Assuming 0603 caps, it is
recommended that at least 6 small, 6 medium, and 4 large caps be used for the core supply and 12 small,
12 medium, and 4 large caps be used for the I/O supply.
Any cap selection needs to be evaluated from an electromagnetic radiation (EMI) point-of-view; EMI varies
from one system design to another so it is expected that engineers alter the decoupling capacitors to
minimize radiation. Refer to the High-Speed DSP Systems Design Reference Guide (literature number
SPRU889) for more detailed design information on decoupling techniques.
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4.8 Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The
RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core
and I/O voltages have reached their proper operating conditions. As a best practice, RESET should be
held low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages
should be at their proper operating conditions.
4.8.1 Reset Electrical Data/Timing
Table 4-1 assumes testing over recommended operating conditions.
Table 4-1. Reset Timing Requirements
NO.
1
MIN
100
20
MAX
UNIT
ns
tw(RSTL)
Pulse width, RESET low
2
tsu(BPV-RSTH)
th(RSTH-BPV)
Setup time, boot pins valid before RESET high
Hold time, boot pins valid after RESET high
ns
3
20
ns
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4.9 Dual Data Movement Accelerator (dMAX)
4.9.1 dMAX Device-Specific Information
The dMAX is a module designed to perform Data Movement Acceleration. The dMAX controller handles
user-programmed data transfers between the internal data memory controller and the device peripherals
on the C672x DSP. The dMAX allows movement of data to/from any addressable memory space,
including internal memory, peripherals, and external memory. The dMAX controller in the C672x DSP has
a different architecture from the previous EDMA controller in the C621x/C671x devices.
The dMAX controller includes features, such as capability to perform three-dimensional data transfers for
advanced data sorting, capability to manage a section of the memory as a circular buffer/FIFO with delay
tap based reading and writing data. The dMAX controller is capable of concurrently processing two
transfer requests (provided that they are to/from different source/destinations).
Figure 4-4 shows a block diagram of the dMAX controller.
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High-Priority PaRAM
dMAX
Event Entry #0
Event
Entry
Table
Event Entry #k
HiMAX
RAM
R/W
Event Entry #31
Reserved
HiMAX
Master
Crossbar
Switch
Port
HiMAX
(MAX0)
Transfer Entry #0
Transfer
Entry
Table
High-Priority
REQ
Transfer Entry #k
Transfer Entry #7
Interrupt
Lines to
the CPU
Control
R/W
Event
Encoder
+
To/From
Crossbar
Switch
Event and
Interrupt
Events
Low-Priority PaRAM
Event Entry #0
Registers
Event
Entry
Table
Event Entry #k
Low-Priority
REQ
LoMAX
RAM
Event Entry #31
Reserved
R/W
LoMAX
Master
Crossbar
Switch
Port
LoMAX
(MAX1)
Transfer Entry #0
Transfer
Entry
Table
Transfer Entry #k
Transfer Entry #7
Figure 4-4. dMAX Controller Block Diagram
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The dMAX controller comprises:
•
•
•
•
•
•
Event and interrupt processing registers
Event encoder
High-priority event Parameter RAM (PaRAM)
Low-priority event Parameter RAM (PaRAM)
Address-generation hardware for High-Priority Events – MAX0 (HiMAX)
Address-generation hardware for Low-Priority Events – MAX1 (LoMAX)
The TMS320C672x Peripheral Bus Structure can be described logically as a Crossbar Switch with five
master ports and five slave ports. When accessing the slave ports, the MAX0 (HiMAX) module is always
given the highest priority followed by the MAX1 (LoMAX) module. In other words, in case several masters
(including MAX0 and MAX1) attempt to access same slave port concurrently, the MAX0 will be given the
highest priority followed by MAX1.
Event signals are connected to bits of the dMAX Event Register (DER), and the bits in the DER reflect the
current state of the event signals. An event is defined as a transition of the event signal. The dMAX Event
Flag Register (DEFR) can be programmed, individually for each event signal, to capture either low-to-high
or high-to-low transitions of the bits in the DER (event polarity is individually programmable).
An event is a synchronization signal that can be used: 1) to either trigger dMAX to start a transfer, or 2) to
generate an interrupt to the CPU. All the events are sorted into two groups: low-priority event group and
high-priority event group.
The High-Priority Data Movement Accelerator MAX0 (HiMAX) module is dedicated to serving requests
coming from the high-priority event group. The Low-Priority Data Movement Accelerator MAX1 (LoMAX)
module is dedicated to serving requests coming from the low-priority event group.
Each PaRAM contains two sections: the event entry table section and the transfer entry table section. An
event entry describes an event type and associates the event to either one of transfer types or to an
interrupt. In case an event entry associates the event to one of the transfer types, the event entry will
contain a pointer to the specific transfer entry in the transfer entry table. The transfer table may contain up
to eight transfer entries. A transfer entry specifies details required by the dMAX controller to perform the
transfer. In case an event entry associates the event to an interrupt, the event entry specifies which
interrupt should be generated to the CPU in case the event arrives.
Prior to enabling events and triggering a transfer, the event entry and transfer entry must be configured.
The event entry must specify: type of transfer, transfer details (type of synchronization, reload, element
size, etc.), and should include a pointer to the transfer entry. The transfer entry must specify: source,
destination, counts, and indexes. If an event is sorted in the high-priority event group, the event entry and
transfer entry must be specified in the high-priority Parameter RAM. If an event is sorted in the low-priority
event group, the event entry and transfer entry must be specified in the low-priority parameter RAM.
The dMAX Event Flag Register (DEFR) captures up to 31 separate events; therefore, it is possible for
events to occur simultaneously on the dMAX event inputs. In such cases, the event encoder resolves the
order of processing. This mechanism sorts simultaneous events and sets the priority of the events. The
dMAX controller can simultaneously process one event from each priority group. Therefore, the two
highest-priority events (one from each group) can be processed at the same time.
An event-triggered dMAX transfer allows the submission of transfer requests to occur automatically based
on system events, without any intervention by the CPU. The dMAX also includes support for CPU-initiated
transfers for added control and robustness, and they can be used to start memory-to-memory transfers.
To generate an event to the dMAX controller the CPU must create a transition on one of the bits from the
dMAX Event Trigger (DETR) Register, which are mapped to the DER register.
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Table 4-2 lists how the synchronization events are associated with event numbers in the dMAX controller.
Table 4-2. dMAX Peripheral Event Input Assignments
EVENT NUMBER
EVENT ACRONYM
DETR[0]
EVENT DESCRIPTION
0
The CPU triggers the event by creating appropriate transition (edge) on bit0
in DETR register.
1
DETR[16]
The CPU triggers the event by creating appropriate transition (edge) on bit16
in DETR register.
2
3
RTIREQ0
RTI DMA REQ[0]
RTIREQ1
RTI DMA REQ[1]
4
MCASP0TX
MCASP0RX
MCASP1TX
MCASP1RX
MCASP2TX
MCASP2RX
DETR[1]
McASP0 TX DMA REQ
McASP0 RX DMA REQ
McASP1 TX DMA REQ
McASP1 RX DMA REQ
McASP2 TX DMA REQ
McASP2 RX DMA REQ
5
6
7
8
9
10
The CPU triggers the event by creating appropriate transition (edge) on bit1
in DETR register.
11
DETR[17]
The CPU triggers the event by creating appropriate transition (edge) on bit17
in DETR register.
12
13
14
15
16
17
UHPIINT
SPI0RX
UHPI CPU_INT
SPI0 DMA_RX_REQ
SPI1 DMA_RX_REQ
RTI DMA REQ[2]
RTI DMA REQ[3]
SPI1RX
RTIREQ2
RTIREQ3
DETR[2]
The CPU triggers the event by creating appropriate transition (edge) on bit2
in DETR register.
18
DETR[18]
The CPU triggers the event by creating appropriate transition (edge) on bit18
in DETR register.
19
20
21
22
23
I2C0XEVT
I2C0REVT
I2C1XEVT
I2C1REVT
DETR[3]
I2C 0 Transmit Event
I2C 0 Receive Event
I2C 1 Transmit Event
I2C 1 Receive Event
The CPU triggers the event by creating appropriate transition (edge) on bit3
in DETR register.
24
DETR[19]
The CPU triggers the event by creating appropriate transition (edge) on bit19
in DETR register.
25
26
27
28
29
30
Reserved
MCASP0ERR
MCASP1ERR
MCASP2ERR
OVLREQ[0/1]
DETR[20]
AMUTEIN0 or McASP0 TX INT or McASP0 RX INT (error on McASP0)
AMUTEIN1 or McASP1 TX INT or McASP1 RX INT (error on McASP1)
AMUTEIN2 or McASP2 TX INT or McASP2 RX INT (error on McASP2)
Error on RTI
The CPU triggers the event by creating appropriate transition (edge) on bit20
in DETR register.
31
DETR[21]
The CPU triggers the event by creating appropriate transition (edge) on bit21
in DETR register.
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4.9.2 dMAX Peripheral Registers Description(s)
Table 4-3 is a list of the dMAX registers.
Table 4-3. dMAX Configuration Registers
BYTE ADDRESS
0x6000 0008
0x6000 000C
0x6000 0010
0x6000 0014
0x6000 0018
0x6000 001C
0x6000 0034
0x6000 0054
0x6000 0074
0x6000 0094
0x6000 0040
0x6000 0060
0x6000 0080
0x6000 00A0
N/A
REGISTER NAME
DEPR
DESCRIPTION
Event Polarity Register
Event Enable Register
Event Disable Register
Event High-priority Register
Event Low-priority Register
Event Flag Register
DEER
DEDR
DEHPR
DELPR
DEFR
DER0
Event Register 0
DER1
Event Register 1
DER2
Event Register 2
DER3
Event Register 3
DFSR0
DFSR1
DTCR0
DTCR1
DETR
DESR
FIFO Status Register 0
FIFO Status Register 1
Transfer Complete Register 0
Transfer Complete Register 1
Event Trigger Register (Located in C67x+ DSP Register File)
Event Status Register (Located in C67x+ DSP Register File)
N/A
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4.10 External Interrupts
The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in
combination with a McASP AMUTEIN signal to provide external interrupt capability. There is a multiplexer
for each McASP, controlled by the CFGMCASP0/1/2 registers, which allows the AMUTEIN input for that
McASP to be sourced from one of seven I/O pins on the DSP. Once a pin is configured as an AMUTEIN
source, a very short pulse (two SYSCLK2 cycles or more) on that pin will generate an event to the dMAX.
This event can trigger the dMAX to generate a CPU interrupt by programming the assoicated Event Entry.
There are a few additional points to consider when using the AMUTEIN signal to enable external interrupts
as described above. The I/O pin selected by the CFGMCASP0/1/2 registers must be configured as a
general-purpose input pin within the associated peripheral. Also, the AMUTEIN signal should be disabled
within the corresponding McASP so that AMUTE is not driven when AMUTEIN is active. This can be done
by clearing the INEN bit of the AMUTE register inside the McASP. Finally, AMUTEIN events are logically
ORed with the McASP transmit and receive error events within the dMAX; therefore, the ISR that
processes the dMAX interrupt generated by these events must discern the source of the event.
The EMIF EM_WAIT pin has the ability to generate an NMI (INT1) based upon a rising edge on the
EM_WAIT pin. Note that while this interrupt is connected to the CPU NMI (non-maskable interrupt), it is
actually maskable through the EMIF control registers. In fact, the default state for this interrupt is disabled.
Also, interrupt generation always occurs on a rising edge of EM_WAIT; the polarity selection for wait state
generation has no effect on the interrupt polarity. The EM_WAIT pin should remain asserted for at least
two SYSCLK3 cycles to ensure that the edge is detected.
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4.11 External Memory Interface (EMIF)
4.11.1 EMIF Device-Specific Information
The C672x DSP includes an external memory interface (EMIF) for optional SDRAM, NOR FLASH, NAND
FLASH, or SRAM. The key features of this EMIF are:
•
•
One chip select (EM_CS[0]) dedicated for x16 and x32 SDRAM (x8 not supported)
One chip select (EM_CS[2]) dedicated for x8, x16, or x32 NOR FLASH; x8, x16, or x32 Asynchronous
SRAM; or x8 or x16 NAND FLASH
•
•
•
•
•
•
Data bus width is 16 bits on the C6726 and C6722, and 32 bits on the C6727
SDRAM burst length of 16 bytes
External Wait Input on the C6727 through EM_WAIT (programmable active-high or active-low)
External Wait pin functions as an interrupt for NAND Flash support
NAND Flash logic calculates ECC on blocks of up to 512 bytes
ECC logic suitable for single-bit errors
Figure 4-5 and Figure 4-6 show typical examples of EMIF-to-memory hookup on the C672x DSP.
As the figures illustrate, the C672x DSP includes a limited number of EMIF address lines. These are
sufficient to connect to SDRAM seamlessly. Asynchronous memory such as FLASH typically will need to
use additional GPIO pins to act as upper address lines during device boot up when the FLASH contents
are copied into SDRAM. (Normally, code is executed from SDRAM since SDRAM has faster access
times).
Any pins listed with a ‘Y' in the GPIO column of Table 2-12 may be used for this purpose, as long as it can
be assured that they be pulled low at (and after) reset and held low until configured as outputs by the
DSP.
Note that EM_BA[1:0] are used as low-order address lines for the asynchronous interface. For example, in
Figure 4-5 and Figure 4-6, the flash memory is not byte-addressable and its A[0] input selects a 16-bit
value. The corresponding DSP address comes from EM_BA[1]. The remaining address lines from the
DSP (EM_A[12:0]) drive a word address into the flash inputs A[13:1].
For a more detailed explanation of the C672x EMIF operation please refer to the document
TMS320C672x External Memory Interface (EMIF) User's Guide (literature number SPRU711).
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C6726/C6722
DSP EMIF
SDRAM
2M x 16 x 4 Bank
EM_CS[0]
EM_CAS
EM_RAS
EM_WE
CE
CAS
RAS
WE
EM_CLK
EM_CKE
EM_BA[1:0]
CLK
CKE
BA[1:0]
EM_A[11:0]
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_D[15:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
EM_CS[2]
EM_RW
EM_OE
FLASH
512K x 16
EM_BA[1]
A[0]
GPIO
(6 Pins)
A[12:1]
DQ[15:0]
CE
RESET
WE
RESET
OE
RESET
A[18:13]
Any GPIO-capable pins which
can be pulled down at reset
can be used to control A[18:13]
for FLASH BOOTLOAD
RY/BY
Examples: AHCLKR0, SPI0_SCS/SCL1
Figure 4-5. C6726/C6722 DSP 16-Bit EMIF Example
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C6727
DSP EMIF
SDRAM
4M x 16 x 4 Bank
EM_CS[0]
EM_CAS
EM_RAS
EM_WE
CE
CAS
RAS
WE
EM_CLK
EM_CKE
EM_BA[1:0]
CLK
CKE
BA[1:0]
EM_A[12:0]
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_D[15:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
EM_WE_DQM[2]
EM_WE_DQM[3]
EM_D[31:16]/UHPI_HA[15:0]
EM_CS[2]
SDRAM
4M x 16 x 4 Bank
CE
EM_RW
EM_OE
EM_WAIT
CAS
RAS
WE
GPIO
(5 Pins)
CLK
CKE
BA[1:0]
RESET
A[12:0]
LDQM
RESET
UDQM
DQ[15:0]
FLASH
512K x 16
EM_BA[1]
A[0]
A[13:1]
DQ[15:0]
CE
WE
OE
RESET
A[18:14]
Any GPIO-capable pins which
RY/BY
can be pulled down at reset
can be used to control A[18:14]
for FLASH BOOTLOAD
Examples: AHCLKR0, SPI0_SCS/SCL1
Figure 4-6. C6727 DSP 32-Bit EMIF Example
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4.11.2 EMIF Peripheral Registers Description(s)
Table 4-4 is a list of the EMIF registers. For more information about these registers, see the
TMS320C672x DSP External Memory Interface (EMIF) User's Guide (literature number SPRU711).
Table 4-4. EMIF Registers
BYTE ADDRESS
0xF000 0004
0xF000 0008
0xF000 000C
0xF000 0010
0xF000 0020
0xF000 003C
0xF000 0040
0xF000 0044
0xF000 0048
0xF000 004C
0xF000 0060
0xF000 0064
0xF000 0070
REGISTER NAME
AWCCR
DESCRIPTION
Asynchronous Wait Cycle Configuration Register
SDRAM Configuration Register
SDCR
SDRCR
A1CR
SDRAM Refresh Control Register
Asynchronous 1 Configuration Register
SDRAM Timing Register
SDTIMR
SDSRETR
EIRR
SDRAM Self Refresh Exit Timing Register
EMIF Interrupt Raw Register
EIMR
EMIF Interrupt Mask Register
EIMSR
EMIF Interrupt Mask Set Register
EMIF Interrupt Mask Clear Register
NAND Flash Control Register
EIMCR
NANDFCR
NANDFSR
NANDF1ECC
NAND Flash Status Register
NAND Flash 1 ECC Register
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4.11.3 EMIF Electrical Data/Timing
Table 4-5 through Table 4-8 assume testing over recommended operating conditions (see Figure 4-7
through Figure 4-13).
Table 4-5. EMIF SDRAM Interface Timing Requirements
NO.
19
MIN
3
MAX UNIT
tsu(EM_DV-EM_CLKH)
th(EM_CLKH-EM_DIV)
Input setup time, read data valid on D[31:0] before EM_CLK rising
Input hold time, read data valid on D[31:0] after EM_CLK rising
ns
ns
20
1.9
Table 4-6. EMIF SDRAM Interface Switching Characteristics
NO.
1
PARAMETER
MIN
10
3
MAX UNIT
ns
tc(EM_CLK)
Cycle time, EMIF clock EM_CLK
2
tw(EM_CLK)
Pulse width, EMIF clock EM_CLK high or low
Delay time, EM_CLK rising to EM_CS[0] valid
Output hold time, EM_CLK rising to EM_CS[0] invalid
ns
3
td(EM_CLKH-EM_CSV)S
toh(EM_CLKH-EM_CSIV)S
7.7 ns
ns
4
1.15
1.15
5
td(EM_CLKH-EM_WE-DQMV)S
toh(EM_CLKH-EM_WE-DQMIV)S
td(EM_CLKH-EM_AV)S
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
7.7 ns
ns
6
Output hold time, EM_CLK rising to EM_WE_DQM[3:0] invalid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
7
7.7 ns
Output hold time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0]
invalid
8
toh(EM_CLKH-EM_AIV)S
1.15
ns
9
td(EM_CLKH-EM_DV)S
Delay time, EM_CLK rising to EM_D[31:0] valid
Output hold time, EM_CLK rising to EM_D[31:0] invalid
Delay time, EM_CLK rising to EM_RAS valid
7.7 ns
ns
10
11
12
13
14
15
16
17
18
toh(EM_CLKH-EM_DIV)S
td(EM_CLKH-EM_RASV)S
toh(EM_CLKH-EM_RASIV)S
td(EM_CLKH-EM_CASV)S
toh(EM_CLKH-EM_CASIV)S
td(EM_CLKH-EM_WEV)S
toh(EM_CLKH-EM_WEIV)S
tdis(EM_CLKH-EM_DHZ)S
tena(EM_CLKH-EM_DLZ)S
1.15
1.15
1.15
1.15
1.15
7.7 ns
ns
Output hold time, EM_CLK rising to EM_RAS invalid
Delay time, EM_CLK rising to EM_CAS valid
7.7 ns
ns
Output hold time, EM_CLK rising to EM_CAS invalid
Delay time, EM_CLK rising to EM_WE valid
7.7 ns
ns
Output hold time, EM_CLK rising to EM_WE invalid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
7.7 ns
ns
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Table 4-7. EMIF Asynchronous Interface Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Input setup time, read data valid on EM_D[31:0] before EM_CLK
rising
28
tsu(EM_DV-EM_CLKH)A
5
ns
29
30
31
33
th(EM_CLKH-EM_DIV)A
tsu(EM_CLKH-EM_WAITV)A
th(EM_CLKH-EM_WAITIV)A
tw(EM_WAIT)A
Input hold time, read data valid on EM_D[31:0] after EM_CLK rising
Setup time, EM_WAIT valid before EM_CLK rising edge
Hold time, EM_WAIT valid after EM_CLK rising edge
Pulse width of EM_WAIT assertion and deassertion
2
ns
ns
ns
ns
5
0
2E + 5
Delay from EM_WAIT sampled deasserted on EM_CLK rising to
beginning of HOLD phase
34
td(EM_WAITD-HOLD)A
4E(3) ns
Setup before end of STROBE phase (if no extended wait states are
inserted) by which EM_WAIT must be sampled asserted on
EM_CLK rising in order to add extended wait states.(4)
35
tsu(EM_WAITA-HOLD)A
4E(3)
ns
(1) E = SYSCLK3 (EM_CLK) period.
(2) These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.
(3) These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF
entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge
must also be met in order to ensure the EM_WAIT signal is correctly sampled.
(4) In Figure 4-13, it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are
part of the extended wait period should not be counted; the 4 EM_CLK requirement is to the start of where the HOLD phase would
begin if there were no extended wait cycles.
Table 4-8. EMIF Asynchronous Interface Switching Characteristics(1)
NO.
1
PARAMETER
MIN
10
3
MAX UNIT
tc(EM_CLK)
Cycle time, EMIF clock EM_CLK
ns
ns
2
tw(EM_CLK)
Pulse width, high or low, EMIF clock EM_CLK
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
Delay time, from EM_CLK rising edge to EM_CS[2] valid
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
Delay time, EM_CLK rising to EM_D[31:0] valid
Delay time, EM_CLK rising to EM_OE valid
Delay time, EM_CLK rising to EM_RW valid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Delay time, EM_CLK rising to EM_WE valid
17
18
21
22
23
24
25
26
27
32
tdis(EM_CLKH-EM_DHZ)S
tena(EM_CLKH-EM_DLZ)S
td(EM_CLKH-EM_CS2V)A
td(EM_CLKH-EM_WE_DQMV)A
td(EM_CLKH-EM_AV)A
td(EM_CLKH-EM_DV)A
td(EM_CLKH-EM_OEV)A
td(EM_CLKH-EM_RW)A
tdis(EM_CLKH-EM_DDIS)A
td(EM_CLKH-EM_WE)A
7.7 ns
ns
1.15
0
8
8
8
8
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
0
(1) These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.
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1
BASIC SDRAM
WRITE OPERATION
2
2
EM_CLK
3
5
7
7
9
4
EM_CS[0]
EM_WE_DQM[3:0]
EM_BA[1:0]
6
8
8
EM_A[12:0]
EM_D[31:0]
EM_RAS
EM_CAS
EM_WE
11
12
13
15
14
16
Figure 4-7. Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EM_CLK
EM_CS[0]
3
5
7
7
4
6
EM_WE_DQM[3:0]
EM_BA[1:0]
8
8
EM_A[12:0]
19
20
2 EM_CLK Delay
17
18
EM_D[31:0]
EM_RAS
11
12
13
14
EM_CAS
EM_WE
Figure 4-8. Basic SDRAM Read Operation
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ASYNCHRONOUS READ
WE STROBE MODE
STROBE
SETUP
HOLD
TA
EM_CLK
EM_CS[2]
21
22
23
23
17
21
22
23
23
EM_WE_DQM[3:0]
EM_BA[1:0]
ADDRESS
EM_A[12:0]
ADDRESS
28
29
25
READ DATA
EM_D[31:0]
25
18
EM_OE
EM_WE
EM_RW
Figure 4-9. Asynchronous Read WE Strobe Mode
ASYNCHRONOUS READ
SELECT STROBE MODE
SETUP
STROBE
21
HOLD
21
TA
EM_CLK
EM_CS[2]
22
23
23
17
22
23
23
EM_WE_DQM[3:0]
EM_BA[1:0]
BYTE LANE ENABLES
ADDRESS
EM_A[12:0]
ADDRESS
28
29
READ DATA
EM_D[31:0]
25
25
18
EM_OE
EM_WE
EM_RW
Figure 4-10. Asynchronous Read Select Strobe Mode
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ASYNCHRONOUS WRITE
WE STROBE MODE
STROBE
SETUP
HOLD
EM_CLK
21
22
23
23
24
21
22
23
23
EM_CS[2]
EM_WE_DQM[3:0]
EM_BA[1:0]
22
22
BYTE WRITE STROBES
ADDRESS
EM_A[12:0]
ADDRESS
27
EM_D[31:0]
WRITE DATA
EM_OE
EM_WE
32
32
26
26
EM_RW
Figure 4-11. Asynchronous Write WE Strobe Mode
ASYNCHRONOUS WRITE
SELECT STROBE MODE
SETUP
STROBE
HOLD
21
EM_CLK
EM_CS[2]
21
22
23
23
24
22
EM_WE_DQM[3:0]
EM_BA[1:0]
BYTE LANE ENABLES
23
23
ADDRESS
ADDRESS
WRITE DATA
EM_A[12:0]
27
EM_D[31:0]
EM_OE
32
32
EM_WE
EM_RW
26
26
Figure 4-12. Asynchronous Write Select Strobe Mode
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SETUP
STROBE
EXTENDED WAIT STATES
35
STROBE HOLD
34
EM_CLK
EM_WAIT
30
31
ASSERTED
33
DEASSERTED
33
Figure 4-13. EM_WAIT Timing Requirements
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4.12 Universal Host-Port Interface (UHPI) [C6727 Only]
4.12.1 UHPI Device-Specific Information
The C672x DSP includes a flexible universal host-port interface (UHPI) with more options than the
host-port interface on the C671x DSP.
The UHPI on the C672x DSP supports three major operating modes listed in Table 4-9.
Table 4-9. UHPI Major Modes on C672x
UHPI MAJOR MODE
EXAMPLE FIGURE
Figure 4-15
Multiplexed Host Address/Data Half-Word (16-Bit) Mode
Multiplexed Host Address/Data Fullword (32-Bit) Mode
Non-Multiplexed Host Address/Data Fullword (32-Bit) Mode
Figure 4-16
Figure 4-17
In all modes, the UHPI uses three select inputs (UHPI_HCS, UHPI_HDS[2:1]) which are combined
internally to produce the internal strobe signal HSTROBE. The HSTROBE strobe signal is used in the
UHPI to capture incoming address and control signals on its falling edge and write data on its rising edge.
The UHPI_HCS signal also gates the deassertion of the UHPI_HRDY signal externally.
UHPI_HDS[2]
UHPI_HDS[1]
Internal HSTROBE
Internal HRDY
UHPI_HCS
UHPI_HRDY
Figure 4-14. UHPI Strobe and Ready Interaction
The two HPI control pins UHPI_HCNTL[1:0] determine the type of access that the host will perform. Note
that only two of the four access types are supported in Non-Multiplexed Host Address/Data Fullword
Mode.
Table 4-10. HPI Access Types Selected by UHPI_HCNTL[1:0]
NON-
MULTIPLEXED
FULLWORD
MULTIPLEXED
HALF-WORD
MULTIPLEXED
FULLWORD
UHPI_HCNTL[1:0]
DESCRIPTION
00
01
10
11
HPI Control Register (HPIC) Access
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
HPI Data Access (HPID) with autoincrementing address
HPI Address Register (HPIA) Access
HPI Data Access (HPID) without autoincrementing
address
CAUTION
When performing
a
set of HPID with autoincrementing address accesses
(UHPI_HCNTL[1:0] = '01'), the set must begin and end at a word-aligned address. In
addition, all four of the UHPI_HBE[3:0] must be enabled on every access in the set.
CAUTION
The encoding of UHPI_CNTL[1:0] on the C672x DSP is different from HCNTL[1:0] on
the C671x DSP. Modes 01 and 10 are swapped.
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Figure 4-15 illustrates the Multiplexed Host Address/Data Half-Word Mode hookup between the C672x
DSP and an external host microcontroller. In this mode, each 32-bit HPI access is broken up into two
halves. The UHPI_HD[16]/HHWIL pin functions as UHPI_HHWIL which must be '0' during the first half of
access and '1' during the second half.
CAUTION
Unless configured as general-purpose I/O in the UHPI module, UHPI_HD[31:17] and
UHPI_HD[16]/HHWIL will be driven as outputs along with UHPI_HD[15:0] when the HPI
is read, even though only the lower half-word is used to transfer data. This can be
especially problematic for the UHPI_HD[16]/HHWIL pin which should be used as an
input in this mode. Therefore, be sure to configure the upper half of the UHPI_HD bus
as general-purpose I/O pins. Furthermore, be sure to program the UHPI_HD[16]
function as a general-purpose input to avoid a drive conflict with the external host
MCU.
In this mode, as well as the Multiplexed Host Address/Data Fullword mode, the UHPI can be made more
secure by restricting the upper 16 bits of the DSP addresses it can access to what is set in CFGHPIAMSB
and CFGHPIAUMB registers. (See Table 4-13 and Table 4-14).
The host is responsible for configuring the internal HPIA register whether or not it is being overridden by
the device configuration registers CFGHPIAMSB and CFGHPIAUMB.
After the HPIA register has been set, either a single or a group of autoincrementing accesses to HPID
may be performed.
The UHPI_HRDY adds wait states to extend the host MCU access until the C672x DSP has completed
the desired operation.
The HINT signal is available for the DSP to interrupt the host MCU. The UHPI also includes an interrupt to
the DSP core from the host as part of the HPIC register.
DSP
External Host MCU
(A)
EM_D[31:16]/UHPI_HA[15:0]
NC
(D)
UHPI_HCNTL[1:0]
UHPI_HD[15:0]
A[x:y]
D[15:0]
(E)
UHPI_HD[16]/HHWIL
UHPI_HD[31:17]
A[1]
NC or GPIO
(B)
UHPI_HAS
(C)
(F)
UHPI_HBE[1:0]
BE[1:0]
UHPI_HRW
R/W
(G)
(G)
UHPI_HDS[2]
WE
(G)
(G)
UHPI_HDS[1]
RD
UHPI_HCS
UHPI_HRDY
CS
RDY
AMUTE2/HINT
INTERRUPT
A. May be used as EM_D[31:16]
B. Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus.
C. DSP byte enables UHPI_HBE[3:2] are not required in this mode.
D. Two host address lines or host GPIO if address lines are not available.
E. A[1], assuming this address increments from 0 to 1 between two successive 16-bit accesses.
F. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write-enable
pins.
G. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements. Tie UHPI_HDS[2] and
UHPI_HDS[1] opposite. For more information, see Figure 4-14.
Figure 4-15. UHPI Multiplexed Host Address/Data Half-Word Mode
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Figure 4-16 illustrates the Multiplexed Host Address/Data Fullword Mode hookup between the C672x DSP
and an external host microcontroller. In this mode, all 32 bits of UHPI_HD[31:0] are used and the host can
access HPIA, HPID, and HPIC in a single bus cycle.
DSP
External Host MCU
(A)
EM_D[31:16]/UHPI_HA[15:0]
NC
(C)
UHPI_HCNTL[1:0]
UHPI_HD[15:0]
A[x:y]
D[15:0]
D[16]
UHPI_HD[16]/HHWIL
UHPI_HD[31:17]
D[31:17]
(B)
UHPI_HAS
(D)
UHPI_HBE[3:0]
UHPI_HRW
BE[3:0]
R/W
(E)
UHPI_HDS[2]
UHPI_HDS[1]
UHPI_HCS
WE
(E)
RD
CS
UHPI_HRDY
AMUTE2/HINT
RDY
INTERRUPT
A. May be used as EM_D[31:16]
B. Optional for hosts supporting multiplexed address and data. Pull up if not used. Low when address is on the bus.
C. Two host address lines or host GPIO if address lines are not available.
D. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable
pins.
E. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements.
Figure 4-16. UHPI Multiplexed Host Address/Data Fullword Mode
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Figure 4-17 illustrates the Non-Multiplexed Host Address/Data Fullword mode of the UHPI. In this mode,
the UHPI behaves almost like an asynchronous SRAM except it asserts the UHPI_HRDY signal. This
mode allows the host to randomly access a 64K-byte page in the C672x address space. The upper 32 bits
of the C672x address are set by the DSP (only) through the CFGHPIAMSB and CFGHPIAUMB registers
(see Table 4-13 and Table 4-14).
DSP
External Host MCU
A[17:2]
EM_D[31:16]/UHPI_HA[15:0]
(A)
UHPI_HCNTL[1:0]
UHPI_HD[15:0]
A[x:y]
D[15:0]
D[16]
UHPI_HD[16]/HHWIL
UHPI_HD[31:17]
D[31:17]
(B)
UHPI_HAS
(C)
UHPI_HBE[3:0]
UHPI_HRW
BE[3:0]
R/W
(D)
UHPI_HDS[2]
UHPI_HDS[1]
UHPI_HCS
WE
(D)
RD
CS
UHPI_HRDY
AMUTE2/HINT
RDY
INTERRUPT
A. Two host address lines or host GPIO if address lines are not available.
B. Not used in this mode.
C. Byte Enables (active during reads and writes). Some processors support a byte-enable mode on their write enable
pins.
D. Only required if needed for strobe timing. Not required if CS meets strobe timing requirements.
Figure 4-17. UHPI Non-Multiplexed Host Address/Data Fullword Mode
CAUTION
The EMIF data bus and UHPI HA inputs share the EM_D[31:16]/UHPI_HA[15:0] pins.
When using Non-Multiplexed mode, make sure the EMIF does not drive EM_D[31:16];
otherwise, a drive conflict with the external host MCU may result. Normally, the EMIF
will begin to drive the EM_D[31:16] lines immediately after it completes the SDRAM
initialization sequence, which occurs automatically after RESET is released. To avoid
a drive conflict then, the boot software must set CFGHPI.NMUX to '1' before the EMIF
drives EM_D[31:16]. Setting CFGHPI.NMUX to '1' forces these pins to be input pins.
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4.12.2 UHPI Peripheral Registers Description(s)
Table 4-11 is a list of the UHPI registers.
Table 4-11. UHPI Configuration Registers
BYTE ADDRESS
REGISTER NAME
DESCRIPTION
Device-Level Configuration Registers Controlling UHPI
0x4000 0008
0x4000 000C
0x4000 0010
CFGHPI
UHPI Configuration Register
Most Significant Byte of UHPI Address
Upper Middle Byte of UHPI Address
UHPI Internal Registers
CFGHPIAMSB
CFGHPIAUMB
0x4300 0000
0x4300 0004
0x4300 0008
0x4300 000C
0x4300 0010
0x4300 0014
0x4300 0018
0x4300 001C
0x4300 0020
0x4300 0024
0x4300 0028
0x4300 002C
0x4300 0030
0x4300 0034
0x4300 0038
0x4300 003C
0x4300 0040
PID
Peripheral ID Register
PWREMU
GPIOINT
GPIOEN
GPIODIR1
GPIODAT1
GPIODIR2
GPIODAT2
GPIODIR3
GPIODAT3
Reserved
Reserved
HPIC
Power and Emulation Management Register
General Purpose I/O Interrupt Control Register
General Purpose I/O Enable Register
General Purpose I/O Direction Register 1
General Purpose I/O Data Register 1
General Purpose I/O Direction Register 2
General Purpose I/O Data Register 2
General Purpose I/O Direction Register 3
General Purpose I/O Data Register 3
Reserved
Reserved
Control Register
HPIAW
Write Address Register
HPIAR
Read Address Register
Reserved
Reserved
Reserved
Reserved
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The UHPI has several device-level configuration registers which affect its behavior. Figure 4-18,
Figure 4-19, and Figure 4-20 show the bit layout of these registers. Table 4-12, Table 4-13, and
Table 4-14 contain a description of the bits in these registers.
31
8
Reserved
7
5
4
3
2
1
0
Reserved
BYTEAD
FULL
NMUX
PAGEM
ENA
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-18. CFGHPI Register Bit Layout (0x4000 0008)
Table 4-12. CFGHPI Register Bit Field Description (0x4000 0008)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
Reserved
DESCRIPTION
31:5
4
N/A
0
N/A
Reads are indeterminate. Only 0s should be written to these bits.
BYTEAD
R/W
UHPI Host Address Type
0 = Host Address is a word address
1 = Host Address is a byte address
3
2
FULL
0
0
R/W
R/W
UHPI Multiplexing Mode (when NMUX = 0)
0 = Half-Word (16-bit data) Multiplexed Address and Data Mode
1 = Fullword (32-bit data) Multiplexed Address and Data Mode
NMUX
UHPI Non-Multiplexed Mode Enable
0 = Multiplexed Address and Data Mode
1 = Non-Multiplexed Address and Data Mode (utilizes optional UHPI_HA[15:0] pins).
Host data bus is 32 bits in Non-Multiplexed mode. Setting this bit prevents the EMIF
from driving data out or 'parking' the shared EM_D[31:16]/UHPI_HA[15:0] pins.
1
0
PAGEM
ENA
0
0
R/W
R/W
UHPI Page Mode Enable (Only for Multiplexed Address and Data Mode).
0 = Full 32-bit DSP address specified through host port.
1 = Only lower 16 bits of DSP address are specified through host port. Upper 16 bits
are restricted to the page selected by CFGHPIAMSB and CFGHPIAUMB registers.
UHPI Enable
0 = UHPI is disabled
1 = UHPI is enabled. Set this bit to '1' only after configuring the other bits in this
register.
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31
8
0
Reserved
7
HPIAMSB
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C)
Table 4-13. CFGHPIAMSB Register Bit Field Description (0x4000 000C)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
DESCRIPTION
31:8
7:0
Reserved
HPIAMSB
N/A
0
N/A
Reads are indeterminate. Only 0s should be written to these bits.
R/W
UHPI most significant byte of DSP address to access in Non-Multiplexed mode and
in Multiplexed Address and Data mode when PAGEM = 1. Sets bits [31:24] of the
DSP internal address as accessed through UHPI.
31
7
8
Reserved
0
HPIAUMB
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-20. CFGHPIAUMB Register Bit Layout (0x4000 0010)
Table 4-14. CFGHPIAUMB Register Bit Field Description (0x4000 0010)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
DESCRIPTION
31:8
7:0
Reserved
HPIAUMB
N/A
0
N/A
Reads are indeterminate. Only 0s should be written to these bits.
R/W
UHPI upper middle byte of DSP address to access in Non-Multiplexed mode and in
Multiplexed Address and Data mode when PAGEM = 1. Sets bits [23:16] of the DSP
internal address as accessed through UHPI.
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4.12.3 UHPI Electrical Data/Timing
4.12.3.1 Universal Host-Port Interface (UHPI) Read and Write Timing
Table 4-15 and Table 4-16 assume testing over recommended operating conditions (see Figure 4-21
through Figure 4-24).
Table 4-15. UHPI Read and Write Timing Requirements(1)(2)
NO.
9
MIN
5
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(HASL-DSL)
th(DSL-HASL)
tsu(HAD-HASL)
th(HASL-HAD)
tw(DSL)
Setup time, UHPI_HAS low before DS falling edge
Hold time, UHPI_HAS low after DS falling edge
Setup time, HAD valid before UHPI_HAS falling edge
Hold time, HAD valid after UHPI_HAS falling edge
Pulse duration, DS low
10
11
12
13
14
15
16
17
18
37
38
2
5
5
15
2P
5
tw(DSH)
Pulse duration, DS high
tsu(HAD-DSL)
th(DSL-HAD)
tsu(HD-DSH)
th(DSH-HD)
Setup time, HAD valid before DS falling edge
Hold time, HAD valid after DS falling edge
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge
Setup time, UHPI_HCS low before DS falling edge
Hold time, DS low after UHPI_HRDY rising edge
5
5
0
tsu(HCSL-DSL)
th(HRDYH-DSL)
0
1
(1) P = SYSCLK2 period
(2) DS refers to HSTROBE. HD refers to UHPI_HD[31:0]. HDS refers to UHPI_HDS[1] or UHPI_HDS[2]. HAD refers to UHPI_HCNTL[0],
UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HRW.
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Table 4-16. UHPI Read and Write Switching Characteristics(1)(2)
NO.
PARAMETER
MIN
MAX
UNIT
Case 1. HPIC or HPIA read
1
15
Case 2. HPID read with no
auto-increment
9 * 2H + 20(3)
Case 3. HPID read with
auto-increment and read FIFO
initially empty
9 * 2H + 20(3)
1
td(DSL-HDV)
Delay time, DS low to HD valid
ns
Case 4. HPID read with
auto-increment and data previously
prefetched into the read FIFO
1
15
2
3
4
5
tdis(DSH-HDV)
ten(DSL-HDD)
td(DSL-HRDYH)
td(DSH-HRDYH)
Disable time, HD high-impedance from DS high
Enable time, HD driven from DS low
1
3
4
15
12
12
ns
ns
ns
ns
Delay time, DS low to UHPI_HRDY high
Delay time, DS high to UHPI_HRDY high
Case 1. HPID read with no
auto-increment
10 * 2H + 20(3)
Delay time, DS low to UHPI_HRDY
low
6
7
td(DSL-HRDYL)
ns
Case 2. HPID read with
auto-increment and read FIFO
initialy empty
10 * 2H + 20(3)
td(HDV-HRDYL)
Delay time, HD valid to UHPI_HRDY low
Case 1. HPIA write
0
ns
ns
5 * 2H + 20(3)
5 * 2H + 20(3)
Delay time, DS high to
UHPI_HRDY low
Case 2. HPID read with
auto-increment and read FIFO
initially empty
34 td(DSH-HRDYL)
Delay time, DS low to UHPI_HRDY low for HPIA write and FIFO not
empty
35 td(DSL-HRDYL)
36 td(HASL-HRDYH)
40 * 2H + 20(3)
12
ns
ns
Delay time, UHPI_HAS low to UHPI_HRDY high
(1) H = 0.5 * SYSCLK2 period
(2) DS refers to HSTROBE. HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HRW.
(3) Max delay is a best case, assuming no delays due to resource conflicts between UHPI and dMAX or CPU. UHPI_HRDY should always
be used to indicate when an access is complete instead of relying on these parameters.
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Read
Write
UHPI_HCS
37
37
14
13
13
UHPI_HDSx
15
16
15
16
UHPI_HRW
UHPI_HA[15:0]
Valid
Valid
1
2
3
UHPI_HD[31:0]
(Read)
Read data
18
17
UHPI_HD[31:0]
(Write)
Write data
34
4
7
5
6
UHPI_HRDY
A. Depending on the type of write or read operation (HPID or HPIC), transitions on UHPI_HRDY may or may not occur.
Figure 4-21. Non-Multiplexed Read/Write Timings
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UHPI_HCS
UHPI_HAS
12
11
12
11
UHPI_HCNTL[1:0]
12
11
12
11
UHPI_HRW
12
11
12
11
UHPI_HHWIL
10
9
10
9
37
13
13
37
14
(A)
HSTROBE
1
3
1
3
2
2
UHPI_HD[15:0]
7
38
36
6
UHPI_HRDY
A. See Figure 4-14.
B. Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
Figure 4-22. Multiplexed Read Timings Using UHPI_HAS
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UHPI_HCS
UHPI_HAS
UHPI_HCNTL[1:0]
UHPI_HRW
UHPI_HHWIL
13
16
13
16
15
15
37
14
37
(A)
HSTROBE
3
1
3
1
2
2
UHPI_HD[15:0]
38
4
7
6
UHPI_HRDY
A. See Figure 4-14.
B. Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
Figure 4-23. Multiplexed Read Timings With UHPI_HAS Held High
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UHPI_HCS
UHPI_HAS
UHPI_HCNTL[1:0]
UHPI_HRW
UHPI_HHWIL
16
13
16
15
37
15
37
13
14
(A)
HSTROBE
18
34
18
17
17
UHPI_HD[15:0]
34
38
4
5
35
5
UHPI_HRDY
A. See Figure 4-14.
B. Depending on the type of write or read operation (HPID without auto-incrementing, HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
Figure 4-24. Multiplexed Write Timings With UHPI_HAS Held High
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4.13 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst).
Time slots of 8,12,16, 20, 24, 28, and 32 bits.
First bit delay 0, 1, or 2 clocks.
MSB or LSB first bit order.
Left- or right-aligned data words within time slots
•
•
•
DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers.
Extensive error-checking and mute generation logic
All unused pins GPIO-capable
Pins
Function
AHCLKRx Receive Master Clock
Receive Logic
Clock/Frame Generator
State Machine
Peripheral
Configuration
Bus
GIO
Control
ACLKRx
AFSRx
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
The McASPs DO NOT have
dedicated AMUTEINx pins.
AMUTEINx
AMUTEx
Clock Check and
Error Detection
DIT RAM
384 C
384 U
AFSXx
ACLKXx
AHCLKXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Transmit Logic
Clock/Frame Generator
State Machine
Optional
Transmit
Formatter
Serializer 0
Serializer 1
AXRx[0]
AXRx[1]
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
McASP
DMA Bus
(Dedicated)
Receive
Formatter
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1, 2)
Figure 4-25. McASP Block Diagram
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The three McASPs on C672x have different configurations (see Table 4-17). NOTE: McASP2 is not
available on the C6722.
Table 4-17. McASP Configurations on C672x DSP
McASP
McASP0
DIT
No
CLOCK PINS
DATA PINS
Up to 16
COMMENTS
AHCLKX0/AHCLKX2, ACLKX0, AFSX0
AHCLKR0/AHCLKR1, ACLKR0, AFSR0
AHCLKX0/AHCLKX2 share pin.
AHCLKR0/AHCLKR1 share pin.
McASP1
McASP2
No
AHCLKX1, ACLKX1, AFSX1, ACLKR1, AFSR1
Up to 6
Up to 2
AHCLKR0/AHCLKR1 share pin
Yes
ACLKX2, AFSX2, AHCLKR2, ACLKR2, AFSR2
(Only available on the C6727.)
Full functionality on C6727. On C6726,
functions only as DIT since only
AHCLKX0/AHCLKX2 is available.
Not available on the C6722.
NOTE: The McASPs do not have dedicated AMUTEINx pins. Instead they can select one of the pins
listed in Table 4-19, Table 4-20, and Table 4-21 to use as a mute input.
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4.13.1 McASP Peripheral Registers Description(s)
Table 4-18 is a list of the McASP registers. For more information about these registers, see the
TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU878).
Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
McASP2
BYTE
ADDRESS
REGISTER
NAME
DESCRIPTION
Device-Level Configuration Registers Controlling McASP
0x4000 0018
0x4000 001C
0x4000 0020
CFGMCASPx
Selects the peripheral pin to be used as AMUTEINx
McASP Internal Registers
0x4400 0000
0x4400 0004
0x4400 0010
0x4400 0014
0x4400 0018
0x4400 001C
0x4500 0000
0x4500 0004
0x4500 0010
0x4500 0014
0x4500 0018
0x4500 001C
0x4600 0000
0x4600 0004
0x4600 0010
0x4600 0014
0x4600 0018
0x4600 001C
PID
Peripheral identification register
PWRDEMU
PFUNC
Power down and emulation management register
Pin function register
PDIR
Pin direction register
PDOUT
Pin data output register
PDIN (reads)
PDSET (writes)
Read returns: Pin data input register
Writes affect: Pin data set register
(alternate write address: PDOUT)
0x4400 0020
0x4400 0044
0x4400 0048
0x4400 004C
0x4400 0050
0x4400 0060
0x4500 0020
0x4500 0044
0x4500 0048
0x4500 004C
0x4500 0050
0x4500 0060
0x4600 0020
0x4600 0044
0x4600 0048
0x4600 004C
0x4600 0050
0x4600 0060
PDCLR
Pin data clear register (alternate write address: PDOUT)
Global control register
GBLCTL
AMUTE
DLBCTL
DITCTL
RGBLCTL
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only
receive bits are affected - allows receiver to be reset
independently from transmitter
0x4400 0064
0x4400 0068
0x4400 006C
0x4400 0070
0x4400 0074
0x4400 0078
0x4400 007C
0x4400 0080
0x4400 0084
0x4400 0088
0x4400 008C
0x4400 00A0
0x4500 0064
0x4500 0068
0x4500 006C
0x4500 0070
0x4500 0074
0x4500 0078
0x4500 007C
0x4500 0080
0x4500 0084
0x4500 0088
0x4500 008C
0x4500 00A0
0x4600 0064
0x4600 0068
0x4600 006C
0x4600 0070
0x4600 0074
0x4600 0078
0x4600 007C
0x4600 0080
0x4600 0084
0x4600 0088
0x4600 008C
0x4600 00A0
RMASK
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
RFMT
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
Receive high-frequency clock control register
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
RINTCTL
RSTAT
RSLOT
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
RCLKCHK
REVTCTL
XGBLCTL
Transmitter global control register. Alias of GBLCTL, only
transmit bits are affected - allows transmitter to be reset
independently from receiver
0x4400 00A4
0x4400 00A8
0x4400 00AC
0x4400 00B0
0x4400 00B4
0x4400 00B8
0x4400 00BC
0x4400 00C0
0x4400 00C4
0x4500 00A4
0x4500 00A8
0x4500 00AC
0x4500 00B0
0x4500 00B4
0x4500 00B8
0x4500 00BC
0x4500 00C0
0x4500 00C4
0x4600 00A4
0x4600 00A8
0x4600 00AC
0x4600 00B0
0x4600 00B4
0x4600 00B8
0x4600 00BC
0x4600 00C0
0x4600 00C4
XMASK
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
XFMT
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
XINTCTL
XSTAT
XSLOT
Current transmit TDM time slot register
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Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued)
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
McASP2
BYTE
ADDRESS
REGISTER
NAME
DESCRIPTION
0x4400 00C8
0x4500 00C8
0x4600 00C8
0x4600 00CC
0x4600 0100
0x4600 0104
0x4600 0108
0x4600 010C
0x4600 0110
0x4600 0114
0x4600 0118
0x4600 011C
0x4600 0120
0x4600 0124
0x4600 0128
0x4600 012C
0x4600 0130
0x4600 0134
0x4600 0138
0x4600 013C
0x4600 0140
0x4600 0144
0x4600 0148
0x4600 014C
0x4600 0150
0x4600 0154
0x4600 0158
0x4600 015C
0x4600 0180
0x4600 0184
–
XCLKCHK
Transmit clock check control register
Transmitter DMA event control register
Left channel status register 0
Left channel status register 1
Left channel status register 2
Left channel status register 3
Left channel status register 4
Left channel status register 5
Right channel status register 0
Right channel status register 1
Right channel status register 2
Right channel status register 3
Right channel status register 4
Right channel status register 5
Left channel user data register 0
Left channel user data register 1
Left channel user data register 2
Left channel user data register 3
Left channel user data register 4
Left channel user data register 5
Right channel user data register 0
Right channel user data register 1
Right channel user data register 2
Right channel user data register 3
Right channel user data register 4
Right channel user data register 5
Serializer control register 0
0x4400 00CC
0x4500 00CC
XEVTCTL
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
SRCTL0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x4400 0180
0x4400 0184
0x4400 0188
0x4400 018C
0x4400 0190
0x4400 0194
0x4400 0198
0x4400 019C
0x4400 01A0
0x4400 01A4
0x4400 01A8
0x4400 01AC
0x4400 01B0
0x4400 01B4
0x4400 01B8
0x4400 01BC
0x4400 0200
0x4400 0204
0x4400 0208
0x4500 0180
0x4500 0184
SRCTL1
Serializer control register 1
0x4500 0188
SRCTL2
Serializer control register 2
0x4500 018C
–
SRCTL3
Serializer control register 3
0x4500 0190
–
SRCTL4
Serializer control register 4
0x4500 0194
–
SRCTL5
Serializer control register 5
–
–
SRCTL6
Serializer control register 6
–
–
SRCTL7
Serializer control register 7
–
–
SRCTL8
Serializer control register 8
–
–
SRCTL9
Serializer control register 9
–
–
SRCTL10
SRCTL11
SRCTL12
SRCTL13
SRCTL14
SRCTL15
XBUF0(1)
XBUF1(1)
XBUF2(1)
Serializer control register 10
Serializer control register 11
Serializer control register 12
Serializer control register 13
Serializer control register 14
Serializer control register 15
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
–
–
–
–
–
–
–
–
–
–
0x4500 0200
0x4500 0204
0x4500 0208
0x4600 0200
0x4600 0204
–
(1) Writes to XRBUF originate from peripheral configuration bus only when XBUSEL = 1 in XFMT.
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Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus (continued)
McASP0
BYTE
ADDRESS
McASP1
BYTE
ADDRESS
McASP2
BYTE
ADDRESS
REGISTER
NAME
DESCRIPTION
0x4400 020C
0x4400 0210
0x4400 0214
0x4400 0218
0x4400 021C
0x4400 0220
0x4400 0224
0x4400 0228
0x4400 022C
0x4400 0230
0x4400 0234
0x4400 0238
0x4400 023C
0x4400 0280
0x4400 0284
0x4400 0288
0x4400 028C
0x4400 0290
0x4400 0294
0x4400 0298
0x4400 029C
0x4400 02A0
0x4400 02A4
0x4400 02A8
0x4400 02AC
0x4400 02B0
0x4400 02B4
0x4400 02B8
0x4400 02BC
0x4500 020C
–
XBUF3(1)
Transmit buffer register for serializer 3
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
Transmit buffer register for serializer 8
Transmit buffer register for serializer 9
Transmit buffer register for serializer 10
Transmit buffer register for serializer 11
Transmit buffer register for serializer 12
Transmit buffer register for serializer 13
Transmit buffer register for serializer 14
Transmit buffer register for serializer 15
Receive buffer register for serializer 0
Receive buffer register for serializer 1
Receive buffer register for serializer 2
Receive buffer register for serializer 3
Receive buffer register for serializer 4
Receive buffer register for serializer 5
Receive buffer register for serializer 6
Receive buffer register for serializer 7
Receive buffer register for serializer 8
Receive buffer register for serializer 9
Receive buffer register for serializer 10
Receive buffer register for serializer 11
Receive buffer register for serializer 12
Receive buffer register for serializer 13
Receive buffer register for serializer 14
Receive buffer register for serializer 15
0x4500 0210
–
XBUF4(1)
XBUF5(1)
XBUF6(1)
XBUF7(1)
XBUF8(1)
XBUF9(1)
XBUF10(1)
XBUF11(1)
XBUF12(1)
XBUF13(1)
XBUF14(1)
XBUF15(1)
RBUF0(2)
RBUF1(2)
RBUF2(2)
RBUF3(2)
RBUF4(2)
RBUF5(2)
RBUF6(2)
RBUF7(2)
RBUF8(2)
RBUF9(2)
RBUF10(2)
RBUF11(2)
RBUF12(2)
RBUF13(2)
RBUF14(2)
RBUF15(2)
0x4500 0214
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x4500 0280
0x4600 0280
0x4500 0284
0x4600 0284
0x4500 0288
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0x4500 028C
0x4500 0290
0x4500 0294
–
–
–
–
–
–
–
–
–
–
(2) Reads from XRBUF originate on peripheral configuration bus only when RBUSEL = 1 in RFMT.
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Figure 4-26 shows the bit layout of the CFGMCASP0 register and Table 4-19 contains a description of the
bits.
31
8
Reserved
7
3
2
0
Reserved
AMUTEIN0
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-26. CFGMCASP0 Register Bit Layout (0x4000 0018)
Table 4-19. CFGMCASP0 Register Bit Field Description (0x4000 0018)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
DESCRIPTION
31:3
2:0
Reserved
AMUTEIN0
N/A
0
N/A
Reads are indeterminate. Only 0s should be written to these bits.
R/W
AMUTEIN0 Selects the source of the input to the McASP0 mute input.
000 = Select the input to be a constant '0'
001 = Select the input from AXR0[7]/SPI1_CLK
010 = Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI
011 = Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO
100 = Select the input from AHCLKR2
101 = Select the input from SPI0_SIMO
110 = Select the input from SPI0_SCS/I2C1_SCL
111 = Select the input from SPI0_ENA/I2C1_SDA
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Figure 4-27 shows the bit layout of the CFGMCASP1 register and Table 4-20 contains a description of the
bits.
31
8
Reserved
7
3
2
0
Reserved
AMUTEIN1
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-27. CFGMCASP1 Register Bit Layout (0x4000 001C)
Table 4-20. CFGMCASP1 Register Bit Field Description (0x4000 001C)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
DESCRIPTION
31:3
2:0
Reserved
AMUTEIN1
N/A
0
N/A
Reads are indeterminate. Only 0s should be written to these bits.
R/W
AMUTEIN1 Selects the source of the input to the McASP1 mute input.
000 = Select the input to be a constant '0'
001 = Select the input from AXR0[7]/SPI1_CLK
010 = Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI
011 = Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO
100 = Select the input from AHCLKR2
101 = Select the input from SPI0_SIMO
110 = Select the input from SPI0_SCS/I2C1_SCL
111 = Select the input from SPI0_ENA/I2C1_SDA
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Figure 4-28 shows the bit layout of the CFGMCASP2 register and Table 4-21 contains a description of the
bits.
31
8
Reserved
7
3
2
0
Reserved
AMUTEIN2
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-28. CFGMCASP2 Register Bit Layout (0x4000 0020)
Table 4-21. CFGMCASP2 Register Bit Field Description (0x4000 0020)(1)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
DESCRIPTION
31:3
2:0
Reserved
AMUTEIN2
N/A
0
N/A
Reads are indeterminate. Only 0s should be written to these bits.
R/W
AMUTEIN2 Selects the source of the input to the McASP2 mute input.
000 = Select the input to be a constant '0'
001 = Select the input from AXR0[7]/SPI1_CLK
010 = Select the input from AXR0[8]/AXR1[5]/SPI1_SOMI
011 = Select the input from AXR0[9]/AXR1[4]/SPI1_SIMO
100 = Select the input from AHCLKR2
101 = Select the input from SPI0_SIMO
110 = Select the input from SPI0_SCS/I2C1_SCL
111 = Select the input from SPI0_ENA/I2C1_SDA
(1) CFGMCASP2 is reserved on the C6722.
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4.13.2 McASP Electrical Data/Timing
4.13.2.1 Multichannel Audio Serial Port (McASP) Timing
Table 4-22 and Table 4-23 assume testing over recommended operating conditions (see Figure 4-29 and
Figure 4-30).
Table 4-22. McASP Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR external, AHCLKR input
Cycle time, AHCLKX external, AHCLKX input
Pulse duration, AHCLKR external, AHCLKR input
Pulse duration, AHCLKX external, AHCLKX input
Cycle time, ACLKR external, ACLKR input
20
1
tc(AHCKRX)
tw(AHCKRX)
tc(ACKRX)
tw(ACKRX)
ns
20
7.5
2
3
4
ns
ns
ns
7.5
greater of 2P or 20 ns
Cycle time, ACLKX external, ACLKX input
greater of 2P or 20 ns
Pulse duration, ACLKR external, ACLKR input
Pulse duration, ACLKX external, ACLKX input
Setup time, AFSR input to ACLKR internal
10
10
8
8
3
3
3
3
0
0
3
3
3
3
8
3
3
3
3
3
Setup time, AFSX input to ACLKX internal
Setup time, AFSR input to ACLKR external input
Setup time, AFSX input to ACLKX external input
Setup time, AFSR input to ACLKR external output
Setup time, AFSX input to ACLKX external output
Hold time, AFSR input after ACLKR internal
Hold time, AFSX input after ACLKX internal
Hold time, AFSR input after ACLKR external input
Hold time, AFSX input after ACLKX external input
Hold time, AFSR input after ACLKR external output
Hold time, AFSX input after ACLKX external output
Setup time, AXRn input to ACLKR internal
5
6
tsu(AFRXC-ACKRX)
ns
ns
th(ACKRX-AFRX)
7
8
tsu(AXR-ACKRX)
Setup time, AXRn input to ACLKR external input
Setup time, AXRn input to ACLKR external output
Hold time, AXRn input after ACLKR internal
Hold time, AXRn input after ACLKR external input
Hold time, AXRn input after ACLKR external output
ns
ns
th(ACKRX-AXR)
(1) ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
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Table 4-23. McASP Switching Characteristics(1)
NO.
PARAMETER
MIN
20
MAX
UNIT
Cycle time, AHCLKR internal, AHCLKR output
Cycle time, AHCLKR external, AHCLKR output
Cycle time, AHCLKX internal, AHCLKX output
Cycle time, AHCLKX external, AHCLKX output
Pulse duration, AHCLKR internal, AHCLKR output
Pulse duration, AHCLKR external, AHCLKR output
Pulse duration, AHCLKX internal, AHCLKX output
Pulse duration, AHCLKX external, AHCLKX output
Cycle time, ACLKR internal, ACLKR output
Cycle time, ACLKR external, ACLKR output
Cycle time, ACLKX internal, ACLKX output
Cycle time, ACLKX external, ACLKX output
Pulse duration, ACLKR internal, ACLKR output
Pulse duration, ACLKR external, ACLKR output
Pulse duration, ACLKX internal, ACLKX output
Pulse duration, ACLKX external, ACLKX output
Delay time, ACLKR internal, AFSR output
20
9
tc(AHCKRX)
tw(AHCKRX)
tc(ACKRX)
tw(ACKRX)
ns
20
20
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
10
11
12
ns
ns
ns
5
5
Delay time, ACLKX internal, AFSX output
Delay time, ACLKR external input, AFSR output
Delay time, ACLKX external input, AFSX output
Delay time, ACLKR external output, AFSR output
Delay time, ACLKX external output, AFSX output
Delay time, ACLKR internal, AFSR output
10
10
10
10
13
td(ACKRX-FRX)
ns
–1
–1
0
Delay time, ACLKX internal, AFSX output
Delay time, ACLKR external input, AFSR output
Delay time, ACLKX external input, AFSX output
Delay time, ACLKR external output, AFSR output
Delay time, ACLKX external output, AFSX output
Delay time, ACLKX internal, AXRn output
0
0
0
–1
0
5
10
10
10
10
10
14
15
td(ACLKX-AXRV)
Delay time, ACLKX external input, AXRn output
Delay time, ACLKX external output, AXRn output
Disable time, ACLKX internal, AXRn output
Disable time, ACLKX external input, AXRn output
Disable time, ACLKX external output, AXRn output
ns
ns
0
–3
–3
–3
tdis(ACKX-AXRHZ)
(1) ACLKX internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR internal – ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR.
(3) AHX - Cycle time, AHCLKX.
(4) P = SYSCLK2 period
(5) AR - ACLKR period.
(6) AX - ACLKX period.
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 4-29. McASP Input Timings
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 4-30. McASP Output Timings
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4.14 Serial Peripheral Interface Ports (SPI0, SPI1)
4.14.1 SPI Device-Specific Information
Figure 4-31 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
Configuration Bus
16-Bit Shift Register
SPIx_ENA
SPIx_SCS
SPIx_CLK
State
Machine
GPIO
Control
(all pins)
Interrupt and
DMA Requests
16-Bit Buffer
Clock
Control
16-Bit Emulation Buffer
C672x SPI Module
Figure 4-31. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The C672x will only shift data and drive the SPIx_SOMI pin
when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
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Optional − Slave Chip Select
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
Optional Enable (Ready)
MASTER SPI
SLAVE SPI
Figure 4-32. Illustration of SPI Master-to-SPI Slave Connection
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4.14.2 SPI Peripheral Registers Description(s)
Table 4-24 is a list of the SPI registers.
Table 4-24. SPIx Configuration Registers
SPI0
BYTE ADDRESS
SPI1
REGISTER NAME
DESCRIPTION
Global Control Register 0
BYTE ADDRESS
0x4800 0000
0x4800 0004
0x4800 0008
0x4800 000C
0x4800 0010
0x4800 0014
0x4800 0018
0x4800 001C
0x4800 0020
0x4800 0024
0x4800 0028
0x4800 002C
0x4800 0030
0x4800 0034
0x4800 0038
0x4800 003C
0x4800 0040
0x4800 0044
0x4800 0048
0x4800 004C
0x4800 0050
0x4800 0054
0x4800 0058
0x4800 005C
0x4800 0060
0x4800 0064
0x4700 0000
0x4700 0004
0x4700 0008
0x4700 000C
0x4700 0010
0x4700 0014
0x4700 0018
0x4700 001C
0x4700 0020
0x4700 0024
0x4700 0028
0x4700 002C
0x4700 0030
0x4700 0034
0x4700 0038
0x4700 003C
0x4700 0040
0x4700 0044
0x4700 0048
0x4700 004C
0x4700 0050
0x4700 0054
0x4700 0058
0x4700 005C
0x4700 0060
0x4700 0064
SPIGCR0
SPIGCR1
SPIINT0
SPILVL
Global Control Register 1
Interrupt Register
Interrupt Level Register
SPIFLG
Flag Register
SPIPC0
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Pin Control Register 3 (Pin Data Out)
Pin Control Register 4 (Pin Data Set)
Pin Control Register 5 (Pin Data Clear)
Reserved - Do not write to this register
Reserved - Do not write to this register
Reserved - Do not write to this register
Shift Register 0 (without format select)
Shift Register 1 (with format select)
Buffer Register
SPIPC1
SPIPC2
SPIPC3
SPIPC4
SPIPC5
Reserved
Reserved
Reserved
SPIDAT0
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
Emulation Register
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
TGINTVECT0
TGINTVECT1
Format Register 1
Format Register 2
Format Register 3
Interrupt Vector for SPI INT0
Interrupt Vector for SPI INT1
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4.14.3 SPI Electrical Data/Timing
4.14.3.1 Serial Peripheral Interface (SPI) Timing
Table 4-25 through Table 4-32 assume testing over recommended operating conditions (see Figure 4-33
through Figure 4-36).
Table 4-25. General Timing Requirements for SPIx Master Modes(1)
NO.
MIN
MAX UNIT
greater of 8P or
100 ns
1
tc(SPC)M
Cycle Time, SPIx_CLK, All Master Modes
256P ns
2
3
tw(SPCH)M
tw(SPCL)M
Pulse Width High, SPIx_CLK, All Master Modes
Pulse Width Low, SPIx_CLK, All Master Modes
greater of 4P or 45 ns
greater of 4P or 45 ns
ns
ns
Polarity = 0, Phase = 0,
to SPIx_CLK rising
4P
0.5tc(SPC)M + 4P
4P
Polarity = 0, Phase = 1,
Delay, initial data bit valid
to SPIx_CLK rising
4
5
6
7
8
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
on SPIx_SIMO to initial
ns
edge on SPIx_CLK(2)
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5tc(SPC)M + 4P
Polarity = 0, Phase = 0,
from SPIx_CLK rising
15
Polarity = 0, Phase = 1,
from SPIx_CLK falling
15
ns
15
Delay, subsequent bits
valid on SPIx_SIMO after
transmit edge of SPIx_CLK
Polarity = 1, Phase = 0,
from SPIx_CLK falling
Polarity = 1, Phase = 1,
from SPIx_CLK rising
15
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5P + 15
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Output hold time,
SPIx_SIMO valid after
receive edge of SPIxCLK,
except for final bit(3)
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Polarity = 0, Phase = 1,
to SPIx_CLK rising
0.5P + 15
Input Setup Time,
SPIx_SOMI valid before
receive edge of SPIx_CLK
ns
Polarity = 1, Phase = 0,
to SPIx_CLK rising
0.5P + 15
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5P + 15
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5P + 5
Polarity = 0, Phase = 1,
from SPIx_CLK rising
0.5P + 5
Input Hold Time,
SPIx_SOMI valid after
receive edge of SPIx_CLK
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
0.5P + 5
Polarity = 1, Phase = 1,
from SPIx_CLK falling
0.5P + 5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.
(3) The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.
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Table 4-26. General Timing Requirements for SPIx Slave Modes(1)
NO.
MIN
MAX UNIT
greater of 8P or
100 ns
9
tc(SPC)S
Cycle Time, SPIx_CLK, All Slave Modes
Pulse Width High, SPIx_CLK, All Slave Modes
Pulse Width Low, SPIx_CLK, All Slave Modes
256P ns
greater of 4P or
45 ns
10 tw(SPCH)S
11 tw(SPCL)S
ns
ns
greater of 4P or
45 ns
Polarity = 0, Phase = 0,
to SPIx_CLK rising
2P
2P
2P
2P
Setup time, transmit data
written to SPI and output
onto SPIx_SOMI pin before
initial clock edge from
master.(2)(3)
Polarity = 0, Phase = 1,
to SPIx_CLK rising
12 tsu(SOMI_SPC)S
13 td(SPC_SOMI)S
14 toh(SPC_SOMI)S
15 tsu(SIMO_SPC)S
ns
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK rising
2P + 15
Polarity = 0, Phase = 1,
from SPIx_CLK falling
2P + 15
ns
Delay, subsequent bits
valid on SPIx_SOMI after
transmit edge of SPIx_CLK
Polarity = 1, Phase = 0,
from SPIx_CLK falling
2P + 15
Polarity = 1, Phase = 1,
from SPIx_CLK rising
2P + 15
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5tc(SPC)S – 10
0.5P + 15
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Output hold time,
SPIx_SOMI valid after
receive edge of SPIxCLK,
except for final bit(4)
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Polarity = 0, Phase = 1,
to SPIx_CLK rising
0.5P + 15
Input Setup Time,
SPIx_SIMO valid before
receive edge of SPIx_CLK
ns
Polarity = 1, Phase = 0,
to SPIx_CLK rising
0.5P + 15
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5P + 15
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5P + 5
Polarity = 0, Phase = 1,
from SPIx_CLK rising
0.5P + 5
Input Hold Time,
SPIx_SIMO valid after
receive edge of SPIx_CLK
16 tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
0.5P + 5
Polarity = 1, Phase = 1,
from SPIx_CLK falling
0.5P + 5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPIx_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPIx_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, as evidenced by new output data appearing on the
SPIx_SOMI pin. In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to
the SPI module by either the DSP CPU or the dMAX.
(4) The final data bit will be held on the SPIx_SOMI pin until the SPIDAT0 or SPIDAT1 register is written with new data.
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Table 4-27. Additional(1) SPI Master Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
3P + 15
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
0.5tc(SPC)M + 3P + 15
Delay from slave assertion of
SPIx_ENA active to first
SPIx_CLK from master.(4)
17 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPIx_CLK falling
3P + 15
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5tc(SPC)M + 3P + 15
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Max delay for slave to deassert
SPIx_ENA after final SPIx_CLK
edge to ensure master does not
begin the next transfer.(5)
0
0.5tc(SPC)M
0
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-25).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPIx_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPIx_ENA deassertion.
Table 4-28. Additional(1) SPI Master Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPIx_CLK rising
2P – 10
Polarity = 0, Phase = 1,
to SPIx_CLK rising
0.5tc(SPC)M + 2P – 10
Delay from SPIx_SCS active to
first SPIx_CLK(4)(5)
19 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPIx_CLK falling
2P – 10
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5tc(SPC)M + 2P – 10
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPIx_CLK falling
0
0.5tc(SPC)M
0
Delay from final SPIx_CLK edge
to master deasserting
SPIx_SCS(6)(7)
20 td(SPC_SCS)M
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-25).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPIx_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 4-29. Additional(1) SPI Master Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M
Max delay for slave to
deassert SPIx_ENA after
final SPIx_CLK edge to
ensure master does not
begin the next
Polarity = 0, Phase = 1,
from SPIx_CLK falling
0
0.5tc(SPC)M
0
18 td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
transfer.(4)
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Delay from final
SPIx_CLK edge to
master deasserting
SPIx_SCS(5)(6)
0
0.5tc(SPC)M
0
20 td(SPC_SCS)M
21 td(SCSL_ENAL)M
22 td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Max delay for slave SPI to drive SPIx_ENA valid
after master asserts SPIx_SCS to delay the
master from beginning the next transfer.
0.5P ns
Polarity = 0, Phase = 0,
to SPIx_CLK rising
2P – 10
0.5tc(SPC)M + 2P – 10
2P – 10
Polarity = 0, Phase = 1,
Delay from SPIx_SCS
to SPIx_CLK rising
active to first
ns
SPIx_CLK(7)(8)(9)
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5tc(SPC)M + 2P – 10
Polarity = 0, Phase = 0,
to SPIx_CLK rising
3P + 15
Polarity = 0, Phase = 1,
to SPIx_CLK rising
0.5tc(SPC)M + 3P + 15
3P + 15
Delay from assertion of
SPIx_ENA low to first
SPIx_CLK edge.(10)
23 td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
0.5tc(SPC)M + 3P + 15
(1) These parameters are in addition to the general timings for SPI master modes (Table 4-25).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPIx_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPIx_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPIx_ENA is asserted immediately such that the transmission is not delayed by SPIx_ENA.
(8) In the case where the master SPI is ready with new data before SPIx_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPIx_ENA was initially deasserted high and SPIx_CLK is delayed.
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Table 4-30. Additional(1) SPI Slave Timings, 4-Pin Enable Option(2)(3)
NO.
MIN
MAX UNIT
3P + 15
Polarity = 0, Phase = 0,
from SPIx_CLK falling
P – 10
0.5tc(SPC)M + P – 10
P – 10
Polarity = 0, Phase = 1,
from SPIx_CLK falling
0.5tc(SPC)M + 3P + 15
3P + 15
Delay from final
24 td(SPC_ENAH)S SPIx_CLK edge to slave
deasserting SPIx_ENA.
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
0.5tc(SPC)M + P – 10
0.5tc(SPC)M + 3P + 15
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-26).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 4-31. Additional(1) SPI Slave Timings, 4-Pin Chip Select Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPIx_SCS asserted at slave to first
SPIx_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M + P + 10
P + 10
Polarity = 0, Phase = 1,
Required delay from final
from SPIx_CLK falling
26
td(SPC_SCSH)S
SPIx_CLK edge before
ns
Polarity = 1, Phase = 0,
SPIx_SCS is deasserted.
0.5tc(SPC)M + P + 10
P + 10
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Delay from master asserting SPIx_SCS to slave driving
SPIx_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 15
P + 15
ns
ns
Delay from master deasserting SPIx_SCS to slave 3-stating
SPIx_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-26).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 4-32. Additional(1) SPI Slave Timings, 5-Pin Option(2)(3)
NO.
MIN
MAX UNIT
Required delay from SPIx_SCS asserted at slave to first
SPIx_CLK edge at slave.
25
td(SCSL_SPC)S
P
ns
Polarity = 0, Phase = 0,
from SPIx_CLK falling
0.5tc(SPC)M + P + 10
P + 10
Polarity = 0, Phase = 1,
Required delay from final
from SPIx_CLK falling
26
td(SPC_SCSH)S
SPIx_CLK edge before
ns
Polarity = 1, Phase = 0,
SPIx_SCS is deasserted.
0.5tc(SPC)M + P + 10
P + 10
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Delay from master asserting SPIx_SCS to slave driving
SPIx_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 10
P + 10
15
ns
ns
ns
Delay from master deasserting SPIx_SCS to slave 3-stating
SPIx_SOMI
Delay from master deasserting SPIx_SCS to slave driving
SPIx_ENA valid
Polarity = 0, Phase = 0,
from SPIx_CLK falling
2P + 15
2P + 15
2P + 15
2P + 15
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Delay from final clock receive
edge on SPIx_CLK to slave
3-stating or driving high
SPIx_ENA.(4)
30
tdis(SPC_ENA)S
ns
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 4-26).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPIx_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPIx_CLK
5
4
6
SPI_SIMO
SPI_SOMI
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
SPI_SIMO
SPI_SOMI
6
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
SPI_SIMO
SPI_SOMI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
SPI_SIMO
SPI_SOMI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 4-33. SPI Timings—Master Mode
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9
SLAVE MODE
POLARITY = 0 PHASE = 0
12
10
15
11
SPIx_CLK
SPI_SIMO
SPI_SOMI
16
SI(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(0)
SO(1)
SO(n−1)
SO(n)
12
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
SPI_SIMO
SPI_SOMI
15
SI(0)
16
SI(1)
SI(n−1)
SI(n)
13
14
SO(0)
SO(1)
SO(n−1)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 0
12
SPIx_CLK
SPI_SIMO
SPI_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(n−1)
SO(0)
SO(n)
SLAVE MODE
POLARITY = 1 PHASE = 1
12
SPIx_CLK
SPI_SIMO
SPI_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
14
SO(0)
SO(1)
SO(n−1)
SO(n)
Figure 4-34. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPI_SIMO
SPI_SOMI
SPIx_ENA
MO(0)
MI(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPI_SIMO
SPI_SOMI
SPIx_SCS
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
MASTER MODE 5 PIN
23
22
20
MO(1)
18
SPIx_CLK
SPI_SIMO
SPI_SOMI
MO(0)
MO(n−1)
MO(n)
MI(0)
MI(1)
MI(n−1)
MI(n)
21
(A)
(A)
SPIx_ENA
SPIx_SCS
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 4-35. SPI Timings—Master Mode (4-Pin and 5-Pin)
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SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPI_SOMI
SPI_SIMO
SPIx_ENA
SO(0)
SI(0)
SO(1)
SO(n−1) SO(n)
SI(n−1) SI(n)
SI(1)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPIx_CLK
27
28
SO(n−1)
SPI_SOMI
SPI_SIMO
SPIx_SCS
SO(0)
SO(1)
SO(n)
SI(0)
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
25
26
30
SPIx_CLK
27
29
28
SO(1)
SPI_SOMI
SPI_SIMO
SO(0)
SI(0)
SO(n−1)
SO(n)
SI(1)
SI(n−1) SI(n)
SPIx_ENA
SPIx_SCS
(A)
(A)
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 4-36. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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4.15 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
4.15.1 I2C Device-Specific Information
Having two I2C modules on the C672x simplifies system architecture, since one module may be used by
the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate
with other controllers in a system or to implement a user interface. Figure 4-37 is block diagram of the
C672x I2C Module.
Each I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
CAUTION
The C672x I2C pins use a standard ±8 mA LVCMOS buffer, not the slow I/O buffer
defined in the I2C specification. Series resistors may be necessary to reduce noise at
the system level.
C672x I2C Module
Clock Prescaler
I2CPSCx
Control
I2CCOARx
Prescaler
Register
Own Address
Register
Slave Address
Register
I2CSARx
Bit Clock Generator
I2CCLKHx
Noise
Filter
I2Cx_SCL
Clock Divide
High Register
I2CCMDRx
I2CEMDRx
I2CCNTx
I2CPID1
Mode Register
Extended Mode
Register
Clock Divide
Low Register
I2CCLKLx
Data Count
Register
Peripheral
Configuration
Bus
Transmit
I2CXSRx
Peripheral ID
Register 1
Transmit Shift
Register
Peripheral ID
Register 2
I2CPID2
I2CDXRx
Transmit Buffer
Noise
Filter
I2Cx_SDA
Interrupt/DMA
Interrupt Enable
Register
Receive
I2CIERx
Interrupt DMA
Requests
Receive Buffer
I2CDRRx
Interrupt Status
Register
I2CSTRx
I2CSRCx
Receive Shift
Register
Interrupt Source
Register
I2CRSRx
Control
Pin Function
Register
Pin Data Out
Register
I2CPDOUT
I2CPFUNC
Pin Direction
Register
Pin Data In
Register
Pin Data Set
Register
Pin Data Clear
Register
I2CPDIR
I2CPDIN
I2CPDSET
I2CPDCLR
Figure 4-37. I2C Module Block Diagram
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4.15.2 I2C Peripheral Registers Description(s)
Table 4-33 is a list of the I2C registers.
Table 4-33. I2Cx Configuration Registers
I2C0
BYTE ADDRESS
I2C1
REGISTER NAME
DESCRIPTION
BYTE ADDRESS
0x4A00 0000
0x4A00 0004
0x4A00 0008
0x4A00 000C
0x4A00 0010
0x4A00 0014
0x4A00 0018
0x4A00 001C
0x4A00 0020
0x4A00 0024
0x4A00 0028
0x4A00 002C
0x4A00 0030
0x4A00 0034
0x4A00 0038
0x4A00 0048
0x4A00 004C
0x4A00 0050
0x4A00 0054
0x4A00 0058
0x4A00 005C
0x4900 0000
0x4900 0004
0x4900 0008
0x4900 000C
0x4900 0010
0x4900 0014
0x4900 0018
0x4900 001C
0x4900 0020
0x4900 0024
0x4900 0028
0x4900 002C
0x4900 0030
0x4900 0034
0x4900 0038
0x4900 0048
0x4900 004C
0x4900 0050
0x4900 0054
0x4900 0058
0x4900 005C
I2COAR
I2CIER
Own Address Register
Interrupt Enable Register
Interrupt Status Register
Clock Low Time Divider Register
Clock High Time Divider Register
Data Count Register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
Data Receive Register
Slave Address Register
Data Transmit Register
Mode Register
I2CDXR
I2CMDR
I2CISR
Interrupt Source Register
Extended Mode Register
Prescale Register
I2CEMDR
I2CPSC
I2CPID1
I2CPID2
I2CPFUNC
I2CPDIR
I2CPDIN
I2CPDOUT
I2CPDSET
I2CPDCLR
Peripheral Identification Register 1
Peripheral Identification Register 2
Pin Function Register
Pin Direction Register
Pin Data Input Register
Pin Data Output Register
Pin Data Set Register
Pin Data Clear Register
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4.15.3 I2C Electrical Data/Timing
4.15.3.1 Inter-Integrated Circuit (I2C) Timing
Table 4-34 and Table 4-35 assume testing over recommended operating conditions (see Figure 4-38 and
Figure 4-39).
Table 4-34. I2C Input Timing Requirements
NO.
MIN
10
MAX UNIT
Standard Mode
Fast Mode
1
tc(SCL)
Cycle time, I2Cx_SCL
µs
2.5
4.7
0.6
4
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
2
3
tsu(SCLH-SDAL)
th(SCLL-SDAL)
tw(SCLL)
µs
µs
µs
µs
ns
Standard Mode
Fast Mode
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
Pulse duration, I2Cx_SCL high
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Rise time, I2Cx_SDA
0.6
4.7
1.3
4
Standard Mode
Fast Mode
4
Standard Mode
Fast Mode
5
tw(SCLH)
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
tr(SDA)
0.6
250
100
0
Standard Mode
Fast Mode
6
Standard Mode
Fast Mode
7
µs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
8
µs
Standard Mode
Fast Mode
1000
ns
9
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
300
Standard Mode
Fast Mode
1000
ns
10
11
12
13
14
15
tr(SCL)
Rise time, I2Cx_SCL
300
Standard Mode
Fast Mode
300
ns
tf(SDA)
Fall time, I2Cx_SDA
300
Standard Mode
Fast Mode
300
ns
tf(SCL)
Fall time, I2Cx_SCL
20 + 0.1Cb
300
Standard Mode
Fast Mode
4
0.6
N/A
0
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
µs
Standard Mode
Fast Mode
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
ns
50
Standard Mode
Fast Mode
400
pF
Cb
400
Table 4-35. I2C Switching Characteristics(1)
NO.
PARAMETER
MIN
10
MAX UNIT
Standard Mode
16
tc(SCL)
Cycle time, I2Cx_SCL
µs
Fast Mode
2.5
4.7
0.6
4
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
17
18
tsu(SCLH-SDAL)
µs
µs
Standard Mode
Fast Mode
th(SDAL-SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
0.6
(1) I2C must be configured correctly to meet the timings in Table 4-35.
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Table 4-35. I2C Switching Characteristics (continued)
NO.
PARAMETER
MIN
4.7
1.3
4
MAX UNIT
Standard Mode
Fast Mode
19
tw(SCLL)
Pulse duration, I2Cx_SCL low
Pulse duration, I2Cx_SCL high
µs
Standard Mode
Fast Mode
20
21
22
23
28
29
tw(SCLH)
µs
0.6
250
100
0
Standard Mode
Fast Mode
Setup time, I2Cx_SDA valid before I2Cx_SCL
high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
ns
Standard Mode
Fast Mode
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
µs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
4
µs
µs
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
0.6
Standard Mode
Fast Mode
10
pF
10
Capacitive load on each bus line from this
device
Cb
11
9
I2Cx_SDA
I2Cx_SCL
6
8
14
4
13
5
10
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 4-38. I2C Receive Timings
26
24
I2Cx_SDA
I2Cx_SCL
21
23
19
28
20
25
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 4-39. I2C Transmit Timings
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4.16 Real-Time Interrupt (RTI) Timer With Digital Watchdog
4.16.1 RTI/Digital Watchdog Device-Specific Information
C672x includes an RTI timer module which is used to generate periodic interrupts. This module also
includes an optional digital watchdog feature. Figure 4-40 contains a block diagram of the RTI module.
Counter 0
SYSCLK2
32-Bit + 32-Bit Prescale
(Used by DSP BIOS)
Compare 0
32-Bit
RTI Interrupt 0
Capture 0
32-Bit + 32-Bit Prescale
Compare 1
32-Bit
RTI Interrupt 1
RTI Interrupt 2
RTI Interrupt 3
Compare 2
32-Bit
Counter 1
32-Bit + 32-Bit Prescale
Compare 3
32-Bit
Capture 1
32-Bit + 32-Bit Prescale
Digital Watchdog
25-Bit Counter
RESET
(Internal Only)
Controlled by
CFGRTI Register
Watchdog Key Register
16-Bit Key
McASP0,1,2
Transmit/Receive
DMA Events
McASP0,1,2
Transmit/Receive
DMA Events
Figure 4-40. RTI Timer Block Diagram
The RTI timer module consists of two independent counters which are both clocked from SYSCLK2 (but
may be started individually and may have different prescaler settings).
The counters provide the timebase against which four output comparators operate. These comparators
may be programmed to generate periodic interrupts. The comparators include an adder which
automatically updates the compare value after each periodic interrupt. This means that the DSP only
needs to initialize the comparator once with the interrupt period.
The two input captures can be triggered from any of the McASP0, McASP1, or McASP2 DMA events. The
device configuration register which selects the McASP events to measure is defined in Table 4-37.
Measuring the time difference between these events provides an accurate measure of the sample rates at
which the McASPs are transmitting and receiving. This measurement can be useful as a hardware assist
for a software asynchronous sample rate converter algorithm.
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The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A
followed by 0xA35C in two separate writes) must be continually written to the key register before the
watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to
provide an added measure of robustness against a software failure. If the application fails and ceases to
write to the watchdog key; the watchdog will respond by resetting the DSP and thereby restarting the
application.
Note that Counter 0 and Compare 0 are used by DSP BIOS to generate the tick counter it requires;
however, Capture 0 is still available for use by the application as well as the remaining RTI resources.
4.16.2 RTI/Digital Watchdog Registers Description(s)
Table 4-36 is a list of the RTI registers.
Table 4-36. RTI Registers
BYTE ADDRESS
REGISTER NAME
DESCRIPTION
Device-Level Configuration Registers Controlling RTI
0x4000 0014
CFGRTI
Selects the sources for the RTI input captures from among the six McASP DMA event.
RTI Internal Registers
0x4200 0000
0x4200 0004
0x4200 0008
0x4200 000C
0x4200 0010
0x4200 0014
0x4200 0018
0x4200 0020
RTIGCTRL
Reserved
Global Control Register. Starts / stops the counters.
Reserved bit.
RTICAPCTRL
RTICOMPCTRL
RTIFRC0
Capture Control. Controls the capture source for the counters.
Compare Control. Controls the source for the compare registers.
Free-Running Counter 0. Current value of free-running counter 0.
Up-Counter 0. Current value of prescale counter 0.
Compare Up-Counter 0. Compare value compared with prescale counter 0.
RTIUC0
RTICPUC0
RTICAFRC0
Capture Free-Running Counter 0. Current value of free-running counter 0 on external
event.
0x4200 0024
0x4200 0030
0x4200 0034
0x4200 0038
0x4200 0040
RTICAUC0
RTIFRC1
Capture Up-Counter 0. Current value of prescale counter 0 on external event.
Free-Running Counter 1. Current value of free-running counter 1.
Up-Counter 1. Current value of prescale counter 1.
RTIUC1
RTICPUC1
RTICAFRC1
Compare Up-Counter 1. Compare value compared with prescale counter 1.
Capture Free-Running Counter 1. Current value of free-running counter 1 on external
event.
0x4200 0044
0x4200 0050
0x4200 0054
RTICAUC1
RTICOMP0
RTIUDCP0
Capture Up-Counter 1. Current value of prescale counter 1 on external event.
Compare 0. Compare value to be compared with the counters.
Update Compare 0. Value to be added to the compare register 0 value on compare
match.
0x4200 0058
0x4200 005C
RTICOMP1
RTIUDCP1
Compare 1. Compare value to be compared with the counters.
Update Compare 1. Value to be added to the compare register 1 value on compare
match.
0x4200 0060
0x4200 0064
RTICOMP2
RTIUDCP2
Compare 2. Compare value to be compared with the counters.
Update Compare 2. Value to be added to the compare register 2 value on compare
match.
0x4200 0068
0x4200 006C
RTICOMP3
RTIUDCP3
Compare 3. Compare value to be compared with the counters.
Update Compare 3. Value to be added to the compare register 3 value on compare
match.
0x4200 0070
0x4200 0074
0x4200 0080
Reserved
Reserved
RTISETINT
Reserved bit.
Reserved bit.
Set Interrupt Enable. Sets interrupt enable bits int RTIINTCTRL without having to do a
read-modify-write operation.
0x4200 0084
RTICLEARINT
Clear Interrupt Enable. Clears interrupt enable bits int RTIINTCTRL without having to
do a read-modify-write operation.
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Table 4-36. RTI Registers (continued)
BYTE ADDRESS
0x4200 0088
0x4200 0090
0x4200 0094
0x4200 0098
0x4200 009C
0x4200 00A0
REGISTER NAME
RTIINTFLAG
DESCRIPTION
Interrupt Flags. Interrupt pending bits.
RTIDWDCTRL
RTIDWDPRLD
RTIWDSTATUS
RTIWDKEY
Digital Watchdog Control. Enables the Digital Watchdog.
Digital Watchdog Preload. Sets the experation time of the Digital Watchdog.
Watchdog Status. Reflects the status of Analog and Digital Watchdog.
Watchdog Key. Correct written key values discharge the external capacitor.
Digital Watchdog Down-Counter
RTIDWDCNTR
Figure 4-41 shows the bit layout of the CFGRTI register and Table 4-37 contains a description of the bits.
31
8
Reserved
7
6
4
3
2
0
Reserved
CAPSEL1
R/W, 0
Reserved
CAPSEL0
R/W, 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-41. CFGRTI Register Bit Layout (0x4000 0014)
Table 4-37. CFGRTI Register Bit Field Description (0x4000 0014)
RESET
VALUE
READ
WRITE
BIT NO.
NAME
DESCRIPTION
31:7,3 Reserved
N/A
0
N/A
R/W
R/W
Reads are indeterminate. Only 0s should be written to these bits.
6:4
2:0
CAPSEL1
CAPSEL0
CAPSEL0 selects the input to the RTI Input Capture 0 function.
CAPSEL1 selects the input to the RTI Input Capture 1 function.
0
The encoding is the same for both fields:
000 = Select McASP0 Transmit DMA Event
001 = Select McASP0 Receive DMA Event
010 = Select McASP1 Transmit DMA Event
011 = Select McASP1 Receive DMA Event
100 = Select McASP2 Transmit DMA Event
101 = Select McASP2 Receive DMA Event
Other values are reserved and their effect is not determined.
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4.17 External Clock Input From Oscillator or CLKIN Pin
The C672x device includes two choices to provide an external clock input, which is fed to the on-chip PLL
to generate high-frequency system clocks. These options are illustrated in Figure 4-42.
•
•
Figure 4-42 (a) illustrates the option that uses an on-chip 1.2-V oscillator with external crystal circuit.
Figure 4-42 (b) illustrates the option that uses an external 3.3-V LVCMOS-compatible clock input with
the CLKIN pin.
Note that the two clock inputs are logically combined internally before the PLL so the clock input that is not
used must be tied to ground.
CV (1.2 V)
DD
C
5
OSCV
OSCV
DD
DD
C
C
7
OSCIN
OSCIN
X
1
R
B
Clock
Input
From
CLKIN
to
Clock
Input
From
OSCIN
to
8
R
S
NC
OSCOUT
OSCOUT
PLL
C
6
PLL
OSCV
SS
OSCV
SS
CLKIN
CLKIN
On-Chip 1.2-V Oscillator
(a)
External 3.3-V LVCMOS-Compatible Clock Source
(b)
Figure 4-42. C672x Clock Input Options
If the on-chip oscillator is chosen, then the recommended component values for Figure 4-42 (a) are listed
in Table 4-38.
Table 4-38. Recommended On-Chip Oscillator Components
(1)
(1)
FREQUENCY
22.579
XTAL TYPE
AT-49
X1
C5
C6
C7
C8
RB
RS
KDS 1AF225796A
KDS 1AS225796AG
KDS 1AF245766AAA
KDS 1AS245766AHA
470 pF
470 pF
470 pF
470 pF
470 pF
470 pF
470 pF
470 pF
8 pF
8 pF
8 pF
8 pF
8 pF
8 pF
8 pF
8 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0 Ω
0 Ω
0 Ω
0 Ω
22.579
24.576
24.576
SMD-49
AT-49
SMD-49
(1) Capacitors C5 and C6 are used to reduce oscillator jitter, but are optional. If C5 and C6 are not used, then the node connecting
capacitors C7 and C8 should be tied to OSCVSS and OSCVDD should be tied to CVDD
.
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4.17.1 Clock Electrical Data/Timing
Table 4-39 assumes testing over recommended operating conditions.
Table 4-39. CLKIN Timing Requirements
NO.
1
MIN
12
MAX
UNIT
MHz
ns
fosc
Oscillator frequency range (OSCIN/OSCOUT)
Cycle time, external clock driven on CLKIN
Pulse width, CLKIN high
25
2
tc(CLKIN)
tw(CLKINH)
tw(CLKINL)
tt(CLKIN)
fPLL
20
3
0.4tc(CLKIN)
0.4tc(CLKIN)
ns
4
Pulse width, CLKIN low
ns
5
Transition time, CLKIN
5
ns
6
Frequency range of PLL input
12
50
MHz
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4.18 Phase-Locked Loop (PLL)
4.18.1 PLL Device-Specific Information
The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs four clocks that have programmable divider options. Figure 4-43 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 4-40 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
PLLEN
(PLL_CSR[0])
Clock
Input
from
PLLOUT
Divider
D0
(/1 to /32)
PLLREF
PLL
x4 to x25
1
0
Divider
D1
(/1 to /32)
SYSCLK1
SYSCLK2
CPU and Memory
CLKIN or
OSCIN
Divider
D2
(/1 to /32)
Peripherals and dMAX
Divider
D3
(/1 to /32)
SYSCLK3
AUXCLK
EMIF
McASP0,1,2
Figure 4-43. PLL Topology
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Table 4-40. Allowed PLL Operating Conditions
ALLOWED SETTING OR RANGE
PARAMETER
DEFAULT VALUE
MIN
MAX
1
2
PLLRST = 1 assertion time during initialization
N/A
N/A
125 ns
187.5 µs
Lock time before setting PLLEN = 1. After changing D0, PLLM, or
input clock.
3
4
5
6
PLL input frequency (PLLREF after D0(1)
PLL multiplier values (PLLM)
PLL output frequency (PLLOUT before dividers D1, D2, D3)(2)
)
12 MHz
x4
50 MHz
x25
x13
N/A
140 MHz
600 MHz
SYSCLK1 frequency (set by PLLM and dividers D0, D1)
PLLOUT/1
Device Frequency
Specification
7
8
SYSCLK2 frequency (set by PLLM and dividers D0, D2)
SYSCLK3 frequency (set by PLLM and dividers D0, D3)
PLLOUT/2
PLLOUT/3
/2, /3, or /4 of SYSCLK1
EMIF Frequency
Specification
(1) Some values for the D0 divider produce results outside of this range and should not be selected.
(2) In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter.
CAUTION
SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0]
to '1'; and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and
D3 are changed in order to make sure the change takes effect and preserves
alignment.
CAUTION
When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3
dividers, the bridge BR2 in Figure 2-4 must be reset by the CFGBRIDGE register. See
Table 2-7.
The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V
power pin (PLLHV) that should be connected to DVDD at the board level through an external filter, as
illustrated in Figure 4-44.
BOARD
DV (3.3 V)
DD
PLLHV
+
Place Filter and Capacitors as Close
to DSP as Possible
10 mF
0.1 mF
EMI
Filter
EMI Filter: TDK ACF451832−333, −223, −153, or −103,
Panasonic EXCCET103U, or Equivalent
Figure 4-44. PLL Power Supply Filter
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4.18.2 PLL Registers Description(s)
Table 4-41 is a list of the PLL registers. For more information about these registers, see the
TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide
(literature number SPRU879).
Table 4-41. PLL Controller Registers
BYTE ADDRESS
0x4100 0000
0x4100 0100
0x4100 0110
0x4100 0114
0x4100 0118
0x4100 011C
0x4100 0120
0x4100 0138
0x4100 013C
0x4100 0140
0x4100 0148
0x4100 014C
0x4100 0150
REGISTER NAME
PLLPID
DESCRIPTION
PLL controller peripheral identification register
PLLCSR
PLLM
PLL control/status register
PLL multiplier control register
PLL controller divider register 0
PLL controller divider register 1
PLL controller divider register 2
PLL controller divider register 3
PLL controller command register
PLL controller status register
PLL controller clock align control register
Clock enable control register
Clock status register
PLLDIV0
PLLDIV1
PLLDIV2
PLLDIV3
PLLCMD
PLLSTAT
ALNCTL
CKEN
CKSTAT
SYSTAT
SYSCLK status register
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5 Application Example
Figure 5-1 illustrates a high-level block diagram of the device and other devices to which it may typically
connect. See Section 1.2 for an overview of each major block.
DSP
CODEC, DIR,
Audio Zone 1
McASP0
SPI1
ADC, DAC, DSD,
Network
256K
Bytes
RAM
SPI or I2C
Control (optional)
C67x+
DSP Core
I2C0
Audio Zone 2
Audio Zone 3
McASP1
McASP2
SPIO
384K
Bytes
ROM
CODEC, DIR,
ADC, DAC, DSD,
Network
Program
Cache
I2C1
Crossbar Switch
Digital Out,
TDM Port
RTI
EMIF
dMAX
UHPI
PLL
OSC
6 Independent Audio
Zones (3 TX + 3 RX)
16 Serial Data Pins
ASYNC
FLASH
High Speed
Parallel Data
DSP Control
SPI or I2C
Host
Microprocessor
100 MHz
SDRAM
A. UHPI is only available on the C6727. McASP2 is not available on the C6722.
Figure 5-1. TMS320C672x Audio DSP System Diagram
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6 Revision History
This data sheet revision history highlights the technical changes made to the SPRS268D device-specific
data sheet to make it an SPRS268E revision.
Scope: Corrected addresses of the XGBLCTL register in Table 4-18, McASP Registers Accessed Through
Peripheral Configuration Bus.
ADDS/CHANGES/DELETES
Table 4-18, McASP Registers Accessed Through Peripheral Configuration Bus:
•
Corrected addresses of XGBLCTL, Transmitter Global Control Register
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7 Mechanical Data
7.1 Package Thermal Resistance Characteristics
Table 7-1 and Table 7-2 provide the thermal characteristics for the recommended package types used on
the TMS320C672x DSP.
Table 7-1. Thermal Characteristics for GDH/ZDH Package
AIR FLOW
NO.
°C/W
(m/s)
Two-Signal, Two-Plane, 101.5 x 114.5 x 1.6 mm , 2-oz Cu. EIA/JESD51-9 PCB
1
2
3
4
5
RθJA
RθJB
RθJC
ΨJB
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Board
Thermal Resistance Junction to Top of Case
Thermal Metric Junction to Board
25
14.5
10
0
0
0
0
0
14
ΨJT
Thermal Metric Junction to Top of Case
0.39
Table 7-2. Thermal Characteristics for RFP Package
THERMAL PAD CONFIGURATION
AIR
NO.
°C/W FLOW
VIA
ARRAY
TOP
BOTTOM
(m/s)
Two-Signal, Two-Plane, 76.2 x 76.2 mm PCB(1)(2)(3)
1
2
3
RθJA
ΨJP
Thermal Resistance Junction to Ambient
10.6 x 10.6 mm
7.5 x 7.5 mm
10.6 x 10.6 mm
7.5 x 7.5 mm
6 x 6
5 x 5
6 x 6
20
22
0
0
0
Thermal Metric Junction to Power Pad
10.6 x 10.6 mm
10.6 x 10.6 mm
0.39
Double-Sided 76.2 x 76.2 mm PCB(1)(2)(4)
RθJA
Thermal Resistance Junction to Ambient
10.6 x 10.6 mm
10.6 x 10.6 mm
10.6 x 10.6 mm
10.6 x 10.6 mm
10.6 x 10.6 mm
10.6 x 10.6 mm
38.1 x 38.1 mm
57.2 x 57 mm
6 x 6
6 x 6
6 x 6
6 x 6
6 x 6
49
27
0
0
0
0
0
22
76.2 x 76.2 mm
10.6 x 10.6 mm
20
4
ΨJP
Thermal Metric Junction to Power Pad
0.39
(1) PCB modeled with 2 oz/ft2 Top and Bottom Cu.
(2) Package thermal pad must be properly soldered to top layer PCB thermal pad for both thermal and electrical performance. Thermal pad
is VSS
.
(3) Top layer thermal pad is connected through via array to both bottom layer thermal pad and internal VSS plane.
(4) Top layer thermal pad is connected through via array to bottom layer thermal pad.
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7.2 Supplementary Information About the 144-Pin RFP PowerPAD™ Package
7.2.1 Standoff Height
This section highlights a few important details about the 144-pin RFP PowerPAD™ package. Texas
Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002)
should be consulted before designing a PCB for this device.
As illustrated in Figure 7-1, the standoff height specification for this device (between 0.050 mm and
0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest
point on the package body. Due to warpage, the lowest point on the package body is located in the center
of the package at the exposed thermal pad.
Using this definition of standoff height provides the correct result for determining the correct solder paste
thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (literature number
SLMA002), the recommended range of solder paste thickness for this package is between 0.152 mm and
0.178 mm.
Standoff Height
Figure 7-1. Standoff Height Measurement on 144-Pin RFP Package
108
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7.2.2 PowerPAD™ PCB Footprint
Texas Instruments' PowerPAD Thermally Enhanced Package Technical Brief (literature number
SLMA002) should be consulted when creating a PCB footprint for this device. In general, for proper
thermal performance, the thermal pad under the package body should be as large as possible. However,
the soldermask opening for the PowerPAD™ should be sized to match the pad size on the 144-pin RFP
package; as illustrated in Figure 7-2.
Thermal Pad on Top Copper
should be as large as Possible.
Soldermask opening should be smaller and match
the size of the thermal pad on the DSP.
Figure 7-2. Soldermask Opening Should Match Size of DSP Thermal Pad
7.3 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
On the 144-pin RFP package, the actual size of the Thermal Pad is 5.4 mm × 5.4 mm.
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PACKAGE OPTION ADDENDUM
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4-May-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMX320C6722RFP
TMX320C6726RFP
TMX320C6727GDH
TMX320C6727ZDH
OBSOLETE HTQFP
OBSOLETE HTQFP
RFP
144
144
256
256
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
RFP
OBSOLETE
OBSOLETE
BGA
BGA
GDH
ZDH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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power.ti.com
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