TMS320C6743ZKB2 [TI]
16-BIT, 50MHz, OTHER DSP, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256;
| 型号： | TMS320C6743ZKB2 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT, 50MHz, OTHER DSP, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256 时钟 外围集成电路 |
| 文件： | 总152页 (文件大小：1326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Check for Samples: TMS320C6743
1 TMS320C6743 Fixed/Floating-Point Digital Signal Processor
1.1 Features
12
Cycle
• Highlights
– Two Multiply Functional Units
– Up to 375-MHz FIxed/Floating-Point VLIW
DSP Core
– Enhanced Direct-Memory-Access Controller
(EDMA3)
•
•
Mixed-Precision IEEE Floating Point
Multiply Supported up to:
–
–
–
–
2 SP x SP -> SP Per Clock
– Two External Memory Interfaces
2 SP x SP -> DP Every Two Clocks
2 SP x DP -> DP Every Three Clocks
2 DP x DP -> DP Every Four Clocks
– Two Configurable 16550 type UART Modules
– One Serial Peripheral Interface (SPI)
– Multimedia Card (MMC)/Secure Digital (SD)
– Two Master/Slave Inter-Integrated Circuit
Modules (I2C)
– RMII Ethernet Media Access Controller
(EMAC)
– Three Event Capture (eCAP) Modules
Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop
Operation
– Protected Mode Operation
– Two Quadrature Encoding (eQEP) Modules
– Two Multi-Channel Audio Serial Ports
(McASP)
– Exceptions Support for Error Detection and
Program Redirection
– Programmable Real-Time Unit Subsystem
(PRUSS)
• C674x Instruction Set Features
– Two 64-bit Timers (each configurable as 32-
bit)
• Applications
– Superset of the C67x+™ and C64x+™ ISAs
– 3000/2250 C674x MIPS/MFLOPS
– Industrial Control
– Networking
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– High-Speed Encoding
– Professional Audio™
• Software Support
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• TMS320C674x Floating Point VLIW DSP Core
• C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– Load-Store Architecture With Non-Aligned
Support
– 128K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
• Enhanced Direct-Memory-Access Controller 3
(EDMA3):
•
Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
Supports up to Two Floating Point (SP or
DP) Reciprocal Approximation (RCPxP)
and Square-Root Reciprocal
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
• 3.3V LVCMOS IOs
•
•
• Two External Memory Interfaces:
– EMIFA
•
NOR (8-Bit-Wide Data)
Approximation (RSQRxP) Operations Per
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
•
NAND (8-Bit-Wide Data)
– Supports TDM, I2S, and Similar Formats
– EMIFB
– FIFO buffers for Transmit and Receive
• 10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
•
16-bit SDRAM, up to 128 MB
• Two Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
• One Serial Peripheral Interface (SPI) With One
Chip-Select
• Multimedia Card (MMC)/Secure Digital (SD)
Card Interface with Secure Data I/O (SDIO)
• Two Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• One 64-Bit General-Purpose Timer
(Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose/Watch Dog Timer
(Configurable as Two 32-Bit Timers)
• Three Enhanced Pulse Width Modulators
(eHRPWM):
– Dedicated 16-Bit Time-Base Counter With
Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3
Dual Edge Asymmetric Outputs
• Programmable Real-Time Unit Subsystem
(PRUSS)
– Two Independent Programmable Realtime
Unit (PRU) Cores
– Dead-Band Generation
•
•
•
•
32-Bit Load/Store RISC architecture
4K Byte instruction RAM per core
512 Bytes data RAM per core
PRU Subsystem (PRUSS) can be disabled
via software to save power
Register 30 of each PRU is exported from
the subsystem in addition to the normal
R31 output of the PRU cores.
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
• Three 32-Bit Enhanced Capture Modules
(eCAP):
– Configurable as 3 Capture Inputs or 3
Auxiliary Pulse Width Modulator (APWM)
outputs
– Single Shot Capture of up to Four Event
Time-Stamps
•
– Standard power management mechanism
• Two 32-Bit Enhanced Quadrature Encoder
Pulse Modules (eQEP)
• 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)
[ZKB Suffix], 1.0-mm Ball Pitch
• 176-Pin Thin Quad Flat Pack (TQFP) [PTP
Suffix], 0.5-mm Pin Pitch
• Commercial or Automotive Temperature
•
•
Clock gating
Entire subsystem under a single PSC
clock gating domain
– Dedicated interrupt controller
– Dedicated switched central resource
• Two Multichannel Audio Serial Ports:
2
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
The C6743 is a Low-power digital signal processor based on C674x DSP core. It consumes significantly
lower power than other members of the TMS320C6000™ platform of DSPs.
The C6743 enables OEMs and ODMs to quickly bring to market devices featuring high processing
performance .
The C6743 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a
32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The
Level 2 program cache (L2P) consists of a 128KB memory space that is shared between program and
data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 2 multichannel audio serial port (McASP)
with 14/9 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one
configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with
programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UART interfaces
(one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-
bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3
auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals;
and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower
memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6743 and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is
available for PHY configuration.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Submit Documentation Feedback
Product Folder Links: TMS320C6743
3
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
1.2 Functional Block Diagram
DSP Subsystem
JTAG Interface
System Control
C674x
DSP CPU
PLL/Clock
Generator
w/OSC
Input
Clock(s)
Memory
Protection
AET
General-
Purpose
Timer
Power/Sleep
Controller
32 KB
L1 Pgm
32 KB
L1 RAM
General-
Purpose
Timer
Pin
Multiplexing
BOOT ROM
(Watchdog)
Switched Central Resource (SCR)
Peripherals
DMA
Audio Ports
Serial Interfaces
McASP
w/FIFO
(2)
2
SPI
(1)
UART
(2)
I C
(2)
EDMA3
GPIO
Connectivity
External Memory Interfaces
EMIFB
Control Timers
(10/100)
EMAC
(RMII)
ePWM
(3)
eCAP
(3)
eQEP
(2)
MMC/SD
(8b)
EMIFA(8b)
NAND/Flash
SDRAM Only
(16b)
MDIO
(1) Not all peripherals are available at the same time due to multiplexing.
Figure 1-1. TMS320C6743 Functional Block Diagram
4
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS565B device-specific data
manual to make it an SPRS565C revision.
Revision History
See
ADDITIONS/MODIFICATIONS/DELETIONS
Global
EMIFB sub-bullets:
Section 1.1
Features
•
Updated/Changed "16-bit SDRAM, up to 256 MB" to "16-bit SDRAM, up to 128 MB"
Figure 1-1, Functional Block Diagram:
Added “Memory Protection” in the System Control Block
Section 1.2
Functional Block Diagram
•
Table 2-1, Characteristics of the C6743 Processor:
•
•
•
Updated/Changed EMIFB “SDRAM only, 16-bit bus width, up to 256 Mbit (PTP)” to “SDRAM
only, 16-bit bus width, up to 128 MB (PTP)”
Section 2.1
Device Characteristics
Updated/Changed EMIFB SDRAM only, “16-bit bus width, up to 512 Mbit (ZKB)” to “16-bit
bus width, up to 128 MB (ZKB)”
Added Silicon Revisions "3.0" and "2.1" to the JTAG BSDL_ID row
Table 2-2, C674x Cache Registers:
•
Updated/Changed DESCRIPTION for MAR192 – MAR223 from “… SDRAM Data (CS2) …”
to “…SDRAM Data (CS0) …”
Section 2.3.2.3
C674x CPU
Added “Note: Read/Write accesses …” sentence
Section 2.4
Memory Map Summary
Table 2-4, C6743 Top Level Memory Map:
•
•
Updated/Changed "0xC000 0000" – "0xCFFF FFFF" "256M" "EMIFB SDRAM Data" to
"0xC000 0000" – "0xC7FF FFFF" "128M"
Updated/Changed "0xD000 0000" – "0xFFFF FFFF” to "0xC800 0000" – "0xFFFF FFFF"
"BLANK" RESERVED row
Table 2-18, Ethernet Media Access Controller (EMAC) Terminal Functions:
Section 2.6.14
Ethernet Media Access
Controller (EMAC)
•
Added “MDIO serial data” DESCRIPTION for the MDIO AXR0[8]/MDIO_D/GP3[8] SIGNAL
NAME
Table 2-21, Reserved and No Connect Terminal Functions:
•
•
Updated/Changed the RSV1 TYPE column from “PWR” to “-“
Section 2.6.17
Reserved and No Connect
Terminal Functions
Updated/Changed RSV2 DESCRIPTION to “… be tied either directly to CVDD or left
unconnected [do not connect to ground (VSS)]”
NOR Flash Boot bullet:
•
•
•
Deleted "or 16-bit" from NOR Direct boot
Deleted "or 16-bit" from NOR Legacy boot
Deleted "or 16-bit" from NOR AIS boot
Section 3.1
Boot Modes
Table 3-1, System Configuration (SYSCFG) Module Register Access:
•
Updated/Changed 0x01C1 4018, DEVIDR0 REGISTER DESCRIPTION from “Device
Identification Register 0” to “JTAG Identification Register”
Section 3.2
SYSCFG Module
•
Added 0x01C1 4024, CHIPREVID, Silicon Revision Identification Register row
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Submit Documentation Feedback
Product Folder Links: TMS320C6743
5
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Revision History (continued)
See
ADDITIONS/MODIFICATIONS/DELETIONS
Section 4.1, Absolute Maximum Ratings Over Operating Case Temperature Range:
•
Updated/Changed Input voltage ranges, VI I/O, 3.3V (Steady State) from “-0.3V to DVDD +
0.3V” to
“-0.3V to DVDD + 0.35V”
Section 4
Device Operating Conditions
Section 4.2, Recommended Operating Conditions:
Updated/Change DVDD, Supply voltage, I/O, 3.3V (DVDD) MIN value from “3.15” to “3.0” V
Section 5.4.1, Power-On Reset (POR):
•
•
Deleted "RESETOUT, which remains active through the reset sequence, and" from the "All
pins are tri-stated ..." sentence in the first paragraph
Section 5.4
Reset
Section 5.4.2, Warm Reset:
•
Deleted "RESETOUT, which remains active through the reset sequence, and" from the "All
pins are tri-stated ..." sentence in the first paragraph
•
Updated/Changed "During reset, GP7[14] is ..." sentence in the first paragraph
Table 5-4, Allowed PLL Operating Conditions:
Added “Max PLL Lock Time =” to PARAMETER NO 2, Lock time MAX equation
Section 5.6.1
PLL Device-Specific
Information
•
Table 5-7, C6743 DSP Interrupts:
•
Updated/Changed EVT# 74 INTERRUPT NAME from “PROTERR” to
“MPU_BOOTCFG_ERR”
Section 5.6.1
DSP Interrupts
•
Updated/Changed EVT# 74 SOURCE from “SYSCFG Protection Shared Interrupt” to “Shared
MPU and SYSCFG Address/Protection Error Interrupt"
Section 5.11
External Memory Interface B
(EMIFB)
Figure 5-17, EMIFB Functional Block Diagram:
Added MPU2 block to figure
•
Section 5.11.1, EMIFB SDRAM Loading Limitations:
Added new Subsection
•
Section 5.11.2
Interfacing to SDRAM
Deleted "EMIFB to Dual 4M × 16 × 4 Bank SDRAM Interface" figure, incorrect
Table 5-25, EMIFB SDRAM Interface Switching Characteristics:
•
Updated/Changed PARAMETER No. 1, tc(CLK) Cycle time, EMIF clock EMB_CLK MIN value
from “7.5” to “6.579” ns
Section 5.11.3
EMIFB Electrical Data/Timing
•
Updated/Changed PARAMETER No. 2, tw(CLK) Pulse width, EMIF clock EMB_CLK high or
low MIN value from “3” to “2.63” ns
Section 5.27, JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0):
Added Silicon Revisions "3.0" and "2.1" to the "0x9B7D F02F for silicon revision 2.0" bullet
Section 5.27
IEEE 1149.1 JTAG
•
Section 6.1.2
Device and Development-
Support Tool Nomenclature
Updated/Changed subsection title from “Device Nomenclature” to “Device and Development-
Support Tool Nomenclature”
Figure 6-1, Device Nomenclature:
•
Updated/Changed Silicon Revision to include Revision 3.0
6
TMS320C6743 Fixed/Floating-Point Digital Signal Processor
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the C6743 Low power digital signal processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 2-1. Characteristics of the C6743 Processor
HARDWARE FEATURES
C6743
SDRAM only, 16-bit bus width, up to
128 MB (PTP)
SDRAM only, 16-bit bus width, up to
128 MB (ZKB)
EMIFB
EMIFA
Asynchronous (8-bit bus width) RAM, Flash, NOR, NAND
MMC and SD cards supported.
Flash Card Interface
EDMA3
32 independent channels, 8 QDMA channels, 2 Transfer controllers
2 64-Bit General Purpose (configurable as 2 separate 32-bit timers, 1
configurable as Watch Dog)
Timers
UART
SPI
I2C
2 (One with RTS and CTS flow control)
One with one hardware chip select
2 (both Master/Slave)
Peripherals
Not all peripherals pins
are available at the
same time (for more
detail, see the Device
Configurations section).
Multichannel Audio Serial Port
[McASP]
2 (each with transmit/receive, FIFO buffer, 14/9 serializers)
1 (RMII Interface)
10/100 Ethernet MAC with
Management Data I/O
eHRPWM
eCAP
6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
2 32-bit QEP channels with 4 inputs/channel
eQEP
General-Purpose Input/Output
Port
8 banks of 16-bit
PRU Subsystem (PRUSS)
Size (Bytes)
2 Programmable PRU Cores
320KB RAM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
On-Chip Memory
Organization
128KB Unified Mapped RAM/Cache (L2)
DSP Memories can be made accessible to EDMA3, and other peripherals.
C674x CPU ID + CPU Control Status Register
0x1400
0x0000
Rev ID
(CSR.[31:16])
C674x Megamodule
Revision
Revision ID Register
(MM_REVID[15:0])
0x8B7DF02F (Silicon Revision 1.0)
0x8B7DF02F (Silicon Revision 1.1)
JTAG BSDL_ID
DEVIDR0 register
0x9B7DF02F (Silicon Revision 3.0, 2.1, and 2.0)
CPU Frequency
Voltage
MHz
C674x DSP 375(/200) MHz
Core (V)
I/O (V)
1.2 V
3.3 V
24 mm x 24 mm, 176-Pin, 0.5 mm
pitch, TQFP (PTP)
17 mm x 17 mm, 256-Ball 1 mm pitch,
PBGA (ZKB)
Package
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(1)
PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
7
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.2 Device Compatibility
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.
2.3 DSP Subsystem
The DSP Subsystem includes the following features:
•
•
•
•
•
•
C674x DSP CPU
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
128KB Unified Mapped RAM/Cache (L2)
Boot ROM (cannot be used for application code)
Little endian
32K Bytes
L1P RAM/
Cache
128K Bytes
L2 RAM
Boot ROM
256
256
256
256
Cache Control
Memory Protect
Bandwidth Mgmt
Cache Control
Memory Protect
Bandwidth Mgmt
L1P
L2
256
256
Power Down
Interrupt
Controller
256
256
Instruction Fetch
C64x
Fixed/Floating-Point CPU
IDMA
256
Register
File A
Register
File B
64
64
CFG
Bandwidth Mgmt
Memory Protect
Cache Control
EMC
Configuration
Peripherals
Bus
32
L1D
MDMA
SDMA
8 x 32
64
64
64
64
32K Bytes
L1D RAM/
Cache
High
Performance
Switch Fabric
Figure 2-1. C674x Megamodule Block Diagram
8
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.3.1 C674x DSP CPU Description
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 2-2. The two general-purpose register files (A and B) each contain 32 32-
bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-
bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
•
•
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-
running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
9
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
TMS320C64x Technical Overview (SPRU395)
10
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Even
Odd
register
src1
src2
register
file A
file A
(A0, A2,
(A1, A3,
A4...A30)
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
DA1
2x
1x
Even
register
file B
Odd
register
file B
src2
DA2
.D2
(B0, B2,
B4...B30)
src1
dst
(B1, B3,
B5...B31)
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
32 MSB
32 LSB
ST2a
ST2b
8
long src
even dst
(D)
odd dst
src2
.L2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-2. TMS320C674x CPU (DSP Core) Data Paths
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
11
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.3.2 DSP Memory Mapping
The DSP memory map is shown in Section 2.4.
2.3.2.1 External Memories
The DSP has access to the following External memories:
•
•
Asynchronous EMIF / NAND / NOR Flash (EMIFA)
SDRAM (EMIFB)
2.3.2.2 DSP Internal Memories
The DSP has access to the following DSP memories:
•
•
•
L2 RAM
L1P RAM
L1D RAM
2.3.2.3 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 128 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C674x CPU cache registers for the device.
Table 2-2. C674x Cache Registers
HEX ADDRESS RANGE
0x0184 0000
REGISTER NAME
L2CFG
DESCRIPTION
L2 Cache configuration register
L1P Size Cache configuration register
L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register
L1D Freeze Mode Cache configuration register
Reserved
0x0184 0020
L1PCFG
L1PCC
0x0184 0024
0x0184 0040
L1DCFG
L1DCC
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
-
EDMAWEIGHT
-
L2 EDMA access control register
Reserved
0x0184 1004 - 0x0184 1FFC
0x0184 2000
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2 allocation register 0
0x0184 2004
L2 allocation register 1
0x0184 2008
L2 allocation register 2
0x0184 200C
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
0x0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
L1D writeback invalidate word count register
Reserved
0x0184 4004
0x0184 4010
0x0184 4014
0x0184 4018
0x0184 401C
L2IWC
0x0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
0x0184 4024
0x0184 4030
0x0184 4034
0x0184 4038
0x0184 4040
L1DWBAR
L1D Block Writeback
12
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 2-2. C674x Cache Registers (continued)
HEX ADDRESS RANGE
REGISTER NAME
L1DWWC
L1DIBAR
L1DIWC
-
DESCRIPTION
0x0184 4044
0x0184 4048
L1D Block Writeback
L1D invalidate base address register
L1D invalidate word count register
Reserved
0x0184 404C
0x0184 4050 - 0x0184 4FFF
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2INV
L2 writeback invalidate all register
L2 Global Invalidate without writeback
Reserved
0x0184 5008
0x0184 500C - 0x0184 5027
0x0184 5028
-
L1PINV
L1P Global Invalidate
0x0184 502C - 0x0184 5039
0x0184 5040
-
Reserved
L1DWB
L1D Global Writeback
0x0184 5044
L1DWBINV
L1DINV
L1D Global Writeback with Invalidate
L1D Global Invalidate without writeback
Reserved 0x0000 0000 – 0x3FFF FFFF
Reserved 0x4000 0000 – 0x5FFF FFFF
0x0184 5048
0x0184 8000 – 0x0184 80FF
0x0184 8100 – 0x0184 817F
MAR0 - MAR63
MAR64 – MAR95
Memory Attribute Registers for EMIFA Async Data (CS2) 0x6000 0000 –
0x61FF FFFF
0x0184 8180 – 0x0184 8187
0x0184 8188 – 0x0184 818F
MAR96 - MAR97
MAR98 – MAR99
Memory Attribute Registers for EMIFA Async Data (CS3) 0x6200 0000 –
0x63FF FFFF
0x0184 8190 – 0x0184 8197
0x0184 8198 – 0x0184 819F
MAR100 – MAR101
MAR102 – MAR103
Reserved 0x6400 0000 – 0x65FF FFFF
Reserved 0x6600 0000 – 0x67FF FFFF
Reserved 0x6800 0000 – 0x7FFF FFFF
Reserved 0x8000 0000 – 0x81FF FFFF
Reserved 0x8200 0000 – 0xBFFF FFFF
0x0184 81A0 – 0x0184 81FF MAR104 – MAR127
0x0184 8200
MAR128
0x0184 8204 – 0x0184 82FF
MAR129 – MAR191
Memory Attribute Registers for EMIFB SDRAM Data (CS0) 0xC000
0000 – 0xDFFF FFFF
0x0184 8300 – 0x0184 837F
0x0184 8380 – 0x0184 83FF
MAR192 – MAR223
MAR224 – MAR255
Reserved 0xE000 0000 – 0xFFFF FFFF
Table 2-3. C674x L1/L2 Memory Protection Registers
HEX ADDRESS RANGE
0x0184 A000
REGISTER NAME
L2MPFAR
L2MPFSR
L2MPFCR
-
DESCRIPTION
L2 memory protection fault address register
L2 memory protection fault status register
L2 memory protection fault command register
Reserved
0x0184 A004
0x0184 A008
0x0184 A00C - 0x0184 A0FF
0x0184 A100
L2MPLK0
L2MPLK1
L2MPLK2
L2MPLK3
L2MPLKCMD
L2MPLKSTAT
-
L2 memory protection lock key bits [31:0]
L2 memory protection lock key bits [63:32]
L2 memory protection lock key bits [95:64]
L2 memory protection lock key bits [127:96]
L2 memory protection lock key command register
L2 memory protection lock key status register
Reserved
0x0184 A104
0x0184 A108
0x0184 A10C
0x0184 A110
0x0184 A114
0x0184 A118 - 0x0184 A1FF
L2 memory protection page attribute register 0
(controls memory address 0x0080 0000 - 0x0080 1FFF)
0x0184 A200
0x0184 A204
0x0184 A208
0x0184 A20C
L2MPPA0
L2MPPA1
L2MPPA2
L2MPPA3
L2 memory protection page attribute register 1
(controls memory address 0x0080 2000 - 0x0080 3FFF)
L2 memory protection page attribute register 2
(controls memory address 0x0080 4000 - 0x0080 5FFF)
L2 memory protection page attribute register 3
(controls memory address 0x0080 6000 - 0x0080 7FFF)
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
13
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
REGISTER NAME
DESCRIPTION
L2 memory protection page attribute register 4
(controls memory address 0x0080 8000 - 0x0080 9FFF)
0x0184 A210
L2MPPA4
L2 memory protection page attribute register 5
(controls memory address 0x0080 A000 - 0x0080 BFFF)
0x0184 A214
0x0184 A218
0x0184 A21C
0x0184 A220
0x0184 A224
0x0184 A228
0x0184 A22C
0x0184 A230
0x0184 A234
0x0184 A238
0x0184 A23C
0x0184 A240
0x0184 A244
0x0184 A248
0x0184 A24C
0x0184 A250
0x0184 A254
0x0184 A258
0x0184 A25C
0x0184 A260
0x0184 A264
0x0184 A268
0x0184 A26C
0x0184 A270
0x0184 A274
0x0184 A278
0x0184 A27C
L2MPPA5
L2 memory protection page attribute register 6
(controls memory address 0x0080 C000 - 0x0080 DFFF)
L2MPPA6
L2 memory protection page attribute register 7
(controls memory address 0x0080 E000 - 0x0080 FFFF)
L2MPPA7
L2 memory protection page attribute register 8
(controls memory address 0x0081 0000 - 0x0081 1FFF)
L2MPPA8
L2 memory protection page attribute register 9
(controls memory address 0x0081 2000 - 0x0081 3FFF)
L2MPPA9
L2 memory protection page attribute register 10
(controls memory address 0x0081 4000 - 0x0081 5FFF)
L2MPPA10
L2MPPA11
L2MPPA12
L2MPPA13
L2MPPA14
L2MPPA15
L2MPPA16
L2MPPA17
L2MPPA18
L2MPPA19
L2MPPA20
L2MPPA21
L2MPPA22
L2MPPA23
L2MPPA24
L2MPPA25
L2MPPA26
L2MPPA27
L2MPPA28
L2MPPA29
L2MPPA30
L2MPPA31
L2 memory protection page attribute register 11
(controls memory address 0x0081 6000 - 0x0081 7FFF)
L2 memory protection page attribute register 12
(controls memory address 0x0081 8000 - 0x0081 9FFF)
L2 memory protection page attribute register 13
(controls memory address 0x0081 A000 - 0x0081 BFFF)
L2 memory protection page attribute register 14
(controls memory address 0x0081 C000 - 0x0081 DFFF)
L2 memory protection page attribute register 15
(controls memory address 0x0081 E000 - 0x0081 FFFF)
L2 memory protection page attribute register 16
(controls memory address 0x0082 0000 - 0x0082 1FFF)
L2 memory protection page attribute register 17
(controls memory address 0x0082 2000 - 0x0082 3FFF)
L2 memory protection page attribute register 18
(controls memory address 0x0082 4000 - 0x0082 5FFF)
L2 memory protection page attribute register 19
(controls memory address 0x0082 6000 - 0x0082 7FFF)
L2 memory protection page attribute register 20
(controls memory address 0x0082 8000 - 0x0082 9FFF)
L2 memory protection page attribute register 21
(controls memory address 0x0082 A000 - 0x0082 BFFF)
L2 memory protection page attribute register 22
(controls memory address 0x0082 C000 - 0x0082 DFFF)
L2 memory protection page attribute register 23
(controls memory address 0x0082 E000 - 0x0082 FFFF)
L2 memory protection page attribute register 24
(controls memory address 0x0083 0000 - 0x0083 1FFF)
L2 memory protection page attribute register 25
(controls memory address 0x0083 2000 - 0x0083 3FFF)
L2 memory protection page attribute register 26
(controls memory address 0x0083 4000 - 0x0083 5FFF)
L2 memory protection page attribute register 27
(controls memory address 0x0083 6000 - 0x0083 7FFF)
L2 memory protection page attribute register 28
(controls memory address 0x0083 8000 - 0x0083 9FFF)
L2 memory protection page attribute register 29
(controls memory address 0x0083 A000 - 0x0083 BFFF)
L2 memory protection page attribute register 30
(controls memory address 0x0083 C000 - 0x0083 DFFF)
L2 memory protection page attribute register 31
(controls memory address 0x0083 E000 - 0x0083 FFFF)
14
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
REGISTER NAME
DESCRIPTION
L2 memory protection page attribute register 32
(controls memory address 0x0070 0000 - 0x0070 7FFF)
0x0184 A280
0x0184 A284
0x0184 A288
0x0184 A28C
0x0184 A290
0x0184 A294
0x0184 A298
0x0184 A29C
0x0184 A2A0
0x0184 A2A4
0x0184 A2A8
0x0184 A2AC
0x0184 A2B0
0x0184 A2B4
0x0184 A2B8
0x0184 A2BC
0x0184 A2C0
0x0184 A2C4
0x0184 A2C8
0x0184 A2CC
0x0184 A2D0
0x0184 A2D4
0x0184 A2D8
0x0184 A2DC
0x0184 A2E0
0x0184 A2E4
0x0184 A2E8
0x0184 A2EC
L2MPPA32
L2 memory protection page attribute register 33
(controls memory address 0x0070 8000 - 0x0070 FFFF)
L2MPPA33
L2MPPA34
L2MPPA35
L2MPPA36
L2MPPA37
L2MPPA38
L2MPPA39
L2MPPA40
L2MPPA41
L2MPPA42
L2MPPA43
L2MPPA44
L2MPPA45
L2MPPA46
L2MPPA47
L2MPPA48
L2MPPA49
L2MPPA50
L2MPPA51
L2MPPA52
L2MPPA53
L2MPPA54
L2MPPA55
L2MPPA56
L2MPPA57
L2MPPA58
L2MPPA59
L2 memory protection page attribute register 34
(controls memory address 0x0071 0000 - 0x0071 7FFF)
L2 memory protection page attribute register 35
(controls memory address 0x0071 8000 - 0x0071 FFFF)
L2 memory protection page attribute register 36
(controls memory address 0x0072 0000 - 0x0072 7FFF)
L2 memory protection page attribute register 37
(controls memory address 0x0072 8000 - 0x0072 FFFF)
L2 memory protection page attribute register 38
(controls memory address 0x0073 0000 - 0x0073 7FFF)
L2 memory protection page attribute register 39
(controls memory address 0x0073 8000 - 0x0073 FFFF)
L2 memory protection page attribute register 40
(controls memory address 0x0074 0000 - 0x0074 7FFF)
L2 memory protection page attribute register 41
(controls memory address 0x0074 8000 - 0x0074 FFFF)
L2 memory protection page attribute register 42
(controls memory address 0x0075 0000 - 0x0075 7FFF)
L2 memory protection page attribute register 43
(controls memory address 0x0075 8000 - 0x0075 FFFF)
L2 memory protection page attribute register 44
(controls memory address 0x0076 0000 - 0x0076 7FFF)
L2 memory protection page attribute register 45
(controls memory address 0x0076 8000 - 0x0076 FFFF)
L2 memory protection page attribute register 46
(controls memory address 0x0077 0000 - 0x0077 7FFF)
L2 memory protection page attribute register 47
(controls memory address 0x0077 8000 - 0x0077 FFFF)
L2 memory protection page attribute register 48
(controls memory address 0x0078 0000 - 0x0078 7FFF)
L2 memory protection page attribute register 49
(controls memory address 0x0078 8000 - 0x0078 FFFF)
L2 memory protection page attribute register 50
(controls memory address 0x0079 0000 - 0x0079 7FFF)
L2 memory protection page attribute register 51
(controls memory address 0x0079 8000 - 0x0079 FFFF)
L2 memory protection page attribute register 52
(controls memory address 0x007A 0000 - 0x007A 7FFF)
L2 memory protection page attribute register 53
(controls memory address 0x007A 8000 - 0x007A FFFF)
L2 memory protection page attribute register 54
(controls memory address 0x007B 0000 - 0x007B 7FFF)
L2 memory protection page attribute register 55
(controls memory address 0x007B 8000 - 0x007B FFFF)
L2 memory protection page attribute register 56
(controls memory address 0x007C 0000 - 0x007C 7FFF)
L2 memory protection page attribute register 57
(controls memory address 0x007C 8000 - 0x007C FFFF)
L2 memory protection page attribute register 58
(controls memory address 0x007D 0000 - 0x007D 7FFF)
L2 memory protection page attribute register 59
(controls memory address 0x007D 8000 - 0x007D FFFF)
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
15
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
REGISTER NAME
DESCRIPTION
L2 memory protection page attribute register 60
(controls memory address 0x007E 0000 - 0x007E 7FFF)
0x0184 A2F0
L2MPPA60
L2 memory protection page attribute register 61
(controls memory address 0x007E 8000 - 0x007E FFFF)
0x0184 A2F4
0x0184 A2F8
0x0184 A2FC
L2MPPA61
L2MPPA62
L2MPPA63
L2 memory protection page attribute register 62
(controls memory address 0x007F 0000 - 0x007F 7FFF)
L2 memory protection page attribute register 63
(controls memory address 0x007F 8000 - 0x007F FFFF)
0x0184 A300 - 0x0184 A3FF
0x0184 A400
-
Reserved
L1PMPFAR
L1PMPFSR
L1PMPFCR
-
L1P memory protection fault address register
L1P memory protection fault status register
L1P memory protection fault command register
Reserved
0x0184 A404
0x0184 A408
0x0184 A40C - 0x0184 A4FF
0x0184 A500
L1PMPLK0
L1PMPLK1
L1PMPLK2
L1PMPLK3
L1PMPLKCMD
L1PMPLKSTAT
-
L1P memory protection lock key bits [31:0]
L1P memory protection lock key bits [63:32]
L1P memory protection lock key bits [95:64]
L1P memory protection lock key bits [127:96]
L1P memory protection lock key command register
L1P memory protection lock key status register
Reserved
0x0184 A504
0x0184 A508
0x0184 A50C
0x0184 A510
0x0184 A514
0x0184 A518 - 0x0184 A5FF
0x0184 A600 - 0x0184 A63F
(1)
-
Reserved.
L1P memory protection page attribute register 16
(controls memory address 0x00E0 0000 - 0x00E0 07FF)
0x0184 A640
0x0184 A644
0x0184 A648
0x0184 A64C
0x0184 A650
0x0184 A654
0x0184 A658
0x0184 A65C
0x0184 A660
0x0184 A664
0x0184 A668
0x0184 A66C
0x0184 A670
0x0184 A674
0x0184 A678
L1PMPPA16
L1PMPPA17
L1PMPPA18
L1PMPPA19
L1PMPPA20
L1PMPPA21
L1PMPPA22
L1PMPPA23
L1PMPPA24
L1PMPPA25
L1PMPPA26
L1PMPPA27
L1PMPPA28
L1PMPPA29
L1PMPPA30
L1P memory protection page attribute register 17
(controls memory address 0x00E0 0800 - 0x00E0 0FFF)
L1P memory protection page attribute register 18
(controls memory address 0x00E0 1000 - 0x00E0 17FF)
L1P memory protection page attribute register 19
(controls memory address 0x00E0 1800 - 0x00E0 1FFF)
L1P memory protection page attribute register 20
(controls memory address 0x00E0 2000 - 0x00E0 27FF)
L1P memory protection page attribute register 21
(controls memory address 0x00E0 2800 - 0x00E0 2FFF)
L1P memory protection page attribute register 22
(controls memory address 0x00E0 3000 - 0x00E0 37FF)
L1P memory protection page attribute register 23
(controls memory address 0x00E0 3800 - 0x00E0 3FFF)
L1P memory protection page attribute register 24
(controls memory address 0x00E0 4000 - 0x00E0 47FF)
L1P memory protection page attribute register 25
(controls memory address 0x00E0 4800 - 0x00E0 4FFF)
L1P memory protection page attribute register 26
(controls memory address 0x00E0 5000 - 0x00E0 57FF)
L1P memory protection page attribute register 27
(controls memory address 0x00E0 5800 - 0x00E0 5FFF)
L1P memory protection page attribute register 28
(controls memory address 0x00E0 6000 - 0x00E0 67FF)
L1P memory protection page attribute register 29
(controls memory address 0x00E0 6800 - 0x00E0 6FFF)
L1P memory protection page attribute register 30
(controls memory address 0x00E0 7000 - 0x00E0 77FF)
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
16
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 2-3. C674x L1/L2 Memory Protection Registers (continued)
HEX ADDRESS RANGE
REGISTER NAME
DESCRIPTION
L1P memory protection page attribute register 31
(controls memory address 0x00E0 7800 - 0x00E0 7FFF)
0x0184 A67C
L1PMPPA31
0x0184 A67F – 0x0184 ABFF
0x0184 AC00
-
Reserved
L1DMPFAR
L1DMPFSR
L1DMPFCR
-
L1D memory protection fault address register
L1D memory protection fault status register
L1D memory protection fault command register
Reserved
0x0184 AC04
0x0184 AC08
0x0184 AC0C - 0x0184 ACFF
0x0184 AD00
L1DMPLK0
L1DMPLK1
L1DMPLK2
L1DMPLK3
L1DMPLKCMD
L1DMPLKSTAT
-
L1D memory protection lock key bits [31:0]
L1D memory protection lock key bits [63:32]
L1D memory protection lock key bits [95:64]
L1D memory protection lock key bits [127:96]
L1D memory protection lock key command register
L1D memory protection lock key status register
Reserved
0x0184 AD04
0x0184 AD08
0x0184 AD0C
0x0184 AD10
0x0184 AD14
0x0184 AD18 - 0x0184 ADFF
0x0184 AE00 - 0x0184 AE3F
(2)
-
Reserved.
L1D memory protection page attribute register 16
(controls memory address 0x00F0 0000 - 0x00F0 07FF)
0x0184 AE40
0x0184 AE44
0x0184 AE48
0x0184 AE4C
0x0184 AE50
0x0184 AE54
0x0184 AE58
0x0184 AE5C
0x0184 AE60
0x0184 AE64
0x0184 AE68
0x0184 AE6C
0x0184 AE70
0x0184 AE74
0x0184 AE78
L1DMPPA16
L1DMPPA17
L1DMPPA18
L1DMPPA19
L1DMPPA20
L1DMPPA21
L1DMPPA22
L1DMPPA23
L1DMPPA24
L1DMPPA25
L1DMPPA26
L1DMPPA27
L1DMPPA28
L1DMPPA29
L1DMPPA30
L1D memory protection page attribute register 17
(controls memory address 0x00F0 0800 - 0x00F0 0FFF)
L1D memory protection page attribute register 18
(controls memory address 0x00F0 1000 - 0x00F0 17FF)
L1D memory protection page attribute register 19
(controls memory address 0x00F0 1800 - 0x00F0 1FFF)
L1D memory protection page attribute register 20
(controls memory address 0x00F0 2000 - 0x00F0 27FF)
L1D memory protection page attribute register 21
(controls memory address 0x00F0 2800 - 0x00F0 2FFF)
L1D memory protection page attribute register 22
(controls memory address 0x00F0 3000 - 0x00F0 37FF)
L1D memory protection page attribute register 23
(controls memory address 0x00F0 3800 - 0x00F0 3FFF)
L1D memory protection page attribute register 24
(controls memory address 0x00F0 4000 - 0x00F0 47FF)
L1D memory protection page attribute register 25
(controls memory address 0x00F0 4800 - 0x00F0 4FFF)
L1D memory protection page attribute register 26
(controls memory address 0x00F0 5000 - 0x00F0 57FF)
L1D memory protection page attribute register 27
(controls memory address 0x00F0 5800 - 0x00F0 5FFF)
L1D memory protection page attribute register 28
(controls memory address 0x00F0 6000 - 0x00F0 67FF)
L1D memory protection page attribute register 29
(controls memory address 0x00F0 6800 - 0x00F0 6FFF)
L1D memory protection page attribute register 30
(controls memory address 0x00F0 7000 - 0x00F0 77FF)
L1D memory protection page attribute register 31
(controls memory address 0x00F0 7800 - 0x00F0 7FFF)
0x0184 AE7C
L1DMPPA31
-
0x0184 AE80 – 0x0185 FFFF
Reserved
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
17
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.4 Memory Map Summary
Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined
behavior.
Table 2-4. C6743 Top Level Memory Map
START
ADDRESS
END
ADDRESS
SIZE
DSP MEM MAP
EDMA MEM MAP
PRUSS MEM MAP
MASTER PERIPHERAL
MEM MAP
0x0000 0000
0x0000 0FFF
4K
PRUSS Local
Address Space
0x0000 1000
0x0070 0000
0x0080 0000
0x0082 0000
0x0084 0000
0x00E0 0000
0x00E0 8000
0x00F0 0000
0x00F0 8000
0x0180 0000
0x006F FFFF
0x007F FFFF
0x0081 FFFF
0x0083 FFFF
0x00DF FFFF
0x00E0 7FFF
0x00EF FFFF
0x00F0 7FFF
0x017F FFFF
0x0180 FFFF
1024K
128K
32K
DSP L2 ROM(1)
DSP L2 RAM
DSP L1P RAM
DSP L1D RAM
32K
64K
4K
DSP Interrupt
Controller
0x0181 0000
0x0181 0FFF
DSP Powerdown
Controller
0x0181 1000
0x0181 2000
0x0181 3000
0x0182 0000
0x0183 0000
0x0181 1FFF
0x0181 2FFF
0x0181 FFFF
0x0182 FFFF
0x0183 FFFF
4K
4K
DSP Security ID
DSP Revision ID
64K
64K
DSP EMC
DSP Internal
Reserved
0x0184 0000
0x0184 FFFF
64K
DSP Memory
System
0x0185 0000
0x01C0 0000
0x01C0 8000
0x01C0 8400
0x01C0 8800
0x01C1 0000
0x01C1 1000
0x01C1 2000
0x01C1 4000
0x01C1 5000
0x01C2 0000
0x01C2 1000
0x01C2 2000
0x01C2 3000
0x01C4 0000
0x01C4 1000
0x01C4 2000
0x01C4 3000
0x01D0 0000
0x01D0 1000
0x01BF FFFF
0x01C0 7FFF
0x01C0 83FF
0x01C0 87FF
0x01C0 FFFF
0x01C1 0FFF
0x01C1 1FFF
0x01C1 3FFF
0x01C1 4FFF
0x01C1 FFFF
0x01C2 0FFF
0x01C2 1FFF
0x01C2 2FFF
0x01C2 FFFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 2FFF
0x01CF FFFF
0x01D0 0FFF
0x01D0 1FFF
32K
1024
1024
EDMA3 CC
EDMA3 TC0
EDMA3 TC1
4K
4K
PSC 0
PLL Controller
4K
BootConfig
4K
4K
4K
Timer64P 0
Timer64P 1
I2C 0
4K
4K
4K
MMC/SD 0
SPI 0
UART 0
4K
4K
McASP 0 Control
McASP 0 AFIFO Ctrl
(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code.
18 Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 2-4. C6743 Top Level Memory Map (continued)
START
ADDRESS
END
ADDRESS
SIZE
DSP MEM MAP
EDMA MEM MAP
PRUSS MEM MAP
MASTER PERIPHERAL
MEM MAP
0x01D0 2000
0x01D0 3000
0x01D0 4000
0x01D0 5000
0x01D0 6000
0x01D0 7000
0x01D0 D000
0x01D0 E000
0x01E1 4000
0x01E1 5000
0x01E1 6000
0x01E2 0000
0x01E2 2000
0x01E2 3000
0x01E2 4000
0x01E2 5000
0x01E2 6000
0x01E2 7000
0x01E2 8000
0x01E2 9000
0x01F0 0000
0x01F0 1000
0x01F0 2000
0x01F0 3000
0x01F0 4000
0x01F0 5000
0x01F0 6000
0x01F0 7000
0x01F0 8000
0x01F0 9000
0x01F0 A000
0x01F0 B000
0x1170 0000
0x1180 0000
0x1182 0000
0x1184 0000
0x11E0 0000
0x11E0 8000
0x11F0 0000
0x11F0 8000
0x6000 0000
0x6200 0000
0x6400 0000
0x6800 0000
0x6800 8000
0xB000 0000
0x01D0 2FFF
0x01D0 3FFF
0x01D0 4FFF
0x01D0 5FFF
0x01D0 6FFF
0x01D0 CFFF
0x01D0 DFFF
0x01E1 3FFF
0x01E1 4FFF
0x01E1 5FFF
0x01E1 FFFF
0x01E2 1FFF
0x01E2 2FFF
0x01E2 3FFF
0x01E2 4FFF
0x01E2 5FFF
0x01E2 6FFF
0x01E2 7FFF
0x01E2 8FFF
0x01EF FFFF
0x01F0 0FFF
0x01F0 1FFF
0x01F0 2FFF
0x01F0 3FFF
0x01F0 4FFF
0x01F0 5FFF
0x01F0 6FFF
0x01F0 7FFF
0x01F0 8FFF
0x01F0 9FFF
0x01F0 AFFF
0x116F FFFF
0x117F FFFF
0x1181 FFFF
0x1183 FFFF
0x11DF FFFF
0x11E0 7FFF
0x11EF FFFF
0x11F0 7FFF
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x67FF FFFF
0x6800 7FFF
0xAFFF FFFF
0xB000 7FFF
4K
McASP 0 Data
4K
4K
4K
McASP 1 Control
McASP 1 AFIFO Ctrl
McASP 1 Data
4K
UART2
4K
4K
Memory Protection Unit 1
Memory Protection Unit 2
8K
4K
4K
4K
EMAC Control Module RAM
EMAC Control Module Registers
EMAC Control Registers
EMAC MDIO port
4K
4K
4K
GPIO
PSC 1
12C 1
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
4K
eHRPWM 0
HRPWM 0
eHRPWM 1
HRPWM 1
eHRPWM 2
HRPWM 2
ECAP 0
ECAP 1
ECAP 2
EQEP 0
EQEP 1
1024K
128K
32K
DSP L2 ROM(2)
DSP L2 RAM
DSP L1P RAM
DSP L1D RAM
32K
32M
32M
EMIFA async data (CS2)
EMIFA async data (CS3)
32K
32K
EMIFA Control Regs
EMIFB Control Regs
(2) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code.
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Device Overview
19
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 2-4. C6743 Top Level Memory Map (continued)
START
ADDRESS
END
ADDRESS
SIZE
DSP MEM MAP
EDMA MEM MAP
PRUSS MEM MAP
MASTER PERIPHERAL
MEM MAP
0xB000 8000
0xC000 0000
0xC800 0000
0xBFFF FFFF
0xC7FF FFFF
0xFFFF FFFF
128M
EMIFB SDRAM Data
20
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
2.5.1 Pin Map (Bottom View)
Figure 2-3 and Figure 2-4 show the pin assignments for ZKB package and PTP packages, respectively.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SPI0_CLK/
EQEP1I/
GP5[2]/
EMA_D[0]/
MMCSD_DAT[0]/
GP0[0]/
EQEP1S/
GP5[7]/
BOOT[7]
AXR1[0]/
GP4[0]
EMA_A[0]/
GP1[0]
EMA_A[4]/
GP1[4]
EMA_A[8]/
GP1[8]
EMA_CS[3]/
GP2[6]
T
R
P
N
M
L
T
R
P
N
M
L
VSS
VSS
VSS
VSS
NC
NC
NC
GP0[9]
BOOT[2]
BOOT[12]
/
SPI0_ENA/
SPI0_SOMI[0]/
EQEP0I/
GP5[0]/
UART0_RXD/
I2C0_SDA
EMA_A[1]/
MMCSD_CLK/
GP1[1]
EMA_D[2]/
MMCSD_DAT[2]/
GP0[2]
EMA_D[1]/
MMCSD_DAT[1]/
GP0[1]
EMA_OE/
AXR0[13]/
GP2[7]
UART0_CTS/
EQEP0A/
GP5[3]/
AXR1[1]/
GP4[1]
UART2_RXD/
GP5[12]
EMA_BA[0]/
GP1[14]
EMA_A[5]/
GP1[5]
EMA_A[9]/
GP1[9]
DVDD
DVDD
GP0[11]
GP0[13]
GP0[15]
NC
NC
NC
GP0[10]
GP0[12]
GP0[14]
NC
TM64P0_IN12/
GP5[8]/BOOT[8]
BOOT[0]
BOOT[3]
SPI0_SIMO[0]/
EQEP0S/
GP5[1]/
UART0_TXD/
I2C0_SCL/
AXR1[3]/
EQEP1A/
GP4[3]
I2C1_SCL/
GP5[5]/
BOOT[5]
EMA_A[2]/
MMCSD_CMD/
GP1[2]
EMA_D[4]/
MMCSD_DAT[4]/
GP0[4]
EMA_D[3]/
MMCSD_DAT[3]/
GP0[3]
EMA_CS[2]/
GP2[5]/
BOOT[15]
AXR1[2]/
GP4[2]
UART2_TXD/
GP5[13]
EMA_BA[1]/
GP1[13]
EMA_A[6]/
GP1[6]
EMA_A[11]/
GP1[11]
TM64P0_OUT12/
GP5[9]/BOOT[9]
BOOT[1]
SPI0_SCS[0]/
UART0_RTS/
EQEP0B/
GP5[4]/
BOOT[4]
AXR1[5]/
EPWM2B/
GP4[5]
AXR1[4]/
EQEP1B/
GP4[4]
I2C1_SDA/
GP5[6]/
BOOT[6]
EMA_D[6]/
MMCSD_DAT[6]/
GP0[6]
EMA_D[5]/
MMCSD_DAT[5]/
GP0[5]
EMA_WAIT[0]/
GP2[10]
EMA_A[10]/
GP1[10]
EMA_A[3]/
GP1[3]
EMA_A[7]/
GP1[7]
EMA_A[12]/
GP1[12]
NC
NC
GP0[8]
DVDD
DVDD
DVDD
CVDD
RVDD
DVDD
DVDD
EMA_WE/
AXR0[12]/
GP2[3]/
EMA_D[7]/
MMCSD_DAT[7]/
GP0[7]/
AXR1[8]/
EPWM1A/
GP4[8]
AXR1[7]/
EPWM1B/
GP4[7]
AXR1[6]/
EPWM2A/
GP4[6]
DVDD
DVDD
DVDD
VSS
VSS
DVDD
VSS
VSS
VSS
VSS
VSS
VSS
DVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
BOOT[14]
BOOT[13]
ACLKR1/
ECAP2/
APWM2/
GP4[12]
AHCLKR1/
GP4[11]
AFSR1/
GP4[13]
CVDD
CVDD
CVDD
VSS
VSS
DVDD
CVDD
CVDD
CVDD
CVDD
DVDD
VSS
EMB_CAS
NC
NC
NC
AFSX1/
EPWMSYNCI/
EPWMSYNCO/
GP4[10]
AHCLKX1/
EPWM0B/
GP3[14]
ACLKX1/
EPWM0A/
GP3[15]
EMB_WE_
DQM[0]/
GP5[15]
K
J
K
J
GP7[14]
TMS
CVDD
CVDD
CVDD
CVDD
RSV1
CVDD
CVDD
CVDD
CVDD
VSS
EMB_WE
NC
NC
EMB_D[5]/
GP6[5]
EMB_D[6]/
GP6[6]
EMB_D[7]/
GP6[7]
EMU0/
GP7[15]
TDI
TDO
TCK
TRST
NC
NC
NC
NC
NC
EMB_D[3]/
GP6[3]
EMB_D[4]/
GP6[4]
H
G
F
H
G
F
RSV4
RV
DD
NC
NC
VSS
VSS
NC
NC
NC
NC
NC
EMB_D[1]/
GP6[1]
EMB_D[2]/
GP6[2]
CVDD
VSS
RESET
DV
DD
CV
DD
EMB_D[15]/
GP6[15]
EMB_D[0]/
GP6[0]
OSCOUT
PLL0_VSSA
PLL0_VDDA
OSCIN
OSCVSS
DV
DD
CV
DD
NC
NC
NC
NC
VSS
EMB_D[13]/
GP6[13]
EMB_D[14]/
GP6[14]
E
D
C
B
A
E
D
C
B
A
DV
DD
VSS
VSS
DV
DD
DV
DD
VSS
DV
DD
NC
AMUTE1/
EPWMTZ/
GP4[14]
AFSX0/
GP2[13]/
BOOT[10]
AXR0[6]/ AXR0[2]/
RMII_RXER/ RMII_TXEN/ EMB_CS[0]
AXR0[10]/
GP3[10]
EMB_A[0]/
GP7[2]
EMB_A[4]/
GP7[6]
EMB_A[8]/
GP7[10]
EMB_D[9]/
GP6[9]
EMB_D[10]/ EMB_D[11]/ EMB_D[12]/
GP6[12]
NC
NC
VSS
GP6[10]
GP6[11]
GP3[6]
GP3[2]
ACLKX0/
ECAP0/
APWM0/
GP2[12]
AXR0[5]/ AXR0[1]/
RMII_RXD[1]/ RMII_TXD[1]/
GP3[5]
EMB_WE_
DQM[1]/
GP5[14]
AFSR0/
GP3[12]
AXR0[9]/
GP3[9]
EMB_BA[0]/
GP7[1]
EMB_A[1]/
GP7[3]
EMB_A[5]/
GP7[7]
EMB_A[9]/
GP7[11]
EMB_D[8]/
GP6[8]
EMB_SDCKE EMB_CLK
NC
GP3[1]
ACLKR0/
ECAP1/
APWM1/
GP2[15]
AHCLKX0/
AHCLKX2/
GP2[11]
AXR0[8]/
MDIO_D/
GP3[8]
AXR0[4]/ AXR0[0]/
RMII_RXD[0]/ RMII_TXD[0]/
GP3[4]
EMB_BA[1]/
GP7[0]
EMB_A[2]/
GP7[4]
EMB_A[6]/
GP7[8]
EMB_A[11]/
GP7[13]
EMB_A[12]/
GP3[13]
RSV2
DVDD
NC
NC
GP3[0]
AHCLKR0/
RMII_MHZ_
50_CLK/
GP2[14]/
BOOT[11]
AXR0[7]/
MDIO_CLK/ RMII_CRS_DV/
GP3[7]
AXR0[3]/
AXR0[11]/
GP3[11]
EMB_A[10]/
GP7[12]
EMB_A[3]/
GP7[5]
EMB_A[7]/
GP7[9]
VSS
VSS
VSS
VSS
VSS
EMB_RAS
8
NC
12
NC
13
NC
14
GP3[3]
1
Note: NC = No Connect
2
3
4
5
6
7
9
10
11
15
16
Figure 2-3. Pin Map (ZKB)
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
21
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
RSV2
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
EMB_SDCKE
DVDD
NC
NC
EMB_CLK
NC
EMB_WE_DQM[1]/GP5[14]
EMB_D[8]/GP6[8]
EMB_D[9]/GP6[9]
EMB_D[10]/GP6[10]
DVDD
NC
NC
NC
NC
PLL0_VDDA
EMB_D[11]/GP6[11]
EMB_D[12]/GP6[12]
EMB_D[13]/GP6[13]
CVDD
PLL0_VSSA
OSCIN
OSCVSS
OSCOUT
EMB_D[14]/GP6[14]
DVDD
RESET
CVDD
EMB_D[15]/GP6[15]
EMB_D[0]/GP6[0]
EMB_D[1]/GP6[1]
DVDD
RSV4
RSV3
TRST
DVDD
EMB_D[2]/GP6[2]
CVDD
TMS
TDI
EMB_D[3]/GP6[3]
RVDD
CVDD
Thermal Pad
(177)
TCK
EMB_D[4]/GP6[4]
DVDD
TDO
GP7[14]
EMB_D[5]/GP6[5]
EMB_D[6]/GP6[6]
EMB_D[7]/GP6[7]
CVDD
DVDD
RVDD
AHCLKX1/EPWM0B/GP3[14]
CVDD
EMB_WE_DQM[0]/GP5[15]
EMB_WE
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]
DVDD
DVDD
EMB_CAS
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
CVDD
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
DVDD
CVDD
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
DVDD
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
CVDD
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
DVDD
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
AXR1[1]/GP4[1]
Figure 2-4. Pin Map (PTP)
22
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6 Terminal Functions
Table 2-5 to Section 2.6.18 identify the external signal names, the associated pin/ball numbers along with
the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any
internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a
functional pin description.
2.6.1 Device Reset and JTAG
Table 2-5. Reset and JTAG Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
RESET
MUXED
DESCRIPTION
PTP
ZKB
RESET
146
G3
I
Device reset input
JTAG
IPU
IPU
IPU
IPU
IPD
IPD
TMS
TDI
152
153
156
155
150
-
J1
J2
J3
H3
J4
J5
I
I
JTAG test mode select
JTAG test data input
JTAG test data output
JTAG test clock
TDO
TCK
TRST
O
I
I
JTAG test reset
EMU0/GP7[15]
I/O
GPIO
Emulation Signal
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.6.2 High-Frequency Oscillator and PLL
Table 2-6. High-Frequency Oscillator and PLL Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
PULL(2)
DESCRIPTION
PTP
ZKB
1.2-V OSCILLATOR
OSCIN
143
145
144
F2
F1
E2
I
Oscillator input
Oscillator output
OSCOUT
OSCVSS
O
GND
Oscillator ground (for filter only)
1.2-V PLL
PLL0_VDDA
PLL0_VSSA
141
142
D1
E1
PWR
GND
PLL analog VDD (1.2-V filtered supply)
PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
23
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.6.3 External Memory Interface A (ASYNC)
Table 2-7. External Memory Interface A (EMIFA) Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M15
N13
N15
P13
P15
R13
R15
T13
N11
P11
N8
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
EMA_A[12]/GP1[12]
54
52
51
49
48
46
45
44
42
41
27
40
39
37
36
35
34
32
31
30
29
26
25
21
23
55
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
MMC/SD, GPIO, BOOT
MMC/SD, GPIO
EMIFA data bus
MMC/SD, GPIO, BOOT
EMA_A[11]/ GP1[11]
O
EMA_A[10]/GP1[10]
O
EMA_A[9]/GP1[9]
R11
T11
N10
P10
R10
T10
N9
O
EMA_A[8]/GP1[8]
O
GPIO
EMIFA address bus
EMA_A[7]/GP1[7]
O
EMA_A[6]/GP1[6]
O
EMA_A[5]/GP1[5]
O
EMA_A[4]/GP1[4]
O
EMA_A[3]/GP1[3]
O
EMA_A[2]/MMCSD_CMD/GP1[2]
EMA_A[1]/MMCSD_CLK/GP1[1]
EMA_A[0]/GP1[0]
P9
O
MMCSD, GPIO
GPIO
R9
O
EMIFA address bus
T9
O
EMA_BA[1]/GP1[13]
P8
O
EMIFA bank
address
EMA_BA[0]/GP1[14]
R8
O
EMA_CS[3] /GP2[6]
T7
O
GPIO
EMIFA Async Chip
Select
EMA_CS[2] /GP2[5]/BOOT[15]
EMA_WE /AXR0[12]/GP2[3]/BOOT[14]
P7
O
GPIO, BOOT
M13
O
MCASP0, GPIO, BOOT EMIFA write enable
EMIFA output
EMA_OE /AXR0[13]/GP2[7]
EMA_WAIT[0]/ GP2[10]
22
19
R7
N6
O
I
IPU
IPU
McASP0, GPIO
enable
EMIFA wait
input/interrupt
GPIO
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
24
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6.4 External Memory Interface B (SDRAM only)
Table 2-8. External Memory Interface B (EMIFB) Terminal Functions
PIN NO
PTP
SIGNAL NAME
EMB_D[15]/GP6[15]
TYPE(1)
PULL(2)
MUXED
DESCRIPTION
ZKB
F13
E16
E13
D16
D15
D14
D13
C16
J16
J15
J13
H16
H13
G16
G13
F16
B15
B12
A9
74
76
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
EMB_D[14]/GP6[14]
EMB_D[13]/GP6[13]
EMB_D[12]/GP6[12]
EMB_D[11]/GP6[11]
EMB_D[10]/GP6[10]
EMB_D[9]/GP6[9]
EMB_D[8]/GP6[8]
EMB_D[7]/GP6[7]
EMB_D[6]/GP6[6]
EMB_D[5]/GP6[5]
EMB_D[4]/GP6[4]
EMB_D[3]/GP6[3]
EMB_D[2]/GP6[2]
EMB_D[1]/GP6[1]
EMB_D[0]/GP6[0]
EMB_A[12]/GP3[13]
EMB_A[11]/GP7[13]
EMB_A[10]/GP7[12]
EMB_A[9]/GP7[11]
EMB_A[8]/GP7[10]
EMB_A[7]/GP7[9]
EMB_A[6]/GP7[8]
EMB_A[5]/GP7[7]
EMB_A[4]/GP7[6]
EMB_A[3]/GP7[5]
EMB_A[2]/GP7[4]
EMB_A[1]/GP7[3]
EMB_A[0]/GP7[2]
EMB_BA[1]/GP7[0]
EMB_BA[0]/GP7[1]
EMB_CLK
78
79
80
82
83
84
GPIO
EMIFB SDRAM data bus
62
63
64
66
68
70
72
73
89
91
O
105
92
O
C12
D12
A11
B11
C11
D11
A10
B10
C10
D10
B9
O
EMIFB SDRAM row/column address
bus
GPIO
94
O
95
O
96
O
97
O
98
O
100
101
102
103
106
107
86
O
O
EMIFB SDRAM row/column address
EMIFB SDRAM bank address
O
GPIO
O
O
C9
O
C14
C13
K15
A8
O
EMIF SDRAM clock
EMB_SDCKE
88
O
EMIFB SDRAM clock enable
EMIFB write enable
EMB_WE
59
I/O
O
GPIO
GPIO
EMB_RAS
110
57
EMIFB SDRAM row address strobe
EMIFB column address strobe
EMIFB SDRAM chip select 0
EMB_CAS
L13
D9
O
EMB_CS[0]
108
85
O
EMB_WE_DQM[1]
EMB_WE_DQM[0]
C15
K14
O
EMIFB write enable/data mask for
EMB_D
60
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
25
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.6.5 Serial Peripheral Interface Modules (SPI0)
Table 2-9. Serial Peripheral Interface (SPI) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
ZKB
SPI0
UART0, EQEP0B,
GPIO, BOOT
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
9
N4
I/O
IPU
SPI0 chip select
SPI0 enable
UART0, EQEP0A,
GPIO, BOOT
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
12
11
18
R5
T5
P6
I/O
I/O
I/O
IPU
IPD
IPD
eQEP1, GPIO, BOOT SPI0 clock
SPI0 data slave-in-
master-out
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
eQEP0, GPIO, BOOT
eQEP0, GPIO, BOOT
SPI0 data slave-
out-master-in
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
17
R6
I/O
IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.6.6 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 2-10. Enhanced Capture Module (eCAP) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
eCAP0
MUXED
DESCRIPTION
PTP
ZKB
enhanced capture 0 input or
auxiliary PWM 0 output
ACLKX0/ECAP0/APWM0/GP2[12]
ACLKR0/ECAP1/APWM1/GP2[15]
ACLKR1/ECAP2/APWM2/GP4[12]
126
C5
I/O
IPD
IPD
IPD
McASP0, GPIO
McASP0, GPIO
McASP1, GPIO
eCAP1
I/O
enhanced capture 1 input or
auxiliary PWM 1 output
130
B4
eCAP2
I/O
enhanced capture 2 input or
auxiliary PWM 2 output
165
L2
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
26
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6.7 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 2-11. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
ZKB
eHRPWM0
eHRPWM0 A output (with
high-resolution)
ACLKX1/EPWM0A/GP3[15]
162
160
K3
K2
I/O
I/O
IPD
IPD
McASP1, GPIO
AHCLKX1/EPWM0B/GP3[14]
AMUTE1/EPWMTZ/GP4[14]
eHRPWM0 B output
McASP1,
eHRPWM1, GPIO,
eHRPWM2
132
163
D4
K4
I/O
I/O
IPD
IPD
eHRPWM0 trip zone input
Sync input to eHRPWM0
module or sync output to
external PWM
McASP1,
eHRPWM0, GPIO
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
eHRPWM1
eHRPWM1 A (with high-
resolution)
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
168
169
M2
I/O
I/O
IPD
IPD
McASP1, GPIO
M3
D4
eHRPWM1 B output
McASP1,
eHRPWM0, GPIO,
eHRPWM2
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
eHRPWM1 trip zone input
eHRPWM2
eHRPWM2 A (with high-
resolution)
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
170
171
M4
I/O
I/O
IPD
IPD
McASP1, GPIO
N1
D4
eHRPWM2 B output
McASP1,
eHRPWM0, GPIO,
eHRPWM2
AMUTE1/EPWMTZ/GP4[14]
132
I/O
IPD
eHRPWM2 trip zone input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
27
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.6.8 Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 2-12. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
ZKB
eQEP0
eQEP0A quadrature
input
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
12
9
R5
N4
I
I
IPU
IPU
SPIO, UART0,
GPIO, BOOT
eQEP0B quadrature
input
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
17
18
R6
I
I
IPD
IPD
eQEP0 index
eQEP0 strobe
SPI0, GPIO, BOOT
McASP1, GPIO
P6
eQEP1
eQEP1A quadrature
input
AXR1[3]/EQEP1A/GP4[3]
AXR1[4]/EQEP1B/GP4[4]
174
173
P1
N2
I
I
IPD
IPD
eQEP1B quadrature
input
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
EQEP1S/GP5[7]/BOOT[7]
11
16
T5
T6
I
I
IPD
IPD
SPI0, GPIO, BOOT eQEP1 index
GPIO, BOOT eQEP1 strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
28
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6.9 Boot
Table 2-13. Boot Terminal Functions(1)
PIN NO
SIGNAL NAME
TYPE(2) PULL(3)
MUXED
DESCRIPTION
PTP
ZKB
EMA_CS[2]/GP2[5]/BOOT[15]
23
P7
I
I
IPU
IPU
EMIFA, GPIO
BOOT[15]
BOOT[14]
EMIFA, McASP0,
GPIO
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
55
M13
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
54
44
M15
T13
I
I
IPU
IPU
BOOT[13]
BOOT[12]
EMIFA, MMC/SD,
GPIO
McASP0, EMAC,
GPIO
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
AFSX0/GP2[13]/BOOT[10]
129
127
3
A4
D5
P3
I
I
I
IPD
IPD
IPU
BOOT[11]
BOOT[10]
BOOT[9]
McASP0, GPIO
UART0, I2C0,
Timer0, GPIO
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
UART0, I2C0,
Timer0, GPIO
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
2
R3
I
IPU
BOOT[8]
EQEP1S/GP5[7]/BOOT[7]
I2C1_SDA/GP5[6]/BOOT[6]
I2C1_SCL/GP5[5]/BOOT[5]
16
14
13
T6
N5
P5
I
I
I
IPD
IPU
IPU
eQEP1, GPIO
BOOT[7]
BOOT[6]
BOOT[5]
I2C1, GPIO
SPI0, UART0,
eQEP0, GPIO
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3]
9
N4
R5
I
I
IPU
IPU
BOOT[4]
BOOT[3]
SPI0, UART0,
eQEP0, GPIO
12
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
11
18
17
T5
P6
R6
I
I
I
IPD
IPD
IPD
SPIO, eQEP1, GPIO BOOT[2]
BOOT[1]
SPI0, eQEP0, GPIO
BOOT[0]
(1) Boot decoding will be defined in the ROM datasheet.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
29
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART2)
Table 2-14. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
ZKB
UART0
I2C0, BOOT,
Timer0, GPIO,
UART0 receive
data
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4]
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3]
2
3
R3
P3
N4
R5
I
IPU
IPU
IPU
IPU
I2C0, Timer0,
GPIO, BOOT
UART0 transmit
data
O
O
I
UART0 ready-to-
send output
9
SPIO, eQEP0,
GPIO, BOOT
UART0 clear-to-
send input
12
UART2
UART2 receive
data
UART2_RXD/GP5[12]
UART2_TXD/GP5[13]
7
8
R4
P4
I
IPU
IPU
GPIO
UART2 transmit
data
O
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.6.11 Inter-Integrated Circuit Modules (I2C0, I2C1)
Table 2-15. Inter-Integrated Circuit (I2C) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
ZKB
I2C0
UART0, Timer0,
GPIO, BOOT
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
2
3
R3
P3
I/O
I/O
IPU
IPU
I2C0 serial data
I2C0 serial clock
UART0, Timer0,
GPIO, BOOT
I2C1
I2C1_SDA/GP5[6]/BOOT[6]
I2C1_SCL/GP5[5]/BOOT[5]
14
13
N5
P5
I/O
I/O
IPU
IPU
I2C1 serial data
I2C1 serial clock
GPIO, BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
30
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6.12 Timers
Table 2-16. Timers Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
ZKB
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
2
3
R3
I
IPU
IPU
Timer0 lower input
UART0, I2C0,
GPIO, BOOT
Timer0 lower
output
P3
O
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
Table 2-17. Multichannel Audio Serial Ports (McASPs) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2) MUXED
DESCRIPTION
PTP
ZKB
McASP0
EMA_OE/AXR0[13]/GP2[7]
22
R7
M13
A5
D6
C6
B6
A6
D7
C7
B7
A7
D8
C8
B8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPU
IPU
IPD
IPD
IPD
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
EMIFA, GPIO
EMIFA, GPIO, BOOT
GPIO
EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
AXR0[11]/ GP3[11]
55
124
123
122
121
120
118
117
116
115
113
112
111
AXR0[10]/GP3[10]
GPIO
AXR0[9]/GP3[9]
GPIO
AXR0[8]/MDIO_D/GP3[8]
AXR0[7]/MDIO_CLK/GP3[7]
AXR0[6]/RMII_RXER/GP3[6]
AXR0[5]/RMII_RXD[1]/GP3[5]
AXR0[4]/RMII_RXD[0]/GP3[4]
AXR0[3]/RMII_CRS_DV/GP3[3]
AXR0[2]/RMII_TXEN/GP3[2]
AXR0[1]/RMII_TXD[1]/GP3[1]
AXR0[0]/RMII_TXD[0]/GP3[0]
MDIO, GPIO
McASP0 serial data
EMAC, GPIO
McASP0 transmit
master clock
AHCLKX0/GP2[11]
125
126
127
129
130
131
B5
C5
D5
A4
B4
C4
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
GPIO
McASP0 transmit bit
clock
ACLKX0/ECAP0/APWM0/GP2[12]
AFSX0/GP2[13]/BOOT[10]
eCAP0, GPIO
GPIO, BOOT
EMAC, GPIO, BOOT
eCAP1, GPIO
GPIO
McASP0 transmit
frame sync
McASP0 receive
master clock
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
ACLKR0/ECAP1/APWM1/GP2[15]
AFSR0/GP3[12]
McASP0 receive bit
clock
McASP0 receive frame
sync
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
31
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 2-17. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN NO
PTP ZKB
McASP1
SIGNAL NAME
TYPE(1) PULL(2) MUXED
DESCRIPTION
AXR1[8]/EPWM1A/GP4[8]
168
169
170
171
173
174
175
176
1
M2
M3
M4
N1
N2
P1
P2
R2
T3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
eHRPWM1 A, GPIO
eHRPWM1 B, GPIO
eHRPWM2 A, GPIO
eHRPWM2 B, GPIO
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
McASP1 serial data
eQEP, GPIO
AXR1[1]/GP4[1]
GPIO
AXR1[0]/GP4[0]
McASP1 transmit
master clock
AHCLKX1/EPWM0B/GP3[14]
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
AHCLKR1/GP4[11]
160
162
163
-
K2
K3
K4
L1
L2
L3
I/O
I/O
I/O
I/O
I/O
I/O
IPD
IPD
IPD
IPD
IPD
IPD
eHRPWM0, GPIO
eHRPWM0, GPIO
eHRPWM0, GPIO
GPIO
McASP1 transmit bit
clock
McASP1 transmit
frame sync
McASP1 receive
master clock
McASP1 receive bit
clock
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
165
166
eCAP2, GPIO
GPIO
McASP1 receive frame
sync
eHRPWM0,
AMUTE1/EPWMTZ/GP4[14]
132
D4
O
IPD
eHRPWM1, GPIO,
eHRPWM2
McASP1 mute output
32
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6.14 Ethernet Media Access Controller (EMAC)
Table 2-18. Ethernet Media Access Controller (EMAC) Terminal Functions
PIN NO
PTP ZKB
RMII
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
McASP0, GPIO,
BOOT
EMAC 50-MHz clock
input or output
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
129
A4
I/O
IPD
AXR0[6]/RMII_RXER/GP3[6]
AXR0[5]/RMII_RXD[1]/GP3[5]
AXR0[4]/RMII_RXD[0]/GP3[4]
118
117
116
D7
C7
B7
I
I
I
IPD
IPD
IPD
EMAC RMII receiver error
EMAC RMII receive data
EMAC RMII carrier sense
data valid
AXR0[3]/RMII_CRS_DV/GP3[3]
AXR0[2]/RMII_TXEN/GP3[2]
115
113
A7
D8
I
IPD
IPD
McASP0, GPIO
EMAC RMII transmit
enable
O
AXR0[1]/RMII_TXD[1]/GP3[1]
AXR0[0]/RMII_TXD[0]/GP3[0]
112
111
C8
B8
O
O
IPD
IPD
EMAC RMII trasmit data
MDIO
AXR0[8]/MDIO_D/GP3[8]
121
120
B6
A6
I/O
O
IPU
IPD
MDIO serial data
MDIO data clock
McASP0, GPIO
AXR0[7]/MDIO_CLK/GP3[7]
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
2.6.15 Multimedia Card/Secure Digital (MMC/SD)
Table 2-19. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
PTP
30
31
54
52
51
49
48
46
45
44
ZKB
R9
EMA_A[1]/MMCSD_CLK/GP1[1]
O
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
MMCSD_CLK
MMCSD_CMD
EMIFA, GPIO
EMA_A[2]/MMCSD_CMD/GP1[2]
P9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
EMA_D[6]/MMCSD_DAT[6]/GP0[6]
EMA_D[5]/MMCSD_DAT[5]/GP0[5]
EMA_D[4]/MMCSD_DAT[4]/GP0[4]
EMA_D[3]/MMCSD_DAT[3]/GP0[3]
EMA_D[2]/MMCSD_DAT[2]/GP0[2]
EMA_D[1]/MMCSD_DAT[1]/GP0[1]
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
M15
N13
N15
P13
P15
R13
R15
T13
EMIFA, GPIO, BOOT
EMIFA, GPIO
MMC/SD data
EMIFA, GPIO, BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
33
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2.6.16 General-Purpose IO Only Terminal Functions
Table 2-20. General-Purpose IO Only Terminal Functions
PIN NO
PTP
SIGNAL NAME
TYPE(1) PULL(2)
MUXED
DESCRIPTION
ZKB
M16
N14
N16
P14
P16
R14
T14
N12
-
GP0[15]
GP0[14]
GP0[13]
GP0[12]
GP0[11]
GP0[10]
GP0[9]
-
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
-
-
-
-
-
None
General-Purpose IO
-
-
GP0[8]
GP5[11]
GP5[10]
GP7[14](3)
6
4
-
157
-
K1
EMU0/GP7[15]
J5
I/O
Emulation
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (i.e., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will be stable only after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
2.6.17 Reserved and No Connect Terminal Functions
Table 2-21. Reserved and No Connect Terminal Functions
PIN NO
SIGNAL NAME
RSV1
TYPE(1)
DESCRIPTION
PTP
ZKB
Reserved. (Leave unconnected, do not connect to power or
-
F7
-
ground.)
Reserved. For proper device operation, this pin must be tied
either directly to CVDD or left unconnected (do not connect to
ground).
RSV2
133
B1
PWR
Reserved. For proper device operation, this pin must be tied
RSV3
RSV4
149
148
-
PWR
I
directly to CVDD
.
H1
Reserved. This pin may be tied high or low.
A12, A13, A14, B13,
B14, C1, C2, C3, D2,
D3, E3, E4, E14, E15,
F14, F15, G14, G15, H2,
H5, H14, H15, J14, K13,
K16, L4, L14, L15, L16,
M1, M14, N3, N7, P12,
R12, T4, T8, T12
134, 135,
137, 138,
140
-
-
No Connect (leave unconnected)
NC
136, 139
F3, H4,
This pin may be left unconnected or connected to VSS.
(1) PWR = Supply voltage.
34
Device Overview
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
2.6.18 Supply and Ground Terminal Functions
Table 2-22. Supply and Ground Terminal Functions
PIN NO
SIGNAL NAME
TYPE(1)
DESCRIPTION
PTP
ZKB
F6, G1, G6, G7, G10,
G11, H7, H10, H11, J6,
J7, J10, J11, J12, K6,
K7, K10, K11, L6
10, 20, 28, 38, 50, 56,
61, 69, 77, 93, 104,
114, 147, 154, 161, 167
CVDD (Core supply)
PWR
PWR
1.2-V core supply voltage pins
1.2V internal ram supply voltage
pins
RVDD (Internal RAM supply)
DVDD (I/O supply)
67, 159
H6, H12
5, 15, 24, 33, 43, 47,
53, 58, 65, 71, 75, 81,
87, 90, 99, 109, 119,
128, 151, 158, 164,
172,
B16, E5, E8, E9, E12,
F5, F11, F12, G5, G12,
K5, K12, L5, L11, L12,
M5, M8, M9, M12, R1,
R16
PWR
3.3-V I/O supply voltage pins.
A1, A2, A3, A15, A16,
B2, B3, E6, E7, E10,
E11, F4, F8, F9, F10,
G2, G4, G8, G9, H8,
H9, J8, J9, K8, K9, L7,
L8, L9, L10, M6, M7,
M10, M11, T1, T2, T15,
T16
VSS (Ground)
177
GND
Ground pins.
(1) PWR = Supply voltage, GND - Ground.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Overview
35
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
3 Device Configuration
3.1 Boot Modes
This device supports a variety of boot modes through an internal ROM bootloader. This device does not
support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input
states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system
configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by
the values of the BOOT pins.
See Using the D800K001 Bootloader Application Report (SPRAB04) for more details on the ROM Boot
Loader.
The following boot modes are supported:
•
NAND Flash boot
8-bit NAND
NOR Flash boot
–
•
–
–
–
NOR Direct boot (8-bit)
NOR Legacy boot (8-bit)
NOR AIS boot (8-bit)
•
•
I2C0 / I2C1 Boot
–
–
EEPROM (Master Mode)
External Host (Slave Mode)
SPI0 Boot
–
–
–
Serial Flash (Master Mode)
SERIAL EEPROM (Master Mode)
External Host (Slave Mode)
•
UART0 / UART2 Boot
External Host
–
3.2 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
•
•
•
•
•
Readable Device, Die, and Chip Revision ID
Control of Pin Multiplexing
Priority of bus accesses different bus masters in the system
Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
Special case settings for peripherals:
–
–
–
–
Locking of PLL controller settings
Default burst sizes for EDMA3 TC0 and TC1
Selection of the source for the eCAP module input capture (including on chip sources)
Clock source selection for EMIFA and EMIFB
•
Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function.
Since the SYSCFG peripheral controls global operation of the device, its registers are protected against
erroneous accesses by several mechanisms:
•
A special key sequence must be written to KICK0, KICK1 registers before any other registers are
writeable.
•
Additionally, many registers are accessible only by a host (DSP) when it is operating in its privileged
mode. (ex. from the kernel, but not from user space code).
36
Device Configuration
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 3-1. System Configuration (SYSCFG) Module Register Access
BYTE ADDRESS
REGISTER NAME
REVID
REGISTER DESCRIPTION
Revision Identification Register
ACCESS
—
0x01C1 4000
0x01C1 4008
0x01C1 400C
0x01C1 4010
0x01C1 4014
0x01C1 4018
0x01C1 4020
0x01C1 4024
0x01C1 4038
0x01C1 403C
0x01C1 4040
0x01C1 4044
0x01C1 40E0
0x01C1 40E4
0x01C1 40E8
0x01C1 40EC
0x01C1 40F0
0x01C1 40F4
0x01C1 40F8
0x01C1 4110
0x01C1 4114
0x01C1 4118
0x01C1 4120
0x01C1 4124
0x01C1 4128
0x01C1 412C
0x01C1 4130
0x01C1 4134
0x01C1 4138
0x01C1 413C
0x01C1 4140
0x01C1 4144
0x01C1 4148
0x01C1 414C
0x01C1 4150
0x01C1 4154
0x01C1 4158
0x01C1 415C
0x01C1 4160
0x01C1 4164
0x01C1 4168
0x01C1 416C
0x01C1 4170
0x01C1 4174
0x01C1 4178
0x01C1 417C
0x01C1 4180
DIEIDR0
Device Identification Register 0
Device Identification Register 1
Device Identification Register 2
Device Identification Register 3
JTAG Identification Register
Boot Configuration Register
—
DIEIDR1
—
DIEIDR2
—
DIEIDR3
—
DEVIDR0
BOOTCFG
CHIPREVID
KICK0R
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
Silicon Revision Identification Register
Kick 0 Register
KICK1R
Kick 1 Register
HOST0CFG
HOST1CFG
IRAWSTAT
IENSTAT
IENSET
Host 0 Configuration Register
Host 1 Configuration Register
Interrupt Raw Status/Set Register
Interrupt Enable Status/Clear Register
Interrupt Enable Register
—
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
IENCLR
Interrupt Enable Clear Register
End of Interrupt Register
EOI
FLTADDRR
FLTSTAT
MSTPRI0
MSTPRI1
MSTPRI2
PINMUX0
PINMUX1
PINMUX2
PINMUX3
PINMUX4
PINMUX5
PINMUX6
PINMUX7
PINMUX8
PINMUX9
PINMUX10
PINMUX11
PINMUX12
PINMUX13
PINMUX14
PINMUX15
PINMUX16
PINMUX17
PINMUX18
PINMUX19
SUSPSRC
CHIPSIG
Fault Address Register
Fault Status Register
Master Priority 0 Register
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
Privileged mode
—
Master Priority 1 Register
Master Priority 2 Register
Pin Multiplexing Control 0 Register
Pin Multiplexing Control 1 Register
Pin Multiplexing Control 2 Register
Pin Multiplexing Control 3 Register
Pin Multiplexing Control 4 Register
Pin Multiplexing Control 5 Register
Pin Multiplexing Control 6 Register
Pin Multiplexing Control 7 Register
Pin Multiplexing Control 8 Register
Pin Multiplexing Control 9 Register
Pin Multiplexing Control 10 Register
Pin Multiplexing Control 11 Register
Pin Multiplexing Control 12 Register
Pin Multiplexing Control 13 Register
Pin Multiplexing Control 14 Register
Pin Multiplexing Control 15 Register
Pin Multiplexing Control 16 Register
Pin Multiplexing Control 17 Register
Pin Multiplexing Control 18 Register
Pin Multiplexing Control 19 Register
Suspend Source Register
Chip Signal Register
CHIPSIG_CLR
CFGCHIP0
CFGCHIP1
Chip Signal Clear Register
—
Chip Configuration 0 Register
Chip Configuration 1 Register
Privileged mode
Privileged mode
Copyright © 2009–2013, Texas Instruments Incorporated
Device Configuration
37
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 3-1. System Configuration (SYSCFG) Module Register Access (continued)
BYTE ADDRESS
0x01C1 4184
0x01C1 4188
0x01C1 418C
REGISTER NAME
CFGCHIP2
REGISTER DESCRIPTION
Chip Configuration 2 Register
ACCESS
Privileged mode
Privileged mode
Privileged mode
CFGCHIP3
Chip Configuration 3 Register
Chip Configuration 4 Register
CFGCHIP4
3.3 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
•
Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
•
Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
•
•
Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
•
•
•
Remember to include tolerances when selecting the resistor value.
For pullup resistors, also remember to include tolerances on the IO supply rail.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
•
For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
•
•
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see Section 4.2, Recommended Operating Conditions.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
38
Device Configuration
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Copyright © 2009–2013, Texas Instruments Incorporated
Device Configuration
39
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
4 Device Operating Conditions
4.1 Absolute Maximum Ratings Over Operating Junction Temperature Range
(1)
(Unless Otherwise Noted)
Core
-0.5 V to 1.4 V
-0.5 V to 3.8V
(2)
(CVDD, RVDD, PLL0_VDDA )
Supply voltage ranges
I/O, 3.3V
(DVDD)
(2)
VI I/O, 1.2V
(OSCIN)
-0.3 V to CVDD + 0.35V
-0.3V to DVDD + 0.3V
VI I/O, 3.3V
Input voltage ranges
(Steady State)
VI I/O, 3.3V
(Transient Overshoot/Undershoot)
20% of DVDD for up to
20% of the signal period
VO I/O, 3.3V
-0.5 V to DVDD + 0.3V
(Steady State)
Output voltage ranges
VO I/O, 3.3V
20% of DVDD for up to
20% of the signal period
(Transient Overshoot/Undershoot )
Input or Output Voltages 0.3V above or below their respective power
±20mA
Clamp Current
rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
(default)
0°C to 90°C
-40°C to 125°C
-55°C to 150°C
>2000V
Operating Junction Temperature ranges,
TJ
(T version)
Storage temperature range, Tstg
(default)
Human Body Model (HBM)(4)
Charged Device Model (CDM)(5)
(3)
ESD Stress Voltage, VESD
>500V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS
(3) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(4) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary
precautions are taken. Pins listed as 1000V may actually have higher performance.
(5) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.
40
Device Operating Conditions
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
4.2 Recommended Operating Conditions
MIN
1.14
1.14
3.0
NOM
1.2
MAX UNIT
Supply voltage, Core
CVDD
1.32
1.32
3.45
V
V
V
(CVDD, PLL0_VDDA )
RVDD
DVDD
Supply Voltage, Internal RAM
1.2
Supply voltage, I/O, 3.3V
(DVDD)
3.3
Supply ground
VSS
VIH
0
0
0
V
(VSS, PLL0_VSSA, OSCVSS(1)
)
High-level input voltage, I/O, 3.3V
High-level input voltage, OSCIN
Low-level input voltage, I/O, 3.3V
Low-level input voltage, OSCIN
Input Hysteresis
2
V
V
0.7*CVDD
0.8
V
VIL
0.3*CVDD
V
VHYS
tt
160
mV
Transition time, 10%-90%, All Inputs (unless otherwise
specified in the electrical data sections)
0.25P or 10(2)
90
ns
°C
Default
0
-40
0
TJ
Operating junction temperature range
DSP Operating Frequency (SYSCLK1,6)
Automotive
(T suffix)
125
°C
Default
375 or 200
375 or 200
MHz
MHz
FSYSCLK1,6
Automotive
(T suffix)
0
(1) When an external crystal is used oscillator (OSC_VSS) ground must be kept separate from other grounds and connected directly to the
crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on the circuit
board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(2) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Operating Conditions
41
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
4.3 Notes on Recommended Power-On Hours (POH)
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
To avoid significant degradation, the device power-on hours (POH) must be limited to the following:
Table 4-1. Recommended Power-On Hours
SILICON
REVISION
OPERATING JUNCTION
TEMPERATURE (Tj)
POWER-ON HOURS [POH]
(HOURS)
SPEED GRADE
NOMINAL CVDD VOLTAGE (V)
A
B
B
B
B
300 MHZ
200 MHZ
200 MHZ
375 MHz
375 MHZ
0 to 90 °C
0 to 90 °C
1.2V
1.2V
1.2V
1.2V
1.2V
100,000
100,000
20,000
-40° to 125°
0 to 90 °C
100,000
20,000
-40 to 125 °C
Note: Logic functions and parameter values are not assured out of the range specified in the recommended
operating conditions.
The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under
TI’s standard terms and conditions for TI semiconductor products.
42
Device Operating Conditions
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
4.4 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Junction Temperature (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
DVDD= 3.15V, IOH = 4 mA
DVDD= 3.15V, IOH = 100 μA
DVDD= 3.15V, IOL = -4mA
DVDD= 3.15V, IOL = -100 μA
MIN
2.4
TYP
MAX UNIT
V
V
VOH
High-level output voltage (3.3V I/O)
2.95
0.4
0.2
V
V
VOL
Low-level output voltage (3.3V I/O)
Input current
VI = VSS to DVDD without opposing
internal resistor
±35
-200
300
μA
μA
μA
VI = VSS to DVDD with opposing
(1)
II
-30
50
(2)
internal pullup resistor
VI = VSS to DVDD with opposing
(2)
internal pulldown resistor
IOH
IOL
High-level output current
Low-level output current
All peripherals
All peripherals
-4
4
mA
mA
VO = VDD or VSS; Internal pull
disabled
(3)
IOZ
I/O Off-state output current
±35
μA
LVCMOS signals
OSCIN
3
2
3
pF
pF
pF
CI
Input capacitance
Output capacitance
CO
LVCMOS signals
(1) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(3) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
Copyright © 2009–2013, Texas Instruments Incorporated
Device Operating Conditions
43
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5 Peripheral Information and Electrical Specifications
5.1 Parameter Information
5.1.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 5-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.2 V I/O, Vref = 0.6 V.
V
ref
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
44
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
5.3 Power Supplies
5.3.1 Power-On Sequence
The device should be powered-on in the following order:
1. Logic supplies:
(a) CVDD core logic supply
(b) Other static logic supplies (RVDD, PLL0_VDDA).
Groups 1a) and 1b) may be powered up together; or 1a) first, followed by 1b).
2. All digital IO supplies (DVDD).
There is no specific required voltage ramp rate for any of the supplies.
Note: Future devices may support higher performance at a higher core logic voltage (CVDD). If future
migration is desired, the current design should provide separate supplies for 1a) and 1b). If not, then 1a)
and 1b) may be provided by a single supply.
RESET must be maintained active until all power supplies have reached their nominal values.
5.3.2 Power-Off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
45
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.4 Reset
www.ti.com
5.4.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of GP7[14]. During reset, GP7[14] is
configured as a reserved function, and its behavior is not guaranteed; the user should be aware that this
pin will drive a level, and in fact may toggle, during reset.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
A summary of the effects of Power-On Reset is given below:
•
•
•
All internal logic (including emulation logic and the PLL logic) is reset to its default state
Internal memory is not maintained through a POR
All device pins go to a high-impedance state
CAUTION
A watchdog reset triggers a POR.
5.4.2 Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of GP7[14]. During
reset, GP7[14] is configured as a reserved function, and its behavior is not deterministic; the user should
be aware that this pin will drive a level, and in fact may toggle, during reset.
During emulation, the emulator will maintain TRST high so only warm reset (not POR) is available during
emulation debug and development.
A summary of the effects of Warm Reset is given below:
•
•
•
All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
Internal memory is maintained through a warm reset
All device pins go to a high-impedance state
46
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.4.3 Reset Electrical Data Timings
Table 5-1 assumes testing over the recommended operating conditions.
Table 5-1. Reset Timing Requirements ((1)
)
NO.
MIN
100
20
MAX
UNIT
ns
1
2
3
tw(RSTL)
Pulse width, RESET/TRST low
tsu(BPV-RSTH)
th(RSTH-BPV)
Setup time, boot pins valid before RESET/TRST high
Hold time, boot pins valid after RESET/TRST high
ns
20
ns
(1) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
Power
Supplies
Ramping
Power Supplies Stable
Clock Source Stable
OSCIN
1
RESET
TRST
3
2
Boot Pins
Config
Figure 5-4. Power-On Reset (RESET and TRST active) Timing
Power Supplies Stable
OSCIN
TRST
1
RESET
3
2
Config
Boot Pins
Driven or Hi-Z
Figure 5-5. Warm Reset (RESET active, TRST high) Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
47
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.5 Crystal Oscillator or External Clock Input
The device includes two choices to provide an external clock input, which is fed to the on-chip PLL to
generate high-frequency system clocks. These options are illustrated in Figure 5-6 and Figure 5-7. For
input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is recommended. For
input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is recommended.
Typical load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1
and C2.
The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1,
the internal oscillator is disabled.
•
•
Figure 5-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
Figure 5-7 illustrates the option that uses an external 1.2V clock input.
C2
OSCIN
Clock Input
to PLL
X1
OSCOUT
C1
OSCVSS
Figure 5-6. On-Chip 1.2V Oscillator
Table 5-2. Oscillator Timing Requirements
NO
fosc
PARAMETER
MIN
MAX
UNIT
Oscillator frequency range (OSCIN/OSCOUT)
12
30
MHz
Clock
Input
to PLL
OSCIN
OSCOUT
NC
OSCVSS
Figure 5-7. External 1.2V Clock Source
48
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-3. OSCIN Timing Requirements for Externally Driven Clock
NO
MIN
12
MAX
UNIT
MHz
ns
fOSCIN
OSCIN frequency range (OSCIN)
Cycle time, external clock driven on OSCIN
Pulse width high, external clock on OSCIN
Pulse width low, external clock on OSCIN
Transition time, OSCIN
50
tc(OSCIN)
tw(OSCINH)
tw(OSCINL)
tt(OSCIN)
tj(OSCIN)
20
0.4 tc(OSCIN)
0.4 tc(OSCIN)
ns
ns
0.25P or 10(1)
0.02P
ns
Period jitter, OSCIN
ns
(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
5.6 Clock PLLs
The device has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
•
•
•
•
Glitch-Free Transitions (on changing clock settings)
Domain Clocks Alignment
Clock Gating
PLL power down
The various clock outputs given by the controller are as follows:
•
•
Domain Clocks: SYSCLK [1:n]
Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
•
•
Post-PLL Divider: POSTDIV
SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
•
•
PLL Multiplier Control: PLLM
Software programmable PLL Bypass: PLLEN
5.6.1 PLL Device-Specific Information
The device DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in Figure 5-
8.
1.14V - 1.32V
50R
PLL0_VDDA
0.1
µF
0.01
µF
VSS
50R
PLL0_VSSA
Ferrite Bead: Murata BLM31PG500SN1L or Equivalent
Figure 5-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator or from an external clock on the OSCIN pin. The
PLL outputs seven clocks that have programmable divider options. Figure 5-9 illustrates the PLL
Topology.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
49
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 5-4 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
CLKMODE
PLLEN
Square
1
Wave
PLLDIV1 (/1)
PLLDIV2 (/2)
OSCIN
Pre-Div
PLL
Post-Div
1
0
SYSCLK1
SYSCLK2
Crystal
0
PLLM
PLLDIV3 (/3)
PLLDIV4 (/4)
SYSCLK3
SYSCLK4
PLLDIV5 (/3)
PLLDIV7 (/6)
SYSCLK5
SYSCLK7
AUXCLK
EMIFA
0
1
Internal
Clock
Source
DIV4.5
CFGCHIP3[EMA_CLKSRC]
EMIFB
DIV4.5
1
0
Internal
Clock
Source
CFGCHIP3[EMB_CLKSRC]
Figure 5-9. PLL Topology
50
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-4. Allowed PLL Operating Conditions
Default
Value
NO
PARAMETER
MIN
MAX
N/A
UNIT
1
PLLRST: Assertion time during initialization
N/A
N/A
/1
1000
ns
2000 N
m
Max PLL Lock Time =
Lock time: The time that the application has to wait for
the PLL to acquire locks before setting PLLEN, after
changing PREDIV, PLLM, or OSCIN
OSCIN
cycles
2
N/A
where N = Pre-Divider Ratio
M = PLL Multiplier
3
4
PREDIV
/1
/32
PLL input frequency
( PLLREF)
30 (if internal oscillator is used)
50 (if external clock source is used)
12
MHz
MHz
(1)
5
6
7
PLL multiplier values (PLLM)
x20
N/A
/1
x4
300
/1
x32
600
/32
PLL output frequency. ( PLLOUT )
POSTDIV
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
5.6.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
PLLC0 generates several clocks from the PLL0 output clock for use by the various modules. These are
summarized in Table 5-5. The clock ratios between SYSCLK1, SYSCLK2, SYSCLK4 and SYSCLK6 must
always be maintained as shown in the table.
Table 5-5. System PLLC0 Output Clocks
OUTPUT
CLOCK
USED BY
DEFAULT RATIO
(RELATIVE TO
SYSCLK1)
NOTES
SYSCLK1
SYSCLK2
DSP
/1
/2
No Required Ratio
SYSCLK1 / 2
EDMA, DSP ports, EMIFB (ports to switch fabric), ECAP 0/1/2,
EPWM 0/1/2, EQEP 0/1, McASP/FIFO 0/1, UART 2, HRPWM
0/1/2, SPI0
SYSCLK3
EMIFA
/3
/4
No Required Ratio
SYSCLK1 / 4
SYSCLK4 SYSCFG, Interrupt Controller, PLLC0, PSC 0, EMAC/MDIO, GPIO,
I2C 1, PSC 1
SYSCLK5
SYSCLK7
EMIFB
/3
/6
No Required Ratio
RMII clock to EMAC
No Required Ratio ;
Should be set to 50 MHz
AUXCLK
DIV4p5
McASP AuxClk, Timer64P0,Timer64P1, I2C0,
133MHz clock source for EMIFB
N/A
No Required Ratio
No Required Ratio
PLL output/4.5
•
•
•
The divide values in the PLL Controller 0 for SYSCLK1/SYSCLK6, SYSCLK2 and SYSCLK4 are not
fixed so that user can change the divide values for power saving reasons. But users are responsible to
guarantee that the divide ratios between these clock domains must be fixed to 1:2:4.
Although the PLL is capable of running at 600 MHz, the SYSCLK dividers in the PLLC0 are not
(maximum 400 MHz). For this reason, the post-divider in the PLLC0 should be configured for /2 to
provide 300 MHz to each of the SYSCLK dividers.
The DIV4p5 (/4.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL
clock for use as clocks to the EMIFs.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
51
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.6.3 PLL Controller 0 Registers
Table 5-6. PLL Controller 0 Registers
ADDRESS
0x01C1 1000
0x01C1 10E4
0x01C1 1100
0x01C1 1104
0x01C1 1110
0x01C1 1114
0x01C1 1118
0x01C1 111C
0x01C1 1120
0x01C1 1124
0x01C1 1128
0x01C1 1138
0x01C1 113C
0x01C1 1140
0x01C1 1144
0x01C1 1148
0x01C1 114C
0x01C1 1150
0x01C1 1160
0x01C1 1164
0x01C1 1168
0x01C1 116C
REGISTER NAME
REVID
REGISTER DESCRIPTION
Revision Identification Register
Reset Type Status Register
PLL Control Register
RSTYPE
PLLCTL
-
Reserved
PLLM
PLL Multiplier Control Register
PLL Pre-Divider Control Register
PLL Controller Divider 1 Register
PLL Controller Divider 2 Register
PLL Controller Divider 3 Register
Reserved
PREDIV
PLLDIV1
PLLDIV2
PLLDIV3
-
POSTDIV
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
PLL Post-Divider Control Register
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Clock Enable Control Register
Clock Status Register
CKSTAT
SYSTAT
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
SYSCLK Status Register
PLL Controller Divider 4 Register
PLL Controller Divider 5 Register
PLL Controller Divider 6 Register
PLL Controller Divider 7 Register
52
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.7 DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 5-7. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 5-8
summarizes the C674x interrupt controller registers and memory locations.
Table 5-7. C6743 DSP Interrupts
EVT#
0
INTERRUPT NAME
EVT0
SOURCE
C674x Int Ctl 0
1
EVT1
C674x Int Ctl 1
2
EVT2
C674x Int Ctl 2
3
EVT3
C674x Int Ctl 3
4
T64P0_TINT12
SYSCFG_CHIPINT2
PRU_EVTOUT0
EHRPWM0
Timer64P0 - TINT12
SYSCFG_CHIPSIG Register
PRU Interrupt
5
6
7
HiResTimer/PWM0 Interrupt
EDMA3 CC0 Region 1 interrupt
C674x-ECM
8
EDMA3_CC0_INT1
EMU-DTDMA
EHRPWM0TZ
EMU-RTDXRX
EMU-RTDXTX
IDMAINT0
9
10
11
12
13
14
15
16
17
18
19-21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
HiResTimer/PWM0 Trip Zone Interrupt
C674x-RTDX
C674x-RTDX
C674x-EMC
IDMAINT1
C674x-EMC
MMCSD_INT0
MMCSD_INT1
PRU_EVTOUT1
EHRPWM1
MMCSD MMC/SD Interrupt
MMCSD SDIO Interrupt
PRU Interrupt
HiResTimer/PWM1 Interrupt
Reserved
-
PRU_EVTOUT2
EHRPWM1TZ
EHRPWM2
PRU Interrupt
HiResTimer/PWM1 Trip Zone Interrupt
HiResTimer/PWM2 Interrupt
HiResTimer/PWM2 Trip Zone Interrupt
EMAC - Core 0 Receive Threshold Interrupt
EMAC - Core 0 Receive Interrupt
EMAC - Core 0 Transmit Interrupt
EMAC - Core 0 Miscellaneous Interrupt
EMAC - Core 1 Receive Threshold Interrupt
EMAC - Core 1 Receive Interrupt
EMAC - Core 1 Transmit Interrupt
EMAC - Core 1 Miscellaneous Interrupt
Reserved
EHRPWM2TZ
EMAC_C0RXTHRESH
EMAC_C0RX
EMAC_C0TX
EMAC_C0MISC
EMAC_C1RXTHRESH
EMAC_C1RX
EMAC_C1TX
EMAC_C1MISC
-
PRU_EVTOUT3
IIC0_INT
PRU Interrupt
I2C0
SP0_INT
SPI0
UART0_INT
PRU_EVTOUT5
T64P1_TINT12
GPIO_B1INT
IIC1_INT
UART0
PRU Interrupt
Timer64P1 Interrupt 12
GPIO Bank 1 Interrupt
I2C1
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
53
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-7. C6743 DSP Interrupts (continued)
EVT#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75-77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
INTERRUPT NAME
-
SOURCE
Reserved
PRU_EVTOUT6
ECAP0
PRU Interrupt
ECAP0
-
Reserved
ECAP1
ECAP1
T64P1_TINT34
GPIO_B2INT
PRU_EVTOUT7
ECAP2
Timer64P1 Interrupt 34
GPIO Bank 2 Interrupt
PRU Interrupt
ECAP2
GPIO_B3INT
EQEP1
GPIO Bank 3 Interrupt
EQEP1
GPIO_B4INT
EMIFA_INT
GPIO Bank 4 Interrupt
EMIFA
EDMA3_CC0_ERRINT
EDMA3_TC0_ERRINT
EDMA3_TC1_ERRINT
GPIO_B5INT
EMIFB_INT
EDMA3 Channel Controller 0
EDMA3 Transfer Controller 0
EDMA3 Transfer Controller 1
GPIO Bank 5 Interrupt
EMIFB Memory Error Interrupt
McASP0,1 Combined RX/TX Interrupts
GPIO Bank 6 Interrupt
Reserved
MCASP_INT
GPIO_B6INT
-
T64P0_TINT34
GPIO_B0INT
PRU_EVTOUT4
SYSCFG_CHIPINT3
EQEP0
Timer64P0 Interrupt 34
GPIO Bank 0 Interrupt
PRU Interrupt
SYSCFG_CHIPSIG Register
EQEP0
UART2_INT
UART2
PSC0_ALLINT
PSC1_ALLINT
GPIO_B7INT
-
PSC0
PSC1
GPIO Bank 7 Interrupt
Reserved
MPU_BOOTCFG_ERR
-
Shared MPU and SYSCFG Address/Protection Error Interrupt
Reserved
T64P0_CMPINT0
T64P0_CMPINT1
T64P0_CMPINT2
T64P0_CMPINT3
T64P0_CMPINT4
T64P0_CMPINT5
T64P0_CMPINT6
T64P0_CMPINT7
T64P1_CMPINT0
T64P1_CMPINT1
T64P1_CMPINT2
T64P1_CMPINT3
T64P1_CMPINT4
T64P1_CMPINT5
Timer64P0 - Compare 0
Timer64P0 - Compare 1
Timer64P0 - Compare 2
Timer64P0 - Compare 3
Timer64P0 - Compare 4
Timer64P0 - Compare 5
Timer64P0 - Compare 6
Timer64P0 - Compare 7
Timer64P1 - Compare 0
Timer64P1 - Compare 1
Timer64P1 - Compare 2
Timer64P1 - Compare 3
Timer64P1 - Compare 4
Timer64P1 - Compare 5
54
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-7. C6743 DSP Interrupts (continued)
EVT#
92
INTERRUPT NAME
T64P1_CMPINT6
T64P1_CMPINT7
-
SOURCE
Timer64P1 - Compare 6
Timer64P1 - Compare 7
Reserved
93
94-95
96
INTERR
C674x-Int Ctl
C674x-EMC
Reserved
97
EMC_IDMAERR
-
98-112
113
PMC_ED
C674x-PMC
Reserved
114-115
116
-
UMC_ED1
UMC_ED2
PDC_INT
C674x-UMC
C674x-UMC
C674x-PDC
C674x-SYS
117
118
119
SYS_CMPA
PMC_CMPA
PMC_CMPA
DMC_CMPA
DMC_CMPA
UMC_CMPA
UMC_CMPA
EMC_CMPA
EMC_BUSERR
120
C674x-PMC
C674x-PMC
C674x-DMC
C674x-DMC
C674x-UMC
C674x-UMC
C674x-EMC
C674x-EMC
121
122
123
124
125
126
127
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
55
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-8. C674x DSP Interrupt Controller Registers
BYTE ADDRESS
0x0180 0000
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
REGISTER NAME
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
EVTSET0
REGISTER DESCRIPTION
Event flag register 0
Event flag register 1
Event flag register 2
Event flag register 3
Event set register 0
EVTSET1
Event set register 1
EVTSET2
Event set register 2
EVTSET3
Event set register 3
EVTCLR0
Event clear register 0
EVTCLR1
Event clear register 1
EVTCLR2
Event clear register 2
EVTCLR3
Event clear register 3
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
Event mask register 0
Event mask register 1
Event mask register 2
Event mask register 3
Masked event flag register 0
Masked event flag register 1
Masked event flag register 2
Masked event flag register 3
Exception mask register 0
Exception mask register 1
Exception mask register 2
Exception mask register 3
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
56
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.8 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
The GPIO peripheral supports the following:
•
•
Up to 128 Pins on ZKB and up to 109 Pins on PTP package configurable as GPIO
External Interrupt and DMA request Capability
–
–
–
–
–
Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62
and 72 respectively
Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
•
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 5-9.
5.8.1 GPIO Register Description(s)
Table 5-9. GPIO Registers
GPIO
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
0x01E2 6000
0x01E2 6004
0x01E2 6008
REV
Peripheral Revision Register
-
Reserved
BINTEN
GPIO Interrupt Per-Bank Enable Register
GPIO Banks 0 and 1
0x01E2 6010
0x01E2 6014
0x01E2 6018
0x01E2 601C
0x01E2 6020
0x01E2 6024
0x01E2 6028
0x01E2 602C
DIR01
GPIO Banks 0 and 1 Direction Register
GPIO Banks 0 and 1 Output Data Register
GPIO Banks 0 and 1 Set Data Register
GPIO Banks 0 and 1 Clear Data Register
GPIO Banks 0 and 1 Input Data Register
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
OUT_DATA01
SET_DATA01
CLR_DATA01
IN_DATA01
SET_RIS_TRIG01
CLR_RIS_TRIG01
SET_FAL_TRIG01
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
57
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-9. GPIO Registers (continued)
GPIO
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
0x01E2 6030
0x01E2 6034
CLR_FAL_TRIG01
INTSTAT01
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
GPIO Banks 0 and 1 Interrupt Status Register
GPIO Banks 2 and 3
0x01E2 6038
0x01E2 603C
0x01E2 6040
0x01E2 6044
0x01E2 6048
0x01E2 604C
0x01E2 6050
0x01E2 6054
0x01E2 6058
0x01E2 605C
DIR23
GPIO Banks 2 and 3 Direction Register
OUT_DATA23
SET_DATA23
CLR_DATA23
IN_DATA23
GPIO Banks 2 and 3 Output Data Register
GPIO Banks 2 and 3 Set Data Register
GPIO Banks 2 and 3 Clear Data Register
GPIO Banks 2 and 3 Input Data Register
SET_RIS_TRIG23
CLR_RIS_TRIG23
SET_FAL_TRIG23
CLR_FAL_TRIG23
INTSTAT23
GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
GPIO Banks 2 and 3 Interrupt Status Register
GPIO Banks 4 and 5
0x01E2 6060
0x01E2 6064
0x01E2 6068
0x01E2 606C
0x01E2 6070
0x01E2 6074
0x01E2 6078
0x01E2 607C
0x01E2 6080
0x01E2 6084
DIR45
GPIO Banks 4 and 5 Direction Register
OUT_DATA45
SET_DATA45
CLR_DATA45
IN_DATA45
GPIO Banks 4 and 5 Output Data Register
GPIO Banks 4 and 5 Set Data Register
GPIO Banks 4 and 5 Clear Data Register
GPIO Banks 4 and 5 Input Data Register
SET_RIS_TRIG45
CLR_RIS_TRIG45
SET_FAL_TRIG45
CLR_FAL_TRIG45
INTSTAT45
GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
GPIO Banks 4 and 5 Interrupt Status Register
GPIO Banks 6 and 7
0x01E2 6088
0x01E2 608C
0x01E2 6090
0x01E2 6094
0x01E2 6098
0x01E2 609C
0x01E2 60A0
0x01E2 60A4
0x01E2 60A8
0x01E2 60AC
DIR67
GPIO Banks 6 and 7 Direction Register
OUT_DATA67
SET_DATA67
CLR_DATA67
IN_DATA67
GPIO Banks 6 and 7 Output Data Register
GPIO Banks 6 and 7 Set Data Register
GPIO Banks 6 and 7 Clear Data Register
GPIO Banks 6 and 7 Input Data Register
SET_RIS_TRIG67
CLR_RIS_TRIG67
SET_FAL_TRIG67
CLR_FAL_TRIG67
INTSTAT67
GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
58
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 5-10. Timing Requirements for GPIO Inputs(1) (see Figure 5-10)
NO.
MIN MAX UNIT
2C(1) (2)
ns
2C(1) (2)
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 5-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-10)
NO.
3
PARAMETER
MIN MAX UNIT
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
2C(1) (2)
2C(1) (2)
ns
ns
4
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m] as input
4
3
GPn[m] as output
Figure 5-10. GPIO Port Timing
5.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 5-12. Timing Requirements for External Interrupts(1) (see Figure 5-11)
NO.
1
MIN MAX UNIT
2C(1) (2)
ns
2C(1) (2)
tw(ILOW)
tw(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
2
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have the device recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to
access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
2
1
GPn[m] as input
Figure 5-11. GPIO External Interrupt Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
59
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.9 EDMA
Table 5-13 is the list of EDMA3 Channel Contoller Registers and Table 5-14 is the list of EDMA3 Transfer
Controller registers. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide
(SPRUFK9) for more details.
Table 5-13. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS
0x01C0 0000
REGISTER NAME
PID
REGISTER DESCRIPTION
Peripheral Identification Register
EDMA3CC Configuration Register
0x01C0 0004
CCCFG
Global Registers
0x01C0 0200
0x01C0 0204
0x01C0 0208
0x01C0 020C
0x01C0 0210
0x01C0 0214
0x01C0 0218
0x01C0 021C
0x01C0 0240
0x01C0 0244
0x01C0 0248
0x01C0 024C
0x01C0 0260
0x01C0 0284
0x01C0 0300
0x01C0 0308
0x01C0 0310
0x01C0 0314
0x01C0 0318
0x01C0 031C
0x01C0 0320
0x01C0 0340
0x01C0 0348
0x01C0 0350
0x01C0 0358
0x01C0 0380
0x01C0 0384
0x01C0 0388
0x01C0 038C
0x01C0 0400 - 0x01C0 043C
0x01C0 0440 - 0x01C0 047C
0x01C0 0600
0x01C0 0604
0x01C0 0620
0x01C0 0640
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
QDMAQNUM
QUEPRI
QDMA Channel 0 Mapping Register
QDMA Channel 1 Mapping Register
QDMA Channel 2 Mapping Register
QDMA Channel 3 Mapping Register
QDMA Channel 4 Mapping Register
QDMA Channel 5 Mapping Register
QDMA Channel 6 Mapping Register
QDMA Channel 7 Mapping Register
DMA Channel Queue Number Register 0
DMA Channel Queue Number Register 1
DMA Channel Queue Number Register 2
DMA Channel Queue Number Register 3
QDMA Channel Queue Number Register
Queue Priority Register(1)
EMR
Event Missed Register
EMCR
Event Missed Clear Register
QEMR
QDMA Event Missed Register
QEMCR
QDMA Event Missed Clear Register
EDMA3CC Error Register
CCERR
CCERRCLR
EEVAL
EDMA3CC Error Clear Register
Error Evaluate Register
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
QDMA Region Access Enable Register for Region 3
Event Queue Entry Registers Q0E0-Q0E15
Event Queue Entry Registers Q1E0-Q1E15
Queue 0 Status Register
DRAE1
DRAE2
DRAE3
QRAE0
QRAE1
QRAE2
QRAE3
Q0E0-Q0E15
Q1E0-Q1E15
QSTAT0
QSTAT1
Queue 1 Status Register
QWMTHRA
CCSTAT
Queue Watermark Threshold A Register
EDMA3CC Status Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
60
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
Global Channel Registers
0x01C0 1000
0x01C0 1008
0x01C0 1010
0x01C0 1018
0x01C0 1020
0x01C0 1028
0x01C0 1030
0x01C0 1038
0x01C0 1040
0x01C0 1050
0x01C0 1058
0x01C0 1060
0x01C0 1068
0x01C0 1070
0x01C0 1078
0x01C0 1080
0x01C0 1084
0x01C0 1088
0x01C0 108C
0x01C0 1090
0x01C0 1094
ER
Event Register
ECR
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
SECR
IER
IECR
IESR
IPR
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2000
0x01C0 2008
0x01C0 2010
0x01C0 2018
0x01C0 2020
0x01C0 2028
0x01C0 2030
0x01C0 2038
0x01C0 2040
0x01C0 2050
0x01C0 2058
0x01C0 2060
0x01C0 2068
0x01C0 2070
0x01C0 2078
0x01C0 2080
0x01C0 2084
0x01C0 2088
0x01C0 208C
0x01C0 2090
0x01C0 2094
ER
Event Register
ECR
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
SECR
IER
IECR
IESR
IPR
ICR
IEVAL
QER
Interrupt Evaluate Register
QDMA Event Register
QEER
QEECR
QEESR
QSER
QSECR
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
61
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-13. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
Shadow Region 1 Channel Registers
0x01C0 2200
0x01C0 2208
0x01C0 2210
0x01C0 2218
0x01C0 2220
0x01C0 2228
0x01C0 2230
0x01C0 2238
0x01C0 2240
0x01C0 2250
0x01C0 2258
0x01C0 2260
0x01C0 2268
0x01C0 2270
0x01C0 2278
0x01C0 2280
0x01C0 2284
0x01C0 2288
0x01C0 228C
0x01C0 2290
0x01C0 2294
0x01C0 4000 - 0x01C0 4FFF
ER
Event Register
ECR
Event Clear Register
ESR
Event Set Register
CER
Chained Event Register
EER
Event Enable Register
EECR
EESR
SER
Event Enable Clear Register
Event Enable Set Register
Secondary Event Register
Secondary Event Clear Register
Interrupt Enable Register
Interrupt Enable Clear Register
Interrupt Enable Set Register
Interrupt Pending Register
Interrupt Clear Register
SECR
IER
IECR
IESR
IPR
ICR
IEVAL
QER
QEER
QEECR
QEESR
QSER
QSECR
—
Interrupt Evaluate Register
QDMA Event Register
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Parameter RAM (PaRAM)
Table 5-14. EDMA3 Transfer Controller (EDMA3TC) Registers
TRANSFER
TRANSFER
REGISTER NAME REGISTER DESCRIPTION
CONTROLLER 0
BYTE ADDRESS
CONTROLLER 1
BYTE ADDRESS
0x01C0 8000
0x01C0 8004
0x01C0 8100
0x01C0 8120
0x01C0 8124
0x01C0 8128
0x01C0 812C
0x01C0 8130
0x01C0 8140
0x01C0 8240
0x01C0 8244
0x01C0 8248
0x01C0 824C
0x01C0 8250
0x01C0 8254
0x01C0 8258
0x01C0 825C
0x01C0 8260
0x01C0 8280
0x01C0 8284
0x01C0 8400
0x01C0 8404
0x01C0 8500
0x01C0 8520
0x01C0 8524
0x01C0 8528
0x01C0 852C
0x01C0 8530
0x01C0 8540
0x01C0 8640
0x01C0 8644
0x01C0 8648
0x01C0 864C
0x01C0 8650
0x01C0 8654
0x01C0 8658
0x01C0 865C
0x01C0 8660
0x01C0 8680
0x01C0 8684
PID
Peripheral Identification Register
EDMA3TC Configuration Register
EDMA3TC Channel Status Register
Error Status Register
TCCFG
TCSTAT
ERRSTAT
ERREN
Error Enable Register
ERRCLR
ERRDET
ERRCMD
RDRATE
SAOPT
Error Clear Register
Error Details Register
Error Interrupt Command Register
Read Command Rate Register
Source Active Options Register
SASRC
Source Active Source Address Register
Source Active Count Register
SACNT
SADST
Source Active Destination Address Register
Source Active B-Index Register
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
DFCNTRLD
DFSRCBREF
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Destination FIFO Set Count Reload Register
Destination FIFO Set Source Address B-Reference Register
62
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-14. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
TRANSFER
TRANSFER
REGISTER NAME REGISTER DESCRIPTION
CONTROLLER 0
BYTE ADDRESS
CONTROLLER 1
BYTE ADDRESS
0x01C0 8288
0x01C0 8300
0x01C0 8304
0x01C0 8308
0x01C0 830C
0x01C0 8310
0x01C0 8314
0x01C0 8340
0x01C0 8344
0x01C0 8348
0x01C0 834C
0x01C0 8350
0x01C0 8354
0x01C0 8380
0x01C0 8384
0x01C0 8388
0x01C0 838C
0x01C0 8390
0x01C0 8394
0x01C0 83C0
0x01C0 83C4
0x01C0 83C8
0x01C0 83CC
0x01C0 83D0
0x01C0 83D4
0x01C0 8688
0x01C0 8700
0x01C0 8704
0x01C0 8708
0x01C0 870C
0x01C0 8710
0x01C0 8714
0x01C0 8740
0x01C0 8744
0x01C0 8748
0x01C0 874C
0x01C0 8750
0x01C0 8754
0x01C0 8780
0x01C0 8784
0x01C0 8788
0x01C0 878C
0x01C0 8790
0x01C0 8794
0x01C0 87C0
0x01C0 87C4
0x01C0 87C8
0x01C0 87CC
0x01C0 87D0
0x01C0 87D4
DFDSTBREF
DFOPT0
Destination FIFO Set Destination Address B-Reference Register
Destination FIFO Options Register 0
DFSRC0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
DFCNT0
DFDST0
Destination FIFO Destination Address Register 0
Destination FIFO B-Index Register 0
DFBIDX0
DFMPPRXY0
DFOPT1
Destination FIFO Memory Protection Proxy Register 0
Destination FIFO Options Register 1
DFSRC1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
DFCNT1
DFDST1
Destination FIFO Destination Address Register 1
Destination FIFO B-Index Register 1
DFBIDX1
DFMPPRXY1
DFOPT2
Destination FIFO Memory Protection Proxy Register 1
Destination FIFO Options Register 2
DFSRC2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
DFCNT2
DFDST2
Destination FIFO Destination Address Register 2
Destination FIFO B-Index Register 2
DFBIDX2
DFMPPRXY2
DFOPT3
Destination FIFO Memory Protection Proxy Register 2
Destination FIFO Options Register 3
DFSRC3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
DFCNT3
DFDST3
Destination FIFO Destination Address Register 3
Destination FIFO B-Index Register 3
DFBIDX3
DFMPPRXY3
Destination FIFO Memory Protection Proxy Register 3
Table 5-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 5-16 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 5-15. EDMA Parameter Set RAM
HEX ADDRESS RANGE
0x01C0 4000 - 0x01C0 401F
0x01C0 4020 - 0x01C0 403F
0x01C0 4040 - 0x01cC0 405F
0x01C0 4060 - 0x01C0 407F
0x01C0 4080 - 0x01C0 409F
0x01C0 40A0 - 0x01C0 40BF
...
DESCRIPTION
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x01C0 4FC0 - 0x01C0 4FDF
0x01C0 4FE0 - 0x01C0 4FFF
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
63
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-16. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
SRC_DST_CIDX
CCNT
Source B Index, Destination B Index
Link Address, B Count Reload
Source C Index, Destination C Index
C Count
Table 5-17. EDMA Events
EVENT
EVENT NAME / SOURCE
McASP0 Receive
EVENT
EVENT NAME / SOURCE
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MMCSD Receive
MMCSD Transmit
-
McASP0 Transmit
McASP1 Receive
McASP1 Transmit
-
2
3
-
4
PRU_EVTOUT6
PRU_EVTOUT7
GPIO Bank 2 Interrupt
GPIO Bank 3 Interrupt
I2C0 Receive
5
-
6
GPIO Bank 0 Interrupt
GPIO Bank 1 Interrupt
UART0 Receive
UART0 Transmit
Timer64P0 Event Out 12
Timer64P0 Event Out 34
-
7
8
9
I2C0 Transmit
10
11
12
13
14
15
I2C1 Receive
I2C1 Transmit
GPIO Bank 4 Interrupt
GPIO Bank 5 Interrupt
UART2 Receive
UART2 Transmit
-
SPI0 Receive
SPI0 Transmit
64
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the device. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
5.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
•
•
•
SRAM memories
NAND Flash memories
NOR Flash memories
The EMIFA data bus width is up to 16-bits on the ZKB package and 8 bits on the PTP package. Both
devices support up to fifteen address lines and an external wait/interrupt input. Up to four asynchronous
chip selects are supported by EMIFA (EMA_CS[5:2]) . All four chip selects are available on the ZKB
package. Two of the four are available on the PTP package (EMA_CS[3:2]).
Each chip select has the following individually programmable attributes:
•
•
•
•
•
•
•
Data Bus Width
Read cycle timings: setup, hold, strobe
Write cycle timings: setup, hold, strobe
Bus turn around time
Extended Wait Option With Programmable Timeout
Select Strobe Option
NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
5.10.2 EMIFA Connection Examples
A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 5-12.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
65
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
EMA_A[1]
EMA_A[2]
ALE
CLE
DQ[7:0]
CE1
CE2
WE
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
NAND
FLASH
x8,
MultiPlane
EMA_OE
RE
EMIFA
R/B1
R/B2
EMA_WAIT
DVDD
ALE
CLE
DQ[7:0]
CE1
CE2
WE
NAND
FLASH
x8,
EMA_CS[4]
EMA_CS[5]
MultiPlane
RE
R/B1
R/B2
Figure 5-12. C6743 EMIFA Connection Diagram: Multiple NAND Flash Planes
5.10.3 External Memory Interface (EMIF) Registers
Table 5-18 is a list of the EMIF registers.
Table 5-18. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
0x6800 0000
0x6800 0004
0x6800 0008
0x6800 000C
0x6800 0010
0x6800 0014
0x6800 0018
0x6800 001C
0x6800 0020
0x6800 003C
0x6800 0040
0x6800 0044
0x6800 0048
0x6800 004C
0x6800 0060
0x6800 0064
0x6800 0070
0x6800 0074
0x6800 0078
0x6800 007C
0x6800 00BC
0x6800 00C0
0x6800 00C4
0x6800 00C8
REGISTER NAME
MIDR
REGISTER DESCRIPTION
Module ID Register
AWCC
Asynchronous Wait Cycle Configuration Register
SDRAM Configuration Register (Not supported)
SDRAM Refresh Control Register (Not supported)
Asynchronous 1 Configuration Register
Asynchronous 2 Configuration Register
Asynchronous 3 Configuration Register
Asynchronous 4 Configuration Register
SDRAM Timing Register (Not supported)
SDRAM Self Refresh Exit Timing Register (Not supported)
EMIFA Interrupt Raw Register
SDCR
SDRCR
CE2CFG
CE3CFG
CE4CFG
CE5CFG
SDTIMR
SDSRETR
INTRAW
INTMSK
EMIFA Interrupt Mask Register
INTMSKSET
INTMSKCLR
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
NAND4BITECC3
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
NAND Flash 4-Bit ECC Register 3
66
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-18. External Memory Interface (EMIFA) Registers (continued)
BYTE ADDRESS
REGISTER NAME
NAND4BITECC4
NANDERRADD1
NANDERRADD2
NANDERRVAL1
NANDERRVAL2
REGISTER DESCRIPTION
0x6800 00CC
0x6800 00D0
0x6800 00D4
0x6800 00D8
0x6800 00DC
NAND Flash 4-Bit ECC Register 4
NAND Flash 4-Bit ECC Error Address Register 1
NAND Flash 4-Bit ECC Error Address Register 2
NAND Flash 4-Bit ECC Error Value Register 1
NAND Flash 4-Bit ECC Error Value Register 2
5.10.4 EMIFA Electrical Data/Timing
Table 5-19 and Table 5-20 assume testing over recommended operating conditions.
Table 5-19. EMIFA Asynchronous Memory Timing Requirements(1)
NO.
MIN
NOM
MAX
UNIT
READS and WRITES
Cycle time, EMIFA module clock
E
2
tc(CLK)
10
2E
ns
ns
tw(EM_WAIT)
Pulse duration, EM_WAIT assertion and deassertion
READS
12 tsu(EMDV-EMOEH)
13 th(EMOEH-EMDIV)
14 tsu (EMOEL-EMWAIT)
Setup time, EMA_D[15:0] valid before EM_OE high
Hold time, EMA_D[15:0] valid after EM_OE high
Setup time, EM_WAIT asserted before end of Strobe Phase(2)
WRITES
3
0
ns
ns
ns
4E+3
28 tsu (EMWEL-EMWAIT) Setup time, EM_WAIT asserted before end of Strobe Phase(2)
4E+3
ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 5-15 and Figure 5-16 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-20. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3)
NO.
PARAMETER
MIN
NOM
MAX UNIT
READS and WRITES
(TA)*E-3
1
td(TURNAROUND)
Turn around time
(TA)*E
(TA)*E+3
ns
READS
(RS+RST+RH)*E-3
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E
(RS+RST+RH)*E+3
ns
ns
3
4
tc(EMRCYCLE)
(RS+RST+RH+(EWC*16))*E-3 (RS+RST+RH+(EWC*16))*E
(RS+RST+RH+(EWC*16))*E+3
Output setup time,
EMA_CE[5:2] low to EMA_OE low (SS = 0)
(RS)*E-3
-3
(RS)*E
0
(RS)*E+3
+3
ns
ns
ns
ns
ns
ns
ns
tsu(EMCEL-EMOEL)
Output setup time,
EMA_CE[5:2] low to EMA_OE low (SS = 1)
Output hold time,
EMA_OE high to EMA_CE[5:2] high (SS = 0)
(RH)*E-3
-3
(RH)*E
0
(RH)*E+3
+3
5
th(EMOEH-EMCEH)
Output hold time,
EMA_OE high to EMA_CE[5:2] high (SS = 1)
Output setup time,
EMA_BA[1:0] valid to EMA_OE low
6
7
8
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
(RS)*E-3
(RH)*E-3
(RS)*E-3
(RS)*E
(RH)*E
(RS)*E
(RS)*E+3
(RH)*E+3
(RS)*E+3
Output hold time,
EMA_OE high to EMA_BA[1:0] invalid
Output setup time,
EMA_A[13:0] valid to EMA_OE low
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
67
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
MAX UNIT
Table 5-20. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3) (continued)
NO.
PARAMETER
MIN
NOM
Output hold time,
9
th(EMOEH-EMAIV)
(RH)*E-3
(RH)*E
(RH)*E+3
ns
EMA_OE high to EMA_A[13:0] invalid
EMA_OE active low width (EW = 0)
EMA_OE active low width (EW = 1)
(RST)*E-3
(RST)*E
(RST)*E+3
ns
ns
10 tw(EMOEL)
(RST+(EWC*16))*E-3
(RST+(EWC*16))*E
(RST+(EWC*16))*E+3
Delay time from EMA_WAIT deasserted to
EMA_OE high
11 td(EMWAITH-EMOEH)
3E-3
4E
4E+3
ns
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E-3
(WS+WST+WH)*E
(WS+WST+WH)*E+3
ns
ns
15 tc(EMWCYCLE)
(WS+WST+WH+(EWC*16))*E-3 (WS+WST+WH+(EWC*16))*E (WS+WST+WH+(EWC*16))*E+3
Output setup time,
EMA_CE[5:2] low to EMA_WE low (SS = 0)
(WS)*E-3
-3
(WS)*E
0
(WS)*E+3
+3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16 tsu(EMCEL-EMWEL)
Output setup time,
EMA_CE[5:2] low to EMA_WE low (SS = 1)
Output hold time,
EMA_WE high to EMA_CE[5:2] high (SS = 0)
(WH)*E-3
-3
(WH)*E
0
(WH)*E+3
+3
17 th(EMWEH-EMCEH)
Output hold time,
EMA_WE high to EMA_CE[5:2] high (SS = 1)
Output setup time,
EMA_BA[1:0] valid to EMA_WE low
18 tsu(EMDQMV-EMWEL)
19 th(EMWEH-EMDQMIV)
20 tsu(EMBAV-EMWEL)
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E-3
(WH)*E-3
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E
(WH)*E
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
(WS)*E+3
(WH)*E+3
Output hold time,
EMA_WE high to EMA_BA[1:0] invalid
Output setup time,
EMA_BA[1:0] valid to EMA_WE low
Output hold time,
EMA_WE high to EMA_BA[1:0] invalid
Output setup time,
EMA_A[13:0] valid to EMA_WE low
Output hold time,
EMA_WE high to EMA_A[13:0] invalid
EMA_WE active low width (EW = 0)
EMA_WE active low width (EW = 1)
(WST)*E-3
(WST)*E
(WST)*E+3
ns
ns
24 tw(EMWEL)
(WST+(EWC*16))*E-3
(WST+(EWC*16))*E
(WST+(EWC*16))*E+3
Delay time from EMA_WAIT deasserted to
EMA_WE high
25 td(EMWAITH-EMWEH)
26 tsu(EMDV-EMWEL)
27 th(EMWEH-EMDIV)
3E-3
(WS)*E-3
(WH)*E-3
4E
(WS)*E
(WH)*E
4E+3
(WS)*E+3
(WH)*E+3
ns
ns
ns
Output setup time,
EMA_D[15:0] valid to EMA_WE low
Output hold time,
EMA_WE high to EMA_D[15:0] invalid
68
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
3
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[22:0]
EMA_WE_DQM[1:0]
EMA_A_RW
1
4
8
5
9
7
6
10
EMA_OE
13
12
EMA_D[15:0]
EMA_WE
Figure 5-13. Asynchronous Memory Read Timing for EMIFA
15
1
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[22:0]
EMA_WE_DQM[1:0]
EMA_A_RW
16
18
20
22
17
19
21
23
1
24
EMA_WE
26
27
EMA_D[15:0]
EMA_OE
Figure 5-14. Asynchronous Memory Write Timing for EMIFA
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
69
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
SETUP
STROBE
Extended Due to EMA_WAIT
STROBE HOLD
EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
EMA_A_RW
14
11
EMA_OE
2
2
EMA_WAIT
Asserted
Deasserted
Figure 5-15. EMA_WAIT Read Timing Requirements
Figure 5-16. EMA_WAIT Write Timing Requirements
70
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.11 External Memory Interface B (EMIFB)
Figure 5-17, EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its
connections within the device. Multiple requesters have access to EMIFB through a switched central
resource (indicated as crossbar in the figure). The EMIFB implements a split transaction internal bus,
allowing concurrence between reads and writes from the various requesters. See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
EMIFB
Registers
CPU
EMB_CS
EMB_CAS
EDMA
Cmd/Write
FIFO
EMB_RAS
EMB_WE
Crossbar
MPU2
Master
Peripherals
(USB, UHPI...)
EMB_CLK
SDRAM
Interface
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
Read
FIFO
EMB_D[x:0]
EMB_WE_DQM[x:0]
Figure 5-17. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
5.11.1 EMIFB SDRAM Loading Limitations
EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads. Additional
loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by
board simulation using IBIS models.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
71
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.11.2 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
•
•
•
•
Pre-charge bit is A[10]
Supports 8, 9, 10 or 11 column address bits.
Supports up to 13 row address bits is 13.
Supports 1, 2 or 4 internal banks.
Table 5-21 shows the supported SDRAM configurations for EMIFB.
Table 5-21. EMIFB Supported SDRAM Configurations(1)
SDRAM
Memory
Data
Bus Width
(bits)
Memory
Density
(Mbits)
Number of EMIFB Data
Total Memory Total Memory
Rows
Columns
Banks
Memories
Bus Size
(Mbits)
(Mbytes)
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
8
8
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
32
64
4
8
32
64
8
128
64
16
8
128
64
9
9
128
256
128
256
512
256
512
1024
32
16
32
16
32
64
32
64
128
4
128
256
128
256
512
256
512
1024
16
9
16
10
10
10
11
11
11
8
8
64
8
32
8
128
64
16
8
64
9
32
9
128
256
128
256
512
256
512
1024
16
32
16
32
64
32
64
128
64
9
128
64
8
10
10
10
11
11
11
128
256
128
256
512
(1) The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
Figure 5-18 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. In addition,
and shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 5-
22, as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 5-22, page size/column size (not indicated in the
table) is varied to get the required addressability range.
72
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
SDRAM
2M x 16 x 4
Bank
EMIFB
EMB_CS
CE
EMB_CAS
EMB_RAS
CAS
RAS
WE
EMB_WE
EMB_CLK
CLK
CKE
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
Figure 5-18. EMIFB to 2M × 16 × 4 Bank SDRAM Interface
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
73
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-22. Example of 16/32-Bit EMIFB Address Pin Connections
SDRAM SIZE
WIDTH
BANKS
MEMORY
SDRAM
EMIFB
ADDRESS PINS
64M bits
×16
4
A[11:0]
EMB_A[11:0]
A[10:0]
×32
×16
×32
×16
×32
×16
×32
4
4
4
4
4
4
4
SDRAM
EMIFB
EMB_A[10:0]
A[11:0]
128M bits
256M bits
512M bits
SDRAM
EMIFB
EMB_A[11:0]
A[11:0]
SDRAM
EMIFB
EMB_A[11:0]
A[12:0]
SDRAM
EMIFB
EMB_A[12:0]
A[11:0]
SDRAM
EMIFB
EMB_A[11:0]
A[12:0]
SDRAM
EMIFB
EMB_A[12:0]
A[12:0]
SDRAM
EMIFB
EMB_A[12:0]
Table 5-23 is a list of the EMIFB registers.
Table 5-23. EMIFB Base Controller Registers
BYTE ADDRESS
0xB000 0000
0xB000 0008
0xB000 000C
0xB000 0010
0xB000 0014
0xB000 001C
0xB000 0020
0xB000 0040
0xB000 0044
0xB000 0048
0xB000 004C
0xB000 0050
0xB000 00C0
0xB000 00C4
0xB000 00C8
0xB000 00CC
REGISTER NAME
REGISTER DESCRIPTION
MIDR
SDCFG
SDRFC
SDTIM1
SDTIM2
SDCFG2
BPRIO
PC1
Module ID Register
SDRAM Configuration Register
SDRAM Refresh Control Register
SDRAM Timing Register 1
SDRAM Timing Register 2
SDRAM Configuration 2 Register
Peripheral Bus Burst Priority Register
Performance Counter 1 Register
Performance Counter 2 Register
Performance Counter Configuration Register
Performance Counter Master Region Select Register
Performance Counter Time Register
Interrupt Raw Register
PC2
PCC
PCMRS
PCT
IRR
IMR
Interrupt Mask Register
IMSR
Interrupt Mask Set Register
IMCR
Interrupt Mask Clear Register
74
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.11.3 EMIFB Electrical Data/Timing
Table 5-24. EMIFB SDRAM Interface Timing Requirements
NO.
19
MIN
0.8
MAX UNIT
tsu(EMA_DV-EM_CLKH)
th(CLKH-DIV)
Input setup time, read data valid on EMB_D[31:0] before EMB_CLK rising
Input hold time, read data valid on EMB_D[31:0] after EMB_CLK rising
ns
ns
20
1.5
Table 5-25. EMIFB SDRAM Interface Switching Characteristics
NO.
1
PARAMETER
MIN
6.579
2.63
MAX UNIT
tc(CLK)
Cycle time, EMIF clock EMB_CLK
ns
ns
2
tw(CLK)
Pulse width, EMIF clock EMB_CLK high or low
3
td(CLKH-CSV)
toh(CLKH-CSIV)
td(CLKH-DQMV)
toh(CLKH-DQMIV)
td(CLKH-AV)
Delay time, EMB_CLK rising to EMB_CS[0] valid
Output hold time, EMB_CLK rising to EMB_CS[0] invalid
Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid
Output hold time, EMB_CLK rising to EMB_WE_DQM[3:0] invalid
Delay time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] valid
Output hold time, EMB_CLK rising to EMB_A[12:0] and EMB_BA[1:0] invalid
Delay time, EMB_CLK rising to EMB_D[31:0] valid
Output hold time, EMB_CLK rising to EMB_D[31:0] invalid
Delay time, EMB_CLK rising to EMB_RAS valid
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
5
6
7
8
toh(CLKH-AIV)
td(CLKH-DV)
9
10
11
12
13
14
15
16
17
18
toh(CLKH-DIV)
td(CLKH-RASV)
toh(CLKH-RASIV)
td(CLKH-CASV)
toh(CLKH-CASIV)
td(CLKH-WEV)
toh(CLKH-WEIV)
tdis(CLKH-DHZ)
tena(CLKH-DLZ)
Output hold time, EMB_CLK rising to EMB_RAS invalid
Delay time, EMB_CLK rising to EMB_CAS valid
Output hold time, EMB_CLK rising to EMB_CAS invalid
Delay time, EMB_CLK rising to EMB_WE valid
Output hold time, EMB_CLK rising to EMB_WE invalid
Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated
Output hold time, EMB_CLK rising to EMB_D[31:0] driving
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
75
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
1
BASIC SDRAM
WRITE OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
9
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
10
EMB_D[31:0]
EMB_RAS
EMB_CAS
EMB_WE
11
12
13
15
16
Figure 5-19. EMIFB Basic SDRAM Write Operation
1
BASIC SDRAM
READ OPERATION
2
2
EMB_CLK
EMB_CS[0]
3
5
7
7
4
6
EMB_WE_DQM[3:0]
EMB_BA[1:0]
8
8
EMB_A[12:0]
19
20
2 EM_CLK Delay
17
18
EMB_D[31:0]
EMB_RAS
11
12
13
14
EMB_CAS
EMB_WE
Figure 5-20. EMIFB Basic SDRAM Read Operation
76
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.12 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
•
•
•
•
•
•
•
Provides memory protection for fixed and programmable address ranges.
Supports multiple programmable address region.
Supports secure and debug access privileges.
Supports read, write, and execute access privileges.
Supports privid(8) associations with ranges.
Generates an interrupt when there is a protection violation, and saves violating transfer parameters.
MMR access is also protected.
Table 5-26. MPU1 Registers
BYTE ADDRESS
0x01E1 4000
0x01E1 4004
0x01E1 4010
0x01E1 4014
0x01E1 4018
0x01E1 401C
REGISTER NAME
REVID
REGISTER DESCRIPTION
Revision ID
CONFIG
Configuration
IRAWSTAT
IENSTAT
Interrupt raw status/set
Interrupt enable status/clear
IENSET
Interrupt enable
IENCLR
Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF
0x01E1 4200
-
Reserved
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
Programmable range 1, memory page protection attributes
Reserved
0x01E1 4204
0x01E1 4208
0x01E1 420C - 0x01E1 420F
0x01E1 4210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 4214
0x01E1 4218
0x01E1 421C - 0x01E1 421F
0x01E1 4220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 4224
0x01E1 4228
0x01E1 422C - 0x01E1 422F
0x01E1 4230
PROG4_MPSAR
PROG4_MPEA
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 4234
0x01E1 4238
0x01E1 423C - 0x01E1 423F
0x01E1 4240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 4244
0x01E1 4248
0x01E1 424C - 0x01E1 424F
0x01E1 4250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 4254
0x01E1 4258
0x01E1 425C - 0x01E1 42FF
0x01E1 4300
FLTADDRR
Fault address
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
77
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-26. MPU1 Registers (continued)
BYTE ADDRESS
0x01E1 4304
REGISTER NAME
REGISTER DESCRIPTION
Fault status
FLTSTAT
FLTCLR
-
0x01E1 4308
Fault clear
0x01E1 430C - 0x01E1 4FFF
Reserved
Table 5-27. MPU2 Registers
BYTE ADDRESS
0x01E1 5000
REGISTER NAME
REVID
REGISTER DESCRIPTION
Revision ID
0x01E1 5004
CONFIG
Configuration
0x01E1 5010
IRAWSTAT
IENSTAT
Interrupt raw status/set
Interrupt enable status/clear
Interrupt enable
0x01E1 5014
0x01E1 5018
IENSET
0x01E1 501C
IENCLR
Interrupt enable clear
Reserved
0x01E1 5020 - 0x01E1 51FF
0x01E1 5200
-
PROG1_MPSAR
PROG1_MPEAR
PROG1_MPPA
-
Programmable range 1, start address
Programmable range 1, end address
0x01E1 5204
0x01E1 5208
Programmable range 1, memory page protection attributes
Reserved
0x01E1 520C - 0x01E1 520F
0x01E1 5210
PROG2_MPSAR
PROG2_MPEAR
PROG2_MPPA
-
Programmable range 2, start address
Programmable range 2, end address
Programmable range 2, memory page protection attributes
Reserved
0x01E1 5214
0x01E1 5218
0x01E1 521C - 0x01E1 521F
0x01E1 5220
PROG3_MPSAR
PROG3_MPEAR
PROG3_MPPA
-
Programmable range 3, start address
Programmable range 3, end address
Programmable range 3, memory page protection attributes
Reserved
0x01E1 5224
0x01E1 5228
0x01E1 522C - 0x01E1 522F
0x01E1 5230
PROG4_MPSAR
PROG4_MPEA
PROG4_MPPA
-
Programmable range 4, start address
Programmable range 4, end address
Programmable range 4, memory page protection attributes
Reserved
0x01E1 5234
0x01E1 5238
0x01E1 523C - 0x01E1 523F
0x01E1 5240
PROG5_MPSAR
PROG5_MPEAR
PROG5_MPPA
-
Programmable range 5, start address
Programmable range 5, end address
Programmable range 5, memory page protection attributes
Reserved
0x01E1 5244
0x01E1 5248
0x01E1 524C - 0x01E1 524F
0x01E1 5250
PROG6_MPSAR
PROG6_MPEAR
PROG6_MPPA
-
Programmable range 6, start address
Programmable range 6, end address
Programmable range 6, memory page protection attributes
Reserved
0x01E1 5254
0x01E1 5258
0x01E1 525C - 0x01E1 525F
0x01E1 5260
PROG7_MPSAR
PROG7_MPEAR
PROG7_MPPA
-
Programmable range 7, start address
Programmable range 7, end address
Programmable range 7, memory page protection attributes
Reserved
0x01E1 5264
0x01E1 5268
0x01E1 526C - 0x01E1 526F
0x01E1 5270
PROG8_MPSAR
PROG8_MPEAR
PROG8_MPPA
-
Programmable range 8, start address
Programmable range 8, end address
Programmable range 8, memory page protection attributes
Reserved
0x01E1 5274
0x01E1 5278
0x01E1 527C - 0x01E1 527F
0x01E1 5280
PROG9_MPSAR
PROG9_MPEAR
Programmable range 9, start address
Programmable range 9, end address
0x01E1 5284
78
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-27. MPU2 Registers (continued)
BYTE ADDRESS
REGISTER NAME
PROG9_MPPA
-
REGISTER DESCRIPTION
0x01E1 5288
Programmable range 9, memory page protection attributes
Reserved
0x01E1 528C - 0x01E1 528F
0x01E1 5290
PROG10_MPSAR
PROG10_MPEAR
PROG10_MPPA
-
Programmable range 10, start address
Programmable range 10,end address
Programmable range 10, memory page protection attributes
Reserved
0x01E1 5294
0x01E1 5298
0x01E1 529C - 0x01E1 529F
0x01E1 52A0
PROG11_MPSAR
PROG11_MPEAR
PROG11_MPPA
-
Programmable range 11, start address
Programmable range 11, end address
Programmable range 11, memory page protection attributes
Reserved
0x01E1 52A4
0x01E1 52A8
0x01E1 52AC - 0x01E1 52AF
0x01E1 52B0
PROG12_MPSAR
PROG12_MPEAR
PROG12_MPPA
-
Programmable range 12, start address
Programmable range 12, end address
Programmable range 12, memory page protection attributes
Reserved
0x01E1 52B4
0x01E1 52B8
0x01E1 52BC - 0x01E1 52FF
0x01E1 5300
FLTADDRR
FLTSTAT
Fault address
0x01E1 5304
Fault status
0x01E1 5308
FLTCLR
Fault clear
0x01E1 530C - 0x01E1 5FFF
-
Reserved
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
79
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.13 MMC / SD / SDIO (MMCSD)
The C6743 includes an MMCSD controller which is compliant with MMC V3.31, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications. See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
The MMC/SD Controller has following features:
•
•
•
•
•
•
•
•
MultiMediaCard (MMC)
Secure Digital (SD) Memory Card
MMC/SD protocol support
SD high capacity support
SDIO protocol support
Programmable clock frequency
512 bit Read/Write FIFO to lower system overhead
Slave EDMA transfer capability
The C6743 MMC/SD Controller does not support SPI mode.
5.13.1 MMCSD Peripheral Register Description(s)
Table 5-28. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
BYTE ADDRESS
0x01C4 0000
0x01C4 0004
0x01C4 0008
0x01C4 000C
0x01C4 0010
0x01C4 0014
0x01C4 0018
0x01C4 001C
0x01C4 0020
0x01C4 0024
0x01C4 0028
0x01C4 002C
0x01C4 0030
0x01C4 0034
0x01C4 0038
0x01C4 003C
0x01C4 0040
0x01C4 0044
0x01C4 0048
0x01C4 0050
0x01C4 0064
0x01C4 0068
0x01C4 006C
0x01C4 0070
0x01C4 0074
REGISTER NAME
MMCCTL
REGISTER DESCRIPTION
MMC Control Register
MMCCLK
MMC Memory Clock Control Register
MMC Status Register 0
MMCST0
MMCST1
MMC Status Register 1
MMCIM
MMC Interrupt Mask Register
MMC Response Time-Out Register
MMC Data Read Time-Out Register
MMC Block Length Register
MMC Number of Blocks Register
MMC Number of Blocks Counter Register
MMC Data Receive Register
MMC Data Transmit Register
MMC Command Register
MMCTOR
MMCTOD
MMCBLEN
MMCNBLK
MMCNBLC
MMCDRR
MMCDXR
MMCCMD
MMCARGHL
MMCRSP01
MMCRSP23
MMCRSP45
MMCRSP67
MMCDRSP
MMCCIDX
SDIOCTL
MMC Argument Register
MMC Response Register 0 and 1
MMC Response Register 2 and 3
MMC Response Register 4 and 5
MMC Response Register 6 and 7
MMC Data Response Register
MMC Command Index Register
SDIO Control Register
SDIOST0
SDIO Status Register 0
SDIOIEN
SDIO Interrupt Enable Register
SDIO Interrupt Status Register
MMC FIFO Control Register
SDIOIST
MMCFIFOCTL
80
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.13.2 MMC/SD Electrical Data/Timing
Table 5-29. Timing Requirements for MMC/SD Module
(see Figure 5-22 and Figure 5-24)
NO.
1
MIN
3.2
1.5
3.2
1.5
MAX UNIT
tsu(CMDV-CLKH)
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Setup time, MMCSD_CMD valid before MMCSD_CLK high
Hold time, MMCSD_CMD valid after MMCSD_CLK high
Setup time, MMCSD_DATx valid before MMCSD_CLK high
Hold time, MMCSD_DATx valid after MMCSD_CLK high
ns
ns
ns
ns
2
3
4
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 5-21 through Figure 5-24)
NO.
7
PARAMETER
MIN
0
MAX UNIT
f(CLK)
Operating frequency, MMCSD_CLK
Identification mode frequency, MMCSD_CLK
Pulse width, MMCSD_CLK low
52
ns
ns
ns
ns
ns
ns
ns
ns
8
f(CLK_ID)
tW(CLKL)
tW(CLKH)
tr(CLK)
0
400
9
6.5
6.5
10
11
12
13
14
Pulse width, MMCSD_CLK high
Rise time, MMCSD_CLK
3
3
tf(CLK)
Fall time, MMCSD_CLK
td(CLKL-CMD)
td(CLKL-DAT)
Delay time, MMCSD_CLK low to MMCSD_CMD transition
Delay time, MMCSD_CLK low to MMCSD_DATx transition
-4.5
-4.5
2.5
2.5
10
9
7
MMCSD_CLK
MMCSD_CMD
13
13
13
13
START
XMIT
Valid
Valid
Valid
END
Figure 5-21. MMC/SD Host Command Timing
9
10
7
MMCSD_CLK
MMCSD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 5-22. MMC/SD Card Response Timing
10
9
7
MMCSD_CLK
MMCSD_DATx
14
14
14
Dx
14
START
D0
D1
END
Figure 5-23. MMC/SD Host Write Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
81
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
9
10
7
MMCSD_CLK
4
4
3
Start
3
MMCSD_DATx
D0
D1
Dx
End
Figure 5-24. MMC/SD Host Read and Card CRC Status Timing
82
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.14 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between C6743 and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the C6743 device to the PHY. The MDIO module controls
PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the C6743 device through a custom interface that
allows efficient data transmission and reception. This custom interface is referred to as the EMAC control
module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to
multiplex and control interrupts. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview
Reference Guide(SPRUFK9) for more details.
5.14.1 EMAC Peripheral Register Description(s)
Table 5-31. Ethernet Media Access Controller (EMAC) Registers
BYTE ADDRESS
0x01E2 3000
0x01E2 3004
0x01E2 3008
0x01E2 3010
0x01E2 3014
0x01E2 3018
0x01E2 3080
0x01E2 3084
0x01E2 3088
0x01E2 308C
0x01E2 3090
0x01E2 3094
0x01E2 30A0
0x01E2 30A4
0x01E2 30A8
0x01E2 30AC
0x01E2 30B0
0x01E2 30B4
0x01E2 30B8
0x01E2 30BC
0x01E2 3100
0x01E2 3104
0x01E2 3108
0x01E2 310C
0x01E2 3110
0x01E2 3114
0x01E2 3120
0x01E2 3124
0x01E2 3128
0x01E2 312C
0x01E2 3130
0x01E2 3134
0x01E2 3138
REGISTER NAME
TXREV
REGISTER DESCRIPTION
Transmit Revision Register
TXCONTROL
Transmit Control Register
TXTEARDOWN
RXREV
Transmit Teardown Register
Receive Revision Register
RXCONTROL
Receive Control Register
RXTEARDOWN
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACEOIVECTOR
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
Receive Teardown Register
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Clear Register
MAC Input Vector Register
MAC End Of Interrupt Vector Register
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
RXBUFFEROFFSET
RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
83
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-31. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
0x01E2 313C
0x01E2 3140
0x01E2 3144
0x01E2 3148
0x01E2 314C
0x01E2 3150
0x01E2 3154
0x01E2 3158
0x01E2 315C
0x01E2 3160
0x01E2 3164
0x01E2 3168
0x01E2 316C
0x01E2 3170
0x01E2 3174
0x01E2 31D0
0x01E2 31D4
0x01E2 31D8
0x01E2 31DC
0x01E2 31E0
0x01E2 31E4
0x01E2 31E8
0x01E2 31EC
REGISTER NAME
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
REGISTER DESCRIPTION
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
Receive Channel 4 Free Buffer Count Register
Receive Channel 5 Free Buffer Count Register
Receive Channel 6 Free Buffer Count Register
Receive Channel 7 Free Buffer Count Register
MAC Control Register
MAC Status Register
EMCONTROL
Emulation Control Register
FIFOCONTROL
MACCONFIG
FIFO Control Register
MAC Configuration Register
SOFTRESET
Soft Reset Register
MACSRCADDRLO
MACSRCADDRHI
MACHASH1
MAC Source Address Low Bytes Register
MAC Source Address High Bytes Register
MAC Hash Address Register 1
MACHASH2
MAC Hash Address Register 2
BOFFTEST
Back Off Test Register
TPACETEST
Transmit Pacing Algorithm Test Register
Receive Pause Timer Register
RXPAUSE
TXPAUSE
Transmit Pause Timer Register
0x01E2 3200 - 0x01E2 32FC (see Table 5-32)
EMAC Statistics Registers
0x01E2 3500
0x01E2 3504
0x01E2 3508
0x01E2 3600
0x01E2 3604
0x01E2 3608
0x01E2 360C
0x01E2 3610
0x01E2 3614
0x01E2 3618
0x01E2 361C
0x01E2 3620
0x01E2 3624
0x01E2 3628
0x01E2 362C
0x01E2 3630
0x01E2 3634
0x01E2 3638
0x01E2 363C
0x01E2 3640
0x01E2 3644
0x01E2 3648
0x01E2 364C
MACADDRLO
MACADDRHI
MACINDEX
TX0HDP
TX1HDP
TX2HDP
TX3HDP
TX4HDP
TX5HDP
TX6HDP
TX7HDP
RX0HDP
RX1HDP
RX2HDP
RX3HDP
RX4HDP
RX5HDP
RX6HDP
RX7HDP
TX0CP
MAC Address Low Bytes Register, Used in Receive Address Matching
MAC Address High Bytes Register, Used in Receive Address Matching
MAC Index Register
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
Receive Channel 1 DMA Head Descriptor Pointer Register
Receive Channel 2 DMA Head Descriptor Pointer Register
Receive Channel 3 DMA Head Descriptor Pointer Register
Receive Channel 4 DMA Head Descriptor Pointer Register
Receive Channel 5 DMA Head Descriptor Pointer Register
Receive Channel 6 DMA Head Descriptor Pointer Register
Receive Channel 7 DMA Head Descriptor Pointer Register
Transmit Channel 0 Completion Pointer Register
TX1CP
Transmit Channel 1 Completion Pointer Register
TX2CP
Transmit Channel 2 Completion Pointer Register
TX3CP
Transmit Channel 3 Completion Pointer Register
84
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-31. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS
REGISTER NAME
TX4CP
REGISTER DESCRIPTION
0x01E2 3650
0x01E2 3654
0x01E2 3658
0x01E2 365C
0x01E2 3660
0x01E2 3664
0x01E2 3668
0x01E2 366C
0x01E2 3670
0x01E2 3674
0x01E2 3678
0x01E2 367C
Transmit Channel 4 Completion Pointer Register
Transmit Channel 5 Completion Pointer Register
Transmit Channel 6 Completion Pointer Register
Transmit Channel 7 Completion Pointer Register
Receive Channel 0 Completion Pointer Register
Receive Channel 1 Completion Pointer Register
Receive Channel 2 Completion Pointer Register
Receive Channel 3 Completion Pointer Register
Receive Channel 4 Completion Pointer Register
Receive Channel 5 Completion Pointer Register
Receive Channel 6 Completion Pointer Register
Receive Channel 7 Completion Pointer Register
TX5CP
TX6CP
TX7CP
RX0CP
RX1CP
RX2CP
RX3CP
RX4CP
RX5CP
RX6CP
RX7CP
Table 5-32. EMAC Statistics Registers
BYTE ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
0x01E2 3200
RXGOODFRAMES
Good Receive Frames Register
Broadcast Receive Frames Register
(Total number of good broadcast frames received)
0x01E2 3204
RXBCASTFRAMES
Multicast Receive Frames Register
(Total number of good multicast frames received)
0x01E2 3208
0x01E2 320C
0x01E2 3210
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
Pause Receive Frames Register
Receive CRC Errors Register
(Total number of frames received with CRC errors)
Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors)
0x01E2 3214
0x01E2 3218
0x01E2 321C
0x01E2 3220
RXALIGNCODEERRORS
RXOVERSIZED
Receive Oversized Frames Register
(Total number of oversized frames received)
Receive Jabber Frames Register
(Total number of jabber frames received)
RXJABBER
Receive Undersized Frames Register
(Total number of undersized frames received)
RXUNDERSIZED
0x01E2 3224
0x01E2 3228
0x01E2 322C
RXFRAGMENTS
RXFILTERED
Receive Frame Fragments Register
Filtered Receive Frames Register
Received QOS Filtered Frames Register
RXQOSFILTERED
Receive Octet Frames Register
(Total number of received bytes in good frames)
0x01E2 3230
0x01E2 3234
RXOCTETS
Good Transmit Frames Register
(Total number of good frames transmitted)
TXGOODFRAMES
0x01E2 3238
0x01E2 323C
0x01E2 3240
0x01E2 3244
0x01E2 3248
0x01E2 324C
0x01E2 3250
0x01E2 3254
0x01E2 3258
0x01E2 325C
0x01E2 3260
0x01E2 3264
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Transmit Collision Frames Register
Transmit Single Collision Frames Register
Transmit Multiple Collision Frames Register
Transmit Excessive Collision Frames Register
Transmit Late Collision Frames Register
Transmit Underrun Error Register
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
TXEXCESSIVECOLL
TXLATECOLL
TXUNDERRUN
TXCARRIERSENSE
TXOCTETS
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
85
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-32. EMAC Statistics Registers (continued)
BYTE ADDRESS
0x01E2 3268
0x01E2 326C
0x01E2 3270
0x01E2 3274
0x01E2 3278
0x01E2 327C
0x01E2 3280
0x01E2 3284
0x01E2 3288
0x01E2 328C
REGISTER NAME
FRAME64
REGISTER DESCRIPTION
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
Transmit and Receive 1024 to 1518 Octet Frames Register
Network Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
FRAME1024TUP
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
Receive FIFO or DMA Start of Frame Overruns Register
Receive FIFO or DMA Middle of Frame Overruns Register
Receive DMA Start of Frame and Middle of Frame Overruns Register
Table 5-33. EMAC Control Module Registers
BYTE ADDRESS
0x01E2 2000
0x01E2 2004
0x01E2 200C
0x01E2 2010
0x01E2 2014
0x01E2 2018
0x01E2 201C
0x01E2 2020
0x01E2 2024
0x01E2 2028
0x01E2 202C
0x01E2 2030
0x01E2 2034
0x01E2 2038
0x01E2 203C
0x01E2 2040
0x01E2 2044
0x01E2 2048
0x01E2 204C
0x01E2 2050
0x01E2 2054
0x01E2 2058
0x01E2 205C
0x01E2 2060
0x01E2 2064
0x01E2 2068
0x01E2 206C
0x01E2 2070
0x01E2 2074
0x01E2 2078
0x01E2 207C
0x01E2 2080
0x01E2 2084
REGISTER NAME
REV
REGISTER DESCRIPTION
EMAC Control Module Revision Register
SOFTRESET
INTCONTROL
C0RXTHRESHEN
C0RXEN
EMAC Control Module Software Reset Register
EMAC Control Module Interrupt Control Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
C0TXEN
C0MISCEN
C1RXTHRESHEN
C1RXEN
C1TXEN
C1MISCEN
C2RXTHRESHEN
C2RXEN
C2TXEN
C2MISCEN
C0RXTHRESHSTAT
C0RXSTAT
C0TXSTAT
C0MISCSTAT
C1RXTHRESHSTAT
C1RXSTAT
C1TXSTAT
C1MISCSTAT
C2RXTHRESHSTAT
C2RXSTAT
C2TXSTAT
C2MISCSTAT
C0RXIMAX
C0TXIMAX
C1RXIMAX
C1TXIMAX
C2RXIMAX
C2TXIMAX
86
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-34. EMAC Control Module RAM
BYTE ADDRESS
DESCRIPTION
EMAC Local Buffer Descriptor Memory
0x01E2 0000 - 0x01E2 1FFF
5.14.2 EMAC Electrical Data/Timing
Table 5-35. RMII Timing Requirements(1)
NO.
1
MIN
TYP MAX UNIT
tc(REFCLK)
Cycle Time, RMII_MHZ_50_CLK
20
ns
ns
ns
ns
ns
ns
2
tw(REFCLKH)
tw(REFCLKL)
Pulse Width, RMII_MHZ_50_CLK High
7
7
4
2
4
13
13
3
Pulse Width, RMII_MHZ_50_CLK Low
6
tsu(RXD-REFCLK)
th(REFCLK-RXD)
Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High
Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High
Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High
7
8
tsu(CRSDV-
REFCLK)
9
th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High
tsu(RXER-REFCLK) Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High
th(REFCLKR-RXER) Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High
2
4
2
ns
ns
ns
10
11
(1) Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.
Table 5-36. RMII Switching Characteristics
NO.
4
MIN TYP
MAX UNIT
td(REFCLK-TXD)
td(REFCLK-TXEN)
Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid
Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid
2.5
2.5
13
13
ns
ns
5
1
2
3
RMII_MHz_50_CLK
5
5
RMII_TXEN
4
RMII_TXD[1:0]
6
7
RMII_RXD[1:0]
RMII_CRS_DV
8
9
10
11
RMII_RXER
Figure 5-25. RMII Timing Diagram
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
87
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.15 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time. See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
5.15.1 MDIO Peripheral Register Description(s)
For a list of supported MDIO registers see Table 5-37 [MDIO Registers].
Table 5-37. MDIO Register Memory Map
BYTE ADDRESS
0x01E2 4000
REGISTER NAME
REV
REGISTER DESCRIPTION
Revision Identification Register
0x01E2 4004
CONTROL
MDIO Control Register
0x01E2 4008
ALIVE
MDIO PHY Alive Status Register
0x01E2 400C
LINK
MDIO PHY Link Status Register
0x01E2 4010
LINKINTRAW
LINKINTMASKED
–
MDIO Link Status Change Interrupt (Unmasked) Register
MDIO Link Status Change Interrupt (Masked) Register
Reserved
0x01E2 4014
0x01E2 4018
0x01E2 4020
USERINTRAW
USERINTMASKED
USERINTMASKSET
USERINTMASKCLEAR
–
MDIO User Command Complete Interrupt (Unmasked) Register
MDIO User Command Complete Interrupt (Masked) Register
MDIO User Command Complete Interrupt Mask Set Register
MDIO User Command Complete Interrupt Mask Clear Register
Reserved
0x01E2 4024
0x01E2 4028
0x01E2 402C
0x01E2 4030 - 0x01E2 407C
0x01E2 4080
USERACCESS0
USERPHYSEL0
USERACCESS1
USERPHYSEL1
–
MDIO User Access Register 0
0x01E2 4084
MDIO User PHY Select Register 0
MDIO User Access Register 1
0x01E2 4088
0x01E2 408C
MDIO User PHY Select Register 1
Reserved
0x01E2 4090 - 0x01E2 47FF
5.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 5-38. Timing Requirements for MDIO Input (see Figure 5-26 and Figure 5-27)
NO.
1
MIN
400
180
MAX UNIT
tc(MDIO_CLK)
Cycle time, MDIO_CLK
ns
ns
2
tw(MDIO_CLK)
Pulse duration, MDIO_CLK high/low
3
tt(MDIO_CLK)
Transition time, MDIO_CLK
5
ns
ns
ns
4
tsu(MDIO-MDIO_CLKH)
th(MDIO_CLKH-MDIO)
Setup time, MDIO_D data input valid before MDIO_CLK high
Hold time, MDIO_D data input valid after MDIO_CLK high
10
0
5
88
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
1
3
3
MDIO_CLK
4
5
MDIO_D
(input)
Figure 5-26. MDIO Input Timing
Table 5-39. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 5-27)
NO.
PARAMETER
MIN
MAX UNIT
100 ns
7
td(MDIO_CLKL-MDIO)
Delay time, MDIO_CLK low to MDIO_D data output valid
0
1
MDIO_CLK
7
MDIO_D
(output)
Figure 5-27. MDIO Output Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
89
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.16 Multichannel Audio Serial Ports (McASP0, McASP1)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
•
•
•
Flexible clock and frame sync generation logic and on-chip dividers
Up to fourteen transmit or receive data pins and serializers
Large number of serial data format options, including:
–
–
–
–
–
TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
Time slots of 8,12,16, 20, 24, 28, and 32 bits
First bit delay 0, 1, or 2 clocks
MSB or LSB first bit order
Left- or right-aligned data words within time slots
•
•
Extensive error checking and mute generation logic
All unused pins GPIO-capable
Additionally, while the McASP modules are backward compatible with the McASP on previous devices; the
McASP also includes the following new features:
•
Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
•
Dynamic Adjustment of Clock Dividers
–
Clock Divider Value may be changed without resetting the McASP
See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for
more details.
The three McASPs on the C6743 are configured with the following options:
Table 5-40. C6743 McASP Configurations(1)
MODULE
SERIALIZERS
AFIFO
DIT
C6743 PINS
64 Word RX
64 Word TX
AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0,
AFSX0
McASP0
16
N
64 Word RX
64 Word TX
AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1,
ACLKX1, AFSX1, AMUTE1
McASP1
12
N
(1) Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Pins Function
AHCLKRx Receive Master Clock
Receive Logic
Clock/Frame Generator
State Machine
Peripheral
Configuration
Bus
GIO
Control
ACLKRx
AFSRx
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
The McASPs DO NOT have
dedicated AMUTEINx pins.
AMUTEINx
AMUTEx
Clock Check and
Error Detection
AFSXx
Transmit Left/Right Clock or Frame Sync
Transmit Bit Clock
Transmit Master Clock
Transmit Logic
Clock/Frame Generator
State Machine
ACLKXx
AHCLKXx
Transmit
Formatter
Serializer 0
Serializer 1
AXRx[0]
AXRx[1]
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
McASP
DMA Bus
(Dedicated)
Receive
Formatter
Serializer y
AXRx[y]
Transmit/Receive Serial Data Pin
McASPx (x = 0, 1)
Figure 5-28. McASP Block Diagram
90
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.16.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 5-41. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 5-42
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 5-43. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 5-41. McASP Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE
McASP1
BYTE
REGISTER NAME
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01D0 0000
0x01D0 0010
0x01D0 0014
0x01D0 0018
0x01D0 001C
0x01D0 001C
0x01D0 0020
0x01D0 0044
0x01D0 0048
0x01D0 004C
0x01D0 0050
0x01D0 0060
0x01D0 4000
0x01D0 4010
0x01D0 4014
0x01D0 4018
0x01D0 401C
0x01D0 401C
0x01D0 4020
0x01D0 4044
0x01D0 4048
0x01D0 404C
0x01D0 4050
0x01D0 4060
REV
Revision identification register
Pin function register
PFUNC
PDIR
Pin direction register
PDOUT
PDIN
Pin data output register
Read returns: Pin data input register
Writes affect: Pin data set register (alternate write address: PDOUT)
Pin data clear register (alternate write address: PDOUT)
Global control register
PDSET
PDCLR
GBLCTL
AMUTE
DLBCTL
DITCTL
RGBLCTL
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only receive bits
are affected - allows receiver to be reset independently from
transmitter
0x01D0 0064
0x01D0 0068
0x01D0 006C
0x01D0 0070
0x01D0 0074
0x01D0 0078
0x01D0 007C
0x01D0 0080
0x01D0 0084
0x01D0 0088
0x01D0 008C
0x01D0 00A0
0x01D0 4064
0x01D0 4068
0x01D0 406C
0x01D0 4070
0x01D0 4074
0x01D0 4078
0x01D0 407C
0x01D0 4080
0x01D0 4084
0x01D0 4088
0x01D0 408C
0x01D0 40A0
RMASK
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
RFMT
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
Receive high-frequency clock control register
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
RINTCTL
RSTAT
RSLOT
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
RCLKCHK
REVTCTL
XGBLCTL
Transmitter global control register. Alias of GBLCTL, only transmit
bits are affected - allows transmitter to be reset independently from
receiver
0x01D0 00A4
0x01D0 00A8
0x01D0 00AC
0x01D0 00B0
0x01D0 00B4
0x01D0 00B8
0x01D0 00BC
0x01D0 00C0
0x01D0 00C4
0x01D0 00C8
0x01D0 00CC
0x01D0 40A4
0x01D0 40A8
0x01D0 40AC
0x01D0 40B0
0x01D0 40B4
0x01D0 40B8
0x01D0 40BC
0x01D0 40C0
0x01D0 40C4
0x01D0 40C8
0x01D0 40CC
XMASK
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
XFMT
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
XINTCTL
XSTAT
XSLOT
Current transmit TDM time slot register
Transmit clock check control register
Transmitter DMA event control register
XCLKCHK
XEVTCTL
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
91
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-41. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
McASP1
BYTE
REGISTER NAME
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01D0 0100
0x01D0 0104
0x01D0 0108
0x01D0 010C
0x01D0 0110
0x01D0 0114
0x01D0 0118
0x01D0 011C
0x01D0 0120
0x01D0 0124
0x01D0 0128
0x01D0 012C
0x01D0 0130
0x01D0 0134
0x01D0 0138
0x01D0 013C
0x01D0 0140
0x01D0 0144
0x01D0 0148
0x01D0 014C
0x01D0 0150
0x01D0 0154
0x01D0 0158
0x01D0 015C
0x01D0 0180
0x01D0 0184
0x01D0 0188
0x01D0 018C
0x01D0 0190
0x01D0 0194
0x01D0 0198
0x01D0 019C
0x01D0 01A0
0x01D0 01A4
0x01D0 01A8
0x01D0 01AC
0x01D0 01B0
0x01D0 01B4
0x01D0 01B8
0x01D0 01BC
0x01D0 4100
0x01D0 4104
0x01D0 4108
0x01D0 410C
0x01D0 4110
0x01D0 4114
0x01D0 4118
0x01D0 411C
0x01D0 4120
0x01D0 4124
0x01D0 4128
0x01D0 412C
0x01D0 4130
0x01D0 4134
0x01D0 4138
0x01D0 413C
0x01D0 4140
0x01D0 4144
0x01D0 4148
0x01D0 414C
0x01D0 4150
0x01D0 4154
0x01D0 4158
0x01D0 415C
0x01D0 4180
0x01D0 4184
0x01D0 4188
0x01D0 418C
0x01D0 4190
0x01D0 4194
0x01D0 4198
0x01D0 419C
0x01D0 41A0
0x01D0 41A4
0x01D0 41A8
0x01D0 41AC
0x01D0 41B0
0x01D0 41B4
0x01D0 41B8
0x01D0 41BC
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
SRCTL0
Left (even TDM time slot) channel status register (DIT mode) 0
Left (even TDM time slot) channel status register (DIT mode) 1
Left (even TDM time slot) channel status register (DIT mode) 2
Left (even TDM time slot) channel status register (DIT mode) 3
Left (even TDM time slot) channel status register (DIT mode) 4
Left (even TDM time slot) channel status register (DIT mode) 5
Right (odd TDM time slot) channel status register (DIT mode) 0
Right (odd TDM time slot) channel status register (DIT mode) 1
Right (odd TDM time slot) channel status register (DIT mode) 2
Right (odd TDM time slot) channel status register (DIT mode) 3
Right (odd TDM time slot) channel status register (DIT mode) 4
Right (odd TDM time slot) channel status register (DIT mode) 5
Left (even TDM time slot) channel user data register (DIT mode) 0
Left (even TDM time slot) channel user data register (DIT mode) 1
Left (even TDM time slot) channel user data register (DIT mode) 2
Left (even TDM time slot) channel user data register (DIT mode) 3
Left (even TDM time slot) channel user data register (DIT mode) 4
Left (even TDM time slot) channel user data register (DIT mode) 5
Right (odd TDM time slot) channel user data register (DIT mode) 0
Right (odd TDM time slot) channel user data register (DIT mode) 1
Right (odd TDM time slot) channel user data register (DIT mode) 2
Right (odd TDM time slot) channel user data register (DIT mode) 3
Right (odd TDM time slot) channel user data register (DIT mode) 4
Right (odd TDM time slot) channel user data register (DIT mode) 5
Serializer control register 0
SRCTL1
Serializer control register 1
SRCTL2
Serializer control register 2
SRCTL3
Serializer control register 3
SRCTL4
Serializer control register 4
SRCTL5
Serializer control register 5
SRCTL6
Serializer control register 6
SRCTL7
Serializer control register 7
SRCTL8
Serializer control register 8
SRCTL9
Serializer control register 9
SRCTL10
SRCTL11
SRCTL12
SRCTL13
SRCTL14
SRCTL15
Serializer control register 10
Serializer control register 11
Serializer control register 12
Serializer control register 13
Serializer control register 14
Serializer control register 15
92
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-41. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0
BYTE
McASP1
BYTE
REGISTER NAME
REGISTER DESCRIPTION
ADDRESS
ADDRESS
0x01D0 0200
0x01D0 0204
0x01D0 0208
0x01D0 020C
0x01D0 0210
0x01D0 0214
0x01D0 0218
0x01D0 021C
0x01D0 0220
0x01D0 0224
0x01D0 0228
0x01D0 022C
0x01D0 0230
0x01D0 0234
0x01D0 0238
0x01D0 023C
0x01D0 0280
0x01D0 0284
0x01D0 0288
0x01D0 028C
0x01D0 0290
0x01D0 0294
0x01D0 0298
0x01D0 029C
0x01D0 02A0
0x01D0 02A4
0x01D0 02A8
0x01D0 02AC
0x01D0 02B0
0x01D0 02B4
0x01D0 02B8
0x01D0 02BC
0x01D0 4200
0x01D0 4204
0x01D0 4208
0x01D0 420C
0x01D0 4210
0x01D0 4214
0x01D0 4218
0x01D0 421C
0x01D0 4220
0x01D0 4224
0x01D0 4228
0x01D0 422C
0x01D0 4230
0x01D0 4234
0x01D0 4238
0x01D0 423C
0x01D0 4280
0x01D0 4284
0x01D0 4288
0x01D0 428C
0x01D0 4290
0x01D0 4294
0x01D0 4298
0x01D0 429C
0x01D0 42A0
0x01D0 42A4
0x01D0 42A8
0x01D0 42AC
0x01D0 42B0
0x01D0 42B4
0x01D0 42B8
0x01D0 42BC
XBUF0(1)
XBUF1(1)
XBUF2(1)
XBUF3(1)
XBUF4(1)
XBUF5(1)
XBUF6(1)
XBUF7(1)
XBUF8(1)
XBUF9(1)
XBUF10(1)
XBUF11(1)
XBUF12(1)
XBUF13(1)
XBUF14(1)
XBUF15(1)
RBUF0(2)
RBUF1(2)
RBUF2(2)
RBUF3(2)
RBUF4(2)
RBUF5(2)
RBUF6(2)
RBUF7(2)
RBUF8(2)
RBUF9(2)
RBUF10(2)
RBUF11(2)
RBUF12(2)
RBUF13(2)
RBUF14(2)
RBUF15(2)
Transmit buffer register for serializer 0
Transmit buffer register for serializer 1
Transmit buffer register for serializer 2
Transmit buffer register for serializer 3
Transmit buffer register for serializer 4
Transmit buffer register for serializer 5
Transmit buffer register for serializer 6
Transmit buffer register for serializer 7
Transmit buffer register for serializer 8
Transmit buffer register for serializer 9
Transmit buffer register for serializer 10
Transmit buffer register for serializer 11
Transmit buffer register for serializer 12
Transmit buffer register for serializer 13
Transmit buffer register for serializer 14
Transmit buffer register for serializer 15
Receive buffer register for serializer 0
Receive buffer register for serializer 1
Receive buffer register for serializer 2
Receive buffer register for serializer 3
Receive buffer register for serializer 4
Receive buffer register for serializer 5
Receive buffer register for serializer 6
Receive buffer register for serializer 7
Receive buffer register for serializer 8
Receive buffer register for serializer 9
Receive buffer register for serializer 10
Receive buffer register for serializer 11
Receive buffer register for serializer 12
Receive buffer register for serializer 13
Receive buffer register for serializer 14
Receive buffer register for serializer 15
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
Table 5-42. McASP Registers Accessed Through DMA Port
HEX
McASP0
McASP1
REGISTER REGISTER DESCRIPTION
ADDRESS
BYTE ADDRESS
BYTE ADDRESS NAME
Read
Accesses
01D0 2000
01D0 6000
01D0 6000
RBUF
XBUF
Receive buffer DMA port address. Cycles through receive serializers,
skipping over transmit serializers and inactive serializers. Starts at
the lowest serializer at the beginning of each time slot. Reads from
DMA port only if XBUSEL = 0 in XFMT.
Write
Accesses
01D0 2000
Transmit buffer DMA port address. Cycles through transmit
serializers, skipping over receive and inactive serializers. Starts at
the lowest serializer at the beginning of each time slot. Writes to
DMA port only if RBUSEL = 0 in RFMT.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
93
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-43. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
McASP0
McASP1
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
0x01D0 1000
0x01D0 1010
0x01D0 1014
0x01D0 1018
0x01D0 101C
0x01D0 5000
0x01D0 5010
0x01D0 5014
0x01D0 5018
0x01D0 501C
AFIFOREV
WFIFOCTL
WFIFOSTS
RFIFOCTL
RFIFOSTS
AFIFO revision identification register
Write FIFO control register
Write FIFO status register
Read FIFO control register
Read FIFO status register
5.16.2 McASP Electrical Data/Timing
5.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 5-44 and Table 5-45 assume testing over recommended operating conditions (see Figure 5-29 and
Figure 5-30).
Table 5-44. McASP0 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR0 external, AHCLKR0 input
Cycle time, AHCLKX0 external, AHCLKX0 input
Pulse duration, AHCLKR0 external, AHCLKR0 input
Pulse duration, AHCLKX0 external, AHCLKX0 input
Cycle time, ACLKR0 external, ACLKR0 input
25
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
25
12.5
2
3
4
ns
ns
ns
12.5
greater of 2P or 25
Cycle time, ACLKX0 external, ACLKX0 input
greater of 2P or 25
Pulse duration, ACLKR0 external, ACLKR0 input
Pulse duration, ACLKX0 external, ACLKX0 input
Setup time, AFSR0 input to ACLKR0 internal(3)
Setup time, AFSX0 input to ACLKX0 internal
Setup time, AFSR0 input to ACLKR0 external input(3)
Setup time, AFSX0 input to ACLKX0 external input
Setup time, AFSR0 input to ACLKR0 external output(3)
Setup time, AFSX0 input to ACLKX0 external output
Hold time, AFSR0 input after ACLKR0 internal(3)
Hold time, AFSX0 input after ACLKX0 internal
Hold time, AFSR0 input after ACLKR0 external input(3)
Hold time, AFSX0 input after ACLKX0 external input
Hold time, AFSR0 input after ACLKR0 external output(3)
Hold time, AFSX0 input after ACLKX0 external output
Setup time, AXR0[n] input to ACLKR0 internal(3)
Setup time, AXR0[n] input to ACLKX0 internal(4)
Setup time, AXR0[n] input to ACLKR0 external input(3)
Setup time, AXR0[n] input to ACLKX0 external input(4)
Setup time, AXR0[n] input to ACLKR0 external output(3)
Setup time, AXR0[n] input to ACLKX0 external output(4)
12.5
12.5
9.4
9.4
2.9
2.9
2.9
2.9
-1.2
-1.2
0.9
0.9
0.9
0.9
9.4
9.4
2.9
2.9
2.9
2.9
5
6
7
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
ns
ns
ns
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
94
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
NO.
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-44. McASP0 Timing Requirements(1)(2) (continued)
MIN
-1.3
-1.3
0.5
MAX UNIT
Hold time, AXR0[n] input after ACLKR0 internal(3)
Hold time, AXR0[n] input after ACLKX0 internal(4)
Hold time, AXR0[n] input after ACLKR0 external input(3)
Hold time, AXR0[n] input after ACLKX0 external input(4)
Hold time, AXR0[n] input after ACLKR0 external output(3)
Hold time, AXR0[n] input after ACLKX0 external output(4)
8
th(ACLKRX-AXR)
ns
0.5
0.5
0.5
Table 5-45. McASP0 Switching Characteristics(1)
NO.
PARAMETER
MIN
25
MAX UNIT
Cycle time, AHCLKR0 internal, AHCLKR0 output
Cycle time, AHCLKR0 external, AHCLKR0 output
Cycle time, AHCLKX0 internal, AHCLKX0 output
Cycle time, AHCLKX0 external, AHCLKX0 output
25
9
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
25
25
Pulse duration, AHCLKR0 internal, AHCLKR0 output
Pulse duration, AHCLKR0 external, AHCLKR0 output
Pulse duration, AHCLKX0 internal, AHCLKX0 output
Pulse duration, AHCLKX0 external, AHCLKX0 output
Cycle time, ACLKR0 internal, ACLKR0 output
Cycle time, ACLKR0 external, ACLKR0 output
Cycle time, ACLKX0 internal, ACLKX0 output
Cycle time, ACLKX0 external, ACLKX0 output
Pulse duration, ACLKR0 internal, ACLKR0 output
Pulse duration, ACLKR0 external, ACLKR0 output
Pulse duration, ACLKX0 internal, ACLKX0 output
Pulse duration, ACLKX0 external, ACLKX0 output
Delay time, ACLKR0 internal, AFSR output(7)
Delay time, ACLKX0 internal, AFSX output
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
ns
ns
ns
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
0
0
5.8
5.8
Delay time, ACLKR0 external input, AFSR output(7)
Delay time, ACLKX0 external input, AFSX output
Delay time, ACLKR0 external output, AFSR output(7)
Delay time, ACLKX0 external output, AFSX output
Delay time, ACLKX0 internal, AXR0[n] output
Delay time, ACLKX0 external input, AXR0[n] output
Delay time, ACLKX0 external output, AXR0[n] output
Disable time, ACLKX0 internal, AXR0[n] output
Disable time, ACLKX0 external input, AXR0[n] output
Disable time, ACLKX0 external output, AXR0[n] output
2.5
2.5
2.5
2.5
0
11.6
ns
13
td(ACLKRX-AFSRX)
11.6
11.6
11.6
5.8
14
15
td(ACLKX-AXRV)
2.5
2.5
0
11.6
11.6
5.8
ns
ns
tdis(ACLKX-AXRHZ)
3
11.6
11.6
3
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR0.
(3) AHX - Cycle time, AHCLKX0.
(4) P = SYSCLK2 period
(5) AR - ACLKR0 period.
(6) AX - ACLKX0 period.
(7) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
95
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 5-46 and Table 5-47 assume testing over recommended operating conditions (see Figure 5-29 and
Figure 5-30).
Table 5-46. McASP1 Timing Requirements(1)(2)
NO.
MIN
MAX UNIT
Cycle time, AHCLKR1 external, AHCLKR1 input
Cycle time, AHCLKX1 external, AHCLKX1 input
Pulse duration, AHCLKR1 external, AHCLKR1 input
Pulse duration, AHCLKX1 external, AHCLKX1 input
Cycle time, ACLKR1 external, ACLKR1 input
25
1
tc(AHCLKRX)
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
25
12.5
2
3
4
ns
ns
ns
12.5
greater of 2P or 25
Cycle time, ACLKX1 external, ACLKX1 input
greater of 2P or 25
Pulse duration, ACLKR1 external, ACLKR1 input
Pulse duration, ACLKX1 external, ACLKX1 input
Setup time, AFSR1 input to ACLKR1 internal(3)
Setup time, AFSX1 input to ACLKX1 internal
Setup time, AFSR1 input to ACLKR1 external input(3)
Setup time, AFSX1 input to ACLKX1 external input
Setup time, AFSR1 input to ACLKR1 external output(3)
Setup time, AFSX1 input to ACLKX1 external output
Hold time, AFSR1 input after ACLKR1 internal(3)
Hold time, AFSX1 input after ACLKX1 internal
Hold time, AFSR1 input after ACLKR1 external input(3)
Hold time, AFSX1 input after ACLKX1 external input
Hold time, AFSR1 input after ACLKR1 external output(3)
Hold time, AFSX1 input after ACLKX1 external output
Setup time, AXR1[n] input to ACLKR1 internal(3)
Setup time, AXR1[n] input to ACLKX1 internal(4)
Setup time, AXR1[n] input to ACLKR1 external input(3)
Setup time, AXR1[n] input to ACLKX1 external input(4)
Setup time, AXR1[n] input to ACLKR1 external output(3)
Setup time, AXR1[n] input to ACLKX1 external output(4)
Hold time, AXR1[n] input after ACLKR1 internal(3)
Hold time, AXR1[n] input after ACLKX1 internal(4)
Hold time, AXR1[n] input after ACLKR1 external input(3)
Hold time, AXR1[n] input after ACLKX1 external input(4)
Hold time, AXR1[n] input after ACLKR1 external output(3)
Hold time, AXR1[n] input after ACLKX1 external output(4)
12.5
12.5
10.4
10.4
2.6
5
6
7
8
tsu(AFSRX-ACLKRX)
th(ACLKRX-AFSRX)
tsu(AXR-ACLKRX)
th(ACLKRX-AXR)
ns
ns
ns
ns
2.6
2.6
2.6
-1.9
-1.9
0.7
0.7
0.7
0.7
10.4
10.4
2.6
2.6
2.6
2.6
-1.8
-1.8
0.5
0.5
0.5
0.5
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
96
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
NO.
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-47. McASP1 Switching Characteristics(1)
PARAMETER
MIN
MAX UNIT
Cycle time, AHCLKR1 internal, AHCLKR1 output
Cycle time, AHCLKR1 external, AHCLKR1 output
Cycle time, AHCLKX1 internal, AHCLKX1 output
Cycle time, AHCLKX1 external, AHCLKX1 output
Pulse duration, AHCLKR1 internal, AHCLKR1 output
Pulse duration, AHCLKR1 external, AHCLKR1 output
Pulse duration, AHCLKX1 internal, AHCLKX1 output
Pulse duration, AHCLKX1 external, AHCLKX1 output
Cycle time, ACLKR1 internal, ACLKR1 output
Cycle time, ACLKR1 external, ACLKR1 output
Cycle time, ACLKX1 internal, ACLKX1 output
Cycle time, ACLKX1 external, ACLKX1 output
Pulse duration, ACLKR1 internal, ACLKR1 output
Pulse duration, ACLKR1 external, ACLKR1 output
Pulse duration, ACLKX1 internal, ACLKX1 output
Pulse duration, ACLKX1 external, ACLKX1 output
Delay time, ACLKR1 internal, AFSR output(7)
Delay time, ACLKX1 internal, AFSX output
Delay time, ACLKR1 external input, AFSR output(7)
Delay time, ACLKX1 external input, AFSX output
Delay time, ACLKR1 external output, AFSR output(7)
Delay time, ACLKX1 external output, AFSX output
Delay time, ACLKX1 internal, AXR1[n] output
Delay time, ACLKX1 external input, AXR1[n] output
Delay time, ACLKX1 external output, AXR1[n] output
Disable time, ACLKX1 internal, AXR1[n] output
Disable time, ACLKX1 external input, AXR1[n] output
Disable time, ACLKX1 external output, AXR1[n] output
25
25
9
tc(AHCLKRX)
ns
25
25
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
10
11
12
tw(AHCLKRX)
tc(ACLKRX)
tw(ACLKRX)
ns
ns
ns
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
greater of 2P or 25(4)
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
0.5
0.5
3.4
3.4
3.4
3.4
0.5
3.4
3.4
0.5
3.9
3.9
6.7
6.7
13.8
ns
13
td(ACLKRX-AFSRX)
13.8
13.8
13.8
6.7
14
15
td(ACLKX-AXRV)
13.8
13.8
6.7
ns
ns
tdis(ACLKX-AXRHZ)
13.8
13.8
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
97
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 5-29. McASP Input Timings
98
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 5-30. McASP Output Timings
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
99
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.17 Serial Peripheral Interface Ports (SPI0)
Figure 5-31 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
SPIx_SIMO
SPIx_SOMI
Peripheral
16-Bit Shift Register
16-Bit Buffer
Configuration Bus
SPIx_ENA
SPIx_SCS
SPIx_CLK
State
Machine
GPIO
Control
(all pins)
Interrupt and
Clock
Control
DMA Requests
Figure 5-31. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The C6743 will only shift data and drive the SPIx_SOMI pin
when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output and can be driven in either a push-pull or open-drain
manner. The SPIx_ENA output provides the status of the internal transmit buffer (SPIDAT0/1 registers). In
four-pin mode with the enable option, SPIx_ENA is asserted only when the transmit buffer is full, indicating
that the slave is ready to begin another transfer. In five-pin mode, the SPIx_ENA is additionally qualified
by SPIx_SCS being asserted. This allows a single handshake line to be shared by multiple slaves on the
same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
Although the SPI module supports two interrupt outputs, SPIx_INT1 is the only interrupt connected on this
device. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9)
for more details.
100
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Optional − Slave Chip Select
Optional Enable (Ready)
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
MASTER SPI
SLAVE SPI
Figure 5-32. Illustration of SPI Master-to-SPI Slave Connection
5.17.1 SPI Peripheral Registers Description(s)
Table 5-48 is a list of the SPI registers.
Table 5-48. SPIx Configuration Registers
SPI0
BYTE ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
0x01C4 1000
0x01C4 1004
0x01C4 1008
0x01C4 100C
0x01C4 1010
0x01C4 1014
0x01C4 1018
0x01C4 101C
0x01C4 1020
0x01C4 1024
0x01C4 1028
0x01C4 102C
0x01C4 1030
0x01C4 1034
0x01C4 1038
0x01C4 103C
0x01C4 1040
0x01C4 1044
SPIGCR0
SPIGCR1
SPIINT0
SPILVL
Global Control Register 0
Global Control Register 1
Interrupt Register
Interrupt Level Register
SPIFLG
SPIPC0
SPIPC1
SPIPC2
SPIPC3
SPIPC4
SPIPC5
Reserved
Reserved
Reserved
SPIDAT0
SPIDAT1
SPIBUF
SPIEMU
Flag Register
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Pin Control Register 3 (Pin Data Out)
Pin Control Register 4 (Pin Data Set)
Pin Control Register 5 (Pin Data Clear)
Reserved - Do not write to this register
Reserved - Do not write to this register
Reserved - Do not write to this register
Shift Register 0 (without format select)
Shift Register 1 (with format select)
Buffer Register
Emulation Register
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
101
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-48. SPIx Configuration Registers (continued)
SPI0
BYTE ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
0x01C4 1048
0x01C4 104C
0x01C4 1050
0x01C4 1054
0x01C4 1058
0x01C4 105C
0x01C4 1060
0x01C4 1064
SPIDELAY
SPIDEF
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
Reserved
INTVEC1
Format Register 1
Format Register 2
Format Register 3
Reserved - Do not write to this register
Interrupt Vector for SPI INT1
102
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.17.2 SPI Electrical Data/Timing
5.17.2.1 Serial Peripheral Interface (SPI) Timing
Table 5-49 assumes testing over recommended operating conditions (see Figure 5-33 through Figure 5-
36).
Table 5-49. General Timing Requirements for SPI0 Master Modes(1)
NO.
1
MIN
greater of 3P or 20
0.5tc(SPC)M - 1
MAX UNIT
tc(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
256P
ns
ns
ns
2
tw(SPCH)M
tw(SPCL)M
3
0.5tc(SPC)M - 1
Polarity = 0, Phase = 0,
to SPI0_CLK rising
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
-0.5tc(SPC)M + 5
Delay, initial data bit valid on
SPI0_SIMO after initial edge
on SPI0_CLK(2)
4
5
6
7
8
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
ns
ns
ns
ns
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
5
Polarity = 1, Phase = 1,
to SPI0_CLK falling
-0.5tc(SPC)M + 5
Polarity = 0, Phase = 0,
from SPI0_CLK rising
5
5
5
5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay, subsequent bits valid
on SPI0_SIMO after transmit
edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)M -3
Output hold time, SPI0_SIMO
valid after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)M -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time, SPI0_SOMI
valid before
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time, SPI0_SOMI
valid after
receive edge of SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
103
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-50. General Timing Requirements for SPI0 Slave Modes(1)
NO.
9
MIN
MAX UNIT
tc(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
greater of 3P or 40
ns
ns
ns
10
11
tw(SPCH)S
tw(SPCL)S
18
18
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P
2P
2P
2P
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Setup time, transmit data written to
SPI before initial clock edge from
master.(2) (3)
12
13
14
15
16
tsu(SOMI_SPC)S
td(SPC_SOMI)S
toh(SPC_SOMI)S
tsu(SIMO_SPC)S
tih(SPC_SIMO)S
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
18.5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
18.5
ns
Delay, subsequent bits valid on
SPI0_SOMI after transmit edge of
SPI0_CLK
Polarity = 1, Phase = 0,
from SPI0_CLK falling
18.5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
18.5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 1,
from SPI0_CLK rising
0.5tc(SPC)S -3
Output hold time, SPI0_SOMI valid
after
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)S -3
Polarity = 1, Phase = 1,
from SPI0_CLK falling
0.5tc(SPC)S -3
Polarity = 0, Phase = 0,
to SPI0_CLK falling
0
0
0
0
5
5
5
5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Input Setup Time, SPI0_SIMO valid
before
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Input Hold Time, SPI0_SIMO valid
after
receive edge of SPI0_CLK
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
104
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
NO.
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-51. Additional(1) SPI0 Master Timings, 4-Pin Enable Option(2) (3)
MIN
MAX UNIT
3P + 3.6
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 3P + 3.6
3P + 3.6
Delay from slave assertion of
SPI0_ENA active to first SPI0_CLK
from master.(4)
17
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3.6
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Max delay for slave to deassert
SPI0_ENA after final SPI0_CLK edge
to ensure master does not begin the
next transfer.(5)
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P + 5
P + 5
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-49).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 5-52. Additional(1) SPI0 Master Timings, 4-Pin Chip Select Option(2) (3)
NO.
PARAMETER
MIN
MAX UNIT
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P - 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
0.5tc(SPC)M + 2P - 5
2P - 5
Delay from SPI0_SCS active to first
SPI0_CLK(4) (5)
19
td(SCS_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P - 5
0.5tc(SPC)M +P - 3
P - 3
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final SPI0_CLK edge to
master deasserting SPI0_SCS
20
td(SPC_SCS)M
ns
(6) (7)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
0.5tc(SPC)M + P -3
P - 3
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-49).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
105
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
MAX UNIT
Table 5-53. Additional(1) SPI0 Master Timings, 5-Pin Option(2) (3)
NO.
MIN
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M+ P + 5
Max delay for slave to
deassert SPI0_ENA after final
SPI0_CLK edge to ensure
master does not begin the
next transfer.(4)
Polarity = 0, Phase = 1,
from SPI0_CLK falling
P + 5
0.5tc(SPC)M+ P + 5
P + 5
18
td(SPC_ENA)M
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M+ P - 3
P - 3
0.5tc(SPC)M+ P - 3
P - 3
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final SPI0_CLK
edge to
20
21
22
td(SPC_SCS)M
td(SCSL_ENAL)M
td(SCS_SPC)M
ns
ns
ns
master deasserting
Polarity = 1, Phase = 0,
from SPI0_CLK rising
(5) (6)
SPI0_SCS
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid after
master asserts SPI0_SCS to delay the
master from beginning the next transfer,
C2TDELAY + P
Polarity = 0, Phase = 0,
to SPI0_CLK rising
2P - 5
0.5tc(SPC)M + 2P - 5
2P - 5
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Delay from SPI0_SCS active
to first SPI0_CLK(7) (8) (9)
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 2P - 5
Polarity = 0, Phase = 0,
to SPI0_CLK rising
3P + 3.6
0.5tc(SPC)M + 3P + 3.6
3P + 3.6
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Delay from assertion of
SPI0_ENA low to first
SPI0_CLK edge.(10)
23
td(ENA_SPC)M
ns
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
0.5tc(SPC)M + 3P + 3.6
(1) These parameters are in addition to the general timings for SPI master modes (Table 5-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
106
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
NO.
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-54. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2) (3)
MIN
1.5 P - 3
– 0.5tc(SPC)M + 1.5 P - 3 – 0.5tc(SPC)M + 2.5 P + 18.5
1.5 P - 3 2.5 P + 18.5
– 0.5tc(SPC)M + 1.5 P - 3 – 0.5tc(SPC)M + 2.5 P + 18.5
MAX UNIT
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 18.5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Delay from final
SPI0_CLK edge to
slave deasserting
SPI0_ENA.
24
td(SPC_ENAH)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 5-55. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2) (3)
NO.
MIN
MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
2P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + P + 5
P + 5
Polarity = 0, Phase = 1,
Required delay from final
from SPI0_CLK falling
26
td(SPC_SCSH)S
SPI0_CLK edge before
ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted.
0.5tc(SPC)M + P + 5
P + 5
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
P + 18.5
P + 18.5
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
107
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-56. Additional(1) SPI0 Slave Timings, 5-Pin Option(2) (3)
NO.
PARAMETER
MIN
MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
SPI0_CLK edge at slave.
25
td(SCSL_SPC)S
2P
ns
Polarity = 0, Phase = 0,
from SPI0_CLK falling
0.5tc(SPC)M + 5
Polarity = 0, Phase = 1,
from SPI0_CLK falling
5
0.5tc(SPC)M + 5
5
Required delay from final SPI0_CLK
edge before SPI0_SCS is
deasserted.
26
td(SPC_SCSH)S
ns
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
SPI0_SOMI valid
27
28
29
tena(SCSL_SOMI)S
tdis(SCSH_SOMI)S
tena(SCSL_ENA)S
P + 18.5
ns
ns
ns
Delay from master deasserting SPI0_SCS to slave 3-stating
SPI0_SOMI
P + 18.5
18.5
Delay from master deasserting SPI0_SCS to slave driving
SPI0_ENA valid
Polarity = 0, Phase = 0,
from SPI0_CLK falling
2.5 P + 18.5
2.5 P + 18.5
2.5 P + 18.5
2.5 P + 18.5
Polarity = 0, Phase = 1,
Delay from final clock receive edge
from SPI0_CLK rising
30
tdis(SPC_ENA)S
on SPI0_CLK to slave 3-stating or
ns
driving high SPI0_ENA.(4)
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-50).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-
stated. If tri-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
108
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
1
MASTER MODE
POLARITY = 0 PHASE = 0
2
3
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
MASTER MODE
POLARITY = 0 PHASE = 1
4
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
6
5
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
MASTER MODE
POLARITY = 1 PHASE = 0
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
8
MI(0)
MI(n−1)
MI(n)
MASTER MODE
POLARITY = 1 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 5-33. SPI Timings—Master Mode
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
109
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
9
SLAVE MODE
POLARITY = 0 PHASE = 0
12
10
15
11
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
16
SI(0)
SI(1)
13
SI(n−1)
SI(n)
14
SO(0)
SO(1)
SO(n−1)
SO(n)
12
SLAVE MODE
POLARITY = 0 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
SI(0)
16
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
SLAVE MODE
12
POLARITY = 1 PHASE = 0
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
13
SO(1)
SI(n−1)
14
SO(n−1)
SI(n)
SO(0)
SO(n)
SLAVE MODE
12
POLARITY = 1 PHASE = 1
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
15
16
SI(0)
SI(1)
SI(n−1)
SI(n)
13
SO(1)
14
SO(0)
SO(n−1)
SO(n)
Figure 5-34. SPI Timings—Slave Mode
110
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
MASTER MODE 4 PIN WITH ENABLE
17
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
MO(0)
MI(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MASTER MODE 4 PIN WITH CHIP SELECT
19
20
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_SCS
MO(0)
MO(n)
MI(n)
MO(n−1)
MI(n−1)
MO(1)
MI(1)
MI(0)
MASTER MODE 5 PIN
23
22
20
MO(1)
18
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0)
MO(n−1)
MO(n)
MI(0)
MI(1)
MI(n−1)
MI(n)
21
(A)
(A)
SPIx_ENA
SPIx_SCS
DESEL
DESEL
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 5-35. SPI Timings—Master Mode (4-Pin and 5-Pin)
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
111
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
SLAVE MODE 4 PIN WITH ENABLE
24
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SO(0)
SI(0)
SO(1)
SO(n−1) SO(n)
SI(n−1) SI(n)
SI(1)
SLAVE MODE 4 PIN WITH CHIP SELECT
25
26
SPIx_CLK
27
28
SO(n−1)
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SO(0)
SO(1)
SO(n)
SI(0)
SI(1)
SI(n−1)
SI(n)
SLAVE MODE 5 PIN
25
26
30
SPIx_CLK
27
29
28
SO(1)
SPIx_SOMI
SPIx_SIMO
SO(0)
SI(0)
SO(n−1)
SO(n)
SI(1)
SI(n−1) SI(n)
SPIx_ENA
(A)
(A)
DESEL
DESEL
SPIx_SCS
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
Figure 5-36. SPI Timings—Slave Mode (4-Pin and 5-Pin)
112
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.18 Enhanced Capture (eCAP) Peripheral
The device contains up to three enhanced capture (eCAP) modules. Figure 5-37 shows a functional block
diagram of a module. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference
Guide (SPRUFK9) for more details.
Uses for ECAP include:
•
•
•
•
Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor triggers
Period and duty cycle measurements of Pulse train signals
Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
The ECAP module described in this specification includes the following features:
•
•
•
•
•
•
•
•
•
32 bit time base
4 event time-stamp registers (each 32 bits)
Edge polarity selection for up to 4 sequenced time-stamp capture events
Interrupt on either of the 4 events
Single shot capture of up to 4 event time-stamps
Continuous mode capture of time-stamps in a 4 deep circular buffer
Absolute time-stamp capture
Difference mode time-stamp capture
All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
113
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
CTRPHS
(phase register−32 bit)
SYNCIn
APWM mode
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Pre-scale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
CEVT[1:4]
4
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to Interrupt
Controller
CTR_OVF
CTR=PRD
CTR=CMP
Figure 5-37. eCAP Functional Block Diagram
114
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-57 is the list of the ECAP registers.
Table 5-57. ECAPx Configuration Registers
ECAP0
ECAP1
BYTE ADDRESS
ECAP2
BYTE ADDRESS
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
0x01F0 6000
0x01F0 6004
0x01F0 6008
0x01F0 600C
0x01F0 6010
0x01F0 6014
0x01F0 6028
0x01F0 602A
0x01F0 602C
0x01F0 602E
0x01F0 6030
0x01F0 6032
0x01F0 605C
0x01F0 7000
0x01F0 7004
0x01F0 7008
0x01F0 700C
0x01F0 7010
0x01F0 7014
0x01F0 7028
0x01F0 702A
0x01F0 702C
0x01F0 702E
0x01F0 7030
0x01F0 7032
0x01F0 705C
0x01F0 8000
0x01F0 8004
0x01F0 8008
0x01F0 800C
0x01F0 8010
0x01F0 8014
0x01F0 8028
0x01F0 802A
0x01F0 802C
0x01F0 802E
0x01F0 8030
0x01F0 8032
0x01F0 805C
TSCTR
CTRPHS
CAP1
Time-Stamp Counter
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
REVID
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Revision ID
Table 5-58 shows the eCAP timing requirement and Table 5-59 shows the eCAP switching characteristics.
Table 5-58. Enhanced Capture (eCAP) Timing Requirement
TEST CONDITIONS
Asynchronous
Synchronous
MIN
2tc(SCO)
2tc(SCO)
MAX UNIT
cycles
tw(CAP)
Capture input pulse width
cycles
Table 5-59. eCAP Switching Characteristics
PARAMETER
Pulse duration, APWMx output high/low
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
20
ns
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
115
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.19 Enhanced Quadrature Encoder (eQEP) Peripheral
The device contains up to two enhanced quadrature encoder (eQEP) modules. See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
System
control registers
To CPU
EQEPxENCLK
SYSCLK2
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxINT
16
QCLK
QDIR
QI
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
Position counter/
control unit
(PCCU)
Quadrature
decoder
(QDU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) peripheral
Figure 5-38. eQEP Functional Block Diagram
Table 5-60 is the list of the EQEP registers.
Table 5-61 shows the eQEP timing requirement and Table 5-62 shows the eQEP switching
characteristics.
116
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-60. EQEP Registers
EQEP0
EQEP1
BYTE ADDRESS
0x01F0 9000
0x01F0 9004
0x01F0 9008
0x01F0 900C
0x01F0 9010
0x01F0 9014
0x01F0 9018
0x01F0 901C
0x01F0 9020
0x01F0 9024
0x01F0 9026
0x01F0 9028
0x01F0 902A
0x01F0 902C
0x01F0 902E
0x01F0 9030
0x01F0 9032
0x01F0 9034
0x01F0 9036
0x01F0 9038
0x01F0 903A
0x01F0 903C
0x01F0 903E
0x01F0 9040
0x01F0 905C
BYTE ADDRESS
REGISTER NAME
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
REGISTER DESCRIPTION
eQEP Position Counter
0x01F0 A000
0x01F0 A004
0x01F0 A008
0x01F0 A00C
0x01F0 A010
0x01F0 A014
0x01F0 A018
0x01F0 A01C
0x01F0 A020
0x01F0 A024
0x01F0 A026
0x01F0 A028
0x01F0 A02A
0x01F0 A02C
0x01F0 A02E
0x01F0 A030
0x01F0 A032
0x01F0 A034
0x01F0 A036
0x01F0 A038
0x01F0 A03A
0x01F0 A03C
0x01F0 A03E
0x01F0 A040
0x01F0 A05C
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
QCAPCTL
QPOSCTL
QEINT
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
eQEP Revision ID
QCTMRLAT
QCPRDLAT
REVID
Table 5-61. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
TEST CONDITIONS
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
Asynchronous/synchronous
MIN
2tc(SCO)
2tc(SCO)
2tc(SCO)
2tc(SCO)
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Table 5-62. eQEP Switching Characteristics
PARAMETER
MIN
MAX
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
Delay time, QEP input edge to position compare sync output
4tc(SCO)
6tc(SCO)
td(PCS-OUT)QEP
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
117
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.20 Enhanced Pulse Width Modulator (eHRPWM) Modules
The device contains up to three enhanced PWM Modules (eHRPWM). Figure 5-39 shows a block diagram
of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the eHRPWM. See the
TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more
details.
EPWMSYNCI
EPWM0SYNCI
EPWM0INT
EPWM0A
EPWM0B
ePWM0 module
TZ
EPWM0SYNCO
EPWM1SYNCI
EPWM1INT
EPWM1A
EPWM1B
TZ
GPIO
MUX
ePWM1 module
EPWM1SYNCO
EPWM2SYNCI
ePWM2 module
EPWM2SYNCO
EPWM2INT
EPWM2A
EPWM2B
Interrupt
Controllers
TZ
To eCAP0
module
(sync in)
EPWMSYNCO
Peripheral Bus
Figure 5-39. Multiple PWM Modules in a C6743 System
118
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Time−base (TB)
Sync
in/out
select
Mux
CTR=ZERO
CTR=CMPB
Disabled
TBPRD shadow (16)
TBPRD active (16)
EPWMSYNCO
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[CNTLDE]
EPWMSYNCI
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCNT
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
Phase
control
Event
trigger
and
interrupt
(ET)
TBPHS active (24)
EPWMxINT
CTR = CMPA
CTR = CMPB
CTR_Dir
Counter compare (CC)
Action
qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
16
8
HiRes PWM (HRPWM)
CMPA active (24)
EPWMA
EPWMB
EPWMxA
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxB
EPWMxTZINT
TZ
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 5-40. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
Table 5-63. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM1
eHRPWM2
eHRPWM3
REGISTER
SIZE
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS NAME
(×16) SHADOW REGISTER DESCRIPTION
Time-Base Submodule Registers
0x01F0 4000 TBCTL
TBSTS
0x01F0 0000
0x01F0 0002
0x01F0 0004
0x01F0 2000
0x01F0 2002
0x01F0 2004
1
No
No
No
Time-Base Control Register
Time-Base Status Register
0x01F0 4002
0x01F0 4004
1
TBPHSHR
1
Extension for HRPWM Phase Register
(1)
0x01F0 0006
0x01F0 0008
0x01F0 000A
0x01F0 2006
0x01F0 2008
0x01F0 200A
0x01F0 4006
0x01F0 4008
0x01F0 400A
TBPHS
TBCNT
TBPRD
1
1
1
No
No
Time-Base Phase Register
Time-Base Counter Register
Time-Base Period Register
Yes
Counter-Compare Submodule Registers
0x01F0 000E
0x01F0 0010
0x01F0 200E
0x01F0 2010
0x01F0 400E
0x01F0 4010
CMPCTL
CMPAHR
1
1
No
No
Counter-Compare Control Register
Extension for HRPWM Counter-
Compare A Register
(1)
0x01F0 0012
0x01F0 0014
0x01F0 2012
0x01F0 2014
0x01F0 4012
0x01F0 4014
CMPA
CMPB
1
1
Yes
Yes
Counter-Compare A Register
Counter-Compare B Register
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
119
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-63. eHRPWM Module Control and Status Registers Grouped by Submodule (continued)
eHRPWM1
eHRPWM2
eHRPWM3
REGISTER
SIZE
BYTE ADDRESS
BYTE ADDRESS
BYTE ADDRESS NAME
(×16) SHADOW REGISTER DESCRIPTION
Action-Qualifier Submodule Registers
0x01F0 0016
0x01F0 0018
0x01F0 2016
0x01F0 2018
0x01F0 4016
AQCTLA
1
No
No
Action-Qualifier Control Register for
Output A (eHRPWMxA)
0x01F0 4018
AQCTLB
1
Action-Qualifier Control Register for
Output B (eHRPWMxB)
0x01F0 001A
0x01F0 001C
0x01F0 201A
0x01F0 201C
0x01F0 401A
0x01F0 401C
AQSFRC
1
1
No
Action-Qualifier Software Force Register
AQCSFRC
Yes
Action-Qualifier Continuous S/W Force
Register Set
Dead-Band Generator Submodule Registers
0x01F0 001E
0x01F0 0020
0x01F0 201E
0x01F0 2020
0x01F0 401E
0x01F0 4020
DBCTL
DBRED
1
1
No
No
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge
Delay Count Register
0x01F0 0022
0x01F0 003C
0x01F0 2022
0x01F0 203C
0x01F0 4022
DBFED
1
No
No
Dead-Band Generator Falling Edge
Delay Count Register
PWM-Chopper Submodule Registers
0x01F0 403C PCCTL
Trip-Zone Submodule Registers
1
PWM-Chopper Control Register
0x01F0 0024
0x01F0 0028
0x01F0 002A
0x01F0 002C
0x01F0 002E
0x01F0 0030
0x01F0 2024
0x01F0 2028
0x01F0 202A
0x01F0 202C
0x01F0 202E
0x01F0 2030
0x01F0 4024
0x01F0 4028
0x01F0 402A
0x01F0 402C
0x01F0 402E
0x01F0 4030
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
1
1
1
1
1
1
No
No
No
No
No
No
Trip-Zone Select Register
Trip-Zone Control Register
Trip-Zone Enable Interrupt Register
Trip-Zone Flag Register
Trip-Zone Clear Register
Trip-Zone Force Register
Event-Trigger Submodule Registers
0x01F0 0032
0x01F0 0034
0x01F0 0036
0x01F0 0038
0x01F0 003A
0x01F0 2032
0x01F0 2034
0x01F0 2036
0x01F0 2038
0x01F0 203A
0x01F0 4032
0x01F0 4034
0x01F0 4036
0x01F0 4038
0x01F0 403A
ETSEL
ETPS
1
1
1
1
1
No
No
No
No
No
Event-Trigger Selection Register
Event-Trigger Pre-Scale Register
Event-Trigger Flag Register
Event-Trigger Clear Register
Event-Trigger Force Register
ETFLG
ETCLR
ETFRC
High-Resolution PWM (HRPWM) Submodule Registers
0x01F0 5040 HRCNFG No
(2)
0x01F0 1040
0x01F0 3040
1
HRPWM Configuration Register
(2) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
120
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 5-64 shows the PWM timing requirements and
Table 5-65, switching characteristics.
Table 5-64. eHRPWM Timing Requirements
TEST
MIN
MAX
UNIT
CONDITIONS
tw(SYCIN)
Sync input pulse width
Asynchronous
Synchronous
2tc(SCO)
2tc(SCO)
cycles
cycles
Table 5-65. eHRPWM Switching Characteristics
PARAMETER
TEST
MIN
MAX
UNIT
CONDITIONS
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
20
ns
cycles
ns
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load; no
additional
programmable
delay
25
20
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
no additional
programmable
delay
ns
5.20.2 Trip-Zone Input Timing
t
w(TZ)
TZ
t
d(TZ-PWM)HZ
(A)
PWM
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 5-41. PWM Hi-Z Characteristics
Table 5-66. Trip-Zone input Timing Requirements
TEST CONDITIONS
Asynchronous
MIN
1tc(SCO)
2tc(SCO)
MAX UNIT
cycles
tw(TZ)
Pulse duration, TZx input low
Synchronous
cycles
Table 5-67 shows the high-resolution PWM switching characteristics.
Table 5-67. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER
MIN
TYP
MAX UNIT
Micro Edge Positioning (MEP) step size(1)
200
ps
(1) MEP step size will increase with low voltage and high temperature, and decrease with high voltage and cold temperature.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
121
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.21 Timers
The timers support the following features:
•
•
•
•
•
•
Configurable as single 64-bit timer or two 32-bit timers
Period timeouts generate interrupts, DMA events or external pin events
8 32-bit compare registers
Compare matches generate interrupt events
Capture capability
64-bit Watchdog capability (Timer64P1 only)
Table 5-68 lists the timer registers. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview
Reference Guide (SPRUFK9) for more details.
Table 5-68. Timer Registers
TIMER64P 0
0x01C2 0000
0x01C2 0004
0x01C2 0008
0x01C2 000C
0x01C2 0010
0x01C2 0014
0x01C2 0018
0x01C2 001C
0x01C2 0020
0x01C2 0024
0x01C2 0028
0x01C2 0034
0x01C2 0038
0x01C2 003C
0x01C2 0040
0x01C2 0044
0x01C2 0060
0x01C2 0064
0x01C2 0068
0x01C2 006C
0x01C2 0070
0x01C2 0074
0x01C2 0078
0x01C2 007C
TIMER64P 1
0x01C2 1000
0x01C2 1004
0x01C2 1008
0x01C2 100C
0x01C2 1010
0x01C2 1014
0x01C2 1018
0x01C2 101C
0x01C2 1020
0x01C2 1024
0x01C2 1028
0x01C2 1034
0x01C2 1038
0x01C2 103C
0x01C2 1040
0x01C2 1044
0x01C2 1060
0x01C2 1064
0x01C2 1068
0x01C2 106C
0x01C2 1070
0x01C2 1074
0x01C2 1078
0x01C2 107C
REGISTER NAME
REV
REGISTER DESCRIPTION
Revision Register
EMUMGT
GPINTGPEN
GPDATGPDIR
TIM12
Emulation Management Register
GPIO Interrupt and GPIO Enable Register
GPIO Data and GPIO Direction Register
Timer Counter Register 12
Timer Counter Register 34
Timer Period Register 12
Timer Period Register 34
Timer Control Register
TIM34
PRD12
PRD34
TCR
TGCR
Timer Global Control Register
Watchdog Timer Control Register
Timer Reload Register 12
Timer Reload Register 34
Timer Capture Register 12
Timer Capture Register 34
Timer Interrupt Control and Status Register
Compare Register 0
WDTCR
REL12
REL34
CAP12
CAP34
INTCTLSTAT
CMP0
CMP1
Compare Register 1
CMP2
Compare Register 2
CMP3
Compare Register 3
CMP4
Compare Register 4
CMP5
Compare Register 5
CMP6
Compare Register 6
CMP7
Compare Register 7
122
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.21.1 Timer Electrical Data/Timing
Table 5-69. Timing Requirements for Timer Input(1)(2) (see Figure 5-42)
NO.
1
MIN
4P
MAX UNIT
tc(TM64Px_IN12) Cycle time, TM64Px_IN12
tw(TINPH) Pulse duration, TM64Px_IN12 high
tw(TINPL) Pulse duration, TM64Px_IN12 low
ns
2
0.45C
0.45C
0.55C
0.55C
ns
ns
3
0.25P or
10(3)
4
tt(TM64Px_IN12) Transition time, TM64Px_IN12
ns
(1) P = OSCIN cycle time in ns.
(2) C = TM64P0_IN12 cycle time in ns.
(3) Whichever is smaller. P = The period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
1
2
3
4
4
TM64P0_IN12
Figure 5-42. Timer Timing
Table 5-70. Switching Characteristics Over Recommended Operating Conditions for Timer Output(1)
NO.
5
PARAMETER
Pulse duration, TM64P0_OUT12 high
Pulse duration, TM64P0_OUT12 low
MIN
4P
MAX UNIT
tw(TOUTH)
tw(TOUTL)
ns
ns
6
4P
(1) P = OSCIN cycle time in ns.
5
6
TM64P0_OUT12
Figure 5-43. Timer Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
123
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
5.22.1 I2C Device-Specific Information
Having two I2C modules on the device simplifies system architecture, since one module may be used by
the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate
with other controllers in a system or to implement a user interface. Figure 5-44 is the block diagram of the
I2C Module. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide
(SPRUFK9) for more details.
Each I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
General-Purpose I/O Capability if not used as I2C
Clock Prescaler
I2CPSCx
Control
I2CCOARx
Prescaler
Register
Own Address
Register
Slave Address
Register
I2CSARx
Bit Clock Generator
I2CCLKHx
Noise
Filter
I2Cx_SCL
Clock Divide
High Register
I2CCMDRx
I2CEMDRx
I2CCNTx
I2CPID1
Mode Register
Extended Mode
Register
Clock Divide
Low Register
I2CCLKLx
Data Count
Register
Peripheral
Configuration
Bus
Transmit
I2CXSRx
Peripheral ID
Register 1
Transmit Shift
Register
Peripheral ID
Register 2
I2CPID2
I2CDXRx
Transmit Buffer
Noise
Filter
I2Cx_SDA
Interrupt/DMA
Interrupt Enable
Register
Receive
I2CIERx
Interrupt DMA
Requests
Receive Buffer
I2CDRRx
Interrupt Status
Register
I2CSTRx
I2CSRCx
Receive Shift
Register
Interrupt Source
Register
I2CRSRx
Control
Pin Function
Register
Pin Data Out
Register
I2CPDOUT
I2CPFUNC
Pin Direction
Register
Pin Data Set
Register
I2CPDIR
I2CPDIN
I2CPDSET
I2CPDCLR
Pin Data In
Register
Pin Data Clear
Register
Figure 5-44. I2C Module Block Diagram
124
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.22.2 I2C Peripheral Registers Description(s)
Table 5-71 is the list of the I2C registers.
Table 5-71. Inter-Integrated Circuit (I2C) Registers
I2C0
I2C1
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
ICOAR
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
5.22.3 I2C Electrical Data/Timing
5.22.3.1 Inter-Integrated Circuit (I2C) Timing
Table 5-72 and Table 5-73 assume testing over recommended operating conditions (see Figure 5-45 and
Figure 5-46).
Table 5-72. I2C Input Timing Requirements
NO.
MIN
10
2.5
4.7
0.6
4
MAX UNIT
Standard Mode
Fast Mode
1
tc(SCL)
Cycle time, I2Cx_SCL
μs
Standard Mode
Fast Mode
2
3
4
5
6
7
tsu(SCLH-SDAL)
th(SCLL-SDAL)
tw(SCLL)
Setup time, I2Cx_SCL high before I2Cx_SDA low
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
μs
μs
μs
μs
ns
Standard Mode
Fast Mode
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
tsu(SDA-SCLH)
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Standard Mode
Fast Mode
th(SDA-SCLL)
μs
0
0.9
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
125
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-72. I2C Input Timing Requirements (continued)
NO.
MIN
4.7
MAX UNIT
Standard Mode
Fast Mode
8
tw(SDAH)
Pulse duration, I2Cx_SDA high
Rise time, I2Cx_SDA
μs
1.3
Standard Mode
Fast Mode
1000
ns
9
tr(SDA)
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
300
Standard Mode
Fast Mode
1000
ns
10 tr(SCL)
11 tf(SDA)
12 tf(SCL)
13 tsu(SCLH-SDAH)
14 tw(SP)
Rise time, I2Cx_SCL
300
Standard Mode
Fast Mode
300
ns
Fall time, I2Cx_SDA
300
Standard Mode
Fast Mode
300
ns
Fall time, I2Cx_SCL
20 + 0.1Cb
300
Standard Mode
Fast Mode
4
0.6
N/A
0
Setup time, I2Cx_SCL high before I2Cx_SDA high
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
μs
Standard Mode
Fast Mode
ns
50
Standard Mode
Fast Mode
400
pF
15 Cb
400
Table 5-73. I2C Switching Characteristics(1)
NO.
PARAMETER
MIN
10
2.5
4.7
0.6
4
MAX UNIT
Standard Mode
16 tc(SCL)
Cycle time, I2Cx_SCL
μs
Fast Mode
Standard Mode
Fast Mode
17 tsu(SCLH-SDAL)
18 th(SDAL-SCLL)
19 tw(SCLL)
Setup time, I2Cx_SCL high before I2Cx_SDA low
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
μs
μs
μs
μs
ns
Standard Mode
Fast Mode
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
20 tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
21 tsu(SDAV-SCLH)
22 th(SCLL-SDAV)
23 tw(SDAH)
Setup time, I2Cx_SDA valid before I2Cx_SCL high
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Standard Mode
Fast Mode
μs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
4
μs
μs
Standard Mode
Fast Mode
28 tsu(SCLH-SDAH)
Setup time, I2Cx_SCL high before I2Cx_SDA high
0.6
(1) I2C must be configured correctly to meet the timings in Table 5-73.
126
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
I2Cx_SDA
I2Cx_SCL
SPRS565C –APRIL 2009–REVISED MARCH 2013
11
9
6
8
14
13
4
5
10
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 5-45. I2C Receive Timings
26
24
I2Cx_SDA
I2Cx_SCL
21
23
19
28
20
25
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 5-46. I2C Transmit Timings
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
127
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.23 Universal Asynchronous Receiver/Transmitter (UART)
The device has 2 UART peripherals. Each UART has the following features:
•
•
•
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
Autoflow control signals (CTS, RTS) on UART0 only.
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Programmable Baud Rate up to 3MBaud
Programmable Oversampling Options of x13 and x16
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
The UART registers are listed in Section 5.23.1. See the TMS320C674x/OMAP-L1x Processor Peripherals
Overview Reference Guide (SPRUFK9) for more details.
5.23.1 UART Peripheral Registers Description(s)
Table 5-74 is the list of UART registers.
Table 5-74. UART Registers
UART0
UART2
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
0x01C4 2000
0x01C4 2000
0x01C4 2004
0x01C4 2008
0x01C4 2008
0x01C4 200C
0x01C4 2010
0x01C4 2014
0x01C4 2020
0x01C4 2024
0x01C4 2028
0x01C4 2030
0x01C4 2034
0x01D0 D000
0x01D0 D000
0x01D0 D004
0x01D0 D008
0x01D0 D008
0x01D0 D00C
0x01D0 D010
0x01D0 D014
0x01D0 D020
0x01D0 D024
0x01D0 D028
0x01D0 D030
0x01D0 D034
RBR
Receiver Buffer Register (read only)
Transmitter Holding Register (write only)
Interrupt Enable Register
THR
IER
IIR
Interrupt Identification Register (read only)
FIFO Control Register (write only)
Line Control Register
FCR
LCR
MCR
Modem Control Register
LSR
Line Status Register
DLL
Divisor LSB Latch
DLH
Divisor MSB Latch
REVID1
Revision Identification Register 1
Power and Emulation Management Register
Mode Definition Register
PWREMU_MGMT
MDR
128
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.23.2 UART Electrical Data/Timing
Table 5-75. Timing Requirements for UARTx Receive(1) (see Figure 5-47)
NO.
4
MIN
0.96U
0.96U
MAX
1.05U MBaud
1.05U ns
UNIT
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (RXDn)
Pulse duration, receive start bit
5
(1) U = UART baud time = 1/programmed baud rate.
Table 5-76. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 5-47)
NO.
1
PARAMETER
MIN
MAX
D/E(3)(4) MBaud
UNIT
f(baud)
Maximum programmable baud rate(2)
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
2
tw(UTXDB)
tw(UTXSB)
U - 2
U - 2
U + 2
U + 2
ns
ns
3
(1) U = UART baud time = 1/programmed baud rate.
(2) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF loading, system
frequency, etc.
(3) D = UART input clock in MHz. The UART(s) input clock source is PLL0_SYSCLK2.
(4) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
3
2
Start
Bit
UART_TXDn
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 5-47. UART Transmit/Receive Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
129
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.24 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview
Reference Guide (SPRUFK9) for more details.
The PSC includes the following features:
•
Provides a software interface to:
–
–
–
Control module clock enable/disable
Control module reset
Control CPU local reset
•
Supports IcePick emulation features: power, clock and reset
5.24.1 PSC Peripheral Registers Description(s)
Table 5-77. Power and Sleep Controller (PSC) Registers
PSC0
PSC1
REGISTER NAME
REGISTER DESCRIPTION
BYTE ADDRESS
BYTE ADDRESS
0x01C1 0000
0x01E2 7000
REVID
Peripheral Revision and Class Information
Register
0x01C1 0018
0x01C1 0040
0x01E2 7018
0x01E2 7040
INTEVAL
Interrupt Evaluation Register
MERRPR0
Module Error Pending Register 0 (module 0-
15) (PSC0)
Module Error Pending Register 0 (module 0-
31) (PSC1)
0x01C1 0050
0x01E2 7050
MERRCR0
Module Error Clear Register 0 (module 0-15)
(PSC0)
Module Error Clear Register 0 (module 0-31)
(PSC1)
0x01C1 0060
0x01C1 0068
0x01C1 0120
0x01C1 0128
0x01C1 0200
0x01C1 0204
0x01C1 0300
0x01C1 0304
0x01C1 0400
0x01C1 0404
0x01E2 7060
0x01E2 7068
0x01E2 7120
0x01E2 7128
0x01E2 7200
0x01E2 7204
0x01E2 7300
0x01E2 7304
0x01E2 7400
0x01E2 7404
PERRPR
PERRCR
PTCMD
Power Error Pending Register
Power Error Clear Register
Power Domain Transition Command Register
Power Domain Transition Status Register
Power Domain 0 Status Register
Power Domain 1 Status Register
Power Domain 0 Control Register
Power Domain 1 Control Register
Power Domain 0 Configuration Register
Power Domain 1 Configuration Register
PTSTAT
PDSTAT0
PDSTAT1
PDCTL0
PDCTL1
PDCFG0
PDCFG1
0x01C1 0800 - 0x01C1 083C 0x01E2 7800 - 0x01E2 787C MDSTAT0-MDSTAT15
Module Status n Register (modules 0-15)
(PSC0)
MDSTAT0-MDSTAT31
Module Status n Register (modules 0-31)
(PSC1)
0x01C1 0A00 - 0x01C1 0A3C 0x01E2 7A00 - 0x01E2 7A7C MDCTL0-MDCTL15
MDCTL0-MDCTL31
Module Control n Register (modules 0-15)
(PSC0)
Module Control n Register (modules 0-31)
(PSC1)
130
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.24.2 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several on the on chip modules, controllers and interconnect
components. Table 5-78 and Table 5-79 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. The module states and terminology are defined in Section 5.24.2.2.
Table 5-78. PSC0 Default Module Configuration
LPSC NUMBER
MODULE NAME
POWER DOMAIN
DEFAULT MODULE
STATE
AUTO SLEEP/WAKE
ONLY
0
1
EDMA3 Channel Controller
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
—
—
EDMA3 Transfer Controller 0
2
EDMA3 Transfer Controller 1
—
3
EMIFA (BR7)
SPI 0
—
4
—
5
MMC/SD 0
—
—
8
—
9
UART 0
AlwaysON (PD0)
AlwaysON (PD0)
SwRstDisable
Enable
—
10
SCR0
Yes
(Br 0, Br 1, Br 2, Br 8)
11
12
SCR1
(Br 4)
AlwaysON (PD0)
AlwaysON (PD0)
Enable
Enable
Yes
Yes
SCR2
(Br 3, Br 5, Br 6)
13
15
PRUSS
DSP
AlwaysON (PD0)
PD_DSP (PD1)
SwRstDisable-
Enable
—
—
Table 5-79. PSC1 Default Module Configuration
LPSC NUMBER
MODULE NAME
POWER DOMAIN
DEFAULT MODULE
AUTO SLEEP/WAKE
ONLY
STATE
0-2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
GPIO
AlwaysON (PD0)
—
SwRstDisable
—
4
—
5
EMAC
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
SwRstDisable
SwRstDisable
—
6
EMIFB (Br 20)
7
McASP0 ( + McASP0 FIFO)
8
McASP1 ( + McASP1 FIFO)
9-10
11
—
I2C 1
AlwaysON (PD0)
—
SwRstDisable
—
12
—
13
UART 2
—
AlwaysON (PD0)
—
SwRstDisable
—
14-16
17
eHRPWM0/1/2
—
AlwaysON (PD0)
—
SwRstDisable
—
18-19
20
ECAP0/1/2
EQEP0/1
—
AlwaysON (PD0)
AlwaysON (PD0)
—
SwRstDisable
SwRstDisable
—
21
22-23
24
SCR8
AlwaysON (PD0)
Enable
(Br 15)
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
131
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-79. PSC1 Default Module Configuration (continued)
LPSC NUMBER
MODULE NAME
POWER DOMAIN
AlwaysON (PD0)
AlwaysON (PD0)
—
DEFAULT MODULE
STATE
AUTO SLEEP/WAKE
ONLY
25
26
SCR7
(Br 12)
Enable
Enable
—
Yes
SCR12
(Br 18)
Yes
—
27-31
—
5.24.2.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
•
•
ON: power to the domain is on
OFF: power to the domain is off
In the device, for both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state.
•
On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
5.24.2.2 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 5-80.
Table 5-80. Module States
MODULE STATE MODULE RESET
MODULE
CLOCK
MODULE STATE DEFINITION
Enable
Disable
De-asserted
De-asserted
On
A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Off
A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset
Asserted
Asserted
On
Off
A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable
A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep
De-asserted
Off
A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake
De-asserted
Off
A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
132
Peripheral Information and Electrical Specifications
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
5.25 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
•
•
Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
•
A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 5-81 and in Table 5-82. Note that these two memory maps are implemented inside
the PRUSS and are local to the components of the PRUSS.
Table 5-81. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS
PRU0
PRU1
0x0000 0000 - 0x0000 0FFF
PRU0 Instruction RAM
PRU1 Instruction RAM
Table 5-82. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS
PRU0
Data RAM 0
Reserved
PRU1
Data RAM 1
Reserved
(1)
(1)
(1)
(1)
0x0000 0000 - 0x0000 01FF
0x0000 0200 - 0x0000 1FFF
0x0000 2000 - 0x0000 21FF
0x0000 2200 - 0x0000 3FFF
0x0000 4000 - 0x0000 6FFF
0x0000 7000 - 0x0000 73FF
0x0000 7400 - 0x0000 77FF
0x0000 7800 - 0x0000 7BFF
0x0000 7C00 - 0xFFFF FFFF
Data RAM 1
Reserved
Data RAM 0
Reserved
INTC Registers
PRU0 Control Registers
Reserved
INTC Registers
PRU0 Control Registers
Reserved
PRU1 Control Registers
Reserved
PRU1 Control Registers
Reserved
(1) Note that PRU0 accesses Data RAM0 at address 0x0000 0000, also PRU1 accesses Data RAM1 at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 5-83. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
133
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
Table 5-83. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map
BYTE ADDRESS
REGION
Data RAM 0
0x01C3 0000 - 0x01C3 01FF
0x01C3 0200 - 0x01C3 1FFF
0x01C3 2000 - 0x01C3 21FF
0x01C3 2200 - 0x01C3 3FFF
0x01C3 4000 - 0x01C3 6FFF
0x01C3 7000 - 0x01C3 73FF
0x01C3 7400 - 0x01C3 77FF
0x01C3 7800 - 0x01C3 7BFF
0x01C3 7C00 - 0x01C3 7FFF
0x01C3 8000 - 0x01C3 8FFF
0x01C3 9000 - 0x01C3 BFFF
0x01C3 C000 - 0x01C3 CFFF
0x01C3 D000 - 0x01C3 FFFF
Reserved
Data RAM 1
Reserved
INTC Registers
PRU0 Control Registers
PRU0 Debug Registers
PRU1 Control Registers
PRU1 Debug Registers
PRU0 Instruction RAM
Reserved
PRU1 Instruction RAM
Reserved
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses
5.25.1 PRUSS Register Descriptions
Table 5-84. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers
PRU0 BYTE ADDRESS
0x01C3 7000
PRU1 BYTE ADDRESS
0x01C3 7800
ACRONYM
CONTROL
STATUS
REGISTER DESCRIPTION
PRU Control Register
PRU Status Register
0x01C3 7004
0x01C3 7804
0x01C3 7008
0x01C3 7808
WAKEUP
CYCLCNT
STALLCNT
PRU Wakeup Enable Register
PRU Cycle Count
0x01C3 700C
0x01C3 780C
0x01C3 7010
0x01C3 7810
PRU Stall Count
PRU Constant Table Block Index
Register 0
0x01C3 7020
0x01C3 7028
0x01C3 7820
0x01C3 7828
CONTABBLKIDX0
CONTABPROPTR0
PRU Constant Table Programmable
Pointer Register 0
PRU Constant Table Programmable
Pointer Register 1
0x01C3 702C
0x01C3 782C
CONTABPROPTR1
PRU Internal General Purpose
Register 0 (for Debug)
0x01C37400 - 0x01C3747C
0x01C37480 - 0x01C374FC
0x01C3 7C00 - 0x01C3 7C7C
0x01C3 7C80 - 0x01C3 7CFC
INTGPR0 – INTGPR31
INTCTER0 – INTCTER31
PRU Internal General Purpose
Register 0 (for Debug)
Table 5-85. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers
BYTE ADDRESS
0x01C3 4000
0x01C3 4004
0x01C3 4010
0x01C3 401C
0x01C3 4020
0x01C3 4024
0x01C3 4028
0x01C3 402C
0x01C3 4034
0x01C3 4038
ACRONYM
REVID
REGISTER DESCRIPTION
Revision ID Register
CONTROL
Control Register
GLBLEN
Global Enable Register
GLBLNSTLVL
STATIDXSET
STATIDXCLR
ENIDXSET
Global Nesting Level Register
System Interrupt Status Indexed Set Register
System Interrupt Status Indexed Clear Register
System Interrupt Enable Indexed Set Register
System Interrupt Enable Indexed Clear Register
Host Interrupt Enable Indexed Set Register
Host Interrupt Enable Indexed Clear Register
ENIDXCLR
HSTINTENIDXSET
HSTINTENIDXCLR
134
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-85. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)
Registers (continued)
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
Global Prioritized Index Register
0x01C3 4080
0x01C3 4200
GLBLPRIIDX
STATSETINT0
System Interrupt Status Raw/Set Register 0
System Interrupt Status Raw/Set Register 1
System Interrupt Status Enabled/Clear Register 0
System Interrupt Status Enabled/Clear Register 1
System Interrupt Enable Set Register 0
System Interrupt Enable Set Register 1
System Interrupt Enable Clear Register 0
System Interrupt Enable Clear Register 1
Channel Map Registers 0-15
0x01C3 4204
STATSETINT1
0x01C3 4280
STATCLRINT0
0x01C3 4284
STATCLRINT1
0x01C3 4300
ENABLESET0
0x01C3 4304
ENABLESET1
0x01C3 4380
ENABLECLR0
0x01C3 4384
ENABLECLR1
0x01C3 4400 - 0x01C3 4440
0x01C3 4800 - 0x01C3 4808
CHANMAP0 - CHANMAP15
HOSTMAP0 - HOSTMAP2
Host Map Register 0-2
HOSTINTPRIIDX0 -
HOSTINTPRIIDX9
0x01C3 4900 - 0x01C3 4928
Host Interrupt Prioritized Index Registers 0-9
0x01C3 4D00
0x01C3 4D04
0x01C3 4D80
0x01C3 4D84
POLARITY0
POLARITY1
TYPE0
System Interrupt Polarity Register 0
System Interrupt Polarity Register 1
System Interrupt Type Register 0
System Interrupt Type Register 1
TYPE1
HOSTINTNSTLVL0-
HOSTINTNSTLVL9
0x01C3 5100 - 0x01C3 5128
0x01C3 5500
Host Interrupt Nesting Level Registers 0-9
Host Interrupt Enable Register
HOSTINTEN
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
135
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.26 Emulation Logic
The debug capabilities and features for DSP are as shown below.
DSP:
•
•
•
Basic Debug
–
–
Execution Control
System Visibility
Real-Time Debug
–
–
Interrupts serviced while halted
Low/non-intrusive system visibility while running
Advanced Debug
–
–
–
–
Global Start
Global Stop
Specify targeted memory level(s) during memory accesses
HSRTDX (High Speed Real Time Data eXchange)
•
•
Advanced System Control
–
–
–
Subsystem reset via debug
Peripheral notification of debug events
Cache-coherent debug accesses
Analysis Actions
–
–
–
–
–
–
Stop program execution
Generate debug interrupt
Benchmarking with counters
External trigger generation
Debug state machine state transition
Combinational and Sequential event generation
•
•
Analysis Events
–
–
–
–
–
Program event detection
Data event detection
External trigger Detection
System event detection (i.e. cache miss)
Debug state machine state detection
Analysis Configuration
–
–
Application access
Debugger access
Table 5-86. DSP Debug Features
CATEGORY
HARDWARE FEATURE
AVAILABILITY
Software breakpoint
Unlimited
Up to 10 HWBPs, including:
4 precise(1) HWBPs inside DSP core and one of them is associated with a
counter.
2 imprecise(1) HWBPs from AET.
Basic Debug
Hardware breakpoint
4 imprecise(1) HWBPs from AET which are shared for watch point.
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
136
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-86. DSP Debug Features (continued)
CATEGORY
HARDWARE FEATURE
AVAILABILITY
Up to 4 watch points, which are shared with HWBPs, and can also be used as 2
watch points with data (32 bits)
Watch point
Watch point with Data
Counters/timers
Up to 2, Which can also be used as 4 watch points.
Analysis
1x64-bits (cycle only) + 2x32-bits (water marke counters)
External Event Trigger In
External Event Trigger Out
1
1
5.26.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO).
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
Table 5-87. JTAG Port Description
PIN
TYPE
NAME
DESCRIPTION
When asserted (active low) causes all test and debug logic in the device to
be reset along with the IEEE 1149.1 interface
TRST
I
Test Logic Reset
This is the test clock used to drive an IEEE 1149.1 TAP state machine and
logic.
TCK
I
Test Clock
TMS
TDI
I
I
Test Mode Select
Test Data Input
Test Data Output
Emulation 0
Directs the next state of the IEEE 1149.1 test access port state machine
Scan data input to the device
TDO
EMU0
O
I/O
Scan data output of the device
Channel 0 trigger + HSRTDX
5.26.2 Scan Chain Configuration Parameters
Table 5-88 shows the TAP configuration details required to configure the router/emulator for this device.
Table 5-88. Router TAP Configuration
ROUTER PORT
ID
DEFAULT TAP
TAP NAME
TAP IR LENGTH
17
No
C674x
38
The router is revision C and has a 6-bit IR length.
5.26.3 JTAG 1149.1 Boundary Scan Considerations
To use boundary scan, the following sequence should be followed:
•
•
•
Execute a valid reset sequence and exit reset
Wait at least 6000 OSCIN clock cycles
Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU0 pin for boundary scan testing. If TRST is not driven by the
boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
137
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
5.27 IEEE 1149.1 JTAG
The JTAG (1) interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
Note: The sequencing of all the JTAG signals must follow the IEEE.1149.1 JTAG standard.
5.27.1 JTAG Peripheral Register Description(s) – JTAG ID Register
Table 5-89. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0x01C4 0028
JTAGID
JTAG Identification Register
Read-only. Provides 32-bit JTAG ID of the device.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The
register hex value each silicon revision is:
0x0B79 F02F for silicon revision 1.0.
0x8B79 F02F for silicon revision 1.1.
0x9B79 F02F for silicon revision 3.0, 2.1, and 2.0.
For the actual register bit names and their associated bit field descriptions, see Figure 5-48 and Table 5-
90.
31
VARIANT (4-Bit)
R-xxxx
28
27
12
11
1
0
PART NUMBER (16-Bit)
R-1011 0111 1101 1111
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value after reset
Figure 5-48. JTAG ID (DEVIDR0) Register Description - Register Value
138
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Table 5-90. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
DESCRIPTION
VARIANT
Variant (4-bit) value
PART NUMBER
MANUFACTURER
LSB
Part Number (16-Bit) value
Manufacturer (11-Bit) value
LSB. This bit is read as a "1".
5.27.2 JTAG Test-Port Electrical Data/Timing
Table 5-91. Timing Requirements for JTAG Test Port (see Figure 5-49)
No.
1
PARAMETER
MIN
MAX
UNIT
ns
tc(TCK)
Cycle time, TCK
40
16
16
4
2
tw(TCKH)
Pulse duration, TCK high
ns
3
tw(TCKL)
Pulse duration, TCK low
ns
4
tsu(TDIV-TCKH)
th(TCLKH-TDIV)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
ns
5
4
ns
Table 5-92. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-49)
No.
PARAMETER
Delay time, TCK low to TDO valid
MIN
MAX
UNIT
6
td(TCKL-TDOV)
15
ns
1
3
TCK
TDO
2
6
6
5
4
TDI/TMS/TRST
Figure 5-49. JTAG Test-Port Timing
Copyright © 2009–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
Submit Documentation Feedback
Product Folder Links: TMS320C6743
139
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
6 Device and Documentation Support
6.1 Device Support
6.1.1 Development Support
TI offers an extensive line of development tools for the TMS320C6743 platform, including tools to evaluate
the performance of the processors, generate code, develop algorithm implementations, and fully integrate
and debug software and hardware modules. The tool's support documentation is electronically available
within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320C6743 applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the device , visit the Texas Instruments web
site on the Worldwide Web at www.ti.com uniform resource locator (URL). For information on pricing
and availability, contact the nearest TI field sales office or authorized distributor.
6.1.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320C6743). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
140
Device and Documentation Support
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZWT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default).
Figure 6-1 provides a legend for reading the complete device name for any TMS320C674x member.
( )
( ) ( )
TMS
320
C6743
ZKB
PREFIX
DEVICE SPEED RANGE
TMX = Experimental Device
TMS = Qualified Device
2 = 200 MHz
3 = 300 MHz for revision 1.x
3 = 375 MHz for revision 2.x, 3.0
DEVICE FAMILY
TEMPERATURE RANGE (JUNCTION)
320 = TMS320™ DSP Family
Blank = 0°C to 90°C, Commercial Grade
= –40°C to 125°C, Automotive Grade
T
DEVICE
C6743
PACKAGE TYPE(A)
SILICON REVISION
Blank = Revision 1.0
A = Revision 1.1
B = Revision 2.0
C = Revision 2.1
D = Revision 3.0
ZKB = 256-Pin Plastic BGA, with Pb-free Soldered
Balls [Green]
PTP = 176-Pin Thin Quad Flat Pack (TQFP)
[PTP Suffix], 0.5 mm Pin Pitch
A. BGA = Ball Grid Array.
Figure 6-1. Device Nomenclature
6.2 Documentation Support
The following documents describe the TMS320C6743 Low-power digital signal processor. Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
DSP Reference Guides
SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
Copyright © 2009–2013, Texas Instruments Incorporated
Device and Documentation Support
141
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
SPRU186
TMS320C6000 Assembly Language Tools User's Guide. Describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C6000 platform of devices (including the C64x+, C67x+, and C674x
generations).
SPRU187
TMS320C6000 Optimizing Compiler User's Guide. Describes the TMS320C6000 C
compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code
and produces assembly language source code for the TMS320C6000 platform of devices
(including the C64x+, C67x+, and C674x generations). The assembly optimizer helps you
optimize your assembly code.
SPRUGJ0 TMS320C6743 DSP System Reference Guide. Describes the System-on-Chip (SoC)
system. The SoC system includes TI’s standard TMS320C674x Megamodule and several
blocks of internal memory (L1P, L1D, and L2).
SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRUFK9 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Provides
an overview and briefly describes the peripherals available on TMS320C6743.
142
Device and Documentation Support
Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6743
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
7 Mechanical Packaging and Orderable Information
This section describes the orderable part numbers, packaging options, materials, thermal and mechanical
parameters.
7.1 Thermal Data for ZKB
The following table(s) show the thermal resistance characteristics for the PBGA–ZKB mechanical
package.
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZKB]
NO.
CHARACTERISTIC
°C/W(1)
°C/W(2)
AIR FLOW
(m/s)(3)
1
2
RΘJC
RΘJB
RΘJA
Junction-to-case
12.8
15.1
24.5
21.9
21.1
20.4
19.6
0.6
13.5
19.7
33.8
30
N/A
N/A
Junction-to-board
Junction-to-free air
3
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
4
5
28.7
27.4
26
RΘJMA
Junction-to-moving air
6
7
8
0.8
9
0.8
1
10
11
12
13
14
15
16
17
PsiJT
Junction-to-package top
0.9
1.2
1.1
1.4
1.3
1.8
14.9
14.4
14.4
14.3
14.1
19.1
18.2
18
PsiJB
Junction-to-board
17.7
17.4
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and
1.5oz (50um) inner copper thickness
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) m/s = meters per second
Copyright © 2009–2013, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: TMS320C6743
143
TMS320C6743
SPRS565C –APRIL 2009–REVISED MARCH 2013
www.ti.com
7.2 Thermal Data for PTP
The following table(s) show the thermal resistance characteristics for the HTQFP–PTP mechanical
package.
Table 7-2. Thermal Resistance Characteristics (HTQFP Package) [PTP]
NO.
CHARACTERISTIC
°C/W(1)
°C/W(2)
°C/W(3)
°C/W(4)
AIR FLOW
(m/s)(5)
1
2
3
4
5
6
7
8
9
RΘJC
RΘJB
RΘJA
Junction-to-case
7.8
6.2
9.4
9.9
8.6
7.1
10.1
10.6
30.6
22.6
21.0
19.6
18.2
0.8
N/A
N/A
Junction-to-board
Junction-to-free air
21.3
14.3
13.1
12.1
11.2
0.5
27.9
20.2
18.6
17.4
16.2
0.7
23.2
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
0.00
0.50
1.00
2.00
4.00
RΘJMA Junction-to-moving air
0.6
0.9
1.0
10 PsiJT
Junction-to-package top
Junction-to-board
0.7
1.0
1.1
11
0.8
1.1
1.3
12
1.0
1.3
1.5
13
6.3
9.5
10.8
9.9
14
5.9
8.8
15 PsiJB
5.9
8.7
9.8
16
17
5.8
8.6
9.7
5.8
8.5
9.6
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers
connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient
temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on
environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal
Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 2oz (70um) top and bottom.
(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 1oz (35um) top and bottom.
(5) m/s = meters per second
7.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
This section highlights a few important details about the 176-pin PTP PowerPAD™ package. Texas
Instruments' PowerPAD Thermally Enhanced Package Technical Brief (SLMA002) should be consulted
when creating a PCB footprint for this device.
7.3.1 Standoff Height
As illustrated in Figure 7-1, the standoff height specification for this device (between 0.050 mm and
0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest
point on the package body. Due to warpage, the lowest point on the package body is located in the center
of the package at the exposed thermal pad.
Using this definition of standoff height provides the correct result for determining the correct solder paste
thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (SLMA002), the
recommended range of solder paste thickness for this package is between 0.152 mm and 0.178 mm.
144
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: TMS320C6743
Copyright © 2009–2013, Texas Instruments Incorporated
TMS320C6743
www.ti.com
SPRS565C –APRIL 2009–REVISED MARCH 2013
Standoff Height
Figure 7-1. Standoff Height Measurement on 176-pin PTP Package
7.3.2 PowerPAD™ PCB Footprint
In general, for proper thermal performance, the thermal pad under the package body should be as large
as possible. However, the soldermask opening for the PowerPAD™ should be sized to match the pad size
on the 176-pin PTP package; as illustrated in Figure 7-2.
Thermal Pad on T op Copper
should be as large as Possible.
Soldermask opening should be smaller and match
the size of the thermal pad on the DSP .
Figure 7-2. Soldermask Opening Should Match Size of DSP Thermal Pad
7.4 Mechanical Drawings
This section contains mechanical drawings for the ZKB Plastic Ball Grid Array package and the PTP Thin
Quad Flat Pack package. Additionally, for the PTP package a detailed drawing of the actual thermal pad
dimensions as well as a recommended PCB footprint are provided.
Copyright © 2009–2013, Texas Instruments Incorporated
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: TMS320C6743
145
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
PACKAGING INFORMATION
Orderable Device
TMS320C6743BPTP2
TMS320C6743BPTP3
TMS320C6743BPTPT2
TMS320C6743BPTPT3
TMS320C6743BZKB3
TMS320C6743BZKBT3
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 90
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
NRND
HLQFP
HLQFP
HLQFP
HLQFP
BGA
PTP
176
176
176
176
256
256
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
TMS320
C6743BPTP2
NRND
NRND
NRND
NRND
NRND
PTP
PTP
PTP
ZKB
ZKB
Green (RoHS
& no Sb/Br)
0 to 90
TMS320
C6743BPTP3
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
0 to 90
TMS320
C6743BPTPT2
Green (RoHS
& no Sb/Br)
TMS320
C6743BPTPT3
Green (RoHS
& no Sb/Br)
TMS320
C6743BZKB3
BGA
Green (RoHS
& no Sb/Br)
SNAGCU
-40 to 125
TMS320
C6743BZKBT3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
TMS320C6743ZKB3
16-BIT, 50MHz, OTHER DSP, PBGA256, 17 X 17 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-256
TI
©2020 ICPDF网 联系我们和版权申明