TMS320DM355DZCEA21 [TI]
数字媒体片上系统 (DMSoC) | ZCE | 337 | -40 to 100;
| 型号： | TMS320DM355DZCEA21 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 数字媒体片上系统 (DMSoC) | ZCE | 337 | -40 to 100 外围集成电路 |
| 文件： | 总153页 (文件大小：1391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
1 TMS320DM355 Digital Media System-on-Chip (DMSoC)
1.1 Features
encoder
•
High-Performance Digital Media
System-on-Chip
•
External Memory Interfaces (EMIFs)
–
–
216- and 270-MHz ARM926EJ-S Clock Rate
Fully Software-Compatible With ARM9
–
DDR2 and mDDR SDRAM 16-bit wide EMIF
With 256 MByte Address Space (1.8-V I/O)
Asynchronous16-/8-bit Wide EMIF (AEMIF)
–
•
ARM926EJ-S Core
–
•
Flash Memory Interfaces
Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
DSP Instruction Extensions and Single
Cycle MAC
–
–
NAND (8-/16-bit Wide Data)
OneNAND(16-bit Wide Data)
–
•
Flash Card Interfaces
–
–
ARM Jazelle Technology
EmbeddedICE-RT Logic for Real-Time
Debug
–
Two Multimedia Card (MMC) / Secure
Digital (SD/SDIO)
SmartMedia
–
•
•
ARM9 Memory Architecture
•
•
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
USB Port with Integrated 2.0 High-Speed PHY
that Supports
–
–
–
–
–
16K-Byte Instruction Cache
8K-Byte Data Cache
32K-Byte RAM
8K-Byte ROM
Little Endian
–
–
USB 2.0 Full and High-Speed Device
USB 2.0 Low, Full, and High-Speed Host
•
Three 64-Bit General-Purpose Timers (each
configurable as two 32-bit timers)
One 64-Bit Watch Dog Timer
Three UARTs (One fast UART with RTS and
CTS Flow Control)
Three Serial Port Interfaces (SPI) each with
two Chip-Selects
One Master/Slave Inter-Integrated Circuit
(I2C) Bus™
Two Audio Serial Port (ASP)
Video Processing Subsystem
– Front End Provides:
•
•
•
Hardware IPIPE for Real-Time Image
Processing
•
•
CCD and CMOS Imager Interface
14-Bit Parallel AFE (Analog Front End)
Interface Up to 75MHz
•
•
•
•
•
Glueless Interface to Common Video
Decoders
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
–
–
–
–
–
I2S and TDM I2S
AC97 Audio Codec Interface
S/PDIF via Software
Standard Voice Codec Interface (AIC12)
SPI Protocol (Master Mode Only)
•
•
Histogram Module
Resize Engine
–
–
–
Resize Images From 1/16x to 8x
Separate Horizontal/Vertical Control
Two Simultaneous Output Paths
•
•
•
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins
(Multiplexed with Other Device Functions)
On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, or UART
Configurable Power-Saving Modes
Crystal or External Clock Input (typically
24MHz or 36MHz)
Flexible PLL Clock Generators
Debug Interface Support
–
Back End Provides:
•
•
Hardware On-Screen Display (OSD)
Composite NTSC/PAL video encoder
output
•
•
•
•
8-/16-bit YCC and Up to 18-Bit RGB666
Digital Output
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
Supports digital HDTV (720p/1080i)
output for connection to external
•
•
•
•
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
I2C-bus is a trademark of Texas Instruments.
Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2007, Texas Instruments Incorporated
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
–
–
–
IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
ETB (Embedded Trace Buffer) with
4K-Bytes Trace Buffer memory
Device Revision ID Readable by ARM
•
337-Pin Ball Grid Array (BGA) Package
(ZCE Suffix), 0.65-mm Ball Pitch
90nm Process Technology
•
•
3.3-V and 1.8-V I/O, 1.3-V Internal
2
TMS320DM355 Digital Media System-on-Chip (DMSoC)
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
1.2 Description
The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP
security cameras, 4-channel digital video recorders, video door bell application, and other low cost
portable digital video applications. Designed to offer portable video designers and manufacturers the
ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines
high performance, high quality, low power consumption at a very low price point. The DM355 also enables
seamless interface to most additional external devices required for a complete digital camera
implementation. The interface is flexible enough to support various types of CCD and CMOS sensors,
signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and
auto-focus motor controls, etc.
The processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that
performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses
pipelining so that all parts of the processor and memory system can operate continuously. The ARM core
incorporates:
•
•
•
A coprocessor 15 (CP15) and protection module
Data and program Memory Management Units (MMUs) with table look-aside buffers.
Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
DM355 performance is enhanced by its MPEG/JPEG co-processor. The MPEG/JPEG co-processor
performs the computational operations required for image processing; JPEG compression and MPEG1,2,4
video and imaging standards.
The device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:
•
•
A Video Processing Front-End (VPFE)
A Video Processing Back-End (VPBE)
The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE
provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.
The DM355 peripheral set includes:
•
•
•
•
•
An inter-integrated circuit (I2C) Bus interface
Two audio serial ports (ASP)
Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
A 64-bit watchdog timer
Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation
modes, multiplexed with other peripherals
•
•
•
•
•
•
•
Three UARTs with hardware handshaking support on one UART
Three serial port Interfaces (SPI)
Four pulse width modulator (PWM) peripherals
Four real time out (RTO) outputs
Two Multi-Media Card / Secure Digital (MMC/SD) interfaces
A USB 2.0 full and high-speed device and host interface
Two external memory interfaces:
–
An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as
NAND and OneNAND,
–
A high speed synchronous memory interface for DDR2/mDDR.
For software development support the has a complete set of ARM development tools which include: C
compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger
interface for visibility into source code execution.
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TMS320DM355 Digital Media System-on-Chip (DMSoC)
3
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the DM355 device.
CCD/
CMOS
Module
CCDC
IPIPE
LD/CM
3A
DDR
controller
VPFE
Enhanced DMA
64 channels
DLL/
PHY
16 bit
DDR2/MDDR 16
10b
DAC
Composite video
Digital RGB/YUV
Video
Encoder
OSD
e
VPBE
VPSS
DMA/Data and configuration bus
USB2.0 PHY
ARM INTC
Nand/SM/
Async/One Nand
(EMIF2.3)
MPEG/JPEG
Co-processor
ARM926EJ-S_Z8
Speaker
microphone
ASP (2x)
MMC/SD (x2)
SPI I/F (x3)
UART (x3)
I2C
l-cache
16KB
RAM
32KB
D-cache
ROM
8KB
8KB
Timer/
WDT (x4 - 64)
GIO
PWM (x4)
RTO
Clocks
JTAG
I/F
CLOCK ctrl
PLLs
64bit DMA/Data Bus
Peripherals
32bit Configuration Bus
JTAG 24 MHz
27 MHz
(optional)
Figure 1-1. Functional Block Diagram
4
TMS320DM355 Digital Media System-on-Chip (DMSoC)
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Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Contents
4.1
Absolute Maximum Ratings Over Operating Case
Temperature Range
(Unless Otherwise Noted) .......................... 90
1
2
TMS320DM355 Digital Media System-on-Chip
(DMSoC) ................................................... 1
1.1 Features .............................................. 1
1.2 Description............................................ 3
1.3 Functional Block Diagram ............................ 4
Device Overview ......................................... 6
2.1 Device Characteristics................................ 6
2.2 Memory Map Summary............................... 7
2.3 Pin Assignments...................................... 9
2.4 Pin Functions........................................ 13
2.5 Pin List .............................................. 36
2.6 Device Support ...................................... 55
Detailed Device Description.......................... 59
3.1 ARM Subsystem Overview.......................... 59
3.2 ARM926EJ-S RISC CPU............................ 60
3.3 Memory Mapping.................................... 62
3.4 ARM Interrupt Controller (AINTC)................... 63
3.5 Device Clocking ..................................... 65
3.6 PLL Controller (PLLC)............................... 72
3.7 Power and Sleep Controller (PSC).................. 76
3.8 System Control Module ............................. 76
3.9 Pin Multiplexing...................................... 77
3.10 Device Reset ........................................ 78
3.11 Default Device Configurations....................... 79
3.12 Device Boot Modes ................................. 82
3.13 Power Management................................. 84
3.14 64-Bit Crossbar Architecture ........................ 86
3.15 MPEG/JPEG Overview.............................. 89
Device Operating Conditions ........................ 90
4.2 Recommended Operating Conditions............... 91
4.3
Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case
Temperature (Unless Otherwise Noted) ............ 92
5
Peripheral Information and Electrical
Specifications ........................................... 93
5.1
Parameter Information Device-Specific Information 93
Recommended Clock and Control Signal Transition
Behavior ............................................. 95
5.2
5.3 Power Supplies...................................... 95
5.4 Reset ................................................ 97
5.5 Oscillators and Clocks............................... 98
3
5.6
General-Purpose Input/Output (GPIO)............. 103
5.7 External Memory Interface (EMIF)................. 105
5.8 MMC/SD ........................................... 112
5.9
Video Processing Sub-System (VPSS) Overview . 114
5.10 USB 2.0 ............................................ 127
5.11 Universal Asynchronous Receiver/Transmitter
(UART) ............................................. 129
5.12 Serial Port Interface (SPI).......................... 131
5.13 Inter-Integrated Circuit (I2C) ....................... 134
5.14 Audio Serial Port (ASP)............................ 137
5.15 Timer............................................... 144
5.16 Pulse Width Modulator (PWM)..................... 145
5.17 Real Time Out (RTO) .............................. 147
5.18 IEEE 1149.1 JTAG ................................ 148
Mechanical Data....................................... 151
6.1 Thermal Data for ZCE ............................. 151
6.1.1 Packaging Information............................. 151
6
4
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Contents
5
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device,
including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin
count, etc.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES
DDR2 / mDDR Memory Controller
DDR2 / mDDR (16-bit bus width)
Asynchronous (8/16-bit bus width)
RAM, Flash (NAND, OneNAND)
Asynchronous EMIF (AEMIF)
Two MMC/SD
One SmartMedia/xD
Flash Card Interfaces
EDMA
64 independent DMA channels
Eight EDMA channels
Three 64-Bit General Purpose (each
configurable as two separate 32-bit
timers)
Timers
Peripherals
One 64-Bit Watch Dog
Not all peripherals pins are
available at the same time
(For more detail, see the
Device Configuration
section).
Three (one with RTS and CTS flow
control)
UART
SPI
Three (each supports two slave
devices)
I2C
One (Master/Slave)
Two ASP
Audio Serial Port [ASP]
General-Purpose Input/Output Port
Pulse width modulator (PWM)
Up to 104
Four outputs
One Input (VPFE)
One Output (VPBE)
Configurable Video Ports
USB 2.0
High, Full Speed Device
High, Full, Low Speed Host
ARM
On-Chip CPU Memory
JTAG BSDL_ID
Organization
16-KB I-cache, 8-KB D-cache, 32-KB
RAM, 8-KB ROM
JTAGID register (address location: 0x01C4 0028)
0x0B73B01F
ARM 216 MNz and 270 Mhz
1.3 V
CPU Frequency (Maximum) MHz
Core (V)
Voltage
I/O (V)
3.3 V, 1.8 V
Reference frequency options
Configurable PLL controller
24 MHz (typical), 36 MHz
PLL bypass, programmable PLL
PLL Options
BGA Package
13 x 13 mm
337-Pin BGA (ZCE)
90 nm
Process Technology
Product Preview (PP),
Advance Information (AI),
or Production Data (PD)
Product Status(1)
PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
6
Device Overview
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Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
2.2 Memory Map Summary
Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of
the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories
associated with its processor and various subsystems. To help simplify software development a unified
memory map is used where possible to maintain a consistent view of device resources across all bus
masters. The bus masters are the ARM, EDMA, USB, and VPSS.
Table 2-2. DM355 Memory Map
Start Address
0x0000 0000
0x0000 4000
0x0000 8000
End Address
0x0000 3FFF
0x0000 7FFF
0x0000 FFFF
Size (Bytes)
ARM
Mem Map
EDMA
Mem Map
USB
Mem Map
VPSS
Mem Map
16K
ARM RAM0
(Instruction)
16K
ARM RAM1
(Instruction)
Reserved
Reserved
32K
ARM ROM
(Instruction)
- only 8K used
0x0001 0000
0x0001 4000
0x0001 8000
0x0001 3FFF
0x0001 7FFF
0x0001 FFFF
16K
16K
32K
ARM RAM0 (Data)
ARM RAM1 (Data)
ARM RAM0
ARM RAM1
ARM ROM
ARM RAM0
ARM RAM1
ARM ROM
ARM ROM (Data)
- only 8K used
0x0002 0000
0x0010 0000
0x01BC 0000
0x01BC 1000
0x01BC 1800
0x01BC 1900
0x01BD 0000
0x01C0 0000
0x000F FFFF
0x01BB FFFF
0x01BC 0FFF
0x01BC 17FF
0x01BC 18FF
0x01BC FFFF
0x01BF FFFF
0x01FF FFFF
896K
26M
4K
Reserved
ARM ETB Mem
ARM ETB Reg
ARM IceCrusher
Reserved
2K
Reserved
256
Reserved
59136
192K
4M
CFG Bus
Peripherals
CFG Bus
Peripherals
Reserved
0x0200 0000
0x0A00 0000
0x11F0 0000
0x11F2 0000
0x2000 0000
0x09FF FFFF
0x11EF FFFF
0x11F1 FFFF
0x1FFF FFFF
0x2000 7FFF
128M
127M - 16K
128K
ASYNC EMIF (Data) ASYNC EMIF (Data)
Reserved
Reserved
141M-64K
32K
DDR EMIF Control
Regs
DDR EMIF Control
Regs
0x2000 8000
0x4200 0000
0x4A00 0000
0x8000 0000
0x9000 0000
0x41FF FFFF
0x49FF FFFF
0x7FFF FFFF
0x8FFF FFFF
0xFFFF FFFF
544M-32K
128M
Reserved
AEMIF - shadow
Reserved
Reserved
864M
256M
DDR EMIF
Reserved
DDR EMIF
DDR EMIF
Reserved
DDR EMIF
Reserved
1792M
Reserved
Table 2-3. DM355 ARM Configuration Bus Access to Peripherals
Address
Accessibility
Region
Start
End
Size
64K
1K
ARM
EDMA
EDMA CC
EDMA TC0
EDMA TC1
Reserved
Reserved
UART0
0x01C0 0000
0x01C1 0000
0x01C1 0400
0x01C1 8800
0x01C1 A000
0x01C2 0000
0x01C0 FFFF
0x01C1 03FF
0x01C1 07FF
0x01C1 9FFF
0x01C1 FFFF
0x01C2 03FF
√
√
√
√
√
√
√
√
√
√
√
√
1K
6K
24K
1K
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SPRS463–SEPTEMBER 2007
Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued)
Address
0x01C2 07FF
Accessibility
UART1
Timer4/5
0x01C2 0400
0x01C2 0800
0x01C2 0C00
0x01C2 1000
0x01C2 1400
0x01C2 1800
0x01C2 1C00
0x01C2 2000
0x01C2 2400
0x01C2 2800
0x01C2 2C00
0x01C4 0000
0x01C4 0800
0x01C4 0C00
0x01C4 1000
0x01C4 8000
0x01C6 4000
0x01C6 6000
0x01C6 6800
0x01C6 7000
0x01C6 7800
0x01C7 0000
0x01C7 0000
0x01C7 0080
0x01C7 0100
0x01C7 0200
0x01C7 0300
0x01C7 0400
0x01C7 0600
0x01C7 0800
0x01C7 0900
1K
1K
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0x01C2 0BFF
0x01C2 0FFF
0x01C2 13FF
0x01C2 17FF
0x01C2 1BFF
0x01C2 1FFF
0x01C2 23FF
0x01C2 27FF
0x01C2 2BFF
0x01C2 2FFF
0x01C4 07FF
0x01C4 0BFF
0x01C4 0FFF
0x01C4 1FFF
0x01C4 83FF
0x01C6 5FFF
0x01C6 67FF
0x01C6 6FFF
0x01C6 77FF
0x01C6 FFFF
0x01C7 FFFF
0x01C7 007F
0x01C7 00FF
0x01C7 01FF
0x01C7 02FF
0x01C7 03FF
0x01C7 05FF
0x01C7 07FF
0x01C7 08FF
0x01C7 09FF
Real-time out
I2C
1K
1K
Timer0/1
1K
Timer2/3
1K
WatchDog Timer
PWM0
1K
1K
PWM1
1K
PWM2
1K
PWM3
1K
System Module
PLL Controller 0
PLL Controller 1
Power/Sleep Controller
ARM Interrupt Controller
USB OTG 2.0 Regs / RAM
SPI0
2K
1K
1K
4K
1K
8K
2K
SPI1
2K
GPIO
2K
SPI2
2K
VPSS Subsystem
VPSS Clock Control
Hardware 3A
Image Pipe (IPIPE) Interface
On Screen Display
High Speed Serial IF
Video Encoder
CCD Controller
VPSS Buffer Logic
64K
128
128
256
256
256
512
256
256
256
CFA Multiply Mask / Lens
Distortion
Image Pipe (IPIPE)
Reserved
0x01C7 1000
0x01CC 0000
0x01CD 0000
0x01CD 0380
0x01CD F400
0x01CD FF00
0x01E0 0000
0x01E0 2000
0x01E0 4000
0x01E0 6000
0x01E0 6400
0x01E1 0000
0x01E1 1000
0x01E2 0000
0x0200 0000
0x01C7 3FFF
0x01CD FFFF
0x01CD 007F
0x01CD 03FF
0x01CD F4FF
0x01CD FFFF
0x01E0 1FFF
0x01E0 3FFF
0x01E0 5FFF
0x01E0 63FF
0x01E0 FFFF
0x01E1 0FFF
0x01E1 FFFF
0x01FF FFFF
0x03FF FFFF
12K
128K
128
128
256
256
8K
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
Reserved
Reserved
Reserved
Sequencer
Multimedia / SD 1
ASP0
8K
ASP1
8K
UART2
1K
Reserved
39K
4K
ASYNC EMIF Control
Multimedia / SD 0
Reserved
60K
1792K
32M
ASYNC EMIF Data (CE0)
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SPRS463–SEPTEMBER 2007
Table 2-3. DM355 ARM Configuration Bus Access to Peripherals (continued)
Address
0x05FF FFFF
Accessibility
ASYNC EMIF Data (CE1)
Reserved
0x0400 0000
0x0A00 0000
0x0C00 0000
32M
32M
64M
√
√
√
√
√
√
0x0BFF FFFF
0x0FFF FFFF
Reserved
2.3 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
2.3.1 Pin Map (Bottom View)
Figure 2-1 through Figure 2-4 show the pin assignments in four quadrants (A, B, C, and D). Note that
micro-vias are not required. Contact your TI representative for routing recommendations.
VDDA3P3
USB
VSSA_
PLL2
VSS
VSS
VSS
VDD
DP
VSS
CIN0
VCLK
CIN3
CIN2
VREF
J
H
G
F
VDDA1P2
_USB
VDDA_
PLL2
VSS
FIELD
VVALID
VSYNC
VDD
VSS
VSS
VFB
EXTCLK
COUT1
COUT3
COUT4
YOUT7
YOUT4
VDDSHV
TVOUT
IOUT
VSS
IBIAS
VSS
COUT0
COUT2
HSYNC VDDSHV4 VDDSHV4 VDDSHV4 VDDSHV
USB_
VBUS
EMU1
EMU0
TMS
TDO
TDI
E
D
C
B
A
VSS_USB
VSS_USB
COUT6
COUT7
YOUT3
USB_ID
USB_DRV VDDD1P2
USB
VDD
COUT5
YOUT0
USB_R1
VSSREF
TRST
MXO1
VBUS
VDDA_
USB_PLL
VSS_USB
VSS
VSS
YOUT5
VDD
VSS
VSS
YOUT1
2
YOUT2
3
YOUT6
4
USB_DM
6
USB_DP
7
MXI1
9
1
5
8
Figure 2-1. Pin Map [Quadrant A]
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1
2
3
4
5
6
7
8
9
DDR_CLK
VSS
DDR_A2
DDR_A3
DDR_A5
DDR_A8
DDR_A9 DDR_A11
DDR_CLK
W
V
U
T
VSS
DDR_A0
DDR_A1
DDR_A4
DDR_A7 DDR_A10 DDR_A12
DDR_
BA[2]
DDR_CAS
VSS
VSS
VSS
VSS
VSS
DDR_A6 DDR_A13
DDR_
BA[1]
DDR_
BA[0]
VSS
VSS
MXO2
MXI2
MX2GND
VSS
PCLK
YIN3
YIN4
CIN7
CIN5
CIN1
VSS
DDR_RAS
DDR_CS
DDR_ZN
VSS
VSS
VDD
VDD
VDDS
CAM_VD CAM_WEN_
FIELD
R
P
N
M
L
VDDSHV3 VDDSHV3 VDDSHV3
VDDS
YIN1
LVIREF
YIN2
YIN0
CAM_HD
YIN5
VDD
VSS
VSS
VDDA18V
_CCP2
VSS
VSS
VSS
VDDS
SN
YIN6
CIN4
VDDA18V VSS_DAC
_DAC
VSS
VSS
SP
YIN7
VDDSHV1
VSSA_
CCP2
VDD
VSS
DN
CIN6
VDDSHV2
K
Figure 2-2. Pin Map [Quadrant B]
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10
11
12
13
14
15
16
17
18
19
DDR_
DQ10
DDR_
DQ11
DDR_
DQ13
DDR_
DQ15
DDR_
GATE0
VDD
DDR_WE DDR_DQ1 DDR_DQ5 DDR_DQ7
W
V
U
T
DDR_
GATE1
DDR_
DQS[0]
DDR_
DQS[1]
DDR_
DQ14
VSS
DDR_CKE DDR_DQ0
DDR_DQ6 DDR_DQ9
EM_A13
EM_A12
EM_A8
UART0_
RXD
DDR_
DQM[1]
DDR_
DQ12
VSS
VSS
DDR_
VREF
DDR_DQ2 DDR_DQ4 DDR_DQ8
UART0_
TXD
DDR_
DQM[0]
VDDS
VSS
VDD
DDR_DQ3
DDR_
VDDDLL
UART1_
RXD
UART1_
TXD
VDDS
DDR_
VSSDLL
I2C_SDA I2C_SCL
EM_A11
EM_A7
EM_A10
EM_A6
EM_A3
EM_D15
EM_D12
EM_D9
EM_A5
R
P
N
M
L
VDDS
VDDS
VDDS
VDDS
VDDS
VSS
VSS
VSS
VSS
EM_A4
EM_A2
EM_A9
EM_A1
VSS
EM_BA1
EM_BA0
EM_D14
EM_D10
EM_D7
VDDSHV VDDSHV
VDDSHV VDDSHV VDDSHV VDDSHV
EM_D13
EM_D4
EM_A0
EM_D8
VSS
VDD
VDD
VDDSHV
EM_D11
EM_D6
VSS
VDD
VDD
VDDSHV
K
Figure 2-3. Pin Map [Quadrant C]
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VSS
VDD
VSS
VDD
VDD
VDD
VSS
EM_WE
EM_CE0
EM_ADV
EM_D1
EM_D3
EM_D0
EM_D5
EM_D2
J
ASP0_
DX
VSS_PLL
1
VDD
VDD
VSS
VDD
H
G
F
ASP0_
FSX
VDDA_
PLL1
VDDSHV
GIO3
GIO2
VSS
EM_WAIT EM_CE1
ASP0_
FSR
ASP0_
CLKR
ASP0_
EM_OE
CLKX
VDDSHV VDDSHV VDDSHV VDDSHV VDDSHV
SPI1_
SDENA
ASP1_
FSX
ASP1_
FSR
ASP0_
EM_CLK
DR
TCK
RTCK
SPI1_SDO
CLKOUT1
GIO1
E
D
C
B
A
SD0_
DATA1
ASP1_
CLKS
ASP1_
CLKR
ASP1_
CLKX
RESET
GIO5
SPI0_
SCLK
SPI1_
SCLK
ASP1_
DX
ASP1_
DR
MX1GND CLKOUT3
MMCSD0_ MMCSD1_
CMD CLK
GIO0
GIO7
GIO4
SPI0_
SDENA
MMCSD0_ MMCSD0_ MMCSD1_ MMCSD1_
DATA1
VSS
VDD
SPI0_SDO
GIO6
DATA2
DATA0
DATA3
MMCSD0_
DATA3
MMCSD1_
DATA2
MMCSD1_
DATA0
VDD
10
VSS
19
CLKOUT2 SPI0_SDI SPI1_SDI
MMCSD0_
CLK
MMCSD1_
CMD
11
12
13
14
15
16
17
18
Figure 2-4. Pin Map [Quadrant D]
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2.4 Pin Functions
The pin functions tables (Table 2-4 through Table 2-22) identify the external signal names, the associated
pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any
internal pullup or pulldown resistors, and a functional pin description. For more detailed information on
device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see
Section 3. For the list of all pin in chronological order see Section 2.5
2.4.1 Image Data Input - Video Processing Front End
The CCD Controller module in the Video Processing Front End has an external signal interface for image
data input. It supports YUV (YC) inputs as well as Bayer RGB and complementary input signals (I.e.,
image data input).
The definition of the CCD controller data input signals depend on the input mode selected.
•
In 16-bit YCbCr mode, the Cb and Cr signals are multiplexed on the Cl signals and the order is
configurable (i.e., Cb first or Cr first).
•
In 8-bit YCbCr mode, the Y, Cb, and Cr signals are multiplexed and not only is the order selectable,
but also the half of the bus used.
Table 2-4. CCD Controller Signals for Each Input Mode
PIN NAME
Cl7
CCD
16-BIT YCbCr
Cb7,Cr7
Cb6,Cr6
Cb5,Cr5
Cb4,Cr4
Cb3,Cr3
Cb2,Cr2
Cb1,Cr1
Cb0,Cr0
Y7
8-BIT YCbCr
Y7,Cb7,Cr7
Y6,Cb6,Cr6
Y5,Cb5,Cr5
Y4,Cb4,Cr4
Y3,Cb3,Cr3
Y2,Cb2,Cr2
Y1,Cb1,Cr1
Y0,Cb0,Cr0
Y7,Cb7,Cr7
Y6,Cb6,Cr6
Y5,Cb5,Cr5
Y4,Cb4,Cr4
Y3,Cb3,Cr3
Y2,Cb2,Cr2
Y1,Cb1,Cr1
Y0,Cb0,Cr0
Cl6
Cl5
CCD13
CCD12
CCD11
CCD10
CCD9
CCD8
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
Cl4
Cl3
Cl2
Cl1
Cl0
Yl7
Yl6
Y6
Yl5
Y5
Yl4
Y4
Yl3
Y3
Yl2
Y2
Yl1
Y1
Yl0
Y0
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Table 2-5. CCD Controller/Video Input Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Standard CCD Analog Front End (AFE): NOT USED
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[07]
CIN7/
GIO101/
SPI2_SCLK
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]
N3
I/O/Z
SPI: SPI2 Clock
GIO: GIO[101]
Standard CCD Analog Front End (AFE): NOT USED
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[06]
CIN6/
GIO100/
SPI2_SDO
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]
K5
M3
L4
I/O/Z
I/O/Z
I/O/Z
SPI: SPI2 Data Out
GIO: GIO[100]
Standard CCD Analog Front End (AFE): Raw[13]
CIN5/
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[05]
GIO099/
SPI2_SDEN
A[0]
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
SPI: SPI2 Chip Select
GIO: GIO[099]
Standard CCD Analog Front End (AFE): Raw[12]
CIN4/
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[04]
GIO098/
SPI2_SDEN
A[1]
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
SPI: SPI2 Data In
GIO: GIO[098]
Standard CCD Analog Front End (AFE): Raw[11]
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[03]
CIN3/
GIO097/
PD
VDD_VIN
J4
J5
L3
J3
L5
M4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[097]
Standard CCD Analog Front End (AFE): Raw[10]
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[02]
CIN2/
GIO096/
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[097]
Standard CCD Analog Front End (AFE): Raw[09]
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[01]
CIN1/
GIO095/
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[095]
Standard CCD Analog Front End (AFE): Raw[08]
•
•
YCC 16-bit: Time multiplexed between chroma: CB/SR[00]
CIN0/
GIO094/
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[094]
Standard CCD Analog Front End (AFE): Raw[07]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[07]
YIN7/
GIO093
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]
GIO: GIO[093]
Standard CCD Analog Front End (AFE): Raw[06]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[06]
YIN6/
GIO092
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]
GIO: GIO[092]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) PD = internal pull-down, PU = internal pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
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Table 2-5. CCD Controller/Video Input Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Standard CCD Analog Front End (AFE): Raw[05]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[05]
YIN5/
GIO091
PD
VDD_VIN
M5
I/O/Z
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
GIO: GIO[091]
Standard CCD Analog Front End (AFE): Raw[04]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[04]
YIN4/
GIO090
PD
VDD_VIN
P3
R3
P4
P2
P5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
GIO: GIO[090]
Standard CCD Analog Front End (AFE): Raw[03]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[03]
YIN3/
GIO089
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[089]
Standard CCD Analog Front End (AFE): Raw[02]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[02]
YIN2/
GIO088
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[088]
Standard CCD Analog Front End (AFE): Raw[01]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[01]
YIN1/
GIO087
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[087]
Standard CCD Analog Front End (AFE): Raw[00]
•
•
YCC 16-bit: Time multiplexed between chroma: Y[00]
YIN0/
GIO086
PD
VDD_VIN
YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[086]
Horizontal synchronization signal that can be either an input (slave mode) or an
output (master mode). Tells the CCDC when a new line starts.
GIO: GIO[085]
CAM_HD/
GIO085
PD
VDD_VIN
N5
R4
I/O/Z
I/O/Z
Vertical synchronization signal that can be either an input (slave mode) or an output
(master mode). Tells the CCDC when a new frame starts.
GIO: GIO[084]
CAM_VD
GIO084
PD
VDD_VIN
Write enable input signal is used by external device (AFE/TG) to gate the DDR
output of the CCDC module. Alternately, the field identification input signal is used
by external device (AFE/TG) to indicate which of two frames is input to the CCDC
module for sensors with interlaced output. CCDC handles 1- or 2-field sensors in
hardware.
CAM_WEN
_FIELD\
GIO083
PD
VDD_VIN
R5
T3
I/O/Z
I/O/Z
GIO: GIO[083]
PCLK/
GIO082
PD
VDD_VIN
Pixel clock input (strobe for lines C17 through Y10)
GIO: GIO[0082]
2.4.2 Image Data Output - Video Processing Back End (VPBE)
The Video Encoder/Digital LCD interface module in the video processing back end has an external signal
interface for digital image data output as described in Table 2-7 and Table 2-8.
The digital image data output signals support multiple functions / interfaces, depending on the display
mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565
signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).
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Table 2-6. Signals for VPBE Display Modes
PIN NAME
YCC16
HSYNC
YCC8/
REC656
PRGB
SRGB
HSYNC
GIO073
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
GIO072
VSYNC
VSYNC
VSYNC
LCD_OE
GIO071
As needed
As needed
As needed
As needed
As needed
As needed
As needed
As needed
FIELD
GIO070
R2
PWM3C
EXTCLK
GIO069
B2
As needed
VCLK
As needed
VCLK
As needed
VCLK
As needed
VCLK
PWM3D
VCLK
GIO068
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
C7
Y7,Cb7,Cr7
Y6,Cb6,Cr6
Y5,Cb5,Cr5
Y4,Cb4,Cr4
Y3,Cb3,Cr3
Y2,Cb2,Cr2
Y1,Cb1,Cr1
Y0,Cb0,Cr0
LCD_AC
R7
R6
R5
R4
R3
G7
G6
G5
G4
Data7
Data6
Data5
Data4
Data3
Data2
Data1
Data0
LCD_AC
COUT7
GIO081
PWM0
COUT6
GIO080
PWM1
C6
C5
LCD_OE
BRIGHT
G3
G2
LCD_OE
BRIGHT
COUT5
GIO079
PWM2A
RTO0
COUT4
GIO078
PWM2B
RTO1
C4
C3
C2
PWM
CSYNC
-
B7
B6
B5
PWM
CSYNC
-
COUT3
GIO077
PWM2C
RTO2
COUT2
GIO076
PWM2D
RTO3
COUT1
GIO075
PWM3A
C1
C0
-
-
B4
B3
-
-
COUT0
GIO074
PWM3B
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Table 2-7. Digital Video Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION(4)
NAME
NO.
C2
A4
B4
B3
B2
A3
A2
B1
YOUT7-R7
YOUT6-R6
YOUT5-R5
YOUT4-R4
YOUT3-R3
YOUT2-G7
YOUT1-G6
YOUT0-G5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
Digital Video Out: VENC settings determine function
COUT7-
G4/GIO081
/PWM0
C2
D2
I/O/Z
I/O/Z
VDD_VOUT
Digital Video Out: VENC settings determine function GIO: GIO[081] PWM0
Digital Video Out: VENC settings determine function GIO: GIO[080] PWM1
COUT6-G3
/GIO080
/PWM1
VDD_VOUT
COUT5-G2
/ GIO079 /
PWM2A /
RTO0
C1
D3
E3
E4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A RTO0
Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B RTO1
Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C RTO2
Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D RTO3
COUT4-B7 /
GIO078 /
PWM2B /
RTO1
COUT3-B6 /
GIO077 /
PWM2C /
RTO2
COUT2-B5 /
GIO076 /
PWM2D /
RTO3
COUT1-B4 /
GIO075 /
PWM3A
Digital Video Out: VENC settings determine function
GIO: GIO[075]
PWM3A
F3
F4
I/O/Z
I/O/Z
VDD_VOUT
COUT0-B3 /
GIO074 /
PWM3B
Digital Video Out: VENC settings determine function
GIO: GIO[074]
PWM3B
VDD_VOUT
HSYNC /
GIO073
PD
VDD_VOUT
Video Encoder: Horizontal Sync
GIO: GIO[073]
F5
I/O/Z
I/O/Z
VSYNC /
GIO072
PD
VDD_VOUT
Video Encoder: Vertical Sync
GIO: GIO[072]
G5
FIELD /
GIO070 /
R2 /
Video Encoder: Field identifier for interlaced display formats
GIO: GIO[070]
Digital Video Out: R2
PWM3C
H4
I/O/Z
VDD_VOUT
PWM3C
Video Encoder: External clock input, used if clock rates > 27 MHz are needed, e.g.
74.25 MHz for HDTV digital output
GIO: GIO[069]
Digital Video Out: B2
PWM3D
EXTCLK /
GIO069 /
B2 /
PD
VDD_VOUT
G3
H3
I/O/Z
I/O/Z
PWM3D
VCLK /
GIO068
Video Encoder: Video Output Clock
GIO: GIO[068]
VDD_VOUT
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
(4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the
following outputs placed near the DM355: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths
should be minimized.
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Table 2-8. Analog Video Terminal Functions
TERMINAL
TYPE(1) OTHER(2) DESCRIPTION
NAME
NO.
Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not
used, the VREF signal should be connected to VSS
VREF
J7
A I/O/Z
A I/O/Z
.
Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not
used, the IOUT signal should be connected to VSS
IOUT
IBIAS
VFB
E1
F2
G1
F1
.
Video DAC: External resistor (2550 Ohms to GND) connection for current bias
configuration. When the DAC is not used, the IBIAS signal should be connected to
A I/O/Z
A I/O/Z
A I/O/Z
VSS
.
Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to
TVOUT). When the DAC is not used, the VFB signal should be connected to VSS
.
Video DAC: Analog Composite NTSC/PAL output (SeeFigure 5-31 andFigure 5-32 for
circuit connection). When the DAC is not used, the TVOUT signal should be left as a
TVOUT
V
No Connect or connected to VSS
Video DAC: Analog 1.8V power. When the DAC is not used, the VDDA18_DAC signal
should be connected to VSS
Video DAC: Analog 1.8V ground. When the DAC is not used, the VSSA_DAC signal
should be connected to VSS
.
VDDA18_DAC
VSSA_DAC
L7
L8
PWR
GND
.
.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply
voltage for each signal. See Section 5.3, Power Supplies for more detail.
(2) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
2.4.3 Asynchronous External Memory Interface (AEMIF)
The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND.
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Address bus bit[13]
GIO: GIO[67]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used
to drive boot status LED signal (active low) in ROM boot modes.
EM_A13/
GIO067/
BTSEL[1]
PD
VDD
V19
I/O/Z
EM_A12/
GIO066/
BTSEL[0]
Async EMIF: Address bus bit[12]
GIO: GIO[66]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
PD
VDD
U19
R16
I/O/Z
I/O/Z
Async EMIF: Address bus bit[11]
GIO: GIO[65]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets
default for PinMux2_EM_D15_8: AEMIF default bus width (16 or 8 bits)
EM_A11/
GIO065/
AECFG[3]
PU
VDD
Async EMIF: Address bus bit[10]
EM_A10/
GIO064/
AECFG[2]
GIO: GIO[64]
PU
VDD
R18
P17
I/O/Z
I/O/Z
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit[09]
GIO: GIO[63]
AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
EM_A09/
GIO063/
AECFG[1]
PD
VDD
Async EMIF: Address bus bit[08]
GIO: GIO[62]
AECFG[0] sets default for:
EM_A08/
GIO062/
AECFG[0]
PD
VDD
T19
P16
I/O/Z
I/O/Z
•
•
PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND)
PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND)
EM_A07/
GIO061
Async EMIF: Address bus bit[07]
GIO: GIO[61]
VDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
EM_A06/
GIO060
Async EMIF: Address bus bit[06]
GIO: GIO[60]
P18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EM_A05/
GIO059
Async EMIF: Address bus bit[05]
GIO: GIO[59]
R19
P15
N18
N15
N17
M16
EM_A04/
GIO058
Async EMIF: Address bus bit[04]
GIO: GIO[58]
EM_A03/
GIO057
Async EMIF: Address bus bit[03]
GIO: GIO[57]
Async EMIF: Address bus bit[02]
NAND/SM/xD: CLE - Command latch enable output
EM_A02/
EM_A01/
Async EMIF: Address bus bit[01]
NAND/SM/xD: ALE - Address latch enable output
EM_A00/
GIO056
Async EMIF: Address bus bit[00]
GIO: GIO[56]
Async EMIF: Bank address 1 signal - 16-bit address:
EM_BA1/
GIO055
•
In 16-bit mode, lowest address bit.
P19
T19
I/O/Z
I/O/Z
VDD
•
In 8-bit mode, second lowest address bit.
GIO: GIO[055]
Async EMIF: Bank address 0 signal - 8-bit address:
EM_BA0/
GIO054
EM_A14
•
In 8-bit mode, lowest address bit. or can be used as an extra address line
(bit14) when using 16-bit memories.
VDD
GIO: GIO[054]
EM_D15/
GIO053
Async EMIF: Data bus bit 15
GIO: GIO[053]
M18
M19
M15
L18
L17
L19
K18
L16
K19
K17
J19
L15
J18
H19
J17
H18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EM_D14/
GIO052
Async EMIF: Data bus bit 14
GIO: GIO[052]
EM_D13/
GIO051
Async EMIF: Data bus bit 13
GIO: GIO[051]
EM_D12/
GIO050
Async EMIF: Data bus bit 12
GIO: GIO[050]
EM_D11/
GIO049
Async EMIF: Data bus bit 11
GIO: GIO[049]
EM_D10/
GIO048
Async EMIF: Data bus bit 10
GIO: GIO[048]
EM_D09/
GIO047
Async EMIF: Data bus bit 09
GIO: GIO[047]
EM_D08/
GIO046
Async EMIF: Data bus bit 08
GIO: GIO[046]
EM_D07/
GIO045
Async EMIF: Data bus bit 07
GIO: GIO[045]
EM_D06/
GIO044
Async EMIF: Data bus bit 06
GIO: GIO[044]
EM_D05/
GIO043
Async EMIF: Data bus bit 05
GIO: GIO[043]
EM_D04/
GIO042
Async EMIF: Data bus bit 04
GIO: GIO[042]
EM_D03/
GIO041
Async EMIF: Data bus bit 03
GIO: GIO[041]
EM_D02/
GIO040
Async EMIF: Data bus bit 02
GIO: GIO[040]
EM_D01/
GIO039
Async EMIF: Data bus bit 01
GIO: GIO[039]
EM_D00/
GIO038
Async EMIF: Data bus bit 00
GIO: GIO[038]
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Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Lowest numbered chip select. Can be programmed to be used for
standard asynchronous memories (example: flash), OneNAND, or NAND
memory. Used for the default boot and ROM boot modes.
GIO: GIO[037]
EM_CE0/
GIO037
J16
I/O/Z
VDD
Async EMIF: Second chip select. Can be programmed to be used for standard
asynchronous memories(example: flash), OneNAND, or NAND memory.
GIO: GIO[036]
EM_CE1/
GIO036
G19
J15
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
Async EMIF: Write Enable
NAND/SM/xD: WE (Write Enable) output
GIO: GIO[035]
EM_WE/
GIO035
Async EMIF: Output Enable
NAND/SM/xD: RE (Read Enable) output
GIO: GIO[034]
EM_OE/
GIO034
F19
G18
Async EMIF: Async WAIT
NAND/SM/xD: RDY/ BSY input
GIO: GIO[033]
EM_WAIT/
GIO033
EM_AVD/
GIO032
OneNAND: Address valid detect for OneNAND interface
GIO: GIO[032]
H16
E19
I/O/Z
I/O/Z
VDD
VDD
EM_CLK/
GIO031
OneNAND: Clock for OneNAND flash interface
GIO: GIO[031]
2.4.4 DDR Memory Interface
The DDR EMIF supports DDR2 and mobile DDR.
Table 2-10. DDR Terminal Functions
TERMINAL
NAME
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NO.
W9
W8
T6
DDR_CLK
DDR_CLK
DDR_RAS
DDR_CAS
DDR_WE
DDR_CS
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
DDR Data Clock
DDR Complementary Data Clock
DDR Row Address Strobe
DDR Column Address Strobe
DDR Write Enable
V9
W10
T8
DDR Chip Select
DDR_CKE
V10
DDR Clock Enable
DDR_DQM[
1]
Data mask outputs:
U15
T12
V15
I/O/Z
I/O/Z
I/O/Z
VDD_DDR
VDD_DDR
VDD_DDR
•
•
DQM0 - For DDR_DQ[7:0]
DQM1 - For DDR_DQ[15:8]
DDR_DQM[
0]
DDR_DQS[
1]
Data strobe input/outputs for each byte of the 16-bit data bus used to
synchronize the data transfers. Output to DDR when writing and inputs when
reading.
DDR_DQS[
0]
•
•
DQS1 - For DDR_DQ[15:8]
DQS0 - For DDR_DQ[7:0]
V12
I/O/Z
VDD_DDR
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
DDR_A13
DDR_A12
DDR_A11
V8
U7
U8
U6
V7
W7
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
Bank select outputs. Two are required for 1Gb DDR2 memories.
Bank select outputs. Two are required for 1Gb DDR2 memories.
Bank select outputs. Two are required for 1Gb DDR2 memories.
DDR Address Bus bit 13
DDR Address Bus bit 12
DDR Address Bus bit 11
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-10. DDR Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
V6
DDR_A10
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
DDR Address Bus bit 10
DDR Address Bus bit 09
DDR Address Bus bit 08
DDR Address Bus bit 07
DDR Address Bus bit 06
DDR Address Bus bit 05
DDR Address Bus bit 04
DDR Address Bus bit 03
DDR Address Bus bit 02
DDR Address Bus bit 01
DDR Address Bus bit 00
DDR Data Bus bit 15
DDR Data Bus bit 14
DDR Data Bus bit 13
DDR Data Bus bit 12
DDR Data Bus bit 11
DDR Data Bus bit 10
DDR Data Bus bit 09
DDR Data Bus bit 08
DDR Data Bus bit 07
DDR Data Bus bit 06
DDR Data Bus bit 05
DDR Data Bus bit 04
DDR Data Bus bit 03
DDR Data Bus bit 02
DDR Data Bus bit 01
DDR Data Bus bit 00
DDR_A09
W6
DDR_A08
W5
DDR_A07
V5
DDR_A06
U5
DDR_A05
W4
DDR_A04
V4
DDR_A03
W3
DDR_A02
W2
DDR_A01
V3
DDR_A00
V2
DDR_DQ15
DDR_DQ14
DDR_DQ13
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ09
DDR_DQ08
DDR_DQ07
DDR_DQ06
DDR_DQ05
DDR_DQ04
DDR_DQ03
DDR_DQ02
DDR_DQ01
DDR_DQ00
W17
V16
W16
U16
W15
W14
V14
U13
W13
V13
W12
U12
T11
U11
W11
V11
DDR_GATE
0
DDR: Loopback signal for external DQS gating. Route to DDR and back to
DDR_GATE0 with same constraints as used for DDR clock and data.
W18
V17
U10
R11
R10
T9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
DDR_GATE
1
DDR: Loopback signal for external DQS gating. Route to DDR and back to
DDR_GATE0 with same constraints as used for DDR clock and data.
DDR: Voltage input for the SSTL_18 I/O buffers. Note even in the case of mDDR
an external resistor divider connected to this pin is necessary.
DDR_VREF
DDR_VSSD
LL
DDR: Ground for the DDR DLL
DDR_VDDD
LL
DDR: Power (3.3 V) for the DDR DLL
DDR: Reference output for drive strength calibration of N and P channel outputs.
Tie to ground via 50 ohm resistor @ 0.5% tolerance.
DDR_ZN
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2.4.5 GPIO
The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are
multiplexed with other functions.
Table 2-11. GPIO Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
GIO: GIO[000] Active low during MMC/SD boot (can be used as MMC/SD power
control).
GIO000
C16
I/O/Z
VDD
Can be used as external clock input for Timer 3.
GIO001
GIO002
GIO003
GIO004
GIO005
GIO006
E14
F15
G15
B17
D15
B18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
VDD
GIO: GIO[001] Can be used as external clock input for Timer 3.
GIO: GIO[002] Can be used as external clock input for Timer 3.
GIO: GIO[003] Can be used as external clock input for Timer 3.
GIO: GIO[004]
GIO: GIO[005]
GIO: GIO[006]
GIO007 /
SPI0_SDE
NA[1]
GIO: GIO[007]
SPI0: Chip Select 1
C17
B11
I/O/Z
I/O/Z
VDD
SPI1_SD
O /
GIO008
SPI1: Data Out
GIO: GIO[008]
VDD
SPI1_SDI
/ GIO009 /
SPI1_SDE
NA[1]
A12
I/O/Z
VDD
SPI1: Data In -OR- SPI1: Chip Select 1 GIO: GIO[009]
SPI1_SCL
K /
GIO010
SPI1: Clock GIO:
GIO[010]
C12
B12
R17
R15
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
SPI1_SDE
NA[0] /
GIO011
SPI1: Chip Select 0
GIO: GIO[011]
UART1_T
XD /
GIO012
UART1: Transmit Data
GIO: GIO[012]
UART1_R
XD /
GIO013
UART1: Receive Data
GIO: GIO[013]
I2C_SCL /
GIO014
I2C: Serial Clock GIO:
GIO[014]
R14
R13
C11
A11
D12
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
I2C_SDA /
GIO015
I2C: Serial Data
GIO: GIO[015]
CLKOUT3
/ GIO016
CLKOUT: Output Clock 3
GIO: GIO[016]
CLKOUT2
/ GIO017
CLKOUT: Output Clock 2
GIO: GIO[017]
CLKOUT1
/ GIO018
CLKOUT: Output Clock 1
GIO: GIO[018]
MMCSD1
_DATA0 /
GIO019 /
UART2_T
XD
MMCSD1: DATA0
GIO: GIO[019]
UART2: Transmit Data
A18
I/O/Z
VDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
MMCSD1
_DATA1 /
GIO020 /
UART2_R
XD
MMCSD1: DATA1
GIO: GIO[020]
UART2: Receive Data
B15
I/O/Z
VDD
MMCSD1
_DATA2 /
GIO021 /
UART2_C
TS
MMCSD1: DATA2
GIO: GIO[021]
UART2: CTS
A16
B16
I/O/Z
I/O/Z
VDD
MMCSD1
_DATA3 /
GIO022 /
UART2_R
TS
MMCSD1: DATA3
GIO: GIO[022]
UART2: RTS
VDD
MMCSD1
_CMD /
GIO023
MMCSD1: Command
GIO: GIO[023]
A17
C15
F16
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
MMCSD1
_CLK /
GIO024
MMCSD1: Clock
GIO: GIO[024]
ASP0_FS
R /
GIO025
ASP0: Receive Frame Synch
GIO: GIO[025]
ASP0_CL
KR /
GIO026
ASP0: Receive Clock
GIO: GIO[026]
F17
E18
G17
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
ASP0_DR
/ GIO027
ASP0: Receive Data
GIO: GIO[027]
ASP0_FS
X /
GIO028
ASP0: Transmit Frame Synch
GIO: GIO[028]
ASP0_CL
KX /
GIO029
ASP0: Transmit Clock
GIO: GIO[029]
F18
I/O/Z
VDD
ASP0_DX
/ GIO030
ASP0: Transmit Data
GIO: GIO[030]
H15
E19
H16
G18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
EM_CLK /
GIO031
OneNAND: Clock signal for OneNAND flash interface GIO: GIO[031]
EM_AVD /
GIO032
PD
VDD
OneNAND: Address Valid Detect for OneNAND interface
GIO: GIO[032]
EM_WAIT
/ GIO033
PU
VDD
Async EMIF: Async WAIT NAND/SM/xD: RDY/_BSY input
GIO: GIO[033]
Async EMIF: Output Enable
NAND/SM/xD: RE (Read Enable) output
GIO: GIO[034]
EM_OE /
GIO034
F19
J15
G19
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
Async EMIF: Write Enable
NAND/SM/xD: WE (Write Enable) output
GIO: GIO[035]
EM_WE /
GIO035
Async EMIF: Second Chip Select., Can be programmed to be used for standard
asynchronous memories (example: flash), OneNand or NAND memory.
GIO: GIO[036]
EM_CE1 /
GIO036
Async EMIF: Lowest numbered Chip Select. Can be programmed to be used for
standard asynchronous memories (example: flash), OneNand or NAND memory.
Used for the default boot and ROM boot modes.
EM_CE0 /
GIO037
J16
I/O/Z
I/O/Z
VDD
GIO: GIO[037]
EM_D00 /
GIO038
Async EMIF: Data Bus bit[00]
GIO: GIO[038]
H18
VDD
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
EM_D01 /
GIO039
Async EMIF: Data Bus bit[01]
GIO: GIO[039]
J17
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
EM_D02 /
GIO040
Async EMIF: Data Bus bit[02]
GIO: GIO[040]
H19
J18
EM_D03 /
GIO041
Async EMIF: Data Bus bit[03]
GIO: GIO[041]
EM_D04 /
GIO042
Async EMIF: Data Bus bit[04]
GIO: GIO[042]
L15
EM_D05 /
GIO043
Async EMIF: Data Bus bit[05]
GIO: GIO[043]
J19
EM_D06 /
GIO044
Async EMIF: Data Bus bit[06]
GIO: GIO[044]
K17
K19
L16
EM_D07 /
GIO045
Async EMIF: Data Bus bit[07]
GIO: GIO[045]
EM_D08 /
GIO046
Async EMIF: Data Bus bit[08]
GIO: GIO[046]
EM_D09 /
GIO047
Async EMIF: Data Bus bit[09]
GIO: GIO[047]
K18
ML19
L17
EM_D10 /
GIO048
Async EMIF: Data Bus bit[10]
GIO: GIO[048]
EM_D11 /
GIO049
Async EMIF: Data Bus bit[11]
GIO: GIO[049]
EM_D12 /
GIO050
Async EMIF: Data Bus bit[12]
GIO: GIO[050]
L18
EM_D13 /
GIO051
Async EMIF: Data Bus bit[13]
GIO: GIO[051]
M15
M19
M18
EM_D14 /
GIO052
Async EMIF: Data Bus bit[14]
GIO: GIO[052]
EM_D15 /
GIO053
Async EMIF: Data Bus bit[15]
GIO: GIO[053]
Async EMIF: Bank Address 0 signal = 8-bit address. In 8-bit mode, lowest
address bit. Or, can be used as an extra Address line (bit[14] when using 16-bit
memories.
GIO: GIO[054]
EM_BA0 /
GIO054 /
EM_A14
T19
I/O/Z
VDD
Async EMIF: Bank Address 1 signal = 16-bit address. In 16-bit mode, lowest
address bit. In 8-bit mode, second lowest address bit
GIO: GIO[055]
EM_BA1 /
GIO055
P19
M16
I/O/Z
I/O/Z
VDD
Async EMIF: Address Bus bit[00] Note that the EM_A0 is always a 32-bit
address
GIO: GIO[056]
EM_A00 /
GIO056
VDD
EM_A03 /
GIO057
Async EMIF: Address Bus bit[03]
GIO: GIO[057]
N18
P15
R19
P18
P16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
EM_A04 /
GIO058
Async EMIF: Address Bus bit[04]
GIO: GIO[058]
EM_A05 /
GIO059
Async EMIF: Address Bus bit[05]
GIO: GIO[059]
EM_A06 /
GIO060
Async EMIF: Address Bus bit[06]
GIO: GIO[060]
EM_A07 /
GIO061
Async EMIF: Address Bus bit[07]
GIO: GIO[061] - Used by ROM Bootloader to provide progress status via LED
Async EMIF: Address Bus bit[08]
EM_A08 /
GIO062 /
AECFG[0]
GIO: GIO[062] AECFG[0] sets default for - PinMux2.EM_A0_BA1: AEMIF
Address Width (OneNAND or NAND) - PinMux2.EM_A13_3: AEMIF Address
Width (OneNAND or NAND)
T19
I/O/Z
VDD
24
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SPRS463–SEPTEMBER 2007
Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Address Bus bit[09]
EM_A09 /
GIO063 /
AECFG[1]
GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0
Definition (EM_BA0, EM_A14, GIO[054], rsvd)
P17
I/O/Z
VDD
Async EMIF: Address Bus bit[10]
EM_A10 /
GIO064 /
AECFG[2]
GIO: GIO[064] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0
Definition (EM_BA0, EM_A14, GIO[054], rsvd)
R18
I/O/Z
VDD
EM_A03 /
GIO057
Async EMIF: Address Bus bit[03]
GIO: GIO[057]
N18
P15
R19
P18
P16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
EM_A04 /
GIO058
Async EMIF: Address Bus bit[04]
GIO: GIO[058]
EM_A05 /
GIO059
Async EMIF: Address Bus bit[05]
GIO: GIO[059]
EM_A06 /
GIO060
Async EMIF: Address Bus bit[06]
GIO: GIO[060]
EM_A07 /
GIO061
Async EMIF: Address Bus bit[07]
GIO: GIO[061] - Used by ROM Bootloader to provide progress status via LED
Async EMIF: Address Bus bit[08]
EM_A08 /
GIO062 /
AECFG[0]
PU
VDD
GIO: GIO[062] AECFG[0] sets default for - PinMux2.EM_A0_BA1: AEMIF
Address Width (OneNAND or NAND) - PinMux2.EM_A13_3: AEMIF Address
Width (OneNAND or NAND)
T19
P17
R18
I/O/Z
I/O/Z
I/O/Z
Async EMIF: Address Bus bit[09]
EM_A09 /
GIO063 /
AECFG[1]
PD
VDD
GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0
Definition (EM_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address Bus bit[10]
EM_A10 /
GIO064 /
AECFG[2]
PU
VDD
GIO: GIO[064] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0
Definition (EM_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address Bus bit[11]
EM_A11 /
GIO065 /
AECFG[3]
PU
VDD
GIO: GIO[065] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
Configuration AECFG[3] sets default for PinMux2.EM_D15_8: AEMIF Default
Bus Width (16 or 8 bits)
R16
U19
I/O/Z
I/O/Z
EM_A12 /
GIO066 /
BTSEL[0]
Async EMIF: Address Bus bit[12]
GIO: GIO[066] System: BTSEL[1:0] sampled at Power-on-Reset to determine
Boot method
PD
VDD
Async EMIF: Address Bus bit[13]
EM_A13 /
GIO067 /
BTSEL[1]
PD
VDD
GIO: GIO[067] System: BTSEL[1:0] sampled at Power-on-Reset to determine
Boot method Used to drive Boot Status LED signal (active low) in ROM boot
modes
V19
H3
I/O/Z
I/O/Z
I/O/Z
VCLK /
GIO068
Video Encoder: Video Output Clock
GIO: GIO[068]
VDD_VOUT
EXTCLK /
GIO069 /
B2 /
Video Encoder: External clock input, used if clock rates > 27 MHz are needed,
e.g. 74.25 MHz for HDTV digital output
GIO: GIO[069] Digital Video Out: B2 PWM3D
PD
VDD_VOUT
G3
PWM3D
FIELD /
GIO070 /
R2 /
Video Encoder: Field identifier for interlaced display formats
GIO: GIO[070] Digital Video Out: R2 PWM3C
H4
I/O/Z
VDD_VOUT
PWM3C
VSYNC /
GIO072
PD
VDD_VOUT
Video Encoder: Vertical Sync
GIO: GIO[072]
G5
F5
I/O/Z
I/O/Z
HSYNC /
GIO073
PD
VDD_VOUT
Video Encoder: Horizontal Sync
GIO: GIO[073]
COUT0-
B3 /
GIO074 /
PWM3B
Digital Video Out: VENC settings determine function GIO: GIO[074]
PWM3B
F4
I/O/Z
VDD_VOUT
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SPRS463–SEPTEMBER 2007
Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
COUT1-
B4 /
GIO075 /
PWM3A
Digital Video Out: VENC settings determine function GIO: GIO[075]
PWM3A
F3
I/O/Z
VDD_VOUT
COUT2-
B5 /
GIO076 /
PWM2D /
RTO3
Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D
RTO3
E4
E3
D3
I/O/Z
I/O/Z
I/O/Z
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
COUT3-
B6 /
GIO077 /
PWM2C /
RTO2
Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C
RTO2
COUT4-
B7 /
GIO078 /
PWM2B /
RTO1
Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B
RTO1
COUT5-
G2 /
GIO079 /
PWM2A /
RTO0
Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A
RTO0
C1
D2
I/O/Z
I/O/Z
COUT6-
G3 /
GIO080 /
PWM1
Digital Video Out: VENC settings determine function GIO: GIO[080]
PWM1
VDD_VOUT
COUT7-
G4 /
GIO081 /
PWM0
Digital Video Out: VENC settings determine function GIO: GIO[081]
PWM0
C2
T3
I/O/Z
I/O/Z
VDD_VOUT
PCLK /
GIO082
PD
VDD_VIN
Pixel clock input (strobe for lines CI7 through YI0) GIO: GIO[082]
Write enable input signal is used by external device (AFE/TG) to gate the DDR
output of the CCDC module. Alternately, the field identification input signal is
used by external device (AFE/TG) to indicate the which of two frames is input to
the CCDC module for sensors with interlaced output. CCDC handles 1- or 2-field
sensors in hardware. GIO: GIO[083]
CAM_WE
N_FIELD /
GIO083
PD
VDD_VIN
R5
I/O/Z
Vertical synchronization signal that can be either an input (slave mode) or an
output (master mode). Tells the CCDC when a new frame starts.
GIO: GIO[084]
CAM_VD /
GIO084
PD
VDD_VIN
R4
N5
I/O/Z
I/O/Z
Horizontal synchronization signal that can be either an input (slave mode) or an
output (master mode). Tells the CCDC when a new line starts.
GIO: GIO[085]
CAM_HD /
GIO085
PD
VDD_VIN
Standard CCD Analog Front End (AFE): raw[00] YCC 16-bit: time multiplexed
between luma: Y[00] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[00]
YIN0 /
GIO086
PD
VDD_VIN
P5
P2
P4
I/O/Z
I/O/Z
I/O/Z
GIO: GIO[086]
Standard CCD Analog Front End (AFE): raw[01] YCC 16-bit: time multiplexed
between luma: Y[01] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[01]
YIN1 /
GIO087
PD
VDD_VIN
GIO: GIO[087]
Standard CCD Analog Front End (AFE): raw[02] YCC 16-bit: time multiplexed
between luma: Y[02] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[02]
YIN2 /
GIO088
PD
VDD_VIN
GIO: GIO[088]
26
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Standard CCD Analog Front End (AFE): raw[03] YCC 16-bit: time multiplexed
between luma: Y[03] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[03]
YIN3 /
GIO089
PD
VDD_VIN
R3
I/O/Z
GIO: GIO[089]
Standard CCD Analog Front End (AFE): raw[04] YCC 16-bit: time multiplexed
between luma: Y[04] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[04]
YIN4 /
GIO090
PD
VDD_VIN
P3
M5
M4
L5
J3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
GIO: GIO[090]
Standard CCD Analog Front End (AFE): raw[05] YCC 16-bit: time multiplexed
between luma: Y[05] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[05]
YIN5 /
GIO091
PD
VDD_VIN
GIO: GIO[091]
Standard CCD Analog Front End (AFE): raw[06] YCC 16-bit: time multiplexed
between luma: Y[06] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[06]
YIN6 /
GIO092
PD
VDD_VIN
GIO: GIO[092]
Standard CCD Analog Front End (AFE): raw[07] YCC 16-bit: time multiplexed
between luma: Y[07] YCC 08-bit (which allows for 2 simultaneous decoder
inputs), it is time multiplexed between luma and chroma of the lower channel.
Y/CB/CR[07]
YIN7 /
GIO093
PD
VDD_VIN
GIO: GIO[093]
Standard CCD Analog Front End (AFE): raw[08] YCC 16-bit: time multiplexed
between chroma: CB/CR[00] YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed between luma and chroma of the upper
channel. Y/CB/CR[00]
CIN0 /
GIO094
PD
VDD_VIN
GIO: GIO[094]
Standard CCD Analog Front End (AFE): raw[09] YCC 16-bit: time multiplexed
between chroma: CB/CR[01] YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed between luma and chroma of the upper
channel. Y/CB/CR[01]
CIN1 /
GIO095
PD
VDD_VIN
L3
J5
GIO: GIO[095]
Standard CCD Analog Front End (AFE): raw[10] YCC 16-bit: time multiplexed
between chroma: CB/CR[02] YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed between luma and chroma of the upper
channel. Y/CB/CR[02]
CIN2 /
GIO096
PD
VDD_VIN
GIO: GIO[096]
Standard CCD Analog Front End (AFE): raw[11] YCC 16-bit: time multiplexed
between chroma: CB/CR[03] YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed between luma and chroma of the upper
channel. Y/CB/CR[03]
CIN3 /
GIO097
PD
VDD_VIN
J4
GIO: GIO[097]
CIN4 /
Standard CCD Analog Front End (AFE): raw[12] YCC 16-bit: time multiplexed
between chroma: CB/CR[04] YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed between luma and chroma of the upper
channel. Y/CB/CR[04] SPI: SPI2 Data In
GIO098 /
SPI2_SDI
/
SPI2_SDE
NA[1]
PD
VDD_VIN
L4
I/O/Z
GIO: GIO[098]
Standard CCD Analog Front End (AFE): raw[13] YCC 16-bit: time multiplexed
between chroma: CB/CR[05] YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed between luma and chroma of the upper
channel. Y/CB/CR[05] SPI: SPI2 Chip Select
CIN5 /
GIO099 /
SPI2_SDE
NA[0]
PD
VDD_VIN
M3
K5
I/O/Z
I/O/Z
GIO: GIO[99]
Standard CCD Analog Front End (AFE): NOT USED YCC 16-bit: time
multiplexed between chroma: CB/CR[06] YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time multiplexed between luma and chroma of
the upper channel. Y/CB/CR[06] SPI: SPI2 Data Out
CIN6 /
GIO100 /
SPI2_SD
O
PD
VDD_VIN
GIO: GIO[100]
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SPRS463–SEPTEMBER 2007
Table 2-11. GPIO Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Standard CCD Analog Front End (AFE): NOT USED YCC 16-bit: time
multiplexed between chroma: CB/CR[07] YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time multiplexed between luma and chroma of
the upper channel. Y/CB/CR[07] SPI: SPI2 Clock
CIN7 /
GIO101 /
SPI2_SCL
K
PD
VDD_VIN
N3
I/O/Z
GIO: GIO[101]
SPI0_SDI
/ GIO102
SPI0: Data In
GIO: GIO[102]
A12
B12
I/O/Z
I/O/Z
VDD
SPI0_SDE
NA[0] /
GIO103
SPI0: Chip Select 0
GIO: GIO[103]
VDD
2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces
The DM355 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the
MMC/SD and SDIO protocol.
Table 2-12. MMC/SD Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
MMCSD0_
CLK/
A15
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
VDD
MMCSD0: Clock
MMCSD0_
CMD/
C14
B14
D14
B13
A14
MMCSD0: Command
MMCSD0: DATA0
MMCSD0: DATA1
MMCSD0: DATA2
MMCSD0: DATA3
MMCSD0_
DATA0/
MMCSD0_
DATA1/
MMCSD0_
DATA2/
MMCSD0_
DATA3/
MMCSD1_
CLK/
GIO024
MMCSD1: Clock
GIO: GIO[024]
C15
A17
I/O/Z
I/O/Z
VDD
MMCSD1_
CMD/
GIO023
MMCSD1: Command
GIO: GIO[023]
VDD
MMCSD1_
DATA0/
GIO019/
UART2_T
XD
MMCSD1: DATA0
GIO: GIO[019]
UART2: Transmit data
A18
B15
A16
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
MMCSD1_
DATA1/
GIO020/
UART2_R
XD
MMCSD1: DATA1
GIO: GIO[020]
UART2: Receive data
MMCSD1_
DATA2/
GIO021/
UART2_C
TS
MMCSD1: DATA2
GIO: GIO[021]
UART2: CTS
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
28
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Table 2-12. MMC/SD Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
MMCSD1_
DATA3/
GIO022/
UART2_R
TS
MMCSD1: DATA3
GIO: GIO[022]
UART2: RTS
B16
I/O/Z
VDD
2.4.7 Universal Serial Bus (USB) Interface
The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-role
Host/Slave support. However, no charge pump is included.
NOTE
OTG supplies are not supported. Please ignore all references to OTG in this document.
Table 2-13. USB Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
USB D+ (differential signal pair).
When USB is not used, this signal should be connected to VSS_USB
USB_DP
A7
A I/O/Z
A I/O/Z
VDDA33_USB
VDDA33_USB
.
.
USB D- (differential signal pair).
When USB is not used, this signal should be connected to VSS_USB
USB_DM
USB_R1
A6
C7
USB reference current output
Connect to VSS_USB_REF via 10K ohm , 1% resistor placed as close to the
device as possible.
A I/O/Z
When USB is not used, this signal should be connected to VSS_USB
.
USB operating mode identification pin
For Device mode operation only, pull up this pin to VDD with a 1.5K ohm resistor.
For Host mode operation only, pull down this pin to ground (VSS) with a 1.5K
ohm resistor.
If using an OTG or mini-USB connector, this pin will be set properly via the
cable/connector configuration.
USB_ID
D5
E5
A I/O/Z
VDDA33_USB
When USB is not used, this signal should be connected to VSS_USB
.
For host or device mode operation, tie the VBUS/USB power signal to the USB
connector.
When used in OTG mode operation, tie VBUS to the external charge pump and
to the VBUS signal on the USB connector.
USB_VBUS
A I/O/Z
VDD
When the USB is not used, tie VBUS to Vss_USB.
Digital output to control external 5 V supply
When USB is not used, this signal should be left as a No Connect.
USB_DRVVBUS
VSS_USB_REF
C5
C8
O/Z
VDD
USB Ground Reference
Connect directly to ground and to USB_R1 via 10K ohm, 1% resistor placed as
close to the device as possible
GND
VDD
Analog 3.3 V power USBPHY
When USB is not used, this signal should be connected to VSS_USB
VDDA3P3_USB
VDDACM3P3_USB
VDDA1P2_USB
VDDD1P2_USB
J8
B6
H7
C6
PWR
PWR
PWR
PWR
VDD
VDD
VDD
VDD
.
.
.
.
Common mode 3.3 V power for USB PHY
When USB is not used, this signal should be connected to VSS_USB
Analog 1.2 V power for USB PHY
When USB is not used, this signal should be connected to VSS_USB
Digital 1.2 V power for USB PHY
When USB is not used, this signal should be connected to VSS_USB
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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2.4.8 Audio Interfaces
The DM355 includes two Audio Serial Ports (ASP ports), which are backward compatible with other TI
ASP serial ports and provide I2S audio interface. One interface is multiplexed with GIO signals.
Table 2-14. ASP Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
ASP0_CL
KR/
GIO26
ASP0: Receive Clock
GIO: GIO[026]
F17
I/O/Z
VDD
ASP0_CL
KX /
GIO029
ASP0: Transmit Clock
GIO: GIO[029]
F18
E18
H15
F16
G17
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
VDD
VDD
ASP0_DR
/
GIO027
ASP0: Receive DataF
GIO: GIO[027]
ASP0_DX
/
GIO030
ASP0: Transmit Data
GIO: GIO[030]
ASP0_FS
R /
GIO025
ASP0: Receive Frame Synch
GIO: GIO[025]
ASP0_FS
X /
ASP0: Transmit Frame SynchGIO: GIO[028]
GIO028
ASP1_CL
KR
D18
D17
D19
I/O/Z
I/Z
VDD
VDD
VDD
ASP1: Receive Clock
ASP1: Master Clock
ASP1: Transmit Clock
ASP1_CL
KS
ASP1_CL
KX
I/O/Z
ASP1_DR
ASP1_DX
C19
C18
I/O/Z
I/O/Z
VDD
VDD
ASP1: Receive Data
ASP1: Transmit Data
ASP1_FS
R
E17
E16
I/O/Z
I/O/Z
VDD
VDD
ASP1: Receive Frame Synch
ASP1: Transmit Frame Sync
ASP1_FS
X
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
2.4.9 UART Interface
The includes three UART ports. These ports are multiplexed with GIO and other signals.
Table 2-15. UART Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3) DESCRIPTION
NAME
NO.
U18
T18
UART0_RXD
UART0_TXD
I
VDD
VDD
UART0: Receive data. Used for UART boot mode
O
UART0: Transmit data. Used for UART boot mode
UART1_RXD
GIO013
UART1: Receive data.
GIO: GIO013
R15
R17
I/O/Z
I/O/Z
VDD
VDD
UART1_TXD
GIO012
UART1: Transmit data.
GIO: GIO012
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-15. UART Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3) DESCRIPTION
NAME
NO.
MMCSD1_DA
TA2/
GIO021
MMCSD1: DATA2
GIO: GIO021
UART2: CTS
A16
I/O/Z
VDD
VDD
VDD
VDD
UART2_CTS
MMCSD1_DA
TA3/
GIO022
MMCSD1: DATA3
GIO: GIO022
UART2: RTS
B16
B15
A18
I/O/Z
I/O/Z
I/O/Z
UART2_RTS
MMCSD1_DA
TA1/
GIO020
MMCSD1: DATA1
GIO: GIO020
UART2: RXD
UART2_RXD
MMCSD1_DA
TA0/
GIO019
MMCSD1: DATA0
GIO: GIO019
UART2: TXD
UART2_TXD
2.4.10 I2C Interface
The includes an I2C two-wire serial interface for control of external peripherals. This interface is
multiplexed with GIO signals.
Table 2-16. I2C Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
I2C_SDA/
GIO015
I2C: Serial data
GIO: GIO015
R13
I/O/Z
I/O/Z
VDD
VDD
I2C_SCL/
GIO014
I2C: Serial clock
GIO: GIO014
R14
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
2.4.11 Serial Interface
The includes three independent serial ports. These interfaces are multiplexed with GIO and other signals.
Table 2-17. SPI Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3) DESCRIPTION
NAME
NO.
SPI0_SCLK
C12
I/O/Z
I/O/Z
VDD
VDD
SPI0: Clock
SPI0_SDENA[0]/
GIO103
SPI0: Chip select 0
GIO: GIO[103]
B12
B12
GIO007
SPI0_SDENA[1]
GIO: GIO[007]
SPI0: Chip select 1
I/O/Z
VDD
SPI0_SDI/
GIO102
SPI0: Data in
GIO: GIO[102]
A12
B11
C13
I/O/Z
I/O/Z
I/O/Z
VDD
VDD
VDD
SPI0_SDO
SPI0: Data out
SPI1_SCLK/
GIO010
SPI1: Clock
GIO: GIO[010]
SPI1: Chip select 0
GIO: GIO[011] - Active low during MMC/SD boot (can be used as
MMC/SD power control)
SPI1_SDENA[0]/
GIO011
E13
I/O/Z
VDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-17. SPI Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3) DESCRIPTION
NAME
NO.
SPI1_SDI
GIO009
SPI1_SDENA[1]
SPI1: Data in or
SPI1: Chip select
GIO: GIO[09]
A13
I/O/Z
I/O/Z
VDD
SPI1_SDO
GIO008
SPI1: Data out
GIO: GIO[008]
E12
VDD
Standard CCD Analog Front End (AFE): Not used
•
•
YCC 16-bit: time multiplexed between chroma. CB/CR[07]
CIN7/
GIO101/
SPI2_SCLK
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[07]
PD
VDD_VIN
N3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
SPI: SPI2 clock
GIO: GIO[101]
Standard CCD Analog Front End (AFE): Raw[13]
•
•
YCC 16-bit: time multiplexed between chroma. CB/CR[05]
CIN5/
GIO099/
SPI2_SDENA[0]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[07]
PD
VDD_VIN
M3
SPI: SPI2 chip select
GIO: GIO[099]
Standard CCD Analog Front End (AFE): Raw[12]
•
•
YCC 16-bit: time multiplexed between chroma. CB/CR[04]
CIN4/
GIO098/
SPI2_SDI/
SPI2_SDENA[1]
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[04]
PD
VDD_VIN
L4
SPI: SPI2 Data in
GIO: GIO[0998]
Standard CCD Analog Front End (AFE): Not used
•
•
YCC 16-bit: time multiplexed between chroma. CB/CR[06]
CIN6/
GIO100/
SPI2_SDO/
YCC 8-bit (which allows for two simultaneous decoder inputs), it is
time multiplexed between luma and chroma of the upper channel.
Y/CB/CR[06]
PD
VDD_VIN
K5
SPI: SPI2 Data out
GIO: GIO[100]
2.4.12 Clock Interface
The provides interface with the system clocks.
Table 2-18. Clocks Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
CLKOUT1
/ GIO018
CLKOUT: Output Clock 1
GIO: GIO[018]
D12
I/O/Z
I/O/Z
VDD
VDD
CLKOUT2
/ GIO017
CLKOUT: Output Clock 2
GIO: GIO[017]
A11
CLKOUT3
/ GIO016
CLKOUT: Output Clock 3
GIO: GIO[016]
C11
A9
I/O/Z
VDD
VDD
VDD
MXI1
I
Crystal input for system oscillator (24 MHz or 36 MHz)
Output for system oscillator (24 MHz or 36 MHz). When the MX02 is not used,
the MX02 signal can be left open.
MXO1
B9
O
Crystal input for video oscillator (27 MHz) Optional, use only if 27MHz derived
from MXI1 and PLL does not provide sufficient performance for Video DAC.
When the MX12 is not used and powered down, the MXI2 signal should be left
as a No Connect
MXI2
R1
I
VDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-18. Clocks Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Output for video oscillator (27 MHz) Optional, use only if 27MHz derived from
MXI1 and PLL does not provide sufficient performance for Video DAC When the
MXO2 is not used and powered down, the MXO2 signal should be left as a No
Connect.
MXO2
T1
O
VDD
2.4.13 Real Time Output (RTO) Interface
The provides Real Time Output (RTO) interface.
Table 2-19. RTO Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
COUT5-
G2 /
Digital Video Out: VENC settings determine function GIO: GIO[079]
GIO079 /
PWM2A /
RTO0
C1
I/O/Z
VDD_VOUT
PWM2A
RTO0
COUT4-
B7 /
Digital Video Out: VENC settings determine function GIO: GIO[078]
GIO078 /
PWM2B /
RTO1
D3
E3
E4
I/O/Z
I/O/Z
I/O/Z
VDD_VOUT
VDD_VOUT
VDD_VOUT
PWM2B
RTO1
COUT3-
B6 /
GIO077 /
PWM2C /
RTO2
Digital Video Out: VENC settings determine function GIO: GIO[077]
PWM2C
RTO2
COUT2-
B5 /
GIO076 /
PWM2D /
RTO3
Digital Video Out: VENC settings determine function GIO: GIO[076]
PWM2D
RTO3
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
2.4.14 Pulse Width Modulator (PWM) Interface
The provides Pulse Width Modulator (PWM) interface.
Table 2-20. PWM Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
COUT7-
G4 /
GIO081 /
PWM0
Digital Video Out: VENC settings determine function GIO: GIO[081]
PWM0
C2
I/O/Z
VDD_VOUT
COUT6-
G3 /
GIO080 /
PWM1
Digital Video Out: VENC settings determine function GIO: GIO[080]
PWM1
D2
I/O/Z
VDD_VOUT
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-20. PWM Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
COUT5-
G2 /
Digital Video Out: VENC settings determine function GIO: GIO[079]
GIO079 /
PWM2A /
RTO0
C1
I/O/Z
VDD_VOUT
PWM2A
RTO0
COUT4-
B7 /
Digital Video Out: VENC settings determine function GIO: GIO[078]
GIO078 /
PWM2B /
RTO1
D3
E3
E4
I/O/Z
I/O/Z
I/O/Z
VDD_VOUT
VDD_VOUT
VDD_VOUT
PWM2B
RTO1
COUT3-
B6 /
GIO077 /
PWM2C /
RTO2
Digital Video Out: VENC settings determine function GIO: GIO[077]
PWM2C
RTO2
COUT2-
B5 /
GIO076 /
PWM2D /
RTO3
Digital Video Out: VENC settings determine function GIO: GIO[076]
PWM2D
RTO3
COUT1-
B4 /
GIO075 /
PWM3A
Digital Video Out: VENC settings determine function GIO: GIO[075]
PWM3A
F3
F4
H4
G3
I/O/Z
I/O/Z
I/O/Z
I/O/Z
VDD_VOUT
VDD_VOUT
VDD_VOUT
COUT0-
B3 /
GIO074 /
PWM3B
Digital Video Out: VENC settings determine function GIO: GIO[074]
PWM3B
FIELD /
GIO070 /
R2 /
Video Encoder: Field identifier for interlaced display formats GIO: GIO[070]
Digital Video Out: R2
PWM3C
PWM3C
EXTCLK /
GIO069 /
B2 /
Video Encoder: External clock input, used if clock rates > 27 MHz are needed,
e.g. 74.25 MHz for HDTV digital output GIO: GIO[069] Digital Video Out: B2
PWM3D
PD
VDD_VOUT
PWM3D
2.4.15 System Configuration Interface
The provides interfaces for system configuration and boot load.
Table 2-21. System/Boot Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Address bus bit 13
GIO: GIO[067]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method. Used
to drive boot status LED signal (active low) in ROM boot modes.
EM_A13/
GOP067/
BTSEL[1]
PD
VDD
V19
I/O/Z
EM_A12/
GOP066/
BTSEL[0]
Async EMIF: Address bus bit 12
GIO: GIO[066]
System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
PD
VDD
U19
R16
I/O/Z
I/O/Z
Async EMIF: Address bus bit 11
GIO: GIO[065]
System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
AECFG[3] sets default fo PinMux2.EM_D15_8. AEMIF default bus width (16 or 8
bits).
EM_A11/
GOP065/
AECFG[3]
PU
VDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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Table 2-21. System/Boot Terminal Functions (continued)
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
Async EMIF: Address bus bit 10
EM_A10/
GOP064/
AECFG[2]
GIO: GIO[064]
PU
VDD
R18
I/O/Z
System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition:
(EM,_BA0, EM_A14, GOP[054], rsvd)
Async EMIF: Address bus bit 09
EM_A09/
GOP063/
AECFG[1]
GIO: GIO[063]
PD
VDD
P17
T19
I/O/Z
I/O/Z
System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition:
(EM,_BA0, EM_A14, GOP[054], rsvd)
Async EMIF: Address bus bit 08
GIO: GIO[062]
System: AECFG[0] sets default for:
EM_A08/
GOP062/
AECFG[0]
PD
VDD
•
•
PinMux2.EM_A0_BA1 - AEMIF address width (OneNAND, or NAND)
PinMux2.EM_A13_3 - AEMIF address width (OneNAND, or NAND)
2.4.16 Emulation
The emulation interface allow software and hardware debugging.
Table 2-22. Emulation Terminal Functions
TERMINAL
TYPE(1)
OTHER(2)(3)
DESCRIPTION
NAME
NO.
TCK
E10
I
I
VDD
JTAG test clock input
JTAG test data input
JTAG test data output
JTAG test mode select
PU
VDD
TDI
D9
E9
D8
TDO
TMS
O
I
VDD
PU
VDD
PD
VDD
TRST
RTCK
C9
I
JTAG test logic reset (active low)
JTAG test clock output
E11
O
VDD
JTAG emulation 0 I/O
EMU[1:0] = 00 - Force Debug Scan chain (ARM and ARM ETB TAPs connected)
EMU[1:0] = 11 - Normal Scan chain (ICEpick only)
PU
VDD
EMU0
EMU1
E8
E7
I/O/Z
I/O/Z
JTAG emulation 1 I/O
EMU[1:0] = 00 - Force Debug Scan chain (ARM and ARM ETB TAPs connected)
EMU[1:0] = 11 - Normal Scan chain (ICEpick only)
PU
VDD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
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2.5 Pin List
Table 2-23 provides a complete pin description list in pin number order.
Table 2-23. DM355 Pin Descriptions
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
CIN7 / GIO101
/ SPI2_SCLK
1
N3
I/O CCDC
/ GIO /
VDD_VIN
PD
in
Standard CCD Analog Front End (AFE): PINMUX0[1:0].CIN
NOT USED
_7
SPI2
YCC 16-bit: time multiplexed between
chroma: CB/CR[07]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between
luma and chroma of the upper channel.
Y/CB/CR[07]
SPI: SPI2 Clock
GIO: GIO[101]
CIN6 / GIO100
/ SPI2_SDO
2
K5
I/O CCDC
/ GIO /
VDD_VIN
PD
in
Standard CCD Analog Front End (AFE): PINMUX0[3:2].CIN
NOT USED
_6
SPI2
YCC 16-bit: time multiplexed between
chroma: CB/CR[06]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[06]
SPI: SPI2 Data Out
GIO: GIO[100]
CIN5 / GIO099
/
3
M3
I/O CCDC
/ GIO /
VDD_VIN
PD
in
Standard CCD Analog Front End (AFE): PINMUX0[5:4].CIN
raw[13]
_5
SPI2_SDENA[
0]
SPI2
YCC 16-bit: time multiplexed between
chroma: CB/CR[05]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[05]
SPI: SPI2 Chip Select
GIO: GIO[99]
CIN4 / GIO098
/ SPI2_SDI /
SPI2_SDENA[
1]
4
L4
I/O CCDC
/ GIO /
VDD_VIN
PD
in
Standard CCD Analog Front End (AFE): PINMUX0[7:6].CIN
raw[12]
_4
SPI2 /
SPI2
YCC 16-bit: time multiplexed between
chroma: CB/CR[04]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[04]
SPI: SPI2 Data In
GIO: GIO[098]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3, Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩ resistor should be used.)
(4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ω to 50 Ω damping resistors are recommend on the
following outputs placed near the DM355: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths
should be minimized.
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Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
CIN3 / GIO097
5
6
7
8
9
J4
I/O CCDC
/ GIO
VDD_VIN
VDD_VIN
VDD_VIN
VDD_VIN
VDD_VIN
VDD_VIN
PD
PD
PD
PD
PD
PD
in
in
in
in
in
in
Standard CCD Analog Front End (AFE): PINMUX0[8].CIN_
raw[11]
32
YCC 16-bit: time multiplexed between
chroma: CB/CR[03]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[03]
GIO: GIO[097]
CIN2 / GIO096
CIN1 / GIO095
CIN0 / GIO094
YIN7 / GIO093
J5
L3
J3
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[8].CIN_
raw[10]
32
YCC 16-bit: time multiplexed between
chroma: CB/CR[02]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[02]
GIO: GIO[096]
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[9].CIN_
raw[09]
10
YCC 16-bit: time multiplexed between
chroma: CB/CR[01]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[01]
GIO: GIO[095]
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[9].CIN_
raw[08]
10
YCC 16-bit: time multiplexed between
chroma: CB/CR[00]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the upper channel. Y/CB/CR[00]
GIO: GIO[094]
L5
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[07]
_70
YCC 16-bit: time multiplexed between
luma: Y[07]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[07]
GIO: GIO[093]
YIN6 / GIO092 10
M4
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[06]
_70
YCC 16-bit: time multiplexed between
luma: Y[06]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[06]
GIO: GIO[092]
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Device Overview
37
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
YIN5 / GIO091 11
YIN4 / GIO090 12
YIN3 / GIO089 13
YIN2 / GIO088 14
YIN1 / GIO087 15
YIN0 / GIO086 16
M5
I/O CCDC
/ GIO
VDD_VIN
VDD_VIN
VDD_VIN
VDD_VIN
VDD_VIN
VDD_VIN
PD
PD
PD
PD
PD
PD
in
in
in
in
in
in
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[05]
_70
YCC 16-bit: time multiplexed between
luma: Y[05]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[05]
GIO: GIO[091]
P3
R3
P4
P2
P5
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[04]
_70
YCC 16-bit: time multiplexed between
luma: Y[04]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[04]
GIO: GIO[090]
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[03]
_70
YCC 16-bit: time multiplexed between
luma: Y[03]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[03]
GIO: GIO[089]
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[02]
_70
YCC 16-bit: time multiplexed between
luma: Y[02]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[02]
GIO: GIO[088]
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[01]
_70
YCC 16-bit: time multiplexed between
luma: Y[01]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[01]
GIO: GIO[087]
I/O CCDC
/ GIO
Standard CCD Analog Front End (AFE): PINMUX0[10].YIN
raw[00]
_70
YCC 16-bit: time multiplexed between
luma: Y[00]
YCC 08-bit (which allows for 2
simultaneous decoder inputs), it is time
multiplexed between luma and chroma of
the lower channel. Y/CB/CR[00]
GIO: GIO[086]
38
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
CAM_HD /
GIO085
17
18
19
N5
I/O CCDC
/ GIO
VDD_VIN
VDD_VIN
VDD_VIN
PD
PD
PD
in
in
in
Horizontal synchronization signal that can PINMUX0[11].CA
be either an input (slave mode) or an
output (master mode). Tells the CCDC
when a new line starts.
M_HD
GIO: GIO[085]
CAM_VD /
GIO084
R4
R5
I/O CCDC
/ GIO
Vertical synchronization signal that can
be either an input (slave mode) or an
output (master mode). Tells the CCDC
when a new frame starts.
PINMUX0[12].CA
M_VD
GIO: GIO[084]
CAM_WEN_FI
ELD / GIO083
I/O CCDC
/ GIO
Write enable input signal is used by
external device (AFE/TG) to gate the
DDR output of the CCDC module.
PINMUX0[13].CA
M_WEN
Alternately, the field identification input
signal is used by external device
plus
(AFE/TG) to indicate the which of two
frames is input to the CCDC module for
sensors with interlaced output. CCDC
handles 1- or 2-field sensors in hardware.
GIO: GIO[083]
CCDC.MODE[7].C
CDMD &
CCDC.MODE[5].S
WEN
PCLK /
GIO082
20
T3
I/O CCDC
/ GIO
VDD_VIN
PD
in
Pixel clock input (strobe for lines CI7
through YI0)
PINMUX0[14].PCL
K
GIO: GIO[082]
DP
21
22
23
24
25
26
J1
K1
L1
DN
SP
SN
M1
N2
M2
LVIREF
VDDA18V_CC
P2
VSSA_CCP2
27
28
29
K2
YOUT7-R7
YOUT6-R6
YOUT5-R5
YOUT4-R4
YOUT3-R3
YOUT2-G7
YOUT1-G6
YOUT0-G5
C3
A4
B4
B3
B2
A3
A2
B1
I/O VENC
I/O VENC
I/O VENC
I/O VENC
I/O VENC
I/O VENC
I/O VENC
I/O VENC
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
in
in
in
in
in
in
in
in
Digital Video Out: VENC settings
determine function(4)
30
31
32
33
34
35
36
Digital Video Out: VENC settings
determine function(4)
Digital Video Out: VENC settings
determine function(4)
Digital Video Out: VENC settings
determine function(4)
Digital Video Out: VENC settings
determine function(4)
Digital Video Out: VENC settings
determine function(4)
Digital Video Out: VENC settings
determine function(4)
Digital Video Out: VENC settings
determine function(4)
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Device Overview
39
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
COUT7-G4 /
GIO081 /
PWM0
37
38
39
C2
I/O VENC
/ GIO /
PWM
VDD_VOUT
VDD_VOUT
VDD_VOUT
in
in
in
Digital Video Out: VENC settings
determine function
PINMUX1[1:0].CO
UT_7
0
GIO: GIO[081]
PWM0
COUT6-G3 /
GIO080 /
PWM1
D2
C1
I/O VENC
/ GIO /
PWM
Digital Video Out: VENC settings
determine function
PINMUX1[3:2].CO
UT_6
1
GIO: GIO[080]
PWM1(4)
COUT5-G2 /
GIO079 /
PWM2A /
RTO0
I/O VENC
/ GIO /
PWM
Digital Video Out: VENC settings
determine function
PINMUX1[5:4].CO
UT_5
2 /
RTO
GIO: GIO[079]
PWM2A
RTO0(4)
COUT4-B7 /
GIO078 /
PWM2B /
RTO1
40
41
42
43
D3
E3
E4
F3
I/O VENC
/ GIO /
PWM
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
in
in
in
in
Digital Video Out: VENC settings
determine function
PINMUX1[7:6].CO
UT_4
2 /
RTO
GIO: GIO[078]
PWM2B
RTO1(4)
COUT3-B6 /
GIO077 /
PWM2C /
RTO2
I/O VENC
/ GIO /
PWM
Digital Video Out: VENC settings
determine function
PINMUX1[9:8].CO
UT_3
2 /
RTO
GIO: GIO[077]
PWM2C
RTO2(4)
COUT2-B5 /
GIO076 /
PWM2D /
RTO3
I/O VENC
/ GIO /
PWM
Digital Video Out: VENC settings
determine function
PINMUX1[11:10].C
OUT_2
2 /
RTO
GIO: GIO[076]
PWM2D
RTO3(4)
COUT1-B4 /
GIO075 /
PWM3A
I/O VENC
/ GIO /
PWM
Digital Video Out: VENC settings
determine function
PINMUX1[13:12].C
OUT_1
3
GIO: GIO[075]
PWM3A(4)
40
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
COUT0-B3 /
GIO074 /
PWM3B
44
F4
I/O VENC
/ GIO /
PWM
VDD_VOUT
in
Digital Video Out: VENC settings
determine function
PINMUX1[15:14].C
OUT_0
3
GIO: GIO[074]
PWM3B(4)
HSYNC /
GIO073
45
46
47
48
F5
G5
H5
H4
I/O VENC
/ GIO
VDD_VOUT
VDD_VOUT
VDD_VOUT
VDD_VOUT
PD
PD
in
in
in
in
Video Encoder: Horizontal Sync
PINMUX1[16].HVS
YNC
GIO: GIO[073](4)
VSYNC /
GIO072
I/O VENC
/ GIO
Video Encoder: Vertical Sync
PINMUX1[16].HVS
YNC
GIO: GIO[072](4)
VVALID /
GIO071
I/O VENC
/ GIO
Video Encoder: LCD Output Enable or
BRIGHT signal
GIO: GIO[071](4)
PINMUX1[17].DLC
D
FIELD /
GIO070 / R2 /
PWM3C
I/O VENC
Video Encoder: Field identifier for
interlaced display formats
PINMUX1[19:18].F
IELD
/ GIO /
VENC
/
PWM
3
GIO: GIO[070]
Digital Video Out: R2
PWM3C(4)
EXTCLK /
GIO069 / B2 /
PWM3D
49
G3
I/O VENC
VDD_VOUT
PD
in
Video Encoder: External clock input,
used if clock rates > 27 MHz are needed, XTCLK
e.g. 74.25 MHz for HDTV digital output
PINMUX1[21:20].E
/ GIO /
VENC
/
PWM
3
GIO: GIO[069]
Digital Video Out: B2
PWM3D(4)
VCLK /
GIO068
50
H3
I/O VENC
/ GIO
VDD_VOUT
out L Video Encoder: Video Output Clock
PINMUX1[22].VCL
K
GIO: GIO[068](4)
VREF
IOUT
IBIAS
51
52
53
J7
E1
F2
A I/O Video
DAC
Video DAC: Reference voltage output
(0.45V, 0.1uF to GND)
A I/O Video
DAC
Video DAC: Pre video buffer DAC output
(1000 ohm to VFB)
A I/O Video
DAC
Video DAC: External resistor (2550
Ohms to GND) connection for current
bias configuration
VFB
54
55
G1
F1
A I/O Video
DAC
Video DAC: Pre video buffer DAC output
(1000 ohm to IOUT, 1070 ohm to
TVOUT)
TVOUT
A I/O Video VDDA18_DAC
DAC
Video DAC: Analog Composite
NTSC/PAL output (SeeFigure 5-31
andFigure 5-32 for circuit connection)
VDDA18V_DAC
VSSA_DAC
56
57
58
L7
L8
PWR Video
DAC
Video DAC: Analog 1.8V power
Video DAC: Analog 1.8V ground
out L DDR Data Clock
GND Video
DAC
DDR_CLK
W9
I/O DDR
VDD_DDR
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Device Overview
41
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
DDR_CLK
DDR_RAS
DDR_CAS
DDR_WE
59
60
61
62
63
64
65
W8
T6
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
out H DDR Complementary Data Clock
out H DDR Row Address Strobe
out H DDR Column Address Strobe
out H DDR Write Enable (active low)
out H DDR Chip Select (active low)
out L DDR Clock Enable
V9
W10
T8
DDR_CS
DDR_CKE
DDR_DQM[1]
V10
U15
out L Data mask outputs: DQM0: For
DDR_DQ[7:0]
DDR_DQM[0]
DDR_DQS[1]
66
67
T12
V15
I/O DDR
I/O DDR
VDD_DDR
VDD_DDR
out L Data mask outputs: DQM1: For
DDR_DQ[15:8]
in
Data strobe input/outputs for each byte of
the 16 bit data bus used to synchronize
the data transfers. Output to DDR when
writing and inputs when reading.
DQS1: For DDR_DQ[15:8]
DDR_DQS[0]
68
V12
I/O DDR
VDD_DDR
in
Data strobe input/outputs for each byte of
the 16 bit data bus used to synchronize
the data transfers. Output to DDR when
writing and inputs when reading.
DQS0: For DDR_DQ[7:0]
DDR_BA[2]
DDR_BA[1]
DDR_BA[0]
69
70
71
V8
U7
U8
I/O DDR
I/O DDR
I/O DDR
VDD_DDR
VDD_DDR
VDD_DDR
out L Bank select outputs. Two are required for
1Gb DDR2 memories.
out L Bank select outputs. Two are required for
1Gb DDR2 memories.
out L Bank select outputs. Two are required for
1Gb DDR2 memories.
DDR_A13
DDR_A12
DDR_A11
DDR_A10
DDR_A09
DDR_A08
DDR_A07
DDR_A06
DDR_A05
DDR_A04
DDR_A03
DDR_A02
DDR_A01
DDR_A00
DDR_DQ15
DDR_DQ14
DDR_DQ13
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ09
DDR_DQ08
DDR_DQ07
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
U6
V7
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
out L DDR Address Bus bit 13
out L DDR Address Bus bit 12
out L DDR Address Bus bit 11
out L DDR Address Bus bit 10
out L DDR Address Bus bit 09
out L DDR Address Bus bit 08
out L DDR Address Bus bit 07
out L DDR Address Bus bit 06
out L DDR Address Bus bit 05
out L DDR Address Bus bit 04
out L DDR Address Bus bit 03
out L DDR Address Bus bit 02
out L DDR Address Bus bit 01
out L DDR Address Bus bit 00
W7
V6
W6
W5
V5
U5
W4
V4
W3
W2
V3
V2
W17
V16
W16
U16
W15
W14
V14
U13
W13
in
in
in
in
in
in
in
in
in
DDR Data Bus bit 15
DDR Data Bus bit 14
DDR Data Bus bit 13
DDR Data Bus bit 12
DDR Data Bus bit 11
DDR Data Bus bit 10
DDR Data Bus bit 09
DDR Data Bus bit 08
DDR Data Bus bit 07
42
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
DDR_DQ06
95
96
V13
W12
U12
T11
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
I/O DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
in
in
in
in
in
in
in
DDR Data Bus bit 06
DDR_DQ05
DDR_DQ04
DDR_DQ03
DDR_DQ02
DDR_DQ01
DDR_DQ00
DDR_GATE0
DDR Data Bus bit 05
DDR Data Bus bit 04
DDR Data Bus bit 03
DDR Data Bus bit 02
DDR Data Bus bit 01
DDR Data Bus bit 00
97
98
99
U11
W11
V11
W18
100
101
102
DDR: Loopback signal for external DQS
gating. Route to DDR and back to
DDR_STRBEN_DEL with same
constraints as used for DDR clock and
data.
DDR_GATE1
DDR_VREF
103
104
V17
I/O DDR
VDD_DDR
DDR: Loopback signal for external DQS
gating. Route to DDR and back to
DDR_STRBEN with same constraints as
used for DDR clock and data.
U10 PWR DDRI
O
VDD_DDR
VDD_DDR
VDD_DDR
VDD_DDR
DDR: Voltage input for the SSTL_18 IO
buffers
DDR_VSSDLL 105
DDR_VDDDLL 106
R11 GND DDRD
LL
DDR: Ground for the DDR DLL
R10 PWR DDRD
LL
DDR: Power (3.3 Volts) for the DDR DLL
DDR_ZN
107
T9
I/O DDRI
O
DDR: Reference output for drive strength
calibration of N and P channel outputs.
Tie to ground via 50 ohm resistor @
0.5% tolerance.
EM_A13 /
GIO067 /
BTSEL[1]
108
V19
I/O AEMI
F /
VDD
PD
in L Async EMIF: Address Bus bit[13]
PINMUX2[0].EM_A
13_3,
GIO /
syste
m
GIO: GIO[067]
default set by
AECFG[0]
System: BTSEL[1:0] sampled at
Power-on-Reset to determine Boot
method (00:NAND, 01:Flash, 10:UART,
11:SD)
EM_A12 /
GIO066 /
BTSEL[0]
109
U19
I/O AEMI
F /
VDD
PD
in L Async EMIF: Address Bus bit[12]
PINMUX2[0].EM_A
13_3,
GIO /
syste
m
GIO: GIO[066]
default set by
AECFG[0]
System: BTSEL[1:0] sampled at
Power-on-Reset to determine Boot
method (00:NAND, 01:Flash, 10:UART,
11:SD)
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Device Overview
43
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
EM_A11 /
GIO065 /
AECFG[3]
110
R16
I/O AEMI
F /
VDD
PU
in H Async EMIF: Address Bus bit[11]
PINMUX2[0].EM_A
13_3,
GIO /
syste
m
GIO: GIO[065]
default set by
AECFG[0]
System: AECFG[3:0] sampled at
Power-on-Reset to set AEMIF
Configuration
AECFG[3] sets default for
PinMux2.EM_D15_8: AEMIF Default Bus
Width (0:16 or 1:8 bits)
EM_A10 /
GIO064 /
AECFG[2]
111
R18
P17
T19
I/O AEMI
F /
VDD
PU
in H Async EMIF: Address Bus bit[10]
PINMUX2[0].EM_A
13_3,
GIO /
syste
m
GIO: GIO[064]
default set by
AECFG[0]
System: AECFG[3:0] sampled at
Power-on-Reset to set AEMIF
Configuration
AECFG[2:1] sets default for
PinMux2.EM_BA0: AEMIF EM_BA0
Definition (00: EM_BA0, 01: EM_A14,
10:GIO[054], 11:rsvd)
EM_A09 /
GIO063 /
AECFG[1]
112
I/O AEMI
F /
VDD
PD
in L Async EMIF: Address Bus bit[09]
PINMUX2[0].EM_A
13_3,
GIO /
syste
m
GIO: GIO[063]
default set by
AECFG[0]
System: AECFG[3:0] sampled at
Power-on-Reset to set AEMIF
Configuration
AECFG[2:1] sets default for
PinMux2.EM_BA0: AEMIF EM_BA0
Definition (00: EM_BA0, 01: EM_A14,
10:GIO[054], 11:rsvd)
EM_A08 /
GIO062 /
AECFG[0]
113
I/O AEMI
F /
VDD
PU
in H Async EMIF: Address Bus bit[08]
PINMUX2[0].EM_A
13_3,
GIO /
syste
m
GIO: GIO[062]
default set by
AECFG[0]
AECFG[0] sets default for
- PinMux2.EM_A0_BA1: AEMIF Address
Width (OneNAND or NAND)
- PinMux2.EM_A13_3: AEMIF Address
Width (OneNAND or NAND)
(0:AEMIF address bits, 1:GIO[67:57])
44
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
EM_A07 /
GIO061
114
P16
I/O AEMI
F /
VDD
out L Async EMIF: Address Bus bit[07]
GIO: GIO[061] - Used by ROM
PINMUX2[0].EM_A
13_3,
GIO
default set by
Bootloader to provide progress status via AECFG[0]
LED (active low)
EM_A06 /
GIO060
115
116
117
118
P18
R19
P15
N18
I/O AEMI
F /
VDD
VDD
VDD
VDD
out L Async EMIF: Address Bus bit[06]
PINMUX2[0].EM_A
13_3,
GIO
GIO: GIO[060]
default set by
AECFG[0]
EM_A05 /
GIO059
I/O AEMI
F /
out L Async EMIF: Address Bus bit[05]
PINMUX2[0].EM_A
13_3,
GIO
GIO: GIO[059]
default set by
AECFG[0]
EM_A04 /
GIO058
I/O AEMI
F /
out L Async EMIF: Address Bus bit[04]
PINMUX2[0].EM_A
13_3,
GIO
GIO: GIO[058]
default set by
AECFG[0]
EM_A03 /
GIO057
I/O AEMI
F /
out L Async EMIF: Address Bus bit[03]
PINMUX2[0].EM_A
13_3,
GIO
GIO: GIO[057]
default set by
AECFG[0]
EM_A02
EM_A01
119
120
121
N15
N17
M16
I/O AEMI
F
VDD
VDD
VDD
out L Async EMIF: Address Bus bit[02]
NAND/SM/xD: CLE - Command Latch
Enable output
I/O AEMI
F
out L Async EMIF: Address Bus bit[01]
NAND/SM/xD: ALE - Address Latch
Enable output
EM_A00 /
GIO056
I/O AEMI
F /
out L Async EMIF: Address Bus bit[00] Note
that the EM_A0 is always a 32-bit
address
PINMUX2[1].EM_A
0_BA1,
GIO
GIO: GIO[056]
default set by
AECFG[0]
EM_BA1 /
GIO055
122
123
P19
I/O AEMI
F /
VDD
out H Async EMIF: Bank Address 1 signal =
16-bit address.
PINMUX2[1].EM_A
0_BA1,
GIO
In 16-bit mode, lowest address bit.
default set by
AECFG[0]
In 8-bit mode, second lowest address bit
GIO: GIO[055]
EM_BA0 /
GIO054 /
EM_A14
N19
I/O AEMI
F /
VDD
out H Async EMIF: Bank Address 0 signal =
8-bit address.
PINMUX2[3:2].EM
_BA0,
GIO /
EMIF2
.30
In 8-bit mode, lowest address bit.
default set by
AECFG[2:1]
Or, can be used as an extra Address line
(bit[14] when using 16-bit memories.
GIO: GIO[054]
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45
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
EM_D15 /
GIO053
124
125
126
127
128
129
130
131
M18
I/O AEMI
F /
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
in
in
in
in
in
in
in
in
Async EMIF: Data Bus bit[15]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[053]
default set by
AECFG[3]
EM_D14 /
GIO052
M19
M15
L18
L17
L19
K18
L16
I/O AEMI
F /
Async EMIF: Data Bus bit[14]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[052]
default set by
AECFG[3]
EM_D13 /
GIO051
I/O AEMI
F /
Async EMIF: Data Bus bit[13]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[051]
default set by
AECFG[3]
EM_D12 /
GIO050
I/O AEMI
F /
Async EMIF: Data Bus bit[12]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[050]
default set by
AECFG[3]
EM_D11 /
GIO049
I/O AEMI
F /
Async EMIF: Data Bus bit[11]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[049]
default set by
AECFG[3]
EM_D10 /
GIO048
I/O AEMI
F /
Async EMIF: Data Bus bit[10]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[048]
default set by
AECFG[3]
EM_D09 /
GIO047
I/O AEMI
F /
Async EMIF: Data Bus bit[09]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[047]
default set by
AECFG[3]
EM_D08 /
GIO046
I/O AEMI
F /
Async EMIF: Data Bus bit[08]
PINMUX2[4].EM_
D15_8,
GIO
GIO: GIO[046]
default set by
AECFG[3]
EM_D07 /
GIO045
132
133
134
135
K19
K17
J19
L15
I/O AEMI
F /
VDD
VDD
VDD
VDD
in
in
in
in
Async EMIF: Data Bus bit[07]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[045]
EM_D06 /
GIO044
I/O AEMI
F /
Async EMIF: Data Bus bit[06]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[044]
EM_D05 /
GIO043
I/O AEMI
F /
Async EMIF: Data Bus bit[05]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[043]
EM_D04 /
GIO042
I/O AEMI
F /
Async EMIF: Data Bus bit[04]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[042]
46
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
EM_D03 /
GIO041
136
137
138
139
140
J18
I/O AEMI
F /
VDD
VDD
VDD
VDD
VDD
in
in
in
in
Async EMIF: Data Bus bit[03]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[041]
EM_D02 /
GIO040
H19
J17
H18
J16
I/O AEMI
F /
Async EMIF: Data Bus bit[02]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[040]
EM_D01 /
GIO039
I/O AEMI
F /
Async EMIF: Data Bus bit[01]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[039]
EM_D00 /
GIO038
I/O AEMI
F /
Async EMIF: Data Bus bit[00]
PINMUX2[5].EM_
D7_0
GIO
GIO: GIO[038]
EM_CE0 /
GIO037
I/O AEMI
F /
out H Async EMIF: Lowest numbered Chip
Select. Can be programmed to be used
for standard asynchronous memories
(example:flash), OneNand or NAND
memory. Used for the default boot and
ROM boot modes.
PINMUX2[6].EM_
CE0
GIO
GIO: GIO[037]
EM_CE1 /
GIO036
141
142
G19
J15
I/O AEMI
F /
VDD
out H Async EMIF: Second Chip Select., Can
be programmed to be used for standard
asynchronous memories (example:
PINMUX2[7].EM_
CE1
GIO
flash), OneNand or NAND memory.
GIO: GIO[036]
EM_WE /
GIO035
I/O AEMI
F /
VDD
out H Async EMIF: Write Enable
PINMUX2[8].EM_
WE_OE
GIO
NAND/SM/xD: WE (Write Enable) output
GIO: GIO[035]
EM_OE /
GIO034
143
144
F19
G18
I/O AEMI
F /
VDD
out H Async EMIF: Output Enable
PINMUX2[8].EM_
WE_OE
GIO
NAND/SM/xD: RE (Read Enable) output
GIO: GIO[034]
EM_WAIT /
GIO033
I/O AEMI
F /
VDD
PU
PD
in H Async EMIF: Async WAIT
PINMUX2[9].EM_
WAIT
GIO
NAND/SM/xD: RDY/_BSY input
GIO: GIO[033]
EM_AVD /
GIO032
145
146
147
H16
E19
H15
I/O AEMI
F /
VDD
VDD
VDD
in L OneNAND: Address Valid Detect for
OneNAND interface
PINMUX2[10].EM_
AVD
GIO
GIO: GIO[032]
EM_CLK /
GIO031
I/O AEMI
F /
out L OneNAND: Clock signal for OneNAND
flash interface
PINMUX2[11].EM_
CLK
GIO
GIO: GIO[031]
ASP0_DX /
GIO030
I/O ASP5
120 /
in
ASP0: Transmit Data
PINMUX3[0].GIO3
0
GIO
GIO: GIO[030]
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Device Overview
47
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
ASP0_CLKX /
GIO029
148
149
150
F18
I/O ASP5
120 /
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
in
in
in
in
in
in
in
in
ASP0: Transmit Clock
PINMUX3[1].GIO2
9
GIO
GIO: GIO[029]
ASP0_FSX /
GIO028
G17
E18
F17
F16
C15
A17
B16
I/O ASP5
120 /
ASP0: Transmit Frame Synch
PINMUX3[2].GIO2
8
GIO
GIO: GIO[028]
ASP0_DR /
GIO027
I/O ASP5
120 /
ASP0: Receive Data
PINMUX3[3].GIO2
7
GIO
GIO: GIO[027]
ASP0_CLKR / 151
GIO026
I/O ASP5
120 /
ASP0: Receive Clock
PINMUX3[4].GIO2
6
GIO
GIO: GIO[026]
ASP0_FSR /
GIO025
152
153
I/O ASP5
120 /
ASP0: Receive Frame Synch
PINMUX3[5].GIO2
5
GIO
GIO: GIO[025]
MMCSD1_CL
K / GIO024
I/O MMC
SD /
MMCSD1: Clock
PINMUX3[6].GIO2
4
GIO
GIO: GIO[024]
MMCSD1_CM 154
D / GIO023
I/O MMC
SD /
MMCSD1: Command
PINMUX3[7].GIO2
3
GIO
GIO: GIO[023]
MMCSD1_DA
TA3 / GIO022
/ UART2_RTS
155
156
157
I/O MMC
SD /
MMCSD1: DATA3
PINMUX3[9:8].GIO
22
GIO /
UART
2
GIO: GIO[022]
UART2: RTS
MMCSD1_DA
TA2 / GIO021
/ UART2_CTS
A16
B15
I/O MMC
SD /
VDD
in
in
MMCSD1: DATA2
PINMUX3[11:10].G
IO21
GIO /
UART
2
GIO: GIO[021]
UART2: CTS
MMCSD1_DA
TA1 / GIO020
/ UART2_RXD
I/O MMC
SD /
VDD
MMCSD1: DATA1
PINMUX3[13:12].G
IO20
GIO /
UART
2
GIO: GIO[020]
UART2: Receive Data
48
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
MMCSD1_DA
TA0 / GIO019
/ UART2_TXD
158
A18
I/O MMC
SD /
VDD
in
MMCSD1: DATA0
PINMUX3[15:14].G
IO19
GIO /
UART
2
GIO: GIO[019]
UART2: Transmit Data
CLKOUT: Output Clock 1
CLKOUT1 /
GIO018
159
160
161
D12
A11
C11
I/O Clock
VDD
VDD
VDD
in
in
in
PINMUX3[16].GIO
18
s /
GIO
GIO: GIO[018]
CLKOUT2 /
GIO017
I/O Clock
CLKOUT: Output Clock 2
PINMUX3[17].GIO
17
s /
GIO
GIO: GIO[017]
CLKOUT3 /
GIO016
I/O Clock
CLKOUT: Output Clock 3
PINMUX3[18].GIO
16
s /
GIO
GIO: GIO[016]
I2C: Serial Data
I2C_SDA /
GIO015
162
163
R13
R14
R15
I/O I2C /
GIO
VDD
VDD
VDD
in
in
in
PINMUX3[19].GIO
15
GIO: GIO[015]
I2C_SCL /
GIO014
I/O I2C /
GIO
I2C: Serial Clock
PINMUX3[20].GIO
14
GIO: GIO[014]
UART1_RXD / 164
GIO013
I/O UART
UART1: Receive Data
PINMUX3[21].GIO
13
1 /
GIO
GIO: GIO[013]
UART1_TXD / 165
GIO012
R17
I/O UART
VDD
in
UART1: Transmit Data
PINMUX3[22].GIO
12
1 /
GIO
GIO: GIO[012]
SPI1_SDENA[ 166
0] / GIO011
E13
C13
A13
I/O SPI1 /
GIO
VDD
VDD
VDD
in
in
in
SPI1: Chip Select 0
PINMUX3[23].GIO
11
GIO: GIO[011]
SPI1: Clock
SPI1_SCLK /
GIO010
167
168
I/O SPI1 /
GIO
PINMUX3[24].GIO
10
GIO: GIO[010]
SPI1_SDI /
GIO009 /
SPI1_SDENA[
1]
I/O SPI1 /
GIO /
SPI1: Data In -OR- SPI1: Chip Select 1
PINMUX3[26:25].G
IO9
SPI1
GIO: GIO[009]
SPI1: Data Out
SPI1_SDO /
GIO008
169
170
E12
C17
I/O SPI1 /
GIO
VDD
in
in
PINMUX3[27].GIO
8
GIO: GIO[008]
GIO: GIO[007]
GIO007 /
SPI0_SDENA[
1]
I/O GIO
debou
nce /
VDD
PINMUX3[28].GIO
7
SPI0
SPI0: Chip Select 1
GIO: GIO[006]
GIO006
171
B18
I/O GIO
debou
nce
VDD
in
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Device Overview
49
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
GIO005
172
173
174
175
176
177
D15
I/O GIO
VDD
VDD
VDD
VDD
VDD
VDD
in
in
in
in
in
in
GIO: GIO[005]
debou
nce
GIO004
GIO003
GIO002
GIO001
GIO000
B17
G15
F15
E14
C16
I/O GIO
GIO: GIO[004]
GIO: GIO[003]
GIO: GIO[002]
GIO: GIO[001]
GIO: GIO[000]
debou
nce
I/O GIO
debou
nce
I/O GIO
debou
nce
I/O GIO
debou
nce
I/O GIO
debou
nce
USB_DP
USB_DM
USB_R1
178
179
180
A7
A6
C7
A I/O USBP VDDA33_USB
HY
USB D+ (differential signal pair)
USB D- (differential signal pair)
USB Reference current output
A I/O USBP VDDA33_USB
HY
A I/O USBP
HY
Connect to VSS_USB_REF via 10K Ω
±1% resistor placed as close to the
device as possible.
USB_ID
181
D5
A I/O USBP VDDA33_USB
HY
USB operating mode identification pin
For Device mode operation only, pull up
this pin to VDD with a 1.5K ohm resistor.
For Host mode operation only, pull down
this pin to ground (VSS) with a 1.5K ohm
resistor.
If using an OTG or mini-USB connector,
this pin will be set properly via the
cable/connector configuration.
USB_VBUS
182
E5
A I/O USBP
HY
For host or device mode operation, tie
the VBUS/USB power signal to the USB
connector.
When used in OTG mode operation, tie
VBUS to the external charge pump and
to the VBUS signal on the USB
connector.
When the USB is not used, tie VBUS to
Vss_USB.
USB_DRVVB
US
183
184
C5
C8
O
USBP
HY
VDD
VDD
Digital output to control external 5 V
supply
VSS_REF
GND USBP
HY
USB Ground Reference
Connect directly to ground and to
USB_R1 via
10K Ω ±1% resistor placed as close to
the device as possible.
VDDA33_USB 185
J8
PWR USBP
HY
VDD
Analog 3.3 V power USB PHY
(Transceiver)
50
Device Overview
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TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
VSS_USB
186
B7
GND USBP
HY
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Analog 3.3 V ground for USB PHY
(Transceiver)
VDDA33_USB 187
_PLL
C8
PWR USBP
HY
Common mode 3.3 V power for USB
PHY (PLL)
VSS_USB
188
E6
GND USBP
HY
Common mode 3.3 V ground for USB
PHY (PLL)
VDDA1P2_US 189
B
H7
PWR USBP
HY
Analog 1.2 V power for USB PHY
Analog 1.2 V ground for USB PHY
Digital 1.2 V power for USB PHY
Digital 1.2 V ground for USB PHY
VSS_USB
190
E6
GND USBP
HY
VDDD1P2_US 191
B
C6
PWR USBP
HY
VSS_USB
192
D6
GND USBP
HY
MMCSD0_CL
K
193
A15
C14
A14
B13
D14
B14
U18
I/O MMC
SD0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
out L MMCSD0: Clock
PINMUX4[2].MMC
SD0_MS
MMCSD0_CM 194
D
I/O MMC
SD0
in
in
in
in
in
in
MMCSD0: Command
MMCSD0: DATA3
PINMUX4[2].MMC
SD0_MS
MMCSD0_DA
TA3
195
196
197
198
199
I/O MMC
SD0
PINMUX4[2].MMC
SD0_MS
MMCSD0_DA
TA2
I/O MMC
SD0
MMCSD0: DATA2
PINMUX4[2].MMC
SD0_MS
MMCSD0_DA
TA1
I/O MMC
SD0
MMCSD0: DATA1
PINMUX4[2].MMC
SD0_MS
MMCSD0_DA
TA0
I/O MMC
SD0
MMCSD0: DATA0
PINMUX4[2].MMC
SD0_MS
UART0_RXD
UART0_TXD
I
UART
0
UART0: Receive Data
Used for UART boot mode
200
T18
B12
O
UART
0
VDD
out H UART0: Transmit Data
Used for UART boot mode
SPI0_SDENA[ 201
0] / GIO103
I/O SPI0 /
GIO
VDD
in
SPI0: Enable / Chip Select 0
PINMUX4[0].SPI0_
SDENA
GIO: GIO[103]
SPI0: Clock
SPI0_SCLK
202
203
C12
A12
I/O SPI0
VDD
VDD
in
in
SPI0_SDI /
GIO102
I/O SPI0 /
GIO
SPI0: Data In
PINMUX4[1].SPI0_
SDI
GIO: GIO[102]
SPI0_SDO
ASP1_DX
204
205
B11
C18
I/O SPI0
VDD
VDD
in
in
SPI0: Data Out
I/O ASP5
121
ASP1: Transmit Data
ASP1_CLKX
ASP1_FSX
ASP1_DR
206
207
208
209
210
D19
E16
C19
D18
E17
I/O ASP5
121
VDD
VDD
VDD
VDD
VDD
in
in
in
in
in
ASP1: Transmit Clock
I/O ASP5
121
ASP1: Transmit Frame Sync
ASP1: Receive Data
I/O ASP5
121
ASP1_CLKR
ASP1_FSR
I/O ASP5
121
ASP1: Receive Clock
I/O ASP5
121
ASP1: Receive Frame Synch
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Device Overview
51
TMS320DM355
Digital Media System-on-Chip (DMSoC)
www.ti.com
SPRS463–SEPTEMBER 2007
Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
ASP1_CLKS
211
D17
I
ASP5
121
VDD
in
ASP1: Master Clock
RESET
MXI1
212
213
D11
A9
I
I
VDD
VDD
PU
in
in
Global Chip Reset (active low)
Clock
s
Crystal input for system oscillator (24
MHz)
MXO1
MXI2
214
215
B9
R1
O
I
Clock
s
VDD
VDD
out
in
Output for system oscillator (24 MHz)
Clock
s
Crystal input for video oscillator (27
MHz). This crystal is not required
VDD
MXO2
216
T1
O
Clock
s
VDD
out
Output for video oscillator (27 MHz). This
crystal is not required.
VDD
TCK
217
218
219
220
221
222
223
E10
D9
E9
I
I
EMUL
ATIO
N
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PU
PU
in
in
JTAG test clock input
TDI
EMUL
ATIO
N
JTAG test data input
TDO
TMS
TRST
RTCK
EMU0
O
I
EMUL
ATIO
N
out L JTAG test data output
D8
C9
E11
E8
EMUL
ATIO
N
PU
PD
in
in
JTAG test mode select
I
EMUL
ATIO
N
JTAG test logic reset (active low)
O
EMUL
ATIO
N
out L JTAG test clock output
I/O EMUL
PU
PU
in
in
JTAG emulation 0 I/O
ATIO
N
VDD
VDD
EMU1
224
E7
I/O EMUL
VDD
JTAG emulation 1 I/O
ATIO
N
EMU[1:0] = 00 - Force Debug Scan chain
(ARM and ARM ETB TAPs connected)
EMU[1:0] = 11 - Normal Scan chain
(ICEpick only)
VSS
225
226
227
228
229
230
231
232
233
234
235
236
237
A5
A8
GND
GND
Digital ground
VSS
Digital ground
VSS
A19 GND
Digital ground
VSS
B5
B8
GND
GND
Digital ground
VSS
Digital ground
VSS
B10 GND
Digital ground
VSS
D1
P1
E2
GND
GND
GND
Digital ground
MX2GND
VSS
Video oscillator (27 MHz) - ground
Digital ground
VSS
E15 GND
Digital ground
VSS
G2
G9
H1
GND
GND
GND
Digital ground
VSS
Digital ground
VSS
Digital ground
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Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
H2
H6
GND
GND
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
H11 GND
H14 GND
J2
J6
GND
GND
GND
GND
GND
GND
J10
J14
K3
K9
K10 GND
K14 GND
L2
L9
GND
GND
L10 GND
L14 GND
M6
M7
M8
GND
GND
GND
M14 GND
M17 GND
N1
N8
N9
GND
GND
GND
N14 GND
R2
R6
GND
GND
MX1GND
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
VDD
C10 GND
L12 PWR
L11 PWR
System oscillator (24 MHz) - ground
Core power (1.3 V)
Core power (1.3 V)
M9
PWR
Core power (1.3 V)
J12 PWR
K12 PWR
K11 PWR
P13 PWR
P14 PWR
H10 PWR
H17 PWR
Core power (1.3 V)
Core power (1.3 V)
Core power (1.3 V)
Core power (1.3 V)
Core power (1.3 V)
Core power (1.3 V)
Core power (1.3 V)
H8
PWR
Core power (1.3 V)
B19 PWR
A10 PWR
Core power (1.3 V)
Core power (1.3 V)
K6
G11 PWR
C4 PWR
PWR
Core power (1.3 V)
Core power (1.3 V)
Core power (1.3 V)
M10 PWR
M13 PWR
Power for USB DRVVBUS IO (3.3 V)
Power for Digital IO (3.3 V)
VDD
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Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
VDD
VDD
VDD
VDD
VDD
VDD
VDD
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
W19 PWR
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital Video Input IO (3.3 V)
Power for Digital Video Input IO (3.3 V)
Power for Digital Video Output IO (3.3 V)
Power for Digital Video Output IO (3.3 V)
Power for Digital Video Output IO (3.3 V)
Power for MXI/O2 IO (3.3 V)
Power for DDR IO (1.8v)
Power for DDR IO (1.8v)
Power for DDR IO (1.8v)
Power for DDR IO (1.8v)
Gnd
R8
PWR
M11 PWR
K15 PWR
L13 PWR
J13 PWR
R7
P8
K8
G8
G6
K2
PWR
PWR
PWR
PWR
PWR
PWR
VDD_SHV3
VDDA1P2USB
VDD_SHV
VDD
VSS_CCP2
VDDS
T14 PWR
R12 PWR
R11 PWR
VDDS
VSSA_DLL
VDDS
R9
T5
PWR
PWR
VSS
VDDA_PLL1
VDDA_PLL2
VSSA_PLL1
VSSA_PLL2
VDD
G12 PWR
H9 PWR
H12 GND
Analog Power for PLL1 (1.3 V)
Analog Power for PLL2 (1.3 V)
Analog Ground for PLL1
Analog Ground for PLL2
Core power (1.3 V)
J9
A1
P9
GND
PWR
PWR
VDDS
Core power (1.3 V)
VDDS
P10 PWR
P11 PWR
Core power (1.3 V)
VDDS
Core power (1.3 V)
VSS
U1
U2
U3
N6
GND
GND
GND
PWR
Digital ground
VSS
Digital ground
VSS
Digital ground
VDDS
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO (3.3 V)
Power for Digital IO
VDD
T17 PWR
N12 PWR
N11 PWR
M12 PWR
VDDSHV
VDDSHV
VDDSHV
VDDSHV2
VDDSHV1
VDDSHV4
VDDSHV4
VDDSHV4
VDDSHV4
VDDSHV
VDDSHV
VDDSHV
VDDSHV
VDDSHV
VDDSHV
VSS
K8
L6
F6
F7
F8
F9
PWR
PWR
PWR
PWR
PWR
PWR
Power for Digital IO
Power for Digital IO
Power for Digital IO
Power for Digital IO
Power for Digital IO
F10 PWR
F11 PWR
F12 PWR
F13 PWR
F14 PWR
G14 PWR
Power for Digital IO
Power for Digital IO
Power for Digital IO
Power for Digital IO
Power for Digital IO
Power for Digital IO
T5
GND
Digital ground
54
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Table 2-23. DM355 Pin Descriptions (continued)
Name
Pin
#
BGA Type Grou
Power
PU Reset
Description(4)
Mux Control
(1)
ID
p
Supply(2) PD(3 State
)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
330
331
332
333
334
335
336
337
U4
V1
GND
GND
GND
GND
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
W1
U9
T15 GND
U14 GND
U17 GND
V18 GND
2.6 Device Support
2.6.1 Development Tools
TI offers an extensive line of development tools for DM355 systems, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tools support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of DM355 based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports TMS320DM355 DMSoC multiprocessor
system debug) EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320DM355 DMSoC platform, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
2.6.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., ). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
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TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate is undefined. Only qualified production devices are to
be used in production.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCE), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz). The
following figure provides a legend for reading the complete device name for any TMS320DM355 DMSoC
platform member.
(
)
ZCE 216
TMX 320 DM355
PREFIX
SPEED GRADE
216 MHz
270 MHz
TMX= Experimental device
TMS= Qualified device
(A)
PACKAGE TYPE
ZCE = 337-pin plastic BGA, with Pb-free soldered balls
DEVICE FAMILY
320 = TMS320 DSP family
SILICON REVISION
(B)
DEVICE
Blank = Initial Silicon1.1
DM355
A. BGA = Ball Grid Array
B.
Figure 2-5. Device Nomenclature
2.6.3 Device Documentation
2.6.3.1 Related Documentation From Texas Instruments
The following documents describe the TMS320DM355 Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet at www.ti.com. Contact your TI representative for Extranet
access.
SPRS463
TMS320DM355 Digital Media System-on-Chip (DMSoC) Data Manual This document
describes the overall TMS320DM355 system, including device architecture and features,
memory map, pin descriptions, timing characteristics and requirements, device mechanicals,
etc.
SPRZ264
TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functional
specifications for the TMS320DM355 DMSoC.
SPRUFB3 TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM
Subsystem in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The ARM
subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the
components of the ARM Subsystem, the peripherals, and the external memories.
SPRUED1 TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) Reference
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Guide This document describes the asynchronous external memory interface (EMIF) in the
TMS320DM35x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless
interface to a variety of external devices.
SPRUED2 TMS320DM35x DMSoC Universal Serial Bus (USB) Controller Reference Guide This
document describes the universal serial bus (USB) controller in the TMS320DM35x Digital
Media System-on-Chip (DMSoC). The USB controller supports data throughput rates up to
480 Mbps. It provides a mechanism for data transfer between USB devices and also
supports host negotiation.
SPRUED3 TMS320DM35x DMSoC Audio Serial Port (ASP) Reference Guide This document
describes the operation of the audio serial port (ASP) audio interface in the TMS320DM35x
Digital Media System-on-Chip (DMSoC). The primary audio modes that are supported by the
ASP are the AC97 and IIS modes. In addition to the primary audio modes, the ASP supports
general serial port receive and transmit operation, but is not intended to be used as a
high-speed interface.
SPRUED4 TMS320DM35x DMSoC Serial Peripheral Interface (SPI) Reference Guide This document
describes the serial peripheral interface (SPI) in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). The SPI is a high-speed synchronous serial input/output port that
allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the
device at a programmed bit-transfer rate. The SPI is normally used for communication
between the DMSoC and external peripherals. Typical applications include an interface to
external I/O or peripheral expansion via devices such as shift registers, display drivers, SPI
EPROMs and analog-to-digital converters.
SPRUED9 TMS320DM35x DMSoC Universal Asynchronous Receiver/Transmitter (UART)
Reference Guide This document describes the universal asynchronous receiver/transmitter
(UART) peripheral in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The
UART peripheral performs serial-to-parallel conversion on data received from a peripheral
device, and parallel-to-serial conversion on data received from the CPU.
SPRUEE0 TMS320DM35x DMSoC Inter-Integrated Circuit (I2C) Peripheral Reference Guide This
document describes the inter-integrated circuit (I2C) peripheral in the TMS320DM35x Digital
Media System-on-Chip (DMSoC). The I2C peripheral provides an interface between the
DMSoC and other devices compliant with the I2C-bus specification and connected by way of
an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive
up to 8-bit wide data to and from the DMSoC through the I2C peripheral. This document
assumes the reader is familiar with the I2C-bus specification.
SPRUEE2 TMS320DM35x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller
Reference Guide This document describes the multimedia card (MMC)/secure digital (SD)
card controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The MMC/SD
card is used in a number of applications to provide removable data storage. The MMC/SD
controller provides an interface to external MMC and SD cards. The communication between
the MMC/SD controller and MMC/SD card(s) is performed by the MMC/SD protocol.
SPRUEE4 TMS320DM35x DMSoC Enhanced Direct Memory Access (EDMA) Controller Reference
Guide This document describes the operation of the enhanced direct memory access
(EDMA3) controller in the TMS320DM35x Digital Media System-on-Chip (DMSoC). The
EDMA controller's primary purpose is to service user-programmed data transfers between
two memory-mapped slave endpoints on the DMSoC.
SPRUEE5 TMS320DM35x DMSoC 64-bit Timer Reference Guide This document describes the
operation of the software-programmable 64-bit timers in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are used as general-purpose (GP)
timers and can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit
chained mode; Timer 2 is used only as a watchdog timer. The GP timer modes can be used
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to generate periodic interrupts or enhanced direct memory access (EDMA) synchronization
events and Real Time Output (RTO) events (Timer 3 only). The watchdog timer mode is
used to provide a recovery mechanism for the device in the event of a fault condition, such
as a non-exiting code loop.
SPRUEE6 TMS320DM35x DMSoC General-Purpose Input/Output (GPIO) Reference Guide This
document describes the general-purpose input/output (GPIO) peripheral in the
TMS320DM35x Digital Media System-on-Chip (DMSoC). The GPIO peripheral provides
dedicated general-purpose pins that can be configured as either inputs or outputs. When
configured as an input, you can detect the state of the input by reading the state of an
internal register. When configured as an output, you can write to an internal register to
control the state driven on the output pin.
SPRUEE7 TMS320DM35x DMSoC Pulse-Width Modulator (PWM) Reference Guide This document
describes the pulse-width modulator (PWM) peripheral in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUEH7 TMS320DM35x DMSoC DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Reference
Guide This document describes the DDR2 / mobile DDR memory controller in the
TMS320DM35x Digital Media System-on-Chip (DMSoC). The DDR2 / mDDR memory
controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM and
mobile DDR devices.
SPRUF71 TMS320DM35x DMSoC Video Processing Front End (VPFE) Users Guide This document
describes the Video Processing Front End (VPFE) in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUF72 TMS320DM35x DMSoC Video Processing Back End (VPBE) Users Guide This document
describes the Video Processing Back End (VPBE) in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUF74 TMS320DM35x DMSoC Real Time Out (RTO) Controller Reference Guide This document
describes the Real Time Out (RTO) controller in the TMS320DM35x Digital Media
System-on-Chip (DMSoC).
SPRUFC8 TMS320DM355 DMSoC Peripherals Overview Reference Guide This document provides
an overview of the peripherals in the TMS320DM355 Digital Media System-on-Chip
(DMSoC).
The following documents describe TMS320DM35x Digital Media System-on-Chip (DMSoC) that are not
available by literature number. Copies of these documents are available (by title only) on the internet at
www.ti.com. Contact your TI representative for Extranet access.
TMS320DM35x DDR2 / mDDR Board Design Application Note This provides board
design recommendations and guidelines for DDR2 and mobile DDR.
TMS320DM35x USB Board Design and Layout Guidelines Application Note This
provides board design recommendations and guidelines for high speed USB.
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3 Detailed Device Description
This section provides a detailed overview of the DM355 device.
3.1 ARM Subsystem Overview
The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of
the overall DM355 system, including the components of the ARM Subsystem, the peripherals, and the
external memories.
The ARM is responsible for handling system functions such as system-level initialization, configuration,
user interface, user command execution, connectivity functions, interface and control of the subsystem,
etc. The ARM is master and performs these functions because it has a large program memory space and
fast context switching capability, and is thus suitable for complex, multi-tasking, and general-purpose
control tasks.
3.1.1 Components of the ARM Subsystem
The ARM Subsystem in DM355 consists of the following components:
•
ARM926EJ-S RISC processor, including:
–
–
–
–
–
–
coprocessor 15 (CP15)
MMU
16KB Instruction cache
8KB Data cache
Write Buffer
Java accelerator
•
ARM Internal Memories
–
–
32KB Internal RAM (32-bit wide access)
8KB Internal ROM (ARM bootloader for non-AEMIF boot options)
•
•
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
System Control Peripherals
–
–
–
–
ARM Interrupt Controller
PLL Controller
Power and Sleep Controller
System Control Module
The ARM also manages/controls all the device peripherals:
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR2 / mDDR EMIF Controller
AEMIF Controller, including the OneNAND and NAND flash interface
Enhanced DMA (EDMA)
UART
Timers
Real Time Out (RTO)
Pulse Width Modulator (PWM)
Inter-IC Communication (I2C)
Multi-Media Card/Secure Digital (MMC/SD)
Audio Serial Port (ASP)
Universal Serial Bus Controller (USB)
Serial Port Interface (SPI)
Video Processing Front End (VPFE)
–
CCD Controller (CCDC)
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–
–
–
Image Pipe (IPIPE)
H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure)
Multiply Mask / Lens Distortion Module (CFALD)
•
Video Processing Back End (VPBE)
–
–
On Screen Display (OSD)
Video Encoder Engine (VENC)
Figure 3-1 shows the functional block diagram of the DM355 ARM Subsystem.
ARM
Master
interrupt
controller
(AINTC)
Master IF
IF
Arbiter
Arbiter
I-AHB
D-AHB
System
control
I-TCM
D-TCM
Slave
IF
ARM926EJ-S
Arbiter
PLLC2
PLLC1
Power
sleep
16K I$
8K D$
CP15
MMU
8K
16K
16K
controller
(PSC)
ROM
RAM1 RAM0
Peripherals
...
Figure 3-1. DM355 ARM Subsystem Block Diagram
3.2 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•
•
•
•
•
•
ARM926EJ -S integer core
CP15 system control coprocessor
Memory Management Unit (MMU)
Separate instruction and data Caches
Write buffer
Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
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•
•
Separate instruction and data AHB bus interfaces
Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.2.1 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,
when the ARM in a privileged mode such as supervisor or system mode.
3.2.2 MMU
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux,
WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to
control the address translation, permission checks and memory region attributes for both data and
instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables. The MMU features are:
•
•
Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
Mapping sizes are:
–
–
–
–
1MB (sections)
64KB (large pages)
4KB (small pages)
1KB (tiny pages)
•
Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•
•
•
•
Hardware page table walks
Invalidate entire TLB, using CP15 register 8
Invalidate TLB entry, selected by MVA, using CP15 register 8
Lockdown of TLB entries, using CP15 register 10
3.2.3 Caches and Write Buffer
The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following
features:
•
•
Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•
Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.
•
•
Critical-word first cache refilling
Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•
Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•
Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.2.4 Tightly Coupled Memory (TCM)
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt
Vector table. ARM internal ROM enables non-AEMIF boot options, such as NAND, UART, and HPI. The
RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that
provides for separate instruction and data bus connections. Since the ARM TCM does not allow
instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and
instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM
from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for
direct accesses to the ARM internal memory from a non-ARM master. Because of the time-critical nature
of the TCM link to the ARM internal memory, all accesses from non-ARM devices are treated as DMA
transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.
3.2.5 Advanced High-performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus
and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB
by the configuration bus and the external memories bus.
3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in DM355 also includes the Embedded
Trace Buffer (ETB). The ETM consists of two parts:
•
•
Trace Port provides real-time trace capability for the ARM9.
Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The DM355 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The
ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace
data.
3.3 Memory Mapping
The ARM memory map is shown in Table 2-2 and Table 2-3. This section describes the memories and
interfaces within the ARM's memory map.
3.3.1 ARM Internal Memories
The ARM has access to the following ARM internal memories:
•
32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
•
8KB ARM Internal ROM
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3.3.2 External Memories
The ARM has access to the following External memories:
•
•
•
•
DDR2 / mDDR Synchronous DRAM
Asynchronous EMIF / OneNAND
NAND Flash
Flash card devices:
–
–
–
MMC/SD
xD
SmartMedia
3.3.3 Peripherals
The ARM has access to all of the peripherals on the device.
3.4 ARM Interrupt Controller (AINTC)
The DM355 ARM Interrupt Controller (AINTC) has the following features:
•
•
•
Supports up to 64 interrupt channels (16 external channels)
Interrupt mask for each channel
Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request
(IRQ) type of interrupt.
•
•
•
Hardware prioritization of simultaneous interrupts
Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ)
Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time
The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference
Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is
mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The
INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize
the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding
highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can
read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a
software dispatcher to determine the asserted interrupt.
3.4.1 Interrupt Mapping
The AINTC takes up to 64 ARM device interrupts and maps them to either the IRQ or to the FIQ of the
ARM. Each interrupt is also assigned one of 8 priority levels (2 for FIQ, 6 for IRQ). For interrupts with the
same priority level, the priority is determined by the hardware interrupt number (the lowest number has the
highest priority). Table 3-1 shows the connection of device interrupts to the ARM.
Table 3-1. AINTC Interrupt Connections(1)
Interrupt
Number
Acronym
Source
Interrupt
Number
Acronym
Source
0
VPSSINT0
VPSS - INT0,
Configurable via
VPSSBL register:
INTSEL
32
TINT0
Timer 0 - TINT12
1
2
3
4
VPSSINT1
VPSSINT2
VPSSINT3
VPSSINT4
VPSS - INT1
VPSS - INT2
VPSS - INT3
VPSS - INT4
33
34
35
36
TINT1
Timer 0 - TINT34
Timer 1 - TINT12
Timer 1 - TINT34
PWM0
TINT2
TINT3
PWMINT0
(1) The total number of interrupts in DM355 exceeds 64, which is the maximum value of the AINTC module. Therefore, several interrupts
are multiplexed and you must use the register ARM_INTMUX in the System Control Module to select the interrupt source for multiplexed
interrupts. Refer to the ARM Subsystem Guide for more information on the System Control Module register ARM_INTMUX.
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Table 3-1. AINTC Interrupt Connections (continued)
Interrupt
Number
Acronym
Source
Interrupt
Number
Acronym
Source
5
6
VPSSINT5
VPSSINT6
VPSSINT7
VPSSINT8
Reserved
Reserved
Reserved
USBINT
VPSS - INT5
VPSS - INT6
VPSS - INT7
VPSS - INT8
37
38
39
40
41
42
43
44
45
PWMINT1
PWMINT2
I2CINT
PWM 1
PWM2
I2C
7
8
UARTINT0
UARTINT1
SPINT0-0
SPINT0-1
GPIO0
UART0
UART1
SPI0
9
10
11
12
13
SPI0
USB OTG Collector
GPIO
GPIO
RTOINT or
TINT4
RTO or
Timer 2 - TINT12
SYS.ARM_INTMUX
GPIO1
14
UARTINT2 or
TINT5
UART2 or
Timer 2 - TINT34
46
GPIO2
GPIO
15
16
17
TINT6
Timer 3 TINT12
47
48
49
GPIO3
GPIO4
GPIO5
GPIO
GPIO
GPIO
CCINT0
EDMA CC Region 0
SPINT1-0 or
CCERRINT
SPI1 or
EDMA CC Error
18
19
SPINT1-1 or
TCERRINT0
SPI1 or
EDMA TC0 Error
50
51
GPIO6
GPIO7
GPIO
GPIO
SPINT2-0 or
TCERRINT1
SPI2 or
EDMA TC1 Error
20
21
22
23
24
PSCINT
SPINT2-1
TINT7
PSC - ALLINT
SPI2
52
53
54
55
56
GPIO8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO9
Timer3 - TINT34
MMC/SD0
GPIOBNK0
GPIOBNK1
GPIOBNK2
SDIOINT0
MBXINT0 or
MBXINT1
ASP0 or
ASP1
25
MBRINT0 or
MBRINT1
ASP0 or
ASP1
57
GPIOBNK3
GPIO
26
27
28
29
30
31
MMCINT0
MMCINT1
PWMINT3
DDRINT
MMC/SD0
MMC/SC1
PWM3
58
59
60
61
62
63
GPIOBNK4
GPIOBNK5
GPIOBNK6
COMMTX
COMMRX
EMUINT
GPIO
GPIO
GPIO
DDR EMIF
Async EMIF
SDIO1
ARMSS
ARMSS
E2ICE
AEMIFINT
SDIOINT1
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3.5 Device Clocking
3.5.1 Overview
The DM355 requires one primary reference clock . The reference clock frequency may be generated
either by crystal input or by external oscillator. The reference clock is the clock at the pins named
MXI1/MXOI. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1
generates the clocks required by the ARM, MPEG and JPEG co-processor, VPBE, VPSS, and
peripherals. PLL2 generates the clock required by the DDR PHY. A block diagram of DM355's clocking
architecture is shown in Figure 5-1. The PLLs are described further in Section 3.6.
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SYSCLKBP
AUXCLK
CLKOUT2
UART0, 1
I2C
BPDIV (/3)
Reference clock
(MXI/MXO)
24 MHz or 36 Mhz
AUXCLK (/1)
PLLDIV1 (/2)
SYSCLK1
ARM subsystem
MPEG/JPEG
co-Processor
PWMs (x4)
Timers (x4)
RTO
CLKOUT1
Reference
clock
(MXI/MXO)
(24 MHz or
36 MHz)
SYSCLK2
PLLDIV2 (/4)
USB Phy
SYSCLK3
SYSCLK4
60 MHz
PLLDIV3 (/n)
USB
EMIF/NAND
MMC/SD (x2)
SPI (x3)
PLLDIV4 (/4 or /2)
VPSS
PLL controller 1
VPFE
VPBE
PCLK
ASP (x2)
GPIO
EXTCLK
ARM INTC
DAC
UART2
EDMA
SYSCLK1
PLLDIV1 (/1)
DDR PHY
DDR
Bus logic
Sys logic
PSC
SYSCLKBP
BPDIV (/8)
CLKOUT3
PLL controller 2
IcePick
Sequencer
Figure 3-2. Device Clocking Block Diagram
3.5.2 Supported Clocking Configurations for DM355 - 216
This section describes the only supported device clocking configurations for DM355 - 216. The DM355
supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input).
Configurations are shown for both cases.
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3.5.2.1 Supported Clocking Configurations for DM355 - 216 (24 MHz reference)
3.5.2.1.1 DM355 - 216 PLL1 (24 MHz reference)
All supported clocking configurations for DM355 - 216 PLL1 with 24 MHz reference clock are shown in
Table 3-2
Table 3-2. PLL1 Supported Clocking Configurations for DM355 - 216 (24 MHz reference)
PREDI
V
PLLM
POSTDIV
PLL1
VCO
ARM /
MPEG and
JPEG
Peripherals
Venc
VPSS
Co-Processor
(/8
(m
(/2 or /1
(MHz) PLLDIV SYSC PLLDIV SYSCLK2
PLLDIV3
(/n
SYSCL
K3
PLLDIV4
(/4 or /2
SYSCLK
4
fixed) programmable programma
1
LK1
2
(MHz)
)
ble)
(/2
(MHz)
(/4
programma (MHz) programmable
(MHz)
fixed)
fixed)
ble)
)
bypass
bypass
bypass
bypas
s
2
12
4
6
10
2.4
4
6
8
8
8
8
8
8
8
8
8
8
8
144
135
126
117
108
99
1
1
1
1
1
1
2
2
2
2
2
432
405
378
351
324
297
270
243
216
189
162
2
2
2
2
2
2
2
2
2
2
2
216
202.5
189
4
4
4
4
4
4
4
4
4
4
4
108
101.25
94.5
87.75
81
16
15
14
13
12
11
10
9
27
27
27
27
27
27
27
27
27
27
27
4
4
4
4
4
4
2
2
2
2
2
108
101.25
94.5
87.75
81
175.5
162
148.5
135
74.25
67.5
60.75
54
74.25
135
180
162
144
126
108
121.5
108
121.5
108
8
94.5
81
47.25
40.5
7
94.5
81
6
3.5.2.1.2 DM355 - 216 PLL2 (24 MHz reference)
All supported clocking configurations for DM355 - 216 PLL2 with 24 MHz reference clock are shown in
Table 3-3
Table 3-3. PLL2 Supported Clocking Configurations for DM355 - 216 (24 MHz reference)
PREDIV
PLLM
POSTDIV
PLL2 VCO
DDR PHY
DDR Clock
(/n programmable)
(m
(/2 fixed)
(MHz)
PLLDIV1
(/1 fixed)
SYSCLK1
(MHz)
DDR_CLK
(MHz)
programmable)
bypass
bypass
114
108
102
96
bypass
bypass
342
1
1
1
1
1
1
1
1
24
12
8
8
1
1
1
1
1
1
1
342
324
306
288
266
200
160
171
162
153
144
133
100
80
324
8
306
8
288
12
12
15
133
100
100
266
200
160
3.5.2.2 Supported Clocking Configurations for DM355 - 216 (36 MHz reference)
3.5.2.2.1 DM355 - 216 PLL1 (36 MHz reference)
All supported clocking configurations for DM355 - 216 PLL1 with 36 MHz reference clock are shown in
Table 3-4
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Table 3-4. PLL1 Supported Clocking Configurations DM355 - 216 (36 MHz reference)
PREDI
V
PLLM
POSTDIV
PLL1
VCO
ARM /
MPEG and
JPEG
Peripherals
Venc
VPSS
Co-Processor
(/8
(m
(/2 or /1
(MHz) PLLDIV SYSCL PLLDIV SYSCLK
PLLDIV3
SYSCLK
3
(MHz)
PLLDIV4
(/4 or /2
programmable
)
SYSCLK
4
(MHz)
fixed) programmable programma
1
K1
2
2
(/n
programma
ble)
)
ble)
(/2
(MHz)
(/4
(MHz)
fixed)
fixed)
bypass
bypass
96
bypass
bypass
432
405
378
351
324
297
270
243
216
2
2
2
2
2
2
2
2
2
2
18
4
4
4
4
4
4
4
4
4
4
9
10
16
15
14
13
12
11
10
9
3.6
27
27
27
27
27
27
27
27
27
4
4
4
4
4
4
4
2
2
2
9
8
8
8
8
8
8
8
8
8
1
2
2
2
2
2
2
2
2
216
108
108
180
168
156
144
132
120
108
96
202.5
189
101.25
94.5
87.75
81
101.25
94.5
87.75
81
175.5
162
148.5
135
74.25
67.5
60.75
54
74.25
135
121.5
108
121.5
108
8
3.5.2.2.2 DM355 - 216 PLL2 (36 MHz reference)
All supported clocking configurations for DM355 - 216 PLL2 with 36 MHz reference clock are shown in
Table 3-5
Table 3-5. PLL2 Supported Clocking Configurations for DM355 - 216 (36 MHz reference)
PREDIV
PLLM
POSTDIV
PLL2 VCO
DDR PHY
DDR Clock
(/n programmable)
(m
(/2 fixed)
(MHz)
PLLDIV1
(/1 fixed)
SYSCLK1
(MHz)
DDR_CLK
(MHz)
programmable)
bypass
12
bypass
114
108
102
96
bypass
bypass
342
1
1
1
1
1
1
1
1
36
18
1
1
1
1
1
1
1
342
324
306
288
266
200
160
171
162
153
144
133
100
80
12
324
12
306
12
288
18
133
150
120
266
27
200
27
160
3.5.3 Supported Clocking Configurations for DM355 270
This section describes the only supported device clocking configurations for DM355 - 270. The DM355
supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input).
Configurations are shown for both cases.
3.5.3.1 Supported Clocking Configurations for DM355 - 270 (24 MHz reference)
3.5.3.1.1 DM355 - 270 PLL1 (24 MHz reference)
All supported clocking configurations for DM355 - 270 PLL1 with 24 MHz reference clock are shown in
Table 3-2
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Table 3-6. PLL1 Supported Clocking Configurations for DM355 - 270 (24 MHz reference)
PRED
IV
PLLM
POSTDIV PLL1
ARM /
Peripherals
Venc
VPSS
VCO MPEG and JPEG
Co-Processor
(/8
(m
(/2 fixed) (MHz) PLLDIV1 SYSC PLLDI SYSCLK2
PLLDIV3
SYSCLK PLLDIV4 SYSCLK4
fixed) programmable)
(/2 fixed)
LK1
(MHz)
V2
(/4
(MHz)
(/n
3
(/2 fixed)
(MHz)
programmable)
(MHz)
fixed)
bypas
s
bypass
bypass
bypas
s
2
12
4
6
10
2.4
4
6
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
180
171
162
153
144
135
126
117
108
99
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
540
513
486
459
432
405
378
351
324
297
270
243
216
189
162
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
270
256.5
243
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
135
128.25
121.5
114.75
108
20
19
18
17
16
15
14
13
12
11
10
9
27
27
27
27
27
27
27
27
27
27
27
27
27
27
27
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
135
128.25
121.5
114.75
108
229.5
216
202.5
189
101.25
94.5
101.25
94.5
175.5
162
87.75
81
87.75
81
148.5
135
74.25
67.5
74.25
135
180
162
144
126
108
121.5
108
60.75
54
121.5
108
8
94.5
81
47.25
40.5
7
94.5
6
81
3.5.3.1.2 DM355 - 270 PLL2 (24 MHz reference)
All supported clocking configurations for DM355 - 270 PLL2 with 24 MHz reference clock are shown in
Table 3-3
Table 3-7. PLL2 Supported Clocking Configurations for DM355 - 270 (24 MHz reference)
PREDIV
PLLM
POSTDIV
PLL2 VCO
DDR PHY
DDR Clock
(/n programmable)
(m
(/2 fixed)
(MHz)
PLLDIV1
(/1 fixed)
SYSCLK1
(MHz)
DDR_CLK
(MHz)
programmable)
bypass
bypass
114
108
102
96
bypass
bypass
342
1
1
1
1
1
1
1
1
24
12
8
8
1
1
1
1
1
1
1
342
324
306
288
266
200
160
171
162
153
144
133
100
80
324
8
306
8
288
12
12
15
133
100
100
266
200
160
3.5.3.2 Supported Clocking Configurations for DM355 - 270 (36 MHz reference)
3.5.3.2.1 DM355 - 270 PLL1 (36 MHz reference)
All supported clocking configurations for DM355 - 270 PLL1 with 36 MHz reference clock are shown in
Table 3-4
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Table 3-8. PLL1 Supported Clocking Configurations for DM355 - 270 (36 MHz reference)
PREDI
V
PLLM
POSTDI PLL1
VCO
ARM /
MPEG and
JPEG
Peripherals
Venc
VPSS
V
Co-Processor
(/8
(m
(/2 fixed) (MHz) PLLDIV SYSC PLLDIV SYSCLK2
PLLDIV3
SYSCL PLLDIV4 SYSCLK4
fixed) programmable)
1
LK1
2
(MHz)
(/n
K3
(/2 fixed)
(MHz)
(/2
(MHz)
(/4
programmable)
(MHz)
fixed)
fixed)
bypas
s
bypass
bypass
bypas
s
2
18
4
9
10
3.6
4
18
8
8
8
8
8
8
8
8
8
8
8
8
8
120
114
108
102
96
1
1
1
1
2
2
2
2
2
2
2
2
2
540
513
486
459
432
405
378
351
324
297
270
243
216
2
2
2
2
2
2
2
2
2
2
2
2
2
270
256.5
243
4
4
4
4
4
4
4
4
4
4
4
4
4
135
128.25
121.5
114.75
108
20
19
18
17
16
15
14
13
12
11
10
9
27
27
27
27
27
27
27
27
27
27
27
27
27
4
4
4
4
4
2
2
2
2
2
2
2
2
135
128.25
121.5
114.75
108
229.5
216
180
168
156
144
132
120
108
96
202.5
189
101.25
94.5
202.5
189
175.5
162
87.75
81
175.5
162
148.5
135
74.25
67.5
148.5
135
121.5
108
60.75
54
121.5
108
8
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3.5.3.2.2 DM355 - 270 PLL2 (36 MHz reference)
All supported clocking configurations for DM355 - 270 PLL2 with 36 MHz reference clock are shown in
Table 3-5
Table 3-9. PLL2 Supported Clocking Configurations for DM355L (36 MHz reference)
PREDIV
PLLM
POSTDIV
PLL2 VCO
DDR PHY
DDR Clock
(/n programmable)
(m
(/2 fixed)
(MHz)
PLLDIV1
(/1 fixed)
SYSCLK1
(MHz)
DDR_CLK
(MHz)
programmable)
bypass
12
bypass
114
108
102
96
bypass
bypass
342
1
1
1
1
1
1
1
1
36
18
1
1
1
1
1
1
1
342
324
306
288
266
200
160
171
162
153
144
133
100
80
12
324
12
306
12
288
18
133
150
120
266
27
200
27
160
3.5.4 Peripheral Clocking Considerations
3.5.4.1 Video Processing Back End Clocking
The Video Processing Back End (VPBE) is a sub-module of the VPSS (Video Processing Subsystem).
The VPBE is designed to interface with a variety of LCDs and an internal DAC module. There are two
asynchronous clock domains in the VPBE: an internal clock domain and an external clock domain. The
internal clock domain is driven by the VPSS clock (PLL1 SYSCLK4). The external clock domain is
configurable; you can select one of five source:
•
•
•
•
•
24 MHz crystal input at MXI1
27 MHz crystal input at MXI2 (optional feature, not typically used)
PLL1 SYSCLK3
EXTCLK pin (external VPBE clock input pin)
PCLK pin (VPFE pixel clock input pin)
See the TMS320DM355 DMSoC Video Processing Back End (VPBE) User's Guide for complete
information on VPBE clocking.
3.5.4.2 USB Clocking
The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of
the USB PHY.
NOTE
For proper USB function, SYSCLK2 must be greater than 60 MHz.
The USB PHY takes an input clock that is configurable by the USB PHY clock source bits (PHYCLKSRC)
in the USB PHY control register (USB_PHY_CTL) in the System Control Module. When a 24 MHz crystal
is used at MXI1/MXO1, set PHYCLKSRC to 0. This will present a 24 MHz clock to the USB PHY. When a
36 MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to 1. This will present a 12 MHz clock (36 MHz
divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12
MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1. See the TMS320DM355
DMSoC Univeral Serial Bus (USB) Controller User's Guide (SPRUED2) for more information. See the
TMS320DM355 DMSoC ARM Subsystem User's Guide for more information on the System Control
Module.
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3.6 PLL Controller (PLLC)
This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM355 Digital Media
System-on-Chip ARM Subsystem User's Guide for more information on the PLL controllers.
3.6.1 PLL Controller Module
The DM355 has two PLL controllers that provide clocks to different components of the chip. PLL controller
1 (PLLC1) provides clocks to most of the components of the chip. PLL controller 2 (PLLC2) provides
clocks to the DDR PHY.
As a module, the PLL controller provides the following:
•
•
•
•
•
Glitch-free transitions (on changing PLL settings)
Domain clocks alignment
Clock gating
PLL bypass
PLL power down
The various clock outputs given by the PLL controller are as follows:
•
•
•
Domain clocks: SYSCLKn
Bypass domain clock: SYSCLKBP
Auxiliary clock from reference clock: AUXCLK
Various dividers that can be used are as follows:
•
•
•
•
Pre-PLL divider: PREDIV
Post-PLL divider: POSTDIV
SYSCLK divider: PLLDIV1, …, PLLDIVn
SYSCLKBP divider: BPDIV
Multipliers supported are as follows:
PLL multiplier control: PLLM
•
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3.6.2 PLLC1
PLLC1 provides most of the DM355 clocks. Software controls PLLC1 operation through the PLLC1
registers. The following list, Table 3-10, and Figure 3-3 describe the customizations of PLLC1 in the
DM355.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Provides primary DM355 system clock
Software configurable
Accepts clock input or internal oscillator input
PLL pre-divider value is fixed to (/8)
PLL multiplier value is programmable
PLL post-divider
Only SYSCLK[4:1] are used
SYSCLK1 divider value is fixed to (/2)
SYSCLK2 divider value is fixed to (/4)
SYSCLK3 divider value is programmable
SYSCLK4 divider value is programmable to (/4) or (/2)
SYSCLKBP divider value is fixed to (/3)
SYSCLK1 is routed to the ARM Subsystem
SYSCLK2 is routed to peripherals
SYSCLK3 is routed to the VPBE module
SYSCLK4 is routed to the VPSS module
AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1
SYSCLKBP is routed to the output pin CLKOUT2
Table 3-10. PLLC1 Output Clocks
Output Clock
Used By
PLLDIV
Divider
Notes
SYSCLK1
SYSCLK2
SYSCLK3
ARM Subsystem / MPEG and JPEG Co-Processor
Peripherals
/2
/4
/n
Fixed divider
Fixed divider
VPBE (VENC module)
Programmable divider (used to get 27
MHz for VENC)
SYSCLK4
AUXCLK
VPSS
/4 or /2
none
/3
Programmable divider
No divider
Peripherals, CLKOUT1
CLKOUT2
SYSCLKBP
Fixed divider
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CLKMODE
PLLEN
CLKIN
OSCIN
1
0
Post-DIV
(/2 or /1)
Pre-DIV
(/8)
SYSCLK1
(ARM and MPEG/JPEG
Co-processor)
PLL
1
0
PLLDIV1 (/2)
PLLDIV2 (/4)
PLLDIV3 (/3)
SYSCLK2
(peripherals)
PLLM
(programmable)
SYSCLK3
(VPBE)
SYSCLK4
(VPSS)
PLLDIV4
(/4 or /2)
AUXCLK
(Peripherals,
CLKOUT1)
SYSCLKBP
(CLKOUT2)
BPDIV (/3)
Figure 3-3. PLLC1 Configuration In DM355
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3.6.3 PLLC2
PLLC2 provides the DDR PHY clock and CLKOUT3. Software controls PLLC2 operation through the
PLLC2 registers. The following list, Table 3-11, and Figure 3-4 describe the customizations of PLLC2 in
the DM355.
•
•
•
•
•
•
•
•
•
•
•
•
Provides DDR PHY clock and CLKOUT3
Software configurable
Accepts clock input or internal oscillator input (same input as PLLC1)
PLL pre-divider value is programmable
PLL multiplier value is programmable
PLL post-divider value is fixed to (/1)
Only SYSCLK[1] is used
SYSCLK1 divider value is fixed to (/1)
SYSCLKBP divider value is fixed to (/8)
SYSCLK1 is routed to the DDR PHY
SYSCLKBP is routed to the output pin CLKOUT3
AUXCLK is not used.
Table 3-11. PLLC2 Output Clocks
Output Clock
SYSCLK1
Used by
DDR PHY
CLKOUT3
PLLDIV Divider
Notes
/1
/8
Fixed divider
Fixed divider
SYSCLKBP
PLLC2 Configuration in DM355
CLKMODE
PLLEN
CLKIN
OSCIN
1
Post-DIV
(/1)
Pre-DIV
(programmable)
PLL
1
0
SYSCLK1
0
PLLDIV1 (/1)
(DDR PHY)
PLLM
(programmable)
SYSCLKBP
(CLKOUT3)
BPDIV (/8)
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3.7 Power and Sleep Controller (PSC)
In the DM355 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of
system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of
the operations of the PSC are transparent to software, such as power-on-reset operations. However, the
PSC provides you with an interface to control several important clock and reset operations.
The PSC includes the following features:
•
•
Manages chip power-on/off, clock on/off, and resets
Provides a software interface to:
–
–
Control module clock ON/OFF
Control module resets
•
Supports IcePick emulation features: power, clock, and reset
For more information on the PSC, see the ARM Subsystem User's Guide.
DMSoC
ARM
PLLC
clks
arm_clock
arm_mreset
PSC
arm_power
Interrupt
AINTC
Emulation
RESETN
VDD
MODx
module_clock
module_mreset
module_power
Always on
domain
Figure 3-5. DM355 Power and Sleep Controller (PSC)
3.8 System Control Module
The DM355’s system control module is a system-level module containing status and top-level control logic
required by the device. The system control module consists of a miscellaneous set of status and control
registers, accessible by the ARM and supporting all of the following system features and operations:
•
•
Device identification
Device configuration
–
–
Pin multiplexing control
Device boot configuration status
•
•
ARM interrupt and EDMA event multiplexing control
Special peripheral status and control
–
–
–
–
–
–
Timer64+
USB PHY control
VPSS clock and video DAC control and status
DDR VTP control
Clockout circuitry
GIO de-bounce control
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•
•
Power management
Deep sleep and fast NAND boot control
Bandwidth Management
Bus master DMA priority control
For more information on the System Control Module refer to the ARM Subsystem User's Guide.
–
–
3.9 Pin Multiplexing
The DM355 makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. In order to accomplish this, pin multiplexing is controlled using
a combination of hardware configuration (at device reset) and software control. No attempt is made by the
DM355 hardware to ensure that the proper pin muxing has been selected for the peripherals or interface
mode being used, thus proper pin muxing configuration is the responsibility of the board and software
designers. An overview of the pin multiplexing is shown in Table 3-12.
Table 3-12. Peripheral Pin Mux Overview
Peripheral
VPFE (video in)
VPBE (video out)
AEMIF
Muxed With
GPIO and SPI2
GPIO, PWM, and RTO
GPIO
Primary Function
VPFE (video in)
VPBE (video out)
AEMIF
Secondary Function
Tertiary Function
GPIO
SPI2
PWM and RTO
GPIO
GPIO
none
ASP0
GPIO
ASP0
GPIO
none
MMC/SD1
CLKOUT
I2C
GPIO and UART2
GPIO
MMC/SD1
CLKOUT
I2C
GPIO
UART2
none
GPIO
GPIO
GPIO
none
UART1
GPIO
UART1
GPIO
none
SPI1
GPIO
SPI1
GPIO
none
SPI0
GPIO
SPI0
GPIO
none
3.9.1 Hardware Controlled Pin Multiplexing
Use the Asynchronous EMIF configuration pins (AECFG[3:0]) for hardware pin mux control. AECFG[3:0]
control the partitioning of the AEMIF addresses and GPIOs at reset, which allows you to properly
configure the number of AEMIF address pins required by the boot device while unused addresses pins are
available as GPIOs. These settings may be changed by software after reset by programming the PinMux2
register The PinMux2 register is in the System Control Module. As shown in Table 3-13, the number of
address bits enabled on the AEMIF is selectable from 0 to 16. Pins that are not assigned to another
peripheral and not enabled as address signals become GPIOs (except EM_A[2:1]). The enabled address
signals are always contiguous from EM_BA[1] upwards; bits cannot be skipped. The exception to this are
EM_A[2:1]. These signals (can be used to) represent the ALE and CLE signals for the NAND Flash mode
of the AEMIF and are always enabled. Note that EM_A[0] does not represent the lowest AEMIF address
bit. DM355 supports only 16-bit and 8-bit data widths for the AEMIF. In 16-bit mode, EM_BA[1] represents
the LS address bit (the half-word address) and EM_BA[0] represents the MS address bit (A[14]). In 8-bit
mode, EM_BA[1:0] represent the 2 LS address bits. Note that additional selections are available by
programming the PinMux2 register in software after boot. Note that AECFG selection of ‘0010’ selects
OneNAND interface. The AEMIF needs to operate in the half-rate mode (full_rate = 0) to meet frequency
requirements. Software should not change the PINMUX2 register setting to affect the AEMIF rate
operation. A soft reset of the AEMIF should be performed any time a rate change is made.
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Table 3-13. AECFG (Async EMIF Configuration) Pin Mux Coding
1101(NAND)
GPIO[54]
GPIO[55]
GPIO[56]
EM_A[1]
EM_A[2]
GPIO[57]
GPIO[58]
GPIO[59]
GPIO[60]
GPIO[61]
GPIO[62]
GPIO[63]
GPIO[64]
GPIO[65]
GPIO[66]
GPIO[67]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
1100
1010 (OneNAND)
EM_A[14]
EM_BA[1]
EM_A[0]
1000 (8-bit SRAM)
EM_BA[0]
EM_BA[1]
EM_A[0]
0010 (16-bit SRAM)
EM_A[14]
EM_BA[1]
EM_A[0]
0000
GPIO[54]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
EM_BA[0]
EM_BA[1]
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_D[8]
EM_D[9]
EM_D[10]
EM_D[11]
EM_D[12]
EM_D[13]
EM_D[14]
EM_D[15]
EM_A[1]
EM_A[1]
EM_A[1]
EM_A[2]
EM_A[2]
EM_A[2]
EM_A[3]
EM_A[3]
EM_A[3]
EM_A[4]
EM_A[4]
EM_A[4]
EM_A[5]
EM_A[5]
EM_A[5]
EM_A[6]
EM_A[6]
EM_A[6]
EM_A[7]
EM_A[7]
EM_A[7]
EM_A[8]
EM_A[8]
EM_A[8]
EM_A[9]
EM_A[9]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
GPIO[46]
GPIO[47]
GPIO[48]
GPIO[49]
GPIO[50]
GPIO[51]
GPIO[52]
GPIO[53]
EM_A[10]
EM_A[11]
EM_A[12]
EM_A[13]
EM_D[8]
EM_D[9]
EM_D[10]
EM_D[11]
EM_D[12]
EM_D[13]
EM_D[14]
EM_D[15]
3.9.2 Software Controlled Pin Multiplexing
All pin multiplexing options are configurable by software via pin mux registers that reside in the System
Control Module. The PinMux0 Register controls the Video In muxing, PinMux1 register controls Video Out
signals, PinMux2 register controls AEMIF signals, PinMux3 registers control the multiplexing of the GIO
signals, the PinMux4 register controls the SPI and MMC/SD0 signals. Refer to the ARM Subsystem User's
Guide for complete descriptions of the pin mux registers.
3.10 Device Reset
There are five types of reset in DM355. The types of reset differ by how they are initiated and/or by their
effect on the chip. Each type is briefly described in Table 3-14 and further described in the ARM
Subsystem Guide.
Table 3-14. Reset Types
Type
Initiator
Effect
POR (Power-On-Reset)
RESET pin low and TRST low
Total reset of the chip (cold reset). Resets all modules
including memory and emulation.
Warm Reset
RESET pin low and TRST high (initiated by ARM
emulator).
Resets all modules including memory, except ARM
emulation.
Max Reset
ARM emulator or Watchdog Timer (WDT).
ARM emulator
Same effect as warm reset.
System Reset
Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory
contents and does not affect or reset clocks or power
states.
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Table 3-14. Reset Types (continued)
Type
Module Reset
Initiator
Effect
ARM software
Resets a specific module. Allows the ARM to
independently reset any module. Module reset is
intended as a debug tool not as a tool to use in
production.
3.11 Default Device Configurations
After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the
default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF.
NOTE
Default configuration is the configuration immediately after POR, warm reset, and max
reset and just before the boot process begins. The boot ROM updates the configuration.
See Section 3.12 for more information on the boot process.
3.11.1 Device Configuration Pins
The device configuration pins are described in Table 3-15. The device configuration pins are latched at
reset and allow you to configure all of the following options at reset:
•
•
ARM Boot Mode
Asynchronous EMIF pin configuration
These pins are described further in the following sections.
NOTE
The device configuration pins are multiplexed with AEMIF pins. After the device
configuration pins are sampled at reset, they automatically change to function as AEMIF
pins. Pin multiplexing is described in Section 3.8.
Table 3-15. Device Configuration
Default Setting (by
internal
Device
Configuration Input
Sampled
Pin
pull-up/
pull-down)
Function
Device Configuration Affected
BTSEL[1:0]
Selects ARM boot mode
00 = Boot from ROM (NAND)
01 = Boot from AEMIF
10 = Boot from ROM
(MMC/SD)
EM_A[13:12]
00
(NAND)
If any ROM boot mode is selected, GIO61
is used to indicated boot status.
If NAND boot is selected, CE0 is used for
NAND. Use AECFG[3:0] to configure
AEMIF pins for NAND.
11 = Boot from ROM (UART)
If AEMIF boot is selected, CE0 is used for
AEMIF device (OneNAND, ROM). Use
AECFG[3:0] to configure AEMIF pins for
NAND.
If MMC/SD boot is selected, MMC/SD0 is
used.
AECFG[3:0]
Selects AEMIF pin
configuration
EM_A[11:8]
1101
(NAND)
Selects the AEMIF pin configuration. Refer
to pin-muxing information in Section 3.9.1.
Note that AECFG[3:0] affects both AEMIF
(BTSEL[1:0]=01) and NAND
(BTSEL[1:0]=00) boot modes.
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3.11.2 PLL Configuration
After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The
PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1
(typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.5
and Section 3.6. The default state of the PLLs is reflected in the default state of the register bits in the
PLLC registers. Refer the the ARM Subsystem User's Guide for PLLC register descriptions.
3.11.3 Power Domain and Module State Configuration
Only a subset of modules are enabled after reset by default. Table 3-16 shows which modules are
enabled after reset. Table 3-16 as shows that the following modules are enabled depending on the
sampled state of the device configuration pins: EDMA (CC and TC0), AEMIF, MMC/SD0, UART0, and
Timer0. For example, UART0 is enabled after reset when the device configuration pins (BTSEL[1:0] = 11 -
Enable UART) select UART boot mode. For more information on module configuration refer to the ARM
Subsystem User's Guide.
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Table 3-16. Module Configuration
Default States
Module
Number
Module Name
Power Domain
Power Domain State
Module State
0
1
2
VPSS Master
VPSS Slave
EDMA (CC)
AlwaysOn
AlwaysOn
AlwaysOn
ON
ON
ON
SyncRst
SyncRst
BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
SyncRst
3
EDMA (TC0)
AlwaysOn
ON
4
5
EDMA (TC1)
Timer3
SPI1
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
SyncRst
6
SyncRst
7
MMC/SD1
ASP1
SyncRst
8
SyncRst
9
USB
SyncRst
10
11
12
13
14
PWM3
SPI2
SyncRst
SyncRst
RTO
SyncRst
DDR EMIF
AEMIF
SyncRst
BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
15
MMC/SD0
AlwaysOn
ON
16
17
18
19
Reserved
ASP
AlwaysOn
AlwaysOn
AlwaysOn
ON
ON
ON
SyncRst
I2C
SyncRst
UART0
BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
20
21
22
23
24
25
26
27
UART1
UART2
SPI0
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
ON
ON
ON
ON
ON
ON
ON
ON
SyncRst
SyncRst
SyncRst
PWM0
PWM1
PWM2
GPIO
SyncRst
SyncRst
SyncRst
SyncRst
TIMER0
BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
SyncRst
28
29
30
TIMER1
TIMER2
AlwaysOn
AlwaysOn
AlwaysOn
ON
ON
ON
Enable
System Module
Enable
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Table 3-16. Module Configuration (continued)
Default States
31
32
33
34
35
36
37
38
39
40
ARM
BUS
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
AlwaysOn
Reserved
Always On
ON
ON
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Reserved
SyncRst
BUS
ON
BUS
ON
BUS
ON
BUS
ON
BUS
ON
BUS
ON
Reserved
VPSS DAC
Reserved
ON
3.11.4 ARM Boot Mode Configuration
The input pins BTSEL[1:0] determine whether the ARM will boot from its ROM or from the Asynchronous
EMIF (AEMIF). When ROM boot is selected (BTSEL[1:0] = 00, 10, or 11), a jump to the start of internal
ROM (address 0x0000: 8000) is forced into the first fetched instruction word. The embedded ROM boot
loader code (RBL) then performs certain configuration steps, reads the BOOTCFG register to determine
the desired boot method, and branches to the appropriate boot routine (i.e., a NAND, MMC/SD, or UART
loader routine).
If AEMIF boot is selected (BTSEL[1:0] = 01), a jump to the start of AEMIF (address 0x0200: 0000) is
forced into the first fetched instruction word. The ARM then continues executing from external
asynchronous memory using the default AEMIF timings until modified by software.
NOTE
For AEMIF boot, the OneNAND must be connected to the first AEMIF chip select space
(EM_CE0). Also, the AEMIF does not support direct execution from NAND Flash.
Boot modes are further described in Section 3.12.
3.11.5 AEMIF Configuration
3.11.5.1 AEMIF Pin Configuration
The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0]
to properly configure the pins of the AEMIF. Refer to the section on pin multiplexing in Section 3.9.
Also, see the Asynchronous External Memory Interface (AEMIF) Peripheral Reference Guide (SPRUEE8)
for more information on the AEMIF.
3.11.5.2 AEMIF Timing Configuration
When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is
88 cycles per access (16 cycles of setup, 64 cycles of strobe, and 8 cycles of hold). Thus, with a 24 MHz
clock at MXI, the AEMIF is configured to run at 6 MHz/88 which equals approximately 68 kHz by default.
See the Asynchronous External Memory Interface (AEMIF) Peripheral Reference Guide for more
information on the AEMIF.
3.12 Device Boot Modes
The DM355 ARM can boot from either Async EMIF (AEMIF/OneNand) or from ARM ROM, as determined
by the setting of the device configuration pins BTSEL[1:0]. The BTSEL[1:0] pins can define the ROM boot
mode further as well.
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The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, or
max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[1:0] = 01,
indicating AEMIF (AEMIF/OneNand) boot. See Section 3.11.1 for information on the boot selection pins.
3.12.1 Boot Modes Overview
DM355’s ARM ROM boot loader (RBL) executes when the BOOTSEL[1:0] pins indicate a condition other
than the normal ARM EMIF boot.
•
If BTSEL[1:0] = 01 - Asynchronous EMIF (AEMIF or NOR Flash) boot. This mode is handled by
hardware control and does not involve the ROM. In the case of OneNAND, the user is responsible for
putting any necessary boot code in the OneNAND's boot page. This code shall configure the AEMIF
module for the OneNAND device. After the AEMIF module is configured, booting will continue
immediately after the OneNAND’s boot page with the AEMIF module managing pages thereafter.
Furthermore, in case of Fast Boot from AEMIF/OneNAND, the user is responsible for checking the
state of the FASTBOOT bit in the BOOTCFG register in the System Module in order to respond
properly by executing any required device init, bringing mDDR out of self-refresh, and branching to
user entry point in mDDR.
•
The RBL supports 3 distinct boot modes:
–
–
–
BTSEL[1:0] = 00 - ARM NAND Boot
BTSEL[1:0] = 10 - ARM MMC/SD Boot
BTSEL[1:0] = 11 - ARM UART Boot
•
•
•
•
If NAND boot fails, then MMC/SD mode is tried.
If MMC/SD boot fails, then MMC/SD boot is tried again.
If UART boot fails, then UART boot is tried again.
RBL uses GIO61 to indicate boot status (can use to blink LED):
–
–
After reset, GIO61 is initially driven low (e.g LED off)
If NAND boot fails and then MMC/SD boot fails, then GIO61 shall toggle at 4Hz while MMC/SD
boot is retried.
–
–
–
If MMC/SD boot fails, then GIO61 shall toggle at 4Hz while MMC/SD boot is retried
If UART boot fails, then GIO61 shall toggle at 2Hz while UART boot is retried
When boot is successful, just before program control is given to UBL, GIO61 is driven high (e.g.
LED on)
–
DM355 Timer0 shall be used to accurately toggle GIO61 at 4Hz and 2Hz
•
ARM ROM Boot - NAND Mode
–
No support for a full firmware boot. Instead, copies a second stage user boot loader (UBL) from
NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL.
–
–
–
–
Support for NAND with page sizes up to 2048 bytes.
Support for magic number error detection and retry (up to 24 times) when loading UBL
Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack)
Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while
loading UBL)
–
–
–
–
Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported)
Supports 4-bit ECC (1-bit ECC is not supported)
Supports NAND flash that requires chip select to stay low during the tR read time
Supports Fast Boot option, which allows you to quickly boot and recover from a low power mode
•
ARM ROM Boot - MMC/SD Mode
–
No support for a full firmware boot. Instead, copies a second stage Uwer Boot Loader (UBL) from
MMC/SD to ARm Internal RAM (AIM) and transfers control to the user software.
–
–
Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported)
Support for descriptor error detection and retry (up to 24 times) when loading UBL
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–
Support for up to 30KB UBL (32KB - ~2KB for RBL stack)
•
ARM ROM Boot - UART mode
–
No support for a full firmware boot. Instead, loads a second stage user boot loader (UBL) via UART
to ARM internal RAM (AIM) and transfers control to the user software.
–
Support for up to 30KB UBL (32KB - ~2KB for RBL stack)
The general boot sequence is shown in Figure 3-6. For more information, refer to the ARM Subsystem
User's Guide.
Reset
Boot
mode
?
Internal ROM
Boot
mode
?
Boot from
UART
Boot from
NAND flash
No
No
Boot OK ?
Yes
Boot OK ?
Yes
Boot from
MMC/SD
No
Boot OK ?
Yes
Invoke
Nor Flash
Or OneNAND
Invoke loaded
Program
Figure 3-6. Boot Mode Functional Block Diagram
3.13 Power Management
The is designed for minimal power consumption. There are two components to power consumption: active
power and leakage power. Active power is the power consumed to perform work and scales with clock
frequency and the amount of computations being performed. Active power can be reduced by controlling
the clocks in such a way as to either operate at a clock setting just high enough to complete the required
operation in the required timeline or to run at a clock setting until the work is complete and then drastically
cut the clocks (e.g. to PLL Bypass mode) until additional work must be performed. Leakage power is due
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to static current leakage and occurs regardless of the clock rate. Leakage, or standby power, is
unavoidable while power is applied and scales roughly with the operating junction temperatures. Leakage
power can only be avoided by removing power completely from a device or subsystem. The DM355
includes several power management features which are briefly described in Table 12-1. Refer to the ARM
Subsystem User's Guide for more information on power management.
Table 3-17. Power Management Features
Power Management Features
Description
Clock Management
Module clock disable
Module clocks can be disabled to reduce switching power
Module clock frequency scaling
PLL power-down
Module clock frequency can be scaled to reduce switching power
The PLLs can be powered-down when not in use to reduce
switching power
ARM Sleep Mode
Disable ARM clock to reduce active power
System Sleep Modes
ARM Wait-for-Interrupt sleep mode
Deep Sleep mode
Stop all device clocks and power down internal oscillators to reduce
active power to a minimum. Registers and memory are preserved.
I/O Management
USB Phy power-down
The USB Phy can be powered-down to reduce USB I/O power
The DAC's can be powered-down to reduce DAC power
DAC power-down
DDR self-refresh and power down
The DDR / mDDR device can be put into self-refresh and power
down states
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3.14 64-Bit Crossbar Architecture
The DM355 uses a 64-bit crossbar architecture to control access between device processors, subsystems
and peripherals. It includes an EDMA Controller consisting of a DMA Transfer Controller (TC) and a DMA
Channel Controller (CC). The TC provides two DMA channels for transfer between slave peripherals. The
CC provides a user and event interface to the EDMA system. It includes up to 64 event channels to which
all system synchronization events can be mapped and 8 auto submit “quick” channels (QDMA). In most
ways, these channels are identical. A channel refers to a specific ‘event’ that can cause a transfer to be
submitted to the TC as a Transfer Request.
3.14.1 Crossbar Connections
There are five transfer masters (TCs have separate read and write connections) connected to the
crossbar; ARM, the Video Processing Sub-system (VPSS), the master peripherals (USB), and two EDMA
transfer controllers. These can be connected to four separate slave ports; ARM, the DDR EMIF, and CFG
bus peripherals. Not all masters may connect to all slaves. Connection paths are indicated by √ at
intersection points shown in Table 3-18
Table 3-18. Crossbar Connection Matrix
Slave Module
DMA Master
ARM Internal
Memory
MPEG/JPEG
Co-processor
Memory
Config Bus Registers and
Memory
DDR EMIF Memory
ARM
√
√
√
√
√
√
√
√
VPSS
DMA Master Peripherals (USB)
EDMA3TC0
√
√
√
√
√
√
√
EDMA3TC1
3.14.2 EDMA Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the DM355 device. These are summarized as follows:
•
•
Transfer to/from on-chip memories
–
–
ARM program/data RAM
MPEG/JPEG Co-processor memory
Transfer to/from external storage
–
–
–
–
–
DDR2 / mDDR SDRAM
Asynchronous EMIF
OneNAND flash
NAND flash
Smart Media, SD, MMC, xD media storage
•
Transfer to/from peripherals
–
–
–
–
–
–
–
–
–
ASP
SPI
I2C
PWM
RTO
GPIO
Timer/WDT
UART
MMC/SD
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The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel
Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event
interface for the EDMA system. The CC supports 64-event channels and 8 QDMA channels. The CC
consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering,
channel-chaining, auto-reloading, and memory protection.
The EDMA Channel Controller has the following features:
•
Fully orthogonal transfer description
–
–
–
–
–
Three transfer dimensions
A-synchronized transfers: one dimension serviced per event
AB- synchronized transfers: two dimensions serviced per event
Independent indexes on source and destination
Chaining feature allows 3-D transfer based on single event
•
Flexible transfer definition
–
–
–
Increment and constant addressing modes
Linking mechanism allows automatic PaRAM set update
Chaining allows multiple transfers to execute with one event
•
•
•
Interrupt generation for:
–
–
DMA completion
Error conditions
Debug visibility
–
–
Queue watermarking/threshold
Error and status recording to facilitate debug
64 DMA channels
–
–
–
Event synchronization
Manual synchronization (CPU(s) write to event set register)
Chain synchronization (completion of one transfer chains to next)
•
•
8 QDMA channels
–
–
QDMA channels are triggered automatically upon writing to a PaRAM set entry
Support for programmable QDMA channel to PaRAM mapping
128 PaRAM sets
Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)
–
•
•
•
Two transfer controllers/event queues. The system-level priority of these queues is user programmable
16 event entries per event queue
External events (for example, ASP TX Evt and RX Evt)
The EDMA Transfer Controller has the following features:
•
•
•
•
•
Two transfer controllers
64-bit wide read and write ports per channel
Up to four in-flight transfer requests (TR)
Programmable priority level
Supports two dimensional transfers with independent indexes on source and destination (EDMA3CC
manages the 3rd dimension)
•
•
Support for increment and constant addressing modes
Interrupt and error support
Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in
Parameter RAM (PaRAM) within the CC. DM355 provides 128 PaRAM entries, one for each of the 64
DMA channels and for 64 QDMA / Linked DMA entries.
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DMA Channels: Can be triggered by: " External events (for example, ASP TX Evt and RX Evt), " Software
writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaining to other DMAs.
QDMA: The Quick DMA (QDMA) function is contained within the CC. DM355 implements 8 QDMA
channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer. A QDMA
transfer is submitted immediately upon writing of the "trigger" parameter (as opposed to the occurrence of
an event as with EDMA). The QDMA parameter RAM may be written by any Config bus master through
the Config Bus and by DMAs through the Config Bus bridge.
QDMA Channels: Triggered by a configuration bus write to a designated 'QDMA trigger word'. QDMAs
allow a minimum number of linear writes (optimized for GEM IDMA feature) to be issued to the CC to
force a series of transfers to take place.
3.14.2.1 EDMA Channel Synchronization Events
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 3-19 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the device, the association of an event to a channel is fixed; each of the EDMA
channels has one specific event associated with it. These specific events are captured in the EDMA event
registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH).
For more detailed information on the EDMA module and how EDMA events are enabled, captured,
processed, linked, chained, and cleared, etc., see the Document Support section for the Enhanced Direct
Memory Access (EDMA) Controller Reference Guide.
Table 3-19. EDMA Channel Synchronization Events(1)(2)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0
1
2
3
4
5
6
7
TIMER3: TINT6
TIMER3 TINT7
ASP0: XEVT
ASP0: REVT
VPSS: EVT1
VPSS: EVT2
VPSS: EVT3
VPSS: EVT4
Timer 3 Interrupt (TINT6) Event
Timer 3 Interrupt (TINT7) Event
ASP0 Transmit Event
ASP0 Receive Event
VPSS Event 1
VPSS Event 2
VPSS Event 3
VPSS Event 4
ASP1: XEVT or TIMER2:
TINT4
8
9
ASP1 Transmit Event or Timer 2 interrupt (TINT4) Event
ASP1 Receive Event or Timer 2 interrupt (TINT5) Event
ASP1: REVT or TIMER2:
TINT5
10
11
12
13
14
15
16
17
18
19
20
SPI2: SPI2XEVT
SPI2: SPI2REVT
Reserved
SPI2 Transmit Event
SPI2 Receive Event
Reserved
SPI1: SPI1XEVT
SPI1: SPI1REVT
SPI0: SPI0XEVT
SPI0: SPI0REVT
UART0: URXEVT0
UART0: UTXEVT0
UART1: URXEVT1
SPI1 Transmit Event
SPI1 Receive Event
SP0I Transmit Event
SPI0 Receive Event
UART 0 Receive Event
UART 0 Transmit Event
UART 1 Receive Event
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or
intermediate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the Document Support
section for the Enhanced Direct Memory Access (EDMA) Controller Reference Guide.
(2) The total number of EDMA events in DM355 exceeds 64, which is the maximum value of the EDMA module. Therefore, several events
are multiplexed and you must use the register EDMA_EVTMUX in the System Control Module to select the event source for multiplexed
events. Refer to the ARM Subsystem Guide for more information on the System Control Module register EDMA_EVTMUX.
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Table 3-19. EDMA Channel Synchronization Events (continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
21
22
23
24
25
UART1: UTXEVT1
UART2: URXEVT2
UART2: UTXEVT2
Reserved
UART 1 Transmit Event
UART 2 Receive Event
UART 2 Transmit Event
GPIO: GPINT9
GPIO 9 Interrupt Event
MMC0RXEVT or MEMSTK:
MSEVT
26
MMC/SD0 Receive Event
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56 - 63
MMC0TXEVT
I2CREVT
MMC/SD0 Transmit Event
I2C Receive Event
I2CXEVT
I2C Transmit Event
MMC1RXEVT
MMC1TXEVT
GPINT0
MMC/SD1 Receive Event
MMC/SD1 Transmit Event
GPIO 0 Interrupt Event
GPIO 1 Interrupt Event
GPIO 2 Interrupt Event
GPIO 3 Interrupt Event
GPIO 4 Interrupt Event
GPIO 5 Interrupt Event
GPIO 6 Interrupt Event
GPIO 7 Interrupt Event
GPIO Bank 0 Interrupt Event
GPIO Bank 1 Interrupt Event
GPIO Bank 2 Interrupt Event
GPIO Bank 3 Interrupt Event
GPIO Bank 4 Interrupt Event
GPIO Bank 5 Interrupt Event
GPIO Bank 6 Interrupt Event
GPIO 8 Interrupt Event
Timer 0 Interrupt Event
Timer 1 Interrupt Event
Timer 2 Interrupt Event
Timer 3 Interrupt Event
PWM 0 Event
GPINT1
GPINT2
GPINT3
GPINT4
GPINT5
GPINT6
GPINT7
GPBNKINT0
GPBNKINT1
GPBNKINT2
GPBNKINT3
GPBNKINT4
GPBNKINT5
GPBNKINT6
GPINT8
TIMER0: TINT0
TIMER0: TINT1
TIMER1: TINT2
TIMER1: TINT3
PWM0
PWM1
PWM 1 Event
PWM2
PWM 2 Event
PWM3
PWM 3 Event
Reserved
3.15 MPEG/JPEG Overview
The DM355 supports the computational operations used for image processing, JPEG compression and
MPEG1,2,4 video and imaging standards.
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4 Device Operating Conditions
4.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(3)(4)
(Unless Otherwise Noted)
All 1.3 V supplies
-0.5 V to 1.7 V
-0.5 V to 2.5 V
-0.5 V to 1.89 V
-0.5 V to 4.4 V
-0.5 V to 2.3 V
-0.5 V to 3.8 V
0.0 V to 5.5 V
-20 mA to 20 mA
-0°C to 85 °C
All digital 1.8 V supplies
Supply voltage ranges
All analog 1.8 V supplies
All 3.3 V supplies
All 1.8 V I/Os
Input voltage ranges
All 3.3 V I/Os
VBUS
Iclamp
Clamp current for input or output(1)
Operating case temperature ranges
Storage temperature ranges
Tc
Tstg
-65°C to 150 °C
(3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(4) All voltage values are with respect to VSS.
(1) Clamp current flows from an input or output pad to a supply rail through a clamp circuit or an intrinsic diode. Positive current results from
an applied input or output voltage that is more than 0.5 V higher (more positive) than the supply voltage, VDD/VDD_PLL*/VDD_USB/VDD_DDR
for dual-supply macros. Negative current results from an applied voltage that is more than 0.5 V less (more negative) than the VSS
voltage..
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4.2 Recommended Operating Conditions
MIN NOM
1.235
MAX UNIT
CVDD
Supply voltage, Core
1.3
1.3
1.3
1.3
1.3
3.3
3.3
1.8
3.3
3.3
1.8
1.8
3.3
0
1.365
1.365
1.365
1.365
1.365
3.465
3.465
1.89
3.465
3.465
1.89
1.89
3.465
0
V
V
VDD_PLL1
VDD_PLL2
VDDD13_USB
VDDA13_USB
VDDA33_USB
VDDA33_USB_PLL
VDD_DDR
VDD_VIN
VDD_VOUT
VDDA18
Supply voltage, PLL1
1.235
1.235
1.235
1.235
3.135
3.135
1.71
3.135
3.135
1.71
1.71
3.135
0
Supply voltage, PLL2
V
Supply voltage, USB Digital
Supply voltage, USB Analog
Supply voltage, USB Analog
Supply voltage, USB Common PLL
Supply voltage, DDR2 / MDDR
Supply voltage, Digital video In
Supply voltage, Digital Video Out
Supply voltage, Analog
V
V
V
Supply Voltage
V
V
V
V
V
VDDA18_DAC
VDD
Supply voltage, DAC Analog
Supply voltage, I/Os
V
V
VSS
Supply ground, Core, USB Digital
Supply ground, PLL1
V
VSSA_PLL1
VSSA_PLL2
VSSA_USB
VSSA_DLL
VSSA
0
0
0
V
Supply ground, PLL2
0
0
0
V
Supply ground, USB
0
0
0
V
Supply Ground
Supply ground, DLL
0
0
0
V
Supply ground, Analog
0
0
0
V
VSSA_DAC
VSS_MX1
VSS_MX2
VIH
Supply ground, DAC Analog
MXI1 osc ground, PLL1(1)
MXI2 osc ground, PLL2(1)
High-level input voltage(2)
Low-level input voltage(2)
DAC reference voltage
0
0
0
V
0
0
0
V
0
0
0
V
Voltage Input High
Voltage Input Low
2
V
VIL
0.8
V
VREF
450
2550
499
mV
Ω
Ω
μF
RBIAS
DAC full-scale current adjust resistor
Output resistor
DAC(3)
RLOAD
CBG
Bypass capacitor
0.1
Output resistor (ROUT), between TVOUT and
VFB pins
ROUT
1070
Ω
Video Buffer(3)
RFB
Feedback resistor, between VFB and IOUT pins.
DAC full-scale current adjust resistor
Bypass capacitor
1000
2550
0.1
5
RBIAS
CBG
Ω
μA
V
USB_VBUS
R1
USB external charge pump input
USB reference resistor(4)
4.85
9.9
0
5.25
10.1
85
USB
10
kΩ
°C
Temperature
Tc
Operating case temperature rage
(1) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (see
Section 5.5.1).
(2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and
adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.
(3) See Section 5.9.2.4. Also, resistors should be E-96 spec line (3 digits with 1% accuracy).
(4) Connect USB_R1 to VSS_USB_REF via 10K ohm, 1% resistor placed as close to the device as possible. .
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4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
(1)
PARAMETER
High-level output voltage(2)
TEST CONDITIONS
VDD=MIN, IOH=MAX
VDD=MIN, IOL=MAX
MIN
TYP
MAX UNIT
VOH
VOL
2.4
Voltage
Output
V
Low-level output voltage(2)
0.6
Input current for I/O without
internal pull-up/pull-down
II
VI = VSS to VDD
VI = VSS to VDD
VI = VSS to VDD
-1
40
1
Input current for I/O with internal
pull-up(3)(4)
II(pullup)
190
Current
Input/Outp
ut
Input current for I/O with internal
pull-down(3)(4)
II(pulldown)
-190
-40
μA
IOH
IOL
High-level output current
Low-level output current
-100
4000
VO = VDD or VSS; internal pull
disabled
IOZ
I/O off-state output current
±10
CI
Input capacitance
Output capacitance
Resolution
4
4
Capacitan
ce
pF
CO
Resolution
10
1
Bits
RLOAD = 499 Ω, Video buffer
disabled
INL
Integral non-linearity, best fit
LSB
DAC
RLOAD = 499 Ω, Video buffer
disabled
DNL
Differential non-linearity
Output compliance range
0.5
LSB
V
Compliance
VOH(VIDBUF)
IFS = 1.4 mA, RLOAD = 499 Ω
0
0.700
Output high voltage (top of 75%
NTSC or PAL colorbar)(5)
1.55
Video
Buffer
V
Outpupt low voltage (bottom of
sync tip)
VOL(VIDBUF)
0.470
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and
adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.
(3) This specification applies only to pins with an internal pullup (PU) or pulldown (PD). See Section 2.4 or Section 2.5 for pin descriptions.
(4) To pull up a signal to the opposite supply rail, a 1 kΩ resistor is recommended.
(5) 100% color bars are not supported. 100% color bars require 1.2 V peak-to-peak. The video buffer only provides 1.0 V peak-to-peak.
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5 Peripheral Information and Electrical Specifications
5.1 Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 5-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
V
ref
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
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5.1.2 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
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5.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
5.3 Power Supplies
The power supplies of DM355 are summarized in Table 5-1.
Table 5-1. Power Supplies
Customer Tolerance Package
Chip Plane
Name
Description
Comments
Board
Plane
Supply
1.3 V
±5%
±5%
1.3 V
CVDD
Core VDD
VDDA_PLL1
VDDA_PLL2
VDDD13_USB
VDDA13_USB
VDD
PLL1 VDDA
PLL2 VDDA
USB 1.3 V supply
USB 1.3 V supply
3.3 V
3.3 V
IO VDD for LVCMOS
IO VDD for MXI/O1
VDDSHV
VDDSHV
VDDSHV1
VDDSHV2
VDD
VDD
IO VDD for MXI/O2
VDD
IO VDD for ISB DRVVBUS
DDR DLL analog VDD
Analog 3.3 V power USB PHY
VDDA33_DDRDLL
VDDA33_USB
VDDA33_USB_PLL Common mode 3.3 V power for USB
PHY (PLL)
VDD
IO VDD for peripherals
IO VDD for VideoIN I/F
IO VDD for VideoOUT I/F
3.3 V
±5%
3.3 V
VDD_VIN
VDD_VOUT
VDD_DDR
VDDA18
1.8 V
1.8 V
1.8 V
±5%
±5%
±5%
1.8 V
1.8 V
1.8 V
Analog 1.8 V power
VDDA18_DAC
Place decoupling caps (0.1μF/10μf) close
to chip
0 V
0 V
0 V
n/a
n/a
n/a
0 V
0 V
0 V
VSS_MX1
VSS_MX2
VSS
Connect to external crystal capacitor
ground
Connect to external crystal capacitor
ground
Chip ground
USB ESD ground
ground
VSS
0 V
0 V
0 V
0 V
0 V
n/a
n/a
n/a
n/a
n/a
0 V
0 V
0 V
0 V
0 V
VSSA
ground
Keep separate from digital ground VSS
VSA_PLL1
VSSA_PLL2
VSSA_DLL
VSS_USB
PLL1 VSSA
PLL2 VSSA
DLL ground
USB ground
VSSA13_USB
VSSA13_USB
VSSA33_USB
VSSA33_USB_PLL
0 V
0 V
n/a
n/a
0 V
0 V
VSS_USB_REF
VSSA_DAC
USB PHY reference ground
DAC ground
VSSREF
Keep separate from digital ground VSS
VDDS divided by 2, through board resistors
Connect to external charge pump
VDDS*0.5
5 V
VDDS*0.5 VREFSSTL
5 V USB_VBUS
DRR ref voltage
VBUS
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5.3.1 Power-Supply Sequencing
In order to ensure device reliability, the DM355 requires the following power supply power-on and
power-off sequences. See table Table 5-1 for a description of DM355 power supplies.
Power-On:
1. Power on 1.3 V: CVDD, VDDA_PLL1/2, VDDD13_USB, VDDA13_USB
2. Power on 1.8 V: VDD_DDR, VDDA18, VDDA18_DAC
3. Power on 3.3 V: DVDD, VDDA33_DDRDLL, VDDA33_USB, VDDA33_USBPLL, VDD_VIN, VDD_VOUT
You may power-on the 1.8 V and 3.3 V power supplies simultaneously.
Power-Off:
1. Power off 3.3 V: DVDD, VDDA33_DDRDLL, VDDA33_USB, VDDA33_USBPLL, VDD_VIN, VDD_VOUT
2. Power off 1.8 V: VDD_DDR, VDDA18, VDDA18_DAC
3. Power off 1.3 V: CVDD, VDDA_PLL1/2, VDDD13_USB, VDDA13_USB
You may power-off the 1.8 V and 3.3 V power supplies simultaneously.
Note that when booting the DM355 from OneNAND, you must ensure that the OneNAND device is ready
with valid program instructions before the DM355 attempts to read program instructions from it. In
particular, before you release DM355 reset, you must allow time for OneNAND device power to stabilize
and for the OneNAND device to complete its internal copy routine. During the internal copy routine, the
OneNAND device copies boot code from its internal non-volatile memory to its internal boot memory
section. Board designers typically achieve this requirement by design of the system power and reset
supervisor circuit. Refer to your OneNAND device datasheet for OneNAND power ramp and stabilization
times and for OneNAND boot copy times.
5.3.1.1 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DM355 to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the device, the PC board should include separate power planes for core, I/O, and ground, all
bypassed with high-quality low-ESL/ESR capacitors.
5.3.1.2 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to . These caps need to be close to the power pins, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps, such as 0402, are better because of their lower parasitic
inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF) should be
closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small
package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply be
placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the
"exterior".
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 μF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of
any component, verification of capacitor availability over the product’s production lifetime should be
considered. See also Section 5.5.1 and Section 5.5.2 for additional recommendations on power supplies
for the oscillator/PLL supplies.
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5.4 Reset
5.4.1 Reset Electrical Data/Timing
Table 5-2. Timing Requirements for Reset (1)(2) (see Figure 5-4)
DM355
NO.
UNIT
MIN
12C
12C
12C
MAX
1
2
3
tw(RESET)
tsu(BOOT)
th(BOOT)
Active low width of the RESET pulse
ns
ns
ns
Setup time, boot configuration pins valid before RESET rising edge
Hold time, boot configuration pins valid after RESET rising edge
(1) BTSEL[1:0] and AECFG[4:0] are the boot configuration pins during device reset.
(2) C = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 24 MHz use C = 41.6 ns.
1
RESET
2
3
Boot Configuration Pins
(BTSEL[1:0], AECFG[3:0])
Figure 5-4. Reset Timing
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5.5 Oscillators and Clocks
has two oscillator input/output pairs (MXI1/MXO1 and MXI2/MXO2) usable with external crystals or
ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 24 MHz
(MXI1/MXO1) and 27 MHz (MXI2/MXO2). Optionally, the oscillator inputs are configurable for use with
external clock oscillators. If external clock oscillators are used, to minimize the clock jitter, a single clean
power supply should power both the and the external oscillator circuit and the minimum CLKIN rise and
fall times must be observed. The electrical requirements and characteristics are described in this section.
The timing parameters for CLKOUT[3:1] are also described in this section. The has three output clock pins
(CLKOUT[3:1]). See Section 3.5 and Section 3.6 for more information on CLKOUT[3:1].
5.5.1 MXI1 (24-MHz) Oscillator
The MXI1 (typically 24 MHz, can also be 36 MHz) oscillator provides the primary reference clock for the
device. The on-chip oscillator requires an external crystal connected across the MXI1 and MXO1 pins,
along with two load capacitors, as shown in Figure 5-5. The external crystal load capacitors must be
connected only to the oscillator ground pin (VSS_MX1). Do not connect to board ground (VSS). Also, the PLL
power pin (VDDA_PLL1) should be connected to the power supply through a ferrite bead, L1 in the example
circuit shown in Figure 5-5.
MXO1
V
V
V
F
MXI1/CLKIN
SS_MX1
DDA_PLL1
SSA_PLL1
0.1
1
Crystal
24 MHz or
36 MHz
C1
C2
F
L1
Figure 5-5. MXI1 (24-MHz) Oscillator
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are
C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (MXI1 and MXO1) and to the VSS_MX1 pin.
C1C2
CL
(C1 C2)
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Table 5-3. Switching Characteristics Over Recommended Operating Conditions for 24-MHz System
Oscillator
PARAMETER
MIN
TYP
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency)
4
Oscillation frequency
ESR
24 or 36
MHz
Ω
60
Frequency stability
+/-50
ppm
5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator)
The MXI2 (27 MHz) oscillator provides an optional reference clock for the 's VPSS module. The on-chip
oscillator requires an external 27-MHz crystal connected across the MXI2 and MXO2 pins, along with two
load capacitors, as shown in Figure 5-6. The external crystal load capacitors must be connected only to
the 27-MHz oscillator ground pin (VSS_MX2). Do not connect to board ground (VSS). Also, the PLL power
pin (VDDA_PLL2) should be connected to the power supply through a ferrite bead, L1 in the example circuit
shown in Figure 5-6.
MXO2
V
V
V
SSA_PLL2
MXI2
SS_MX2
DDA_PLL2
Crystal
27 MHz
0.1
1
F
C1
C2
F
L1
Figure 5-6. MXI2 (27-MHz) System Oscillator
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are
C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (MXI and MXO) and to the VSS_MX2 pin.
C1C2
CL
(C1 C2)
Table 5-4. Switching Characteristics Over Recommended Operating Conditions for 27-MHz System
Oscillator
PARAMETER
MIN
TYP
MAX
UNIT
ms
Start-up time (from power up until oscillating at stable frequency)
4
Oscillation frequency
ESR
27
MHz
Ω
60
Frequency stability
+/-50
ppm
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5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 5-5. Timing Requirements for MXI1/CLKIN1(1)(2) (see Figure 5-7)
DM355
TYP
NO
.
UNIT
MIN
27.7(3)
0.45C
0.45C
MAX
1
2
3
4
5
tc(MXI1)
tw(MXI1H)
tw(MXI1L)
tt(MXI1)
Cycle time, MXI1/CLKIN1
41.6(3) ns
0.55C ns
0.55C ns
0.05C ns
0.02C ns
Pulse duration, MXI1/CLKIN1 high
Pulse duration, MXI1/CLKIN1 low
Transition time, MXI1/CLKIN1
Period jitter, MXI1/CLKIN1
tJ(MXI1)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.
(3) tc(MXI1) = 41.6 ns and tc(MXI1) = 27.7 ns are the only supported cycle times for MXI1/CLKIN1.
1
5
4
2
MXI/CLKIN
3
4
Figure 5-7. MXI1/CLKIN1 Timing
Table 5-6. Timing Requirements for MXI2/CLKIN2(1)(2) (see Figure 5-7)
NO.
DM355
UNIT
MIN
37.037(3)
0.45C
TYP
MAX
1
2
3
4
5
tc(MXI2)
tw(MXI2H)
tw(MXI2L)
tt(MXI2)
Cycle time, MXI2/CLKIN2
37.037(3) ns
0.55C ns
0.55C ns
0.05C ns
0.02C ns
Pulse duration, MXI2/CLKIN2 high
Pulse duration, MXI2/CLKIN2 low
Transition time, MXI2/CLKIN2
Period jitter, MXI2/CLKIN2
0.45C
tJ(MXI2)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = MXI2/CLKIN2 cycle time in ns. For example, when MXI2/CLKIN2 frequency is 27 MHz use C = 37.037 ns.
(3) tc(MXI2) = 37.037 ns is the only supported cycle time for MXI2/CLKIN2.
1
5
4
2
MXI/CLKIN
3
4
Figure 5-8. MXI2/CLKIN2 Timing
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Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1(1)(2) (see
Figure 5-9)
DM355
TYP
UNI
T
NO.
PARAMETER
MIN
MAX
1
2
3
4
tC(CLKOUT1)
tw(CLKOUT1H)
tw(CLKOUT1L)
tt(CLKOUT1)
Cycle time, CLKOUT1
tc(MXI1)
0.45P
0.45P
ns
ns
ns
ns
Pulse duration, CLKOUT1 high
Pulse duration, CLKOUT1 low
Transition time, CLKOUT1
0.55P
0.55P
0.05P
td(MXI1H-
CLKOUT1H)
td(MXI1L-
5
6
Delay time, MXI1/CLKIN1 high to CLKOUT1 high
Delay time, MXI1/CLKIN1I low to CLKOUT1 low
1
1
8
8
ns
ns
CLKOUT1L)
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.
(2) P = 1/CLKOUT1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is 24 MHz use P = 41.6 ns.
5
6
MXI/CLKIN
2
4
1
CLKOUT1
3
4
Figure 5-9. CLKOUT1 Timing
Table 5-8. Switching Characteristics Over Recommended Operating Conditions for CLKOUT2(1)(2) (see
Figure 5-10)
DM355
NO.
PARAMETER
UNIT
MIN
tc(MXI1) /3
0.45P
TYP
MAX
1
2
3
4
tC(CLKOUT2)
Cycle time, CLKOUT2
tw(CLKOUT2H) Pulse duration, CLKOUT2 high
tw(CLKOUT2L) Pulse duration, CLKOUT2 low
0.55P
0.55P
0.05P
ns
ns
ns
0.45P
tt(CLKOUT2)
Transition time, CLKOUT2
td(MXI1H-
CLKOUT2H)
td(MXI1L-
5
6
Delay time, MXI1/CLKIN1 high to CLKOUT2 high
1
1
8
8
ns
ns
Delay time, MXI1/CLKIN1 low to CLKOUT2 low
CLKOUT2L)
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.
(2) P = 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is 8 MHz use P = 125 ns.
MXI/CLKIN
5
6
2
4
1
CLKOUT2
3
4
Figure 5-10. CLKOUT2 Timing
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Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3(1)(2) (see
Figure 5-11)
DM355
NO.
PARAMETER
UNIT
MIN
tc(MXI1) /8
0.45P
TYP
MAX
1
2
3
4
tC(CLKOUT3)
tw(CLKOUT3H)
tw(CLKOUT3L)
tt(CLKOUT3)
Cycle time, CLKOUT3
Pulse duration, CLKOUT3 high
Pulse duration, CLKOUT3 low
Transition time, CLKOUT3
0.55P
0.55P
0.05P
ns
ns
ns
0.45P
td(MXI2H-
CLKOUT3H)
td(MXI2L-
5
6
Delay time, CLKIN/MXI high to CLKOUT3 high
Delay time, CLKIN/MXI low to CLKOUT3 low
1
1
8
8
ns
ns
CLKOUT3L)
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.
(2) P = 1/CLKOUT3 clock frequency in nanoseconds (ns). For example, when CLKOUT3 frequency is 3 MHz use P = 333.3 ns.
MXI/CLKIN
1
5
6
4
CLKOUT3
2
3
4
Figure 5-11. CLKOUT3 Timing
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5.6 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). There
are a total of 7 GPIO banks in the , because the has 104 GPIOs.
The GPIO peripheral supports the following:
•
•
Up to 104 3.3v GPIO pins, GPIO[103:0]
Interrupts:
–
–
–
Up to 10 unique GPIO[9:0] interrupts from Bank 0
Up to 7 GPIO (bank aggregated) interrupt signals, one from each of the 7 banks of GPIOs
Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
•
•
DMA events:
–
–
Up to 10 unique GPIO DMA events from Bank 0
Up to 7 GPIO (bank aggregated) DMA event signals, one from each of the 7 banks of GPIOs
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
For more detailed information on GPIOs, see the Documentation Support section for the General-Purpose
Input/Output (GPIO) Reference Guide.
5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing
Table 5-10. Timing Requirements for GPIO Inputs (see Figure 5-12)
DM355
NO.
UNIT
MIN
52
MAX
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
ns
ns
52
Table 5-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-12)
DM355
NO.
PARAMETER
UNIT
MIN
26(1)
26(1)
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
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2
1
GPIx
4
3
GPOx
Figure 5-12. GPIO Port Timing
5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 5-12. Timing Requirements for External Interrupts/EDMA Events(1) (see Figure 5-13)
DM355
NO.
UNIT
MIN
52
MAX
1
2
tw(ILOW)
tw(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
ns
ns
52
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have to recognize the GPIO
changes through software polling of the GPIO register, the GPIO duration must be extended to allow enough time to access the GPIO
register through the internal bus.
2
1
EXT_INTx
Figure 5-13. GPIO External Interrupt Timing
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5.7 External Memory Interface (EMIF)
supports several memory and external device interfaces, including:
•
•
•
Asynchronous EMIF (AEMIF) for interfacing to SRAM.
OneNAND flash memories
NAND flash memories
5.7.1 Asynchronous EMIF (AEMIF)
The EMIF supports the following features:
•
•
•
•
•
SRAM, etc. on up to 2 asynchronous chip selects addressable up to 64KB each
Supports 8-bit or 16-bit data bus widths
Programmable asynchronous cycle timings
Supports extended wait mode
Supports Select Strobe mode
5.7.1.1 NAND (NAND, SmartMedia, xD)
The NAND features of the EMIF are as follows:
•
•
•
•
•
NAND flash on up to 2 asynchronous chip selects
8 and 16-bit data bus widths
Programmable cycle timings
Performs 1-bit and 4-bit ECC calculation
NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
5.7.1.2 OneNAND
The OneNAND features supported are as follows.
•
•
•
•
NAND flash on up to 2 asynchronous chip selects
Only 16-bit data bus widths
Supports asynchronous writes and reads
Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads
with wrap burst modes)
•
Programmable cycle timings for each chip select in asynchronous mode
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5.7.1.3 AEMIF Electrical Data/Timing
Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module(1) (see Figure 5-14
and Figure 5-15)
DM355
Nom
NO
.
UNIT
MIN
MAX
READS and WRITES
Pulse duration, EM_WAIT assertion and
deassertion
2
tw(EM_WAIT)
2E
ns
READS
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high
5
0
ns
ns
13 th(EMOEH-EMDIV)
Hold time, EM_D[15:0] valid after EM_OE high
tsu(EMOEL-
EMWAIT)
Delay time from EM_OE low to EM_WAIT
asserted(2)
14
4E
ns
READS (OneNAND Synchronous Burst Read)
Setup time, EM_D[15:0] valid before EM_CLK
high
30 tsu(EMDV-EMCLKH)
4
4
ns
ns
31 th(EMCLKH-EMDIV) Hold time, EM_D[15:0] valid after EM_CLK high
WRITES
Delay time from EM_WE low to EM_WAIT
asserted(2)
tsu(EMWEL-
28
4E
ns
EMWAIT)
(1) E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example,
when PLLC output clock = 432 MHz, E = 9.259 ns. See Section 3.5 for more information.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 5-16 and Figure 5-17 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module(1)(2)(3) (see Figure 5-14 and Figure 5-15)
DM355
UNI
T
NO.
PARAMETER
MIN
Nom
MAX
READS and WRITES
READS
1
td(TURNAROUND)
Turn around time
(TA)*E
ns
EMIF read cycle time (EW = 0)
EMIF read cycle time (EW = 1)
(RS+RST+RH)*E
ns
ns
3
4
tc(EMRCYCLE)
(RS+RST+RH+(EWC*
16))*E
Output setup time, EM_CE[1:0] low to
EM_OE low (SS = 0)
(RS)*E
ns
ns
ns
ns
tsu(EMCEL-EMOEL)
Output setup time, EM_CE[1:0] low to
EM_OE low (SS = 1)
0
(RH)*E
0
Output hold time, EM_OE high to
EM_CE[1:0] high (SS = 0)
5
th(EMOEH-EMCEH)
Output hold time, EM_OE high to
EM_CE[1:0] high (SS = 1)
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256]. See the TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1)
for more information.
(2) E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example,
when PLLC output clock = 432 MHz, E = 9.259 ns. See Section 3.5 for more information
(3) EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320DM355 DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (SPRUED1) for more information.
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Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15) (continued)
DM355
UNI
T
NO.
PARAMETER
MIN
Nom
MAX
Output setup time, EM_BA[1:0] valid to
EM_OE low
6
7
8
9
tsu(EMBAV-EMOEL)
th(EMOEH-EMBAIV)
tsu(EMBAV-EMOEL)
th(EMOEH-EMAIV)
(RS)*E
ns
ns
ns
ns
Output hold time, EM_OE high to
EM_BA[1:0] invalid
(RH)*E
(RS)*E
(RH)*E
Output setup time, EM_A[13:0] valid to
EM_OE low
Output hold time, EM_OE high to
EM_A[13:0] invalid
EM_OE active low width (EW = 0)
EM_OE active low width (EW = 1)
(RST)*E
ns
ns
10 tw(EMOEL)
(RST+(EWC*16))*E
td(EMWAITH-
EMOEH)
Delay time from EM_WAIT deasserted to
EM_OE high
11
4E
ns
READS (OneNAND Synchronous Burst Read)
MH
z
32 fc(EM_CLK)
Frequency, EM_CLK
Cycle time, EM_CLK
1
66
33 tc(EM_CLK)
tsu(EM_AVDV-
15
1000 ns
Output setup time, EM_AVD valid before
EM_CLK high
34
35
36
37
5
6
5
6
ns
EM_CLKH)
th(EM_CLKH-
EM_AVDIV)
Output hold time, EM_CLK high to EM_AVD
invalid
ns
ns
ns
tsu(EM_AV-
EM_CLKH)
Output setup time, EM_A[13:0]/EM_BA[1]
valid before EM_CLK high
th(EM_CLKH-
EM_AIV)
Output hold time, EM_CLK high to
EM_A[13:0]/EM_BA[1] invalid
38 tw(EM_CLKH)
Pulse duration, EM_CLK high
Pulse duration, EM_CLK low
tc(EM_CLK)/3
tc(EM_CLK)/3
ns
ns
39 tw(EM_CLKL)
WRITES
EMIF write cycle time (EW = 0)
EMIF write cycle time (EW = 1)
(WS+WST+WH)*E
ns
ns
15 tc(EMWCYCLE)
(WS+WST+WH+(EW
C*16))*E
Output setup time, EM_CE[1:0] low to
EM_WE low (SS = 0)
(WS)*E
0
ns
ns
ns
ns
ns
ns
ns
ns
16 tsu(EMCEL-EMWEL)
Output setup time, EM_CE[1:0] low to
EM_WE low (SS = 1)
Output hold time, EM_WE high to
EM_CE[1:0] high (SS = 0)
(WH)*E
0
17 th(EMWEH-EMCEH)
Output hold time, EM_WE high to
EM_CE[1:0] high (SS = 1)
Output setup time, EM_BA[1:0] valid to
EM_WE low
20 tsu(EMBAV-EMWEL)
21 th(EMWEH-EMBAIV)
22 tsu(EMAV-EMWEL)
23 th(EMWEH-EMAIV)
(WS)*E
(WH)*E
(WS)*E
(WH)*E
Output hold time, EM_WE high to
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
EM_WE low
Output hold time, EM_WE high to
EM_A[13:0] invalid
EM_WE active low width (EW = 0)
EM_WE active low width (EW = 1)
(WST)*E
ns
ns
24 tw(EMWEL)
(WST+(EWC*16))*E
td(EMWAITH-
EMWEH)
Delay time from EM_WAIT deasserted to
EM_WE high
25
4E
ns
ns
Output setup time, EM_D[15:0] valid to
EM_WE low
26 tsu(EMDV-EMWEL)
(WS)*E
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Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module (see Figure 5-14 and Figure 5-15) (continued)
DM355
UNI
T
NO.
PARAMETER
MIN
Nom
MAX
Output hold time, EM_WE high to
EM_D[15:0] invalid
27 th(EMWEH-EMDIV)
(WH)*E
ns
3
1
EM_CE[1:0]
EM_BA[1:0]
EM_A[13:0]
4
8
5
9
7
6
10
EM_OE
13
12
EM_D[15:0]
EM_WE
Figure 5-14. Asynchronous Memory Read Timing for EMIF
15
1
EM_CE[1:0]
EM_BA[1:0]
EM_A[13:0]
16
18
20
22
17
19
21
23
24
EM_WE
27
26
EM_D[15:0]
EM_OE
Figure 5-15. Asynchronous Memory Write Timing for EMIF
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SETUP
STROBE
Extended Due to EM_WAIT
STROBE HOLD
EM_CE[1:0]
EM_BA[1:0]
EM_A[13:0]
EM_D[15:0]
11
EM_OE
14
2
2
EM_WAIT
Asserted
Deasserted
Figure 5-16. EM_WAIT Read Timing Requirements
SETUP
STROBE
Extended Due to EM_WAIT
STROBE HOLD
EM_CE[1:0]
EM_BA[1:0]
EM_A[13:0]
EM_D[15:0]
28
25
EM_WE
2
2
Asserted
Deasserted
EM_WAIT
Figure 5-17. EM_WAIT Write Timing Requirements
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33
38
EM_CLK
39
EM_CE[1:0]
EM_AVD
34
35
31
36
EM_BA0,
EM_A[13:0],
EM_BA1
30
Da
37
Da+n+1
EM_D[15:0]
EM_OE
Da+1
Da+2
Da+3
Da+4
Da+5
Da+n
EM_WAIT
Figure 5-18. Synchronous OneNAND Flash Read Timing
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5.7.2 DDR2 Memory Controller
The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports
JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
DDR2 / mDDR SDRAM plays a key role in a DM355-based system. Such a system is expected to require
a significant amount of high-speed external memory for all of the following functions:
•
•
•
•
Buffering of input image data from sensors or video sources
Intermediate buffering for processing/resizing of image data in the VPFE
Numerous OSD display buffers
Intermediate buffering for large raw Bayer data image files while performing image processing
functions
•
•
Buffering for intermediate data while performing video encode and decode functions
Storage of executable code for the ARM
The DDR2 / mDDR Memory Controller supports the following features:
•
•
•
•
•
JESD79D-2A standard compliant DDR2 SDRAM
Mobile DDR SDRAM
256 MByte memory space
Data bus width 16 bits
CAS latencies:
–
–
DDR2: 2, 3, 4, and 5
mDDR: 2 and 3
•
Internal banks:
–
–
DDR2: 1, 2, 4, and 8
mDDR: 1, 2, and 4
•
•
Burst length: 8
Burst type: sequential
•
•
•
•
•
•
•
•
•
•
1 CS signal
Page sizes: 256, 512, 1024, and 2048
SDRAM autoinitialization
Self-refresh mode
Partial array self-refresh (for mDDR)
Power down mode
Prioritized refresh
Programmable refresh rate and backlog counter
Programmable timing parameters
Little endian
For details on the DDR2 Memory Controller, refer to the DDR/mDDR Peripheral Reference Guide.
5.7.2.1 DDR2/mDDR Memory Controller Electrical Data/Timing
TI only supports DDR2/mDDR board designs that follow the guidelines described in the application note
titled TMS320DM355 DDR2 / mDDR Board Design Application Note. Refer to this application note for
information on board design recommendations and guidelines for DDR2 and mDDR.
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5.8 MMC/SD
The DM355 includes two separate MMC/SD Controllers which are compliant with MMC V3.31, Secure
Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V1.0
specifications.
The MMC/SD Controller has following features:
•
•
•
•
•
•
•
MultiMediaCard (MMC).
Secure Digital (SD) Memory Card.
MMC/SD protocol support.
SDIO protocol support.
Programmable clock frequency.
256 bit Read/Write FIFO to lower system overhead.
Slave EDMA transfer capability.
The MMC/SD Controller does not support SPI mode.
5.8.1 MMC/SD Electrical Data/Timing
Table 5-15. Timing Requirements for MMC/SD Module
(see Figure 5-20 and Figure 5-22)
DM355
FAST MODE STANDARD MODE UNIT
NO.
MIN
6
2.5(1)
MAX
MIN
5
MAX
1
2
3
4
tsu(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK high
ns
ns
ns
ns
th(CLKH-CMDV)
tsu(DATV-CLKH)
th(CLKH-DATV)
Hold time, SD_CMD valid after SD_CLK high
Setup time, SD_DATx valid before SD_CLK high
Hold time, SD_DATx valid after SD_CLK high
5
6
5
2.5
5
(1) For this parameter, you may include margin in your board design so that the toh = 2.5 ns of the MMC/SD device is not degraded at the
DM355 input pin.
Table 5-16. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 5-19 through Figure 5-22)
DM355
STANDARD
NO.
PARAMETER
FAST MODE
UNIT
MODE
MIN
0
MIN
0
MAX
MAX
7
8
9
f(CLK)
Operating frequency, SD_CLK
50
25 MHz
400 KHz
ns
f(CLK_ID)
tW(CLKL)
Identification mode frequency, SD_CLK
Pulse width, SD_CLK low
Pulse width, SD_CLK high
Rise time, SD_CLK
0
400
0
7
10
10 tW(CLKH)
11 tr(CLK)
12 tf(CLK)
7
10
ns
3
3
10 ns
10 ns
Fall time, SD_CLK
td(CLKL-
CMD)
13
Delay time, SD_CLK low to SD_CMD transition
-7.5
-7.5
4
4
-7.5
-7.5
14 ns
14 ns
14 td(CLKL-DAT) Delay time, SD_CLK low to SD_DATx transition
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10
9
7
SD_CLK
13
13
13
Valid
13
START
XMIT
Valid
Valid
END
SD_CMD
Figure 5-19. MMC/SD Host Command Timing
9
10
7
SD_CLK
SD_CMD
1
2
Valid
START
XMIT
Valid
Valid
END
Figure 5-20. MMC/SD Card Response Timing
10
9
7
SD_CLK
14
14
14
Dx
14
START
D0
D1
END
SD_DATx
Figure 5-21. MMC/SD Host Write Timing
9
10
7
SD_CLK
4
4
3
3
Start
SD_DATx
D0
D1
Dx
End
Figure 5-22. MMC/SD Host Read and Card CRC Status Timing
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5.9 Video Processing Sub-System (VPSS) Overview
The contains a Video Processing Sub-System (VPSS) that provides an input interface (Video Processing
Front End or VPFE) for external imaging peripherals such as image sensors, video decoders, etc.; and an
output interface (Video Processing Back End or VPBE) for display devices, such as analog SDTV
displays, digital LCD panels, HDTV video encoders, etc.
In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure
efficient use of the DDR2 burst bandwidth. The shared buffer logic/memory is a unique block that is
tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the primary
source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from/to
DDR2. In order to efficiently utilize the external DDR2 bandwidth, the shared buffer logic/memory
interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer logic/memory
also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared buffer
logic/memory (divided into the read & write buffers and arbitration logic) is capable of performing the
following functions. It is imperative that the VPSS utilize DDR2 bandwidth efficiently due to both its large
bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible to
configure the VPSS modules in such a way that DDR2 bandwidth is exceeded, a set of user accessible
registers is provided to monitor overflows or failures in data transfers.
5.9.1 Video Processing Front-End (VPFE)
The VPFE or Video Processing Front-End block is comprised of the CCD Controller (CCDC), Image Pipe
(IPIPE), Hardware 3A Statistic Generator (H3A), and CFA Multiply Mask / Lens Distortion Module
(CFALD). These modules are described in the sections that follow.
5.9.1.1 CCD Controller (CCDC)
The CCDC is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or
CCD). In addition, the CCDC can accept YUV video data in numerous formats, typically from so-called
video decoder devices. In the case of raw inputs, the CCDC output requires additional image processing
to transform the raw input image to the final processed image. This processing can be done either
on-the-fly in the Preview Engine hardware ISP or in software on the ARM and MPEG/JPEG co-processor
subsystems. In parallel, raw data input to the CCDC can also used for computing various statistics (3A,
Histogram) to eventually control the image/video tuning parameters. The CCDC is programmed via control
and parameter registers. DM355 performance is enhanced by its dedicated hard-wired MPEG/JPEG
co-processor (MJCP). The MJCP performs all the computational operations required for JPE and MPEG4
compression. These operations can be invoked using the xDM (xDIAS for Digital Media) APIs. For more
information, refer to the xDIAS-DM (xDIAS for Digital Media) User's Guide (SPRUEC8). The following
features are supported by the CCDC module.
•
•
•
•
Support for conventional Bayer pattern, movie mode VGA (e.g. Panasonic/Sony), and Foveon sensor
formats.
Support for the various movie mode formats is also provided via a data reformatter that transforms
from any specific sensor format to the Bayer format. This data reformatter is internal to the CCDC.
Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the
external timing generator.
Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware
support for higher number of fields, typically 3-, 4-, and 5-field sensors).
•
•
•
•
•
•
•
Support for up to 75 MHz sensor clock
Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8- or 16-bit).
Support for YCbCr 422 format, either 8- or 16-bit with discrete H and VSYNC signals.
Support for up to 14-bit input.
Support for color space conversion
Generates optical black clamping signals.
Support for shutter signal control.
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•
•
Support for digital clamping and black level compensation.
Fault pixel correction based on a lookup table that contains row and column position of the pixel to be
corrected.
•
•
•
Support for program lens shading correction.
Support for 10-bit to 8-bit A-law compression.
Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left
and right edges of each line are cropped from the output.
•
Support for generating output to range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in
storage area).
•
•
•
Support for down sampling via programmable culling patterns.
Ability to control output to the DDR2 via an external write enable signal.
Support for up to 32K pixels (image size) in both the horizontal and vertical direction.
5.9.1.2 IPIPE - Image Pipe
The hardware Image Pipe (IPIPE) is a programmable hardware image processing module that is
responsible for transforming raw (unprocessed) image/video data from a sensor (CMOS or CCD) into
YCbCr 422 data that is amenable for compression or display. The IPIPE can also be configured to operate
in a resize only mode, which allows YCbCr 422 to be resized without applying the processing of every
module in the IPIPE. Typically, the output of the IPIPE is used for both video compression and displaying
it on an external display device such as a NTSC/PAL analog encoder or a digital LCD. The IPIPE is
programmed via control and parameter registers. The following features are supported by the IPIPE.
•
The input interface extracts valid raw data from the CCD raw data, and then various modules in IPIPE
process the raw CCD data.
•
The 2D noise filter module reduces impulse noise in the raw data and adjusts the resolution of the
input image.
•
•
The 2D pre-filter adjusts the resolution of the input image and remove line crawl noise.
The white balance module applies two gain adjustments to the data: a digital gain (total gain) and a
white balance gain.
•
•
•
The Color Filter Array (CFA) interpolation module implements CFA interpolation. The output from the
CFA interpolation module is always RGB formatted data.
The RGB2RGB blending module applies a 3x3 matrix transform to the RGB data generated by the
CFA interpolation module.
The gamma correction module independently applies gamma correction to each RGB component.
Gamma is implemented using a piece-wise linear interpolation approach with a 512 entry look up table
for each color.
•
•
•
•
•
The RGB2YCbCr conversion module applies 3x3 matrix transformation to the RGB data to convert it to
YCbCr data. This module also implements offset.
The 4:2:2 conversion module applies the chroma low pass filter and down samples Cb and Cr, so that
IPIPE output data is in YCbCr-4:2:2 format.
The 2D edge enhancer module improves image clarity with luminance non-linear filter. This module
also has contrast and brightness adjustment functions.
The chroma suppression module reduces faulty-color using luminance (Y) value or high-pass-filtering Y
value. The H-resizer and V-resizer modules resize horizontal and vertical image sizes, respectively.
The output interface module transfers data from IPIPE to SDRAM, in the form of YCbCr-422 or RGB
(32bit/16bit).
•
•
•
•
The histogram function can record histograms of up to 4 distinct areas into up to 256 bins.
The boxcar function makes 1/8 or 1/16 size (1/64 or 1/256 in area) images.
The boundary signal calculator makes vectors of row and column summations.
IPIPE has four different processing paths:
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–
–
–
Case 1: The CCD raw data directly leads to IPIPE and stores the YCbCr (or RGB) data to SDRAM.
Case 2: IPIPE reads CCD raw data and stores the ayer data after white balance to SDRAM.
Case 3: IPIPE reads YCbCr-422 data and apply edge enhance, chroma suppression and Resize to
output YCbCr (or RGB) data to SDRAM.
–
Case 4: IPIPE reads CCD raw data and produces Boxcar data.
5.9.1.3 Hardware 3A (H3A)
The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto
Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the various
parameters for processing the imaging/video data. There are 2 main blocks in the H3A module:
•
•
Auto Focus (AF) engine
Auto Exposure (AE) Auto White Balance (AWB) engine
The AF engine extracts and filters the red, green, and blue data from the input image/video data and
provides either the accumulation or peaks of the data in a specified region. The specified region is a
two-dimensional block of data and is referred to as a "paxel" for the case of AF.
The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the
video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a "window".
Thus, other than referring them by different names, a paxel and a window are essentially the same thing.
However, the number, dimensions, and starting position of the AF paxels and the AE/AWB windows are
separately programmable.
The following features are supported by the AF engine:
•
•
•
•
•
•
Support for input from DDR2 / mDDR SDRAM (in addition to the CCDC port)
Support for a Peak Mode in a Paxel (a Paxel is defined as a two dimensional block of pixels).
Accumulate the maximum Focus Value of each line in a Paxel
Support for an Accumulation/Sum Mode (instead of Peak mode).
Accumulate Focus Value in a Paxel.
Support for up to 36 Paxels in the horizontal direction and up to 128 Paxels in the vertical direction.
The number of horizontal paxels is limited by the memory size (and cost), while the vertical number of
paxels is not. Therefore, the number of paxels in horizontal direction is smaller than the number of
paxels in vertical direction.
•
•
•
•
•
Programmable width and height for the Paxel. All paxels in the frame will be of same size.
Programmable red, green, and blue position within a 2x2 matrix.
Separate horizontal start for paxel and filtering.
Programmable vertical line increments within a paxel.
Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11
coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on.
The following features are supported by the AE/AWB engine:
•
•
•
•
•
•
Support for input from DDR2 / mDDR SDRAM (in addition to the CCDC port)
Accumulate clipped pixels along with all non-saturated pixels
Support for up to 36 horizontal windows.
Support for up to 128 vertical windows.
Programmable width and height for the windows. All windows in the frame will be of same size.
Separate vertical start co-ordinate and height for a black row of paxels that is different than the
remaining color paxels.
•
•
Programmable Horizontal Sampling Points in a window
Programmable Vertical Sampling Points in a window
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5.9.1.3.1 CFALD – CFA Multiply Mask / Lens Distortion Module
This hardware module, CFALD, contains two functions: lens distortion correction and CFA multiply mask.
The two functions share hardware components so only one can operate at a time. Lens geometric
distortion, or barrel distortion, refers to the warping of image contents typically at the corners of a captured
image. This is a common problem in digital photography, so being able to correct the distortion in
hardware enhances the value and competitiveness of a digital camera DSP device. The CFA multiply
mask function takes a down-sampled multiplication mask from external memory, and up-samples it to pixel
resolution to scale the corresponding pixels of a CFA image. CFA multiply mask is useful for lens shading
compensation and scene-dependent lighting adjustment. .
•
Lens distortion correction:
–
–
–
–
–
–
–
Correct barrel distortion
Radius-to-magnification-factor table to accommodate various distortion functions via programming
Configurable center point and horizontal/vertical adjustment
Separate lookup table for each color to correct chromatic aberration
Support CFA data format input/output for pre-image-pipe correction
Support up to 14-bit data input/output
Support up to 16383 x 16383 image dimension
•
CFA multiply mask:
–
–
–
–
Multiply mask in 8x8 down-sampled format
Support 8-bit mask (in U8Q5 format)
Support up to 14-bit image data input/output
Support up to 16383 x 16383 image dimension
5.9.1.3.2 Auto Exposure (AE) and Auto White Balance (AWB) Engine
The following features are supported by the Auto Exposure (AE) and Auto White Balance (AWB) Engine.
•
•
•
•
•
Accumulate clipped pixels along with all non-saturated pixels.
Up to 36 horizontal windows.
Up to 128 vertical windows.
Programmable width and height for the windows. All windows in the frame will be of same size.
Separate vertical start coordinate and height for a black row of paxels that is different than the
remaining color paxels.
•
•
Programmable Horizontal Sampling Points in a window.
Programmable Vertical Sampling Points in a window.
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5.9.1.4 VPFE Electrical Data/Timing
Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode (see Figure 5-23)
DM355
NO.
UNIT
MIN
13.33
5.7
MAX
1
2
3
4
tc(PCLK)
tw(PCLKH)
tw(PCLKL)
tt(PCLK)
Cycle time, PCLK
100
ns
ns
ns
ns
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
5.7
3
2
3
1
PCLK
4
4
Figure 5-23. VPFE PCLK Timing
Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24)
DM355
NO.
UNIT
MIN
3
MAX
5
6
tsu(CCDV-PCLK)
th(PCLK-CCDV)
tsu(HDV-PCLK)
th(PCLK-HDV)
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, HD valid before PCLK edge
Hold time, HD valid after PCLK edge
Setup time, VD valid before PCLK edge
Hold time, VD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
7
3
8
2
9
tsu(VDV-PCLK)
th(PCLK-VDV)
tsu(C_WEV-PCLK)
th(PCLK-C_WEV)
3
10
11
12
13
14
2
3
2
tsu(C_FIELDV-PCLK) Setup time, C_FIELD valid before PCLK edge
th(PCLK-C_FIELDV) Hold time, C_FIELD valid after PCLK edge
3
2
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PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
8, 10
7, 9
HD/VD
11, 13
12, 14
C_WE/C_FIELD
5
6
CI[7:0]/YI[7:0]/
CCD[13:0]
Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing
Table 5-19. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 5-25)
DM355
MIN
NO.
UNIT
MAX
15
16
23
24
tsu(CCDV-PCLK)
th(PCLK-CCDV)
tsu(CWEV-PCLK)
th(PCLK-CWEV)
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
3
2
3
2
ns
ns
ns
ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
(Positive Edge Clocking)
PCLK
(Positive Edge Clocking)
15
16
CI[7:0]/YI[7:0]/
CCD[13:0]
23
24
C_WE/C_FIELD
Figure 5-25. VPFE (CCD) Master Mode Input Data Timing
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Table 5-20. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode (see Figure 5-26)
DM355
NO.
PARAMETER
UNIT
MIN
3
MAX
11
18
20
td(PCLKL-HDIV)
td(PCLKL-VDIV)
Delay time, PCLK edge to HD invalid
Delay time, PCLK edge to VD invalid
ns
ns
3
11
PCLK
(Negative Edge Clocking)
PCLK
(Positive Edge Clocking)
18
20
HD
VD
Figure 5-26. VPFE (CCD) Master Mode Control Output Data Timing
5.9.2 Video Processing Back-End (VPBE)
The Video Processing Back-End of VPBE module is comprised of the On Screen Display (OSD) module
and the Video Encoder / Digital LCD Controller (VENC/DLCD).
5.9.2.1 On-Screen Display (OSD)
The primary function of the OSD module is to gather and blend video data and display/bitmap data and
then pass it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from
external DDR2/mDDR memory. The OSD is programmed via control and parameter registers. The
following are the primary features that are supported by the OSD.
•
Support for two video windows and two OSD bitmapped windows that can be displayed simultaneously
(VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1).
•
Video windows supports YCbCr data in 422 format from external memory, with the ability to
interchange the order of the CbCr component in the 32-bit word
•
•
OSD bitmap windows support 1/2/4/8 bit width index data of color palette
In addition one OSD bitmap window at a time can be configured to one of the following:
–
–
–
YUV422 (same as video data)
RGB format data in 16-bit mode (R=5bit, G=6bit, B=5bit)
24-bit mode (each R/G/B=8bit) with pixel level blending with video windows
•
Programmable color palette with the ability to select between a RAM/ROM table with support for 256
colors.
•
•
•
•
•
•
Support for 2 ROM tables, one of which can be selected at a given time
Separate enable/disable control for each window
Programmable width, height, and base starting coordinates for each window
External memory address and offset registers for each window
Support for x2 and x4 zoom in both the horizontal and vertical direction
Pixel-level blending/transparency/blinking attributes can be defined for OSDWIN0 when OSDWIN1 is
configured as an attribute window for OSDWIN0.
•
•
•
•
Support for blinking intervals to the attribute window
Ability to select either field/frame mode for the windows (interlaced/progressive)
An eight step blending process between the bitmap and video windows
Transparency support for the bitmap and video data (when a bitmap pixel is zero, there will be no
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blending for that corresponding video pixel)
•
•
•
•
•
Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows
Horizontal rescaling x1.5 is supported
Support for a rectangular cursor window and a programmable background color selection.
The width, height, and color of the cursor is selectable
The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 >
background color
•
Support for attenuation of the YCbCr values for the REC601 standard.
The following restrictions exist in the OSD module.
•
If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window
dimension cannot be greater than 720 currently. This is due to the limitation in the size of the line
memory.
•
It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM
while another uses ROM.
5.9.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)
The VENC/DLCD consists of three major blocks; a) the video encoder that generates analog video output,
b) the digital LCD controller that generates digital RGB/YCbCr data output and timing signals, and c) the
timing generator.
The video encoder for analog video supports the following features:
•
•
•
Master Clock Input - 27MHz (x2 Upsampling)
Programmable Timing Generator
SDTV Support
–
–
–
–
–
–
Composite NTSC-M, PAL-B/D/G/H/I
Non-Interlace option
CGMS/WSS
Line 21 Closed Caption Data Encoding
Chroma Low Pass Filter 1.5MHz/3MHz
Programmable SC-H phase
•
•
•
•
•
•
•
10-bit Over-Sampling D/A Converter (27MHz)
Internal analog video buffer
Optional 7.5% Pedestal
16-235/0-255 Input Amplitude Selectable
Programmable Luma Delay
Master/Slave Operation
Internal Color Bar Generation (75%)
The digital LCD controller supports the following features:
•
•
•
Programmable DCLK
Programmable Timing Generator
Various Output Format
–
–
–
–
–
YCbCr 16bit
YCbCr 8bit
ITU-R BT. 656
Parallel RGB 16-bit/18-bit
Serial 8-bit RGB
•
•
Low Pass Filter for Digital RGB Output
Master/Slave Operation
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•
•
Internal Color Bar Generation (100%/75%)
YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input
5.9.2.3 VPBE Electrical Data/Timing
Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27)
DM355
MIN
NO.
UNIT
ns
MAX
160
1
2
3
4
5
6
7
8
tc(PCLK)
Cycle time, PCLK
13.33
5.7
tw(PCLKH)
tw(PCLKL)
tt(PCLK)
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
ns
ns
ns
ns
ns
ns
ns
5.7
3
tc(EXTCLK)
tw(EXTCLKH)
tw(EXTCLKL)
tt(EXTCLK)
Cycle time, EXTCLK
13.33
5.7
160
Pulse duration, EXTCLK high
Pulse duration, EXTCLK low
Transition time, EXTCLK
5.7
3
3
7
1
5
2
6
PCLK
4
4
EXTCLK
8
8
Figure 5-27. VPBE PCLK and EXTCLK Timing
Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK(1)(2)(3) (see
Figure 5-28)
DM355
NO.
UNIT
MIN
2
MAX
9
tsu(VCTLV-VCLKIN)
th(VCLKIN-VCTLV)
Setup time, VCTL valid before VCLKIN edge
Hold time, VCTL valid after VCLKIN edge
ns
ns
10
1
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.
(2) VCTL = HSYNC, VSYNC, and FIELD
(3) VCLKIN = PCLK or EXTCLK
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(A)
VCLKIN
(Positive Edge Clocking)
(A)
VCLKIN
(Negative Edge Clocking)
10
9
(B)
VCTL
A. VCLKIN = PCLK or EXTCLK
B. VCTL = HSYNC, VSYNC, and FIELD
Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK
Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and EXTCLK(1)(2)(3) (see Figure 5-29)
DM355
NO.
PARAMETER
UNIT
MIN
2
MAX
11
12
13
14
td(VCLKIN-VCTLV)
td(VCLKIN-VCTLIV)
td(VCLKIN-VDATAV)
Delay time, VCLKIN edge to VCTL valid
Delay time, VCLKIN edge to VCTL invalid
Delay time, VCLKIN edge to VDATA valid
13.3
ns
ns
ns
ns
13.3
td(VCLKIN-VDATAIV) Delay time, VCLKIN edge to VDATA invalid
2
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.
(2) VCLKIN = PCLK or EXTCLK
(3) VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
(A)
VCLKIN
(Positive Edge Clocking)
(A)
VCLKIN
(Negative Edge Clocking)
11
13
12
14
(B)
VCTL
(C)
VDATA
A. VCLKIN = PCLK or EXTCLK
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:3], G[7:2], and B[7:3]
Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK
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Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK(1)(2) (see Figure 5-30)
DM355
NO.
PARAMETER
UNIT
MIN
13.33
5.7
MAX
17
18
19
20
21
22
23
24
25
26
tc(VCLK)
Cycle time, VCLK
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(VCLKH)
Pulse duration, VCLK high
tw(VCLKL)
Pulse duration, VCLK low
5.7
tt(VCLK)
Transition time, VCLK
3
12
12
4
td(VCLKINH-VCLKH)
td(VCLKINL-VCLKL)
td(VCLK-VCTLV)
td(VCLK-VCTLIV)
td(VCLK-VDATAV)
td(VCLK-VDATAIV)
Delay time, VCLKIN high to VCLK high
Delay time, VCLKIN low to VCLK low
Delay time, VCLK edge to VCTL valid
Delay time, VCLK edge to VCTL invalid
Delay time, VCLK edge to VDATA valid
Delay time, VCLK edge to VDATA invalid
2
2
0
4
0
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2) VCLKIN = PCLK or EXTCLK
(A)
VCLKIN
19
21
17
22
18
VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
20
23
25
20
24
26
(B)
VCTL
(C)
VDATA
A. VCLKIN = PCLK or EXTCLK
B. VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
C. VDATA = COUT[7:0], YOUT[7:0], R[7:3], G[7:2], and B[7:3]
Figure 5-30. VPBE Control and Data Output Timing With Respect to VCLK
5.9.2.4 DAC and Video Buffer Electrical Data/Timing
The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer
configuration. In the DAC only configuration the internal video buffer is not used and an external video
buffer is attached to the DAC. In the DAC and video buffer configuration, the DAC and internal video
buffer are both used and a TV cable may be attached directly to the output of the video buffer. See
Figure 5-31 and Figure 5-32 for recommenced circuits for each configuration.
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V
ideo DAC
Buffer
VREF
IBIAS
IOUT
VFB
TVOUT
C
BG
0.1 mF
R
BIAS
2550W
RLOAD
499W
DAC Digital Input
DAC Output Current
DIN <9:0>
MSB
Iout [mA]
1.4 mA
LSB
0
Example for External Circuit
A. Connect IOUT to a high-impedance video buffer device.
B. Place capacitors and resistors as close as possible to the DM355.
C. Configure the VDAC_CONFIG register in the system control module as follows: DINV = 0, PWD_GBZ = 1,
PWD_VBUFZ 0, ACCUP_EN X. See theTMS320DM355 ARM Subsystem Reference Guide and the
=
=
TMS320DM355 DMSoC Video Processing Back End (VPBE) User’s Guide for more information on VDAC_CONFIG.
Figure 5-31. DAC Only Application Example
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Video DAC and Buffer
IBIAS
VREF
IOUT
VFB
TVOUT
TV monitor
R
C
BG
0.1 mF
BIAS
2550 Ω
R
fb
= 1000 Ω
R
out
= 1070 Ω
DAC Digital Input
Video Buffer Output Voltage
TVOUT [V]
DIN <9:0>
MSB
VOH(VIDBUF)
VOL(VIDBUF)
LSB
0
A. Place capacitors and resistors as close as possible to the DM355.
B. You must use the circuit shown in this diagram. Also you must configure the VDAC_CONFIG register in the System
Control module as follows: TRESB4R4 = 0x3, TRESB4R2 = 0x8, TRESB4R1 = 0x8, TRIMBITS = 0x34, PWD_BGZ =
1 (power up VREF), SPEED = 1 (faster), TVINT = don't care, PWD_VBUFZ = 1 (power up video buffer), VREFSET =
don't care, ACCUP_EN = 0 (no A/C coupling), DINV = 1 (invert). See the TMS320DM355 ARM Subsystem Reference
Guide and the TMS320DM355 DMSoC Video Processing Back End (VPBE) User's Guide for more information on the
VDAC_CONFIG register and Video Buffer.
C. For proper TVOUT voltage, you must connect the pin TVOUT directly to the TV. No A/C coupling capacitor or
termination resistor is necessary on your DM355 board. Also, it is assumed that the TV has no internal A/C coupling
capacitor but does have an internal termination resistor, as shown in this diagram. TVOUT voltage will range from
VOL(VIDBUF) to VOH(VIDBUF). See Section 4.3 for the voltage specifications.
Figure 5-32. DAC With Buffer Circuit
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5.10 USB 2.0
DM355 includes a USB Controller Module that is built around the Mentor USB Multi-Point High-Speed
Dual Role Controller, endpoint memory, CPPI DMA controller and UTMI+ PHY. The controller conforms to
USB 2.0 Specification. The USB2.0 peripheral supports the following features:
•
•
•
•
•
USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
All transfer modes (control, bulk, interrupt, and isochronous)
Four Transmit (TX) and four Receive (RX) endpoints in addition to endpoint 0
FIFO RAM
–
–
4K endpoint
Programmable FIFO size
•
•
•
Connects to a standard UTMI+ PHY with a 60 MHz, 8-bit interface
Includes a DMA sub-module that supports four TX and four RX channels of CPPI 3.0 DMAs
RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
The USB2.0 peripheral does not support the following features:
•
•
•
•
•
•
USB OTG extensions, i.e. session request protocol (SRP) and host negotiation protocol (HNP)
On-chip charge pump
High bandwidth ISO mode is not supported (triple buffering)
16-bit 30 MHz UTMI+ interface is not supported
RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes
Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64,
and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined)
5.10.1 USB2.0 Electrical Data/Timing
Table 5-25. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 5-33)
DM355
LOW SPEED
1.5 Mbps
FULL SPEED
12 Mbps
HIGH SPEED(1)
480 Mbps
NO.
PARAMETER
UNIT
MIN
75
MAX
MIN
4
MAX
MIN
0.5
MAX
1
2
3
4
5
tr(D)
Rise time, USB_DP and USB_DM signals(2)
Fall time, USB_DP and USB_DM signals(2)
Rise/Fall time, matching(3)
Output signal cross-over voltage(2)
Source (Host) Driver jitter, next transition
Function Driver jitter, next transition
Source (Host) Driver jitter, paired transition(4)
Function Driver jitter, paired transition
Pulse duration, EOP transmitter
Pulse duration, EOP receiver
300
300
125
2
20
20
ns
ns
%
tf(D)
75
4
0.5
tfrfm
80
90 111.11
VCRS
1.3
1.3
2
2
V
tjr(source)NT
tjr(FUNC)NT
tjr(source)PT
tjr(FUNC)PT
tw(EOPT)
tw(EOPR)
t(DRATE)
2
ns
ns
ns
ns
ns
ns
25
2
6
1
1
10
1
7
8
9
1250
670
1500
160
82
175
Data Rate
1.5
–
12
480 Mb/s
49.5
10 ZDRV
Driver Output Resistance
–
28
49.5
40.5
Ω
(1) For more detailed specification information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(2) Low Speed: CL = 200 pF, Full Speed: CL = 50 pF, High Speed: CL = 50 pF
(3) tfrfm = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(4) tjr = tpx(1) - tpx(0)
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t t
per − jr
USB_DM
V
90% V
OH
CRS
10% V
OL
USB_DP
t
f
t
r
Figure 5-33. USB2.0 Integrated Transceiver Interface Timing
USB
USB_R1
10 K W 1ꢀ
VSS_USB_REF
Figure 5-34. USB Reference Resistor Routing
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5.11 Universal Asynchronous Receiver/Transmitter (UART)
The contains 3 separate UART modules (1 with hardware flow control). These modules performs
serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial
conversion on data received from the CPU. Each UART also includes a programmable baud rate
generator capable of dividing the 24MHz reference clock by divisors from 1 to 65,535 to produce a 16 x
clock driving the internal logic. The UART modules support the following features:
•
•
•
•
•
•
•
Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
16-byte storage space for both the transmitter and receiver FIFOs
Unique interrupts, one for each UART
Unique EDMA events, both received and transmitted data for each UART
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
Programmable auto-rts and auto-cts for autoflow control (supported on UART2)
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Modem control functions: CTS, RTS (supported on UART2)
5.11.1 UART Electrical Data/Timing
Table 5-26. Timing Requirements for UARTx Receive (see Figure 5-35)
DM355
NO.
UNIT
MIN
MAX
1.05U(1)
1.05U(1)
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (RXDn)
Pulse duration, receive start bit
0.99U(1)
0.99U(1)
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit
(see Figure 5-35)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
UART0/1 Maximum programmable baud rate
UART2 Maximum programmable baud rate
Pulse duration, transmit data bit (TXDn)
Pulse duration, transmit start bit
1.5
1
f(baud)
MHz
5
2
3
tw(UTXDB)
tw(UTXSB)
U - 2(1)
U - 2(1)
U + 2(1)
U + 2(1)
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
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3
2
Start
Bit
UART_TXDn
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 5-35. UART Transmit/Receive Timing
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5.12 Serial Port Interface (SPI)
The contains 3 separate SPI modules. These modules provide a programmable length shift register which
allows serial communication with other SPI devices through a 3 or 4 wire interface (Clock, Data In, Data
Out, and Enable). The SPI supports the following features:
•
•
•
•
•
•
•
•
•
•
•
•
Master mode operation
2 chip selects for interfacing to multiple slave SPI devices.
3 or 4 wire interface (Clock, Data In, Data Out, and Enable)
Unique interrupt for each SPI port
Separate DMA events for SPI Receive and Transmit
16-bit shift register
Receive buffer register
Programmable character length (2 to 16 bits)
Programmable SPI clock frequency range
8-bit clock prescaler
Programmable clock phase (delay or no delay)
Programmable clock polarity
The SPI modules do not support the following features:
•
Slave mode. Only Master mode is supported in DM355 (Master mode means that DM355 provides the
serial clock).
•
GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are
multiplexed with GPIO signals.
5.12.1 SPI Electrical Data/Timing
Table 5-28. Timing Requirements for SPI (All Modes)(1) (see Figure 5-36)
DM355
MIN
NO.
UNIT
MAX
1
2
3
tc(CLK)
Cycle time, SPI_CLK
37.037 ns
ns
ns
ns
tw(CLKH)
tw(CLKL)
Pulse duration, SPI_CLK high (All Master Modes)
Pulse duration, SPI_CLK low (All Master Modes
0.45*T
0.45*T
0.55*T
0.55*T
(1) T = tc(CLK) = SPI_CLK period is equal to the SPI module clock divided by a configurable divider.
1
2
3
SPIx_CLK
(Clock Polarity = 0)
SPIx_CLK
(Clock Polarity = 1)
Figure 5-36. SPI_CLK Timing
SPI Master Mode Timings (Clock Phase = 0)
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Table 5-29. Timing Requirements for SPI Master Mode [Clock Phase = 0] (1)(see Figure 5-37)
DM355
NO.
UNIT
MIN
MAX
Setup time, SPI_DI (input) valid before SPI_CLK (output)
falling edge
4
5
6
7
tsu(DIV-CLKL)
tsu(DIV-CLKH)
th(CLKL-DIV)
th(CLKH-DIV)
Clock Polarity = 0
Clock Polarity = 1
Clock Polarity = 0
Clock Polarity = 1
.5P + 3
ns
ns
ns
ns
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
rising edge
.5P + 3
.5P + 3
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
edge
2.5P + 3
(1) P = Period of the SPI module clock in nanoseconds (P = PLL1/6).
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 0] (see Figure 5-37)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, SPI_CLK (output) rising edge to SPI_DO
(output) transition
8
9
td(CLKH-DOV)
td(CLKL-DOV)
td(ENL-CLKH/L)
Clock Polarity = 0
Clock Polarity = 1
-4
5
ns
ns
ns
ns
Delay time, SPI_CLK (output) falling edge to SPI_DO
(output) transition
-4
5
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling
edge
(1)
10
11
2P(1)
P+.5C(2
(2)
td(CLKH/L-ENH) Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output) rising edge
)
(1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface
(SPI) User's Guide (SPRUED4).
(2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface
(SPI) User's Guide (SPRUED4).
11
SPI_EN
SPI_CLK
(Clock Polarity = 0)
10
SPI_CLK
(Clock Polarity = 1)
7
6
4
5
SPI_DI
(Input)
MSB IN
DATA
LSB IN
8
9
SPI_DO
(Output)
MSB OUT
DATA
LSB OUT
Figure 5-37. SPI Master Mode External Timing (Clock Phase = 0)
SPI Master Mode Timings (Clock Phase = 1)
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Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38)
DM355
NO.
UNIT
MIN
MAX
Setup time, SPI_DI (input) valid before SPI_CLK (output)
rising edge
13
14
15
16
tsu(DIV-CLKL)
tsu(DIV-CLKH)
th(CLKL-DIV)
th(CLKH-DIV)
Clock Polarity = 0
Clock Polarity = 1
Clock Polarity = 0
Clock Polarity = 1
.5P + 3
ns
ns
ns
ns
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
falling edge
.5P + 3
.5P + 3
.5P + 3
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
edge
Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 1] (see Figure 5-38)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, SPI_CLK (output) falling edge to SPI_DO
(output) transition
17
18
td(CLKL-DOV)
td(CLKH-DOV)
td(ENL-CLKH/L)
Clock Polarity = 0
Clock Polarity = 1
-4
5
ns
ns
Delay time, SPI_CLK (output) rising edge to SPI_DO
(output) transition
-4
5
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling
edge
2P+.5C
(1)
(2)
19
20
ns
ns
(1)
td(CLKL/H-DOHz) Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance
P(2)
(1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface
(SPI) User's Guide (SPRUED4).
(2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM355 DMSoC Serial Peripheral Interface
(SPI) User's Guide (SPRUED4).
SPI_EN
SPI_CLK
(Clock Polarity = 0)
19
SPI_CLK
(Clock Polarity = 1)
15
16
14
13
SPI_DI
(Input)
MSB IN
DATA
DATA
LSB IN
18
17
SPI_DO
(Output)
MSB OUT
LSB OUT
Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1)
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5.13 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an
I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data
to/from the DM355 through the I2C module.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
For more detailed information on the I2C peripheral, see the Documentation Support section for the
Inter-Integrated Circuit (I2C) Module Reference Guide.
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5.13.1 I2C Electrical Data/Timing
5.13.1.1 Inter-Integrated Circuits (I2C) Timing
Table 5-33. Timing Requirements for I2C Timings(1) (see Figure 5-39)
DM355
STANDARD
MODE
NO.
FAST MODE
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
μs
μs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
th(SCLL-SDAL)
μs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
μs
μs
ns
μs
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SDA-SCLL)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (For I2C bus™ devices)
250
0(3)
0(3) 0.9(4)
Pulse duration, SDA high between STOP and START
conditions
8
tw(SDAH)
4.7
1.3
μs
(5)
9
tr(SDA)
Rise time, SDA
1000 20 + 0.1Cb
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
300
ns
ns
ns
ns
μs
ns
pF
(5)
(5)
(5)
10
11
12
13
14
15
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
50
(5)
Cb
400
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
SCL
6
8
14
4
13
5
10
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 5-39. I2C Receive Timings
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Table 5-34. Switching Characteristics for I2C Timings(1) (see Figure 5-40)
DM355
STANDARD
MODE
NO.
PARAMETER
FAST MODE
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
μs
μs
Delay time, SCL high to SDA low (for a repeated START
condition)
td(SCLH-SDAL)
4.7
4
0.6
0.6
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
18
td(SDAL-SCLL)
μs
19
20
21
22
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
μs
μs
ns
μs
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SCLH)
tv(SCLL-SDAV)
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low (For I2C devices)
250
0
0.9
10
Pulse duration, SDA high between STOP and START
conditions
23
tw(SDAH)
4.7
4
1.3
0.6
μs
28
29
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
μs
10
pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
CAUTION
The DM355 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer
defined in the I2C specification. Series resistors may be necessary to reduce noise at
the system level.
SDA
SCL
21
23
19
28
20
16
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 5-40. I2C Transmit Timings
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5.14 Audio Serial Port (ASP)
DM355 includes two separate ASP controllers. The primary use for the audio serial port (ASP) is for audio
interface purposes. The primary audio modes that are supported by the ASP are the AC97 and IIS modes.
In addition to the primary audio modes, the ASP supports general serial port receive and transmit
operation, but is not intended to be used as a high-speed interface. The ASP is backward compatible with
other TI ASPs. The ASP supports the following features:
•
•
•
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability
is provided)
•
•
•
•
•
•
Direct interface to IIS compliant devices
A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits
μ-Law and A-Law commanding
8-bit data transfers with the option of LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
For more detailed information on the ASP peripheral, see the Documentation Support section for the
Audio Serial Port (ASP) Reference Guide.
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5.14.1 ASP Electrical Data/Timing
5.14.1.1 Audio Serial Port (ASP) Timing
Table 5-35. Timing Requirements for ASP(1) (see Figure 5-41)
DM355
NO.
UNIT
MIN
MAX
15
16
tc(CLK)
Cycle time, CLK
CLK ext
38.5 or 2P(2)(3)
19.25 or P(2)(3)(4)
ns
ns
OTG(CLKS)
Pulse duration, CLKR/X high or CLKR/X low
CLKS ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
21
6
5
6
tsu(FRH-CKRL)
th(CKRL-FRH)
tsu(DRV-CKRL)
th(CKRL-DRV)
tsu(FXH-CKXL)
th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
21
6
7
0
8
Hold time, DR valid after CLKR low
6
21
6
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
0
10
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(3) Use which ever value is greater.
(4) The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.
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Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(1)(2)
(see Figure 5-41)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
2
17
3
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
38.5 or 2P(3)(4)
ns
td(CLKS-CLKRX) Delay time, CLKS high to internal CLKR/X
1
C - 1
3
24
C + 1
25
tw(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
ns
ns
4
9
td(CKRH-FRV)
3
25
-4
8
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
ns
3
25
12
ns
ns
ns
ns
tdis(CKXH-
DXHZ)
Disable time, DX high impedance following last data
bit from CLKX high
12
13
12
-5
3
12
td(CKXH-DXV)
Delay time, CLKX high to DX valid
25
14(5)
Delay time, FSX high to DX valid
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
14
td(FXH-DXV)
ns
FSX ext
25(5)
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(4) Use which ever value is greater.
(5) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
16
15
16
CLKS
2
17
3
3
CLKR
4
4
FSR (int)
5
6
FSR (ext)
DR
7
8
Bit(n-1)
(n-2)
(n-3)
2
17
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX
(XDATDLY=00b)
(A)
13
14
(A)
13
Bit(n-1)
12
DX
Bit 0
(n-2)
(n-3)
A. Parameter No. 13 applies to the first data bitonly when XDATDLY ≠ 0.
Figure 5-41. ASP Timing
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Table 5-37. ASP as SPI Timing Requirements
CLKSTP = 10b, CLKXP = 0 (see Figure 5-42)
MASTER
NO.
UNIT
MIN
11
0
MAX
M30
M31
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
Table 5-38. ASP as SPI Switching Characteristics(1)(2)
CLKSTP = 10b, CLKXP = 0 (see Figure 5-42)
MASTER
MIN
NO.
PARAMETER
UNIT
MAX
38.5 or
M33
tc(CKX)
Cycle time, CLKX
ns
2P(1)(3)
T – 2
C – 2
–2
M24
M25
M26
M27
td(CKXL-FXH)
td(FXL-CKXH)
td(CKXH-DXV)
tdis(CKXL-DXHZ)
Delay time, CLKX low to FSX high(2)
Delay time, FSX low to CLKX high(4)
T + 3
C + 2
6
ns
ns
ns
ns
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last data bit from CLKX low
C – 3
C +3
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(2) T = BCLKX period = (1 + CLKGDV) × 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
CLKX
M33
M24
M25
FSX
M27
M26
(n-2)
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-3)
(n-4)
M30
M31
(n-2)
Bit 0
(n-4)
Figure 5-42. ASP as SPI: CLKSTP = 10b, CLKXP = 0
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Table 5-39. ASP as SPI Timing Requirements
CLKSTP = 11b, CLKXP = 0
MASTER
NO.
UNIT
MIN
11
1
MAX
M39
M40
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
Table 5-40. ASP as SPI Switching Characteristics(1)(2)
CLKSTP = 11b, CLKXP = 0 (see Figure 5-43)
MASTER
NO.
PARAMETER
UNIT
MIN
MAX
38.5 or
2P(1)(3)
M42
tc(CKX)
Cycle time, CLKX
ns
M34
M35
M36
td(CKXL-FXH)
td(FXL-CKXH)
td(CKXL-DXV)
Delay time, CLKX low to FSX high(4)
Delay time, FSX low to CLKX high(5)
Delay time, CLKX low to DX valid
C – 2
T – 2
–2
C + 3
T + 2
6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX low
M37
M38
tdis(CKXL-DXHZ)
td(FXL-DXV)
–3
3
ns
ns
Delay time, FSX low to DX valid
D – 2
D + 10
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(2) T = CLKX period = (1 + CLKGDV) × P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
CLKX
M42
M35
M34
FSX
DX
M37
M38
M39
M36
(n-2)
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-3)
(n-4)
M40
(n-2)
DR
Bit 0
(n-4)
Figure 5-43. ASP as SPI: CLKSTP = 11b, CLKXP = 0
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Table 5-41. ASP as SPI Timing Requirements
CLKSTP = 10b, CLKXP = 1 (see Figure 5-44)
MASTER
NO.
UNIT
MIN
11
0
MAX
M49
M50
tsu(DRV-CKXH)
th(CKXH-DRV)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
ns
ns
Table 5-42. ASP as SPI Switching Characteristics(1)(2)
CLKSTP = 10b, CLKXP = 1 (see Figure 5-44)
MASTER
NO.
PARAMETER
UNIT
MIN
MAX
38.5 or
2P(1)(3)
M52
tc(CKX)
Cycle time, CLKX
ns
M43
M44
M45
td(CKXH-FXH)
td(FXL-CKXL)
td(CKXL-DXV)
Delay time, CLKX high to FSX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX low to DX valid
T – 1
D – 2
–2
T + 3
D + 2
6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX high
M46
tdis(CKXH-DXHZ)
D – 3
D + 3
ns
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(2) T = CLKX period = (1 + CLKGDV) × P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
CLKX
M43
FSX
M44
M52
M46
M45
(n-2)
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
M49
M50
(n-2)
Bit 0
(n-3)
(n-4)
Figure 5-44. ASP as SPI: CLKSTP = 10b, CLKXP = 1
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Table 5-43. ASP as SPI Timing Requirements
CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)
MASTER
UNIT
NO.
MIN
11
0
MAX
M58
M59
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
Table 5-44. ASP as SPI Switching Characteristics(1)(2)
CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)
MASTER
MIN
NO.
PARAMETER
UNIT
MAX
38.5 or
M62
tc(CKX)
Cycle time, CLKX
ns
2P(3)(3)
D – 1
T – 2
–2
M53
M54
M55
td(CKXH-FXH)
td(FXL-CKXL)
td(CKXL-DXV)
Delay time, CLKX high to FSX high(4)
Delay time, FSX low to CLKX low(5)
Delay time, CLKX low to DX valid
D + 3
T + 2
6
ns
ns
ns
Disable time, DX high impedance following last data bit from
CLKX high
M56
M57
tdis(CKXH-DXHZ)
td(FXL-DXV)
– 3
+ 3
ns
ns
Delay time, FSX low to DX valid
C – 1
C + 10
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5) .
(2) T = CLKX period = (1 + CLKGDV) × P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
CLKX
M62
M53
M54
FSX
DX
M57
M56
M55
(n-2)
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
M58
M59
(n-2)
DR
Bit 0
(n-3)
(n-4)
Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1
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5.15 Timer
The contains four software-programmable timers. Timer 0, Timer 1, and Timer 3 (general-purpose timers)
can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode. Timer 3
supports additional features over the other timers: external clock/event input, period reload, output event
tied to Real Time Out (RTO) module, external event capture, and timer counter register read reset. Timer
2 is used only as a watchdog timer. Timer 2 is tied to device reset.
•
•
64-bit count-up counter
Timer modes:
–
–
–
64-bit general-purpose timer mode (Timer 0, 1, 3)
Dual 32-bit general-purpose timer mode (Timer 0, 1, 3)
Watchdog timer mode (Timer 2)
•
•
Two possible clock sources:
–
–
Internal clock
External clock/event input via timer input pins (Timer 3)
Three possible operation modes:
–
–
–
One-time operation (timer runs for one period then stops)
Continuous operation (timer automatically resets after each period)
Continuous operation with period reload (Timer 3)
•
•
•
•
•
Generates interrupts to the ARM CPU
Generates sync event to EDMA
Generates output event to device reset (Timer 2)
Generates output event to Real Timer Out (RTO) module (Timer 3)
External event capture via timer input pins (Timer 3)
For more detailed information, see the TMS320DM355 DMSoC 64-bit Timer User's Guide for more
information (SPRUEE5).
5.15.1 Timer Electrical Data/Timing
Table 5-45. Timing Requirements for Timer Input(1)(2)(3) (see Figure 5-46)
DM355
NO.
UNIT
MIN
4P
MAX
1
2
3
4
tc(TIN)
Cycle time, TIM_IN
ns
ns
ns
ns
tw(TINPH)
tw(TINPL)
tt(TIN)
Pulse duration, TIM_IN high
Pulse duration, TIM_IN low
Transition time, TIM_IN
0.45C
0.45C
0.55C
0.55C
0.05C
(1) GPIO000, GPIO001, GPIO002, and GPIO003 can be used as external clock inputs for Timer 3. See the TMS320DM355 DMSoC 64-bit
Timer User's Guide for more information (SPRUEE5).
(2) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
(3) C = TIM_IN cycle time in ns. For example, when TIM_IN frequency is 24 MHz use C = 41.6 ns
1
2
3
4
4
TIM_IN
Figure 5-46. Timer Input Timing
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5.16 Pulse Width Modulator (PWM)
The DM355 contains 4 separate Pulse Width Modulator (PWM) modules. The pulse width modulator
(PWM) feature is very common in embedded systems. It provides a way to generate a pulse periodic
waveform for motor control or can act as a digital-to-analog converter with some external components.
This PWM peripheral is basically a timer with a period counter and a first-phase duration comparator,
where bit width of the period and first-phase duration are both programmable. The Pulse Width Modulator
(PWM) modules support the following features:
•
•
•
32-bit period counter
32-bit first-phase duration counter
8-bit repeat count for one-shot operation. One-shot operation will produce N + 1 periods of the
waveform, where N is the repeat counter value.
•
•
•
Configurable to operate in either one-shot or continuous mode
Buffered period and first-phase duration registers
One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or
high-to-low).
•
One-shot operation triggerable by the CCD VSYNC output of the video processing subsystem (VPSS),
which allows any of the PWM instantiations to be used as a CCD timer. This allows the DM355 module
to support the functions provided by the DM320 CCD timer feature (generating strobe and shutter
signals).
•
•
•
One-shot operation generates N+1 periods of waveform, N being the repeat count register value
Configurable PWM output pin inactive state
Interrupt and EDMA synchronization events
5.16.1 PWM0/1/2/3 Electrical/Timing Data
Table 5-46. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2/3
Outputs(1) (see Figure 5-47 and Figure 5-48)
DM355
NO.
PARAMETER
UNIT
MIN
P
MAX
1
2
3
4
tw(PWMH)
tw(PWML)
Pulse duration, PWMx high
ns
ns
ns
ns
Pulse duration, PWMx low
P
tt(PWM)
Transition time, PWMx
.05P
10
td(CCDC-PWMV)
Delay time, CCDC(VD) trigger event to PWMx valid
(1) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
1
2
PWM0/1/2/3
3
3
Figure 5-47. PWM Output Timing
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VD(CCDC)
4
INVALID
VALID
PWM0
PWM1
4
INVALID
VALID
4
INVALID
VALID
PWM2
PWM3
4
INVALID
VALID
Figure 5-48. PWM Output Delay Timing
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5.17 Real Time Out (RTO)
The Real Time Out (RTO) peripheral supports the following features:
•
•
Four separate outputs
Trigger on Timer3 event
5.17.1 RTO Electrical/Timing Data
Table 5-47. Switching Characteristics Over Recommended Operating Conditions for RTO Outputs (see
Figure 5-49 and Figure 5-50)
DM355
NO.
PARAMETER
UNIT
MIN
P
MAX
1
2
3
4
tw(RTOH)
Pulse duration, RTOx high
ns
ns
ns
ns
tw(RTOL)
Pulse duration, RTOx low
P
tt(RTO)
Transition time, RTOx
.1P
10
td(TIMER3-RTOV)
Delay time, Timer 3 (TINT12 or TINT34) trigger event to RTOx valid
1
2
RTO0/1/2/3
3
3
Figure 5-49. RTO Output Timing
TINT12/TINT34
(Timer3)
4
RTO0
RTO1
INVALID
VALID
4
INVALID
VALID
4
INVALID
4
VALID
RTO2
RTO3
INVALID
VALID
Figure 5-50. RTO Output Delay Timing
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5.18 IEEE 1149.1 JTAG
The JTAG(1) interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, includes an internal pulldown (PD) on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to intialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations. Following the release of
RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The
EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed
information, see the terminal functions section of this data sheet.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
5.18.1 Scan Chain
The
DM355
scan
chain
information
is
as
follows:
ICEPick port Default TAP TAP IR bits
---------------------------------------------------------------------------
18 no c64x+ 38
17 no ETB 4
26 no ARM926 4
NOTE: This is assuming the EMU 0/1 pins are pulled high
ICEPick Boot Mode upon Power-on Reset
EMU1 EMU0 TAPs in the TDI>TDO path Other Effects
---------------------------------------------------------------------------
0 0 ICEPick + default TAP(s)
0 1 ICEPick Reserved
1 0 ICEPick Wait-in-reset
1 1 ICEPick Default condition
NOTES: ICDPick is always in the scan chain
Default TAPs are the ARM and the ETB
Notes: It is highly rrecommended that support for the default condition
be inmpemented. Going forward, TI will be moving to have only the
ICDPick in the scan chain, with no configuration with default TAP(s) is
in the scan chain. Thus, support for ICDPick and the ability to
configure the scan chain will be important.
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5.18.2 JTAG Test-Port Electrical Data/Timing
Table 5-48. Timing Requirements for JTAG Test Port (see Figure 5-51)
DM355
MIN MAX
NO.
UNIT
1
2
3
4
5
6
7
tc(TCK)
Cycle time, TCK
20
8
ns
ns
ns
ns
ns
ns
ns
tw(TCKH)
Pulse duration, TCK high
tw(TCKL)
Pulse duration, TCK low
8
tsu(TDIV-RTCKH)
th(RTCKH-TDIIV)
tsu(TMSV-RTCKH)
th(RTCKH-TMSIV)
Setup time, TDI valid before RTCK high
Hold time, TDI valid after RTCK high
Setup time, TMS valid before RTCK high
Hold time, TMS valid after RTCK high
10
9
2
5
1
2
3
TCK
RTCK
TDO
TDI
5
7
4
6
TMS
Figure 5-51. JTAG Input Timing
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Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-51)
DM355
NO.
PARAMETER
UNIT
MIN
MAX
8
9
tc(RTCK)
Cycle time, RTCK
20
10
10
ns
tw(RTCKH)
Pulse duration, RTCK high
Pulse duration, RTCK low
10 tw(RTCKL)
11 tr(all JTAG outputs) Rise time, all JTAG outputs
12 tf(all JTAG outputs) Fall time, all JTAG outputs
1.3
ns
ns
1.3
0.25*tc(RT
CK)
13 td(RTCKL-TDOV)
Delay time, TCK low to TDO valid
0
ns
8
9
10
RTCK
TDO
13
Figure 5-52. JTAG Output Timing
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6 Mechanical Data
The following table(s) show the thermal resistance characteristics for the PBGA – ZCE mechanical
package. Note that micro-vias are not required. Contact your TI representative for routing
recommendations.
6.1 Thermal Data for ZCE
The following table shows the thermal resistance characteristics for the PBGA – ZCE mechanical
package.
Table 6-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]
NO.
1
μC/W
TBD
TBD
TBD
TBD
TBD
AIR FLOW (m/s)(1)
RΘJC
RΘJB
RΘJA
PsiJT
PsiJB
Junction-to-case
TBD
TBD
TBD
TBD
TBD
2
Junction-to-board
Junction-to-free air
Junction-to-package top
Junction-to-board
3
4
5
(1) m/s = meters per second
6.1.1 Packaging Information
The following packaging information and reflect the most current data available for the designated device.
This data is subject to change without notice and without revision of this document. Note that micro-vias
are not required for this package.
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151
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