TMS320DM648CUTD7_技术文档

TMS320DM647/TMS320DM648

Digital Media Processor

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SPRS372–MAY 2007

1 TMS320DM647/TMS320DM648 Digital Media Processor

1.1 Features

•

High-Performance Digital Media Processor

(DM647/DM648)

•

C64x+ L1/L2 Memory Architecture

–

256K-bit (32K-byte) L1P Program Cache

[Direct Mapped]

256K-bit (32K-byte) L1D Data Cache

[2-Way Set-Associative]

2M-bit/256K-byte (DM647) or

4M-Bit/512K-byte) (DM648) L2 Unified

Mapped RAM/Cache [Flexible Allocation]

–

720, 900-MHz C64x+™ Clock Rate

1.39, 1.11-ns Instruction Cycle Time

5760, 7200 MIPS

Eight 32-Bit C64x+ Instructions/Cycle

Fully Software-Compatible With

C64x/Debug

•

Supports Little Endian Mode Only

Five Configurable Video Ports

–

Commercial Temperature Ranges

•

VelociTI.2™ Extensions to VelociTI™

Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x+™ DSP Core

–

Providing a Glueless I/F to Common Video

Decoder and Encoder Devices

–

Supports Multiple Resolutions/Video Stds

–

Eight Highly Independent Functional Units

With VelociTI.2 Extensions:

•

VCXO Interpolated Control Port (VIC)

Supports Audio/Video Synchronization

External Memory Interfaces (EMIFs)

•

Six ALUs (32-/40-Bit), Each Supports

Single 32-bit, Dual 16-bit, or Quad 8-bit

Arithmetic per Clock Cycle

–

32-Bit DDR2 SDRAM Memory Controller

With 256M-Byte Address Space (1.8-V I/O)

Asynchronous 16-Bit Wide EMIF (EMIFA)

With up to 64M-Byte Address Reach

Glueless Interface to Asynchronous

Memories (SRAM, Flash, and EEPROM)

Synchronous Memories (SBSRAM and ZBT

SRAM)

•

Two Multipliers Support Four 16 x 16-bit

Multiplies (32-bit Results) per Clock

Cycle or Eight 8 x 8-bit Multiplies (16-Bit

Results) per Clock Cycle

–

Load-Store Architecture With Non-Aligned

Support

64 32-bit General-Purpose Registers

Instruction Packing Reduces Code Size

All Instructions Conditional

–

Supports Interface to Standard Sync

Devices and Custom Logic (FPGA, CPLD,

ASICs, etc)

Additional C64x+™ Enhancements

•

Protected Mode Operation

Exceptions Support for Error Detection

and Program Redirection

•

Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

•

3-Port Gigabit Ethernet Switch

•

Hardware Support for Modulo Loop

Auto-Focus Module Operation

Four 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

•

C64x+ Instruction Set Features

•

One UART (With RTS and CTS Flow Control)

–

Byte-Addressable (8-/16-/32-/64-bit Data)

8-bit Overflow Protection

Bit-Field Extract, Set, Clear

Normalization, Saturation, Bit-Counting

VelociTI.2 Increased Orthogonality

C64x+ Extensions

One 4-wire Serial Port Interface (SPI) With Two

Chip-Selects

•

Master/Slave Inter-Integrated Circuit (I2C

Bus™)

Multichannel Audio Serial Port (McASP)

•

Compact 16-bit Instructions

Additional Instructions to Support

Complex Multiplies

– Ten Serializers and SPDIF (DIT) Mode

•

16/32-Bit Host-Port Interface (HPI)

32-Bit 33-/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface

Conforms to PCI Specification 2.3

•

VLYNQ™ Interface (FPGA Interface)

On-Chip ROM Bootloader

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

PRODUCT PREVIEW information concerns products in the

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

TMS320DM647/TMS320DM648

Digital Media Processor

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SPRS372–MAY 2007

•

Individual Power-Saving Modes

Flexible PLL Clock Generators

–

529-pin nFBGA (ZUT suffix)

19x19 mm 0.8 mm pitch BGA

0.09-µm/6-Level Cu Metal Process (CMOS)

IEEE-1149.1 (JTAG™)

•

3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -900)

Applications:

Boundary-Scan-Compatible

•

32 General-Purpose I/O (GPIO) Pins

(Multiplexed With Other Device Functions)

–

Digital Video Recording

Package:

1.1.1 Trademarks

TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are

trademarks of Texas Instruments.

I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.

Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.

All trademarks are the property of their respective owners.

1.2 Description

The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the

highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The

DM647/DM648 devices are based on the third-generation high-performance, advanced VelociTI™

very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs

an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from

previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added

functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and

C64x+ CPU, respectively.

With performance of up to 7200 million instructions per second (MIPS) at a clock rate of 900 MHz, the

C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses

the operational flexibility of high-speed controllers and the numerical capability of array processors. The

C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly

independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The

eight functional units include instructions to accelerate the performance in video and imaging applications.

The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million

MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details

on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide

(literature number SPRU732).

The DM647/DM648 devices also have application-specific hardware logic, on-chip memory, and additional

on-chip peripherals similar to the other C6000 DSP platform devices. The DM647/DM648 core uses a

two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache

and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache

(L2) consists of a 4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and

data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: The DM647/DM648 devices have five configurable 16-bit video port

peripherals (VP0, VP1, VP2, VP3, and VP4). These video port peripherals provide a glueless interface to

common video decoder and encoder devices. The DM647/DM648 video port peripherals support multiple

resolutions and video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and

296M), a VCXO interpolated control port (VIC); a 1000 Mbps 3-port switch with a management data

input/output (MDIO) module and two SGMII ports (DM648 only); an 1000 Mbps Ethernet media access

controller (EMAC) and a management data input/output (MDIO) module (only DM647); a 4-bit transmit,

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Digital Media Processor

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4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel audio serial

port (McASP) with ten serializers; four 64-bit general-purpose timers each configurable as two

independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port interface (HPI); 32 pins for

general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed

with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and

asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher DDR2

SDRAM interface.

The video port peripherals provide a glueless interface to common video decoder and encoder devices.

The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,

BT.1120, SMPTE 125M, 260M, 274M, and 296M).

The video port peripherals are configurable and can support either video capture and/or video display

modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is

splittable between the two channels.

For more details on the video port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated

Control (VIC) Port Reference Guide (literature number SPRU629).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to

enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with

host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

The DM647/DM648 devices have a complete set of development tools. These include C compilers, a DSP

assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for

visibility into source code execution.

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Digital Media Processor

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1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the DM647/DM648 device.

DM647/DM648

Timers

(4 64-bit

or 8 32-bit)

PCI66

or

PLL

JTAG

EDMA 3.0

UHPI

CC

3-port Ethernet

Switch

Subsystem

GPIO x32

TC

SGMII

(x2, DM648)

(x1, DM647)

VIC

VLYNQ

Switched Central Resource

DDR2

EMIFA 16-bit

Video Ports (5)

McASP

L2 RAM

L1D 32KB

256KB

(DM647)

512KB

C64x+

UART

(DM648)

Mega

SPI

L2 ROM

64KB

L1P 32KB

I2C

Imaging Coprocessor

Figure 1-1. TMS320DM647/TMS320DM648 Functional Block Diagram

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Contents

1

2

TMS320DM647/TMS320DM648 Digital Media

6

Peripheral Information and Electrical

Processor.................................................. 1

1.1 Features .............................................. 1

1.1.1 Trademarks .......................................... 2

1.2 Description............................................ 2

1.3 Functional Block Diagram ............................ 4

Device Overview ......................................... 6

2.1 Device Characteristics................................ 6

2.2 CPU (DSP Core) Description......................... 7

2.3 C64x+ CPU.......................................... 10

2.4 Memory Map Summary ............................. 12

2.5 Pin Assignments .................................... 15

2.6 Terminal Functions.................................. 19

2.7 Device Support ...................................... 33

Specifications ........................................... 56

6.1 Parameter Information .............................. 56

6.2

Recommended Clock and Control Signal Transition

Behavior ............................................. 58

6.3 Power Supplies...................................... 58

6.4 PLL1 and PLL1 Controller........................... 63

6.5 PLL2 and PLL2 Controller........................... 67

6.6

Enhanced Direct Memory Access (EDMA3)

Controller ............................................ 70

6.7 Reset Controller ..................................... 83

6.8 Interrupts ............................................ 90

6.9 DDR2 Memory Controller ........................... 94

6.10 External Memory Interface A (EMIFA) .............. 96

6.11 Video Port.......................................... 104

2.8

Device and Development-Support Tool

6.12 VCXO Interpolated Control (VIC) .................. 112

6.13 Universal Asynchronous Receiver/Transmitter

(UART) ............................................. 114

6.14 Inter-Integrated Circuit (I2C) ....................... 116

6.15 Host-Port Interface (HPI) Peripheral............... 120

Nomenclature ....................................... 35

2.9 Documentation Support ............................. 36

Device Configuration .................................. 38

3.1 System Module Registers ........................... 38

3.2 Bootmode Registers ................................ 38

3.3 Debugging Considerations .......................... 47

3.4 Pullup/Pulldown Resistors........................... 47

System Interconnect................................... 49

3

6.16 Peripheral Component Interconnect (PCI)......... 131

6.17 Multichannel Audio Serial Port (McASP)

Peripheral .......................................... 136

4

5

6.18 3-Port Ethernet Switch Subsystem (3PSW) ....... 144

6.19 Management Data Input/Output (MDIO)........... 153

6.20 Timers.............................................. 155

6.21 VLYNQ Peripheral ................................. 157

6.22 General-Purpose Input/Output (GPIO)............. 160

6.23 IEEE 1149.1 JTAG................................. 163

Mechanical Data....................................... 165

7.1 Thermal Data for ZUT.............................. 165

7.1.1 Packaging Information............................. 165

4.1

Internal Buses, Bridges, and Switch Fabrics........ 49

4.2 Data Switch Fabric Connections .................... 49

4.3 Configuration Switch Fabric ......................... 51

Device Operating Conditions ........................ 53

5.1

Absolute Maximum Ratings Over Operating

Temperature Range (Unless Otherwise Noted)..... 53

7

5.2 Recommended Operating Conditions............... 54

5.3

Electrical Characteristics Over Recommended

Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted) ............ 55

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Digital Media Processor

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2 Device Overview

2.1 Device Characteristics

Table 2-1, provides an overview of the TMS320DM647/TMS320DM648 DSPs. The tables show significant

features of the DM647/DM648 devices, including the capacity of on-chip RAM, the peripherals, the CPU

frequency, and the package type with pin count.

Table 2-1. Characteristics of the DM647/DM648 Processor

HARDWARE FEATURES

DM647

DM648

DDR2 memory controller (32-bit bus

width) [1.8 V I/O]

1

16-bit bus width

synchronous/asynchronous EMIF

[EMIFA]

1

EDMA3 (64 independent channels, 8

QDMA channels)

4 64-bit General Purpose

(each configurable as 1 64-bit or 2

32-bit)

4 64-bit General Purpose

(each configurable as 1 64-bit or 2

32-bit)

Timers

UART

I2C

(with RTS and CTS flow control)

1 (Master/Slave)

(with RTS and CTS flow control)

1 (Master/Slave)

Peripherals

Not all peripheral

pins are available

at the same time

(For more detail,

see Section 3.)

SPI

1 (4-wire, 2 chip select)

1 (10 serailizers)

1 (4-wire, 2 chip select)

1 (10 serailizers)

McASP

3-port Ethernet Switch Subsystem

supporting 10/100/1000 Base-T

1 SGMII port available

2 SGMII ports available

Management data input/output (MDIO)

VLYNQ

1

General-purpose input/output port

(GPIO)

Up to 32 pins

HPI (16/32-bit)

1

PCI (32 bit) (33 MHz or 66 MHz)

VIC

1 (PCI33 or PCI66)

1

Configurable video ports

Size (bytes)

5

320KB RAM, 64KB ROM

576KB RAM, 64KB ROM

32KB L1 program (L1P)/cache (Cache 32KB L1 program (L1P)/cache (up to

up to 32KB) 32KB)

32KB L1 data (L1D)/cache (Cache up 32KB L1 data (L1D)/cache (up to

On-Chip Memory

Organization

to 32KB)

32KB)

256KB unified mapped RAM/Cache

512 KB unified mapped RAM/Cache

(L2)

64KB Boot ROM

Revision ID Register

(MM_REVID[15:0])

(address location 0x0181 2000)

MegaModule Rev

ID

0x0003

CPU ID + CPU

Rev ID

Control Status Register (CSR.[31:16])

0x1000

JTAGID register

(address location: 0x0204 9018)

JTAG BSDL_ID

0x0B77 A02F

CPU Frequency

Cycle Time

MHz

720, 900

ns

1.39 ns (-720), 1.11 ns (-900)

1.2 V (-720, 900)

1.39 ns (-720), 1.11 ns (-900)

1.2 V (-720, 900)

Core (V)

Voltage

I/O (V)

1.8 V, 3.3 V

PLL Options

CLKIN1 frequency multiplier

x1 (Bypass), x15, x20, x25, x30, x32

529-Pin Flip Chip Plastic BGA (ZUT)

x1 (Bypass), x15, x20, x25, x30, x32

529-Pin Flip Chip Plastic BGA (ZUT)

BGA Package

6

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Table 2-1. Characteristics of the DM647/DM648 Processor (continued)

HARDWARE FEATURES

DM647

DM648

Process

Technology

0.09-µm/6-Level Cu Metal Process

(CMOS)

0.09 µm

Product Preview (PP), Advance

Product Status⁽¹⁾Information (AI),

PP

or Production Data (PD)

(1) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of

development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or

discontinue these products without notice.

2.2 CPU (DSP Core) Description

The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data

paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit

registers for a total of 64 registers. The general-purpose registers can be used for data or can be data

address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data,

40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored

in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in

the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one

instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units

perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from

memory to the register file and store results from the register file into memory.

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.

Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x

32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with

add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four

16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for

Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and

modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs

and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding

capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The

32 x 32 bit multiply instructions provide the extended precision necessary for audio and other

high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a

pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data

performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2

comparisons were available only on the .L units. On the C64x+ core they are also available on the .S unit

which increases the performance of algorithms that do searching and sorting. Finally, to increase data

packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit

and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack

instructions return parallel results to output precision including saturation support.

Other new features include:

•

SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where

multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size

associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

•

Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common

instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+

compiler can restrict the code to use certain registers in the register file. This compression is

performed by the code generation tools.

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•

Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit

multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field

multiplication.

Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to

detect and respond to exceptions, both from internally detected sources (such as illegal opcodes) and

from system events (such as a watchdog time expiration).

Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a

basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with

read, write, and execute permissions.

Time-Stamp Counter - Primarily targeted for real-time operating system (RTOS) robustness, a

free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following

documents:

•

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)

TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871)

TMS320C64x to TMS320C64x+ CPU Migration Guide Application Report (literature number SPRAA84)

TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)

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Even

Odd

src1

src2

register

file A

(A0, A2,

(A1, A3,

A4...A30)

A5...A31)

.L1

odd dst

even dst

long src

(D)

8

32 MSB

32 LSB

ST1b

ST1a

8

long src

even dst

odd dst

src1

(D)

Data path A

.S1

src2

32

(A)

(B)

dst2

dst1

src1

.M1

src2

(C)

32 MSB

32 LSB

LD1b

LD1a

dst

src1

src2

.D1

.D2

DA1

2x

1x

Even

register

Odd

src2

DA2

file B

(B0, B2,

B4...B30)

(B1, B3,

register

file B

src1

dst

B5...B31)

32 LSB

LD2a

LD2b

32 MSB

src2

(C)

.M2

src1

dst2

32

(B)

(A)

dst1

src2

src1

.S2

odd dst

even dst

long src

(D)

Data path B

8

32 MSB

32 LSB

ST2a

ST2b

long src

even dst

(D)

odd dst

.L2

src2

src1

Control Register

A. On .M unit, dst2 is 32 MSB.

B. On .M unit, dst1 is 32 LSB.

C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.

D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths

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2.3 C64x+ CPU

The C64x+ core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P)

consists of 32-KB memory space that can be configured as mapped memory or direct mapped cache. The

Level 1 data memory/cache (L1D) consists of 32 KB that can be configured as mapped memory or 2-way

associated cache. The Level 2 memory/cache (L2) consists of a 256 KB (DM647)/512 KB (DM648)

memory space that is shared between program and data space. L2 memory can be configured as mapped

memory, cache, or a combination of both.

Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.

Table 2-2. C64x+ Cache Registers

HEX ADDRESS RANGE

0x0184 0000

REGISTER ACRONYM

L2CFG

DESCRIPTION

L2 cache configuration register

0x0184 0020

L1PCFG

L1PCC

L1P size cache configuration register

L1P freeze mode cache configuration register

L1D size cache configuration register

L1D freeze mode cache configuration register

Reserved

0x0184 0024

0x0184 0040

L1DCFG

L1DCC

-

0x0184 0044

0x0184 0048 - 0x0184 0FFC

0x0184 1000

EDMAWEIGHT

-

L2 EDMA access control register

Reserved

0x0184 1004 - 0x0184 1FFC

0x0184 2000

L2ALLOC0

L2ALLOC1

L2ALLOC2

L2ALLOC3

-

L2 allocation register 0

0x0184 2004

L2 allocation register 1

0x0184 2008

L2 allocation register 2

0x0184 200C

L2 allocation register 3

0x0184 2010 - 0x0184 3FFF

0x0184 4000

Reserved

L2WBAR

L2WWC

L2WIBAR

L2WIWC

L2IBAR

L2IWC

L2 writeback base address register

L2 writeback word count register

L2 writeback invalidate base address register

L2 writeback invalidate word count register

L2 invalidate base address register

L2 invalidate word count register

L1P invalidate base address register

L1P invalidate word count register

L1D writeback invalidate base address register

L1D writeback invalidate word count register

Reserved

0x0184 4004

0x0184 4010

0x0184 4014

0x0184 4018

0x0184 401C

0x0184 4020

L1PIBAR

L1PIWC

L1DWIBAR

L1DWIWC

-

0x0184 4024

0x0184 4030

0x0184 4034

0x0184 4038

0x0184 4040

L1DWBAR

L1DWWC

L1DIBAR

L1DIWC

-

L1D block writeback

0x0184 4044

L1D block writeback

0x0184 4048

L1D invalidate base address register

L1D invalidate word count register

Reserved

0x0184 404C

0x0184 4050 - 0x0184 4FFF

0x0184 5000

L2WB

L2 writeback all register

0x0184 5004

L2WBINV

L2INV

L2 writeback invalidate all register

L2 global invalidate without writeback

Reserved

0x0184 5008

0x0184 500C - 0x0184 5027

0x0184 5028

-

L1PINV

-

L1P global invalidate

0x0184 502C - 0x0184 5039

0x0184 5040

Reserved

L1DWB

L1DWBINV

L1D global writeback

0x0184 5044

L1D global writeback with invalidate

10

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Digital Media Processor

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SPRS372–MAY 2007

Table 2-2. C64x+ Cache Registers (continued)

HEX ADDRESS RANGE

0x0184 5048

REGISTER ACRONYM

L1DINV

DESCRIPTION

L1D global invalidate without writeback

0x0184 8000 - 0x0184 80FC

0x0184 80C0 - 0x0184 80FC

0x0184 8100 - 0x0184 813C

0x0184 8140 - 0x0184 827C

0x0184 8280 - 0x0184 82BC

0x0184 8130 - 0x0184 813C

0x0184 82C0 - 0x0184 82FC

0x0184 8300- 0x0184 837C

0x0184 8380 - 0x0184 83BC

0x0184 83C0 - 0x0184 83FC

MAR0 - MAR63

Reserved 0x0000 0000 - 0x3FFF FFFF

MAR48 - MAR63

MAR64 - MAR79

MAR80 - MAR159

MAR160 - MAR175

MAR76 - MAR79

MAR176 - MAR191

MAR192 - MAR223

MAR224 - MAR239

MAR240 - MAR255

Reserved 0x3000 0000 - 0x3FFF FFFF

Memory attribute registers for PCI Data 0x4000 0000 - 0x4FFF FFFF

Reserved 0x5000 0000 - 0x9FFF FFFF

Memory attribute registers for EMIFA CE2 0xA000 0000- 0xA3FF FFFF

Memory Attribute Registers for VLYNQ 0x4C00 0000 - 0x4FFF FFFF

Memory attribute registers for EMIFA CE3 0xB000 0000- 0xB3FF FFFF

Reserved 0xC000 0000 - 0xDFFF FFFF

Memory attribute registers for DDR2 0xE000 0000 - 0xEFFF FFFF

Reserved 0xF000 0000 - 0xFFFF FFFF

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Digital Media Processor

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SPRS372–MAY 2007

2.4 Memory Map Summary

Table 2-3 shows the memory map address ranges of the device. The device has multiple on-chip

memories associated with its two processors and various subsystems. To help simplify software

development, a unified memory map is used where possible to maintain a consistent view of device

resources across all bus masters.

Table 2-3. Memory Map Summary

START

END

SIZE

C64x+

ADDRESS

(Bytes)

MEMORY MAP

0x0000 0000

0x0010 0000

0x0012 0000

0x0020 0000

0x0080 0000

0x008C 0000

0x00A0 0000

0x00A4 0000

0x00B6 0000

0x00E0 0000

0x00E0 8000

0x00F0 0000

0x00F0 8000

0x0100 0000

0x0180 0000

0x0181 0000

0x0181 1000

0x0181 2000

0x0181 3000

0x0182 0000

0x0182 0410

0x0183 0000

0x0184 0000

0x0185 0000

0x01BC 0000

0x01BD 0000

0x01BE 0000

0x0200 0000

0x0200 0080

0x0204 0000

0x0204 4000

0x0204 4400

0x0204 4800

0x020 44C00

0x0204 5000

0x0204 5400

0x0204 6000

0x0204 7000

0x0204 7400

0x0204 7800

0x0204 7C00

0x0204 8000

0x000F FFFF

1M

128K

1M-128K

6M

Reserved

VICP

0x0011 FFFF

0x001F FFFF

0x007F FFFF

0x008B FFFF

0x009F 7FFF

0x00A3 FFFF

0x00A7 FFFF

0x00DF FFFF

0x00E0 7FFF

0x00EF FFFF

0x00F0 7FFF

0x00FF FFFF

0x017F FFFF

0x0180 FFFF

0x0181 0FFF

0x0181 1FFF

0x0181 2FFF

0x0181 FFFF

0x0182 040F

0x 0182 FFFF

0x 0183 FFFF

0x 0184 FFFF

0x 01BB FFFF

0x 01BC FFFF

0x 01BD FFFF

0x 01BF FFFF

0x 01FF FFFF

0x0200 0007F

0x0203 FFFF

0x0204 3FFF

0x0204 43FF

0x0204 47FF

0x0204 4BFF

0x0204 4FFF

0x0204 53FF

0x0204 5FFF

0x0204 6FFF

0x0204 73FF

0x0204 77FF

0x0204 7BFF

0x0204 7FFF

0x0204 83FF

Reserved

Internal ROM

Reserved

768K

2M-768K

256K

4M-1408K

32K

L2 SRAM (For both DM647 and DM648)

L2 SRAM (For DM648 only)

Reserved

L1P SRAM

1M – 32K

32K

Reserved

L1D SRAM

1M – 32K

8M

Reserved

64K

C64x+ Interrupt Controller

C64x+ Power-down Control

C64x+ Security ID

C64x+ Revision ID

Reserved

4K

52K

1040B

64K – 16

64K

C64x+ EMC

Reserved

64K

C64x+ Memory control

Reserved

3, 520K

64K

Emulation

64K

Reserved

128K

4.125M

128B

256K – 128

16K

Reserved

HPI Control

Reserved

McASP Control

McASP Data

Timer0

1K

Timer1

1K

Timer2

1K

Timer3

3K

Reserved

4K

PSC

1K

UART

1K

VIC Control

SPI

1K

I2C Data and Control

GPIO

1K

12

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Digital Media Processor

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SPRS372–MAY 2007

Table 2-3. Memory Map Summary (continued)

START

ADDRESS

END

ADDRESS

SIZE

(Bytes)

C64x+

MEMORY MAP

0x0204 8400

0x0204 8800

0x0204 9000

0x0204 A000

0x0208 0000

0x020A 0000

0x020E 0000

0x020E 0200

0x0212 0000

0x0212 0200

0x0216 0000

0x02A0 0000

0x02A0 8000

0x02A2 0000

0x02A2 8000

0x02A3 0000

0x02A3 8000

0x02A4 0000

0x02A8 0000

0x02A8 0500

0x02AC 0000

0x02AE 0000

0x02B0 0000

0x02B0 0100

0x02B0 4000

0x02B0 4080

0x02B4 0000

0x02B4 0200

0x02B8 0000

0x02BA 0000

0x02BC 0000

0x02C0 0000

0x02C0 4000

0x02C0 8000

0x02C0 C000

0x02C1 0000

0x02C1 4000

0x02C4 0000

0x02C8 0000

0x02CC 0000

0x02D0 0000

0x02D0 2000

0x02D0 3000

0x02D0 4000

0x02D0 4800

0x02D0 4C00

0x02D0 5000

0x02D0 5800

0x02DC 0000

0x0204 87FF

1K

2K

PCI Control

Reserved

0x0204 8FFF

0x0204 9FFF

0x0207 FFFF

0x0209 FFFF

0x020D FFFF

0x020E 01FF

0x0211 FFFF

0x0212 01FF

0x0215 FFFF

0x029C FFFF

0x02A0 7FFF

0x02A1 FFFF

0x02A2 7FFF

0x02A2 FFFF

0x02A3 7FFF

0x02A3 FFFF

0x02A7 FFFF

0x02A8 04FF

0x02AB FFFF

0x02AD FFFF

0x02AF FFFF

0x02B0 00FF

0x02B0 3FFF

0x02B0 407F

0x02B3 FFFF

0x02B4 01FF

0x02B7 FFFF

0x02B9 FFFF

0x02BB FFFF

0x02BF FFFF

0x02C0 3FFF

0x02C0 7FFF

0x02C0 BFFF

0x02C0 FFFF

0x02C1 3FFF

0x02C3 FFFF

0x02C7 FFFF

0x02CB FFFF

0x02CF FFFF

0x02D0 1FFF

0x02D0 2FFF

0x02D0 3FFF

0x02D0 47FF

0x02D0 4BFF

0x02D0 4FFF

0x02D0 57FF

0x02DB FFFF

0x02DF FFFF

4K

Chip-Level Registers

Reserved

216K

128K

256K

512

VICP Configuration

Reserved

PLL Controller 1⁽¹⁾

Reserved

256K – 512

512

PLL Controller 2⁽¹⁾

Reserved

256K – 512

9M-576K

32K

Reserved

EDMA3CC

Reserved

96K

32K

EDMA3TC0

EDMA3TC1

EDMA3TC2

EDMA3TC3

Reserved

32K

256K

1.25K

256K – 1.25K

128K

256

Reserved

16K – 256

128

Reserved

256K – 128

512

Reserved

256K – 512

128K

256K

16K

Reserved

VP0 Control

VP1 Control

VP2 Control

VP3 Control

VP4 Control

Reserved

16K

176K

256K

8K

Reserved

Ethernet Subsystem CPPI RAM

Ethernet Subsystem Control

Ethernet Subsystem 3PSW

Ethernet Subsystem MDIO

Ethernet Subsystem SGMII0

Ethernet Subsystem SGMII1 (DM648 only)

Reserved

4K

2K

1K

2K

746K

256K

Reserved

(1) The EMIFA CS0 and CS1 are not functionally supported on the DM648 device, and therefore, are not pinned out.

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TMS320DM647/TMS320DM648

Digital Media Processor

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SPRS372–MAY 2007

Table 2-3. Memory Map Summary (continued)

START

END

SIZE

C64x+

ADDRESS

(Bytes)

MEMORY MAP

0x02E0 0000

0x02E0 4000

0x0300 0000

0x0400 0000

0x1000 0000

0x2000 0000

0x3000 0000

0x3000 0100

0x3400 0000

0x3400 0100

0x3800 0000

0x3C00 0000

0x3D00 0000

0x3E00 0000

0x4000 0000

0x5000 0000

0x5200 0000

0x5400 0000

0x5600 0000

0x5800 0000

0x5A00 0000

0x5C00 0000

0x5E00 0000

0x6000 0000

0x6200 0000

0x6400 0000

0x6600 0000

0x6800 0000

0x7000 0000

0x7800 0000

0x8000 0000

0x9000 0000

0xA000 0000

0xA400 0000

0xB000 0000

0xB400 0000

0xC000 0000

0xD000 0000

0xE000 0000

0xF000 0000

0x02E0 3FFF

16K

2M – 16K

16M

Reserved

0x02FF FFFF

0x03FF FFFF

0x0FFF FFFF

0x1FFF FFFF

0x2FFF FFFF

0x3000 00FF

0x33FF FFFF

0x3400 00FF

0x37FF FFFF

0x3BFF FFFF

0x3CFF FFFF

0x3DFF FFFF

0x3FFF FFFF

0x4FFF FFFF

0x51FF FFFF

0x53FF FFFF

0x55FF FFFF

0x57FF FFFF

0x59FF FFFF

0x5BFF FFFF

0x5DFF FFFF

0x5FFF FFFF

0x61FF FFFF

0x63FF FFFF

0x65FF FFFF

0x67FF FFFF

0x6FFF FFFF

0x77FF FFFF

0x7FFF FFFF

0x8FFF FFFF

0x9FFF FFFF

0xA3FF FFFF

0xAFFF FFFF

0xB3FF FFFF

0xBFFF FFFF

0xCFFF FFFF

0xDFFF FFFF

0xEFFF FFFF

0xFFFF FFFF

Reserved

192M

256M

256

Reserved

64M – 256

256

Reserved

64M – 256

64M

Reserved

VLYNQ

16M

Reserved

16M

Reserved

32M

Reserved

256M

32M

PCI Data

VP0 ChannelA Data

VP0 ChannelB Data

VP1 ChannelA Data

VP1 ChannelB Data

VP2 ChannelA Data

VP2 ChannelB Data

Reserved

32M

Reserved

32M

VP3 ChannelA Data

VP3 ChannelB Data

VP4 ChannelA Data

VP4 ChannelB Data

Reserved

32M

128M

256M

64M

EMIFA Config

DDR2 EMIF Config

Reserved

EMIFA CE2

Reserved

256-64M

64M

EMIFA CE3

Reserved

256-64M

256M

Reserved

DDR2 SDRAM

Reserved

14

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Digital Media Processor

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2.5 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in

the smallest possible package. Pin multiplexing is controlled using a combination of hardware

configuration at device reset and software programmable register settings. For more information on pin

muxing, see Section 3.2.6, PINMUX Register.

2.5.1 Pin Map (Bottom View)

Figure 2-2 through Figure 2-5 show the bottom view of the ZUT package pin assignments in four

quadrants (A, B, C, and D).

1

2

3

4

5

6

7

8

9

10

11

12

AC

AB

AA

Y

V_SS

D_VDD33

V_SS

SGMII1RXN

AHCLKX

AHCLKR

ACLKR

ACLKX

REFCLKN

V_SS

D_VDD33

A_VDDT

A_VDDR

D_VDD33

VP2CLK0 VP2CTL1 AMUTEIN

AXR3

AXR0

SGMII1RXP

REFCLKP

VDAC/

AXR9

PREQ/

GP03

V_SS

VP2CTL0

VP2D03

VP2D06

AXR6

AXR2

AXR1

AFSR

AFSX

SGMII0RXP SGMII0RXN

VP2CTL2/

VSCRUN

STCLK/

AXR8

D_VDD33

V_SS

VP2D04

VP2D07

AXR4

SGMII0TXP

SGMII0TXN

A_VDDA

RSV21

RSV22

VP2CLK1/ VP2D12/

VCLK

VRXD0

V_SS

A_VDDA

RSV17

D_VDDD

A_VDDA

W

V

VP2D09

VP2D02

VP2D08

SGMII1TXP SGMII1TXN

VP2D13

/VRXD1

VP2D14/

VRXD2

PINTA/

GP02

V_SS

D_VDD33

C_VDD

V_SS

AXR7

AXR5

AMUTE

V_SS

VP2D15/

VRXD3

VP2D17/

VTXD1

VP2D16/

VTXD0

VP2D19/

VTXD3

VP2D18/

VTXD2

PRST/

GP01

U

A_VDDT

VP2D05

MDIO

MDCLK

VP3CLK0/ VP3CTL0/ VP3D05/

VP3D04/

AED02

VP3D03/

AED01

VP3D02/

AED00

D_VDD33

V_SS

D_VDD33

T

AECLKIN

ASDWE

AED03

VP3CTL1/ VP3D12/

VP3D09/

AED07

VP3D08/

AED06

VP3D07/

AED05

VP3D06/

AED04

C_VDDESS

D_VDD33

R

C_VDD

D_VDD33

V_SS

C_VDDESS

V_SS

ARNW

AED08

VP3CLK1/

AECLK

OUT

VP3CTL2/ VP3D16/

VP3D15/

AED11

VP3D14/

AED10

VP3D13/

AED09

C_VDD

P

V_SS

D_VDD33

V_SS

C_VDD

V_SS

AOE

D_VDD33

RSV9

AED12

VP3D17/

AED13

VP3D19/

AED15

VP3D18/

AED14

C_VDD

N

V_SS

PLLV1

V_SS

VP4D03/

ABE01

VP4D04/

AEA10

M

CLKIN1

SYSCLK4

VP4D05

C_VDD

V_SS

C_VDD

D_VDD33

Figure 2-2. ZUT Pin Map [Top Left Quadrant]

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TMS320DM647/TMS320DM648

Digital Media Processor

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SPRS372–MAY 2007

13

14

15

16

17

18

19

20

21

22

23

AD26/

HD26

AD22/

HD22

PCLK/

AD14/

HD14

AD02/

HD02

AD04/

HD04

PCBE1/

HDS2

PCBE0/

GP04

V_SS

D_VDD33

AC

AB

AA

HHWIL

AD27/

HD27

AD23/

HD23

AD17/

HD17

AD12/

HD12

AD08/

HD08

AD05/

HD05

AD01/

HD01

PIRDY/

HRDY

D_VDD33

V_SS

AD28/

HD28

PIDSEL/

GP06

AD18/

HD18

PFRAME

/HINT

PTRDY/

GP05

AD15/

HD15

AD13/

HD13

AD09/

HD09

AD06/

HD06

AD00/

HD00

AD03/

HD03

PDEVSEL PSTOP

/HCNTL1 /HCNTL0

AD29/

HD29

AD19/

HD19

AD16/

HD16

AD11/

HD11

AD10/

HD10

AD07/

HD07

PCBE3/

GP07

VP0CTL0 VP0CLK0

Y

W

V

U

T

AD30/

HD30

AD24/

HD24

AD20/

HD20

PPAR/

HAS

PCBE2/

HRW

PPERR/

HCS

PSERR/

HDS1

V_SS

D_VDD33

VP0D02

VP0D09

VP0D16

VP0D06

AD31/

HD31

AD25/

HD25

AD21/

HD21

VP0D012/

GP12

D_VDD33

V_SS

D_VDD33

V_SS

VP0D03

VP0D04

VP0D07

VP0D19

VP0D05

VP0D08

VP0CTL1 VP0CLK1

VP0D17 VP0CTL2

PGNT/

GP00

V_SS

D_VDD33

V_SS

D_VDD33

V_SS

VP0D18

VP0D13/

GP13

VP0D14/ VP0D15/

C_VDD

V_SS

C_VDD

V_SS

D_VDD33

GP14

GP15

VP1D02/

GP16

VP1D07/

GP21

VP1D06/

GP20

VP1D05/

GP19

C_VDD

V_SS

D_VDD33

V_SS

D_VDD33

VP1CTL0

R

P

N

M

VP1D04/

GP18

VP1D03/

GP17

VP1D14/

GP26

VP1D13/

GP25

C_VDD

V_SS

C_VDD

V_SS

VP1CTL1 VP1CLK0

VP1CTL2 VP1CLK1

VP1D17/

GP29

VP1D12/

GP24

VP1D09/

GP23

VP1D08/

GP22

C_VDD

V_SS

D_VDD33

VP1D16/

GP28

VP1D19/

GP31

VP1D15/

GP27

VP1D18/

GP30

V_SS

C_VDD

D_VDD33

V_SS

D_VDD33

Figure 2-3. ZUT Pin Map [Top Right Quadrant]

16

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VP4CLK0/ VP4D02/

ABE00

VP4D06/

ACE2

VP4D07/

ACE3

VP4D08/

AEA00

VP4D13/

AEA03

D_VDD33

V_SS

D_VDD33

V_SS

C_VDD

V_SS

C_VDD

V_SS

L

K

J

AARDY

VP4CTL2/ VP4D09/

AEA01

VP4D12/ VP4D14/

AEA02

VP4D19/

AEA09

V_SS

C_VDD

V_SS

C_VDD

VP4CLK1

AADS

AEA04

VP4D17/ VP4D18/

AEA08

VP4D15/

AEA05

VP4D16/

AEA06

VP4CTL1/ VP4CTL0/

ABA0

D_VDD33

V_SS

C_VDD

V_SS

C_VDD

C_VDD1

D_VDD18

AEA07

ABA1

HPIWIDTH/

AEA16

RSV_BOOT/

AEA15

V_SS

D_VDD18

V_SS

D_VDD18

H

G

F

UHPIEN

AEA23

AEA19

RSV7

PLLV2

V_SS

RSV8

V_SS

EMIB

WIDTH/

AEA22

BOOT

MODE3/

AEA14

AECLKIN

SEL/

AEA17

FASTBOOT

/AEA21

PCI66/

AEA18

D_VDD33

V_SS

D_VDD18

BEA06

BBA2

V_SS

DEVICE

ENABLE0/

AEA20

BOOT

MODE0/

AEA11

BOOT

MODE1/

AEA12

BOOT

MODE2/

AEA13

D_VDD18

CLKIN2

RSV12

RSV18

BEA13

BSDRAS

BEA08

BEA12

BCE

D_VDD18

V_SS

BED07

BED04

BED00

E

D

C

B

A

RSV11

RSV14

RSV13

BSDDQ

GATE0

V_SS

RSV4

RSV3

RSV6

D_VDD18

RSV5

V_SS

BSDDQM1

BED15

BED10

BED08

BED05

BED03

BSDCAS

D_VDD18

BSDWE

V_REFSSTL

RSV20

RSV19

BED06

BED09

BED01

BBA0

BSDDQ

GATE1

A_VDLL1

D_VDD18

V_DD18MON

D_VDD18

BED12

BED14

BSDDQM0

BED02

BSDCKE

BBA1

V_SS

BSDDQS1N BSDDQS1P BSDDQS0N BSDDQS0P

BED13

4

RSV15

10

BECLKOUTP BECLKOUTN

RSV10

2

BED11

3

1

5

6

7

8

9

11

12

Figure 2-4. ZUT Pin Map [Bottom Left Quadrant]

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Digital Media Processor

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SPRS372–MAY 2007

L

K

J

V_CCMON

C_VDD

V_SS

C_VDD

V_SS

C_VDD

V_SS

D_VDD33

EMU4

EMU11

NMI

RSV1

EMU3

EMU8

EMU9

RSV2

EMU2

EMU5

TMS

EMU1

TDI

TRST

EMU0

TDO

V_SS

D_VDD33

V_SS

EMU6

C_VDD1

C_VDD

V_SS

D_VDD33

EMU10

RESETSTAT

D_VDD33

H

V_SS

D_VDD18

V_SS

D_VDD18

V_SS

D_VDD33

V_SS

D_VDD18

V_SS

D_VDD33

EMU7

TCLK

POR

SPIDI/

V_DD33MON

D_VDD18

V_SS

UARTRTS

G

F

RESET

SPIDO/

UART/

CTS

SPICS2/

UARTRX

D_VDD18

V_SS

D_VDD33

BEA02

SPICLK

BSDDQ

GATE2

T0INP12/ T1INP12/

D_VDD33

V_SS

E

D

C

B

A

BEODT0

BEA09

D_VDD18

BEA03

BEA04

BEA05

BSDDQM2

BEA00

BED19

BED18

BED17

BED23

BED22

BED21

BED31

BED29

BED27

GP08

GP10

SPICS1/

UARTTX

T0OUT12/

GP09

V_SS

BED25

BED24

D_VDD18

SCL0

T1OUT12/

GP11

D_VDD18

BEA01

BED30

BED28

SDA0

D_VDD18

A_VDLL2

D_VDD18

BEA11

BEA07

BED16

BED20

BED26

BSDDQM3

BSDDQ

GATE3

V_SS

BSDDQS2N BSDDQS2P

V_SS

BSDDQS3N BSDDQS3P

V_SS

23

BEA10

13

BEODT1

14

RSV16

22

15

16

17

18

19

20

21

Figure 2-5. ZUT Pin Map [Bottom Right Quadrant]

18

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2.6 Terminal Functions

The terminal functions tables (Table 2-4 through Table 2-5) identify the external signal names, the

associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin

has any internal pullup or pulldown resistors, and a functional pin description. For more detailed

information on device configuration, peripheral selection, multiplexed/shared pin, and debugging

considerations, see Section 3.

All device boot and configuration pins are multiplexed with functional pins. These pins function as device

boot and configuration pins only during device reset. When both the reset pin (RESET) and the power-on

reset pin (POR) are deasserted, the input states of these multiplexed device boot and configuration pins

are sampled and latched into the BOOTCFG register. For proper device operation, these pins must be

pulled up/down to the desired value via an external resistor.

Table 2-4. TERMINAL FUNCTIONS

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

Clock/PLL Configuration

CLKIN1

CLKIN2

REFCLKN

REFCLKP

PLLV1

M1

F1

I

IPD

3.3 V

Clock Input for PLL1

I

Clock Input for PLL2

AC11

AB11

N3

I

Differential Reference Clock input (negative) for SGMII

Differential Reference Clock input (positive) for SGMII

1.8-V I/O Supply Voltage for PLL1

1.8-V I/O Supply Voltage for PLL2

Clock out of device speed/4

I

A

1.8 V

3.3 V

PLLV2

G7

A

SYSCLK4

M3

I/O/Z

IPD

JTAG

TCLK

TDI

H23

J22

J23

L22

L23

K23

K22

K21

K20

L18

J21

K19

H21

J20

H20

J19

K18

I

IPU

IPD

IPU

3.3 V

JTAG Test Port Clock

I

JTAG Test Port Data In

TDO

OZ

JTAG Test Port Data Out

JTAG Test Port Mode Select

JTAG Test Port Reset

TMS

I

TRST

EMU0

EMU1

EMU2

EMU3

EMU4

EMU5

EMU6

EMU7

EMU8

EMU9

EMU10

EMU11

I

I/O/Z

JTAG Test Port Emulation 0

JTAG Test Port Emulation 1

JTAG Test Port Emulation 2

JTAG Test Port Emulation 3

JTAG Test Port Emulation 4

JTAG Test Port Emulation 5

JTAG Test Port Emulation 6

JTAG Test Port Emulation 7

JTAG Test Port Emulation 8

JTAG Test Port Emulation 9

JTAG Test Port Emulation 10

JTAG Test Port Emulation 11

RESET/INTERRUPTS

NMI

J18

H19

G20

H18

I

O

I

IPD

3.3 V

Non maskable Interrupt

RESETSTAT

RESET

POR

Reset Status Pin

Device Reset

I

Power On Reset

HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) or GPIO[0:7]

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

AD00/HD00

AD01/HD01

AD02/HD02

AD03/HD03

AD04/HD04

AD05/HD05

AD06/HD06

AD07/HD07

AD08/HD08

AD09/HD09

AD10/HD10

AD11/HD11

AD12/HD12

AD13/HD13

AD14/HD14

AD15/HD15

AD16/HD16

AD17/HD17

AD18/HD18

AD19/HD19

AD20/HD20

AD21/HD21

AD22/HD22

AD23/HD23

AD24/HD24

AD25/HD25

AD26/HD26

AD27/HD27

AD28/HD28

AD29/HD29

AD30/HD30

AD31/HD31

PPAR/HAS

PSTOP/HCNTL0

AA22 I/O/Z

AB22 I/O/Z

AC21 I/O/Z

AA23 I/O/Z

AC22 I/O/Z

AB21 I/O/Z

AA21 I/O/Z

IPD

IPU

IPD

3.3 V

Host Port data [15:00] pin or PCI data-address bus [15:00]

[default]

Y21

I/O/Z

AB20 I/O/Z

AA20 I/O/Z

Y20

Y19

I/O/Z

AB18 I/O/Z

AA19 I/O/Z

AC18 I/O/Z

AA18 I/O/Z

Y16

I/O/Z

Host Port data [31:16] pin or PCI data-address bus [31:16]

[default]

AB15 I/O/Z

AA15 I/O/Z

Y15

W15

V15

I/O/Z

AC14 I/O/Z

AB14 I/O/Z

W14

V14

I/O/Z

AC13 I/O/Z

AB13 I/O/Z

AA13 I/O/Z

Y13

W13

V13

W19

Y18

I/O/Z

Host address strobe (I) or PCI parity [default]

Host Control selects between control, address, or data registers (I)

or PCI Stop [default]

PDEVSEL/HCNTL1

Y17

I/O/Z

IPD

3.3 V

Host Control selects between control, address, or data registers (I)

or PCI Device Select [default]

PPERR/HCS

PSERR/ HDS1

PCBE0/GP04

PCBE1/HDS2

PCBE2/HRW

PCBE3/GP07

PCLK/HHWIL

W17

W18

I/O/Z

IPU

3.3 V

Host chip select (I) or PCI parity error [default]

Host data strobe 1 (I) or PCI system error [default]

PCI command/byte enable 0 or GP[2] [default

PCI command/byte enable 1 or host data strobe 2

PCI command/byte enable 2 or host read or write select (I)

PCI command/byte enable 3 or GPIO[7]

AC20 I/O/Z

AC17

W16

Y14

I

I/O/Z

AC15 I/O/Z

PCI clock (I) [default] or host half-word select - first or second

half-word (not necessarily high or low order) [For HPI16 bus width

selection only] (I)

PFRAME/HINT

AA16 I/O/Z

IPD

3.3 V

PCI frame or host interrupt from DSP to host (O/Z)

20

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

PIRDY/HRDY

PGNT/GP00

PRST/GP01

PINTA/GP02

PREQ/GP03

PTRDY/GP05

PIDSEL/GP06

AB17 I/O/Z

IPD

3.3 V

PCI initiator ready [default] or host ready from DSP to host (O/Z)

PCI bus grant (I) or GPIO[0]

U13

U12

V12

I/O/Z

PCI Reset (I) or GPIO[1]

PCI Interrupt A (O/Z) or GPIO[2]

AA12 I/O/Z

AA17 I/O/Z

AA14 I/O/Z

PCI bus request (O/Z) or GPIO[3]

PCI target ready or GPIO[5]

PCI Initialization device select (I) or GPIO[6]

DDR2 MEMORY CONTROLLER

DDR2 Memory Controller Bank Address Control

BBA0

C12

B12

E11

F9

I/O/Z

1.8 V

BBA1

BBA2

BCE

DDR2 Memory Controller Memory Space Enable

DDR2 Memory Controller External Address

BEA00

BEA01

BEA02

BEA03

BEA04

BEA05

BEA06

BEA07

BEA08

BEA09

BEA10

BEA11

BEA12

BEA13

BECLKOUTN

BECLKOUTP

D15

C15

F13

E14

D14

C14

F11

B14

F12

D13

A13

B13

E12

F10

A12

A11

DDR2 Memory Controller Output Clock (CLKIN2 frequency x 10)

Negative DDR2 Memory Controller Output Clock (CLKIN2

frequency x 10)

BED00

BED01

BED02

BED03

BED04

BED05

BED06

BED07

BED08

BED09

E9

C9

B9

C8

E8

D8

C7

E7

C6

B7

I/O/Z

1.8 V

DDR2 Memory Controller External Data

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

BED10

BED11

BED12

BED13

BED14

BED15

BED16

BED17

BED18

BED19

BED20

BED21

BED22

BED23

BED24

BED25

BED26

BED27

BED28

BED29

BED30

BED31

BEODT0

BEODT1

D6

A3

I/O/Z

1.8 V

DDR2 Memory Controller External Data (continued)

B3

A4

B4

C5

B16

C16

D16

E16

B17

C17

D17

E17

C18

D18

B19

C19

B20

D19

C20

E19

E13

A14

On-die termination signals to external DDR2 SDRAM. These pins

are reserved for future use and should not be connected to the

DDR2 SDRAM.

Note: There are no on-die termination resistors implemented on

the DM647/DM648DSP die.

BSDCAS

D10

B11

D7

I/O/Z

1.8 V

DDR2 Memory Controller SDRAM column address strobe

DDR2 Memory Controller SDRAM clock-enable

DDR2 Memory Controller data strobe Gate

BSDCKE

BSDDQGATE0

BSDDQGATE1

BSDDQGATE2

BSDDQGATE3

BSDDQM0

BSDDQM1

BSDDQM2

BSDDQM3

BSDDQS0P

BSDDQS1P

BSDDQS2P

BSDDQS3P

BSDDQS0N

BSDDQS1N

BSDDQS2N

BSDDQS3N

BSDRAS

B6

E18

A21

B8

DDR2 Memory Controller byte-enable controls. Decoded from the

low-order address bits. The number of address bits or byte

enables used depends on the width of external memory. Byte-write

enables for most types of memory. Can be directly connected to

SDRAM read and write mask signal (SDQM).

D5

E15

B21

A9

DDR2 Memory Controller data strobe [3:0]

A7

A17

A20

A8

DDR2 Memory Controller data strobe [3:0] negative

A6

A16

A19

E10

D11

DDR2 Memory Controller SDRAM row address strobe

DDR2 Memory Controller SDRAM write enable

BSDWE

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

CONFIGURATION AND EMIFA

DEVICEENABLE0/AE

A20

F2

I/O/Z

IPD

3.3 V

EMIFA External Address 20 (word address) (O/Z) For proper

device operation, this pin must be externally pulled up with a 1-kΩ

resistor at device reset

EMIFAWIDTH/AEA22

G3

3.3 V

EMIFA External Address 22 (word address) (O/Z) EMIFA data bus

width selection pin state captured at the rising edge of RESET.

0 sets EMIFA CS2 to 8 bit data bus width

1 sets EMIFA CS2 to 16 bit data bus width. For details. see

Section 3.

FASTBOOT/AEA21

UHPIEN

G2

H2

H3

I/O/Z

I

IPD

3.3 V

EMIFA External Address 22 (word address) (O/Z) Enables FAST

BOOT of the device. For details see Section 3.

UHPI enable pin. This pin controls the selection (enable/disable) of

the HPI and GPIO[0:7] muxed with PCI. For details see Section 3.

HPIWIDTH/AEA16

I/O/Z

EMIFA External Address 16 (word address) (O/Z) HPI peripheral

bus width (HPI_WIDTH) select [Applies only when HPI is enabled;

UHPIEN pin = 1]

RSVBOOT/AEA15

PCI66/AEA18

H6

G5

I/O/Z

IPU

IPD

3.3 V

EMIFA External Address 15 (word address) (O/Z) For proper

device operation, this pin must be externally pulled up with a 1-kΩ

resistor at device reset

PCI Frequency Selection (PCI66). The PCI peripheral must be

enabled (UHPIEN = 0) to use this function.PCI66_AEA18 selects

the PCI operating frequency of 66 MHz or 33 MHz. PCI operating

frequency is selected at reset via the pullup/pulldown resistor on

the PCI66 pin:AEA18:

0 - PCI operates at 33 MHz (default)

1 - PCI operates at 66 MHz.

BOOTMODE0/AEA11

BOOTMODE1/AEA12

BOOTMODE2/AEA13

BOOTMODE3/AEA14

F3

F4

F5

G6

I/O/Z

IPD

3.3 V

0000 Master mode - Emulation Boot

0001 Slave mode - HPI Boot (if UHPIEN = 1)

or PCI Boot (if UHPIEN = 0) without auto-initialization

0010 Slave mode - HPI Boot (if UHPIEN = 1)

or PCI Boot (if UHPIEN = 0) with auto-initialization

0011 Master mode - UART boot without flow control

0100 Master mode - EMIFA CS2 direct/fast boot

0101 Master mode - I2C boot

0110 Master mode - SPI boot

0111 Reserved

1000 Master mode - 3-port Ethernet Subsystem boot through

SGMII0 for DM647 only

Reserved in DM648

1001 Master mode - 3-port Ethernet Subsystem boot through

SGMII0 for DM648 only

Reserved in DM647

1010 Master mode - 3-port Ethernet Subsystem boot through

SGMII1 for DM648 only

Reserved in DM647

1011 Reserved

1100 Reserved

1101 Reserved

1110 Master mode - UART boot with flow control

1111 Reserved

INTER-INTEGRATED CIRCUIT (I2C)

SCL0

SDA0

D22

C23

I/O/Z

3.3 V

I2C clock. When the I2C module is used, use an external pullup

resistor.

3.3 V

I2C data. When I2C is used, make certain there is an external

pullup resistor.

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

SGMII0/1 and MDIO

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

SGMII1RXN

SGMII1RXP

SGMII1TXN

SGMII1TXP

MDCLK

AA10

AA9

W11

Y11

AC9

AB9

W9

I

1.2 V

3.3 V

Differential SGMII port 0 RX input (negative)

I

O

Differential SGMII port 0 RX input (positive)

Differential SGMII port 0 TX output (negative)

Differential SGMII port 0 TX output (positive)

Differential SGMII port 1 RX input (negative)

Differential SGMII port 1 RX input (positive)

Differential SGMII port 1 TX output (negative)

Differential SGMII port 1 TX output (positive)

MDIO serial clock (MDCLK)

O

I

O

W8

O

U9

OZ

I/O/Z

IPD

IPU

MDIO

U8

MDIO serial data (MDIO)

SPI or UART

SPICLK

F22

D23

F23

G23

F21

I/O/Z

IPU

3.3 V

SPI clock output

SPICS1/UARTTX

SPICS2/UARTRX

SPIDI/UARTRTS

SPIDO/UARTCTS

SPI chip select 1 or UART transmit (O/Z)

SPI chip select 2 or UART receive

SPI data input or UART ready to send (O/Z)

SPI data output or UART clear to send

TIMER 0/1 or GPIO[8:11]

T0INP12/GP08

T0OUT12/GP09

T1INP12/GP10

T1OUT12/GP11

E20

D21

E21

C22

I/O/Z

IPD

3.3 V

Timer 0 input pin for lower 32-bit counter (I) or GPIO 8

Timer 0 output pin for lower 32-bit counter (O/Z) or GPIO 9

Timer 1 input pin for lower 32-bit counter (I) or GPIO 10

Timer 1 output pin for lower 32-bit counter(O/Z) or GPIO 11

MCASP OR VIDEO PORT OR VIC

McASP receive high-frequency master clock

AHCLKR

AHCLKX

ACLKR

ACLKX

AFSR

AC4

AC3

AC6

AC7

W6

I/O/Z

IPD

3.3 V

McASP transmit high-frequency master clock

McASP receive master clock

McASP transmit master clock

McASP receive frame sync or left/right clock (LRCLK)

McASP transmit frame sync or left/right clock (LRCLK)

McASP data pin [0:7]

AFSX

AA7

AB6

Y6

AXR0

AXR1

AXR2

AA6

AB4

Y5

AXR3

AXR4

AXR5

V7

AXR6

AA4

V6

AXR7

STCLK/AXR8

Y7

I/O/Z

The STCLK signal drives the hardware counter for use by the

video ports (I) or McASP data pin 8.

VDAC/AXR9

AA5

IPD

3.3 V

VCXO Interpolated Control Port (VIC) single-bit digital-to-analog

converter(VDAC) output (O) or McASP data pin 9

AMUTEIN

AMUTE

AB3

U7

I/O/Z

IPD

3.3 V

McASP mute input

McASP mute output (O/Z).

VIDEO PORT 0 OR GPIO[12:15]

VP0CLK0

VP0CLK1

Y23

V23

I

IPU

3.3 V

Video Port 0 Clock 0 (I)

Video Port 0 Clock 1

I/O/Z

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

VP0CTL0

VP0CTL1

VP0CTL2

VP0D02

Y22

V22

U23

W20

V18

U18

V19

W21

T18

U19

V20

V21

T19

T20

T21

U20

U22

U21

R18

I/O/Z

IPU

IPD

3.3 V

Video Port 0 Control 0

Video Port 0 Control 1

Video Port 0 Control 2

Video Port 0 Data 2

Video Port 0 Data 3

Video Port 0 Data 4

Video Port 0 Data 5

Video Port 0 Data 6

Video Port 0 Data 7

Video Port 0 Data 8

Video Port 0 Data 9

VP0D03

VP0D04

VP0D05

VP0D06

VP0D07

VP0D08

VP0D09

VP0D12/GP12

VP0D13/GP13

VP0D14/GP14

VP0D15/GP15

VP0D16

Video Port 0 Data 12 or GPIO 12

Video Port 0 Data 13 or GPIO 13

Video Port 0 Data 14 or GPIO 14

Video Port 0 Data 15 or GPIO 15

Video Port 0 Data 16

VP0D17

Video Port 0 Data 17

VP0D18

Video Port 0 Data 18

VP0D19

Video Port 0 Data 19

VIDEO PORT 1 OR GPIO[16:31]

Video Port 1 Clock 0

VP1CLK0

P23

N23

R23

P22

N22

R19

P19

P18

R22

R21

R20

N21

N20

N19

P21

P20

M20

M18

N18

M21

M19

I

IPU

IPD

3.3 V

VP1CLK1

I/O/Z

Video Port 1 Clock 1

VP1CTL0

Video Port 1 Control 0

VP1CTL1

Video Port 1 Control 1

VP1CTL2

Video Port 1 Control 2

VP1D02/GP16

VP1D03/GP17

VP1D04/GP18

VP1D05/GP19

VP1D06/GP20

VP1D07/GP21

VP1D08/GP22

VP1D09/GP23

VP1D12/GP24

VP1D13/GP25

VP1D14/GP26

VP1D15/GP27

VP1D16/GP28

VP1D17/GP29

VP1D18/GP30

VP1D19/GP31

Video Port 1 Data 2 or GPIO 16

Video Port 1 Data 3 or GPIO 17

Video Port 1 Data 4 or GPIO 18

Video Port 1 Data 5 or GPIO 19

Video Port 1 Data 6 or GPIO 20

Video Port 1 Data 7 or GPIO 21

Video Port 1 Data 8 or GPIO 22

Video Port 1 Data 9 or GPIO 23

Video Port 1 Data 12 or GPIO 24

Video Port 1 Data 13 or GPIO 25

Video Port 1 Data 14 or GPIO 26

Video Port 1 Data 15 or GPIO 27

Video Port 1 Data 16 or GPIO 28

Video Port 1 Data 17 or GPIO 29

Video Port 1 Data 18 or GPIO 30

Video Port 1 Data 19 or GPIO 31

VIDEO PORT 2 OR VLYNQ

VP2CLK0

AB1

W1

I

IPU

3.3 V

Video Port 2 Clock 0 (I)

VP2CLK1/VCLK

VP2CTL0

I/O/Z

Video Port 2 Clock 1 or VLYNQ Clock (I/O)

Video Port 2 Control 0

AA1

AB2

VP2CTL1

Video Port 2 Control 1

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

VP2CTL2/VSCRUN

VP2D02

Y1

W5

AA2

Y3

I/O/Z

IPU

IPD

3.3 V

Video Port 2 Control 2 or VLYNQ serial clock run request (I/O)

Video Port 2 Data 2

VP2D03

Video Port 2 Data 3

VP2D04

Video Port 2 Data 4

VP2D05

U6

Y2

Video Port 2 Data 5

VP2D06

Video Port 2 Data 6

VP2D07

W3

V5

Video Port 2 Data 7

VP2D08

Video Port 2 Data 8

VP2D09

W4

W2

V3

Video Port 2 Data 9

VP2D12/VRXD0

VP2D13/VRXD1

VP2D14/VRXD2

VP2D15/VRXD3

VP2D16/VTXD0

VP2D17/VTXD1

VP2D18/VTXD2

VP2D19/VTXD3

Video Port 2 Data 12 or VLYNQ receive data pin [0] (I)

Video Port 2 Data 13 or VLYNQ receive data pin [1] (I)

Video Port 2 Data 14 or VLYNQ receive data pin [2] (I)

Video Port 2 Data 15 or VLYNQ receive data pin [3] (I)

Video Port 2 Data 16 or VLYNQ transmit data pin [0] (O)

Video Port 2 Data 17 or VLYNQ transmit data pin [1] (O)

Video Port 2 Data 18 or VLYNQ transmit data pin [2] (O)

Video Port 2 Data 19 or VLYNQ transmit data pin [3] (O)

V4

U1

U3

U2

U5

U4

VIDEO PORT 3 OR EMIFA

VP3CLK0/AECLKIN

T1

P1

I

IPD

3.3 V

Video Port 3 Clock 0 (I) or EMIFA external input clock (I)

VP3CLK1/AECLKOU

T

I/O/Z

Video Port 3 Clock 1 or EMIFA output clock (O/Z)

VP3CTL0/ASDWE

T2

I/O/Z

IPU

3.3 V

Video Port 3 Control 0 or Asynchronous memory write

enable/Programmable synchronous interface write-enable

VP3CTL1/ARNW

VP3CTL2/AOE

R1

P2

I/O/Z

IPU

3.3 V

Video Port 3 Control 1 or Asynchronous memory read/write (O/Z)

Video Port 3 Control 2 or Asynchronous/Programmable

synchronous memory output-enable (O/Z)

VP3D02/AED00

VP3D03/AED01

VP3D04/AED02

VP3D05/AED03

VP3D06/AED04

VP3D07/AED05

VP3D08/AED06

VP3D09/AED07

VP3D12/AED08

VP3D13/AED09

VP3D14/AED10

VP3D15/AED11

VP3D16/AED12

VP3D17/AED13

VP3D18/AED14

VP3D19/AED15

T6

T5

T4

T3

R6

R5

R4

R3

R2

P6

P5

P4

P3

N4

N6

N5

I/O/Z

IPU

3.3 V

Video Port 3 Data 2 or EMIFA External Data 0

Video Port 3 Data 3 or EMIFA External Data 1

Video Port 3 Data 4 or EMIFA External Data 2

Video Port 3 Data 5 or EMIFA External Data 3

Video Port 3 Data 6 or EMIFA External Data 4

Video Port 3 Data 7 or EMIFA External Data 5

Video Port 3 Data 8 or EMIFA External Data 6

Video Port 3 Data 9 or EMIFA External Data 7

Video Port 3 Data 12 or EMIFA External Data 8

Video Port 3 Data 13 or EMIFA External Data 9

Video Port 3 Data 14 or EMIFA External Data 10

Video Port 3 Data 15 or EMIFA External Data 11

Video Port 3 Data 16 or EMIFA External Data 12

Video Port 3 Data 17 or EMIFA External Data 13

Video Port 3 Data 18 or EMIFA External Data 14

Video Port 3 Data 19 or EMIFA External Data 15

VIDEO PORT 4 OR EMIFA

VP4CLK0/AARDY

VP4CLK1

L1

K1

I

IPU

IPD

3.3 V

Video Port 4 Clock 0 (I) or Asynchronous memory ready input (I)

Video Port 4 Clock 1

I/O/Z

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

VP4CTL0/ABA0

J2

I/O/Z

IPD

3.3 V

Video Port 4 Control 0 or EMIFA bank address control (ABA[1:0])

(O/Z). Active-low bank selects for the 16-bit EMIFA. When

interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of

the byte address. For an 8-bit asynchronous interface, ABA[1:0]

are used to carry bits 1 and 0 of the byte address.

VP4CTL1/ABA1

VP4CTL2/AADS

J1

I/O/Z

Video Port 4 Control 1 or EMIFA bank address control (ABA[1:0])

(O/Z). Active-low bank selects for the 16-bit EMIFA. WHEN

interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of

the byte address. For an 8-bit asynchronous interface, ABA[1:0]

are used to carry bits 1 and 0 of the byte address.

K2

Video Port 4 Control 2 or Programmable synchronous address

strobe or read-enable. For programmable synchronous interface,

the r_enable field in the ChipSelect x Configuration Register

selects between ASADS and ASRE:

– If r_enable = 0, then the ASADS/ASRE signal functions as the

ASADS signal.

– If r_enable = 1, then the ASADS/ASRE signal functions as the

ASRE signal.

VP4D02/ABE00

L2

I/O/Z

IPU

3.3 V

Video Port 4 Data 2 or EMIFA byte-enable control 0. Decoded

from the low-order address bits. The number of address bits or

byte enables used depends on the width of external memory.

Byte-write enables for most types of memory.

VP4D03/ABE01

VP4D04/AEA10

M4

M5

I/O/Z

IPU

3.3 V

Video Port 4 Data 3 or EMIFA byte-enable control 1. Number of

address bits or byte enables used depends on the width of

external memory. Byte-write enables for most types of memory.

Video Port 4 Data 4 or EMIFA External Address 10 (word address)

(O/Z)

VP4D05

M6

L3

L4

L5

I/O/Z

IPU

IPD

3.3 V

Video Port 4 Data 5

VP4D06/ACE2

VP4D07/ACE3

VP4D08/AEA00

Video Port 4 Data 6 or EMIFA memory space enable 2

Video Port 4 Data 7 or EMIFA memory space enable 3

Video Port 4 Data 8 or EMIFA External Address 0 (word address)

(O/Z)

VP4D09/AEA01

VP4D12/AEA02

VP4D13/AEA03

VP4D14/AEA04

VP4D15/AEA05

VP4D16/AEA06

VP4D17/AEA07

VP4D18/AEA08

VP4D19/AEA09

K3

K4

L6

K5

J3

J4

J5

J6

K6

I/O/Z

IPD

3.3 V

Video Port 4 Data 9 or EMIFA External Address 1 (word address)

(O/Z)

Video Port 4 Data 12 or EMIFA External Address 2 (word address)

(O/Z)

Video Port 4 Data 13 or EMIFA External Address 3 (word address)

(O/Z)

Video Port 4 Data 14 or EMIFA External Address 4 (word address)

(O/Z)

Video Port 4 Data 15 or EMIFA External Address 5 (word address)

(O/Z)

Video Port 4 Data 16 or EMIFA External Address 6 (word address)

(O/Z)

Video Port 4 Data 17 or EMIFA External Address 7 (word address)

(O/Z)

Video Port 4 Data 18 or EMIFA External Address 8 (word address)

(O/Z)

Video Port 4 Data 19 or EMIFA External Address 9 (word address)

(O/Z)

EMIFA

AEA23

AEA19

H4

H5

OZ

IPD

IPU

3.3 V

EMIFA External Address 23 (word address) (O/Z)

EMIFA External Address 19 (word address) (O/Z)

I/O/Z

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Table 2-4. TERMINAL FUNCTIONS (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/

OPER

VOLT

DESCRIPTION

PULLDOWN

AECLKINSEL/AEA17

G4

I/O/Z

IPD

3.3 V

Select EMIFA external clock (I) (The EMIFA input clock AECLKIN

or SYSCLK4 is selected at reset via the pullup/pulldown resistor

on this pin. Note: AECLKIN is the default for the EMIFA input

clock.)

or EMIFA external address 17 (word address) (O/Z)

Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/PULLD

OWN

OPER VOLT DESCRIPTION

V_SS

A1

A5

Ground

A15

A18

A23

C4

D9

D12

D20

E6

E23

F7

F15

F17

F19

G8

G10

G12

G14

G16

G18

G22

H1

H11

H13

H15

H17

J8

J10

J12

J14

J16

K7

K9

K11

K13

K15

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Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY) (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/PULLD

OWN

OPER VOLT DESCRIPTION

V_SS

K17

L8

Ground

L10

L12

L14

L16

M7

M9

M11

M13

M15

M17

M22

N1

N8

N10

N12

N14

N16

P7

P9

P11

P13

P15

P17

R10

R12

R14

R16

T7

T9

T11

T13

T15

T17

T22

U14

U16

V1

V9

V17

W7

W22

Y9

Y10

AA3

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Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY) (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/PULLD

OWN

OPER VOLT DESCRIPTION

V_SS

AA8

AA11

AB5

Ground

AB19

AB23

AC1

AC8

AC10

AC12

AC16

POWER PINS

C_VDD

C_VDDESS

A_VDLL1

A_VDLL2

C_VDD1

J9

1.2-V Core Power Supply

J11

J15

K10

K12

K14

L9

1.2-V Core Power Supply

L11

L13

L15

M10

M12

M14

N11

N13

N15

P10

P12

P14

R13

N9

T16

R8

R15

V8

R11

R9

1.2-V Core Power Supply for Ethernet Subsystem

1.8-V I/O supply

B10

B22

H9

1.8-V I/O supply

1.2-V Power supply for DDR, DDR I/Os, EMIF-DDR

Subsystem

C_VDD1

J13

1.2-V Power supply for DDR, DDR I/Os, EMIF-DDR

Subsystem

A_VDDA

V11

1.2-V SerDes Analog supply

W10

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Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY) (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/PULLD

OWN

OPER VOLT DESCRIPTION

D_VDDD

A_VDDR

T10

U10

AB10

AB8

U11

E22

F20

G19

J7

1.2-V SerDes Digital Supply

1.8-V SerDes Analog Supply (Regulator)

1.2-V SerDes Analog Supply

3.3-V I/O supply voltage

1.8-V I/O supply voltage (DDR2 Memory Controller)

A_VDDT

D_VDD33

D_VDD18

H16

H22

J17

K8

K16

L7

L17

M8

M16

M23

N2

N7

N17

P8

P16

R7

R17

T8

T12

T14

G1

T23

AB7

U15

U17

V2

V16

W23

Y4

Y8

AB16

AC2

AC5

AB12

AC19

AC23

B1

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Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY) (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/PULLD

OWN

OPER VOLT DESCRIPTION

D_VDD18

V_REFSSTL

B5

B15

B18

B23

C3

1.8-V I/O supply voltage (DDR2 Memory Controller)

C10

C13

C21

E5

F8

F14

F16

F18

G9

G11

G13

G15

G17

H10

H12

H14

C11

(DVDD18/2)-V reference for SSTL buffer (DDR2

Memory Controller0. This input voltage cn be generated

directly from DVDD18 using two 1-KΩ resistors to form a

resister divider circuit.

V_CCMON

L19

Die-side 1.2-V core supply voltage monitor pin. The

monitor pins indicate the voltage on the die, and,

therefore, provide the best probe point for voltage

monitoring purposes. If the CVDDMON pin is not used, it

should be connected directly to the 1.2-V core supply.

V_DD18MON

V_DD33MON

B2

Die-side 1.8-V I/O supply voltage monitor pin.

Die-side 3.3-V I/O supply voltage monitor pin.

G21

Reserved

RSV 1

RSV 2

RSV 3

RSV 4

RSV 5

RSV 6

RSV 7

L20

L21

D2

D1

D4

D3

H7

A

Reserved. Unconnected

Reserved . Unconnected

O

A

Reserved. These pins must be connected directly to V_SS

for proper device operation.

RSV 8

H8

A

Reserved. These pins must be connected directly to V_SS

for proper device operation.

RSV 9

M2

A2

E2

A

Reserved . Unconnected

RSV 10

RSV 11

Reserved This pin must be connected directly to V_SSfor

proper device operation.

RSV 12

E1

Reserved. This pin must be connected directly to 1.8-V

I/O supply

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Table 2-5. TERMINAL FUNCTIONS (GROUND and POWER SUPPLY) (continued)

TERMINAL NAME

NO

TYPE

INTERNAL

PULLUP/PULLD

OWN

OPER VOLT DESCRIPTION

RSV 13

RSV 14

E4

E3

Reserved This pin must be connected directly to V_SSfor

proper device operation.

Reserved.This pin must be connected directly to 1.8-V

I/O supply

RSV 15

RSV 16

RSV 17

RSV 18

A10

A22

V10

F6

A

I

Reserved . Unconnected

Reserved. These pins must be connected directly to

1.8-V I/O supply(DVDD18) for proper device operation.

RSV 19

C2

Reserved. This pin must be connected to the 1.8-V I/O

supply (DVDD18) via a 200-Ω resistor for proper device

operation.

NOTE: If the DDR2 Memory Controller is not used, the

V_REFSSTL, RSV19, and RSV20 pins can be directly

connected to ground (V_SS) to save power. However,

connecting these pins directly to ground will prevent

boundary scan from functioning on the DDR2 Memory

Controller pins. To preserve boundary-scan functionality

on the DDR2 Memory Controller pins, see Section 6.3.6.

RSV 20

C1

Reserved. This pin must be connected to ground (V_SS)

via a 200-Ω resistor for proper device operation.

NOTE: If the DDR2 Memory Controller is not used, the

V_REFSSTL, RSV19, and RSV20 pins can be directly

connected to ground (V_SS) to save power. However,

connecting these pins directly to ground will prevent

boundary scan from functioning on the DDR2 Memory

Controller pins. To preserve boundary-scan functionality

on the DDR2 Memory Controller pins, see Section 6.3.6.

RSV 21

RSV 22

Y12

Reserved. This pin must be connected via a 20-Ω

resistor directly to 3.3-V I/O Supply (D_VDD33) for proper

device operation. The resistor used should have a

minimal rating of 250 mW

W12

Reserved. This pin must be connected via a 40-Ω

resistor directly to ground (V_SS) for proper device

operation. The resistor used should have a minimal

rating of 100 mW

2.7 Device Support

2.7.1 Development Support

TI offers an extensive line of development tools for the TMS320DM64x DMP platform, including tools to

evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules. The tools support documentation is electronically

available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of TMS320DM64xx DMP-based applications:

Software Development Tools:

Code Composer Studio™ Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target

software needed to support any SoC application.

Hardware Development Tools:

Extended Development System (XDS™) Emulator (supports TMS320DM64x DMP multiprocessor

system debug) EVM (Evaluation Module)

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For a complete listing of development-support tools for the TMS320DM64x DMP platform, visit the

Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator

(URL). For information on pricing and availability, contact the nearest TI field sales office or authorized

distributor.

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2.8 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,

TMP, or TMS (e.g., TMX320DM647ZUT720). Texas Instruments recommends two of three possible prefix

designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of

product development from engineering prototypes (TMX/TMDX) through fully qualified production

devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications.

Final silicon die that conforms to the device's electrical specifications but has not completed

quality and reliability verification.

Fully-qualified production device.

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal

qualification testing.

TMDS

Fully qualified development-support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial

temperature range), and the device speed range in megahertz (for example, "Blank" is the default

[720-MHz]).

Figure 2-6 provides a legend for reading the complete device name for the devices.

TMX

320

DM647 ZUT

( )

DEVICE SPEED RANGE

720 MHz

900 MHz

PREFIX

TMX = Experimental device

TMS = Qualified device

(A)

PACKAGE TYPE

ZUT = 520-pin plastic ball grid array (BGA)

DEVICE FAMILY

320 = TMS320t DSP family

DEVICE

C64x+tDSP:

DM647

DM648

Figure 2-6. Device Nomenclature

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2.9 Documentation Support

2.9.1 Related Documentation From Texas Instruments

The following documents describe the TMS320DM64x Digital Media Processor (DMP). Copies of these

documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box

provided at www.ti.com.

The current documentation that describes the DM64x DMP, related peripherals, and other technical

collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

CPU

SPRU732

TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU

architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+

digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP

generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an

enhancement of the C64x DSP with added functionality and an expanded instruction set.

Reference Guides

SPRUEK5 TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2

memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The

DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant

DDR2 SDRAM devices and standard Mobile DDR SDRAM devices.

SPRUEK6 TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describes

the operation of the asynchronous external memory interface (EMIF) in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The EMIF supports a glueless

interface to a variety of external devices.

SPRUEK7 TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide

describes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648

Digital Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose

pins that can be configured as either inputs or outputs. When configured as an input, you

can detect the state of the input by reading the state of an internal register. When configured

as an output, you can write to an internal register to control the state driven on the output

pin.

SPRUEK8 TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes

the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal

Processor (DSP). The I2C peripheral provides an interface between the DSP and other

devices compliant with the I2C-bus specification and connected by way of an I2C-bus.

External components attached to this 2-wire serial bus can transmit and receive up to 8-bit

wide data to and from the DSP through the I2C peripheral. This document assumes the

reader is familiar with the I2C-bus specification.

SPRUEL0 TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the

64-bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can be

configured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a

watchdog timer.

SPRUEL1 TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide

describes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital

Signal Processor (DSP). The McASP functions as a general-purpose audio serial port

optimized for the needs of multichannel audio applications. The McASP is useful for

time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and

intercomponent digital audio interface transmission (DIT).

SPRUEL2 TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describes

the operation of the enhanced direct memory access (EDMA3) controller in the

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TMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary

purpose is to service user-programmed data transfers between two memory-mapped slave

endpoints on the DSP.

SPRUEL4 TMS320DM647/DM648 Peripheral Component Interconnect (PCI) User's Guide

describes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648

Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a

PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the

DSP via the enhanced DMA (EDMA) controller. This architecture allows for both PCI master

and slave transactions, while keeping the EDMA channel resources available for other

applications.

SPRUEL5 TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the host

port interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is

a parallel port through which a host processor can directly access the CPU memory space.

The host device functions as a master to the interface, which increases ease of access. The

host and CPU can exchange information via internal or external memory. The host also has

direct access to memory-mapped peripherals. Connectivity to the CPU memory space is

provided through the enhanced direct memory access (EDMA) controller.

SPRUEL8 TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART)

User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral

in the TMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral

performs serial-to-parallel conversion on data received from a peripheral device, and

parallel-to-serial conversion on data received from the CPU.

SPRUEL9 TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed

point-to-point serial interface for connecting to host processors and other VLYNQ compatible

devices. It is a full-duplex serial bus where transmit and receive operations occur separately

and simultaneously without interference.

SPRUEM1 TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User's

Guide discusses the video port and VCXO interpolated control (VIC) port in the

TMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a

video capture port, video display port, or transport stream interface (TSI) capture port. The

VIC port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16

bits. When the video port is used in TSI mode, the VIC port is used to control the system

clock, VCXO, for MPEG transport stream.

SPRUEM2 TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial

Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This

reference guide provides the specifications for a 16-bit configurable, synchronous serial

peripheral interface. The SPI is a programmable-length shift register, used for high speed

communication between external peripherals or other DSPs.

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3 Device Configuration

3.1 System Module Registers

The system module includes status and control registers required for configuration of the device. Brief

descriptions of the various registers are shown in Table 3-1. System Module registers required for device

configuration are described in the following sections.

Table 3-1. System Module Register Memory Map

HEX ADDRESS RANGE

0x0204 9000

REGISTER NAME

PINMUX

DESCRIPTION

Pin multiplexing control 0

Reserved

0x0204 9004

0x0204 9008

DSPBOOTADDR

BOOTCMPLT

Boot Address of DSP, decoded by bootloader software for host boots

Boot Complete

0x0204 900C

0x0204 9010

Reserved

0x0204 9014

BOOTCFG

JTAGID

Device boot configuration

0x0204 9018

Device ID number. See Section 6.23 for details.

Bus master priority control See Section 4 for details

Reserved

0x0204 901C

0x0204 9020 -0x0204 9053

0x0204 9054

PRI_ALLOC

Reserved

KEY_REG

Reserved

Key Register to protect against accidental writes.

Reserved

0x0204 9060 - 0x0204 90A7

0x0204 90A8

CFGPLL

CFGPLL inputs for SerDes

Configure SGMII0 RX

0x0204 90AC

0x0204 90B0

CFGRX0

CFGTX0

Configure SGMII0 TX

0x0204 90B4

CFGRX1

Configure SGMII1 RX

0x0204 90B8

CFGTX1

Configure SGMII1 TX

0x0204 90BC

0x0204 90C0

0x0204 90C4

0x0204 90C8

0x0204 90CC

0x0204 90D0

0x0204 90D4

Reserved

MAC_ADDR_R0

MAC_ADDR_R1

MAC_ADDR_RW0

ESS_LOCK

MAC Address Read Only Register 0

MAC Address Read Only Register 1

MAC Address Read/Write Register 0

MAC Address Read/Write Register 1

Ethernet Sub System Lock Register

3.2 Bootmode Registers

The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status

levels of various pins required for proper boot are stored within these registers.

3.2.1 Boot Configuration (BOOTCFG) Register

Configuration pins latched at reset are presented in the BOOTCFG register accessible through the system

module. This is a read-only register. The bits show the true latched value of the corresponding input at

RESET or POR deassertion. This is desirable since the most important use of this MMR is for the user to

debug/view the actual value driven on the pins during device reset.

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Figure 3-1. BOOTCFG Register

31

24

Reserved

R-0

23

22

21

20

19

18

17

16

AECLKINSEL

PC166

HPIWIDTH

Reserved

FASTBOOT

Reserved

DUHPIEN

EMIFAWIDTH

R-L

R-1

R-L

R-1

R-L

8

15

Reserved

7

4

3

0

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; L = latched; -n = value after reset

BOOTMODE

R-L

Table 3-2. BOOTCFG Register Field Descriptions

Bit

Field

Value Description

Reserved

31:24 Reserved

23

22

21

AECLKINSEL

Controls the clock input for EMIFA. Latched from AECLKINSEL at RESET or POR deassertion

1

0

EMIFA clocked from internal SYSCLK

EMIFA clocked from outside from AECLKIN

PCI66

Controls PCI speed. PCI. Latched from PCI66 at RESET or POR deassertion

0

1

33 MHz PCI

66 MHz

HPIWIDTH

Controls HPI bus width. Latched from HPIWIDTH at RESET or POR deassertion

0

1

16 bit

32 bit

20

19

Reserved

FASTBOOT

Fast Boot. Latched from FASTBOOT at RESET or POR deassertion

0

1

No Fast Boot

Fast Boot

18

17

Reserved

DUHPIEN

Reserved

PCI Enable Default. Latched from UHPIEN at RESET or POR deassertion

0

1

UHPI disabled

UHPI enabled

16

EMIFAWIDTH

EMIFA CS2 Bus Width Default. Latched from EMIFAWIDTH at RESET or POR deassertion

0

1

8-bit

16-bit

15:4

3:0

Reserved

BOOTMODE

Boot Mode. Latched from BOOTMOD at RESET or POR deassertion

3.2.2 DSPBOOTADDR Register Description

The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register

format is shown in Figure 3-2 and bit field descriptions are shown in Table 3-3. DSPBOOTADDR is

readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the

default of the DSPBOOTADDR Register. It can default to either the base address of L2 ROM

(0x00800000) or the base address of EMIFA CS2 (0xA0000000)

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Figure 3-2. DSPBOOTADDR Register

31

10

9

0

BOOTADDR

Reserved

R-0

R/W-0100 0010 0010 0000 0000 00

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-3. DSPBOOTADDR Register Field Descriptions

Bit

31:10 BOOTADDR

9:0 Reserved

Field

Value Description

Upper 22 bits of the C64x+ DSP bootmode address

Reserved

3.2.3 Boot Complete (BOOTCMPLT) register

The BOOTCMPLT register contains a BC (boot complete) field in bit 0, and a ERR (boot error) field in bits

19:16.

The BC field is written by the external host to indicates that it has completed boot. In the bootloader code,

the CPU can poll for this bit. Once this bit = 1, the CPU can begin executing from DSPBOOTADDR.

The ERR field is written by the bootloader software if the software detects a boot error. Coming out of a

boot, application software can read this field to determine if boot was accomplished. Actual error code is

determined by software.

Figure 3-3. BOOTCMPLT Register 3

31

20 19

16 15

1

0

Reserved

R-0

ERR

R-0

Reserved

R-0

B

C

R-

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-4. BOOTCMPLT Register Field Descriptions

Bit

Field

Value

Description

Reserved

Boot error

No error

31:20 Reserved

19:16 ERR

0000

0001 – 1111

Bootloader software detected boot error. For details on boot errors, see the Using the

TMS320DM647x Bootloader Application Note (literature number SPRAAAJ1).

15:1

0

Reserved

BC

Reserved

Boot Complete Flag from host. This is applicable only to host boots.

Host has not completed booting this device.

0

1

Host has completed booting this device and the DSP can begin executing from

DSPBOOTADDR.

3.2.4 Priority Allocation (PRI_ALLOC)

On the DM647/DM648 devices, each of the masters (excluding the C64x+ Megamodule) is assigned a

priority via the Priority Allocation Register (PRI_ALLOC), see Figure 3-4. The priority is enforced when

several masters in the system are vying for the same endpoint. A value of 000b has the highest priority,

while 111b has the lowest priority.

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Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will

be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the

configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the

C64x+ Megamodule.

The Ethernet Subsystem and VLYNQ fields specify the priority of the EMAC and VLYNQ peripherals,

respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals. Other master

peripherals are not present in the PRI_ALLOC register as they have their own registers to program their

priorities. For more information on the default priority values in these peripheral registers, see the

device-compatible peripheral reference guides.

TI recommends that these priority registers be reprogrammed upon initial use.

Table 3-5. Default Master Priorities

Master

Default Priority

EDMA3TC0

EDMA3TC1

EDMA3TC2

EDMA3TC3

64x+_DMAP

64x+_CFGP

Ethernet Subsystem

VLYNQ

0 (EDMA CC QUEPRI Register)

7 (C64x+ MDMAARBE.PRI Register bit field)

1 (C64x+ MDMAARBE.PRI Register bit field)

3 (PRI_ALLOC register)

4 (PRI_ALLOC register)

UHPI

4 (PRI_ALLOC register)

PCI

4 (PRI_ALLOC register)

VICP

5 (PRI_ALLOC register)

Figure 3-4. Priority Allocation Register (PRI_ALLOC)

31

16

0

Reserved

R-0000000111001111

15

12

11

9

8

6

5

3

2

Reserved

VICP

VLYNQ

HOST

Ethernet Subsystem

R-0111

R/W-101

R/W-100

R/W-011

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

3.2.5 KEY_REG

KEY_REG protects against accidental writes to certain system configuration registers. The complete set of

registers protected by the KEY_REG is:

•

PINMUX

BOOTCFG

PRI_ALLOC

CFGPLL

CFGRX0

CFGTX0

CFGRX1

CFGTX1

MAC_ADDR_RW0

MAC_ADDR_RW1

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Writes to these registers are locked/blocked by default. To enable writes to these registers, write

0xADDDECAF to the KEY_REG. After enabling writes to protected registers by doing the above, the

register writes should occur within 10000 CPU/6 cycles, after which the key will be reset.

Figure 3-5. KEY_REG

31

0

KEY_REG

W-0x00000000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

3.2.6 PINMUX Register

All pin multiplexing options are controlled by software via PINMUX register (except the ones mentioned in

Table 3-7, whose default is selected by configuration pins). This PINMUX register reside within the system

module portion of the CFG bus memory map. The format of the registers and a description of the pins

they control are in the following sections.

The PINMux Register controls all the software-controlled pin muxing. The register format is shown in

Figure 3-6. A brief description of each field is shown in Table 3-6.

Figure 3-6. PINMUX Register

31

15

22

21

20

19

18

17

16

Reserved

GPIO_EN

Reserved

VPI_EN

R-0000 0000 00

R/W-00

R-00

R/W-00

14

13

12

11

10

9

8

7

6

5

4

3

1

0

VP34_EN

SPI_UART_EN

Reserved

MCASP_EN

Reserved

VLYNQ_EN

Reserved

TIMER

_EN

R/W-00

R-00

R/W-00

R-00

R/W-00

R-000

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-6. PINMUX Register Field Descriptions

Bit

Field

Value Description

31:22 Reserved

21:20 GPIO_EN

Reserved

Controls the pin muxing between Video Port 0 and the GPIO[12:15]

(1)

(2)

UNMUXED

SECONDARY MUXED⁽³⁾

.VP0D16-19

3-state

VP0D02-09/CLK/CTL

3-state

VP0D12-15 GP12-15

00

01

10

11

3-state

Enable

VP0D12-15

GP12-15

3-state

Enable

19:18 Reserved

Reserved

(1) The complete list of pins: U20, U21, U22, R18.

(2) The complete list of pins: Y23, V23, Y22, V22, U23, W20, V18, U18, V19, W21, T18, U19, V20.

(3) The complete list of pins: V21, T19, T20, T21.

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Table 3-6. PINMUX Register Field Descriptions (continued)

Bit

Field

Value Description

17:16 VP1_EN

Controls the pin muxing between Video Port 1 and GPIO[16:31]

(5)

.

UNMUXED⁽⁴⁾

MUXED

VP1CLK0-

1/VP1CTL0-2

VP1 Data

(V1D02-09/12-19)

GP[16-31]

00

01

10

11

3-state

Enable

3-state

GP16-31

VP1D02-09 and VP1D12-19

(6)

15:14 VP34_EN

Controls the pin muxing between Video Port 3-4 and EMIFA

.

UNMUXED⁽⁷⁾

VP4D05/VP4CLK1

3-state

MUXED⁽⁸⁾

VP3/VP4

EMIFA

00

01

10

11

3-state

Disable

EMIFA

Enable

VP3/VP4

13:12 SPI_UART_EN

Controls the pin muxing between SPI and UART

(9)

(10)

UNMUXED

MUXED

SPI or UART

3-state

SPICLK

3-state

Enable

Disable

Enable

00

01

10

11

SPI

UART

SPIDI

SPIDO

UART_TX

UART_RX

11:10 Reserved

Reserved

(4) The complete list of pins: P23, N23, R23, P22, N22

(5) The complete list of pins: R19, P19, P18, R22, R21, R20, N21, N20, N19, P21, P20, M20, M18, N18, M21, M19

(6) The value of VP34_EN depends on the BOOTMODE[3:0] pin value at reset. If the BOOTMODE[3:0] is 0100 the VP3/4 and the EMIFA

mux will default to EMIFA enable (the value is 10b).

(7) The complete list of pins: K1, M6.

(8) The complete list of pins: T1, P1, T2, R1, P2, T6, T5, T4, T3, R6, R5, R4, R3, R2, P6, P5, P4, P3, N4, N6, N5, L1, J2, J1, K2, L2, M4,

M5, L3, L4, L5, K3, K4, L6, K5, J3, J4, J5, J6, K6.

(9) The complete list of pin:F22

(10) The complete list of pins: D23, F23, G23, F21

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Table 3-6. PINMUX Register Field Descriptions (continued)

Bit

Field

Value Description

9:8

MCASP_EN

Controls the pin muxing between McASP and VIC

UNMUXED

(11)

.

MUXED

STCLK, VCTL, or McASP

3-state

00

01

10

McASP (all McASP Pins)

(McASP without AXR8, AXR9)

ACLKR

AFSR

AXR0

AXR1

AC:LKX

AFSX

AXR2

AXR3

AHCLKR

AMUTEIN

AXR4

AXR5

AHCLKX

AMUTE

AXR6

AXR7

STCLK

VCTL

11

Reserved

7:6

5:4

Reserved

VLYNQ_EN

Controls the pin muxing between Video Port 2 and VLYNQ

.

UNMUXED⁽¹²⁾

MUXED⁽¹³⁾

VP2#2 VLYNQ

VP2#1

00

01

10

11

3-state

Enable

VP2D12-19, VP2CLK1, VP2CTL2

VRXD0-3 and VTXD0-3, VCLK, VSCRUN

Enable

3:1

0

Reserved

TIMER_EN

Controls the pin muxing between TIMER and GPIO[8:11]

.

MUXED⁽¹⁴⁾

(E20, D21, E21, C22)

0

1

GPIO[8:11]

Timer 0/1

(11) The complete list of pins: AC4, AC3, AC6, AC7, W6, AA7, AB6, Y6, AA6, AB4, Y5, V7, AA4, V6, Y7, AA5, AB3, U7

(12) For the first half of the Video Port 2, the complete list of pins with function: AB1(VP2CLK0), AA1 (VP2CTL0), AB2 (VP2CTL1) and W5,

AA2, Y3, U6, Y2, W3, V5, W4 (VP2D02, VP2D03, VP2D04, VP2D05, VP2D06, VP2D07, VP2D08, VP2D09)

(13) For the second half of the Video Port 2, the complete list of pins with function: W1 (VP2CLK1/VCLK), Y1(VP2CTL2/VSCRUN), W2, V3,

V4, U1, U3, U2, U5, U4 (VP2D12/VRXD0, VP2D13/VRXD1, VP2D14/VRXD2, VP2D15/VRXD3, VP2D16/VTXD0, VP2D17/VTXD1,

VP2D18/VTXD2, VP2D19/VTXD3)

(14) The complete list of pins:E20, D21, E21, C22

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Table 3-7. PCI/UHPI/GPIO Block: PCI MUXed With UHPI and GPIO[0:7]

MUXED⁽¹⁾

PCI

UHPI/GPIO[0:7]

UHPIEN (pin)

1

0

UHPI/GPIO[0:7]

PCI

(1) The complete list of pin:AA22, AB22, AC21, AA23, AC22, AB21, AA21, Y21, AB20, AA20, Y20, Y19, AB18, AA19, AC18, AA18, Y16,

AB15, AA15, Y15, W15, V15, AC14, AB14, W14, V14, AC13, AB13, AA13, Y13 , W13, V13, W19, Y18, Y17, W17, W18, AC20, AC17,

W16, Y14, AC15, AA16, AB17, U13, U12, V12, AA12, AA17, AA14.

For information on the Ethernet Subsystem registers, see the TMS320DM647/DM648 DMP DSP

Subsystem Reference Guide (literature number SPRUEU6).

Figure 3-7. SerDes Macro Configuration (SERDES_CFG_CNTL) Register

31

15

16

Reserved

10

9

8

7

5

4

1

0

Reserved

R-0

LB

Reserved

R-0

MPY

ENPLL

R/W-0

R/W-1001

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

3.2.7 ESS_LOCK

The ESS_LOCK register protects the Ethernet Subsystem MMR space (0x02D0 0000 - 0x02D0 4FFF)

and the Ethernet Subsystem's LPSC (LPSC34) MDCTL register (0x0204 6088). The default value of

ESS_LOCK is 0x0000 0000 and read/write is allowed to Ethernet Subsystem MMR space and MDCTL

[34]. To lock the write access to both Ethernet Subsystem MMR space and MDCTL [34], software must

write a value of 0x AAAA AAAA to the ESS_LOCK register. To make sure that the desired lock has been

achieved, the software must read the ESS_LOCK register till it gets a value of 0x1. The software must

make sure that there are no pending accesses to either the Ethernet Subsystem MMR space or MDCTL

[34]. Read access to both Ethernet Subsystem MMR space and MDCTL [34] should be unaffected while

write accesses are locked. To unlock the write access to Ethernet Subsystem MMR space and MDCTL

[34], the software must write a value of 0xCCCC CCCC to ESS_LOCK. To make sure that the desired

write lock has been removed, the software must read ESS_LOCK till it gets a value of 0x0.

Figure 3-8. ESS_LOCK Register

31

0

ESS_LOCK

R/W-0x00000000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

3.2.8 MAC Address Registers

•

MAC_ADDR_R0

MAC_ADDR_R1

MAC_ADDR_RW0

MAC_ADDR_RW1

In DM647/DM648, two sets of registers provide default MAC addresses for the device. One set -

MAC_ADDR_R0 and MAC_ADDR_R1 - is read only and the other set - MAC_ADDR_RW0 and

MAC_ADDR_RW1 - includes read and write registers.

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Figure 3-9. MAC_ADDR_R0 Register

31

0

MAC_ID

R-MAC ADDRESS[31:0]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-8. MAC_ADDR_R0 Register Field Descriptions

Bit

Field

Value

Mac

Description

Bit 0 of MAC_ID is bit 0 of MAC Address

31:0

MAC_ID

Address[31:0] of

the device

Figure 3-10. MAC_ADDR_R1 Register

31

15

24

23

16

CRC

Reserved

R-CRC for the MAC_ID

R-00000000

0

MAC_ID

R-MAC ADDRESS[47:32]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-9. MAC_ADDR_R1 Register Field Descriptions

Bit

Field

Value

Description

31:24 CRC

CRC of the MAC This field will hold the CRC of the MAC address of that particular device.

ID

23:16 Reserved

0x00

Reserved

15:0

MAC_ID

Mac

Bit 0 of MAC_ID is Bit 32 of MAC Address

Address[47:32] of

the device

Figure 3-11. MAC_ADDR_RW0 Register

31

0

MAC_ADDR_R0

R/W - MAC ID[31:0]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-10. MAC_ADDR_RW0 Register Field Descriptions

Bit

Field

Value

Mac

Description

Bit 0 of MAC_ID is bit 0 of MAC Address

31:0

MAC_ID

Address[31:0] of

the device

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Figure 3-12. MAC_ADDR_RW1 Register

31

15

24

23

16

CRC

Reserved

R/W-CRC for the MAC_ID

R/W-00000000

0

MAC_ID

R-MAC ADDRESS[47:32]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3-11. MAC_ADDR_RW1 Register Field Descriptions

Bit

Field

Value

CRC of the

Description

This field will hold the CRC of the MAC address of that particular device.

31:24 CRC

MAC ID

23:16 Reserved

0x00

Reserved

15:0

MAC_ID

Mac

Bit 0 of MAC_ID is Bit 32 of MAC Address

Address[47:32]

of the device

3.3 Debugging Considerations

3.4 Pullup/Pulldown Resistors

Proper board design should specify that input pins to the device always be at a valid logic level and not

floating. This may be achieved via pullup/pulldown resistors. The DM64x features internal pullup (IPU) and

internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external

pullup/pulldown resistors.

An external pullup/pulldown resistor must be used in the following situations:

•

Boot and Configuration Pins: If the pin is both routed out and in high-impedance mode, an external

pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

•

Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external

pullup/pulldown resistor to pull the signal to the opposite rail.

If the boot and configuration pins are both routed out and in high-impedance mode, it is recommended

that an external pullup/pulldown resistor be used. Although internal pullup/pulldown resistors exist on

these pins and they may match the desired configuration value, providing external connectivity can help

specify that valid logic levels are latched on these important boot configuration pins. In addition, applying

external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in

debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

•

Select a resistor with the largest possible resistance

Calculate the worst-case leakage current that flows through this external resistor. Worst-case leakage

current can be calculated by adding up all the leakage current at the pin—e.g., the input current (I_I)

from DM64x, and leakage current from the other device(s) to which this pin is connected.

•

Specify that the voltage at the pin stays well within the low-/high-level input voltages (V_ILor V_IH) when

worst-case leakage current is flowing through this external resistor.

–

To oppose an IPU and pull the signal to a logic low, the voltage at the pin must stay well below V_IL.

To oppose an IPD and pull the signal to a logic high, the voltage at the pin must stay well above

V_IH.

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For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.

Users should confirm this resistor value is correct for their specific application.

For most systems, a 20-kΩ resistor can be used to complement the IPU/IPD on the boot and configuration

pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific

application.

For more detailed information on input current (I_I), and the low-/high-level input voltages (V_ILand V_IH) for

the DM64x device, see Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply

Voltage and Operating Temperature.

For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal

functions table.

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4 System Interconnect

On the DM647/DM648 devices, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system

peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency,

concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric, the

CPU can send data to the video ports without affecting a data transfer between the PCI and the DDR2

memory controller. The switch fabrics also allow for seamless arbitration between the system masters

when accessing system slaves.

4.1 Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the DM647/DM648 devices: data buses and configuration buses. Some

DM647/DM648 peripherals have both a data bus and a configuration bus interface, while others only have

one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.

Configuration buses are mainly used to access the register space of a peripheral and the data buses are

used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer

data. For example, data is transferred to the UART or I2C via their configuration bus. Similarly, the data

bus can also be used to access the register space of a peripheral. For example, the EMIFA and DDR2

memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be

classified into two categories: masters and slaves. Masters are capable of initiating read and write

transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand,

rely on the EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers

and PCI. Slaves include the McASP, video port, and I2C.

The DM647/DM648 devices contain two switch fabrics through which masters and slaves communicate.

The data switch fabric, known as the data switched central resource (SCR), is a high-throughput

interconnect mainly used to move data across the system (for more information, see Section 4.2). The

data SCR connects masters to slaves via 128-bit data buses running at a SYSCLK2 frequency (SYSCLK2

is generated from PLL1 controller). Peripherals that have a 128-bit data bus interface running at this

speed can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly

used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3).

The configuration SCR connects C64x+ Megamodule to slaves via 32-bit configuration buses running at a

SYSCLK2 frequency (SYSCLK2 is generated from PLL1 controller). As with the data SCR, some

peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also

connects to the configuration SCR. Bridges perform a variety of functions:

•

Conversion between configuration bus and data bus.

Width conversion between peripheral bus width and SCR bus width

Frequency conversion between peripheral bus frequency and SCR bus frequency

For example, the EMIFA memory controller require a bridge to convert their 64-bit data bus interface into a

128-bit interface so that they can connect to the data SCR.

Note that some peripherals can be accessed through the data SCR and also through the configuration

SCR.

4.2 Data Switch Fabric Connections

Figure 4-1 shows the connection between slaves and masters through the data switched central resource

(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves

via 128-bit data buses running at a SYSCLK2 frequency. SYSCLK2 is supplied by the PLL1 controller and

is fixed at a frequency equal to the CPU frequency divided by 3. Some peripherals, like PCI and the

C64x+ Megamodule, have both slave and master ports. Note that each EDMA3 transfer controller has an

independent connection to the data SCR.

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Note that masters can access the configuration SCR through the data SCR. The configuration SCR is

described in Section 4.3.

Not all masters on the DM647/DM648 DSPs may connect to all slaves. Allowed connections are

summarized in Table 4-1.

128 SYSCLK2

S

Megamodule

M

128 SYSCLK2

S

0

S

1

M0

DDR2

Memory

Controller

128 SYSCLK2

EDMA3 M1

Transfer

S

2

128 SYSCLK2

Controller

M2

128

64

SYSCLK2

S

3

SYSCLK2

M3

M

S

EMIFA

Bridge

64

SYSCLK2

64

SYSCLK2

128 SYSCLK2

32 SYSCLK3

S

Video Port 0

Megamodule

M

64

SYSCLK2

S

Video Port 1

Bridge

32 SYSCLK3

64

SYSCLK2

HPI

M

Video Port 2

Video Port 3

128 SYSCLK2

Bridge

PCI

64

SYSCLK2

64

SYSCLK2

S

VLYNQ

32 SYSCLK3

32 TXBCLK

128 SYSCLK2

64

SYSCLK2

Bridge

M

128 SYSCLK2

3-port Gigabit

Ethernet Switch

S

Video Port 4

PCI

M

Bridge

128 SYSCLK2

32

SYSCLK3

32

SYSCLK3

S

32

SYSCLK3

Bridge

M

S

VLYNQ

128 SYSCLK2

32

128

SYSCLK2

S

Config SCR

Bridge

Figure 4-1. Data SCR

50

System Interconnect

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Table 4-1. Connectivity Matrix for Data SCR

MEGAMODULE

DDR2 EMIF

EMIFA

VIDEO

PORT 0-2 PORT 3-4

VIDEO

PCI

VLYNQ

Configuration

SCR

TC0

TC1

TC2

TC3

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Megamodule

HPI

PCI

VLYNQ

Ethernet Subsystem

4.3 Configuration Switch Fabric

Figure 4-2 shows the connection between the C64x+ megamodule and the configuration SCR, which is

mainly used by the C64x+ Megamodule to access peripheral registers. The data SCR also has a

connection to the configuration SCR that allows masters to access most peripheral registers. The only

registers not accessible by the data SCR through the configuration SCR are the device configuration

registers and the PLL1 and PLL2 controller registers; these can be accessed only by the C64x+

Megamodule. The configuration SCR uses 32-bit configuration buses running at SYSCLK2 frequency.

SYSCLK2 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency

divided by 3.

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32

SYSCLK2

32

TXBCLK

Ethernet

SubSystem

Config SCR

M

Bridge

S

32

SYSCLK2

32

SYSCLK2

S

Video Port 0

Video Port 1

Video Port 2

Video Port 3

32

SYSCLK2

32

SYSCLK2

M

Bridge

S

32

SYSCLK2

S

32

SYSCLK2

128

SYSCLK2

Video Port 4

UART

32

SYSCLK2

S

32

SYSCLK2

I2C

32

SYSCLK2

S

Timer 0

Timer 1

Timer 2

Timer 3

32

SYSCLK2

32

SYSCLK2

S

32

SYSCLK2

32 SYSCLK2

32

SYSCLK2

S

Megamodule M

32

SYSCLK2

PSC

S

32

SYSCLK2

32 SYSCLK2

S

Data SCR

VICP

M

PLL Controllers

PCI

M

Bridge

32

SYSCLK2

32 SYSCLK3

32 SYSCLK2

S

Bridge

M

32

SYSCLK2

32

SYSCLK2

McASP

SPI

32

SYSCLK2

S

32

SYSCLK2

VIC

32

SYSCLK2

S

GPIO

32

SYSCLK2

S

VICP CFG

HPI

32

SYSCLK2

32

SYSCLK2

S

EDMA3 CC

EDMA3 TC0

32

SYSCLK2

32

SYSCLK2

32

SYSCLK2

S

EDMA3 TC1

EDMA3 TC2

M

Bridge

32

SYSCLK2

32

SYSCLK2

32

SYSCLK2

S

EDMA3 TC3

Figure 4-2. Configuration SCR

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5 Device Operating Conditions

5.1 Absolute Maximum Ratings Over Operating Temperature Range (Unless Otherwise

Noted)⁽¹⁾

Supply voltage ranges:

Core (C_VDD, C_VDDESS, C_VDD1, A_VDDA, D_VDDD

,

1.20-V operation

–0.5 V to 1.5 V

(2)

A_VDDT

)

(2)

I/O, 3.3V (D_VDD33

)

–0.5 V to 4.2 V

–0.5 to 2.5 V

(2)

I/O, 1.8V (D_VDD18, A_VDLL1, A_VDLL2, A_VDDR

)

Input voltage ranges:

Output voltage ranges:

V_II/O, 3.3-V pins

–0.5 V to 4.2 V

–0.5 V to 2.5 V

–0.5 V to 4.2 V

–0.5 V to 2.5 V

0°C to 90°C

V_II/O, 1.8 V

V_OI/O, 3.3-V pins

V_OI/O, 1.8 V

Operating Junction temperature ranges,

T_J:

Commercial

Storage temperature range, T_stg

(default)

–65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS.

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5.2 Recommended Operating Conditions

MIN

1.14

NOM

MAX

1.26

UNIT

(1)

C_VDD

Supply voltage, Core

(1)

C_VDDESS

C_VDD1

A_VDDA

D_VDDD

A_VDDT

D_VDD33

D_VDD18

A_VDLL1

A_VDLL2

A_VDDR

V_SS

Supply voltage, Ethernet Subsystem Core

(1)

Supply voltage, DDR Core

(-720, -900

devices)

1.2

V

(1)

Supply voltage, SerDes Analog

(1)

Supply voltage, SerDes Digital

(1)

Supply voltage, SerDes Analog

Supply voltage, I/O, 3.3 V

Supply voltage, DDR I/O, 1.8 V

Supply voltage, I/O, 1.8 V

3.14

1.71

3.3

1.8

3.46

1.89

V

Supply voltage, 1.8-V SerDes Analog Supply (Regulator)

Supply ground (V_SS

)

0

0.49D_VDD18

2

0

V

V_REFSSTL

DDR2 reference voltage⁽²⁾

0.5D_VDD18

0.51D_VDD18

High-level input voltage, 3.3 V(except I2C pins)

High-level input voltage, I2C

V_IH

0.7D_VDD33

Low-level input voltage, 3.3 V(except I2C pins)

Low-level input voltage, I2C

0.8

0.3DV_DD33

90

V

V_IL

0

V

T_J

Operating Junction temperature⁽³⁾

Commercial

° C

MHz

(-900 devices)

(-720 devices)

33.3

900

F_SYSCLK1

DSP Operating Frequency (SYSCLK1)

720

(1) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance

options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,

1.1 V, 1.14 V, 1.2, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin

configuration modifications. Not incorporating a flexible supply may limit the system ability to easily adapt to future versions of TI SOC

devices.

(2) V_REFSSTLis expected to equal 0.5DV_DDR2of the transmitting device and to track variations in the D_VDD18

.

(3) In the absence of a heat sink, use the following formula to determine the device junction temperature: T_J= T_C+ (Power x Psi_JT). Power

and T_Ccan be measured by the user.

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5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

High-level output voltage (3.3-V I/O except

I2C pins)

V_OH

DV_DD33= MIN, I_OH= MAX

V

Low-level output voltage (3.3-V I/O except

I2C pins)

DV_DD33= MIN, I_OL= MAX

V

V_OL

Low-level output voltage (3.3-V I/O I2C

pins)

I_O= 3 mA

V

V_I= V_SSto DV_DD33without internal resistor

µA

V_I= V_SSto DV_DD33with internal pullup resistor

(2)

Input current [dc]

I_I

V_I= V_SSto DV_DD33with opposing internal

pulldown resistor

µA

(2)

Input current [dc] (I2C)

V_I= V_SSto DV_DD33

µA

mA

µA

DDR2

I_OH

High-level output current [dc]

All other peripherals

DDR2

I_OL

Low-level output current [dc]

All other peripherals

V_O= DV_DD33or V_SS; internal pull disabled

V_O= DV_DD33or V_SS; internal pull enabled

CV_DD= 1.2-V, DSP clock = 720 MHz

CV_DD= 1.2-V, DSP clock = 900 MHz

DV_DD= 3.3-V, DSP clock = 720 MHz

DV_DD= 3.3-V, DSP clock = 900 MHz

DV_DD= 1.8-V, DSP clock = 720 MHz

I_OZ

I/O Off-state output current

µA

mA

I_CDD

Core (CV_DD, V_{DDA_1P1V}) supply current⁽³⁾

3.3-V I/O (DV_DD33) supply current⁽³⁾

I_DDD

1.8-V I/O (DV_DDR2, DDR_VDDDLL,

PLLV_PRW18, V_{DDA_1P8V}, MXV_DD) supply

current⁽³⁾

I_DDD

DV_DD= 1.8-V, DSP clock = 900 MHz

mA

C_I

Input capacitance

Output capacitance

pF

C_o

(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.

(3) Measured under the following conditions.

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6 Peripheral Information and Electrical Specifications

6.1 Parameter Information

Tester Pin Electronics

Data Sheet Timing Reference Point

42 Ω

3.5 nH

Output

Under

Test

Transmission Line

Z0 = 50 Ω

(see Note)

Device Pin

(see Note)

4.0 pF

1.85 pF

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must

be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission

line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 6-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of ac timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

6.1.1 3.3-V Signal Transition Levels

All input and output timing parameters are referenced to V_reffor both 0 and 1 logic levels. For 3.3-V I/O,

V_ref= 1.5 V. For 1.8-V I/O, V_ref= 0.9 V.

V

ref

Figure 6-2. Input and Output Voltage Reference Levels for ac Timing Measurements

All rise and fall transition timing parameters are referenced to V_ILMAX and V_IHMIN for input clocks,

V_OLMAX and V_OHMIN for output clocks.

V

ref

= V MIN (or V MIN)

IH OH

V

ref

= V MAX (or V MAX)

IL OL

Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels

6.1.2 3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 Vpns).

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6.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data sheet do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis Application Report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate for any timing differences.

For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external

device and from the external device to the DSP. This round-trip delay tends to negatively impact the input

setup time margin, but also tends to improve the input hold time margins (see Table 6-1 and Figure 6-4).

Figure 6-4 represents a general transfer between the DSP and an external device. The figure also

represents board route delays and how they are perceived by the DSP and the external device.

Table 6-1. Board-Level Timing Example

(see Figure 6-4)

NO.

1

DESCRIPTION

Clock route delay

2

Minimum DSP hold time

3

Minimum DSP setup time

External device hold time requirement

External device setup time requirement

Control signal route delay

External device hold time

4

5

6

7

8

External device access time

DSP hold time requirement

DSP setup time requirement

Data route delay

9

10

11

AECLKOUT

(Output from DSP)

1

AECLKOUT

(Input to External Device)

2

3

(A)

Control Signals

(Output from DSP)

4

5

6

Control Signals

(Input to External Device)

7

8

(B)

Data Signals

(Output from External Device)

9

10

11

(B)

Data Signals

(Input to DSP)

A. Control signals include data for writes.

B. Data signals are generated during Reads from an external device.

Figure 6-4. Board-Level Input/Output Timings

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6.2 Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V_IHand V_IL(or between V_ILand V_IH) in a monotonic

manner.

6.3 Power Supplies

For more information regarding TI's power management products and suggested devices to power TI

DSPs, visit www.ti.com/dsppower.

6.3.1 Power-Supply Sequencing

The DM647/8 includes 1.2-V core supply (CVDD, CVDDESS, CVDD1, AVDDA, DVDDD, AVDDT), and

two I/O supplies—3.3-V (DVDD33) and 1.8-V (DvDD18, AVDLL1, AVDLL2, AVDDR) To ensure proper

device operation, a specific power-up sequence must be followed. Some TI power-supply devices include

features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable features. For

more information on TI power supplies and their features, visit www.ti.com/dsppower.

Here is a summary of the power sequencing requirements:

•

The power ramp order must be 3.3-V (DVDD33) before 1.8-V (DvDD18, AVDLL1, AVDLL2, AVDDR),

and 1.8-V (DVDD18, AVDLL1, AVDLL2, AVDDR) before 1.2-V core supply (CVDD, CVDDESS,

CVDD1, AVDDA, DVDDD, AVDDT) —meaning during power up, the voltage at the 1.8-V rail should

never exceed the voltage at the 3.3-V rail. Similarly, the voltage at the 1.2-V rail should never exceed

the voltage at the DVDDR2 rail.

•

From the time that power ramp begins, all power supplies (3.3 V, 1.8 V, 1.2 V) must be stable within

200 ms. The term "stable" means reaching the recommended operating condition (see Section 5.2,

Recommended Operating Conditions).

6.3.2 Power-Supply Design Considerations

Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and

resistance in the power delivery path. Additionally, when designing for high-performance applications

utilizing the DM647/8 device, the PC board should include separate power planes for core, I/O, and

ground; all bypassed with high-quality low-ESL/ESR capacitors.

6.3.3 Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as

possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum

distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a

yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling

capacitors; therefore physically smaller capacitors should be used while maintaining the largest available

capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large

bulk caps (on the order of 100 F) should be furthest away, but still as close as possible. Large caps for

each supply should be placed outside of the BGA footprint.

6.3.4 Power and Sleep Controller (PSC)

The power and sleep controller (PSC) controls power by turning off unused power domains or by gating

off clocks to individual peripherals/modules. The DM647/DM648 devices use the clock-gating feature of

the PSC only for power savings. The PSC consists of a global PSC (GPSC) and a set of local PSCs

(LPSCs).

The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each

peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset

control. The LPSCs for DM647/DM648 are shown in Table 6-2. The PSC register memory map is given in

Table 6-3. For more details on the PSC, see the TMS320DM647/TMS320DM648 DMP DSP Subsystem

Reference Guide (Literature Number SPRUEU6).

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Table 6-2. DM647/DM648 LPSC Assignments

LPSC NUMBER

PERIPHERAL/ MODULE

LPSC NUMBER

PERIPHERAL/ MODULE

0

1

EDMA3CC

Reserved

DDR2 Memory Controller

UHPI

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

PCI

VP0

2

VP1

3

VP2

4

VP3

5

VP4

6

EMIFA

7

TIMER2

TIMER3

VIC

8

9

VLYNQ

10

11

12

13

14

15

16

17

18

GPIO

McASP

UART

TIMER0

TIMER1

VICP

Reserved

SPI

Reserved

C64x+ CPU

Ethernet Subsystem

I2C

Table 6-3. PSC Register Memory Map

HEX ADDRESS RANGE

0x0204 6000

REGISTER ACRONYM

DESCRIPTION

PID

–

Peripheral Revision and Class Information Register

0x0204 6004- 0x0204 600F

0x0204 6010

Reserved

–

Reserved

0x0204 6014

Reserved

0x0204 6018

INTEVAL

Interrupt Evaluation Register

0x0204 601C- 0x0204 603F

0x0204 6040

–

Reserved

–

Reserved

0x0204 6044

MERRPR1

Module Error Pending 1 (mod 32- 63) Register

0x0204 6048- 0x0204 604F

0x0204 6050

–

Reserved

–

Reserved

0x0204 6054

MERRCR1

Module Error Clear 1 (mod 32 - 63) Register

0x0204 6058- 0x0204 605F

0x0204 6060

–

Reserved

–

Reserved

0x0204 6064- 0x0204 6067

0x0204 6068

–

Reserved

–

Reserved

0x0204 606C- 0x0204 611F

0x0204 6120

–

Reserved

PTCMD

Power Domain Transition Command Register

Reserved

0x0204 6124- 0x0204 6127

0x0204 6128

–

PTSTAT

Power Domain Transition Status Register

Reserved

0x0204 612C- 0x0204 61FF

0x0204 6200

–

PDSTAT0

Power Domain Status 0 Register (Always On)

Reserved

0x0204 6204- 0x0204 62FF

0x0204 6300

–

PDCTL0

–

Power Domain Control 0 Register (Always On)

Reserved

0x0204 6304- 0x1C4 150F

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Table 6-3. PSC Register Memory Map (continued)

HEX ADDRESS RANGE

0x0204 6510

0x0204 6514

0x0204 6518- 0x0204 65FF

0x0204 6600- 0x0204 67FF

0x0204 6800

0x0204 6804

0x0204 6808

0x0204 680C

0x0204 6810

0x0204 6814

0x0204 6818

0x0204 681C

0x0204 6820

0x0204 6824

0x0204 6828

0x0204 682C

0x0204 6830

0x0204 6834

0x0204 6838

0x0204 683C

0x0204 6840

0x0204 6844

0x0204 6848

0x0204 684C

0x0204 6850

0x0204 6854

0x0204 6858

0x0204 685C

0x0204 6860

0x0204 6864

0x0204 6868

0x0204 686C

0x0204 6870

0x0204 6874

0x0204 6878

0x0204 687C

0x0204 6880

0x0204 6884

0x0204 688C

0x0204 688C-0x0204 69FF

0x0204 6A00

0x0204 6A04

0x0204 6A08

0x0204 6A0C

0x0204 6A10

0x0204 6A14

0x0204 6A18

REGISTER ACRONYM

DESCRIPTION

–

Reserved

–

Reserved

–

Reserved

–

Reserved

MDSTAT0

Module Status 0 Register (EDMACC)

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

MDSTAT7

MDSTAT8

MDSTAT9

MDSTAT10

MDSTAT11

MDSTAT12

–

Module Status 7 Register (DDR2)

Module Status 8 Register (HPI)

Module Status 9 Register (VLYNQ)

Module Status 10 Register (GPIO)

Module Status 11 Register (TIMER 0)

Module Status 12 Register (TIMER 1)

Reserved

–

Reserved

–

Reserved

–

Reserved

MDSTAT17

MDSTAT18

MDSTAT19

MDSTAT20

MDSTAT21

MDSTAT22

MDSTAT23

MDSTAT24

MDSTAT25

MDSTAT26

MDSTAT27

MDSTAT28

MDSTAT29

MDSTAT30

MDSTAT31

–

Module Status 17 Register (SPI)

Module Status 18 Register (I2C)

Module Status 19 Register (PCI)

Module Status 20 Register (Video Port 0)

Module Status 21 Register (Video Port 1)

Module Status 22 Register (Video Port 2)

Module Status 23 Register (Video Port 3)

Module Status 24 Register (Video Port 4)

Module Status 25 Register (EMIFA)

Module Status 26 Register (TIMER 2)

Module Status 27 Register (TIMER 3)

Module Status 28 Register (VIC)

Module Status 29 Register (McASP)

Module Status 30 Register (UART)

Module Status 31 Register (VICP)

Reserved

MDSTAT33

MDSTAT34

–

Module Status 33 Register (C64x+ CPU)

Module Status 34 Register (Ethernet Subsystem)

Reserved

MDCTL0

–

Module Control 0 Register (EDMACC)

Reserved

–

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Table 6-3. PSC Register Memory Map (continued)

HEX ADDRESS RANGE

0x0204 6A1C

0x0204 6A20

0x0204 6A24

0x0204 6A28

0x0204 6A2C

0x0204 6A30

0x0204 6A34

0x0204 6A38

0x0204 6A3C

0x0204 6A40

0x0204 6A44

0x0204 6A48

0x0204 6A4C

0x0204 6A50

0x0204 6A54

0x0204 6A58

0x0204 6A5C

0x0204 6A60

0x0204 6A64

0x0204 6A68

0x0204 6A6C

0x0204 6A70

0x0204 6A74

0x0204 6A78

0x0204 6A7C

0x0204 6A80

0x0204 6A84

0x0204 6A8C

0x0204 6A90- 0x0204 6FFF

REGISTER ACRONYM

MDCTL7

MDCTL8

MDCTL9

MDCTL10

MDCTL11

MDCTL12

–

DESCRIPTION

Module Control 7 Register (DDR2)

Module Control 8 Register (HPI)

Module Control 9 Register (VLYNQ)

Module Control 10 Register (GPIO)

Module Control 11 Register (TIMER 0)

Module Control 12 Register (TIMER 1)

Reserved

–

Reserved

–

Reserved

–

Reserved

MDCTL17

MDCTL18

MDCTL19

MDCTL20

MDCTL21

MDCTL22

MDCTL23

MDCTL24

MDCTL25

MDCTL26

MDCTL27

MDCTL28

MDCTL29

MDCTL30

MDCTL31

–

Module Control 17 Register (SPI)

Module Control 18 Register (I2C)

Module Control 19 Register (PCI)

Module Control 20 Register (Video Port 0)

Module Control 21 Register (Video Port 1)

Module Control 22 Register (Video Port 2)

Module Control 23 Register (Video Port 3)

Module Control 24 Register (Video Port 4)

Module Control 25 Register (EMIFA)

Module Control 26 Register (TIMER 2)

Module Control 27 Register (TIMER 3)

Module Control 28 Register (VIC)

Module Control 29 Register (McASP)

Module Control 30 Register (UART)

Module Control 31 Register (VICP)

Reserved

MDCTL33

MDCTL34

–

Module Control 33 Register (C64x+ CPU)

Module Control 34 Register (Ethernet Subsystem)

Reserved

6.3.5 DM647/DM648 Power and Clock Domains

The DM647/DM648 includes two power domains: the System Domain and the Ethernet Subsystem

Domain. Both of these power domains are always on when the chip is on. Both of these domains are

powered by the C_VDDpins of the DM647/DM648 device.

The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the

system peripherals such as the multichannel audio serial ports (McASPs) and the external memory

interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory

controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from

REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the

secondary PLL controller (PLL2 controller) uses the device input clock CLKIN2

Table 6-4 provides a listing of the DM647/DM648 clock domains.

Table 6-4. DM647/DM648 Power and Clock Domains

POWER DOMAIN

System Domain

CLOCK DOMAIN

CLKDIV1

PERIPHERAL/MODULE/USAGE

C64x+ CPU

CLKDIV3

EDMA/SCR

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Table 6-4. DM647/DM648 Power and Clock Domains (continued)

POWER DOMAIN

System Domain

Ethernet Subsystem Domain

CLOCK DOMAIN

CLKDIV3

CLKDIV6

CLKDIV4 0

CLKDIV4 1

CLKDIV4 2

CLKDIV2

SerDes TXBCLK

PERIPHERAL/MODULE/USAGE

TSIP0

TSIP1

DDR Subsystem

Video Port 0

Video Port 1

Video Port 2

Video Port 3

Video Port 4

EMIFA

HPI

PCI

VLYNQ

UART

I2C

TIMER 0

TIMER 1

TIMER 2

TIMER 3

SPI

McASP

VIC

GPIO

PLL Controller 1

PLL Controller 2

Config SCR

Internal EMIFA Clock

Emulation and Trace

VICP cop_clk/2

VICP cop_clk

Ethernet Subsystem

The DM647/DM648 architecture is divided into the power and clock domains shown in Table 6-5, which

further shows the clock domains and their ratios.

Table 6-5. DM647/DM648 Clock Domain Assignment

SUBSYSTEM

CLOCK DOMAIN

DOMAIN CLOCK SOURCE

FIXED RATIO VS SYSREFCLK

FREQUENCY

DSP Subsystem

CLKDIV1

CLKDIV3

CLKDIV4 1

CLKDIV6

CLKDIV4 0

CLKDIV4 2

CLKDIV2

PLLC1.REFSYSCLK

PLLC1.SYSCLK1

PLLC1.SYSCLK2

PLLC1.SYSCLK3

PLLC1.SYSCLK4

PLLC1.SYSCLK5

PLLC1.SYSCLK6

-

Peripherals (CLKDIV3 Domain)

Emulation/Trace

1:3

1:4

1:6

1:4

1:2

Peripherals (CLKDIV6 Domain)

Internal EMIFA Clock

VICP cop_clk/2

VICP cop_clk

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6.3.6 Preserving Boundary-Scan Functionality on DDR2 Memory Pins

Similarly, when the DDR2 Memory Controller is not used, the V_REFSSTL, RSV19, and RSV20 pins can be

connected directly to ground (V_SS) to save power. However, this will prevent boundary-scan from

functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2

Memory Controller pins, V_REFSSTL, RSV11, and RSV12 should be connected as follows:

•

V_REFSSTL- connect to a voltage of DVDD18/2. The DVDD18/2 voltage can be generated directly from

the D_VDD18supply using two 1-kΩ resistors to form a resistor divider circuit.

•

RSV19 - connect this pin to ground (V_SS) via a 200-Ω resistor.

RSV20 - connect this pin to the 1.8-V I/O supply (D_VDD18) via a 200-Ω resistor

6.4 PLL1 and PLL1 Controller

The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as

well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the

external memory interface (EMIFA).

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DM647/DM648

+1.8 V

PLLV1

C2

560 pF 0.1

C1

EMI Filter

F

PLL1 Controller

PLL1

PLLEN (PLLCTL.[0])

SYSREFCLK

PLLM

DIVIDER PREDIV

/1, /2, /3

CLKIN1

(C64x+ MegaModule)

x1, x15,

x20, x25,

x30, x32

DIVIDER D1

/3

1

0

ENA

SYSCLK1

PREDEN (PREDIV.[15])

DIVIDER D2

/1, /2,

..., /8

ENA

SYSCLK2

D2EN (PLLDIV2.[15])

(Emulation and Trace)

DIVIDER D3

/6

SYSCLK3

DIVIDER D4

/2, /4,

..., /16

ENA

SYSCLK4

(Internal EMIF Clock Input)

D4EN (PLLDIV4.[15])

DIVIDER D5

/4

SYSCLK5

VICP cop_clk/2

DIVIDER D6

/2

SYSCLK6

VICP cop_clk

AECLKIN (External EMIF Clock Input)

VCLK

/1, /2,

..., /8

CLKDIV

(CTRL.[18:16])

0

1

AECLKINSEL

(AEA[17] pin)

1

0

CLKDIR

(CTRL.[15])

EMIFA

(EMIF Input Clock)

VLYNQ

AECLKOUT

SYSCLK4

Figure 6-5. PLL Input Clock

As shown in Figure 6-5, the PLL1 controller features a software-programmable PLL multiplier controller

(PLLM) and five dividers (PREDIV, D1, D2, D3, D4, D5, D6). The PLL1 controller uses the device input

clock CLKIN1 to generate a system reference clock (SYSREFCLK) and five system clocks (SYSCLK1,

SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5 and SYSCLK6). PLL1 power is supplied externally via the

PLL1 power-supply pin (PLLV1). An external EMI filter circuit must be added to PLLV1, as shown in

Figure 8-11. The 1.8-V supply of the EMI filter must be from the same 1.8-V power plane supplying the I/O

power-supply pin, D_VDD18. TI requires EMI filter manufacturer Murata, part number NFM18CC222R1C3.

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All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP

device as possible. For the best performance, TI recommends that all the PLL external components be on

a single side of the board without jumpers, switches, or components other than the ones shown. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C1, C2, and the EMI Filter).The minimum CLKIN1 rise and fall times should also be observed. For the

input clock timing requirements, see Section 6.4.4.

6.4.1 PLL1 Controller Device-Specific Information

As shown in Figure 6-5, the PLL1 controller generates several internal clocks including the system

reference clock (SYSREFCLK), and the system clocks (SYSCLK1/2/3/4/5/6). The high-frequency clock

signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves

as a reference clock for the rest of the DSP system. Dividers D1, D2, D3, D4, D5 and D6 divide the

high-frequency clock SYSREFCLK to generate SYSCLK1, SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5

and SYSCLK6, respectively.

The system clocks are used to clock different portions of the DSP as follows:

•

SYSCLK1 is used for the following modules 3PDMA, the SCR and the bridges, DDR Subsystem

internal logic, Video Port 0, Video Port 1, Video Port 2, Video Port 3, Video Port 4, EMIFA internal

logic.

•

SYSCLK2 is used for Emulation and Trace

SYSCLK3 is used for most of the peripherals. These modules are clocked from SYSCLK3: HPI, PCI,

VLYNQ, UART, I2C, TIMER 0, TIMER 1, TIMER 2, TIMER 3, SPI, McASP, VIC, GPIO, PLL Controller

1, PLL Controller 2, Config SCR

•

SYSCLK4 is used as the EMIFA AECLKOUT

SYSCLK5 is used as the VICP internal clock

SYSCLK6 is used as the VICP internal clock

The PLL multiplier controller (PLLM) must be programmed after reset. There is no hardware CLKMODE

selection on the DM647/DM648 device. Since the divider ratio bits for dividers D1, D3, D5, and D6 are

fixed, the frequency of SYSCLK1, SYCLK3, SYSCLK5 and SYSCLK6 is tied to the frequency of

SYSREFCLK. However, the frequency of SYSCLK2 and SYSCLK4 depends on the configuration of

dividers D2 and D4. For example, with PLLM in the PLL1 multiply control register set to 10011b (x20

mode) and a 35 MHz CLKIN1 input, the PLL output PLLOUT is set to 700 MHz and SYSCLK1 and

SYSCLK3 run at 233 MHz and 117 MHz, respectively. Divider D4 can be programmed through the

PLLDIV4 register to divide SYSREFCLK by 10 such that SYSCLK4 runs at 70 MHz.

Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, SYSCLK4, and

SYSCLK5. The PLL1 Controller must not be configured to exceed any of these constraints (certain

combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). For

the PLL clocks input and output frequency ranges, see Table 6-6.

Table 6-6. PLL1 Clock Frequency Ranges

CLOCK SIGNAL

CLKIN1

PLLREF (PLLEN = 1)⁽¹⁾

MIN

MAX

66.6

UNIT

MHz

33.3

400

66.6

900⁽²⁾

(1)

PLLOUT

(1) Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register)

(2) Only for DM648 device

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6.4.2 PLL1 Controller Operating Modes

The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is

determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is

generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In

bypass mode, CLKIN1 is fed directly to SYSREFCLK.

All hosts (HPI, PCI, etc.) must hold off accesses to the DSP while the frequency of its internal clocks is

changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration

has completed.

6.4.3 PLL1 Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to

become stable after device power-up. The PLL should not be operated until this stabilization time has

expired.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in

order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the

PLL1 reset time value, see Table 6-7.

Table 6-7. PLL1 Stabilization, Lock, and Reset Times

MIN

TYP

MAX

UNIT

µs

PLL stabilization time

PLL lock time

150

2000*C⁽¹⁾

µs

PLL reset time

128*C⁽¹⁾

µs

(1) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

6.4.4 PLL1 Controller Input and Output Clock Electrical Data/Timing

Table 6-8. Timing Requirements for CLKIN1 ^(1)(2)(3)(see Figure 6-6)

-720

-900

PLL MODES

x1 (Bypass), x15, x20,

x25, x30, x32

NO.

UNIT

MIN

15

MAX

1

2

3

4

5

t_c(CLKIN1)

t_w(CLKIN1H)

t_w(CLKIN1L)

t_t(CLKIN1)

Cycle time, CLKIN1

30.3

ns

ps

Pulse duration, CLKIN1 high

Pulse duration, CLKIN1 low

Transition time, CLKIN1

0.4C

1.2

t_J(CLKIN1)

Period jitter, (peak-to-peak), CLKIN1

100

(1) The reference points for the rise and fall transitions are measured at 3.3-V V_ILMAX and V_IHMIN.

(2) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.

(3) The PLL1 multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32) further limit the MIN and MAX values for tc(CLKIN1). For more

detailed information on these limitations, see Section 6.3.5, DM647/DM648 Power and Clock Domains.

1

5

4

2

CLKIN

3

4

Figure 6-6. CLKIN1 Timing

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6.4.5 PLL1 Controller Register Description(s)

A summary of the PLL1 controller registers is shown in Table 6-9.

Table 6-9. PLL1 and Reset Controller Registers Memory Map

HEX ADDRESS RANGE

0x020E 0000

0x020E 00E4

0x020E 0100

0x020E 0110

0x020E 0114

0x020E 011C

0x020E 0138

0x020E 013C

0x020E 0140

0x020E 0144

0x020E 0150

REGISTER NAME

PID

DESCRIPTION

Peripheral Identification and Revision Information Register

Reset Type Register

RSTYPE

PLLCTL

PLLM

PLL Controller 1 Operations Control Register

PLL Controller 1 Multiplier Control Register

PLL Pre-Divider Control Register

PREDIV

PLLDIV2

PLLCMD

PLLSTAT

ALNCTL

DCHANGE

SYSTAT

PLL Controller 1 Control-Divider 2 Register (SYSCLK2)

PLL Controller 1 Command Register

PLL Controller 1 Status Register (Shows PLLC1 Status)

PLL Controller Clock Align Control Register

PLLDIV Ratio Change Status Register

PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off

Status)

0x020E 0160

PLLDIV4

PLL Controller 1 Control-Divider 4 Register (SYSCLK4)

6.5 PLL2 and PLL2 Controller

The secondary PLL controller generates interface clocks for the DDR2 memory controller.

As shown in Figure 6-7, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is fixed

to a x20 multiplier rate. PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external

PLL filter circuit must be added to PLLV2 as shown in Figure 6-7. The 1.8-V supply for the EMI filter must

be from the same 1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter

manufacturer Murata, part number NFM18CC222R1C3.

DM647/DM648

+1.8 V

PLLV2

C161 C162

EMI Filter

SYSCLK1 (From PLL Controller 1)

560 pF 0.1

F

CLKIN2

PLLREF

PLLOUT

DDR2 Memory Controller

PLL2

PLLM

x20

Figure 6-7. PLL Controller

All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+

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DSP device as possible. For the best performance, TI requires that all the PLL external components be on

a single side of the board without jumpers, switches, or components other than the ones shown. For

reduced PLL jitter, maximize the spacing between switching signals and the PLL external components

(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For

the input clock timing requirements, see Section 6.5.3, PLL2 Controller Input Clock Electrical Data/Timing.

6.5.1 PLL2 Controller Device-Specific Information

As shown in Figure 6-7, the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This

clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that,

internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1

controller.

Note that there is a minimum and maximum operating frequency for PLLREF, and PLLOUT. The clock

generator must not be configured to exceed any of these constraints. For the PLL clocks input and output

frequency ranges, see Table 6-10.

Table 6-10. PLL2 Clock Frequency Ranges

CLOCK SIGNAL

PLLREF (CLKIN2 )

PLLOUT (DDR2 clock)

REQUIRED FREQUENCY

UNIT

MHz

26.6

533

6.5.2 PLL2 Controller Operating Modes

Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates

in PLL mode. PLL2 isunlocked only during the power-up sequence (see Section 6.7) and is locked by the

time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

6.5.3 PLL2 Controller Input Clock Electrical Data/Timing

Table 6-11. Timing Requirements for CLKIN2⁽¹⁾⁽²⁾(see Figure 6-8)

-720

-900

NO.

UNIT

PLL MODES x20

MIN

37.5

0.4C

MAX

1

2

3

4

5

t_c(CLKIN2)

t_w(CLKIN2H)

t_w(CLKIN2L)

t_t(CLKIN2)

Cycle time, CLKIN2

37.5 ns

ns

Pulse duration, CLKIN2 high

Pulse duration, CLKIN2 low

Transition time, CLKIN2

ns

1.2 ns

100 ps

t_J(CLKIN2)

Period jitter, (peak-to-peak) CLKIN2

(1) The reference points for the rise and fall transitions are measured at 3.3-V V_ILMAX and V_IHMIN.

(2) C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.

1

5

4

2

CLKIN

3

4

Figure 6-8. CLKIN2 Timing

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6.5.4 PLL1 Controller Register Description(s)

A summary of the PLL2 controller registers is shown in Table 6-12.

Table 6-12. PLL2 and Reset Controller Registers Memory Map

HEX ADDRESS RANGE

0x0212 0000

REGISTER NAME

PID

DESCRIPTION

Peripheral Identification and Revision Information Register

PLL Controller 1 Operations Control Register

PLL Controller 1 Multiplier Control Register

PLL Controller 1 Command Register

0x0212 0100

PLLCTL

0x0212 0110

PLLM

0x0212 0138

PLLCMD

PLLSTAT

0x0212 013C

PLL Controller 1 Status Register (Shows PLLC1 Status)

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6.6 Enhanced Direct Memory Access (EDMA3) Controller

The EDMA controller handles all data transfers between memories and the device slave peripherals on

the DM648 device. These data transfers include cache servicing, non-cacheable memory accesses,

user-programmed data transfers, and host accesses. These are summarized as follows:

•

Transfer to/from on-chip memories

–

DSP L1D memory

DSP L2 memory

Transfer to/from external storage

–

DDR2 SDRAM

Synchronous/Asynchronous EMIF (EMIFA)

Transfer to/from peripherals/hosts

–

VLYNQ

HPI

McASP

UART

Video Port 0/1/2/3/4

Timer 0/1/2/3

SPI

I2C

6.6.1 EDMA3 Channel Synchronization Events

The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.

Table 6-13 lists the source of EDMA synchronization events associated with each of the programmable

EDMA channels. For the DM648 device, the association of an event to a channel is fixed; each of the

EDMA channels has one specific event associated with it. These specific events are captured in the

EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers

(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,

captured, processed, linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced

DMA (EDMA) Controller User's Guide (literature number SPRUEL2).

Table 6-13. EDMA Channel Synchronization Events

TPCC

CHANN

EL

DEFAULT BINARY

EVENT#

DEFAULT EVENT

TPCC

CHANNEL

DEFAULT BINARY

EVENT #

DEFAULT EVENT

0

1

0

1

000 0000

000 0001

000 0010

000 0011

000 0100

000 0101

000 0110

000 0111

000 1000

000 1001

000 1010

000 1011

000 1100

000 1101

000 1110

HPI/PCI : DSPINT

TIMER0 : TINT0L

TIMER0 : TINT0H

TIMER2 : TINT2L

TIMER2 : TINT2H

TIMER3 : TINT3L

TIMER3 : TINT3H

IMCOP: IMXINT

IMCOP: VLCDINT

IMCOP: DSQINT

McASP: AXEVTE

McASP: AXEVTO

McASP: AXEVT

McASP: AREVTE

McASP: AREVTO

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

010 0000

010 0001

010 0010

010 0011

010 0100

010 0101

010 0110

010 0111

010 1000

010 1001

010 1010

010 1011

010 1100

010 1101

010 1110

VP2EVTYA

VP2EVTUA

VP2EVTVA

VP2EVTYB

VP2EVTUB

VP2EVTVB

VP3EVTYA

VP3EVTUA

VP3EVTVA

VP3EVTYB

VP3EVTUB

VP3EVTVB

ICREVT

2

3

4

5

6

7

8

9

10

11

12

13

14

10

11

12

13

14

ICXEVT

SPI: SPIXEVT

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Table 6-13. EDMA Channel Synchronization Events (continued)

TPCC

CHANN

EL

DEFAULT BINARY

EVENT#

DEFAULT EVENT

TPCC

CHANNEL

DEFAULT BINARY

EVENT #

DEFAULT EVENT

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

000 1111

001 0000

001 0001

001 0010

001 0011

001 0100

001 0101

001 0110

001 0111

001 1000

001 1001

001 1010

001 1011

001 1100

001 1101

001 1110

001 1111

McASP: AREVT

TIMER1 : TINT1L

TIMER1 : TINT1H

UART: URXEVT

UART: UTXEVT

VP0EVTYA

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

010 1111

011 0000

011 0001

011 0010

011 0011

011 0100

011 0101

011 0110

011 0111

011 1000

011 1001

011 1010

011 1011

011 1100

011 1101

011 1110

011 1111

SPI: SPIREVT

VP4EVTYA

VP4EVTUA

VP4EVTVA

VP4EVTYB

VP4EVTUB

VP0EVTUA

VP4EVTVB

VP0EVTVA

GPIO : GPINT6

GPIO : GPINT7

GPIO : GPINT8

GPIO : GPINT9

GPIO : GPINT10

GPIO : GPINT11

GPIO : GPINT12

GPIO : GPINT13

GPIO : GPINT14

GPIO : GPINT15

VP0EVTYB

VP0EVTUB

VP0EVTVB

VP1EVTYA

VP1EVTUA

VP1EVTVA

VP1EVTYB

VP1EVTUB

VP1EVTVB

6.6.2 EDMA Peripheral Register Description(s)

Table 6-14 lists the EDMA registers, their corresponding acronyms, and DM648 device memory locations.

Table 6-14. DM647/DM648 EDMA Channel Controller Registers

HEX ADDRESS

0x02A0 0000

0x02A0 0004

0x02A0 0008 - 0x02A0 00FC

0x02A0 0100

0x02A0 0104

0x02A0 0108

0x02A0 010C

0x02A0 0110

0x02A0 0114

0x02A0 0118

0x02A0 011C

0x02A0 0120

0x02A0 0124

0x02A0 0128

0x02A0 012C

0x02A0 0130

0x02A0 0134

0x02A0 0138

0x02A0 013C

0x02A0 0140

0x02A0 0144

0x02A0 0148

ACRONYM

PID

REGISTER NAME

Peripheral ID Register

CCCFG

EDMA3CC Configuration Register

Reserved

DCHMAP0

DCHMAP1

DCHMAP2

DCHMAP3

DCHMAP4

DCHMAP5

DCHMAP6

DCHMAP7

DCHMAP8

DCHMAP9

DCHMAP10

DCHMAP11

DCHMAP12

DCHMAP13

DCHMAP14

DCHMAP15

DCHMAP16

DCHMAP17

DCHMAP18

DMA Channel 0 Mapping Register

DMA Channel 1 Mapping Register

DMA Channel 2 Mapping Register

DMA Channel 3 Mapping Register

DMA Channel 4 Mapping Register

DMA Channel 5 Mapping Register

DMA Channel 6 Mapping Register

DMA Channel 7 Mapping Register

DMA Channel 8 Mapping Register

DMA Channel 9 Mapping Register

DMA Channel 10 Mapping Register

DMA Channel 11 Mapping Register

DMA Channel 12 Mapping Register

DMA Channel 13 Mapping Register

DMA Channel 14 Mapping Register

DMA Channel 15 Mapping Register

DMA Channel 16 Mapping Register

DMA Channel 17 Mapping Register

DMA Channel 18 Mapping Register

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Table 6-14. DM647/DM648 EDMA Channel Controller Registers (continued)

HEX ADDRESS

0x02A0 014C

0x02A0 0150

0x02A0 0154

0x02A0 0158

0x02A0 015C

0x02A0 0160

0x02A0 0164

0x02A0 0168

0x02A0 016C

0x02A0 0170

0x02A0 0174

0x02A0 0178

0x02A0 017C

0x02A0 0180

0x02A0 0184

0x02A0 0188

0x02A0 018C

0x02A0 0190

0x02A0 0194

0x02A0 0198

0x02A0 019C

0x02A0 01A0

0x02A0 01A4

0x02A0 01A8

0x02A0 01AC

0x02A0 01B0

0x02A0 01B4

0x02A0 01B8

0x02A0 01BC

0x02A0 01C0

0x02A0 01C4

0x02A0 01C8

0x02A0 01CC

0x02A0 01D0

0x02A0 01D4

0x02A0 01D8

0x02A0 01DC

0x02A0 01E0

0x02A0 01E4

0x02A0 01E8

0x02A0 01EC

0x02A0 01F0

0x02A0 01F4

0x02A0 01F8

0x02A0 01FC

0x02A0 0200

0x02A0 0204

ACRONYM

DCHMAP19

DCHMAP20

DCHMAP21

DCHMAP22

DCHMAP23

DCHMAP24

DCHMAP25

DCHMAP26

DCHMAP27

DCHMAP28

DCHMAP29

DCHMAP30

DCHMAP31

DCHMAP32

DCHMAP33

DCHMAP34

DCHMAP35

DCHMAP36

DCHMAP37

DCHMAP38

DCHMAP39

DCHMAP40

DCHMAP41

DCHMAP42

DCHMAP43

DCHMAP44

DCHMAP45

DCHMAP46

DCHMAP47

DCHMAP48

DCHMAP49

DCHMAP50

DCHMAP51

DCHMAP52

DCHMAP53

DCHMAP54

DCHMAP55

DCHMAP56

DCHMAP57

DCHMAP58

DCHMAP59

DCHMAP60

DCHMAP61

DCHMAP62

DCHMAP63

QCHMAP0

QCHMAP1

REGISTER NAME

DMA Channel 19 Mapping Register

DMA Channel 20 Mapping Register

DMA Channel 21 Mapping Register

DMA Channel 22 Mapping Register

DMA Channel 23 Mapping Register

DMA Channel 24 Mapping Register

DMA Channel 25 Mapping Register

DMA Channel 26 Mapping Register

DMA Channel 27 Mapping Register

DMA Channel 28 Mapping Register

DMA Channel 29 Mapping Register

DMA Channel 30 Mapping Register

DMA Channel 31 Mapping Register

DMA Channel 32 Mapping Register

DMA Channel 33 Mapping Register

DMA Channel 34 Mapping Register

DMA Channel 35 Mapping Register

DMA Channel 36 Mapping Register

DMA Channel 37 Mapping Register

DMA Channel 38 Mapping Register

DMA Channel 39 Mapping Register

DMA Channel 40 Mapping Register

DMA Channel 41 Mapping Register

DMA Channel 42 Mapping Register

DMA Channel 43 Mapping Register

DMA Channel 44 Mapping Register

DMA Channel 45 Mapping Register

DMA Channel 46 Mapping Register

DMA Channel 47 Mapping Register

DMA Channel 48 Mapping Register

DMA Channel 49 Mapping Register

DMA Channel 50 Mapping Register

DMA Channel 51 Mapping Register

DMA Channel 52 Mapping Register

DMA Channel 53 Mapping Register

DMA Channel 54 Mapping Register

DMA Channel 55 Mapping Register

DMA Channel 56 Mapping Register

DMA Channel 57 Mapping Register

DMA Channel 58 Mapping Register

DMA Channel 59 Mapping Register

DMA Channel 60 Mapping Register

DMA Channel 61 Mapping Register

DMA Channel 62 Mapping Register

DMA Channel 63 Mapping Register

QDMA Channel 0 Mapping to PaRAM Register

QDMA Channel 1 Mapping to PaRAM Register

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Table 6-14. DM647/DM648 EDMA Channel Controller Registers (continued)

HEX ADDRESS

ACRONYM

QCHMAP2

QCHMAP3

QCHMAP4

QCHMAP5

QCHMAP6

QCHMAP7

-

REGISTER NAME

0x02A0 0208

0x02A0 020C

QDMA Channel 2 Mapping to PaRAM Register

QDMA Channel 3 Mapping to PaRAM Register

QDMA Channel 4 Mapping to PaRAM Register

QDMA Channel 5 Mapping to PaRAM Register

QDMA Channel 6 Mapping to PaRAM Register

QDMA Channel 7 Mapping to PaRAM Register

Reserved

0x02A0 0210

0x02A0 0214

0x02A0 0218

0x02A0 021C

0x02A0 0220 - 0x02A0 021C

0x02A0 0220 - 0x02A0 023C

0x02A0 0240

-

Reserved

DMAQNUM0

DMAQNUM1

DMAQNUM2

DMAQNUM3

-

DMA Queue Number Register 0 (Channels 00 to 07)

DMA Queue Number Register 1 (Channels 08 to 15)

DMA Queue Number Register 2 (Channels 16 to 23)

DMA Queue Number Register 3 (Channels 24 to 31)

Reserved

0x02A0 0244

0x02A0 0248

0x02A0 024C

0x02A0 0250 - 0x02A0 025C

0x02A0 0260

QDMAQNUM

–

CC QDMA Queue Number

0x02A0 0264 - 0x02A0 0280

0x02A0 0284

Reserved

QUEPRI

–

Queue Priority Register

0x02A0 0288 - 0x02A0 02FC

0x02A0 0300

Reserved

EMR

Event Missed Register

0x02A0 0304

EMRH

Event Missed Register High

0x02A0 0308

EMCR

Event Missed Clear Register

0x02A0 030C

EMCRH

QEMR

Event Missed Clear Register High

0x02A0 0310

QDMA Event Missed Register

0x02A0 0314

QEMCR

CCERR

CCERRCLR

EEVAL

QDMA Event Missed Clear Register

0x02A0 0318

EDMA3CC Error Register

0x02A0 031C

EDMA3CC Error Clear Register

0x02A0 0320

Error Evaluate Register

0x02A0 0324 - 0x02A0 033C

0x02A0 0340

-

Reserved

DRAE0

DRAEH0

DRAE1

DRAEH1

DRAE2

DRAEH2

DRAE3

DRAEH3

DRAE4

DRAEH4

DRAE5

DRAEH5

DRAE6

DRAEH6

DRAE7

DRAEH7

QRAE0

QRAE1

QRAE2

QRAE3

DMA Region Access Enable Register for Region 0

DMA Region Access Enable Register High for Region 0

DMA Region Access Enable Register for Region 1

DMA Region Access Enable Register High for Region 1

DMA Region Access Enable Register for Region 2

DMA Region Access Enable Register High for Region 2

DMA Region Access Enable Register for Region 3

DMA Region Access Enable Register High for Region 3

DMA Region Access Enable Register for Region 4

DMA Region Access Enable Register High for Region 4

DMA Region Access Enable Register for Region 5

DMA Region Access Enable Register High for Region 5

DMA Region Access Enable Register for Region 6

DMA Region Access Enable Register High for Region 6

DMA Region Access Enable Register for Region 7

DMA Region Access Enable Register High for Region 7

QDMA Region Access Enable Register for Region 0

QDMA Region Access Enable Register for Region 1

QDMA Region Access Enable Register for Region 2

QDMA Region Access Enable Register for Region 3

0x02A0 0344

0x02A0 0348

0x02A0 034C

0x02A0 0350

0x02A0 0354

0x02A0 0358

0x02A0 035C

0x02A0 0360

0x02A0 0364

0x02A0 0368

0x02A0 036C

0x02A0 0370

0x02A0 0374

0x02A0 0378

0x02A0 037C

0x02A0 0380

0x02A0 0384

0x02A0 0388

0x02A0 038C

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Table 6-14. DM647/DM648 EDMA Channel Controller Registers (continued)

HEX ADDRESS

0x02A0 0390 - 0x02A0 039C

0x02A0 0400

0x02A0 0404

0x02A0 0408

0x02A0 040C

0x02A0 0410

0x02A0 0414

0x02A0 0418

0x02A0 041C

0x02A0 0420

0x02A0 0424

0x02A0 0428

0x02A0 042C

0x02A0 0430

0x02A0 0434

0x02A0 0438

0x02A0 043C

0x02A0 0440

0x02A0 0444

0x02A0 0448

0x02A0 044C

0x02A0 0450

0x02A0 0454

0x02A0 0458

0x02A0 045C

0x02A0 0460

0x02A0 0464

0x02A0 0468

0x02A0 046C

0x02A0 0470

0x02A0 0474

0x02A0 0478

0x02A0 047C

0x02A0 0480

0x02A0 0484

0x02A0 0488

0x02A0 048C

0x02A0 0490

0x02A0 0494

0x02A0 0498

0x02A0 049C

0x02A0 04A0

0x02A0 04A4

0x02A0 04A8

0x02A0 04AC

0x02A0 04B0

0x02A0 04B4

ACRONYM

–

REGISTER NAME

Reserved

Q0E0

Q0E1

Q0E2

Q0E3

Q0E4

Q0E5

Q0E6

Q0E7

Q0E8

Q0E9

Q0E10

Q0E11

Q0E12

Q0E13

Q0E14

Q0E15

Q1E0

Q1E1

Q1E2

Q1E3

Q1E4

Q1E5

Q1E6

Q1E7

Q1E8

Q1E9

Q1E10

Q1E11

Q1E12

Q1E13

Q1E14

Q1E15

Q2E0

Q2E1

Q2E2

Q2E3

Q2E4

Q2E5

Q2E6

Q2E7

Q2E8

Q2E9

Q2E10

Q2E11

Q2E12

Q2E13

Event Queue 0 Entry Register 0

Event Queue 0 Entry Register 1

Event Queue 0 Entry Register 2

Event Queue 0 Entry Register 3

Event Queue 0 Entry Register 4

Event Queue 0 Entry Register 5

Event Queue 0 Entry Register 6

Event Queue 0 Entry Register 7

Event Queue 0 Entry Register 8

Event Queue 0 Entry Register 9

Event Queue 0 Entry Register 10

Event Queue 0 Entry Register 11

Event Queue 0 Entry Register 12

Event Queue 0 Entry Register 13

Event Queue 0 Entry Register 14

Event Queue 0 Entry Register 15

Event Queue 1 Entry Register 0

Event Queue 1 Entry Register 1

Event Queue 1 Entry Register 2

Event Queue 1 Entry Register 3

Event Queue 1 Entry Register 4

Event Queue 1 Entry Register 5

Event Queue 1 Entry Register 6

Event Queue 1 Entry Register 7

Event Queue 1 Entry Register 8

Event Queue 1 Entry Register 9

Event Queue 1 Entry Register 10

Event Queue 1 Entry Register 11

Event Queue 1 Entry Register 12

Event Queue 1 Entry Register 13

Event Queue 1 Entry Register 14

Event Queue 1 Entry Register 15

Event Queue 2 Entry Register 0

Event Queue 2 Entry Register 1

Event Queue 2 Entry Register 2

Event Queue 2 Entry Register 3

Event Queue 2 Entry Register 4

Event Queue 2 Entry Register 5

Event Queue 2 Entry Register 6

Event Queue 2 Entry Register 7

Event Queue 2 Entry Register 8

Event Queue 2 Entry Register 9

Event Queue 2 Entry Register 10

Event Queue 2 Entry Register 11

Event Queue 2 Entry Register 12

Event Queue 2 Entry Register 13

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Table 6-14. DM647/DM648 EDMA Channel Controller Registers (continued)

HEX ADDRESS

ACRONYM

Q2E14

Q2E15

Q3E0

Q3E1

Q3E2

Q3E3

Q3E4

Q3E5

Q3E6

Q3E7

Q3E8

Q3E9

Q3E10

Q3E11

Q3E12

Q3E13

Q3E14

Q3E15

-

REGISTER NAME

Event Queue 2 Entry Register 14

0x02A0 04B8

0x02A0 04BC

Event Queue 2 Entry Register 15

Event Queue 3 Entry Register 0

Event Queue 3 Entry Register 1

Event Queue 3 Entry Register 2

Event Queue 3 Entry Register 3

Event Queue 3 Entry Register 4

Event Queue 3 Entry Register 5

Event Queue 3 Entry Register 6

Event Queue 3 Entry Register 7

Event Queue 3 Entry Register 8

Event Queue 3 Entry Register 9

Event Queue 3 Entry Register 10

Event Queue 3 Entry Register 11

Event Queue 3 Entry Register 12

Event Queue 3 Entry Register 13

Event Queue 3 Entry Register 14

Event Queue 3 Entry Register 15

Reserved

0x02A0 04C0

0x02A0 04C4

0x02A0 04C8

0x02A0 04CC

0x02A0 04D0

0x02A0 04D4

0x02A0 04D8

0x02A0 04DC

0x02A0 04E0

0x02A0 04E4

0x02A0 04E8

0x02A0 04EC

0x02A0 04F0

0x02A0 04F4

0x02A0 04F8

0x02A0 04FC

0x02A0 0500 - 0x02A0 051C

0x02A0 0520 - 0x02A0 05FC

0x02A0 0600

-

Reserved

QSTAT0

QSTAT1

QSTAT2

QSTAT3

-

Queue 0 Status Register

0x02A0 0604

Queue 1 Status Register

0x02A0 0608

Queue Status Register 2

0x02A0 060C

Queue Status Register 3

0x02A0 0610 - 0x02A0 061C

0x02A0 0620

Reserved

QWMTHRA

–

Queue Watermark Threshold A Register for Q[3:0]

Reserved

0x02A0 0624

0x02A0 0640

CCSTAT

-

EDMA3CC Status Register

Reserved

0x02A0 0644 - 0x02A0 06FC

0x02A0 0700 - 0x02A0 0FFC

0x02A0 1000

-

Reserved

ER

Event Register

0x02A0 1004

ERH

Event Register High

0x02A0 1008

ECR

Event Clear Register

0x02A0 100C

ECRH

ESR

Event Clear Register High

Event Set Register

0x02A0 1010

0x02A0 1014

ESRH

CER

Event Set Register High

Chained Event Register

Chained Event Register High

Event Enable Register

0x02A0 1018

0x02A0 101C

CERH

EER

0x02A0 1020

0x02A0 1024

EERH

EECR

EECRH

EESR

EESRH

SER

Event Enable Register High

Event Enable Clear Register

Event Enable Clear Register High

Event Enable Set Register

Event Enable Set Register High

Secondary Event Register

Secondary Event Register High

Secondary Event Clear Register

0x02A0 1028

0x02A0 102C

0x02A0 1030

0x02A0 1034

0x02A0 1038

0x02A0 103C

SERH

SECR

0x02A0 1040

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Table 6-14. DM647/DM648 EDMA Channel Controller Registers (continued)

HEX ADDRESS

0x02A0 1044

ACRONYM

REGISTER NAME

Secondary Event Clear Register High

SECRH

0x02A0 1048 - 0x02A0 104C

0x02A0 1050

Reserved

IER

Interrupt Enable Register

Interrupt Enable Register High

Interrupt Enable Clear Register

Interrupt Enable Clear Register High

Interrupt Enable Set Register

Interrupt Enable Set Register High

Interrupt Pending Register

Interrupt Pending Register High

Interrupt Clear Register

Interrupt Clear Register High

Interrupt Evaluate Register

Reserved

0x02A0 1054

IERH

0x02A0 1058

IECR

0x02A0 105C

IECRH

0x02A0 1060

IESR

0x02A0 1064

IESRH

0x02A0 1068

IPR

0x02A0 106C

IPRH

0x02A0 1070

ICR

0x02A0 1074

ICRH

0x02A0 1078

IEVAL

0x02A0 107C

-

0x02A0 1080

QER

QDMA Event Register

0x02A0 1084

QEER

QDMA Event Enable Register

QDMA Event Enable Clear Register

QDMA Event Enable Set Register

QDMA Secondary Event Register

QDMA Secondary Event Clear Register

Reserved

0x02A0 1088

QEECR

0x02A0 108C

QEESR

0x02A0 1090

QSER

0x02A0 1094

QSECR

0x02A0 1098 - 0x02A0 1FFF

0x02A0 2000- 0x02A0 2097

0x02A0 2098 - 0x02A0 21FF

0x02A0 2200 - 0x02A0 2297

0x02A0 2298 - 0x02A0 23FF

0x02A0 2400 - 0x02A0 2497

0x02A0 2498 - 0x02A0 25FF

0x02A0 2600 - 0x02A0 2697

0x02A0 2698 - 0x02A0 27FF

0x02A0 2800 - 0x02A0 2897

0x02A0 2898 - 0x02A0 29FF

0x02A0 2A00 - 0x02A0 2A97

0x02A0 2A98 - 0x02A0 2BFF

0x02A0 2C00 - 0x02A0 2C97

0x02A0 2C98 - 0x02A0 2DFF

0x02A0 2E00 - 0x02A0 2E97

0x02A0 2E98 - 0x02A0 2FFF

-

Shadow Region 0 Channel Registers

Reserved

Shadow Region 1 Channel Registers

Reserved

Shadow Region 2 Channel Registers

Reserved

Shadow Region 3 Channel Registers

Reserved

Shadow Region 4 Channel Registers

Reserved

Shadow Region 5 Channel Registers

Reserved

Shadow Region 6 Channel Registers

Reserved

Shadow Region 7 Channel Registers

Reserved

Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128

EDMA events. Each of the parameter register sets consist of eight 32-bit word entries. Table 6-16 shows

the parameter set entry registers with relative memory address locations within each of the parameter

sets.

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Table 6-15. EDMA Parameter Set RAM

HEX ADDRESS RANGE

DESCRIPTION

0x02A0 4000 - 0x02A0 401F

0x02A0 4020 - 0x02A0 403F

0x02A0 4040 - 0x02A0 405F

0x02A0 4060 - 0x02A0 407F

0x02A0 4080 - 0x02A0 409F

0x02A0 40A0 - 0x02A0 40BF

...

Parameters Set 0 (8 32-bit words)

Parameters Set 1 (8 32-bit words)

Parameters Set 2 (8 32-bit words)

Parameters Set 3 (8 32-bit words)

Parameters Set 4 (8 32-bit words)

Parameters Set 5 (8 32-bit words)

...

0x02A0 4FC0 - 0x02A0 4FDF

0x02A0 4FE0 - 0x02A0 4FFF

...

Parameters Set 126 (8 32-bit words)

Parameters Set 127 (8 32-bit words)

...

0x02A0 5FC0 - 0x02A0 5FDF

0x02A0 5FE0 - 0x02A0 5FFF

...

Parameters Set 254 (8 32-bit words)

Parameters Set 255 (8 32-bit words)

...

0x02A0 7FC0 - 0x02A0 7FDF

0x02A0 7FE0 - 0x02A0 7FFF

Parameters Set 510 (8 32-bit words)

Parameters Set 511 (8 32-bit words)

Table 6-16. Parameter Set Entries

HEX OFFSET ADDRESS

WITHIN THE PARAMETER SET

ACRONYM

PARAMETER ENTRY

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

0x0018

0x001C

OPT

SRC

Option

Source Address

A_B_CNT

DST

A Count, B Count

Destination Address

SRC_DST_BIDX

LINK_BCNTRLD

SRC_DST_CIDX

CCNT

Source B Index, Destination B Index

Link Address, B Count Reload

Source C Index, Destination C Index

C Count

Table 6-17. EDMA3 Transfer Controller 0 Registers

HEX ADDRESS RANGE

02A2 0000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A2 0004

TCCFG

-

02A2 0008 - 02A2 00FC

02A2 0100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A2 0104 - 02A2 011C

02A2 0120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A2 0124

Error Enable Register

Error Clear Register

02A2 0128

02A2 012C

Error Details Register

Error Interrupt Command Register

Reserved

02A2 0130

02A2 0134 - 02A2 013C

02A2 0140

RDRATE

-

Read Rate Register

02A2 0144 - 02A2 023C

02A2 0240

Reserved

SAOPT

SASRC

Source Active Options Register

Source Active Source Address Register

02A2 0244

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Table 6-17. EDMA3 Transfer Controller 0 Registers (continued)

HEX ADDRESS RANGE

02A2 0248

ACRONYM

SACNT

REGISTER NAME

Source Active Count Register

02A2 024C

SADST

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A2 0250

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

02A2 0254

02A2 0258

02A2 025C

02A2 0260

02A2 0264 - 02A2 027C

02A2 0280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

Reserved

02A2 0284

02A2 0288

02A2 028C - 02A2 02FC

02A2 0300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

02A2 0304

02A2 0308

02A2 030C

02A2 0310

02A2 0314

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A2 0318 - 02A2 033C

02A2 0340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

02A2 0344

02A2 0348

02A2 034C

02A2 0350

02A2 0354

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A2 0358 - 02A2 037C

02A2 0380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

02A2 0384

02A2 0388

02A2 038C

02A2 0390

02A2 0394

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A2 0398 - 02A2 03BC

02A2 03C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

02A2 03C4

02A2 03C8

02A2 03CC

02A2 03D0

02A2 03D4

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A2 03D8 - 02A2 7FFF

Table 6-18. EDMA3 Transfer Controller 1 Registers

HEX ADDRESS RANGE

02A2 8000

ACRONYM

REGISTER NAME

PID

TCCFG

-

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A2 8004

02A2 8008 - 02A2 80FC

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Table 6-18. EDMA3 Transfer Controller 1 Registers (continued)

HEX ADDRESS RANGE

02A2 8100

ACRONYM

TCSTAT

-

REGISTER NAME

EDMA3TC Channel Status Register

Reserved

02A2 8104 - 02A2 811C

02A2 8120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A2 8124

Error Enable Register

Error Clear Register

02A2 8128

02A2 812C

Error Details Register

Error Interrupt Command Register

Reserved

02A2 8130

02A2 8134 - 02A2 813C

02A2 8140

RDRATE

-

Read Rate Register

02A2 8144 - 02A2 823C

02A2 8240

Reserved

SAOPT

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

02A2 8244

SASRC

SACNT

02A2 8248

02A2 824C

SADST

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A2 8250

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

02A2 8254

02A2 8258

02A2 825C

02A2 8260

02A2 8264 - 02A2 827C

02A2 8280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

02A2 8284

Destination FIFO Set Destination Address B Reference Register

Reserved

02A2 8288

02A2 828C - 02A2 82FC

02A2 8300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

02A2 8304

02A2 8308

02A2 830C

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

02A2 8310

02A2 8314

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A2 8318 - 02A2 833C

02A2 8340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

02A2 8344

02A2 8348

02A2 834C

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

02A2 8350

02A2 8354

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A2 8358 - 02A2 837C

02A2 8380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

02A2 8384

02A2 8388

02A2 838C

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

02A2 8390

02A2 8394

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A2 8398 - 02A2 83BC

02A2 83C0

DFOPT3

DFSRC3

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

02A2 83C4

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Table 6-18. EDMA3 Transfer Controller 1 Registers (continued)

HEX ADDRESS RANGE

02A2 83C8

ACRONYM

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

REGISTER NAME

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A2 83CC

02A2 83D0

02A2 83D4

02A2 83D8 - 02A2 FFFF

Table 6-19. EDMA3 Transfer Controller 2 Registers

HEX ADDRESS RANGE

02A3 0000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A3 0004

TCCFG

-

02A3 0008 - 02A3 00FC

02A3 0100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A3 0104 - 02A3 011C

02A3 0120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A3 0124

Error Enable Register

02A3 0128

Error Clear Register

02A3 012C

Error Details Register

02A3 0130

Error Interrupt Command Register

Reserved

02A3 0134 - 02A3 013C

02A3 0140

RDRATE

-

Read Rate Register

02A3 0144 - 02A3 023C

02A3 0240

Reserved

SAOPT

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

02A3 0244

02A3 0248

02A3 024C

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A3 0250

02A3 0254

02A3 0258

02A3 025C

02A3 0260

02A3 0264 - 02A3 027C

02A3 0280

DFCNTRLD

DFSRCBREF

DFDSTBREF

-

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

Reserved

02A3 0284

02A3 0288

02A3 028C - 02A3 02FC

02A3 0300

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A3 0304

02A3 0308

02A3 030C

02A3 0310

02A3 0314

02A3 0318 - 02A3 033C

02A3 0340

DFOPT1

DFSRC1

DFCNT1

DFDST1

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

02A3 0344

02A3 0348

02A3 034C

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Table 6-19. EDMA3 Transfer Controller 2 Registers (continued)

HEX ADDRESS RANGE

02A3 0350

ACRONYM

DFBIDX1

DFMPPRXY1

-

REGISTER NAME

Destination FIFO BIDX Register 1

02A3 0354

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A3 0358 - 02A3 037C

02A3 0380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A3 0384

02A3 0388

02A3 038C

02A3 0390

02A3 0394

02A3 0398 - 02A3 03BC

02A3 03C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A3 03C4

02A3 03C8

02A3 03CC

02A3 03D0

02A3 03D4

02A3 03D8 - 02A3 7FFF

Table 6-20. EDMA3 Transfer Controller 3 Registers

HEX ADDRESS RANGE

02A3 8000

ACRONYM

PID

REGISTER NAME

Peripheral Identification Register

EDMA3TC Configuration Register

Reserved

02A3 8004

TCCFG

-

02A3 8008 - 02A3 80FC

02A3 8100

TCSTAT

-

EDMA3TC Channel Status Register

Reserved

02A3 8104 - 02A3 811C

02A3 8120

ERRSTAT

ERREN

ERRCLR

ERRDET

ERRCMD

-

Error Register

02A3 8124

Error Enable Register

02A3 8128

Error Clear Register

02A3 812C

Error Details Register

02A3 8130

Error Interrupt Command Register

Reserved

02A3 8134 - 02A3 813C

02A3 8140

RDRATE

-

Read Rate Register

02A3 8144 - 02A3 823C

02A3 8240

Reserved

SAOPT

SASRC

SACNT

SADST

SABIDX

SAMPPRXY

SACNTRLD

SASRCBREF

SADSTBREF

-

Source Active Options Register

Source Active Source Address Register

Source Active Count Register

Source Active Destination Address Register

Source Active Source B-Index Register

Source Active Memory Protection Proxy Register

Source Active Count Reload Register

Source Active Source Address B-Reference Register

Source Active Destination Address B-Reference Register

Reserved

02A3 8244

02A3 8248

02A3 824C

02A3 8250

02A3 8254

02A3 8258

02A3 825C

02A3 8260

02A3 8264 - 02A3 827C

02A3 8280

DFCNTRLD

DFSRCBREF

DFDSTBREF

Destination FIFO Set Count Reload

Destination FIFO Set Destination Address B Reference Register

02A3 8284

02A3 8288

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Table 6-20. EDMA3 Transfer Controller 3 Registers (continued)

HEX ADDRESS RANGE

02A3 828C - 02A3 82FC

02A3 8300

ACRONYM

-

REGISTER NAME

Reserved

DFOPT0

DFSRC0

DFCNT0

DFDST0

DFBIDX0

DFMPPRXY0

-

Destination FIFO Options Register 0

Destination FIFO Source Address Register 0

Destination FIFO Count Register 0

Destination FIFO Destination Address Register 0

Destination FIFO BIDX Register 0

Destination FIFO Memory Protection Proxy Register 0

Reserved

02A3 8304

02A3 8308

02A3 830C

02A3 8310

02A3 8314

02A3 8318 - 02A3 833C

02A3 8340

DFOPT1

DFSRC1

DFCNT1

DFDST1

DFBIDX1

DFMPPRXY1

-

Destination FIFO Options Register 1

Destination FIFO Source Address Register 1

Destination FIFO Count Register 1

Destination FIFO Destination Address Register 1

Destination FIFO BIDX Register 1

Destination FIFO Memory Protection Proxy Register 1

Reserved

02A3 8344

02A3 8348

02A3 834C

02A3 8350

02A3 8354

02A3 8358 - 02A3 837C

02A3 8380

DFOPT2

DFSRC2

DFCNT2

DFDST2

DFBIDX2

DFMPPRXY2

-

Destination FIFO Options Register 2

Destination FIFO Source Address Register 2

Destination FIFO Count Register 2

Destination FIFO Destination Address Register 2

Destination FIFO BIDX Register 2

Destination FIFO Memory Protection Proxy Register 2

Reserved

02A3 8384

02A3 8388

02A3 838C

02A3 8390

02A3 8394

02A3 8398 - 02A3 83BC

02A3 83C0

DFOPT3

DFSRC3

DFCNT3

DFDST3

DFBIDX3

DFMPPRXY3

-

Destination FIFO Options Register 3

Destination FIFO Source Address Register 3

Destination FIFO Count Register 3

Destination FIFO Destination Address Register 3

Destination FIFO BIDX Register 3

Destination FIFO Memory Protection Proxy Register 3

Reserved

02A3 83C4

02A3 83C8

02A3 83CC

02A3 83D0

02A3 83D4

02A3 83D8 - 02A3 FFFF

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6.7 Reset Controller

The reset controller detects the different types of resets supported on the DM647/DM648 devices and

manages the distribution of those resets throughout the device.

The device has several types of resets: power-on reset, warm reset, max reset and system reset.

Table 6-21 explains further the types of reset, the reset initiator, and the effects of each reset on the chip.

See Section 6.7.8 for more information on the effects of each reset on the PLL controllers and their clocks.

Table 6-21. Device-Level Reset Types

TYPE

INITIATOR

EFFECT(s)

Power-on Reset

POR pin

Resets the entire chip including the test and emulation logic.

Resets everything except for the test and emulation logic and the

Ethernet Subsystem

Warm Reset

Max Reset

RESET pin

Emulator

Same as a warm reset

A system reset maintains memory contents and does not reset the

test and emulation circuit and the Ethernet Subsystem. The device

configuration pins are also not re-latched and system reset does not

affect the state of the peripherals (enable/disable).

System Reset

Emulator/PCI via the PRST pin

In addition to device-level global resets, the PSC provides the capability to cause local resets to

peripherals and/or the CPU.

6.7.1 Power-on Reset (POR Pin)

Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test

and emulation logic. Power-on reset is also referred to as a cold reset since the device usually goes

through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power

supplies have reached their normal operating conditions. Note that a device power-up cycle is not required

to initiate a power-on reset.

The following sequence must be followed during a power-on reset:

1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low). While POR is asserted, all pins will be in high-impedance mode. After the POR pin is

deasserted (driven high), all Z-group pins, low-group pins, and high-group pins are set to their reset

state and will remain at their reset state until configured by their respective peripheral. The clock and

reset of each peripheral is determined by the default settings of the power and sleep controller (PSC).

2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted

(low) for a minimum number of CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI

input clock, PCLK, must also be valid during this time. PCLK is needed only if the PCI module is being

used. If the DDR2 memory controller and the Ethernet Subsystem are not needed, CLKIN2 and

REFCLKP/REFCLKN can be tied low. In this case, the POR pin must remain asserted (low) for a

minimum of 256 CLKIN1 cycles after all power supplies have reached valid operating conditions.

Within the low period of the POR pin, the following occurs:

a. The reset signals flow to the entire chip (including the test and emulation logic), resetting modules

that use reset asynchronously.

b. The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks

are propagated throughout the chip to reset modules that use reset synchronously. By default,

PLL1 is in reset and unlocked.

c. The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held

in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and

all the system clocks are invalid at this point.

d. The RESETSTAT pin stays asserted (low), indicating the device is in reset.

3. The POR pin may now be deasserted (driven high). When the POR pin is deasserted, the

configuration pin values are latched, and the PLL controllers change their system clocks to their default

divide-down values. PLL2 is taken out of reset and automatically starts its locking sequence. Other

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device initialization is also started.

4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,

PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of

both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their

respective system reference clocks. After the pause, the system clocks are restarted at their default

divide-by settings.

The device is now out of reset; device execution begins as dictated by the selected boot mode.

6.7.2 Warm Reset (RESET Pin)

A warm reset has the same effect as a power-on reset, except that in this case, the test and emulation

logic are not reset.

The following sequence must be followed during a warm reset:

1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the low period of the RESET pin,

the following occurs:

a. The Z-group pins, low-group pins, and the high-group pins are set to their reset state

b. The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules

that use reset asynchronously

c. The PLL Controllers are reset. PLL1 switches back to PLL bypass mode, resetting all their

registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock. The PLL1

controller clocks start running at the frequency of the system reference clock. The clocks are

propagated throughout the chip to reset modules that use reset synchronously.

d. The RESETSTAT pin becomes active (low), indicating the device is in reset.

2. . The RESET pin may now be released (driven inactive high). When the RESET pin is released, the

configuration pin values are latched and the PLL controllers immediately change their system clocks to

their default divide-down values. Other device initialization is also started.

After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are

allowed to finish their current cycles and then paused for 10 cycles of their respective system reference

clocks. After the pause the system clocks are restarted at their default divide-by settings.

The clock and reset of each peripheral is determined by the default settings of the PSC.

The device is now out of reset, device execution begins as dictated by the selected boot mode.

6.7.3 Maximum Reset

A maximum (max) reset is initiated by the emulator. The effects are the same as a warm reset, except the

device boot and configuration pins are not re-latched. The emulator initiates a maximum reset via the

ICEPICK module. This ICEPICK initiated reset is nonmaskable.

The max reset sequence is as follows:

1. Max reset is initiated by the emulator. During this time, the following happens:

a. The reset signals flow to the entire chip, resetting all the modules on chip except the test and

emulation logic.

b. The PLL controllers are reset, PLL1 switches back to PLL bypass mode, resetting all their registers

to default values. Both PLL1 and PLL2 are placed in reset and lose lock.

c. The RESETSTAT pin becomes asserted (low), indicating the device is in reset.

2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the

end of these 10 cycles, the RESETSTAT pin is deasserted (driven high). At this point, the following

occurs:

a. The I/O pins are controlled by the default peripherals (default peripherals are determined by

PINMUX register).

b. The clock and reset of each peripheral is determined by the default settings of the power and sleep

controller (PSC).

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c. The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).

After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not

latched with a max reset, the previous values (as shown in the BOOTCFG register) are used to

select the bootmode. For more details on the boot sequence, see the Using the

TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1). After the boot

sequence, follow the software initialization sequence.

6.7.4 System Reset

A system reset maintains memory contents and does not reset the clock logic or the test and emulation

circuitry. The device configuration pins are also not re-latched and the state of the peripherals

(enabled/disabled) is also not affected. A system reset is initiated by the emulator or by the PRST pin of

PCI peripheral.

During a system reset, the following happens:

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to

propagate through the system. Internal system clocks are not affected.

2. After the internal reset signal has propagated, the PLL controllers pause and restart their system

clocks for about 10 cycles of their system reference clocks, but retain their configuration. The PLLs

also remain locked.

3. The boot sequence is started after the system clocks are restarted. Since the configuration pins

(including the BOOTMODE[3:0] pins) are not latched with a system reset, the previous values, as

shown in the BOOTCFG register, are used to select the boot mode.

6.7.5 Peripheral Local Reset

The user can configure the local reset and clock state of a peripheral through programming the PSC.

Table 6-2 identifies the LPSC numbers and the peripherals capable of being locally reset by the PSC. For

more detailed information on the programming of these peripherals by the PSC, see the

TMS320DM647/TMS320DM648 DMP DSP Subsystem Reference Guide (literature number SPRUEU6).

6.7.6 Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTRL processes only the highest priority

reset request. The reset request priorities are as follows (high to low):

•

Power-on Reset

Maximum Reset

Warm Reset

System Reset

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6.7.7 Reset Controller Register

The reset type status (RSTYPE) register is the only register for the reset controller.

6.7.7.1 Reset Type Status Register Description

The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur

simultaneously, this register latches the highest priority reset source. The reset type status register is

shown in Figure 6-9 and described in Table 6-22.

31

15

16

Reserved

R-0

4

3

2

1

0

Reserved

R-0

SRST MRST WRST POR

R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 6-9. Reset Type Status Register (RSTYPE)

Table 6-22. Reset Type Status Register (RSTYPE) Field Descriptions

Bit

31:4

3

Field

Value Description

Reserved

SRST

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

System reset

0

1

System Reset was not the last reset to occur.

System Reset was the last reset to occur.

Max reset

2

1

0

MRST

WRST

POR

0

1

Max Reset was not the last reset to occur.

Max Reset was the last reset to occur.

Warm reset

0

1

Warm Reset was not the last reset to occur.

Warm Reset was the last reset to occur.

Power-on reset

0

1

Power-on Reset was not the last reset to occur.

Power-on Reset was the last reset to occur.

6.7.8 Reset Electrical Data/Timing

NOTE

If a configuration pin must be routed out from the device, the internal pullup/pulldown

(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external

pullup/pulldown resistor.

Table 6-23. Timing Requirements for Reset⁽¹⁾⁽²⁾(see Figure 6-10 and Figure 6-11)

-720

-900

NO.

UNIT

MIN

MAX

5

6

t_w(POR)

t_w(RESET)

Pulse duration, POR low

⁽³⁾ns

ns

Pulse duration, RESET low

(1) C = 1/CLKIN1 clock frequency in ns.

(2) D = 1/CLKIN2 clock frequency in ns.

(3) If CLKIN2 is not used, t_w(POR)must be measured in terms of CLKIN1 cycles; otherwise, use CLKIN2 cycles.

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Table 6-23. Timing Requirements for Reset (see Figure 6-10 and Figure 6-11) (continued)

-720

-900

NO.

UNIT

MIN

MAX

Setup time, boot mode and configuration pins valid before POR high or

RESET high⁽⁴⁾

7

8

t_su(boot)

t_h(boot)

ns

Hold time, boot mode and configuration pins valid after POR high or

RESET high⁽⁴⁾

(4) AEA[22:11], and UHPIEN are the boot configuration pins during device reset.

Table 6-24. Switching Characteristics Over Recommended Operating Conditions During Reset⁽¹⁾

(see Figure 6-11)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

9

t_{d(PORH-RSTATH)}

Delay time, POR high AND RESET high to RESETSTAT high

ns

For Figure 6-10, note the following:

•

Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high

impedance as soon as their respective power supply has reached normal operating conditions. Pins

remain in high impedance until configured otherwise by their respective peripherals.

•

Low group consists of: Pins become low as soon as their respective power supply has reached normal

operating conditions. Pins remain low until configured otherwise by their respective peripheral.

High group consists of: . Pins become high as soon as their respective power supply has reached

normal operating conditions. Pins remain high until configured otherwise by their respective peripheral.

All peripherals must be enable through software following a power-on reset; for more details, see

Section 6.7.1, Power-on Reset.

For power-supply sequence requirements, see Section 6.3.1.

(1) C = 1/CLKIN1 clock frequency in ns.

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Power Supplies Ramping

Power Supplies Stable

CLKIN1

PCLK

5

POR

RESET

9

RESETSATT

SYSREFCLK (PLL1C)

SYSCLK2

SYSCLK3

SYSCLK4

SYSCLK5

AECLKOUT (Internal)

7

Boot and Device

Configuration Pins

8

High-Z

Z Group

Low Group

High Group

Undefined

Low

High

CLKIN2

Undefined

Internal Reset PLL2C

SYSREFCLK (PLL2C)

SYSCLK1 (PLL2C)

(A)

PLL2 Locked

Undefined

PLL2 Unlocked

(B)

Clock Valid

A. SYSREFCLK of the PLL2 controller runs at CLKIN2 ×10.

B. SYSCLK1 of PLL2 controller runs at SYSREFCLK/2 (default).

C. Power supplies, CLKIN1, CLKIN2 (if used), and PCLK (if used) must be stable before the start of t_w(POR)

.

Figure 6-10. Power-Up Timing

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A. RESET should be used only after device has been powered up. For more details on the use of the RESET pin, see

Section 6.7, Reset Controller.

B. A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the

RESET pin during a Warm Reset.

C. Boot and Device Configuration Inputs (during reset) include: AEA[22:11], and UHPIEN.

Figure 6-11. Warm Reset and Max Reset Timing

A. RESET should be used only after device has been powered up. For more details on the use of the RESET pin, see

Section 6.7, Reset Controller.

B. Boot and Device Configuration Inputs (during reset) include: AEA[22:11], and UHPIEN.

Figure 6-12. System Reset Timing

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6.8 Interrupts

The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for

each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation

of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-26

summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP

interrupt control, see TMS320DM647/DM648 DMP DSP Subsystem Reference Guide (literature number

SPRUEU6).

Table 6-25. DM647/DM648 DSP Interrupts

DSP

EVENT

INTERRUPT SOURCE

INTERRUPT

NUMBER

0

EVT0

EVT1

EVT2

EVT33

Output of event combiner 0, for events 1 – 31

Output of event combiner 1, for events 32 – 63

Output of event combiner 2, for events 64 – 95

Output of event combiner 3, for events 96 – 127

Reserved

1

2

3

4-8

9

EMU_DTDMA

ECM interrupt for:

•

Host scan access

DTDMA transfer complete

AET interrupt

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30 -31

32

33

34

35

36

37

38

39

Reserved

EMU_RTDXRX

EMU_RTDXTX

IDMA0 EMC

IDMA1 EMC

HINT

Reserved

RTDX receive complete

RTDX transmit complete

C64x+ EMC 0

C64x+ EMC 1

Host interrupt

I2CINT

I2C interrupt

Reserved

AEASYNCERR

TINT2L

Reserved

EMIFA Error Interrupt

Timer interrupt low

Timer interrupt high

Timer interrupt low

Timer interrupt high

PSC-ALLINT

TINT2H

TINT3L

TINT3H

PSCINT

TPCC_GINT

SPIINT0

EDMA3 channel global completion interrupt

SPI Interrupt

SPIINT1

SPI Interrupt

DSQINT

VICP – Sqr (DSP int)

VICP – IMX

IMXINT

VLCDINT

VICP - VLCD

Reserved

RX_PULSE

RX_THRESH_PULSE

TX_PULSE

MISC_PULSE

UART_INT

Ethernet Subsystem RX pulse interrupt

Ethernet Subsystem RX threshold interrupt

Ethernet Subsystem TX pulse interrupt

Ethernet Subsystem MISC pulse interrupt

UART Interrupt

VP0_INT

VP0 Interrupt

VP1_INT

VP1 Interrupt

VP2_INT

VP2 Interrupt

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Table 6-25. DM647/DM648 DSP Interrupts (continued)

DSP

EVENT

INTERRUPT SOURCE

INTERRUPT

NUMBER

40

41

42

43

44

45-49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

VP3_INT

VP4_INT

GPIO_BNK1_INT

AXINT

VP3 Interrupt

VP4 Interrupt

(GPIO16:31) GPIO Bank 1 Interrupt.

TX Interrupt McASP

RX Interrupt McASP

Reserved

ARINT

VINT

VLYNQ Pulse Interrupt

GPIO Interrupt

GPINT0

GPINT1

GPIO Interrupt

GPINT2

GPIO Interrupt

GPINT3

GPIO Interrupt

GPINT4

GPIO Interrupt

GPINT5

GPIO Interrupt

GPINT6

GPIO Interrupt

GPINT7

GPIO Interrupt

GPINT8

GPIO Interrupt

GPINT9

GPIO Interrupt

GPINT10

GPIO Interrupt

GPINT11

GPIO Interrupt

GPINT12

GPIO Interrupt

GPINT13

GPIO Interrupt

GPINT14

GPIO Interrupt

GPINT15

GPIO Interrupt

TINT0L

Timer interrupt low

TINT0H

Timer interrupt high

TINT1L

Timer interrupt low

TINT1H

Timer interrupt high

EDMA3CC_INT0

EDMA3CC_INT1

EDMA3CC_INT2

EDMA3CC_INT3

EDMA3CC_INT4

EDMA3CC_INT5

EDMA3CC_INT6

EDMA3CC_INT7

EDMA3CC_ERRINT

EDMA3CC_MPINT

EDMA3TC0_ERRINT

EDMA3TC1_ERRINT

EDMA3TC2_ERRINT

EDMA3TC3_ERRINT

Reserved

EDMA3CC Completion Interrupt - Mask0

EDMA3CC Completion Interrupt – Mask1

EDMA3CC Completion Interrupt – Mask2

EDMA3CC Completion Interrupt – Mask3

EDMA3CC Completion Interrupt – Mask4

EDMA3CC Completion Interrupt – Mask5

EDMA3CC Completion Interrupt – Mask6

EDMA3CC Completion Interrupt – Mask7

EDMA3CC Error Interrupt

EDMA3CC Memory Protection Interrupt

EDMA3TC0 Error Interrupt

EDMA3TC1 Error Interrupt

EDMA3TC2 Error Interrupt

EDMA3TC3 Error Interrupt

Reserved

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Table 6-25. DM647/DM648 DSP Interrupts (continued)

DSP

EVENT

INTERRUPT SOURCE

INTERRUPT

NUMBER

90

Reserved

INTERR

Reserved

91

92

93

94

95

96

C64x+ Interrupt Controller Dropped CPU Interrupt Event

C64x+ EMC Invalid IDMA Parameters

Reserved

97

EMC_IDMAERR

Reserved

EFIINTA

98

99

Reserved

100

101

102 - 112

113

114-115

116

117

118

119

120

121

122

123

124

125

126

127

EFI Interrupt from side A.

EFI Interrupt from side B

EFIINTB

Reserved

L1P_ED

Reserved

L1P Single bit error detected during DMA read

Reserved

L2_ED1

L2 single bit error detected

L2 two bit error detected

L2_ED2

PDC_INT

Reserved

L1P_CMPA

L1P_DMPA

L1D_CMPA

L1D_DMPA

L2_CMPA

L2_DMPA

IDMA_CMPA

IDMA_BUSERR

Power Down sleep interrupt

Reserved

L1P CPU memory protection fault

L1P DMA memory protection fault

L1D CPU memory protection fault

L1D DMA memory protection fault

L2 CPU memory protection fault

L2 DMA memory protection fault

IDMA CPU memory protection fault

IDMA bus error interrupt

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Table 6-26. C64x+ Interrupt Controller Registers

HEX ADDRESS

0x0180 0000

0x0180 0004

0x0180 0008

0x0180 000C

0x0180 0020

0x0180 0024

0x0180 0028

0x0180 002C

0x0180 0040

0x0180 0044

0x0180 0048

0x0180 004C

0x0180 0080

0x0180 0084

0x0180 0088

0x0180 008C

0x0180 00A0

0x0180 00A4

0x0180 00A8

0x0180 00AC

0x0180 00C0

0x0180 00C4

0x0180 00C8

0x0180 00CC

0x0180 00E0

0x0180 00E4

0x0180 00E8

0x0180 00EC

0x0180 0104

0x0180 0108

0x0180 010C

0x0180 0140

0x0180 0144

0x0180 0180

0x0180 0184

0x0180 0188

0x0180 01C0

ACRONYM

EVTFLAG0

EVTFLAG1

EVTFLAG2

EVTFLAG3

EVTSET0

REGISTER DESCRIPTION

Event flag register 0

Event flag register 1

Event flag register 2

Event flag register 3

Event set register 0

EVTSET1

Event set register 1

EVTSET2

Event set register 2

EVTSET3

Event set register 3

EVTCLR0

Event clear register 0

EVTCLR1

Event clear register 1

EVTCLR2

Event clear register 2

EVTCLR3

Event clear register 3

EVTMASK0

EVTMASK1

EVTMASK2

EVTMASK3

MEVTFLAG0

MEVTFLAG1

MEVTFLAG2

MEVTFLAG3

EXPMASK0

EXPMASK1

EXPMASK2

EXPMASK3

MEXPFLAG0

MEXPFLAG1

MEXPFLAG2

MEXPFLAG3

INTMUX1

Event mask register 0

Event mask register 1

Event mask register 2

Event mask register 3

Masked event flag register 0

Masked event flag register 1

Masked event flag register 2

Masked event flag register 3

Exception mask register 0

Exception mask register 1

Exception mask register 2

Exception mask register 3

Masked exception flag register 0

Masked exception flag register 1

Masked exception flag register 2

Masked exception flag register 3

Interrupt mux register 1

Interrupt mux register 2

Interrupt mux register 3

Advanced event generator mux register 0

Advanced event generator mux register 1

Interrupt exception status

Interrupt exception clear

Dropped interrupt mask register

Event assert register

INTMUX2

INTMUX3

AEGMUX0

AEGMUX1

INTXSTAT

INTXCLR

INTDMASK

EVTASRT

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6.9 DDR2 Memory Controller

The 32-bit DDR2 memory controller bus of the DM647/DM648 is used to interface to JESD79D-2A

standard-compliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM

devices; it does not share the bus with any other types of peripherals. The decoupling of DDR2 memories

from other devices both simplifies board design and provides I/O concurrency from a second external

memory interface, EMIFA.

The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum

throughput of the DDR2 bus. The data rate of the DDR2 bus is equal to the CLKIN2 frequency multiplied

by 20. The internal data bus clock frequency of the DDR2 memory controller is fixed at a divide-by-three

ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the two bus

frequencies. For example, if the internal data bus frequency is 300 MHz (CPU frequency is 900 MHz) and

the DDR2 data rate is 533 MHz (266 MHz clock rate as CLKIN2 frequency is 26.6 MHz), the maximum

data rate achievable by the DDR2 memory controller is 2.13 Gbytes/sec.

6.9.1 DDR2 Memory Controller Device-Specific Information

The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces

such as EMIF and HPI. For these other interfaces the device timing was specified in terms of data manual

specifications and I/O buffer information specification (IBIS) models.

For the DM647/DM648 DDR2 memory bus, the approach is to specify compatible DDR2 devices and

provide the printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI)

has performed the simulation and system characterization to be sure all DDR2 interface timings in this

solution are met. The complete DDR2 system solution is documented in the Implementing DDR2 PCB

Layout on the TMS320DM647/DM648 DMSoC (literature number SPRAAK9) and TI supports only designs

that follow the guidelines in this application report.

The DDR2 Memory Controller pins must be enabled by setting the DDR2_EN configuration pin (ABA0)

high during device reset.

The ODT[1:0] pins of the memory controller must be left unconnected. The ODT pins on the DDR2

memory device(s) must be connected to ground.

The DDR2 memory controller on the DM647/DM648 devices supports the following memory topologies:

•

A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.

A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.

A race condition may exist when certain masters write data to the DDR2 memory controller. For example,

if master A passes a software message via a buffer in external memory and does not wait for indication

that the write completes, when master B attempts to read the software message, then the master B read

may bypass the master A write and, thus, master B may read stale data and, therefore, receive an

incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete

before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have

hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the DDR2 memory controller module ID and revision register.

3. Perform a dummy read to the DDR2 memory controller module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The

completion of the read in step 3 ensures that the previous write was done.

The master peripherals that need to implement this workaround are HPI, PCI, and VLYNQ.

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6.9.2 DDR2 Memory Controller Peripheral Register Description(s)

Table 6-27. DDR2 Memory Controller Registers

HEX ADDRESS RANGE

0x7800 0000

ACRONYM

REGISTER NAME

MIDR

DDR2 Memory Controller Module and Revision Register

0x7800 0004

DMCSTAT

DDR2 Memory Controller Status Register

0x7800 0008

SDCFG

DDR2 Memory Controller SDRAM Configuration Register

0x7800 000C

SDRFC

DDR2 Memory Controller SDRAM Refresh Control Register

0x7800 0010

SDTIM1

DDR2 Memory Controller SDRAM Timing 1 Register

0x7800 0014

SDTIM2

DDR2 Memory Controller SDRAM Timing 2 Register

0x7800 0018

-

Reserved

0x7800 0020

BPRIO

DDR2 Memory Controller Burst Priority Register

0x7800 0024 - 0x7800 004C

0x7800 0050 - 0x7800 0078

0x7800 007C - 0x7800 00BC

0x7800 00C0 - 0x7800 00E0

0x7800 00E4

-

Reserved

-

Reserved

-

Reserved

-

Reserved

DMCCTL

DDR2 Memory Controller Control Register

0x7800 00E8 - 0x7800 00FC

0x7800 0100 - 0x7FFF FFFF

-

Reserved

6.9.3 DDR2 Memory Controller Electrical Data/Timing

The Implementing DDR2 PCB Layout on the TMS320DM647/DM648 DMSoC Application Report

(literature number SPRAAK9) specifies a complete DDR2 interface solution for the DM647/DM648 as well

as a list of compatible DDR2 devices. TI has performed the simulation and system characterization to be

sure all DDR2 interface timings in this solution are met; therefore, no electrical data/timing information is

supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application

report, SPRAAA7, cited earlier.

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6.10 External Memory Interface A (EMIFA)

The EMIFA can interface to a variety of external devices or ASICs, including:

•

Pipelined and flow-through synchronous-burst SRAM (SBSRAM)

ZBT (zero bus turnaround) SRAM and late write SRAM

Synchronous FIFOs

Asynchronous memory, including SRAM, ROM, and Flash

6.10.1 EMIFA Device-Specific Information

Timing analysis must be done to verify all ac timing requirements are met. TI recommends utilizing I/O

buffer information specification (IBIS) to analyze all ac timing.

To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS

Models for Timing Analysis Application Report (literature number SPRA839).

To maintain signal integrity, serial termination resistors should be inserted into all EMIFA output signal

lines.

A race condition may exist when certain masters write data to the EMIFA. For example, if master A

passes a software message via a buffer in external memory and does not wait for indication that the write

completes, when master B attempts to read the software message, then the master B read may bypass

the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete

before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have

hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write.

2. Perform a dummy write to the EMIFA module ID and revision register.

3. Perform a dummy read to the EMIFA module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The

completion of the read in step 3 ensures that the previous write was done.

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6.10.2 EMIFA Peripheral Register Description(s)

Table 6-28. EMIFA Registers

HEX ADDRESS RANGE

0x7000 0000

ACRONYM

REGISTER NAME

MIDR

Module ID and Revision Register

Status Register

0x7000 0004

STAT

0x7000 0008

-

Reserved

0x7000 000C - 0x7000 001C

0x7000 0020

-

Reserved

BPRIO

Burst Priority Register

Reserved

0x7000 0024 - 0x7000 004C

0x7000 0050 - 0x7000 007C

0x7000 0080

-

Reserved

CE2CFG

EMIFA CE2 Configuration Register

EMIFA CE3 Configuration Register

Reserved

0x7000 0084

CE3CFG

0x7000 0088

-

0x7000 008C

-

Reserved

0x7000 0090 - 0x7000 009C

0x7000 00A0

-

Reserved

AWCC

EMIFA Async Wait Cycle Configuration Register

Reserved

0x7000 00A4 - 0x7000 00BC

0x7000 00C0

-

INTRAW

INTMSK

INTMSKSET

INTMSKCLR

-

EMIFA Interrupt RAW Register

EMIFA Interrupt Masked Register

EMIFA Interrupt Mask Set Register

EMIFA Interrupt Mask Clear Register

Reserved

0x7000 00C4

0x7000 00C8

0x7000 00CC

0x7000 00D0 - 0x7000 00DC

0x7000 00E0 - 0x77FF FFFF

-

Reserved

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6.10.3 EMIFA Electrical Data/Timing

Table 6-29. Timing Requirements for AECLKIN for EMIFA⁽¹⁾⁽²⁾(see Figure 6-13)

-720

-900

NO.

UNIT

MIN

MAX

1

2

3

4

5

t_c(EKI)

t_w(EKIH)

t_w(EKIL)

t_t(EKI)

Cycle time, AECLKIN

6⁽³⁾

2.7

40

ns

Pulse duration, AECLKIN high

Pulse duration, AECLKIN low

Transition time, AECLKIN

Period Jitter, AECLKIN

2

t_J(EKI)

0.02E⁽⁴⁾

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

(2) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

(3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times

are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.

(4) This timing applies only when AECLKIN is used for EMIFA.

1

5

4

2

AECLKIN

3

4

Figure 6-13. AECLKIN Timing for EMIFA

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Table 6-30. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the

EMIFA Module^(1)(2)(3)(see Figure 6-14)

-720

-900

NO.

PARAMETER

Cycle time, AECLKOUT

UNIT

MIN

MAX

1

2

3

4

5

6

t_c(EKO)

E – 0.7

EH – 0.7

EL – 0.7

E + 0.7

ns

t_w(EKOH)

t_w(EKOL)

Pulse duration, AECLKOUT high

EH + 0.7

Pulse duration, AECLKOUT low

EL + 0.7

t_t(EKO)

Transition time, AECLKOUT

1

8

t_d(EKIH-EKOH)

t_d(EKIL-EKOL)

Delay time, AECLKIN high to AECLKOUT high

Delay time, AECLKIN low to AECLKOUT low

1

AECLKIN

1

6

3

4

5

2

AECLKOUT1

A. E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

B. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

C. EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns

for EMIFA.

Figure 6-14. AECLKOUT Timing for the EMIFA Module

(1) E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

(2) The reference points for the rise and fall transitions are measured at V_OLMAX and V_OHMIN.

(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

6.10.3.1 Asynchronous Memory Timing

Table 6-31. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module^(1)(2)(3)

(see Figure 6-15 and Figure 6-16)

-720

-900

NO.

UNIT

MIN

MAX

3

4

5

6

7

t_su(EDV-AOEH)

t_h(AOEH-EDV)

t_{su(ARDY-EKOH)}

t_h(EKOH-ARDY)

t_w(ARDY)

Setup time, AEDx valid before AAOE high

Hold time, AEDx valid after AAOE high

6.5

ns

3

Setup time, AARDY valid before AECLKOUT low

Hold time, AARDY valid after AECLKOUT low

Pulse width, AARDY assertion and deassertion

1

2

2E + 5

Delay time, from AARDY sampled deasserted on AECLKOUT falling to

beginning of programmed hold period

8

9

t_d(ARDY-HOLD)

t_{su(ARDY-HOLD)}

4E

ns

Setup time, before end of programmed strobe period by which AARDY

should be asserted in order to insert extended strobe wait states.

2E

(1) E = AECLKOUT period in ns for EMIFA

(2) To specify data setup time, simply program the strobe width wide enough.

(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E

to specify setup and hold time is met.

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Table 6-32. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module^(1)(2)(3)(see Figure 6-15 and Figure 6-16)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

7

1

t_{osu(SELV-AOEL)}

t_{oh(AOEH-SELIV)}

t_d(EKOH-AOEV)

t_{osu(SELV-AWEL)}

t_{oh(AWEH-SELIV)}

t_d(EKOH-AWEV)

Output setup time, select signals valid to AAOE low

Output hold time, AAOE high to select signals invalid

Delay time, AECLKOUT high to AAOE valid

RS * E – 1.5

RS * E – 1.9

1

ns

2

10

11

12

13

Output setup time, select signals valid to AAWE low

Output hold time, AAWE high to select signals invalid

Delay time, AECLKOUT high to AAWE valid

WS * E – 1.7

WH * E – 1.8

1.3

7.1

Strobe = 4

Setup = 1

Hold = 1

AECLKOUT

ACEx

2

1

2

Byte Enables

Address

ABE[7:0]

1

AEA[19:0]/

ABA[1:0]

3

Read Data

4

AED[63:0]

10

(A)

AAOE/ASOE

(A)

AAWE/ASWE

AR/W

(B)

DEASSERTED

AARDY

A. AAOE /ASOE and AAWEASWE operate as AAOE (identified under select signals) and AAWE, respectively, during

asynchronous memory accesses.

B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration

register (AWCC).

Figure 6-15. Asynchronous Memory Read Timing for EMIFA

(1) E = AECLKOUT period in ns for EMIFA

(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters

are programmed via the EMIFA CE Configuration registers (CEnCFG).

(3) Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].

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Strobe = 4

Hold = 1

Setup = 1

AECLKOUT

12

11

ACEx

Byte Enables

Address

ABE[7:0]

11

AEA[19:0]/

ABA[1:0]

12

Write Data

AED[63:0]

(A)

AAOE/ASOE

13

(A)

AAWE/ASWE

11

12

AR/W

(B)

DEASSERTED

AARDY

A. AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during

asynchronous memory accesses.

B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration

register (AWCC).

Figure 6-16. Asynchronous Memory Write Timing for EMIFA

Strobe

Hold = 2

Setup = 2

Extended Strobe

8

9

AECLKOUT

6

5

7

(A)

ASSERTED

DEASSERTED

AARDY

A. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration

register (AWCC).

Figure 6-17. AARDY Timing

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6.10.3.2 Programmable Synchronous Interface Timing

Table 6-33. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 6-18)

-720

-900

NO.

UNIT

MIN

MAX

6

7

t_su(EDV-EKOH)

t_h(EKOH-EDV)

Setup time, read AEDx valid before AECLKOUT high

Hold time, read AEDx valid after AECLKOUT high

2

ns

1.5

Table 6-34. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module⁽¹⁾(see Figure 6-18–Figure 6-20)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

4.9

1

2

t_d(EKOH-CEV)

t_d(EKOH-BEV)

t_d(EKOH-BEIV)

t_d(EKOH-EAV)

t_d(EKOH-EAIV)

t_d(EKOH-ADSV)

t_d(EKOH-OEV)

t_d(EKOH-EDV)

t_d(EKOH-EDIV)

t_d(EKOH-WEV)

Delay time, AECLKOUT high to ACEx valid

Delay time, AECLKOUT high to ABEx valid

Delay time, AECLKOUT high to ABEx invalid

Delay time, AECLKOUT high to AEAx valid

Delay time, AECLKOUT high to AEAx invalid

Delay time, AECLKOUT high to ASADS/ASRE valid

Delay time, AECLKOUT high to ASOE valid

Delay time, AECLKOUT high to AEDx valid

Delay time, AECLKOUT high to AEDx invalid

Delay time, AECLKOUT high to ASWE valid

1.3

ns

4.9

3

4

4.9

5

1.3

8

4.9

9

10

11

12

1.3

4.9

Strobe = 4

Setup = 1

Hold = 1

AECLKOUT

ACEx

2

1

2

Byte Enables

Address

ABE[7:0]

1

AEA[19:0]/

ABA[1:0]

3

Read Data

4

AED[63:0]

10

(A)

AAOE/ASOE

(A)

AAWE/ASWE

AR/W

(B)

DEASSERTED

AARDY

Figure 6-18. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)^(A)

(1) The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):

•

Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency

Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has

been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CE_EXT = 1).

•

Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with

deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (R_ENABLE = 1).

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AECLKOUT

1

2

1

3

ACEx

ABE[7:0]

BE1

BE2

EA2

Q2

BE3

EA3

Q3

BE4

5

4

AEA[19:0]/ABA[1:0]

AED[63:0]

EA1

10

Q1

EA4

Q4

10

11

8

(B)

ASADS/ASRE

(B)

AAOE/ASOE

12

(B)

AAWE/ASWE

A

The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):

− Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency

− Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

− ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been

issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).

− Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect

cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).

− In this figure W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

B

AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Figure 6-19. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)^(A)

Write

Latency =

(B)

1

AECLKOUT

1

3

ACEx

2

ABE[7:0]

BE1

BE2

EA2

BE3

EA3

Q2

BE4

EA4

Q3

5

4

AEA[19:0]/ABA[1:0]

AED[63:0]

EA1

10

11

8

Q1

Q4

8

(B)

ASADS/ASRE

(B)

AAOE/ASOE

12

(B)

AAWE/ASWE

A

B

The following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):

− Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency

− Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

− ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been

issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).

− Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect

cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).

− In this figure W_LTNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

AAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Figure 6-20. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) ^(A)

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6.11 Video Port

Each video port is capable of sending and receiving digital video data. The video ports are also capable of

capturing/displaying RAW data. The video port peripherals follow video standards such as BT.656 and

SMPTE296.

6.11.1 Video Port Device-Specific Information

The DM647/DM648 devices have five video port peripherals.

The video port peripheral can operate as a video capture port, video display port, or as a transport stream

interface (TSI) capture port.

The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the

two channels. The entire port (both channels) is always configured for either video capture or display only.

Separate data pipelines control the parsing and formatting of video capture or display data for each of the

BT.656, Y/C, raw video, and TSI modes.

For video capture operation, the video port may operate as two 8-bit channels of BT.656 or raw video

capture; or as a single channel of 8-bit BT.656, 8-bit raw video, 16-bit Y/C video, 16-bit raw video, or 8-bit

TSI.

For video display operation, the video port may operate as a single channel of 8-bit BT.656; or as a single

channel of 8-bit BT.656, 8-bit raw video, 16-bit Y/C video, or 16-bit raw video. It may also operate in a two

channel 8-bit raw mode in which the two channels are locked to the same timing. Channel B is not used

during single channel operation.

For more detailed information on the DM647/DM648 video port peripherals, see the

TMS320DM647/DM648 Video Port User's Guide (literature number SPRUEM1).

6.11.2 Video Port Peripheral Register Description(s)

Table 6-35. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

VP0

VP1

VP2

VP3

VP4

Video Port Peripheral Identification

Register

0x02C0 0000

0x02C0 4000

0x02C0 8000

0x02C0 C000

0x02C1 0000

VP_PIDx

0x02C0 0004

0x02C0 0008

0x02C0 000C

0x02C0 0020

0x02C0 0024

0x02C0 0028

0x02C0 002C

0x02C0 0030

0x02C0 0034

0x02C0 0038

0x02C0 003C

0x02C0 0040

0x02C0 0044

0x02C0 00C0

0x02C0 00C4

0x02C0 00C8

0x02C0 00CC

0x02C0 0100

0x02C0 4004

0x02C0 4008

0x02C0 400C

0x02C0 4020

0x02C0 4024

0x02C0 4028

0x02C0 402C

0x02C0 4030

0x02C0 4034

0x02C0 4038

0x02C0 403C

0x02C0 4040

0x02C0 4044

0x02C0 40C0

0x02C0 40C4

0x02C0 40C8

0x02C0 40CC

0x02C0 4100

0x02C0 8004

0x02C0 8008

0x02C0 800C

0x02C0 8020

0x02C0 8024

0x02C0 8028

0x02C0 802C

0x02C0 8030

0x02C0 8034

0x02C0 8038

0x02C0 803C

0x02C0 8040

0x02C0 8044

0x02C0 80C0

0x02C0 80C4

0x02C0 80C8

0x02C0 80CC

0x02C0 8100

0x02C0 C004

0x02C0 C008

0x02C0 C00C

0x02C0 C020

0x02C0 C024

0x02C0 C028

0x02C0 C02C

0x02C0 C030

0x02C0 C034

0x02C0 C038

0x02C0 C03C

0x02C0 C040

0x02C0 C044

0x02C0 C0C0

0x02C0 C0C4

0x02C0 C0C8

0x02C0 C0CC

0x02C0 C100

0x02C1 0004

0x02C1 0008

0x02C1 000C

0x02C1 0020

0x02C1 0024

0x02C1 0028

0x02C1 002C

0x02C1 0030

0x02C1 0034

0x02C1 0038

0x02C1 003C

0x02C1 0040

0x02C1 0044

0x02C1 00C0

0x02C1 00C4

0x02C1 00C8

0x02C1 00CC

0x02C1 0100

VP_PCRx

–

Video Port Peripheral Control Register

Reserved

–

Reserved

VP_PFUNCx

VP_PDIRx

VP_PDINx

VP_PDOUTx

VP_PDSETx

VP_PDCLRx

VP_PIENx

VP_PIPOx

VP_PISTATx

VP_PICLRx

VP_CTLx

VP_STATx

VP_IEx

Video Port Pin Function Register

Video Port Pin Direction Register

Video Port Pin Data Input Register

Video Port Pin Data Output Register

Video Port Pin Data Set Register

Video Port Pin Data Clear Register

Video Port Pin Interrupt Enable Register

Video Port Pin Interrupt Polarity Register

Video Port Pin Interrupt Status Register

Video Port Pin Interrupt Clear Register

Video Port Control Register

Video Port Status Register

Video Port Interrupt Enable Register

Video Port interrupt Status Register

Video Capture Channel A Status Register

VP_ISx

VC_STATx

Video Capture Channel A Control

Register

0x02C0 0104

0x02C0 4104

0x02C0 8104

0x02C0 C104

0x02C1 0104

VC_CTLx

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Table 6-35. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

VP0

VP1

VP2

VP3

VP4

Video Capture Channel A Field 1 Start

Register

0x02C0 0108

0x02C0 4108

0x02C0 8108

0x02C0 C108

0x02C1 0108

VC_ASTRTx

VC_ASTOPx

VC_ASTRTx

VC_ASTOPx

VC_AVINTx

VC_ATHRLDx

Video Capture Channel A Field 1 Stop

Register

0x02C0 010C

0x02C0 0110

0x02C0 0114

0x02C0 0118

0x02C0 011C

0x02C0 410C

0x02C0 4110

0x02C0 4114

0x02C0 4118

0x02C0 411C

0x02C0 810C

0x02C0 8110

0x02C0 8114

0x02C0 8118

0x02C0 811C

0x02C0 C10C

0x02C0 C110

0x02C0 C114

0x02C0 C118

0x02C0 C11C

0x02C1 010C

0x02C1 0110

0x02C1 0114

0x02C1 0118

0x02C1 011C

Video Capture Channel A Field 2 Start

Register

Video Capture Channel A Field 2 Stop

Register

Video Capture Channel A Vertical

Interrupt Register

Video Capture Channel A Threshold

Register

Video Capture Channel A Event Count

Register

0x02C0 0120

0x02C0 0140

0x02C0 0144

0x02C0 4120

0x02C0 4140

0x02C0 4144

0x02C0 8120

0x02C0 8140

0x02C0 8144

0x02C0 C120

0x02C0 C140

0x02C0 C144

0x02C1 0120

0x02C1 0140

0x02C1 0144

VC_AEVTCTx

VC_BSTATx

VC_BCTLx

Video Capture Channel B Status Register

Video Capture Channel B Control

Register

Video Capture Channel B Field 1 Start

Register

0x02C0 0148

0x02C0 014C

0x02C0 0150

0x02C0 0154

0x02C0 0158

0x02C0 015C

0x02C0 0160

0x02C0 4148

0x02C0 414C

0x02C0 4150

0x02C0 4154

0x02C0 4158

0x02C0 415C

0x02C0 4160

0x02C0 8148

0x02C0 814C

0x02C0 8150

0x02C0 8154

0x02C0 8158

0x02C0 815C

0x02C0 8160

0x02C0 C148

0x02C0 C14C

0x02C0 C150

0x02C0 C154

0x02C0 C158

0x02C0 C15C

0x02C0 C160

0x02C1 0148

0x02C1 014C

0x02C1 0150

0x02C1 0154

0x02C1 0158

0x02C1 015C

0x02C1 0160

VC_BSTRTx

VC_BSTOPx

VC_BSTRTx

VC_BSTOPx

VC_BVINTx

VC_BTHRLDx

Video Capture Channel B Field 1 Stop

Register

Video Capture Channel B Field 2 Start

Register

Video Capture Channel B Field 2 Stop

Register

Video Capture Channel B Vertical

Interrupt Register

Video Capture Channel B Threshold

Register

Video Capture Channel B Event Count

Register

VC_BEVTCTx

TSI_CTLx

0x02C0 0180

0x02C0 0184

0x02C0 0188

0x02C0 018C

0x02C0 0190

0x02C0 4180

0x02C0 4184

0x02C0 4188

0x02C0 418C

0x02C0 4190

0x02C0 8180

0x02C0 8184

0x02C0 8188

0x02C0 818C

0x02C0 8190

0x02C0 C180

0x02C0 C184

0x02C0 C188

0x02C0 C18C

0x02C0 C190

0x02C1 0180

0x02C1 0184

0x02C1 0188

0x02C1 018C

0x02C1 0190

TCI Capture Control Register

TSI_CLKINITLx TCI Clock Initialization LSB Register

TSI_CLKINITMx TCI Clock Initialization MSB Register

TSI_STCLKLx

TCI System Time Clock LSB Register

TSI_STCLKMx TCI System Time Clock MSB Register

TCI System Time Clock Compare LSB

0x02C0 0194

0x02C0 0198

0x02C0 019C

0x02C0 01A0

0x02C0 01A4

0x02C0 4194

0x02C0 4198

0x02C0 419C

0x02C0 41A0

0x02C0 41A4

0x02C0 8194

0x02C0 8198

0x02C0 819C

0x02C0 81A0

0x02C0 81A4

0x02C0 C194

0x02C0 C198

0x02C0 C19C

0x02C0 C1A0

0x02C0 C1A4

0x02C1 0194

0x02C1 0198

0x02C1 019C

0x02C1 01A0

0x02C1 01A4

TSI_STCMPLx

Register

TCI System Time Clock Compare MSB

TSI_STCMPMx

Register

TCI System Time Clock Compare Mask

TSI_STMSKLx

LSB Register

TCI System Time Clock Compare Mask

TSI_STMSKMx

MSB Register

TCI System Time Clock Ticks Interrupt

TSI_TICKSx

Register

0x02C0 0200

0x02C0 0204

0x02C0 0208

0x02C0 4200

0x02C0 4204

0x02C0 4208

0x02C0 8200

0x02C0 8204

0x02C0 8208

0x02C0 C200

0x02C0 C204

0x02C0 C208

0x02C1 0200

0x02C1 0204

0x02C1 0208

VD_STATx

VD_CTLx

Video Display Status Register

Video Display Control Register

Video Display Frame Size Register

VD_FRMSZx

Video Display Horizontal Blanking

Register

0x02C0 020C

0x02C0 0210

0x02C0 0214

0x02C0 0218

0x02C0 021C

0x02C0 420C

0x02C0 4210

0x02C0 4214

0x02C0 4218

0x02C0 421C

0x02C0 820C

0x02C0 8210

0x02C0 8214

0x02C0 8218

0x02C0 821C

0x02C0 C20C

0x02C0 C210

0x02C0 C214

0x02C0 C218

0x02C0 C21C

0x02C1 020C

0x02C1 0210

0x02C1 0214

0x02C1 0218

0x02C1 021C

VD_HBLNKx

VD_VBLKS1x

VD_VBLKE1x

VD_VBLKS2x

VD_VBLKE2x

Video Display Field 1 Vertical Blanking

Start Register

Video Display Field 1 Vertical Blanking

End Register

Video Display Field 2 Vertical Blanking

Start Register

Video Display Field 2 Vertical Blanking

End Register

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Table 6-35. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

DESCRIPTION

VP0

VP1

VP2

VP3

VP4

Video Display Field 1 Image Offset

Register

0x02C0 0220

0x02C0 4220

0x02C0 8220

0x02C0 C220

0x02C1 0220

VD_IMGOFF1x

VD_IMGSZ1x

VD_IMGOFF2x

VD_IMGSZ2x

Video Display Field 1 Image Size

Register

0x02C0 0224

0x02C0 0228

0x02C0 022C

0x02C0 4224

0x02C0 4228

0x02C0 422C

0x02C0 8224

0x02C0 8228

0x02C0 822C

0x02C0 C224

0x02C0 C228

0x02C0 C22C

0x02C1 0224

0x02C1 0228

0x02C1 022C

Video Display Field 2 Image Offset

Register

Video Display Field 2 Image Size

Register

0x02C0 0230

0x02C0 0234

0x02C0 0238

0x02C0 4230

0x02C0 4234

0x02C0 4238

0x02C0 8230

0x02C0 8234

0x02C0 8238

0x02C0 C230

0x02C0 C234

0x02C0 C238

0x02C1 0230

0x02C1 0234

0x02C1 0238

VD_FLDT1x

VD_FLDT2x

VD_THRLDx

Video Display Field 1 Timing Register

Video Display Field 2 Timing Register

Video Display Threshold Register

Video Display Horizontal Synchronization

Register

0x02C0 023C

0x02C0 0240

0x02C0 0244

0x02C0 0248

0x02C0 024C

0x02C0 423C

0x02C0 4240

0x02C0 4244

0x02C0 4248

0x02C0 424C

0x02C0 823C

0x02C0 8240

0x02C0 8244

0x02C0 8248

0x02C0 824C

0x02C0 C23C

0x02C0 C240

0x02C0 C244

0x02C0 C248

0x02C0 C24C

0x02C1 023C

0x02C1 0240

0x02C1 0244

0x02C1 0248

0x02C1 024C

VD_HSYNCx

VD_VSYNS1x

VD_VSYNE1x

VD_VSYNS2x

VD_VSYNE2x

Video Display Field 1 Vertical

Synchronization Start Register

Video Display Field 1 Vertical

Synchronization End Register

Video Display Field 2 Vertical

Synchronization Start Register

Video Display Field 2 Vertical

Synchronization End Register

0x02C0 0250

0x02C0 0254

0x02C0 0258

0x02C0 4250

0x02C0 4254

0x02C0 4258

0x02C0 8250

0x02C0 8254

0x02C0 8258

0x02C0 C250

0x02C0 C254

0x02C0 C258

0x02C1 0250

0x02C1 0254

0x02C1 0258

VD_RELOADx Video Display Counter Reload Register

VD_DISPEVTx Video Display Display Event Register

VD_CLIPx

Video Display Clipping Register

Video Display Default Display Value

Register

0x02C0 025C

0x02C0 425C

0x02C0 825C

0x02C0 C25C

0x02C1 025C

VD_DEFVALx

0x02C0 0260

0x02C0 0264

0x02C0 4260

0x02C0 4264

0x02C0 8260

0x02C0 8264

0x02C0 C260

0x02C0 C264

0x02C1 0260

0x02C1 0264

VD_VINTx

VD_FBITx

Video Display Vertical Interrupt Register

Video Display Field Bit Register

Video Display Field 1Vertical Blanking Bit

Register

0x02C0 0268

0x02C0 026C

0x02C0 4268

0x02C0 426C

0x02C0 8268

0x02C0 826C

0x02C0 C268

0x02C0 C26C

0x02C1 0268

0x02C1 026C

VD_VBIT1x

VD_VBIT2x

Video Display Field 2Vertical Blanking Bit

Register

0x5000 0000

0x5000 0020

0x5000 0040

0x5000 0080

0x5000 00A0

0x5000 00C0

0x5200 0000

0x5200 0020

0x5200 0040

0x5200 0080

0x5400 0000

0x5400 0020

0x5400 0040

0x5400 0080

0x5400 00A0

0x5400 00C0

0x5600 0000

0x5600 0020

0x5600 0040

0x5600 0080

0x5800 0000

0x5800 0020

0x5800 0040

0x5800 0080

0x5800 00A0

0x5800 00C0

0x5A00 0000

0x5A00 0020

0x5A00 0040

0x5A00 0080

0x5C00 0000

0x5C00 0020

0x5C00 0040

0x5C00 0080

0x5C00 00A0

0x5C00 00C0

0x5E00 0000

0x5E00 0020

0x5E00 0040

0x5E00 0080

0x6000 0000

0x6000 0020

0x6000 0040

0x6000 0080

0x6000 00A0

0x6000 00C0

0x6200 0000

0x6200 0020

0x6200 0040

0x6200 0080

Y_SRCA

CB_SRCA

CR_SRCA

Y_DSTA

Y FIFO Source Register A

CB FIFO Source Register A

CR FIFO Source Register A

Y FIFO Destination Register A

CB FIFO Destination Register

CR FIFO Destination Register

Y FIFO Source Register B

CB FIFO Source Register b

CR FIFO Source Register B

Y FIFO Destination Register B

CB_DST

CR_DST

Y_SRCB

CB_SRCB

CR_SRCB

Y_DSTB

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6.11.3 Video Port (VP0, VP1, VP2, VP3, VP4) Electrical Data/Timing

6.11.3.1 VCLKIN Timing (Video Capture Mode)

Table 6-36. Timing Requirements for Video Capture Mode for VPxCLKINx⁽¹⁾

(see Figure 6-21)

-720

-900

NO.

UNIT

MIN

12.5

MAX

1

2

3

4

t_c(VKI)

Cycle time, VPxCLKINx

ns

t_w(VKIH)

t_w(VKIL)

t_t(VKI)

Pulse duration, VPxCLKINx high

Pulse duration, VPxCLKINx low

Transition time, VPxCLKINx

5.4

3

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

4

1

2

3

VPxCLKINx

4

Figure 6-21. Video Port Capture VPxCLKINx TIming

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6.11.3.2 Video Data and Control Timing (Video Capture Mode)

Table 6-37. Timing Requirements in Video Capture Mode for Video Data and Control Inputs

(see Figure 6-22)

-720

-900

NO.

UNIT

MIN

2.9

0.5

2.9

0.5

MAX

1

2

3

4

t_{su(VDATV-VKIH)}Setup time, VPxDx valid before VPxCLKINx high

ns

t_{h(VDATV-VKIH)}

t_{su(VCTLV-VKIH)}

t_{h(VCTLV-VKIH)}

Hold time, VPxDx valid after VPxCLKINx high

Setup time, VPxCTLx valid before VPxCLKINx high

Hold time, VPxCTLx valid after VPxCLKINx high

VPxCLKINx

1

3

2

VPxD[19:0] (Input)

VPxCTLx (Input)

4

Figure 6-22. Video Port Capture Data and Control Input Timing

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6.11.3.3 VCLKIN Timing (Video Display Mode)

Table 6-38. Timing Requirements for Video Display Mode for VPxCLKINx⁽¹⁾(see Figure 6-23)

-720

-900

NO.

UNIT

MIN

9

MAX

1

2

3

4

t_c(VKI)

Cycle time, VPxCLKINx

ns

t_w(VKIH)

t_w(VKIL)

t_t(VKI)

Pulse duration, VPxCLKINx high

Pulse duration, VPxCLKINx low

Transition time, VPxCLKINx

4.1

3

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

4

1

2

3

VPxCLKINx

4

Figure 6-23. Video Port Display VPxCLKINx Timing

6.11.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx

and VPxCLKOUTx (Video Display Mode)

Table 6-39. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to

VPxCLKINx and VPxCLKOUTx (see Figure 6-24)

-720

-900

NO.

UNIT

MIN

MAX

13 t_{su(VCTLV-VKIH)}

14 t_{h(VCTLV-VKIH)}

15 t_{su(VCTLV-VKOH)}

16 t_{h(VCTLV-VKOH)}

Setup time, VPxCTLx valid before VPxCLKINx high

Hold time, VPxCTLx valid after VPxCLKINx high

Setup time, VPxCTLx valid before VPxCLKOUTx high⁽¹⁾

Hold time, VPxCTLx valid after VPxCLKOUTx high⁽¹⁾

2.9

0.5

ns

7.4

–0.9

(1) Assuming non-inverted VPxCLKOUTx signal.

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Table 6-40. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode

for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx⁽¹⁾⁽²⁾

(see Figure 6-24)

-720

-900

MIN

V – 0.7

NO.

PARAMETER

Cycle time, VPxCLKOUTx

UNIT

MAX

1

2

3

4

5

6

7

8

9

t_c(VKO)

V + 0.7

ns

t_w(VKOH)

Pulse duration, VPxCLKOUTx high

VH – 0.7 VH + 0.7

VL – 0.7 VL + 0.7

1.8

t_w(VKOL)

Pulse duration, VPxCLKOUTx low

t_t(VKO)

Transition time, VPxCLKOUTx

t_d(VKIH-VKOH)

t_d(VKIL-VKOL)

t_d(VKIH-VKOL)

t_d(VKIL-VKOH)

t_{d(VKIH-VPOUTV)}

Delay time, VPxCLKINx high to VPxCLKOUTx high⁽³⁾

Delay time, VPxCLKINx low to VPxCLKOUTx low⁽³⁾

Delay time, VPxCLKINx high to VPxCLKOUTx low

Delay time, VPxCLKINx low to VPxCLKOUTx high

Delay time, VPxCLKINx high to VPxOUT valid⁽⁴⁾

Delay time, VPxCLKINx high to VPxOUT invalid⁽⁴⁾

Delay time, VPxCLKOUTx high to VPxOUT valid⁽¹⁾⁽⁴⁾

Delay time, VPxCLKOUTx high to VPxOUT invalid⁽¹⁾⁽⁴⁾

1.1

5.7

9

10 t_{d(VKIH-VPOUTIV)}

11 t_{d(VKOH-VPOUTV)}

12 t_{d(VKOH-VPOUTIV)}

1.7

4.3

–0.2

VPxCLKINx

5

2

1

6

8

3

VPxCLKOUTx

[VCLK2P = 0]

4

7

4

VPxCLKOUTx

(Inverted)

[VCLK2P = 1]

12

10

11

9

VPxCTLx,V

PxD[19:0]

(Outputs)

15

16

14

13

VPxCTLx

(Input)

Figure 6-24. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to

VPxCLKINx and VPxCLKOUTx

(1) V = the video input clock (VPxCLKINx) period in ns.

(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.

(3) Assuming non-inverted VPxCLKOUTx signal.

(4) VPxOUT consists of VPxCTLx and VPxD[19:0]

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6.11.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)

Table 6-41. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 6-25)

-720

-900

NO.

UNIT

MIN

MAX

1

t_skr(VKI)

VPxCLKINx

Skew rate, VPxCLKINx before VPyCLKINy

±500

ps

1

VPyCLKINy

Figure 6-25. Video Port Dual-Display Sync Timing

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6.12 VCXO Interpolated Control (VIC)

The VIC can be used in conjunction with the video ports (VPs) to maintain synchronization of a video

stream. The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.

6.12.1 VIC Device-Specific Information

The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from

9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).

Typical D/A converters provide a discrete output level for every value of the digital word that is being

converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A

converter by choosing a few widely spaced output levels and interpolating values between them. The

interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that

the average output represents the value of input code.

In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented

to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is

dependent on the resolution needed.

When the video port is used in transport stream interface (TSI) mode, the VIC port is used to control the

system clock, VCXO, for MPEG transport stream.

The VIC supports the following features:

•

Single interpolation for D/A conversion

Programmable precision from 9-to-16 bits

Interface for register accesses

For more detailed information on the DM642 VCXO interpolated control (VIC) peripheral, see the

TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number

SPRU629).

6.12.2 VIC Peripheral Register Description(s)

Table 6-42. VCXO Interpolated Control (VIC) Port Registers

HEX ADDRESS RANGE

01C4 C000

ACRONYM

VICCTL

VICIN

REGISTER NAME

VIC control register

01C4 C004

VIC input register

VIC clock divider register

Reserved

01C4 C008

VPDIV

–

01C4 C00C – 01C4 FFFF

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6.12.3 VIC Electrical Data/Timing

6.12.3.1 STCLK Timing

Table 6-43. Timing Requirements for STCLK⁽¹⁾(see Figure 6-26)

-720

-900–

NO.

UNIT

MIN MAX

1

2

3

4

t_c(STCLK)

t_w(STCLKH)

t_w(STCLKL)

t_t(STCLK)

Cycle time, STCLK

33.3

16

3

ns

Pulse duration, STCLK high

Pulse duration, STCLK low

Transition time, STCLK

(1) The reference points for the rise and fall transitions are measured at V_ILMAX and V_IHMIN.

4

1

2

3

STCLK

4

Figure 6-26. STCLK Timing

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6.13 Universal Asynchronous Receiver/Transmitter (UART)

The DM647/DM648 devices have a UART peripheral. The UART has the following features:

•

16-byte storage space for both the transmitter and receiver FIFOs

1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA

DMA signaling capability for both received and transmitted data

Programmable auto-rts and auto-cts for autoflow control

Frequency pre-scale values from 1 to 65, 535 to generate appropriate baud rates

Prioritized interrupts

Programmable serial data formats

–

5, 6, 7, or 8-bit characters

Even, odd, or no parity bit generation and detection

1, 1.5, or 2 stop bit generation

•

False start bit detection

Line break generation and detection

Internal diagnostic capabilities

–

Loopback controls for communications link fault isolation

Break, parity, overrun, and framing error simulation

•

Modem control functions (CTS, RTS).

The UART registers are listed in Table 6-44 .

6.13.1 UART Peripheral Register Description(s)

Table 6-44. UART Register Descriptions

HEX ADDRESS RANGE

0x0204 7000

ACRONYM

REGISTER NAME

RBR

UART Receiver Buffer Register (Read Only)

UART Transmitter Holding Register (Write Only)

UART Interrupt Enable Register

UART Interrupt Identification Register (Read Only)

UART FIFO Control Register (Write Only)

UART Line Control Register

UART Modem Control Register

UART Line Status Register

0x0204 7000

THR

0x0204 7004

IER

0x0204 7008

IIR

0x0204 7008

FCR

0x0204 700C

0x0204 7010

LCR

MCR

0x0204 7014

LSR

0x0204 7018

-

Reserved

0x0204 701C

0x0204 7020

-

Reserved

DLL

UART Divisor Latch (LSB)

0x0204 7024

DLH

UART Divisor Latch (MSB)

0x0204 7028

PID1

Peripheral Identification Register 1

Peripheral Identification Register 2

UART Power and Emulation Management Register

Reserved

0x0204 702C

0x0204 7030

PID2

PWREMU_MGMT

-

0x0204 7034 - 0x0204 73FF

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6.13.2 UART Electrical Data/Timing

Table 6-45. Timing Requirements for UARTx Receive⁽¹⁾(see Figure 6-27)

-720

-900

NO.

UNIT

MIN

MAX

1.05U

4

5

t_w(URXDB)

t_w(URXSB)

Pulse duration, receive data bit (RXDn) [15/30/100 pF]

Pulse duration, receive start bit [15/30/100 pF]

0.99U

ns

(1) U = UART baud time = 1/programmed baud rate.

Table 6-46. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit⁽¹⁾

(see Figure 6-27)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

f_(baud)

Maximum programmable baud rate

5

MHz

ns

t_w(UTXDB)

t_w(UTXSB)

Pulse duration, transmit data bit (TXDn) [15/30/100 pF]

Pulse duration, transmit start bit [15/30/100 pF]

U - 2

U + 2

ns

3

2

Start

UART_TXDn

Bit

Data Bits

5

4

Start

Bit

UART_RXDn

Data Bits

Figure 6-27. UART Transmit/Receive Timing

(1) U = UART baud time = 1/programmed baud rate.

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6.14 Inter-Integrated Circuit (I2C)

The inter-integrated circuit (I2C) module provides an interface between DM647/DM648 and other devices

compliant with Philips Semiconductors Inter-IC bus (I²C-bus™) specification version 2.1. External

components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP

through the I2C module. The I2C port does not support CBUS-compatible devices.

The I2C port supports:

•

Compatible with Philips I2C Specification Revision 2.1 (January 2000)

Fast Mode up to 400 Kbps (no fail-safe I/O buffers)

Noise Filter to Remove Noise 50 ns or less

Seven- and Ten-Bit Device Addressing Modes

Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality

Events: DMA, Interrupt, or Polling

Slew-Rate Limited Open-Drain Output Buffers

I2C Module

Clock

Prescale

Peripheral Clock

(DSP/18)

I2CPSC

Control

Bit Clock

Generator

Own

Address

I2COAR

I2CSAR

I2CMDR

I2CCNT

I2CEMDR

SCL

Noise

Filter

I2C Clock

Slave

Address

I2CCLKH

I2CCLKL

Mode

Data

Count

Transmit

I2CXSR

Transmit

Shift

Extended

Mode

Transmit

Buffer

I2CDXR

SDA

Interrupt/DMA

I2CIMR

Noise

Filter

I2C Data

Interrupt

Mask/Status

Receive

I2CDRR

Receive

Buffer

Interrupt

Status

I2CSTR

I2CIVR

Interrupt

Vector

Receive

Shift

I2CRSR

Shading denotes control/status registers.

Figure 6-28. I2C Module Block Diagram

For more detailed information on the I2C peripheral, see the TMS320DM647/DM648 DSP Inter-Integrated

Circuit (I2C) Module User's Guide (literature number SPRUEK8).

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6.14.1 I2C Peripheral Register Description(s)

Table 6-47. I2C Registers

HEX ADDRESS RANGE

0x0204 7C00

0x0204 7C04

0x0204 7C08

0x0204 7C0C

0x0204 7C10

0x0204 7C14

0x0204 7C18

0x0204 7C1C

0x0204 7C20

0x0204 7C24

0x0204 7C28

0x0204 7C2C

0x0204 7C30

0x0204 7C34

ACRONYM

ICOAR

ICIMR

REGISTER NAME

I2C Own Address Register

I2C Interrupt Mask Register

I2C Interrupt Status Register

ICSTR

ICCLKL

ICCLKH

ICCNT

I2C Clock Divider Low Register

I2C Clock Divider High Register

I2C Data Count Register

I2C Data Receive Register

I2C Slave Address Register

I2C Data Transmit Register

I2C Mode Register

ICDRR

ICSAR

ICDXR

ICMDR

ICIVR

I2C Interrupt Vector Register

I2C Extended Mode Register

I2C Prescaler Register

ICEMDR

ICPSC

ICDMAC

I2C DMA Control Register

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6.14.2 I2C Electrical Data/Timing

6.14.2.1 Inter-Integrated Circuits (I2C) Timing

Table 6-48. Timing Requirements for I2C Timings⁽¹⁾(see Figure 6-29)

-720

-900

NO.

STANDARD

MODE

UNIT

FAST MODE

MIN

MAX

MIN

MAX

1

2

t_c(SCL)

Cycle time, SCL

10

2.5

µs

Setup time, SCL high before SDA low (for a repeated START

condition)

t_{su(SCLH-SDAL)}

4.7

4

0.6

Hold time, SCL low after SDA low (for a START and a repeated

START condition)

3

t_h(SCLL-SDAL)

µs

4

5

6

7

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100⁽²⁾

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

t_{su(SDAV-SCLH)}

t_h(SDA-SCLL)

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low

250

0⁽³⁾

0⁽³⁾0.9⁽⁴⁾

Pulse duration, SDA high between STOP and START

conditions

8

t_w(SDAH)

4.7

1.3

µs

(5)

9

t_r(SDA)

Rise time, SDA

1000 20 + 0.1C_b

300 20 + 0.1C_b

300

ns

µs

ns

pF

(5)

10

11

12

13

14

15

t_r(SCL)

Rise time, SCL

t_f(SDA)

Fall time, SDA

t_f(SCL)

Fall time, SCL

t_{su(SCLH-SDAH)}

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4

0.6

0

t_w(SP)

50

(5)

C_b

400

(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(2) A Fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement t_su(SDA-SCLH)≥ 250 ns must then be

met. This will be the case automatically if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line t_rmax + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns

(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4) The maximum t_h(SDA-SCLL)has to be met only if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.

(5) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

11

9

SDA

SCL

6

8

14

4

13

5

10

1

12

3

2

7

3

Stop

Start

Repeated

Start

Stop

Figure 6-29. I2C Receive Timings

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Table 6-49. Switching Characteristics for I2C Timings⁽¹⁾(see Figure 6-30)

-720

-900

NO.

PARAMETER

STANDARD

MODE

UNIT

FAST MODE

MIN MAX

16

17

t_c(SCL)

Cycle time, SCL

10

2.5

µs

Delay time, SCL high to SDA low (for a repeated START

condition)

t_d(SCLH-SDAL)

4.7

4

0.6

Delay time, SDA low to SCL low (for a START and a repeated

START condition)

18

t_d(SDAL-SCLL)

0.6

µs

19

20

21

22

t_w(SCLL)

Pulse duration, SCL low

4.7

4

1.3

0.6

100

0

µs

ns

µs

t_w(SCLH)

Pulse duration, SCL high

t_d(SDAV-SCLH)

t_v(SCLL-SDAV)

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low

250

0

0.9

Pulse duration, SDA high between STOP and START

conditions

23

t_w(SDAH)

4.7

1.3

µs

(1)

24

25

26

27

28

29

t_r(SDA)

t_r(SCL)

Rise time, SDA

1000 20 + 0.1C_b

300

ns

µs

pF

(1)

Rise time, SCL

1000 20 + 0.1C_b

t_f(SDA)

Fall time, SDA

300 20 + 0.1C_b

t_f(SCL)

Fall time, SCL

t_d(SCLH-SDAH)

C_p

Delay time, SCL high to SDA high (for STOP condition)

Capacitance for each I2C pin

4

0.6

10

26

24

SDA

21

23

19

28

20

25

SCL

16

18

27

18

17

22

Stop

Start

Repeated

Start

Stop

Figure 6-30. I2C Transmit Timings

(1) C_b= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

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6.15 Host-Port Interface (HPI) Peripheral

6.15.1 HPI Device-Specific Information

The DM647/DM648 devices include a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32).

The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit

peripheral.

Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the

DM647/DM648.

An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the

EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA

channel 0.

6.15.2 HPI Peripheral Register Description(s)

Table 6-50. HPI Control Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

0x0200 0000

-

Reserved

PWREMU_MGMT has both

host/CPU read/write access.

0x0200 0004

PWREMU_MGMT

HPI power and emulation management register

0x0200 0008 - 0x0200 0024

0x0200 0028

-

Reserved

0x0200 002C

The host and the CPU have

read/write access to the

HPIC register.⁽¹⁾

0x0200 0030

HPIC

HPI control register

HPIA

HPI address register

(Write)

The host has read/write

access to the HPIA registers.

The CPU has only read

0x0200 0034

0x0200 0038

(HPIAW)⁽²⁾

HPIA

HPI address register

(Read)

(HPIAR)⁽²⁾

access to the HPIA registers.

0x0200 000C - 0x0200 007F

0x0200 0080 - 0x0200 FFFF

-

Reserved

(1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an

interrupt from the host.

(2) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that

HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the

perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes,

see theTMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5).

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6.15.3 HPI Electrical Data/Timing

Table 6-51. Timing Requirements for Host-Port Interface Cycles⁽¹⁾⁽²⁾(see Table 6-52 through Figure 6-38)

-720

-900

NO.

UNIT

MIN

MAX

9

t_{su(HASL-HSTBL)}

t_{h(HSTBL-HASL)}

t_{su(SELV-HASL)}

t_h(HASL-SELV)

t_w(HSTBL)

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

Setup time, select signals⁽³⁾valid before HAS low

Hold time, select signals⁽³⁾valid after HAS low

Pulse duration, HSTROBE low

5

2

ns

10

11

12

13

14

15

16

17

18

37

5

2M

5

t_w(HSTBH)

Pulse duration, HSTROBE high between consecutive accesses

Setup time, select signals⁽³⁾valid before HSTROBE low

Hold time, select signals⁽³⁾valid after HSTROBE low

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

Setup time, HCS low before HSTROBE low

t_{su(SELV-HSTBL)}

t_{h(HSTBL-SELV)}

t_{su(HDV-HSTBH)}

t_h(HSTBH-HDV)

t_{su(HCSL-HSTBL)}

5

1

0

Hold time, HSTROBE low after HRDY low. HSTROBE should not be

inactivated until HRDY is active (low); otherwise, HPI writes will not

complete properly.

38

t_{h(HRDYL-HSTBL)}

1.1

ns

(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

(2) M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.

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Table 6-52. Switching Characteristics for Host-Port Interface Cycles⁽¹⁾⁽²⁾

(see Table 6-52 through Figure 6-38)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

Case 1. HPIC or HPIA read

5

15

Case 2. HPID read with no

auto-increment⁽³⁾

9 * M + 20

Delay time, HSTROBE low to

DSP data valid

Case 3. HPID read with auto-increment

and read FIFO initially empty⁽³⁾

1

t_d(HSTBL-HDV)

ns

9 * M + 20

15

Case 4. HPID read with auto-increment

and data previously prefetched into the

read FIFO

5

2

3

4

5

t_{dis(HSTBH-HDV)}

t_en(HSTBL-HD)

t_{d(HSTBL-HRDYH)}

t_{d(HSTBH-HRDYH)}

Disable time, HD high-impedance from HSTROBE high

Enable time, HD driven from HSTROBE low

Delay time, HSTROBE low to HRDY high

Delay time, HSTROBE high to HRDY high

Case 1. HPID read with no

1

3

4

15

12

ns

10 * M + 20

auto-increment⁽³⁾

Delay time, HSTROBE low to

6

t_{d(HSTBL-HRDYL)}

ns

HRDY low

Case 2. HPID read with auto-increment

and read FIFO initially empty⁽³⁾

7

t_d(HDV-HRDYL)

t_d(DSH-HRDYL)

Delay time, HD valid to HRDY low

0

ns

Case 1. HPIA write⁽³⁾

5 * M + 20

Delay time, HSTROBE high to

HRDY low

34

Case 2. HPID write with no

auto-increment⁽³⁾

Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not

empty⁽³⁾

35

36

t_{d(HSTBL-HRDYL)}

t_{d(HASL-HRDYH)}

40 * M + 20

12

ns

Delay time, HAS low to HRDY high

(1) M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.

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HCS

HAS

HCNTL[1:0]

HR/W

HHWIL

13

16

13

16

15

37

14

HSTROBE

HD[15:0]

3

1

2

38

4

7

6

HRDY

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-31. HPI16 Read Timing (HAS Not Used, Tied High)

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HCS

HAS

12

11

12

11

HCNTL[1:0]

12

11

12

11

HR/W

12

11

12

11

HHWIL

10

9

10

9

37

13

37

14

(A)

HSTROBE

1

3

1

3

2

HD[15:0]

7

38

36

6

(B)

HRDY

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-32. HPI16 Read Timing (HAS Used)

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HCS

HAS

HCNTL[1:0]

HR/W

HHWIL

16

13

16

15

37

15

37

13

14

(A)

HSTROBE

18

17

HD[15:0]

34

38

4

34

5

35

5

(B)

HRDY

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-33. HPI16 Write Timing (HAS Not Used, Tied High)

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HCS

HAS

12

11

12

11

HCNTL[1:0]

12

11

12

11

HR/W

12

11

12

11

HHWIL

10

9

10

9

37

13

37

14

(A)

HSTROBE

1

3

1

3

2

HD[15:0]

7

38

36

6

(B)

HRDY

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-34. HPI16 Write Timing (HAS Used)

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HAS (input)

16

15

HCNTL[1:0] (input)

HR/W (input)

13

(A)

HSTROBE (input)

37

HCS (input)

1

2

3

HD[31:0] (output)

38

7

6

4

(B)

HRDY (output)

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-35. HPI32 Read Timing (HAS Not Used, Tied High)

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10

HAS (input)

12

11

HCNTL[1:0] (input)

HR/W (input)

9

13

(A)

HSTROBE

(input)

37

HCS (input)

1

2

3

HD[31:0] (output)

7

38

6

36

(B)

HRDY

(output)

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-36. HPI32 Read Timing (HAS Used)

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HAS (input)

16

15

HCNTL[1:0]

(input)

HR/W (input)

13

(A)

HSTROBE

(input)

37

HCS (input)

18

17

HD[31:0] (input)

38

34

35

5

4

(B)

HRDY (output)

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-37. HPI32 Write Timing (HAS Not Used, Tied High)

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10

HAS (input)

12

11

HCNTL[1:0]

(input)

HR/W (input)

9

13

(A)

HSTROBE

(input)

37

HCS (input)

18

17

HD[31:0] (input)

35

34

38

36

5

(B)

HRDY (output)

A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with

auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed

information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide

(literature number SPRUEL5).

Figure 6-38. HPI32 Write Timing (HAS Used)

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6.16 Peripheral Component Interconnect (PCI)

The DM647/DM648 digital media processors support connections to a PCI backplane via the integrated

PCI master/slave bus interface. The PCI port interfaces to DSP internal resources via the data switched

central resource. .

For more detailed information on the PCI port peripheral module, see the TMS320DM647/DM648

Peripheral Component Interconnect (PCI) User's Guide (literature number SPRUEL4).

6.16.1 PCI Device-Specific Information

The PCI peripheral on the DM64x device DSP conforms to the PCI Local Bus Specification (version 2.3).

The PCI peripheral can act both as a PCI bus master and as a target. It supports PCI bus operation of

speeds up to 66 MHz and uses a 32-bit data/address bus.

On the DM64x device, the pins of the PCI peripheral are multiplexed with the pins of the HPI, and GPIO

peripherals. PCI functionality for these pins is controlled (enabled/disabled) by the UHPIEN pin (H2). The

maximum speed of the PCI, 33 MHz or 66 MHz, is controlled through the PCI66 pin (G5). For more

detailed information on the peripheral control, see Section 3.

The DM64x device provides an initialization mechanism through which the default values for some of the

PCI configuration registers can be read from an I2C EEPROM. Table 6-53 shows the registers which can

be initialized through the PCI auto-initialization. Also shown is the default value of these registers when

PCI auto-initialization is not used. PCI auto-initialization is enabled by selecting PCI boot with

auto-initialization.For more information on this feature, see the TMS320DM647/DM648 Peripheral

Component Interconnect (PCI) User's Guide (literature number SPRUEL4) and the

TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1).

Table 6-53. Default Values for PCI Configuration

Registers

DEFAULT

REGISTER

VALUE

Vendor ID/Device ID Register (PCIVENDEV)

Class Code/Revision ID Register (PCICLREV)

104C B001h

0000 0001h

0000 0000h

Subsystem Vendor ID/Subsystem ID Register

(PCISUBID)

Max Latency/Min Grant/Interrupt Pin/Interrupt Line

Register (PCILGINT)

0000 0100h

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6.16.2 PCI Peripheral Register Description(s)

Table 6-54. PCI Configuration Registers

PCI HOST ACCESS

HEX ADDRESS OFFSET

ACRONYM

PCI HOST ACCESS REGISTER NAME

Vendor ID/Device ID

0x00

0x04

PCIVENDEV

PCICSR

PCICLREV

PCICLINE

PCIBAR0

PCIBAR1

PCIBAR2

PCIBAR3

PCIBAR4

PCIBAR5

-

Command/Status

0x08

Class Code/Revision ID

BIST/Header Type/Latency Timer/Cacheline Size

Base Address 0

0x0C

0x10

0x14

Base Address 1

0x18

Base Address 2

0x1C

Base Address 3

0x20

Base Address 4

0x24

Base Address 5

0x28 - 0x2B

0x2C

Reserved

PCISUBID

-

Subsystem Vendor ID/Subsystem ID

Reserved

0x30

0x34

PCICPBPTR

-

Capabilities Pointer

Reserved

0x38 - 0x3B

0x3C

PCILGINT

-

Max Latency/Min Grant/Interrupt Pin/Interrupt Line

Reserved

0x40 - 0x7F

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Table 6-55. PCI Back End Configuration Registers

DSP ACCESS

ACRONYM

DSP ACCESS REGISTER NAME

HEX ADDRESS RANGE

0x0204 8400 - 0x0204 840F

0x0204 8410

-

Reserved

PCISTATSET

PCISTATCLR

-

PCI Status Set Register

0x0204 8414

PCI Status Clear Register

0x0204 8418 - 0x0204 841F

0x0204 8420

Reserved

PCIHINTSET

PCIHINTCLR

-

PCI Host Interrupt Enable Set Register

PCI Host Interrupt Enable Clear Register

Reserved

0x0204 8424

0x0204 8428 - 0x0204 842F

0x0204 8430

PCIBINTSET

PCIBINTCLR

PCIBCLKMGT

-

PCI Back End Application Interrupt Enable Set Register

PCI Back End Application Interrupt Enable Clear Register

PCI Back End Application Clock Management Register

Reserved

0x0204 8434

0x0204 8438

0x0204 843C - 0x0204 84FF

0x0204 8500

PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register

PCICSRMIR PCI Command/Status Mirror Register

PCICLREVMIR PCI Class Code/Revision ID Mirror Register

0x0204 8504

0x0204 8508

0x0204 850C

PCICLINEMIR

PCIBAR0MSK

PCIBAR1MSK

PCIBAR2MSK

PCIBAR3MSK

PCIBAR4MSK

PCIBAR5MSK

-

PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register

0x0204 8510

PCI Base Address Mask Register 0

PCI Base Address Mask Register 1

PCI Base Address Mask Register 2

PCI Base Address Mask Register 3

PCI Base Address Mask Register 4

PCI Base Address Mask Register 5

Reserved

0x0204 8514

0x0204 8518

0x0204 851C

0x0204 8520

0x0204 8524

0x0204 8528 - 0x0204 852B

0x0204 852C

PCISUBIDMIR

-

PCI Subsystem Vendor ID/Subsystem ID Mirror Register

Reserved

0x0204 8530

0x0204 8534

PCICPBPTRMIR PCI Capabilities Pointer Mirror Register

0x0204 8538 - 0x0204 853B

0x0204 853C

-

Reserved

PCILGINTMIR

-

PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register

Reserved

0x0204 8540 - 0x0204 857F

0x0204 8580

PCISLVCNTL

-

PCI Slave Control Register

0x0204 8584 - 0x0204 85BF

0x0204 85C0

Reserved

PCIBAR0TRL

PCIBAR1TRL

PCIBAR2TRL

PCIBAR3TRL

PCIBAR4TRL

PCIBAR5TRL

-

PCI Slave Base Address 0 Translation Register

PCI Slave Base Address 1 Translation Register

PCI Slave Base Address 2 Translation Register

PCI Slave Base Address 3 Translation Register

PCI Slave Base Address 4 Translation Register

PCI Slave Base Address 5 Translation Register

Reserved

0x0204 85C4

0x0204 85C8

0x0204 85CC

0x0204 85D0

0x0204 85D4

0x0204 85D8 - 0x0204 85DF

0x0204 85E0

PCIBAR0MIR

PCIBAR1MIR

PCIBAR2MIR

PCIBAR3MIR

PCIBAR4MIR

PCIBAR5MIR

-

PCI Base Address Register 0 Mirror Register

PCI Base Address Register 1 Mirror Register

PCI Base Address Register 2 Mirror Register

PCI Base Address Register 3 Mirror Register

PCI Base Address Register 4 Mirror Register

PCI Base Address Register 5 Mirror Register

Reserved

0x0204 85E4

0x0204 85E8

0x0204 85EC

0x0204 85F0

0x0204 85F4

0x0204 85F8 - 0x0204 86FF

0x0204 8700

PCIMCFGDAT PCI Master Configuration/IO Access Data Register

PCIMCFGADR PCI Master Configuration/IO Access Address Register

0x0204 8704

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Table 6-55. PCI Back End Configuration Registers (continued)

DSP ACCESS

HEX ADDRESS RANGE

ACRONYM

DSP ACCESS REGISTER NAME

0x0204 8708

0x0204 870C - 0x0204 870F

0x0204 8710

PCIMCFGCMD PCI Master Configuration/IO Access Command Register

-

Reserved

PCIMSTCFG

PCI Master Configuration Register

Table 6-56. DSP-to_PCI Address Translation Registers

DSP ACCESS

HEX ADDRESS RANGE

ACRONYM

DSP ACCESS REGISTER NAME

0x0204 8714

0x0204 8718

0x0204 871C

0x0204 8720

0x0204 8724

0x0204 8728

0x0204 872C

0x0204 8730

0x0204 8734

0x0204 8738

0x0204 873C

0x0204 8740

0x0204 8744

0x0204 8748

0x0204 874C

0x0204 8750

0x0204 8754

0x0204 8758

0x0204 875C

0x0204 8760

0x0204 8764

0x0204 8768

0x0204 876C

0x0204 8770

0x0204 8774

0x0204 8778

0x0204 877C

0x0204 8780

0x0204 8784

0x0204 8788

0x0204 878C

0x0204 8790

PCIADDSUB0

PCIADDSUB1

PCIADDSUB2

PCIADDSUB3

PCIADDSUB4

PCIADDSUB5

PCIADDSUB6

PCIADDSUB7

PCIADDSUB8

PCIADDSUB9

PCI Address Substitute 0 Register

PCI Address Substitute 1 Register

PCI Address Substitute 2 Register

PCI Address Substitute 3 Register

PCI Address Substitute 4 Register

PCI Address Substitute 5 Register

PCI Address Substitute 6 Register

PCI Address Substitute 7 Register

PCI Address Substitute 8 Register

PCI Address Substitute 9 Register

PCIADDSUB10 PCI Address Substitute 10 Register

PCIADDSUB11 PCI Address Substitute 11 Register

PCIADDSUB12 PCI Address Substitute 12 Register

PCIADDSUB13 PCI Address Substitute 13 Register

PCIADDSUB14 PCI Address Substitute 14 Register

PCIADDSUB15 PCI Address Substitute 15 Register

PCIADDSUB16 PCI Address Substitute 16 Register

PCIADDSUB17 PCI Address Substitute 17 Register

PCIADDSUB18 PCI Address Substitute 18 Register

PCIADDSUB19 PCI Address Substitute 19 Register

PCIADDSUB20 PCI Address Substitute 20 Register

PCIADDSUB21 PCI Address Substitute 21 Register

PCIADDSUB22 PCI Address Substitute 22 Register

PCIADDSUB23 PCI Address Substitute 23 Register

PCIADDSUB24 PCI Address Substitute 24 Register

PCIADDSUB25 PCI Address Substitute 25 Register

PCIADDSUB26 PCI Address Substitute 26 Register

PCIADDSUB27 PCI Address Substitute 27 Register

PCIADDSUB28 PCI Address Substitute 28 Register

PCIADDSUB29 PCI Address Substitute 29 Register

PCIADDSUB30 PCI Address Substitute 30 Register

PCIADDSUB31 PCI Address Substitute 31 Register

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Table 6-57. PCI Hook Configuration Registers

DSP ACCESS

HEX ADDRESS RANGE

ACRONYM

DSP ACCESS REGISTER NAME

0x0204 8794

PCIVENDEVPRG PCI Vendor ID and Device ID Program Register

PCICMDSTATPRG PCI Command and Status Program Register

0x0204 8798

0x0204 879C

0x0204 87A0

0x0204 87A4

0x0204 87A8

0x0204 87AC

0x0204 87B0

0x0204 87B4

0x0204 87B8

0x0204 87BC

0x0204 87C0

0x0204 87C4

0x0204 87C8

0x0204 87CC

0x0204 87D0

0x0204 87D4

0x0204 87D8

0x0204 87DC

0x0204 87E0

0x0204 87E4

0x0204 87E8

0x0204 87EC

0x0204 87F0

0x0204 87F4

0x0204 87F8

0x0204 87FC - 0x0204 87FF

PCICLREVPRG

PCISUBIDPRG

PCI Class Code and Revision ID Program Register

PCI Subsystem Vendor ID and Subsystem ID Program Register

PCIMAXLGPRG PCI Max Latency and Min Grant Program Register

PCILRSTREG

PCICFGDONE

PCI LRESET Register

PCI Configuration Done Register

PCIBAR0MPRG PCI Base Address Mask Register 0 Program Register

PCIBAR1MPRG PCI Base Address Mask Register 1 Program Register

PCIBAR2MPRG PCI Base Address Mask Register 2 Program Register

PCIBAR3MPRG PCI Base Address Mask Register 3 Program Register

PCIBAR4MPRG PCI Base Address Mask Register 4 Program Register

PCIBAR5MPRG PCI Base Address Mask Register 5 Program Register

PCIBAR0PRG

PCIBAR1PRG

PCIBAR2PRG

PCIBAR3PRG

PCIBAR4PRG

PCIBAR5PRG

PCI Base Address Register 0 Program Register

PCI Base Address Register 1 Program Register

PCI Base Address Register 2 Program Register

PCI Base Address Register 3 Program Register

PCI Base Address Register 4 Program Register

PCI Base Address Register 5 Program Register

PCIBAR0TRLPRG PCI Base Address Translation Register 0 Program Register

PCIBAR1TRLPRG PCI Base Address Translation Register 1 Program Register

PCIBAR2TRLPRG PCI Base Address Translation Register 2 Program Register

PCIBAR3TRLPRG PCI Base Address Translation Register 3 Program Register

PCIBAR4TRLPRG PCI Base Address Translation Register 4 Program Register

PCIBAR5TRLPRG PCI Base Address Translation Register 5 Program Register

PCIBASENPRG PCI Base En Prog Register

-

Reserved

Table 6-58. PCI External Memory Space

HEX ADDRESS OFFSET

0x4000 0000 - 0x407F FFFF

0x4080 0000 - 0x40FF FFFF

0x4100 0000 - 0x417F FFFF

0x4180 0000 - 0x41FF FFFF

0x4200 0000 - 0x427F FFFF

0x4280 0000 - 0x42FF FFFF

0x4300 0000 - 0x437F FFFF

0x4380 0000 - 0x43FF FFFF

0x4400 0000 - 0x447F FFFF

0x4480 0000 - 0x44FF FFFF

0x4500 0000 - 0x457F FFFF

0x4580 0000 - 0x45FF FFFF

0x4600 0000 - 0x467F FFFF

0x4680 0000 - 0x46FF FFFF

0x4700 0000 - 0x477F FFFF

ACRONYM

REGISTER NAME

-

PCI Master Window 0

PCI Master Window 1

PCI Master Window 2

PCI Master Window 3

PCI Master Window 4

PCI Master Window 5

PCI Master Window 6

PCI Master Window 7

PCI Master Window 8

PCI Master Window 9

PCI Master Window 10

PCI Master Window 11

PCI Master Window 12

PCI Master Window 13

PCI Master Window 14

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Table 6-58. PCI External Memory Space (continued)

HEX ADDRESS OFFSET

0x4780 0000 - 0x47FF FFFF

0x4800 0000 - 0x487F FFFF

0x4880 0000 - 0x48FF FFFF

0x4900 0000 - 0x497F FFFF

0x4980 0000 - 0x49FF FFFF

0x4A00 0000 - 0x4A7F FFFF

0x4A80 0000 - 0x4AFF FFFF

0x4B00 0000 - 0x4B7F FFFF

0x4B80 0000 - 0x4BFF FFFF

0x4C00 0000 - 0x4C7F FFFF

0x4C80 0000 - 0x4CFF FFFF

0x4D00 0000 - 0x4D7F FFFF

0x4D80 0000 - 0x4DFF FFFF

0x4E00 0000 - 0x4E7F FFFF

0x4E80 0000 - 0x4EFF FFFF

0x4F00 0000 - 0x4F7F FFFF

0x4F80 0000 - 0x4FFF FFFF

ACRONYM

REGISTER NAME

-

PCI Master Window 15

PCI Master Window 16

PCI Master Window 17

PCI Master Window 18

PCI Master Window 19

PCI Master Window 20

PCI Master Window 21

PCI Master Window 22

PCI Master Window 23

PCI Master Window 24

PCI Master Window 25

PCI Master Window 26

PCI Master Window 27

PCI Master Window 28

PCI Master Window 29

PCI Master Window 30

PCI Master Window 31

6.16.3 PCI Electrical Data/Timing

Texas Instruments (TI) has performed the simulation and system characterization to be sure that the PCI

peripheral meets all ac timing specifications as required by the PCI Local Bus Specification (version 2.3).

The ac timing specifications are not reproduced here. For more information on the ac timing specifications,

see Section 4.2.3, Timing Specification (33 MHz timing), and Section 7.6.4, Timing Specification (66 MHz

timing), of the PCI Local Bus Specification (version 2.3). Note that the DM647/DM648 PCI peripheral only

supports 3.3-V signaling.

6.17 Multichannel Audio Serial Port (McASP) Peripheral

The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel

audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated

Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).

6.17.1 McASP Device-Specific Information

The DM647/DM648 devices include one multichannel audio serial port (McASP) interface peripheral

(McASP). The McASP is a serial port optimized for the needs of multichannel audio applications.

The McASP consists of a transmit and receive section. These sections can operate completely

independently with different data formats, separate master clocks, bit clocks, and frame syncs or

alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a

pool of 16 shift registers that may be configured to operate as either transmit data or receive data.

The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)

synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for

S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM

synchronous serial format.

The McASP can support one transmit data format (either a TDM format or DIT format) and one receive

format at a time. All transmit shift registers use the same format and all receive shift registers use the

same format. However, the transmit and receive formats need not be the same.

Both the transmit and receive sections of the McASP also support burst mode which is useful for

non-audio data (for example, passing control information between two DSPs).

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The McASP peripheral has additional capability for flexible clock generation, and error detection/handling,

as well as error management.

For more detailed information on and the functionality of the McASP peripheral, see the

TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide (literature number

SPRUEL1).

6.17.1.1 McASP Block Diagram

Figure 6-39 illustrates the major blocks along with external signals of the TMS320DM648 McASP

peripheral; and shows the 10 serial data [AXR] pins.

McASP

Transmit

DIT

RAM

Frame Sync

Generator

AFSX

T

ransmit

Clock Check

(High-

Transmit

Clock

Generator

AHCLKX

ACLKX

Frequency)

AMUTE

Error

Detect

AMUTEIN

Receive

Clock Check

(High-

Receive

Clock

Generator

AHCLKR

ACLKR

Frequency)

Transmit

Data

Formatter

Receive

Frame Sync

Generator

AFSR

Serializer 0

AXR0[0]

AXR0[1]

AXR0[2]

AXR0[3]

Serializer 1

Serializer 2

Serializer 3

Serializer 9

AXR0[9]

Receive

Data

Formatter

GPIO

Control

Figure 6-39. McASP Configuration

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6.17.1.2 McASP Peripheral Register Description(s)

Table 6-59. McASP Control Registers

HEX ADDRESS RANGE

0x0204 0000

ACRONYM

PID

REGISTER NAME

Peripheral Identification register [Register value: 0x0010 0101]

0x0204 0004

PWRDEMU

–

Power down and emulation management register

Reserved

0x0204 0008

0x0204 000C

0x0204 0010

–

Reserved

PFUNC

PDIR

Pin function register

Pin direction register

Pin data out register

0x0204 0014

0x0204 0018

PDOUT

Pin data in/data set register

Read returns: PDIN

Writes affect: PDSET

0x0204 001C

0x0204 0020

PDIN/PDSET

PDCLR

–

Pin data clear register

0x0204 0024 – 0x0204

0040

Reserved

0x0204 0044

0x0204 0048

0x0204 004C

0x0204 0050

GBLCTL

AMUTE

DLBCTL

DITCTL

Global control register

Mute control register

Digital Loop-back control register

DIT mode control register

0x0204 0054 – 0x0204

005C

–

Reserved

Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset

independently from receive.

0x0204 0060

RGBLCTL

0x0204 0064

0x0204 0068

0x0204 006C

0x0204 0070

0x0204 0074

0x0204 0078

0x0204 007C

0x0204 0080

0x0204 0084

0x0204 0088

RMASK

RFMT

Receiver format UNIT bit mask register

Receive bit stream format register

Receive frame sync control register

Receive clock control register

AFSRCTL

ACLKRCTL

AHCLKRCTL

RTDM

High-frequency receive clock control register

Receive TDM slot 0–31 register

Receiver interrupt control register

Status register – Receiver

RINTCTL

RSTAT

RSLOT

Current receive TDM slot register

Receiver clock check control register

RCLKCHK

0x0204 008C – 0x0204

009C

–

Reserved

Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset

independently from receive.

0x0204 00A0

XGBLCTL

0x0204 00A4

0x0204 00A8

0x0204 00AC

0x0204 00B0

0x0204 00B4

0x0204 00B8

0x0204 00BC

0x0204 00C0

0x0204 00C4

0x0204 00C8

XMASK

XFMT

Transmit format UNIT bit mask register

Transmit bit stream format register

Transmit frame sync control register

Transmit clock control register

AFSXCTL

ACLKXCTL

AHCLKXCTL

XTDM

High-frequency Transmit clock control register

Transmit TDM slot 0–31 register

Transmit interrupt control register

Status register – Transmitter

XINTCTL

XSTAT

XSLOT

Current transmit TDM slot

XCLKCHK

Transmit clock check control register

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Table 6-59. McASP Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

0x0204 00CC – 0x0204

00FC

–

Reserved

0x0204 0100

0x0204 0104

0x0204 0108

0x0204 010C

0x0204 0110

0x0204 0114

0x0204 0118

0x0204 011C

0x0204 0120

0x0204 0124

0x0204 0128

0x0204 012C

0x0204 0130

0x0204 0134

0x0204 0138

0x0204 013C

0x0204 0140

0x0204 0144

0x0204 0148

0x0204 014C

0x0204 0150

0x0204 0154

0x0204 0158

0x0204 015C

DITCSRA0

DITCSRA1

DITCSRA2

DITCSRA3

DITCSRA4

DITCSRA5

DITCSRB0

DITCSRB1

DITCSRB2

DITCSRB3

DITCSRB4

DITCSRB5

DITUDRA0

DITUDRA1

DITUDRA2

DITUDRA3

DITUDRA4

DITUDRA5

DITUDRB0

DITUDRB1

DITUDRB2

DITUDRB3

DITUDRB4

DITUDRB5

Left (even TDM slot) channel status register file

Right (odd TDM slot) channel status register file

Left (even TDM slot) user data register file

Right (odd TDM slot) user data register file

0x0204 0160 – 0x0204

017C

–

Reserved

0x0204 0180

0x0204 0184

0x0204 0188

0x0204 018C

0x0204 0190

0x0204 0194

0x0204 0198

0x0204 019C

0x0204 01A0

0x0204 01A4

SRCTL0

SRCTL1

SRCTL2

SRCTL3

SRCTL4

SRCTL5

SRCTL6

SRCTL7

SRCTL8

SRCTL9

Serializer 0 control register

Serializer 1 control register

Serializer 2 control register

Serializer 3 control register

Serializer 4 control register

Serializer 5 control register

Serializer 6 control register

Serializer 7 control register

Serializer 8 control register

Serializer 9 control register

0x0204 01A8 – 0x0204

01FC

–

Reserved

0x0204 0200

0x0204 0204

0x0204 0208

0x0204 020C

0x0204 0210

0x0204 0214

0x0204 0218

0x0204 021C

XBUF0

XBUF1

XBUF2

XBUF3

XBUF4

XBUF5

XBUF6

XBUF7

Transmit Buffer for Serializer 0

Transmit Buffer for Serializer 1

Transmit Buffer for Serializer 2

Transmit Buffer for Serializer 3

Transmit Buffer for Serializer 4

Transmit Buffer for Serializer 5

Transmit Buffer for Serializer 6

Transmit Buffer for Serializer 7

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Table 6-59. McASP Control Registers (continued)

HEX ADDRESS RANGE

0x0204 021A

ACRONYM

XBUF8

XBUF9

–

REGISTER NAME

Transmit Buffer for Serializer 8

Transmit Buffer for Serializer 9

Reserved

0x0204 0220

0x0204 0224-0x0204 027C

0x0204 0280

RBUF0

RBUF1

RBUF2

RBUF3

RBUF4

RBUF5

RBUF6

RBUF7

RBUF8

RBUF9

–

Receive Buffer for Serializer 0

Receive Buffer for Serializer 1

Receive Buffer for Serializer 2

Receive Buffer for Serializer 3

Receive Buffer for Serializer 4

Receive Buffer for Serializer 5

Receive Buffer for Serializer 6

Receive Buffer for Serializer 7

Receive Buffer for Serializer 8

Receive Buffer for Serializer 9

Reserved

0x0204 0284

0x0204 0288

0x0204 028C

0x0204 0290

0x0204 0294

0x0204 0298

0x0204 029C

0x0204 02A0

0x0204 02A4

0x0204 02A8-0x0204 3FFF

Table 6-60. McASP Data Registers

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

COMMENTS

(Used when RSEL or XSEL

bits = 0 [these bits are located

in the RFMT or XFMT registers,

respectively].)

McASP receive buffers or McASP transmit buffers via the

Peripheral Data Bus.

01D0 1400 – 01D0 17FF

RBUF/XBUF0

6.17.1.3 McASP Electrical Data/Timing

6.17.1.3.1 Multichannel Audio Serial Port (McASP) Timing

Table 6-61. Timing Requirements for McASP (see Figure 6-40 and Figure 6-41)⁽¹⁾

-720

-900

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(AHCKRX)

t_w(AHCKRX)

t_c(CKRX)

Cycle time, AHCLKR/X

20

ns

Pulse duration, AHCLKR/X high or low

Cycle time, ACLKR/X

10

33

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

ACLKR/X int

ACLKR/X ext

t_w(CKRX)

Pulse duration, ACLKR/X high or low

16.5

5

6

7

8

t_su(FRX-CKRX)

t_h(CKRX-FRX)

t_su(AXR-CKRX)

t_h(CKRX-AXR)

Setup time, AFSR/X input valid before ACLKR/X latches data

Hold time, AFSR/X input valid after ACLKR/X latches data

Setup time, AXR input valid before ACLKR/X latches data

Hold time, AXR input valid after ACLKR/X latches data

5

(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

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Table 6-62. Switching Characteristics Over Recommended Operating Conditions for McASP

(see Figure 6-40 and Figure 6-41)⁽¹⁾

-720

-900

NO.

PARAMETER

Cycle time, AHCLKR/X

UNIT

MIN

MAX

9

t_c(AHCKRX)

t_w(AHCKRX)

t_c(CKRX)

20

ns

10

11

12

Pulse duration, AHCLKR/X high or low

Cycle time, ACLKR/X

10

33

ACLKR/X int

ACLKR/X ext

ACLKX int

t_w(CKRX)

Pulse duration, ACLKR/X high or low

16.5

5

13

14

15

t_d(CKRX-FRX)

Delay time, ACLKR/X transmit edge to AFSX/R output valid

Delay time, ACLKX transmit edge to AXR output valid

10

t_d(CKX-AXRV)

ACLKX ext

ACLKR/X int

ACLKR/X ext

Disable time, AXR high impedance following last data bit from

ACLKR/X transmit edge

t_{dis(CKRX-AXRHZ)}

(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

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2

1

2

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

4

3

4

(A)

ACLKR/X (CLKRP = CLKXP = 0)

(B)

ACLKR/X (CLKRP = CLKXP = 1)

6

5

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

8

7

AXR[n] (Data In/Receive)

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

Figure 6-40. McASP Input Timing

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10

9

AHCLKR/X (Falling Edge Polarity)

AHCLKR/X (Rising Edge Polarity)

12

11

12

(A)

ACLKR/X (CLKRP = CLKXP = 1)

(B)

ACLKR/X (CLKRP = CLKXP = 0)

13

AFSR/X (Bit Width, 0 Bit Delay)

AFSR/X (Bit Width, 1 Bit Delay)

AFSR/X (Bit Width, 2 Bit Delay)

AFSR/X (Slot Width, 0 Bit Delay)

AFSR/X (Slot Width, 1 Bit Delay)

AFSR/X (Slot Width, 2 Bit Delay)

AXR[n] (Data Out/Transmit)

13

14

15

A0 A1

A30 A31 B0 B1

B30 B31 C0 C1 C2 C3

C31

A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP

receiver is configured for rising edge (to shift data in).

B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP

receiver is configured for falling edge (to shift data in).

Figure 6-41. McASP Output Timing

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6.18 3-Port Ethernet Switch Subsystem (3PSW)

The Ethernet module controls the flow of packet data between the DM648/DM647 device and two external

Ethernet PHYs (DM648 only) or one external Ethernet PHY (DM647 only), with hardware flow control and

quality-of-service (QOS) support. See Figure 6-42 for a block diagram of the Ethernet module. The

Ethernet Subsystem contains a 3-port gigabit switch, where one port is internally connected to the C64x+

DSP (via the switched central resource) and the other two ports are brought out externally. Each of the

external Ethernet ports support the modes shown in Table 6-63.

Table 6-63. Ethernet Operating Modes

Description

10Base-T

Data Rate

Operating Mode

half- or full-duplex

full-duplex

10 Mbits/second (Mbps)

100 Mbits/second (Mbps)

1000 Mbits/second (Mbps)

100Base-T

1000Base-T

The Ethernet Subsystem provides these functions:

•

Ethernet communication/routing by way of two dedicated 10/100/1000 ports with SGMII interfaces

–

Wire-rate switching (802.1d), non-blocking switch fabric

Four priority levels of QoS TX support (802.1p) in hardware

Programmable interrupt pacing on RX/TX plus interrupt threshold on RX

Supports forwarding frame sizes of 64-2020 bytes

•

Address Lookup

–

1024 total address lookup engine (ALE) entries of VLANs and/or MAC addresses

L2 address lock and L2 filtering support

Multicast/broadcast filtering and forwarding state control

Receive-based or destination-based multicast and broadcast rate limits

MAC address blocking

Source port locking

OUI (Vendor ID) host accept/deny feature

Host controlled time-based aging

MAC authentication (802.1x)

Remapping of priority level of VLAN or ports

Multiple spanning tree support (spanning tree per VLAN)

•

VLAN support

–

802.1Q compliant

•

Auto add port VLAN for untagged frames on ingress

Auto VLAN removal on egress and auto pad to minimum frame size

–

Flow control (IEEE 802.3x)

Programmable priority escalation to specify delivery of lower priority level packets in the event of

over-subscribed TX high priority traffic

–

Host pass CRC mode (enables CRC protection through host)

Write-protect option for Ethernet module registers (3PGSW, CPPI RAM, MDIO, SGMII0, SGMII1,

control)

–

Ethernet statistics:

•

EtherStats and 802.3 Stats RMON statistics gathering (shared)

Programmable statistics interrupt mask when a statistic is above one half its 32-bit value

–

MDIO module for PHY management

SGMII gigabit current mode logic (CML) differential SERializer/DESerializer (SerDes) I/O

receiver/transmitters

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•

Adaptive active equalization for superior data dependent jitter tolerance in the presence of a

lossy channel

•

Loss of signal detector with programmable threshold levels in receive channels

Integrated receiver and transmitter termination

IEEE 802.3 gigabit Ethernet conformant

6.18.1 Ethernet Subsystem Functions

2

Configuration

Registers

Configuration

Bus

Gigabit

MAC 0

SGMII

Port 0

GMII port 0

SGMII 0

3-port

Gigabit

Switch

Host DMA

Controller

2

Peripheral

Bus

Addr Lookup

Engine

REFCLK

2

Buffer

Descriptor

Memory

Gigabit

MAC 1

SGMII

Port 1

SGMII 1^(A)

GMII port 1

DSP

Interrupt

Controller

MII

Serial

Mgmt

Configuration

Bus

MDIO

A. SGMII port 1 is not available on DM647.

Figure 6-42. Ethernet Subsystem Block Diagram

The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the

GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when

an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by

inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

In networking systems, packet transmission and reception are critical tasks. The communications port

programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software

and communications modules. The CPPI block in the DM648/DM647 contains 2048 words of 32-bit buffer

descriptor memory that holds up to 512 buffer descriptors.

After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet

transmit and receive operations.

•

Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head

descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first

packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to

process before sending to the SGMII.

•

Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head

descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the

CPPI protocol.

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DSP writes may be write-protected to the Ethernet Subsystem configuration registers from addresses

0x02D0 0000 – 0x02D0 4FFF (3PGSW, MDIO, SGMII0, SGMII1, control), and the CPPI RAM. The

Ethernet Subsystem setting in the PSC is also write-protected. A specific 32-bit lock code and a 32-bit

unlock code written to ESS_LOCK register will activate or clear this option, respectively.Please see

section Section 3.2.5 and section Section 3.2.8

The 3-port gigabit switch block contains the following functions:

•

3-port gigabit switch: performs packet forwarding and routing functions, one port is internally connected

to the C64x+ DSP and two ports are brought out externally

CPDMA: performs high-speed DMA transfers with RX and TX CPPI buffers in local memory, including

channel setup and channel teardown

GMAC (Gigabit Ethernet MAC):

–

Uses Rx packet FIFO, and a TX packet FIFO to improve data transfer efficiency

Handles processing of Ethernet packet data, frames, and headers

Includes flow control

Provides statistics collection and reporting

•

The address lookup engine (ALE) processes all received packets to determine where (that is, which

packet location) to forward the packet. The ALE uses the incoming packet received port number,

destination address, source address, length/type, and VLAN information to determine how the packet

should be forwarded. The ALE outputs the port mask to the switch fabric that indicates to which packet

the port(s) should be forwarded.

6.18.2 Interrupt Controller and Pacing Interrupts

The interrupt control block selects the interrupts from the 3-port gigabit switch and MDIO modules for

output to the C64x+ DSP. The miscellaneous interrupt is an immediate (non-paced) interrupt selected

from the miscellaneous interrupts (host error level, statistics level, MDIO User [2], MDIO link [2]).

The eight RX interrupts and eight TX interrupts can be paced. The 8 RX threshold interrupts and the

miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that

occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very

high rate, the performance benefit is significant due to minimizing the overhead associated with servicing

each interrupt. Interrupt pacing increases the C64x+ DSP cache hit ratio by minimizing the number of

times that large interrupt service routines are moved to and from the DSP instruction cache.

MDIO

The MDIO module manages the PHY configuration and monitors status. For a list of supported registers

and register fields, see Table 6-65. In 10/100 mode, the GMII_MTXD(7:0) data bus uses only the lower

nibble.

SGMII

The SGMII/SerDes module contains:

•

Gigabit differential current mode logic (CML) receiver/transmitters

An integrated RX/TX PLL to provide the required high-quality/high-speed internal clocks

Phase-interpolator-based clock/data recovery

A bandgap reference for transmitter swing settings

Parallel-to-serial converter

Serial-to-parallel converter

Integrated receiver and transmitter termination

Configuration logic

802.3 auto-negotiation functionality (as defined in Clause 37of the IEEE Specification 802.3).

The SGMII receive interface converts the encoded receive signals from the differential receive input

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terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals.

The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit

output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the

transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as

an error by an error CRC.

NOTE

SGMII1 is pinned out only in the DM648 device. DM647 device has only one SGMII port

(SGMII0).

6.18.3 Peripheral Register Description(s)

Table 6-64 through Table 6-67 list the registers.

Table 6-64. 3-port Gigabit Switch Registers

HEX ADDRESS RANGE

0x02D0 3000

0x02D0 3004

0x02D0 3008

0x02D0 300C

0x02D0 3010

0x02D0 3014

0x02D0 3018

0x02D0 301C

0x02D0 3020

0x02D0 3024

0x02D0 3028

0x02D0 302C

0x02D0 3030

0x02D0 3034

0x02D0 3038

0x02D0 303C

0x02D0 3040

0x02D0 3044

0x02D0 3048

0x02D0 304C

0x02D0 3050

0x02D0 3054

0x02D0 3058

0x02D0 305C

0x02D0 3060

0x02D0 3064

REGISTER NAME

CPSW_Id_Ver

DESCRIPTION

3pGSw ID Version Register

CPSW_Control

CPSW_Soft_Reset

CPSW_Stat_Port_En

CPSW_PTYPE

P0_Max_Blks

3pGSw Switch Control Register

3pGSw Soft Reset Register

3pGSw Statistics Port Enable Register

3pGSw Transmit Priority Type Register

3pGSw Port 0 Maximum FIFO blocks Register

3pGSw Port 0 FIFO Block Usage Count (read only)

3pGSw Port 0 Flow Control Threshold Register

3pGSw Port 0 VLAN Register

P0_BLK_CNT

P0_Flow_Thresh

P0_Port_VLAN

P0_Tx_Pri_Map

GMAC0_Gap_Thresh

GMAC0_SA_LO

GMAC0_SA_HI

P1_Max_Blks

3pGSw Port 0 Tx Header Pri to Switch Pri Mapping Register

3pGSw GMAC0 Short Gap Threshold Register

3pGSw GMAC0 Source Address Low Register

3pGSw GMAC0 Source Address High Register

3pGSw Port 1 Maximum FIFO blocks Register

3pGSw Port 1 FIFO Block Usage Count (read only)

3pGSw Port 1 Flow Control Threshold Register

3pGSw Port 1 VLAN Register

P1_BLK_CNT

P1_Flow_Thresh

P1_Port_VLAN

P1_Tx_Pri_Map

GMAC1_Gap_Thresh

GMAC1_SA_LO

GMAC1_SA_HI

P2_Max_Blks

3pGSw Port 1 Tx Header Priority to Switch Pri Mapping Register

3pGSw GMAC1 Short Gap Threshold Register

3pGSw GMAC1 Source Address Low Register

3pGSw GMAC1 Source Address High Register

3pGSw Port 2 Maximum FIFO blocks Register

3pGSw Port 2 FIFO Block Usage Count (read only)

3pGSw Port 2 Flow Control Threshold Register

3pGSw Port 2 VLAN Register

P2_BLK_CNT

P2_Flow_Thresh

P2_Port_VLAN

P2_Tx_Pri_Map

3pGSw Port 2 Tx (CPDMA RX) Header Priority to Switch Pri Mapping

Register

0x02D0 3068

0x02D0 306C

CPDMA_Tx_Pri_Map

CPDMA_Rx_Ch_Map

3pGSw CPDMA TX (Port 2 Rx) Pkt Priority to Header Priority Mapping

Register

3pGSw CPDMA RX (Port 2 Tx) Switch Priority to DMA channel

Mapping Register

0x02D0 3070 - 0x02D0 307C

0x02D0 3080

Reserved

GMAC0_IDVER

GMAC0_MacControl

GMAC0_MacStatus

GMAC0 ID/Version Register

GMAC0 Mac Control Register

GMAC0 Mac Status Register

0x02D0 3084

0x02D0 3088

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Table 6-64. 3-port Gigabit Switch Registers (continued)

HEX ADDRESS RANGE

0x02D0 308C

REGISTER NAME

GMAC0_Soft_Reset

GMAC0_Rx_Maxlen

GMAC0_BoffTest

GMAC0_Rx_Pause

GMAC0_Tx_Pause

GMAC0_EMControl

GMAC0_Rx_Pri_Map

Reserved

DESCRIPTION

GMAC0 Soft Reset Register

0x02D0 3090

GMAC0 RX Maximum Length Register

GMAC0 Backoff Test Register

GMAC0 Receive Pause Timer Register

GMAC0 Transmit Pause Timer Register

GMAC0 Emulation Control Register

0x02D0 3094

0x02D0 3098

0x02D0 309C

0x02D0 30A0

0x02D0 30A4

GMAC0 Rx Pkt Priority to Header Priority Mapping Register

Reserved

0x02D0 30A8 - 0x02D0 30BC

0x02D0 30C0

GMAC1_IDVER

GMAC1_MacControl

GMAC1_MacStatus

GMAC1_Soft_Reset

GMAC1_Rx_Maxlen

GMAC1_BoffTest

GMAC1_Rx_Pause

GMAC1_Tx_Pause

GMAC1_EMControl

GMAC1_Rx_Pri_Map

Reserved

GMAC1 ID/Version Register

0x02D0 30C4

GMAC1 Mac Control Register

0x02D0 30C8

GMAC1 Mac Status Register

0x02D0 30CC

0x02D0 30D0

GMAC1 Soft Reset Register

GMAC1 RX Maximum Length Register

GMAC1 Backoff Test Register

0x02D0 30D4

0x02D0 30D8

GMAC1 Receive Pause Timer Register

GMAC1 Transmit Pause Timer Register

GMAC1 Emulation Control

0x02D0 30DC

0x02D0 30E0

0x02D0 30E4

GMAC1 Rx Pkt Priority to Header Priority Mapping Register

Reserved

0x02D0 30E8 - 0x02D0 30FC

0x02D0 3100

Tx_IdVer

CPDMA_REGS TX Identification and Version Register

CPDMA_REGS TX Control Register

CPDMA_REGS TX Teardown Register

Reserved

0x02D0 3104

Tx_Control

0x02D0 3108

Tx_Teardown

0x02D0 310C

Reserved

0x02D0 3110

Rx_IdVer

CPDMA_REGS RX Identification and Version Register

CPDMA_REGS RX Control Register

CPDMA_REGS RX Teardown Register

CPDMA_REGS Soft Reset Register

CPDMA_REGS CPDMA Control Register

CPDMA_REGS CPDMA Status Register

CPDMA_REGS Receive Buffer Offset

CPDMA_REGS Emulation Control

0x02D0 3114

Rx_Control

0x02D0 3118

Rx_Teardown

0x02D0 311C

Soft_Reset

0x02D0 3120

DMAControl

0x02D0 3124

DMAStatus

0x02D0 3128

RX_Buffer_Offset

EMControl

0x02D0 312C

0x02D0 3130 - 0x02D0 317C

0x02D0 3180

Reserved

Tx_IntStat_Raw

Tx_IntStat_Masked

Tx_IntMask_Set

Tx_IntMask_Clear

CPDMA_In_Vector

CPDMA_EOI_Vector

Reserved

CPDMA_INT Tx interrupt Status Register (raw value)

CPDMA_INT Tx Interrupt Status Register (masked value)

CPDMA_INT Tx Interrupt Mask Set Register

CPDMA_INT Tx Interrupt Mask Clear Register

CPDMA_INT Input Vector (read only)

CPDMA_INT End Of Interrupt Vector

Reserved

0x02D0 3184

0x02D0 3188

0x02D0 318C

0x02D0 3190

0x02D0 3194

0x02D0 3198 - 0x02D0 319C

0x02D0 31A0

Rx_IntStat_Raw

Rx_IntStat_Masked

Rx_IntMask_Set

Rx_IntMask_Clear

DMA_IntStat_Raw

DMA_IntStat_Masked

DMA_IntMask_Set

DMA_IntMask_Clear

CPDMA_INT Rx Interrupt Status Register (raw value)

CPDMA_INT Rx Interrupt Status Register (masked value)

CPDMA_INT Rx Interrupt Mask Set Register

CPDMA_INT Rx Interrupt Mask Clear Register

CPDMA_INT DMA Interrupt Status Register (raw value)

CPDMA_INT DMA Interrupt Status Register (masked value)

CPDMA_INT DMA Interrupt Mask Set Register

CPDMA_INT DMA Interrupt Mask Clear Register

0x02D0 31A4

0x02D0 31A8

0x02D0 31AC

0x02D0 31B0

0x02D0 31B4

0x02D0 31B8

0x02D0 31BC

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Table 6-64. 3-port Gigabit Switch Registers (continued)

HEX ADDRESS RANGE

0x02D0 31C0

0x02D0 31C4

0x02D0 31C8

0x02D0 31CC

0x02D0 31D0

0x02D0 31D4

0x02D0 31D8

0x02D0 31DC

0x02D0 31E0

0x02D0 31E4

0x02D0 31E8

0x02D0 31EC

0x02D0 31F0

0x02D0 31F4

0x02D0 31F8

0x02D0 31FC

0x02D0 3200

0x02D0 3204

0x02D0 3208

0x02D0 320C

0x02D0 3210

0x02D0 3214

0x02D0 3218

0x02D0 321C

0x02D0 3220

0x02D0 3224

0x02D0 3228

0x02D0 322C

0x02D0 3230

0x02D0 3234

0x02D0 3238

0x02D0 323C

0x02D0 3240

0x02D0 3244

0x02D0 3248

0x02D0 324C

0x02D0 3250

0x02D0 3254

0x02D0 3258

0x02D0 325C

0x02D0 3260

0x02D0 3264

0x02D0 3268

0x02D0 326C

0x02D0 3270

0x02D0 3274

0x02D0 3278

REGISTER NAME

RX0_PendThresh

RX1_PendThresh

RX2_PendThresh

RX3_PendThresh

RX4_PendThresh

RX5_PendThresh

RX6_PendThresh

RX7_PendThresh

RX0_FreeBuffer

RX1_FreeBuffer

RX2_FreeBuffer

RX3_FreeBuffer

RX4_FreeBuffer

RX5_FreeBuffer

RX6_FreeBuffer

RX7_FreeBuffer

Tx0_HDP

DESCRIPTION

CPDMA_INT Receive Threshold Pending Register Channel 0

CPDMA_INT Receive Threshold Pending Register Channel 1

CPDMA_INT Receive Threshold Pending Register Channel 2

CPDMA_INT Receive Threshold Pending Register Channel 3

CPDMA_INT Receive Threshold Pending Register Channel 4

CPDMA_INT Receive Threshold Pending Register Channel 5

CPDMA_INT Receive Threshold Pending Register Channel 6

CPDMA_INT Receive Threshold Pending Register Channel 7

CPDMA_INT Receive Free Buffer Register Channel 0

CPDMA_INT Receive Free Buffer Register Channel 1

CPDMA_INT Receive Free Buffer Register Channel 2

CPDMA_INT Receive Free Buffer Register Channel 3

CPDMA_INT Receive Free Buffer Register Channel 4

CPDMA_INT Receive Free Buffer Register Channel 5

CPDMA_INT Receive Free Buffer Register Channel 6

CPDMA_INT Receive Free Buffer Register Channel 7

CPDMA_STATERAM TX Channel 0 Head Desc Pointer *

CPDMA_STATERAM TX Channel 1 Head Desc Pointer *

CPDMA_STATERAM TX Channel 2 Head Desc Pointer *

CPDMA_STATERAM TX Channel 3 Head Desc Pointer *

CPDMA_STATERAM TX Channel 4 Head Desc Pointer *

CPDMA_STATERAM TX Channel 5 Head Desc Pointer *

CPDMA_STATERAM TX Channel 6 Head Desc Pointer *

CPDMA_STATERAM TX Channel 7 Head Desc Pointer *

CPDMA_STATERAM RX 0 Channel 0 Head Desc Pointer *

CPDMA_STATERAM RX 1 Channel 1 Head Desc Pointer *

CPDMA_STATERAM RX 2 Channel 2 Head Desc Pointer *

CPDMA_STATERAM RX 3 Channel 3 Head Desc Pointer *

CPDMA_STATERAM RX 4 Channel 4 Head Desc Pointer *

CPDMA_STATERAM RX 5 Channel 5 Head Desc Pointer *

CPDMA_STATERAM RX 6 Channel 6 Head Desc Pointer *

CPDMA_STATERAM RX 7 Channel 7 Head Desc Pointer *

CPDMA_STATERAM TX Channel 0 Completion Pointer Register

CPDMA_STATERAM TX Channel 1 Completion Pointer Register *

CPDMA_STATERAM TX Channel 2 Completion Pointer Register *

CPDMA_STATERAM TX Channel 3 Completion Pointer Register *

CPDMA_STATERAM TX Channel 4 Completion Pointer Register *

CPDMA_STATERAM TX Channel 5 Completion Pointer Register *

CPDMA_STATERAM TX Channel 6 Completion Pointer Register *

CPDMA_STATERAM TX Channel 7 Completion Pointer Register *

CPDMA_STATERAM RX Channel 0 Completion Pointer Register *

CPDMA_STATERAM RX Channel 1 Completion Pointer Register *

CPDMA_STATERAM RX Channel 2 Completion Pointer Register *

CPDMA_STATERAM RX Channel 3 Completion Pointer Register *

CPDMA_STATERAM RX Channel 4 Completion Pointer Register *

CPDMA_STATERAM RX Channel 5 Completion Pointer Register *

CPDMA_STATERAM RX Channel 6 Completion Pointer Register *

Tx1_HDP

Tx2_HDP

Tx3_HDP

Tx4_HDP

Tx5_HDP

Tx6_HDP

Tx7_HDP

Rx0_HDP

Rx1_HDP

Rx2_HDP

Rx3_HDP

Rx4_HDP

Rx5_HDP

Rx6_HDP

Rx7_HDP

Tx0_CP

Tx1_CP

Tx2_CP

Tx3_CP

Tx4_CP

Tx5_CP

Tx6_CP

Tx7_CP

Rx0_CP

Rx1_CP

Rx2_CP

Rx3_CP

Rx4_CP

Rx5_CP

Rx6_CP

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Table 6-64. 3-port Gigabit Switch Registers (continued)

HEX ADDRESS RANGE

0x02D0 327C

0x02D0 32C0 - 0x02D0 32FC

0x02D0 3300 - 0x02D0 337C

0x02D0 3380 - 0x02D0 33FC

0x02D0 3400

REGISTER NAME

Rx7_CP

DESCRIPTION

CPDMA_STATERAM RX Channel 7 Completion Pointer Register *

Reserved

RxGoodFrames

RxBroadcastFrames

RxMulticastFrames

RxPauseFrames

RxCRCErrors

3pGSw_STATS Total number of good frames received

3pGSw_STATS Total number of good broadcast frames received

3pGSw_STATS Total number of good multicast frames received

3pGSw_STATS PauseRxFrames

0x02D0 3404

0x02D0 3408

0x02D0 340C

0x02D0 3410

3pGSw_STATS Total number of CRC errors frames received

3pGSw_STATS Total number of alignment/code errors received

3pGSw_STATS Total number of oversized frames received

3pGSw_STATS Total number of jabber frames received

3pGSw_STATS Total number of undersized frames received

3pGSw_STATS RxFragments received

0x02D0 3414

RxAlignCodeErrors

RxOversizedFrames

RxJabberFrames

RxUndersizedFrames

RxFragments

0x02D0 3418

0x02D0 341C

0x02D0 3420

0x02D0 3424

0x02D0 3428

Reserved

Reserved (read as zero)

0x02D0 342C

0x02D0 3430

RxOctets

3pGSw_STATS Total number of received bytes in good frames

3pGSw_STATS GoodTxFrames

0x02D0 3434

TxGoodFrames

0x02D0 3438

TxBroadcastFrames

TxMulticastFrames

TxPauseFrames

TxDeferredFrames

TxCollisionFrames

TxSingleCollFrames

TxMultCollFrames

TxExcessiveCollisions

TxLateCollisions

TxUnderrun

3pGSw_STATS BroadcastTxFrames

3pGSw_STATS MulticastTxFrames

3pGSw_STATS PauseTxFrames

0x02D0 343C

0x02D0 3440

0x02D0 3444

3pGSw_STATS Deferred Frames

0x02D0 3448

3pGSw_STATS Collisions

0x02D0 344C

0x02D0 3450

3pGSw_STATS SingleCollisionTxFrames

3pGSw_STATS MultipleCollisionTxFrames

3pGSw_STATS ExcessiveCollisions

3pGSw_STATS LateCollisions

0x02D0 3454

0x02D0 3458

0x02D0 345C

0x02D0 3460

3pGSw_STATS Transmit Underrun Error

3pGSw_STATS CarrierSenseErrors

3pGSw_STATS TxOctets

TxCarrierSenseErrors

TxOctets

0x02D0 3464

0x02D0 3468

64octetFrames

3pGSw_STATS 64octetFrames

0x02D0 346C

0x02D0 3470

65t127octetFrames

128t255octetFrames

256t511octetFrames

512t1023octetFrames

1024tUPoctetFrames

NetOctets

3pGSw_STATS 65-127octetFrames

3pGSw_STATS 128-255octetFrames

3pGSw_STATS 256-511octetFrames

3pGSw_STATS 512-1023octetFrames

3pGSw_STATS 1023-1518octetFrames

3pGSw_STATS NetOctets

0x02D0 3474

0x02D0 3478

0x02D0 347C

0x02D0 3480

0x02D0 3484

RxSofOverruns

3pGSw_STATS Receive FIFO or DMA Start of Frame Overruns

3pGSw_STATS Receive FIFO or DMA Mid of Frame Overruns

0x02D0 3488

RxMofOverruns

RxDmaOverruns

0x02D0 348C

3pGSw_STATS Receive DMA Start of Frame and Middle of Frame

Overruns

0x02D0 3490 - 0x02D0 34FC

0x02D0 3500

Reserved

ALE_IdVer

Reserved

Address Lookup Engine ID/Version Register

Reserved

0x02D0 3504

0x02D0 3508

ALE_Control

Reserved

Address Lookup Engine Control Register

Reserved

0x02D0 350C

0x02D0 3510

ALE_Prescale

Address Lookup Engine Prescale Register

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Table 6-64. 3-port Gigabit Switch Registers (continued)

HEX ADDRESS RANGE

0x02D0 3514 - 0x02D0 351C

0x02D0 3520

REGISTER NAME

Reserved

DESCRIPTION

Reserved

ALE_TblCtl

Reserved

Address Lookup Engine Table Control

Reserved

0x02D0 3524 - 0x02D0 3530

0x02D0 3534

ALE_TblW2

ALE_TblW1

ALE_TblW0

ALE_PortCtl0

ALE_PortCtl1

ALE_PortCtl2

Reserved

Address Lookup Engine Table Word 2 Register

Address Lookup Engine Table Word 1 Register

Address Lookup Engine Table Word 0 Register

Address Lookup Engine Port 0 Control Register

Address Lookup Engine Port 1 Control Register

Address Lookup Engine Port 2 Control Register

Reserved

0x02D0 3538

0x02D0 353C

0x02D0 3540

0x02D0 3544

0x02D0 3548

0x02D0 354C - 0x02D0 37FF

Table 6-65. 3-port Gigabit Switch Subsystem Registers

HEX ADDRESS RANGE

0x02D0 2000

0x02D0 2004

0x02D0 2008

0x02D0 200C

0x02D0 2010

0x02D0 2014

0x02D0 2018

0x02D0 201C

0x02D0 2020

0x02D0 2024

0x02D0 2028

0x02D0 202C

0x02D0 2030

0x02D0 2034

REGISTER NAME

IdVer

DESCRIPTION

Identification and Version Register

Soft Reset Register

Soft_Reset

EM_Control

Int_Control

Rx_Thresh_En

Rx_En

Emulation Control

Interrupt Control

Receive Threshold Interrupt Enable Register

Receive Interrupt Enable Register

Transmit Interrupt Enable Register

Misc Interrupt Enable Register

Tx_En

Misc_En

Rx_Thresh_Stat

Rx_Stat

Receive Threshold Masked Interrupt Status Register

Receive Interrupt Masked Interrupt Status Register

Transmit Interrupt Masked Interrupt Status Register

Misc Interrupt Masked Interrupt Status Register

Receive Interrupts Per Millisecond

Transmit Interrupts Per Millisecond

Tx_Stat

Misc_Stat

Rx_Imax

Tx_Imax

Table 6-66. SGMII0 Registers

HEX ADDRESS RANGE

0x02D0 4800

REGISTER NAME

IdVer

DESCRIPTION

Identification and Version Register

Soft Reset Register

0x02D0 4804

Soft_Reset

Reserved

0x02D0 4808 - 0x02D0 480C

0x02D0 4810

Reserved

Control

Control Register

0x02D0 4814

Status

Status Register (read only)

Advertised Ability Register

Transmit Next Page Register

Link Partner Advertised Ability (read only)

Link Partner Receive Next Page Register (read only)

Reserved

0x02D0 4818

Mr_Adv_Ability

Mr_Np_Tx

Mr_Lp_Adv_Ability

Mr_Np_Rx

Reserved

0x02D0 481C

0x02D0 4820

0x02D0 4824

0x02D0 4828 - 0x02D0 482C

0x02D0 4830

Reserved

0x02D0 4834

Reserved

0x02D0 4838

Reserved

0x02D0 483C

Reserved

0x02D0 4840

Diag_Clear

Diag_Control

Diagnostics Clear Register

Diagnostics Control Register

0x02D0 4844

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Table 6-66. SGMII0 Registers (continued)

HEX ADDRESS RANGE

0x02D0 4848

REGISTER NAME

Diag_Status

DESCRIPTION

Diagnostics Status Register (read only)

Reserved

0x02D0 484C - 0x02D0 487F

Reserved

Table 6-67. SGMII1 Registers

HEX ADDRESS RANGE

0x02D0 4C00

REGISTER NAME

IdVer

DESCRIPTION

Identification and Version Register

Soft Reset Register

0x02D0 4C04

Soft_Reset

Reserved

0x02D0 4C08 - 0x02D0 4C0C

0x02D0 4C10

Reserved

Control

Control Register

0x02D0 4C14

Status

Status Register (read only)

Advertised Ability Register

Transmit Next Page Register

Link Partner Advertised Ability (read only)

0x02D0 4C18

Mr_Adv_Ability

Mr_Np_Tx

Mr_Lp_Adv_Ability

Mr_Np_Rx

Reserved

0x02D0 4C1C

0x02D0 4C20

0x02D0 4C24

Link Partner Receive Next Page Register (read only)

0x02D0 4C28 - 0x02D0 4C2C

0x02D0 4C30

Reserved

0x02D0 4C34

Reserved

0x02D0 4C38

Reserved

0x02D0 4C3C

Reserved

0x02D0 4C40

Diag_Clear

Diag_Control

Diag_Status

Reserved

Diagnostics Clear Register

Diagnostics Control Register

Diagnostics Status Register (read only)

Reserved

0x02D0 4C44

0x02D0 4C48

0x02D0 4C4C - 0x02D0 4C7F

6.18.4 Ethernet Subsystem Timing

Table 6-68. Ethernet Subsystem Timing Requirements

UNIT

S

PARAMETER

MIN

NOM

MAX

t₀₁

REFCLKP/N period, X4 mode

x 5 mode

2.35

2.82

3.76

4.7

4

5

ns

%

x 6 mode

6

x 8 mode

8

x 10 mode

10

12

12.5

15

30

35

60

x 12 mode

5.65

5.88

7.06

9.41

11.76

40

x 12.5 mode

x 15 mode

x 20 mode

x 25 mode

t₀₂

t₀₃

t₀₄

t₀₅

REFCLKP/N duty cycle

REFCLKP/N rise/fall

PLL Clock Period, x n Mode

PLL power up

700

ps

ns

µs

t_o1/ n

1

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REFCLKP/N Jitter and PLL Loop Bandwidth

Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby

impairing system performance. A good quality, low jitter reference clock is necessary to achieve

compliance with most if not all physical layer standards (see Table 6-69).

Table 6-69. REFCLKP/N Jitter Requirements for Standards Compliance

Standard

Line Rate (Gbps)

Total REFCLKP/N Jitter (within PLL bandwidth)

Gigabit Ethernet

1.25

50 ps pk-pk

6.19 Management Data Input/Output (MDIO)

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to

enumerate all PHY devices in the system. It contains two user access registers to control and monitor up

to two PHYs simultaneously.

The MDIO module implements the 802.3 serial management interface to interrogate and control two

Ethernet PHYs simultaneously using a shared two-wire bus. Figure 6-xx shows a device with two MACs,

each connected to a PHY, being managed by the MII interface module using a shared bus.

6.19.1 MII Management Interface

Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached

to the EMAC, retrieve the negotiation results, and configure required parameters in the EMAC module for

correct operation. The module is designed to allow almost transparent operation of the MDIO interface,

with very little maintenance from the core processor. Only a maximum of two PHYs may be connected at

any given time.

For more detailed information on the MDIO peripheral, see the DM64xxx DMSoC Ethernet Media Access

Controller/Mgmt.Data Input/Output (EMAC/MDIO) Reference Guide (literature number SPRU851). For a

list of supported registers and register fields, see Table 6-70.

6.19.2 MDIO Register Descriptions

Table 6-70. MDIO Registers

HEX ADDRESS RANGE

0x02D0 4000

REGISTER ACRONYM

MDIOVer

DESCRIPTION

Module version register

Module control register

PHY acknowledge status register

PHY link status register

0x02D0 4004

MDIOControl

MDIOAlive

0x02D0 4008

0x02D0 400C

MDIOLink

0x02D0 4010

MDIOLinkIntRaw

Link status change interrupt register (raw

value)

0x02D0 4014

MDIOLinkIntMasked

Link status change interrupt register (masked

value)

0x02D0 4018 - 0x02D0 401C

0x02D0 4020

Reserved

MDIOUserIntRaw

User command complete interrupt register

(raw value)

0x02D0 4024

MDIOUserIntMasked

User command complete interrupt register

(masked value)

0x02D0 4028

MDIOUserIntMaskSet

MDIOUserIntMaskClr

Reserved

User interrupt mask set register

User interrupt mask clear register

0x02D0 402C

0x02D0 4030 - 0x02D0 407C

0x02D0 4080

MDIOUserAccess0

MDIOUserPhySel0

User access register0

0x02D0 4084

User PHY select register0

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Table 6-70. MDIO Registers (continued)

HEX ADDRESS RANGE

0x02D0 4088

REGISTER ACRONYM

MDIOUserAccess1

MDIOUserPhySel1

Reserved

DESCRIPTION

User access register1

0x02D0 408C

User PHY select register1

0x02D0 4090 - 0x02D0 40FF

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6.20 Timers

The DM647/DM648 devices have four 64-bit general-purpose timers of which only Timer 0 and Timer 1

have external input/output. The timers can be used to: time events, count events, generate pulses,

interrupt the CPU, and send synchronization events to the EDMA3 channel controller.

6.20.1 General-Purpose Timers

The DM647/DM648 devices have four general-purpose timers, Timer 0, Timer 1, Timer 2, and Timer 3

each of which can be configured as a general-purpose timer or a watchdog timer. When configured as a

general-purpose timer, each timer can be programmed as a 64-bit timer or as two separate 32-bit timers.

Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx

and TOUTLx are connected to the low counter. The high counter does not have any external device pins.

For more detailed information, see the TMS320DM647DM648 DSP 64-Bit Timer User's Guide (literature

number SPRUEL0).

6.20.2 Timer Peripheral Register Description(s)

Table 6-71. Timer 0 Registers

HEX ADDRESS RANGE

0x0204 4400

ACRONYM

DESCRIPTION

-

Reserved

0x0204 4404

EMUMGT_CLKSPD

Timer 0 Emulation Management/Clock Speed Register

Timer 0 Counter Register 12

Timer 0 Counter Register 34

Timer 0 Period Register 12

Timer 0 Period Register 34

Timer 0 Control Register

0x0204 4410

TIM12

TIM34

PRD12

PRD34

TCR

0x0204 4414

0x0204 4418

0x0204 441C

0x0204 4420

0x0204 4424

TGCR

-

Timer 0 Global Control Register

Reserved

0x0x0204 4428 - 0x0204 44FF

Table 6-72. Timer 1 Registers

HEX ADDRESS RANGE

0x0204 4800

ACRONYM

DESCRIPTION

-

Reserved

0x0204 4804

EMUMGT_CLKSPD

Timer 1 Emulation Management/Clock Speed Register

Timer 1 Counter Register 12

Timer 1 Counter Register 34

Timer 1 Period Register 12

Timer 1 Period Register 34

Timer 1 Control Register

0x0204 4810

TIM12

TIM34

PRD12

PRD34

TCR

0x0204 4814

0x0204 4818

0x0204 481C

0x0204 4820

0x0204 4824

TGCR

-

Timer 1 Global Control Register

Reserved

0x0204 4828 - 0x0204 48FF

Table 6-73. Timer 2 Registers

HEX ADDRESS RANGE

0x0204 4C00

ACRONYM

DESCRIPTION

-

EMUMGT_CLKSPD

TIM12

Reserved

0x0204 4C04

Timer 2 Emulation Management/Clock Speed Register

Timer 2 Counter Register 12

0x0204 4C10

0x0204 4C14

TIM34

Timer 2 Counter Register 34

0x0204 4C18

PRD12

Timer 2 Period Register 12

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Table 6-73. Timer 2 Registers (continued)

HEX ADDRESS RANGE

0x0204 4C1C

ACRONYM

DESCRIPTION

Timer 2 Period Register 34

Timer 2 Control Register

PRD34

TCR

TGCR

-

0x0204 4C20

0x0204 4C24

Timer 2 Global Control Register

Reserved

0x0204 4C28 - 0x0204 4CFF

Table 6-74. Timer 3 Registers

HEX ADDRESS RANGE

0x0204 5000

ACRONYM

DESCRIPTION

-

Reserved

0x0204 5004

EMUMGT_CLKSPD

Timer 3 Emulation Management/Clock Speed Register

Timer 3 Counter Register 12

Timer 3 Counter Register 34

Timer 3 Period Register 12

Timer 3 Period Register 34

Timer 3 Control Register

0x0204 5010

TIM12

TIM34

PRD12

PRD34

TCR

0x0204 5014

0x0204 5018

0x0204 501C

0x0204 5020

0x0204 5024

TGCR

-

Timer 3 Global Control Register

Reserved

0x0204 5000 - 0x0204 50FF

6.20.3 Timer Electrical Data/Timing

Table 6-75. Timing Requirements for Timer Input⁽¹⁾(see Figure 6-43)

-720

-900

NO.

UNIT

MIN

MAX

1

2

t_w(TIMIxH)

t_w(TIMIxL)

Pulse duration, TIMIxH high

Pulse duration, TIMIxL low

12P⁽¹⁾

ns

12P

(1) P = 1/CPU clock frequency in ns.

Table 6-76. Switching Characteristics for Timer Output

over operating free-air temperature range (unless otherwise noted)

-720

-900

NO.

PARAMETER

UNIT

MIN

12P⁽¹⁾

12P

TYP

MAX

3

4

t_w(TIMOxH)

t_w(TIMOxL)

Pulse duration, TIMOxH high

Pulse duration, TIMOxL low

2

1

TINPLx

4

3

TOUTLx

Figure 6-43. Timer Timing

(1) P = 1/CPU clock frequency in ns.

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6.21 VLYNQ Peripheral

6.21.1 VLYNQ Device-Specific Information

The VLYNQ peripheral on the DM647/DM648 devices conforms to the VLYNQ Module Specification

(revision 2.x). By default, the VLYNQ peripheral is initialized with a device ID of 0x22.

6.21.2 VLYNQ Peripheral Register Description(s)

Table 6-77. VLYNQ Registers

HEX ADDRESS RANGE

0x3800 0000

0x3800 0004

0x3800 0008

0x3800 000C

0x3800 0010

0x3800 0014

0x3800 0018

0x3800 001C

0x3800 0020

0x3800 0024

0x3800 0028

0x3800 002C

0x3800 0030

0x3800 0034

0x3800 0038

0x3800 003C

0x3800 0040

0x3800 0044

0x3800 0048

0x3800 004C

0x3800 0050 - 0x3800 005C

0x3800 0060

0x3800 0064

0x3800 0068 - 0x3800 007C

0x3800 0080

0x3800 0084

0x3800 0088

0x3800 008C

0x3800 0090

0x3800 0094

0x3800 0098

0x3800 009C

0x3800 00A0

0x3800 00A4

0x3800 00A8

0x3800 00AC

0x3800 00B0

0x3800 00B4

0x3800 00B8

ACRONYM

-

REGISTER NAME

Reserved

CTRL

VLYNQ Local Control Register

VLYNQ Local Status Register

STAT

INTPRI

INTSTATCLR

INTPENDSET

INTPTR

XAM

VLYNQ Local Interrupt Priority Vector Status/Clear Register

VLYNQ Local Interrupt Status/Clear Register

VLYNQ Local Interrupt Pending/Set Register

VLYNQ Local Interrupt Pointer Register

VLYNQ Local Transmit Address Map

RAMS1

RAMO1

RAMS2

RAMO2

RAMS3

RAMO3

RAMS4

RAMO4

CHIPVER

AUTNGO

MANNGO

NGOSTAT

-

VLYNQ Local Receive Address Map Size 1

VLYNQ Local Receive Address Map Offset 1

VLYNQ Local Receive Address Map Size 2

VLYNQ Local Receive Address Map Offset 2

VLYNQ Local Receive Address Map Size 3

VLYNQ Local Receive Address Map Offset 3

VLYNQ Local Receive Address Map Size 4

VLYNQ Local Receive Address Map Offset 4

VLYNQ Local Chip Version Register

VLYNQ Local Auto Negotiation Register

VLYNQ Local Manual Negotiation Register

VLYNQ Local Negotiation Status Register

Reserved

INTVEC0

INTVEC1

-

VLYNQ Local Interrupt Vector 3 - 0

VLYNQ Local Interrupt Vector 7 - 4

Reserved for future use [Local Interrupt Vectors 8 - 31]

VLYNQ Remote Revision Register

RREVID

RCTRL

RSTAT

RINTPRI

VLYNQ Remote Control Register

VLYNQ Remote Status Register

VLYNQ Remote Interrupt Priority Vector Status/Clear Register

RINTSTATCLR VLYNQ Remote Interrupt Status/Clear Register

RINTPENDSET VLYNQ Remote Interrupt Pending/Set Register

RINTPTR

RXAM

VLYNQ Remote Interrupt Pointer Register

VLYNQ Remote Transmit Address Map

RRAMS1

RRAMO1

RRAMS2

RRAMO2

RRAMS3

RRAMO3

RRAMS4

VLYNQ Remote Receive Address Map Size 1

VLYNQ Remote Receive Address Map Offset 1

VLYNQ Remote Receive Address Map Size 2

VLYNQ Remote Receive Address Map Offset 2

VLYNQ Remote Receive Address Map Size 3

VLYNQ Remote Receive Address Map Offset 3

VLYNQ Remote Receive Address Map Size 4

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Table 6-77. VLYNQ Registers (continued)

HEX ADDRESS RANGE

0x3800 00BC

ACRONYM

RRAMO4

RCHIPVER

RAUTNGO

RMANNGO

RNGOSTAT

-

REGISTER NAME

VLYNQ Remote Receive Address Map Offset 4

VLYNQ Remote Chip Version Register

VLYNQ Remote Auto Negotiation Register

VLYNQ Remote Manual Negotiation Register

VLYNQ Remote Negotiation Status Register

Reserved

0x3800 00C0

0x3800 00C4

0x3800 00C8

0x3800 00CC

0x3800 00D0 - 0x3800 00DC

0x3800 00E0

RINTVEC0

RINTVEC1

-

VLYNQ Remote Interrupt Vector 3 - 0

VYLNQ Remote Interrupt Vector 7 - 4

Reserved for future use [Remote Interrupt Vectors 8 - 31]

0x3800 00E4

0x3800 00E8 - 0x3800 00FC

6.21.3 VLYNQ Electrical Data/Timing

Table 6-78. Timing Requirements for VCLK for VLYNQ (see Figure 6-44)

-720

-900

NO.

UNIT

MIN

MAX

1

2

3

4

t_c(VCLK)

t_w(VCLKH)

t_w(VCLKL)

t_t(VCLK)

Cycle time, VCLK

8

ns

Pulse duration, VCLK high

Pulse duration, VCLK low

Transition time, VCLK

2

1

4

2

VCLK

4

3

Figure 6-44. VCLK Timing for VLYNQ

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Table 6-79. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the

VLYNQ Module (see Figure 6-45)

-720

-900

NO.

PARAMETER

UNIT

MIN

2.25

0.5

MAX

1

2

t_{d(VCLKH-TXDI)}

t_{d(VCLKH-TXDV)}

Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode]

Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode]

Delay time, VCLK to VTXD[3:0] valid

ns

6

Table 6-80. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-45)

-720

-900

NO.

UNIT

MIN

0.2

1.3

0.8

0.4

0.2

0

MAX

RTM disabled

ns

RTM enabled, RXD Flop = 0

RTM enabled, RXD Flop = 1

RTM enabled, RXD Flop = 2

RTM enabled, RXD Flop = 3

RTM enabled, RXD Flop = 4

RTM enabled, RXD Flop = 5

RTM enabled, RXD Flop = 6

RTM enabled, RXD Flop = 7

RTM disabled

Setup time, VRXD[3:0] valid before VCLK

high

3

t_{su(RXDV-VCLKH)}

-0.3

-0.5

-0.7

2

RTM enabled, RXD Flop = 0

RTM enabled, RXD Flop = 1

RTM enabled, RXD Flop = 2

0.5

1.0

1.5

2.0

2.5

3

4

t_{h(VCLKH-RXDV)}

Hold time, VRXD[3:0] valid after VCLK high RTM enabled, RXD Flop = 3

RTM enabled, RXD Flop = 4

RTM enabled, RXD Flop = 5

RTM enabled, RXD Flop = 6

3.5

4

RTM enabled, RXD Flop = 7

1

VCLK

2

VTXD[3:0]

Data

4

3

VRXD[3:0]

Data

Figure 6-45. VLYNQ Transmit/Receive Timing

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6.22 General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register can control the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different

interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.

The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).

The DM647/DM648 GPIO peripheral supports the following:

•

Up to 32 3.3v GPIO pins, GPIO[0:31]

Interrupts:

–

Up to 16 unique GPIO[0:15] interrupts from Bank 0

1 GPIO bank (aggregated) interrupt signal from the GPIOs in Bank 1.

Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO

signal

•

DMA events:

–

Up to 10 unique GPIO DMA events from Bank 0

Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO

signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section

protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to

anther process during GPIO programming).

•

Separate Input/Output registers

Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can

be toggled by direct write to the output register(s).

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status and open-drain I/O cell, allows wired logic be implemented.

The memory map for the GPIO registers is shown in Table 6-81. For more detailed information on GPIOs,

see the TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide (literature

number SPRUEK7).

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6.22.1 GPIO Peripheral Register Description(s)

Table 6-81. GPIO Registers

HEX ADDRESS RANGE

0x0204 8000

ACRONYM

REGISTER NAME

PID

-

Peripheral Identification Register

Reserved

0x0204 8004

0x0204 8008

BINTEN

GPIO interrupt per-bank enable

GPIO Banks 0 and 1

Reserved

0x0204 800C

0x0204 8010

0x0204 8014

0x0204 8018

0x0204 801C

0x0204 8020

0x0204 8024

0x0204 8028

0x0204 802C

0x0204 8030

0x0204 8034

-

DIR01

GPIO Banks 0 and 1 Direction Register (GPIO[0:31])

GPIO Banks 0 and 1 Output Data Register (GPIO[0:31])

GPIO Banks 0 and 1 Set Data Register (GPIO[0:31])

GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GPIO[0:31])

GPIO Banks 0 and 1 Input Data Register (GPIO[0:31])

OUT_DATA01

SET_DATA01

CLR_DATA01

IN_DATA01

SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GPIO[0:31])

CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GPIO[0:31])

SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GPIO[0:31])

CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GPIO[0:31])

INSTAT01

GPIO Banks 0 and 1 Interrupt Status Register (GPIO[0:31])

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6.22.2 GPIO Peripheral Input/Output Electrical Data/Timing

Table 6-82. Timing Requirements for GPIO Inputs⁽¹⁾(see Figure 6-46)

-720

-900

NO.

UNIT

MIN

MAX

1

2

t_w(GPIH)

t_w(GPIL)

Pulse duration, GPIx high

Pulse duration, GPIx low

12P

ns

(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DM647/DM648

recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device

enough time to access the GPIO register through the internal bus. P = 1/CPU clock frequency in ns.

Table 6-83. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs

(see Figure 6-46)

-720

-900

NO.

PARAMETER

Pulse duration, GPOx high

UNIT

MIN

MAX

3

4

t_w(GPOH)

t_w(GPOL)

6P⁽¹⁾

ns

Pulse duration, GPOx low

2

1

GPIx

4

3

GPOx

Figure 6-46. GPIO Port Timing

(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the

GPIO is dependent upon internal bus activity.P = 1/CPU clock frequency in ns.

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6.23 IEEE 1149.1 JTAG

The JTAG⁽²⁾interface is used for BSDL testing and emulation of the DM647/DM648 devices.

TRST needs to be released only when it is necessary to use a JTAG controller to debug the device or

exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by

TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.

For maximum reliability, DM647/DM648 devices include an internal pulldown (IPD) on the TRST pin to

make certain that TRST will always be asserted upon power up and the device's internal emulation logic

will always be properly initialized.

JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG

controllers may not drive TRST high but expect the use of a pullup resistor on TRST.

When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally

drive TRST high before attempting any emulation or boundary scan operations.

(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

6.23.1 JTAG Peripheral Register Description(s) – JTAG ID Register

Table 6-84. JTAG ID Register

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

JTAG Identification Register

COMMENTS

Read-only. Provides 32-bit

JTAG ID of the device.

0x0204 9018

JTAGID

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the

DM647/DM648 devices, the JTAG ID register resides at address location 0x0204 9018. The register hex

value for DM647/DM648 is: 0x0B77 A02F . For the actual register bit names and their associated bit field

descriptions, see Figure 6-47 and Table 6-85.

31-28

27-12

11-1

0

VARIANT (4-Bit)

PART NUMBER (16-Bit)

MANUFACTURER (11-Bit)

LSB

R-0000

R-1011 0111 0111 1010

R-0000 0010 111

R-1

LEGEND: R = Read, W = Write, n = value at reset

Figure 6-47. JTAGID Register (0x0204 9018) Description

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Table 6-85. JTAGID Register Selection Bit Descriptions

BIT

31:28

27:12

11-1

0

NAME

VARIANT

DESCRIPTION

Variant (4-Bit) value. DM647/DM648 value: 0000.

Part Number (16-Bit) value. DM647/DM648 value: 1011 0111 0111 1010.

PART NUMBER

MANUFACTURER Manufacturer (11-Bit) value. DM647/DM648 value: 0000 0010 111.

LSB LSB. This bit is read as a 1 for DM647/DM648.

6.23.2 JTAG Electrical Data/Timing

Table 6-86. Timing Requirements for JTAG Test Port (see Figure 6-48)

-720

-900

NO.

UNIT

MIN

MAX

1

3

4

t_c(TCK)

Cycle time, TCK

10

2

20

ns

t_{su(TDIV-TCKH)}

t_h(TCKH-TDIV)

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

0

Table 6-87. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port

(see Figure 6-48)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

0.25*tc(TC

K)

2

t_d(TCKL-TDOV)

Delay time, TCK low to TDO valid

0

ns

1

TCK

TDO

2

4

3

TDI/TMS/TRST

Figure 6-48. JTAG Test-Port Timing

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TMS320DM647/TMS320DM648

Digital Media Processor

www.ti.com

SPRS372–MAY 2007

7 Mechanical Data

The following table(s) show the thermal resistance characteristics for the ZUT mechanical package.

See Power Application Report.

7.1 Thermal Data for ZUT

Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZUT]

NO.

1

°C/W⁽¹⁾

AIR FLOW (m/s)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case

Junction-to-board

2

3

4

RΘ_JA

Psi_JT

Psi_JB

Junction-to-free air

Junction-to-package top

Junction-to-board

5

7

8

9

11

12

13

(1) The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC

defined 1S2P system and will change based on environment as well as application.

For more information, see these three EIA/JEDEC standards:

•

EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)

EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

•

.

(2) m/s = meters per second

7.1.1 Packaging Information

The following packaging information and addendum reflect the most current data available for the

designated device(s). This data is subject to change without notice and without revision of this document.

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Mechanical Data

165

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型号：	TMS320DM648CUTD7
厂家：	TEXAS INSTRUMENTS
描述：	数字媒体处理器 \| CUT \| 529 \| -40 to 90 时钟外围集成电路
文件：	总166页 (文件大小：1548K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320DM648CUTD7 [TI]

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