TMS320F280037-Q1 [TI]
TMS320F28003x Real-Time Microcontrollers;
| 型号： | TMS320F280037-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F28003x Real-Time Microcontrollers 微控制器 |
| 文件： | 总255页 (文件大小：5821K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
TMS320F28003x Real-Time Microcontrollers
– One Controller Area Network with Flexible
Data-Rate (CAN FD/MCAN) bus port
– Two Serial Peripheral Interface (SPI) ports
– Two UART-compatible Serial Communication
Interface (SCI)
– Two UART-compatible Local Interconnect
Network (LIN) interfaces
– Fast Serial Interface (FSI) with one transmitter
and one receiver (up to 200Mbps)
Analog system
1 Features
•
TMS320C28x 32-bit DSP core at 120 MHz
– IEEE 754 Floating-Point Unit (FPU)
•
Support for Fast Integer Division (FINTDIV)
– Trigonometric Math Unit (TMU)
•
Support for Nonlinear Proportional Integral
Derivative (NLPID) control
– CRC Engine and Instructions (VCRC)
– Ten hardware breakpoints (with ERAD)
Programmable Control Law Accelerator (CLA)
– 120 MHz
– IEEE 754 single-precision floating-point
instructions
•
– Three 4-MSPS, 12-bit Analog-to-Digital
Converters (ADCs)
•
•
•
Up to 23 external channels (includes the two
gpdac outputs)
•
Four integrated Post-Processing Blocks
(PPB) per ADC
– Executes code independently of main CPU
On-chip memory
– Four windowed comparators (CMPSS) with
12-bit reference Digital-to-Analog Converters
(DACs)
– 384KB (192KW) of flash (ECC-protected)
across three independent banks
– 69KB (34.5KW) of RAM (ECC-protected)
– Dual-zone security
•
Digital glitch filters
– Two 12-bit buffered DAC outputs
Enhanced control peripherals
– 16 ePWM channels with eight channels
that have high-resolution capability (150-ps
resolution)
– Secure Boot and JTAG Lock
Clock and system control
•
•
– Two internal 10-MHz oscillators
– Crystal oscillator or external clock input
– Windowed watchdog timer module
– Missing clock detection circuitry
– Dual-clock Comparator (DCC)
3.3-V I/O design
– Internal VREG generation allows for single-
supply design
– Brownout reset (BOR) circuit
System peripherals
•
•
Integrated dead-band support
Integrated hardware trip zones (TZs)
– Three Enhanced Capture (eCAP) modules
•
•
•
High-resolution Capture (HRCAP) available
on one of the three eCAP modules
– Two Enhanced Quadrature Encoder Pulse
(eQEP) modules with support for CW/CCW
operation modes
– Eight Sigma-Delta Filter Module (SDFM) input
channels (two parallel filters per channel)
– 6-channel Direct Memory Access (DMA)
controller
– 55 individually programmable multiplexed
General-Purpose Input/Output (GPIO) pins
– 23 digital inputs on analog pins
– 2 digital inputs/outputs on analog pins (AGPIO)
– Enhanced Peripheral Interrupt Expansion
(ePIE)
– Multiple low-power mode (LPM) support
– Embedded Real-time Analysis and Diagnostic
(ERAD)
•
•
Standard SDFM data filtering
Comparator filter for fast action for
overvalue or undervalue condition
– Embedded Pattern Generator (EPG)
Configurable Logic Block (CLB)
– 4 tiles
– Augments existing peripheral capability
– Supports position manager solutions
Host Interface Controller (HIC)
•
•
– Unique Identification (UID) number
Communications peripherals
– One Power-Management Bus (PMBus)
•
– Access to internal memory from an external
host
interface
•
•
Background CRC (BGCRC)
– One cycle CRC computation on 32 bits of data
Advanced Encryption Standard (AES) accelerator
– Two Inter-integrated Circuit (I2C) interfaces
– One Controller Area Network (CAN/DCAN) bus
port
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
•
•
•
Live Firmware Update (LFU)
– Fast context switching from old to new firmware
– Flash bank erase time improvements
Diagnostic features
– Memory Power On Self Test (MPOST)
– Hardware Built-in Self Test (HWBIST)
Package options:
– 100-pin Low-profile Quad Flatpack (LQFP)
[PZ suffix]
– 80-pin Low-profile Quad Flatpack (LQFP)
[PN suffix]
•
•
Industrial power
– Industrial AC-DC
UPS
– Three phase UPS
– Single phase online UPS
Telecom & server power
– Merchant DC/DC
– Merchant network & server PSU
– Merchant telecom rectifiers
Hybrids, electric & powertrain systems
– DC/DC converter
•
•
– 64-pin (LQFP) [PM suffix]
– 48-pin (LQFP) [PT suffix]
Temperature options:
– Free-air (TA): –40°C to 125°C
– Junction (TJ): –40°C to 150°C
– Inverter & motor control
– On-board (OBC) & wireless charger
– Virtual engine sound system (VESS)
– Engine fan
•
– eTurbo/charger
– Pump
2 Applications
– Electric power steering (EPS)
Infotainment and cluster
– Head-up display
– Automotive head unit
– Automotive external amplifier
Body electronics & lighting
– Automotive HVAC compressor module
– DC/AC inverter
•
•
•
Appliances
– Air conditioner outdoor unit
Building automation
– Door operator drive control
Industrial machine & machine tools
– Automated sorting equipment
– Textile machine
•
•
– Headlight
ADAS
•
AC inverter & VF drives
•
•
– AC drive control module
– AC drive position feedback
– AC drive power stage module
Linear motor transport systems
– Linear motor power stage
Single & multi axis servo drives
– Servo drive position feedback
– Servo drive power stage module
Speed controlled BLDC drives
– AC-input BLDC motor drive
– DC-input BLDC motor drive
Factory automation
– Mechanically scanning LIDAR
EV charging infrastructure
– AC charging (pile) station
– DC charging (pile) station
– EV charging station power module
– Wireless EV charging station
Renewable energy storage
– Energy storage power conversion system
(PCS)
Solar energy
•
•
•
•
•
•
– Central inverter
– Micro inverter
– Robot servo drive
– Solar power optimizer
– Solar arc protection
– Rapid shutdown
– String inverter
– Mobile robot motor control
– Position sensor
3 Description
The TMS320F28003x (F28003x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-
low latency devices designed for efficiency in power electronics, including but not limited to: high power density,
high switching frequencies, and supporting the use of GaN and SiC technologies.
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
These include such applications as:
•
•
•
•
•
•
Industrial motor drives
Motor control
Solar inverters
Digital power
Electrical vehicles and transportation
Sensing and signal processing
The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 120 MHz of signal-
processing performance for floating- or fixed-point code running from either on-chip flash or SRAM. The
C28x CPU is further boosted by the Floating-Point Unit (FPU), Trigonometric Math Unit (TMU), and VCRC
(Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control
systems.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The F28003x supports up to 384KB (192KW) of flash memory divided into three 128KB (64KW) banks, which
enable programming and execution in parallel. Up to 69KB (34.5KW) of on-chip SRAM is also available to
supplement the flash memory.
The Live Firmware Update hardware enhancements on F28003x allow fast context switching from the old
firmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28003x real-time microcontroller (MCU) and are closely
coupled with the processing and PWM units to provide optimal real-time signal chain performance. Sixteen PWM
channels, all supporting frequency-independent resolution modes, enable control of various power stages from a
3-phase inverter to power factor correction and advanced multi-level power topologies.
The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate
FPGA-like functions into the C2000 real-time MCU.
Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,
LIN, CAN and CAN FD) and offers multiple pin-muxing options for optimal signal placement. The Fast Serial
Interface (FSI) enables up to 200 Mbps of robust communications across an isolation boundary.
New to the C2000 platform is the Host Interface Controller (HIC), a high-throughput interface that allows an
external host to access the resources of the TMS320F28003x directly.
Want to learn more about features that make C2000 Real-Time MCUs the right choice for your real-time control
system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the
C2000™ real-time control MCUs page.
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all
aspects of development with C2000 devices from hardware to support resources. In addition to key reference
documents, each section provides relevant links and resources to further expand on the information covered.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Ready to get started? Check out the F28003x evaluation board (coming soon) and download C2000Ware.
Device Information
CONTROL LAW
ACCELERATOR (CLA) LOGIC BLOCK (CLB)
CONFIGURABLE
PART NUMBER(1)
FLASH SIZE
TMS320F280039C-Q1,
TMS320F280039C
Yes
Yes
4 Tiles
–
TMS320F280039-Q1,
TMS320F280039
384KB
TMS320F280038C-Q1
TMS320F280038-Q1
Yes
Yes
4 Tiles
–
TMS320F280037C-Q1,
TMS320F280037C
Yes
Yes
4 Tiles
–
TMS320F280037-Q1,
TMS320F280037
256KB
TMS320F280036C-Q1
TMS320F280036-Q1
Yes
Yes
Yes
4 Tiles
–
TMS320F280034-Q1,
TMS320F280034
–
–
128KB
128KB
TMS320F280033
No
(1) For more information on these devices, see the Device Comparison table.
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
3.1 Functional Block Diagram
The Functional Block Diagram shows the CPU system and associated peripherals.
Buses Legend
CPU
CLA
DMA
HIC
BGCRC
C28x CPU
(120MHz)
FPU32
TMU
CLA
(120MHz)
VCRC
FINTDIV
SYSTEM CONTROL
CLA to CPU MSG RAM
CPU to CLA MSG RAM
CPU Timers
XTAL
Boot ROM
Secure ROM
INTOSC1, INTOSC2
PLL
ePIE
Windowed WD
NMI WD
Flash Bank0
16 Sectors, 64Kw(128KB)
CLA Data ROM
CLA Program ROM
Flash Bank1
16 Sectors, 64Kw(128KB)
SECURITY
DCSM
JTAG Lock
Secure Boot
CLA to DMA MSG RAM
DMA to CLA MSG RAM
Flash Bank2
16 Sectors, 64Kw(128KB)
M0-M1 RAM
2Kw(4KB)
DIAGNOSTICS
DCC
MPOST
HWBIST
ERAD
JTAG/cJTAG
BGCRC
HIC
LS0-LS7 RAM
16Kw(32KB)
GS0-GS3 RAM
16Kw(32KB)
DMA
6 Channels
OTHERS
EPG
PF10
PF11
PF12
LFU
PF1
PF3
PF4
PF2
PF7 PF7
PF8
PF9
2x LIN(A)
1x AES
1x PMBUS
2x SPI
1x FSI RX
1x FSI TX
2x SCI
2x I2C
4x CLB
Result
3x 12-Bit ADC
Data
55x GPIO
16x ePWM
(8 Hi-Res Capable)
1x
DCAN/ MCAN/
CAN CAN FD
1x
4x CMPSS
2x Bu ered DAC
Input XBAR
Output XBAR
ePWM XBAR
CLB XBAR
3x eCAP
(1 HRCAP Capable)
2x eQEP
(CW/CCW Support)
CLB Input XBAR
CLB Output XBAR
8x SD Filters
A. The LIN module can also work as an SCI.
Figure 3-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................5
Revision History................................................................. 6
4 Device Comparison.........................................................7
4.1 Related Products........................................................ 9
5 Pin Configuration and Functions.................................10
5.1 Pin Diagrams............................................................ 10
5.2 Pin Attributes.............................................................15
5.3 Signal Descriptions................................................... 37
5.4 Pin Multiplexing.........................................................61
5.5 Pins With Internal Pullup and Pulldown.................... 69
5.6 Connections for Unused Pins................................... 70
6 Specifications................................................................ 72
6.1 Absolute Maximum Ratings...................................... 72
6.2 ESD Ratings – Commercial...................................... 72
6.3 ESD Ratings – Automotive....................................... 73
6.4 Recommended Operating Conditions.......................73
6.5 Power Consumption Summary................................. 74
6.6 Electrical Characteristics...........................................80
6.7 Thermal Resistance Characteristics for PZ
Package...................................................................... 81
6.8 Thermal Resistance Characteristics for PN
Package...................................................................... 82
6.9 Thermal Resistance Characteristics for PM
Package...................................................................... 83
6.10 Thermal Resistance Characteristics for PT
Package...................................................................... 84
6.11 Thermal Design Considerations..............................84
6.12 System....................................................................85
6.13 Analog Peripherals................................................126
6.14 Control Peripherals............................................... 156
6.15 Communications Peripherals................................171
7 Detailed Description....................................................206
7.1 Overview.................................................................206
7.2 Functional Block Diagram.......................................207
7.3 Memory...................................................................208
7.4 Identification............................................................216
7.5 Bus Architecture – Peripheral Connectivity.............217
7.6 C28x Processor...................................................... 218
7.7 Control Law Accelerator (CLA)............................... 220
7.8 Embedded Real-Time Analysis and Diagnostic
(ERAD)......................................................................222
7.9 Background CRC-32 (BGCRC).............................. 222
7.10 Direct Memory Access (DMA)...............................223
7.11 Device Boot Modes...............................................224
7.12 Dual Code Security Module.................................. 232
7.13 Watchdog..............................................................233
7.14 C28x Timers..........................................................234
7.15 Dual-Clock Comparator (DCC)............................. 234
7.16 Configurable Logic Block (CLB)............................236
8 Applications, Implementation, and Layout............... 238
8.1 TI Reference Design...............................................238
9 Device and Documentation Support..........................239
9.1 Getting Started and Next Steps.............................. 239
9.2 Device Nomenclature..............................................239
9.3 Markings................................................................. 240
9.4 Tools and Software................................................. 241
9.5 Documentation Support.......................................... 243
9.6 Support Resources................................................. 244
9.7 Trademarks.............................................................245
9.8 Electrostatic Discharge Caution..............................245
9.9 Glossary..................................................................245
10 Mechanical, Packaging, and Orderable
Information.................................................................. 246
Revision History
DATE
REVISION
NOTES
October 2021
*
Initial Release
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
4 Device Comparison
Table 4-1 lists the features of the TMS320F28003x devices.
Table 4-1. Device Comparison
F280039C
F280037C
F280039C-Q1 F280038C-Q1 F280037C-Q1 F280036C-Q1
F280034
F280034-Q1
FEATURE(1)
F280033
F280039
F280038-Q1
F280037
F280036-Q1
F280039-Q1
F280037-Q1
Processor and Accelerators
C28x
Frequency (MHz)
120
FPU
Yes (instructions for Fast Integer Division)
VCRC
Yes
TMU
Yes – Type 1 (instructions supporting NLPID)
CLA – Type 2
Available
Frequency (MHz)
Yes
120
Yes
5
No
–
6-Channel DMA – Type 0
External interrupts
Memory
384KB (192KW)
3 x 128KB
Flash
256KB (128KW)
2 x 128KB
128KB (64KW)
2 x 64KB
Flash Banks
RAM
Dedicated
Local Shared
Message
4KB (2KW)
32KB (16KW)
1KB (0.5KW)
32KB (16KW)
69KB (34.5KW)
Global Shared
Total
Message RAM Types
512B (256W) CPU-CLA
512B (256W) CLA-DMA
–
ECC
FLASH, Mx, LSx, GSx, Message RAM
FLASH, Mx,
LSx, GSx
Parity
ROM, CAN RAM
Yes
Code security for on-chip flash and RAM
System
4 Tiles on C Variants
Configurable Logic Block (CLB)
Embedded Pattern Generator (EPG)
32-bit CPU timers
–
Yes
3
Advance Encryption Standard (AES)
Background CRC (BGCRC)
Live Firmware Update (LFU) Support
Secure Boot
Yes
Yes
Yes, with enhancements and flash bank erase time improvements
Yes
Yes
Yes
1
JTAG Lock
HWBIST
Nonmaskable Interrupt Watchdog (NMIWD) timers
Watchdog timers
1
Crystal oscillator/External clock input
Internal oscillator
1
2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
F280033
SPRSP61 – OCTOBER 2021
Table 4-1. Device Comparison (continued)
F280039C
F280037C
F280039C-Q1 F280038C-Q1 F280037C-Q1 F280036C-Q1
F280039
F280034
F280034-Q1
FEATURE(1)
F280038-Q1
F280037
F280036-Q1
F280039-Q1
F280037-Q1
Pins and Power Supply
Internal 3.3-V to 1.2-V Voltage VREG LDO
Regulator
Yes
GPIO pins
100-pin PZ
80-pin PN
51
39
26
–
–
–
51
39
26
14
–
–
51
39
26
14
64-pin PM
25
–
25
–
48-pin PT
Additional GPIO
4 (2 from cJTAG and 2 from X1/X2)
AIO (analog with digital inputs) 100-pin PZ
23
16
16
–
–
–
23
16
16
14
2
–
–
23
16
16
14
2
80-pin PN
64-pin PM
48-pin PT
16
–
16
–
AGPIO (analog with digital
inputs and outputs)
100-pin PZ
80-pin PN
2
–
–
2
–
2
–
2
Analog Peripherals
ADC 12-bit
Number of ADCs
MSPS
3
4
Conversion Time (ns)(2)
100-pin PZ
250
ADC channels (single-ended)
(includes the two gpdac
outputs)
23
–
–
23
18
16
14
–
–
23
18
16
14
80-pin PN
18
16
–
64-pin PM
16
–
16
–
48-pin PT
Temperature sensor
Buffered DAC
CMPSS
1
2
4
(each CMPSS has two comparators and two internal DACs)
Control Peripherals (3)
eCAP/HRCAP modules – Type 2
ePWM/HRPWM channels – Type 4
eQEP modules – Type 2
3 (1 - eCAP3 with HRCAP capability)
16 (8 - ePWM1 to ePWM4 with HRPWM capability)
2
8
SDFM channels – Type 2
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 4-1. Device Comparison (continued)
F280039C
F280037C
F280039C-Q1 F280038C-Q1 F280037C-Q1 F280036C-Q1
F280034
F280034-Q1
FEATURE(1)
F280033
F280039
F280038-Q1
F280037
F280036-Q1
F280039-Q1
F280037-Q1
Communication Peripherals (3)
CAN (DCAN) – Type 0
1
1
CANFD (MCAN) – Type 1
Fast Serial Interface (FSI) – Type 2
I2C – Type 1
1 (1 RX and 1 TX)
2
2
1
1
2
2
LIN – Type 1 (UART-Compatible)
Host Interface Controller (HIC) – Type 1
PMBus – Type 0
SCI – Type 0 (UART-Compatible)
SPI – Type 2
Package Options, Temperature, and Qualification
–40°C to 150°C
–40°C to 125°C
F280037C
Junction temperature (TJ)
Free-Air temperature (TA)
Package Options
100-pin PZ
F280039C
F280039
–
–
–
–
–
–
–
–
–
–
F280034
F280034
F280034
F280034
–
F280033
F280037
80-pin PN
64-pin PM
48-pin PT
100-pin PZ
64-pin PM
48-pin PT
F280039C
F280039
F280037C
F280037
F280033
F280039C
F280039
F280037C
F280037
F280033
–
F280037C
F280037
F280033
Package Options with AEC-
Q100 Qualification available
F280039C-Q1
F280039-Q1
F280037C-Q1
F280037-Q1
–
–
–
–
F280038C-Q1
F280038-Q1
–
F280036C-Q1
F280036-Q1
–
–
–
F280037C-Q1
F280037-Q1
–
F280034-Q1
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module.
(2) Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
(3) For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the
smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared
to the largest package offered within a part number. See Section 5 to identify which peripheral instances are accessible on pins in the
smaller package.
4.1 Related Products
TMS320F2803x Real-Time Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2807x Real-Time Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Real-Time Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
TMS320F28002x Real-Time Microcontrollers
The F28002x series is a reduced version of the F28004x series with the latest generational enhancements.
TMS320F2838x Real-Time Microcontrollers
The F2838x series offers more performance, larger pin counts, flash memory sizes, peripheral and wide variety
of connectivity options. The F2838x series includes the latest generation of accelerators, ePWM peripherals, and
analog technology.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
5 Pin Configuration and Functions
5.1 Pin Diagrams
Figure 5-1 shows the pin assignments on the 100-pin PZ low-profile quad flatpack; the Q and non-Q variant have
the same pinout. Figure 5-2 shows the pin assignments on the 80-pin PN low-profile quad flatpack. Figure 5-3
shows the pin assignments on the 64-pin PM low-profile quad flatpack (Q temperature). Figure 5-4 shows the pin
assignments on the 64-pin PM low-profile quad flatpack. Figure 5-5 shows the pin assignments on the 48-Pin PT
low-profile quad flatpack; the Q and non-Q variant have the same pinout.
GPIO28
XRSn
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GPIO4
2
GPIO8
VDDIO
3
VREGENZ
VSS
VDD
4
VSS
5
VDD
GPIO47
6
VDDIO
GPIO48
7
GPIO19,X1
GPIO18,X2
GPIO58
GPIO57
GPIO56
GPIO32
GPIO35/TDI
TMS
GPIO49
8
GPIO50
9
GPIO51
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GPIO52
GPIO53
GPIO54
A6
B2,C6
GPIO37/TDO
TCK
B3,VDAC
A2,B6,C9
A3,B9,C7
A14,B14,C4
A11,B10,C0
B12,C2
GPIO27
GPIO26
GPIO25
GPIO24
GPIO17
GPIO16
GPIO33
GPIO11
GPIO12
A1,B7,DACB_OUT
A0,B15,C15,DACA_OUT
VREFHI
VREFHI
Not to scale
A. Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-1. 100-Pin PZ Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
GPIO30
GPIO31
GPIO29
GPIO28
XRSn
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
GPIO3
2
GPIO4
3
GPIO8
4
GPIO42
GPIO39
VSS
5
GPIO46
VDDIO
VDD
6
7
GPIO43
VDD
8
VSS
9
VDDIO
A6
10
11
12
13
14
15
16
17
18
19
20
GPIO19,X1
GPIO18,X2
GPIO32
GPIO35/TDI
TMS
B2,C6
A3,B3,C5,VDAC
A2,B6,C9
A15,B9,C7
A14,B14,C4
GPIO37/TDO
TCK
A11,B10,C0
A5,B12,C2
GPIO27
GPIO26
GPIO25
GPIO24
A1,B7,DACB_OUT
A0,B15,C15,DACA_OUT
VREFHI
Not to scale
A. Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-2. 80-Pin PN Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
GPIO29
GPIO28
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIO4
2
GPIO8
XRSn
3
VREGENZ
VSS
VDD
4
VSS
5
VDD
A6
6
VDDIO
B2,C6
7
GPIO19,X1
GPIO18,X2
GPIO32
GPIO35/TDI
TMS
A3,B3,C5,VDAC
A2,B6,C9
8
9
A15,B9,C7
A14,B14,C4
A11,B10,C0
A5,B12,C2
A1,B7,DACB_OUT
A0,B15,C15,DACA_OUT
VREFHI
10
11
12
13
14
15
16
GPIO37/TDO
TCK
GPIO24
GPIO17
GPIO16
Not to scale
A. Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-3. 64-Pin PM Low-Profile Quad Flatpack - Q Temperature (Top View)
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
GPIO29
GPIO28
XRSn
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GPIO4
2
GPIO8
3
GPIO39
VSS
4
VSS
5
VDD
A6
6
VDDIO
B2,C6
7
GPIO19,X1
GPIO18,X2
GPIO32
GPIO35/TDI
TMS
A3,B3,C5,VDAC
A2,B6,C9
8
9
A15,B9,C7
10
11
12
13
14
15
16
A14,B14,C4
A11,B10,C0
GPIO37/TDO
TCK
A5,B12,C2
A1,B7,DACB_OUT
A0,B15,C15,DACA_OUT
VREFHI
GPIO24
GPIO17
GPIO16
Not to scale
A. Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-4. 64-Pin PM Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
GPIO29
GPIO28
1
36
35
34
33
32
31
30
29
28
27
26
25
VDD
2
VDDIO
XRSn
3
GPIO19,X1
GPIO18,X2
GPIO32
A6,B2,C6
4
A3,B3,C5,VDAC
A2,B6,C9
5
6
GPIO35/TDI
TMS
A15,B9,C7
7
A11,B10,C0
8
GPIO37/TDO
TCK
A5,B12,C2
9
A1,B7,DACB_OUT
A0,B15,C15,DACA_OUT
VREFHI
10
11
12
GPIO24
GPIO16
GPIO33
Not to scale
A. Only the GPIO function is shown on GPIO pins. See Section 5.2 for the complete, muxed signal name.
Figure 5-5. 48-Pin PT Low-Profile Quad Flatpack (Top View)
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.2 Pin Attributes
Table 5-1. Pin Attributes
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
ANALOG
A0
I
I
ADC-A Input 0
B15
ADC-B Input 15
C15
I
ADC-C Input 15
DACA_OUT
CMP3_HP2
CMP3_LP2
AIO231
O
I
Buffered DAC-A Output.
23
19
15
15
11
CMPSS-3 High Comparator Positive Input 2
CMPSS-3 Low Comparator Positive Input 2
Analog Pin Used For Digital Input 231
SDFM-1 Channel 1 Clock Input
HIC Base address range select 1
ADC-A Input 1
I
0, 4, 8, 12
I
SD1_C1
HIC_BASESEL1
A1
2
I
15
I
I
B7
I
ADC-B Input 7
DACB_OUT
CMP1_HP4
CMP1_LP4
AIO232
O
I
Buffered DAC-B Output.
CMPSS-1 High Comparator Positive Input 4
CMPSS-1 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 232
SDFM-1 Channel 4 Data Input
HIC Base address range select 0
ADC-A Input 10
22
18
14
14
10
I
0, 4, 8, 12
I
SD1_D4
HIC_BASESEL0
A10
2
I
15
I
I
B1
I
ADC-B Input 1
C10
I
ADC-C Input 10
CMP2_HP3
CMP2_HN0
CMP2_LP3
CMP2_LN0
AIO230
I
CMPSS-2 High Comparator Positive Input 3
CMPSS-2 High Comparator Negative Input 0
CMPSS-2 Low Comparator Positive Input 3
CMPSS-2 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 230
SDFM-1 Channel 4 Clock Input
HIC Base address range select 2
ADC-A Input 11
I
40
29
25
25
21
I
I
0, 4, 8, 12
I
SD1_C4
HIC_BASESEL2
A11
2
I
15
I
I
B10
I
ADC-B Input 10
C0
I
ADC-C Input 0
CMP1_HP1
CMP1_HN1
CMP1_LP1
CMP1_LN1
AIO237
I
CMPSS-1 High Comparator Positive Input 1
CMPSS-1 High Comparator Negative Input 1
CMPSS-1 Low Comparator Positive Input 1
CMPSS-1 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 237
SDFM-1 Channel 2 Data Input
HIC Address 6
I
20
16
12
12
8
I
I
0, 4, 8, 12
I
SD1_D2
HIC_A6
2
I
15
I
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
A12
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-A Input 12
CMP2_HP1
CMP2_HN1
CMP2_LP1
CMP2_LN1
AIO238
SD2_C3
HIC_NCS
A14
CMPSS-2 High Comparator Positive Input 1
CMPSS-2 High Comparator Negative Input 1
CMPSS-2 Low Comparator Positive Input 1
CMPSS-2 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 238
SDFM-2 Channel 3 Clock Input
HIC Chip select input
28
19
17
22
15
13
18
11
9
18
11
9
14
0, 4, 8, 12
2
15
ADC-A Input 14
B14
ADC-B Input 14
C4
ADC-C Input 4
CMP3_HP4
CMP3_LP4
AIO239
SD1_D1
HIC_A5
A2
CMPSS-3 High Comparator Positive Input 4
CMPSS-3 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 239
SDFM-1 Channel 1 Data Input
HIC Address 5
0, 4, 8, 12
2
15
ADC-A Input 2
B6
ADC-B Input 6
C9
ADC-C Input 9
CMP1_HP0
CMP1_LP0
AIO224
SD2_D3
HIC_A3
A3
CMPSS-1 High Comparator Positive Input 0
CMPSS-1 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 224
SDFM-2 Channel 3 Data Input
HIC Address 3
6
0, 4, 8, 12
2
15
ADC-A Input 3
CMP3_HP5
CMP3_LP5
AIO229
A4
CMPSS-3 High Comparator Positive Input 5
CMPSS-3 Low Comparator Positive Input 5
Analog Pin Used For Digital Input 229
ADC-A Input 4
18
36
0, 4, 8, 12
B8
ADC-B Input 8
CMP2_HP0
CMP2_LP0
AIO225
SD2_C2
HIC_NWE
A5
CMPSS-2 High Comparator Positive Input 0
CMPSS-2 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 225
SDFM-2 Channel 2 Clock Input
HIC Data Write enable from host
ADC-A Input 5
27
23
23
19
0, 4, 8, 12
2
15
CMP2_HP5
CMP2_LP5
AIO249
A6
CMPSS-2 High Comparator Positive Input 5
CMPSS-2 Low Comparator Positive Input 5
Analog Pin Used For Digital Input 249
ADC-A Input 6
35
14
0, 4, 8, 12
CMP1_HP2
CMP1_LP2
AIO228
SD2_C1
HIC_A0
CMPSS-1 High Comparator Positive Input 2
CMPSS-1 Low Comparator Positive Input 2
Analog Pin Used For Digital Input 228
SDFM-2 Channel 1 Clock Input
HIC Address 0
10
6
6
4
0, 4, 8, 12
2
15
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
A8
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-A Input 8
CMP4_HP4
CMP4_LP4
AIO240
CMPSS-4 High Comparator Positive Input 4
CMPSS-4 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 240
SDFM-2 Channel 1 Clock Input
HIC Byte enable 1
37
0, 4, 8, 12
SD2_C1
HIC_NBE1
A9
2
15
ADC-A Input 9
CMP2_HP2
CMP2_LP2
AIO227
CMPSS-2 High Comparator Positive Input 2
CMPSS-2 Low Comparator Positive Input 2
Analog Pin Used For Digital Input 227
SDFM-1 Channel 3 Clock Input
HIC Byte enable 0
38
28
24
24
20
0, 4, 8, 12
SD1_C3
HIC_NBE0
B0
2
15
ADC-B Input 0
C11
ADC-C Input 11
CMP2_HP4
CMP2_LP4
AIO253
41
30
CMPSS-2 High Comparator Positive Input 4
CMPSS-2 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 253
ADC-B Input 11
0, 4, 8, 12
0, 4, 8, 12
B11
CMP4_HP5
CMP4_LP5
AIO251
CMPSS-4 High Comparator Positive Input 5
CMPSS-4 Low Comparator Positive Input 5
Analog Pin Used For Digital Input 251
ADC-B Input 11
B11
CMP4_HP5
CMP4_LP5
CMPSS-4 High Comparator Positive Input 5
CMPSS-4 Low Comparator Positive Input 5
49
34
General-Purpose Input Output 21. This pin
also has digital mux functions which are
described in the DIGITAL section of this table.
GPIO21 (See GPIO
Section)
0, 4, 8, 12
I/O
B2
I
I
I
I
I
I
I
I
ADC-B Input 2
C6
ADC-C Input 6
CMP3_HP0
CMP3_LP0
AIO226
SD2_D4
HIC_A1
B3
CMPSS-3 High Comparator Positive Input 0
CMPSS-3 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 226
SDFM-2 Channel 4 Data Input
HIC Address 1
15
11
7
7
4
0, 4, 8, 12
2
15
ADC-B Input 3
Optional external reference voltage for on-chip
DACs.
VDAC
I
CMP3_HP3
CMP3_HN0
CMP3_LP3
CMP3_LN0
AIO242
I
I
I
I
I
I
I
CMPSS-3 High Comparator Positive Input 3
CMPSS-3 High Comparator Negative Input 0
CMPSS-3 Low Comparator Positive Input 3
CMPSS-3 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 242
SDFM-2 Channel 2 Data Input
16
12
8
8
5
0, 4, 8, 12
SD2_D2
2
HIC_A2
15
HIC Address 2
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
B4
C8
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-B Input 4
ADC-C Input 8
CMP4_HP0
CMP4_LP0
AIO236
39
32
28
24
24
20
CMPSS-4 High Comparator Positive Input 0
CMPSS-4 Low Comparator Positive Input 0
Analog Pin Used For Digital Input 236
ADC-B Input 5
0, 4, 8, 12
B5
CMP1_HP5
CMP1_LP5
AIO252
CMPSS-1 High Comparator Positive Input 5
CMPSS-1 Low Comparator Positive Input 5
Analog Pin Used For Digital Input 252
SDFM-2 Channel 4 Clock Input
0, 4, 8, 12
2
SD2_C4
B5
ADC-B Input 5
CMP1_HP5
CMP1_LP5
CMPSS-1 High Comparator Positive Input 5
CMPSS-1 Low Comparator Positive Input 5
48
29
33
22
General-Purpose Input Output 20. This pin
also has digital mux functions which are
described in the DIGITAL section of this table.
GPIO20 (See GPIO
Section)
0, 4, 8, 12
I/O
C1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
ADC-C Input 1
CMP4_HP2
CMP4_LP2
AIO248
CMPSS-4 High Comparator Positive Input 2
CMPSS-4 Low Comparator Positive Input 2
Analog Pin Used For Digital Input 248
ADC-C Input 14
18
18
14
0, 4, 8, 12
C14
CMP4_HP3
CMP4_HN0
CMP4_LP3
CMP4_LN0
AIO247
CMPSS-4 High Comparator Positive Input 3
CMPSS-4 High Comparator Negative Input 0
CMPSS-4 Low Comparator Positive Input 3
CMPSS-4 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 247
ADC-C Input 2
42
0, 4, 8, 12
C2
B12
ADC-B Input 12
CMP3_HP1
CMP3_HN1
CMP3_LP1
CMP3_LN1
AIO244
CMPSS-3 High Comparator Positive Input 1
CMPSS-3 High Comparator Negative Input 1
CMPSS-3 Low Comparator Positive Input 1
CMPSS-3 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 244
SDFM-1 Channel 3 Data Input
21
17
13
13
9
0, 4, 8, 12
SD1_D3
HIC_A7
2
15
HIC Address 7
C3
ADC-C Input 3
A7
ADC-A Input 7
CMP4_HP1
CMP4_HN1
CMP4_LP1
CMP4_LN1
AIO245
CMPSS-4 High Comparator Positive Input 1
CMPSS-4 High Comparator Negative Input 1
CMPSS-4 Low Comparator Positive Input 1
CMPSS-4 Low Comparator Negative Input 1
Analog Pin Used For Digital Input 245
SDFM-1 Channel 2 Clock Input
HIC Output enable for data bus
ADC-C Input 5
31
28
23
12
19
19
15
0, 4, 8, 12
SD1_C2
HIC_NOE
C5
2
15
8
8
5
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
C7
B9
I
I
ADC-C Input 7
18
14
10
10
7
ADC-B Input 9
ADC High Reference. In external reference
mode, externally drive the high reference
voltage onto this pin. In internal reference
mode, a voltage is driven onto this pin by the
device. In either mode, place at least a 2.2-µF
capacitor on this pin. This capacitor should
be placed as close to the device as possible
between the VREFHI and VREFLO pins.
VREFHI
25
27
20
21
16
17
16
17
12
13
I
VREFLO
A15
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC Low Reference
ADC-A Input 15
CMP1_HP3
CMP1_HN0
CMP1_LP3
CMP1_LN0
AIO233
CMPSS-1 High Comparator Positive Input 3
CMPSS-1 High Comparator Negative Input 0
CMPSS-1 Low Comparator Positive Input 3
CMPSS-1 Low Comparator Negative Input 0
Analog Pin Used For Digital Input 233
SDFM-2 Channel 1 Data Input
HIC Address 4
14
10
10
7
0, 4, 8, 12
SD2_D1
HIC_A4
2
15
A3
ADC-A Input 3
CMP3_HP5
CMP3_LP5
A5
12
17
8
8
5
9
CMPSS-3 High Comparator Positive Input 5
CMPSS-3 Low Comparator Positive Input 5
ADC-A Input 5
CMP2_HP5
CMP2_LP5
A8
13
13
CMPSS-2 High Comparator Positive Input 5
CMPSS-2 Low Comparator Positive Input 5
ADC-A Input 8
CMP4_HP4
CMP4_LP4
AIO241
CMPSS-4 High Comparator Positive Input 4
CMPSS-4 Low Comparator Positive Input 4
Analog Pin Used For Digital Input 241
SDFM-2 Channel 1 Clock Input
HIC Byte enable 1
24
20
20
16
0, 4, 8, 12
SD2_C1
HIC_NBE1
B0
2
15
ADC-B Input 0
C11
ADC-C Input 11
24
27
20
23
20
23
16
19
CMP2_HP4
CMP2_LP4
C14
CMPSS-2 High Comparator Positive Input 4
CMPSS-2 Low Comparator Positive Input 4
ADC-C Input 14
CMP4_HP3
CMP4_HN0
CMP4_LP3
CMP4_LN0
CMPSS-4 High Comparator Positive Input 3
CMPSS-4 High Comparator Negative Input 0
CMPSS-4 Low Comparator Positive Input 3
CMPSS-4 Low Comparator Negative Input 0
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO
GPIO0
0, 4, 8, 12
I/O
O
General-Purpose Input Output 0
ePWM-1 Output A
EPWM1_A
1
I2CA_SDA
6
I/OD I2C-A Open-Drain Bidirectional Data
SPIA_STE
7
I/O
I
SPI-A Slave Transmit Enable (STE)
FSIRX-A Input Clock
FSIRXA_CLK
MCAN_RX
9
79
63
52
52
42
10
I
CAN/CAN FD Receive
CLB Output X-BAR Output 8
eQEP-1 Index
CLB_OUTPUTXBAR8
EQEP1_INDEX
HIC_D7
11
O
13
I/O
I/O
I
14
HIC Data 7
HIC_BASESEL1
GPIO1
15
HIC Base address range select 1
General-Purpose Input Output 1
ePWM-1 Output B
0, 4, 8, 12
I/O
O
EPWM1_B
1
6
I2CA_SCL
I/OD I2C-A Open-Drain Bidirectional Clock
SPIA_SOMI
MCAN_TX
7
I/O
O
O
I
SPI-A Slave Out, Master In (SOMI)
CAN/CAN FD Transmit
CLB Output X-BAR Output 7
HIC Address 2
10
11
13
78
62
51
51
41
CLB_OUTPUTXBAR7
HIC_A2
FSITX-A Time Division Multiplexed Additional
Data Input
FSITXA_TDM_D1
14
I
HIC_D10
15
I/O
I/O
O
HIC Data 10
GPIO2
0, 4, 8, 12
General-Purpose Input Output 2
ePWM-2 Output A
EPWM2_A
OUTPUTXBAR1
PMBUSA_SDA
SPIA_SIMO
SCIA_TX
1
5
O
Output X-BAR Output 1
6
I/OD PMBus-A Open-Drain Bidirectional Data
7
I/O
O
I
SPI-A Slave In, Master Out (SIMO)
SCI-A Transmit Data
9
77
61
50
50
40
FSIRXA_D1
I2CB_SDA
HIC_A1
10
FSIRX-A Optional Additional Data Input
11
I/OD I2C-B Open-Drain Bidirectional Data
13
I
HIC Address 1
CANA_TX
HIC_D9
14
O
CAN-A Transmit
15
I/O
I/O
O
HIC Data 9
GPIO3
0, 4, 8, 12
General-Purpose Input Output 3
ePWM-2 Output B
Output X-BAR Output 2
EPWM2_B
OUTPUTXBAR2
PMBUSA_SCL
SPIA_CLK
SCIA_RX
1
2, 5
6
O
I/OD PMBus-A Open-Drain Bidirectional Clock
7
I/O
SPI-A Clock
9
76
60
49
49
39
I
I
SCI-A Receive Data
FSIRX-A Primary Data Input
FSIRXA_D0
I2CB_SCL
HIC_NOE
CANA_RX
HIC_D4
10
11
13
14
15
I/OD I2C-B Open-Drain Bidirectional Clock
O
I
HIC Output enable for data bus
CAN-A Receive
I/O
HIC Data 4
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO4
0, 4, 8, 12
I/O
O
O
O
O
I/O
I/O
I
General-Purpose Input Output 4
ePWM-3 Output A
EPWM3_A
1
MCAN_TX
3
CAN/CAN FD Transmit
Output X-BAR Output 3
CAN-A Transmit
OUTPUTXBAR3
CANA_TX
5
6
SPIB_CLK
7
75
59
48
48
38
SPI-B Clock
EQEP2_STROBE
FSIRXA_CLK
CLB_OUTPUTXBAR6
HIC_BASESEL2
HIC_NWE
9
eQEP-2 Strobe
10
FSIRX-A Input Clock
11
O
I
CLB Output X-BAR Output 6
HIC Base address range select 2
HIC Data Write enable from host
General-Purpose Input Output 5
ePWM-3 Output B
13
15
I
GPIO5
0, 4, 8, 12
I/O
O
O
I
EPWM3_B
1
OUTPUTXBAR3
MCAN_RX
3
Output X-BAR Output 3
CAN/CAN FD Receive
CAN-A Receive
5
CANA_RX
6
I
SPIA_STE
7
89
74
61
61
47
I/O
O
O
I
SPI-A Slave Transmit Enable (STE)
FSITX-A Optional Additional Data Output
CLB Output X-BAR Output 5
HIC Address 7
FSITXA_D1
CLB_OUTPUTXBAR5
HIC_A7
9
10
13
HIC_D4
14
I/O
I/O
I/O
O
O
O
I
HIC Data 4
HIC_D15
15
HIC Data 15
GPIO6
0, 4, 8, 12
General-Purpose Input Output 6
ePWM-4 Output A
EPWM4_A
1
OUTPUTXBAR4
SYNCOUT
2
Output X-BAR Output 4
External ePWM Synchronization Pulse
eQEP-1 Input A
3
EQEP1_A
5
SPIB_SOMI
FSITXA_D0
FSITXA_D1
HIC_NBE1
7
97
80
64
64
48
I/O
O
O
I
SPI-B Slave Out, Master In (SOMI)
FSITX-A Primary Data Output
FSITX-A Optional Additional Data Output
HIC Byte enable 1
9
11
13
CLB_OUTPUTXBAR8
HIC_D14
14
O
I/O
I/O
O
O
I
CLB Output X-BAR Output 8
HIC Data 14
15
GPIO7
0, 4, 8, 12
General-Purpose Input Output 7
ePWM-4 Output B
EPWM4_B
1
3
OUTPUTXBAR5
EQEP1_B
Output X-BAR Output 5
eQEP-1 Input B
5
SPIB_SIMO
FSITXA_CLK
CLB_OUTPUTXBAR2
HIC_A6
7
84
68
57
57
43
I/O
O
O
I
SPI-B Slave In, Master Out (SIMO)
FSITX-A Output Clock
CLB Output X-BAR Output 2
HIC Address 6
9
10
13
15
HIC_D14
I/O
HIC Data 14
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
GPIO8
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 8
ePWM-5 Output A
EPWM5_A
1
ADCSOCAO
EQEP1_STROBE
SCIA_TX
3
O
ADC Start of Conversion A for External ADC
eQEP-1 Strobe
5
I/O
O
6
SCI-A Transmit Data
SPIA_SIMO
I2CA_SCL
7
I/O
SPI-A Slave In, Master Out (SIMO)
74
90
93
58
75
76
47
62
63
47
62
63
9
I/OD I2C-A Open-Drain Bidirectional Clock
FSITXA_D1
CLB_OUTPUTXBAR5
HIC_A0
10
O
O
I
FSITX-A Optional Additional Data Output
CLB Output X-BAR Output 5
HIC Address 0
11
13
FSITXA_TDM_CLK
HIC_D8
14
I
FSITX-A Time Division Multiplexed Clock Input
HIC Data 8
15
I/O
I/O
O
O
O
I/O
I
GPIO9
0, 4, 8, 12
General-Purpose Input Output 9
ePWM-5 Output B
EPWM5_B
1
SCIB_TX
2
SCI-B Transmit Data
OUTPUTXBAR6
EQEP1_INDEX
SCIA_RX
3
Output X-BAR Output 6
eQEP-1 Index
5
6
SCI-A Receive Data
SPIA_CLK
7
I/O
O
I
SPI-A Clock
FSITXA_D0
LINB_RX
10
FSITX-A Primary Data Output
LIN-B Receive
11
HIC_BASESEL0
I2CB_SCL
13
I
HIC Base address range select 0
14
I/OD I2C-B Open-Drain Bidirectional Clock
HIC_NRDY
GPIO10
15
O
I/O
O
HIC Ready from device to host
General-Purpose Input Output 10
ePWM-6 Output A
0, 4, 8, 12
EPWM6_A
1
3
ADCSOCBO
EQEP1_A
O
ADC Start of Conversion B for External ADC
eQEP-1 Input A
5
I
SCIB_TX
6
O
SCI-B Transmit Data
SPIA_SOMI
I2CA_SDA
7
I/O
SPI-A Slave Out, Master In (SOMI)
9
I/OD I2C-A Open-Drain Bidirectional Data
FSITXA_CLK
LINB_TX
10
11
13
14
15
O
O
I
FSITX-A Output Clock
LIN-B Transmit
HIC_NWE
HIC Data Write enable from host
FSITX-A Time Division Multiplexed Data Input
CLB Output X-BAR Output 4
FSITXA_TDM_D0
CLB_OUTPUTXBAR4
I
O
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO11
0, 4, 8, 12
I/O
O
O
I
General-Purpose Input Output 11
ePWM-6 Output B
EPWM6_B
OUTPUTXBAR7
EQEP1_B
SCIB_RX
1
3
Output X-BAR Output 7
eQEP-1 Input B
5
6
I
SCI-B Receive Data
SPIA_STE
FSIRXA_D1
LINB_RX
7
I/O
I
SPI-A Slave Transmit Enable (STE)
FSIRX-A Optional Additional Data Input
LIN-B Receive
52
51
50
37
36
35
31
30
29
31
30
29
9
10
I
EQEP2_A
SPIA_SIMO
HIC_D6
11
I
eQEP-2 Input A
13
I/O
I/O
I
SPI-A Slave In, Master Out (SIMO)
HIC Data 6
14
HIC_NBE0
GPIO12
15
HIC Byte enable 0
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 12
ePWM-7 Output A
EPWM7_A
MCAN_RX
EQEP1_STROBE
SCIB_TX
1
3
5
6
CAN/CAN FD Receive
eQEP-1 Strobe
I/O
O
SCI-B Transmit Data
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
7
I/O
FSIRXA_D0
LINB_TX
9
I
FSIRX-A Primary Data Input
LIN-B Transmit
10
O
SPIA_CLK
CANA_RX
HIC_D13
11
I/O
I
SPI-A Clock
13
CAN-A Receive
14
I/O
O
HIC Data 13
HIC_INT
15
HIC Device interrupt to host
General-Purpose Input Output 13
ePWM-7 Output B
CAN/CAN FD Transmit
eQEP-1 Index
GPIO13
0, 4, 8, 12
I/O
O
EPWM7_B
MCAN_TX
EQEP1_INDEX
SCIB_RX
1
3
O
5
I/O
I
6
SCI-B Receive Data
PMBUSA_ALERT
FSIRXA_CLK
LINB_RX
7
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
9
I
FSIRX-A Input Clock
LIN-B Receive
10
11
13
14
15
I
SPIA_SOMI
CANA_TX
HIC_D11
I/O
O
SPI-A Slave Out, Master In (SOMI)
CAN-A Transmit
I/O
I/O
HIC Data 11
HIC_D5
HIC Data 5
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
GPIO14
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
0, 4, 8, 12
I/O
O
General-Purpose Input Output 14
ePWM-8 Output A
EPWM8_A
1
SCIB_TX
2
O
SCI-B Transmit Data
I2CB_SDA
5
I/OD I2C-B Open-Drain Bidirectional Data
Output X-BAR Output 3
I/OD PMBus-A Open-Drain Bidirectional Data
OUTPUTXBAR3
PMBUSA_SDA
SPIB_CLK
6
O
7
96
79
9
I/O
I
SPI-B Clock
EQEP2_A
10
eQEP-2 Input A
LINB_TX
11
O
O
O
I/O
I/O
O
I
LIN-B Transmit
EPWM3_A
13
ePWM-3 Output A
CLB Output X-BAR Output 7
HIC Data 15
CLB_OUTPUTXBAR7
HIC_D15
14
15
GPIO15
0, 4, 8, 12
General-Purpose Input Output 15
ePWM-8 Output B
SCI-B Receive Data
EPWM8_B
1
SCIB_RX
2
I2CB_SCL
5
I/OD I2C-B Open-Drain Bidirectional Clock
Output X-BAR Output 4
I/OD PMBus-A Open-Drain Bidirectional Clock
OUTPUTXBAR4
PMBUSA_SCL
SPIB_STE
6
O
7
95
78
9
I/O
I
SPI-B Slave Transmit Enable (STE)
eQEP-2 Input B
EQEP2_B
10
LINB_RX
11
I
LIN-B Receive
EPWM3_B
13
O
ePWM-3 Output B
CLB_OUTPUTXBAR6
HIC_D12
14
O
CLB Output X-BAR Output 6
HIC Data 12
15
I/O
I/O
I/O
O
GPIO16
0, 4, 8, 12
General-Purpose Input Output 16
SPI-A Slave In, Master Out (SIMO)
Output X-BAR Output 7
ePWM-5 Output A
SPIA_SIMO
OUTPUTXBAR7
EPWM5_A
1
3
5
O
SCIA_TX
6
O
SCI-A Transmit Data
SD1_D1
7
I
SDFM-1 Channel 1 Data Input
eQEP-1 Strobe
EQEP1_STROBE
PMBUSA_SCL
9
I/O
54
39
33
33
26
10
I/OD PMBus-A Open-Drain Bidirectional Clock
External Clock Output. This pin outputs a
XCLKOUT
11
O
divided-down version of a chosen clock signal
from within the device.
EQEP2_B
SPIB_SOMI
HIC_D1
13
14
15
I
eQEP-2 Input B
I/O
I/O
SPI-B Slave Out, Master In (SOMI)
HIC Data 1
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO17
0, 4, 8, 12
I/O
I/O
O
General-Purpose Input Output 17
SPI-A Slave Out, Master In (SOMI)
Output X-BAR Output 8
ePWM-5 Output B
SPIA_SOMI
OUTPUTXBAR8
EPWM5_B
SCIA_RX
1
3
5
O
6
I
SCI-A Receive Data
55
40
34
34
SD1_C1
7
I
SDFM-1 Channel 1 Clock Input
eQEP-1 Index
EQEP1_INDEX
PMBUSA_SDA
CANA_TX
HIC_D2
9
I/O
10
I/OD PMBus-A Open-Drain Bidirectional Data
11
O
I/O
I/O
I/O
O
CAN-A Transmit
15
HIC Data 2
GPIO18
0, 4, 8, 12
General-Purpose Input Output 18
SPI-A Clock
SPIA_CLK
SCIB_TX
1
2
3
5
6
7
9
SCI-B Transmit Data
CAN-A Receive
CANA_RX
EPWM6_A
I2CA_SCL
SD1_D2
I
O
ePWM-6 Output A
I/OD I2C-A Open-Drain Bidirectional Clock
I
I
SDFM-1 Channel 2 Data Input
eQEP-2 Input A
EQEP2_A
68
50
41
41
33
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
10
I/O
External Clock Output. This pin outputs a
divided-down version of a chosen clock signal
from within the device.
XCLKOUT
11
O
LINB_TX
13
O
I
LIN-B Transmit
FSITXA_TDM_CLK
HIC_INT
14
FSITX-A Time Division Multiplexed Clock Input
HIC Device interrupt to host
Crystal oscillator output.
General-Purpose Input Output 19
SPI-A Slave Transmit Enable (STE)
SCI-B Receive Data
15
O
X2
ALT
I/O
I/O
I/O
I
GPIO19
0, 4, 8, 12
SPIA_STE
SCIB_RX
1
2
CANA_TX
3
O
CAN-A Transmit
EPWM6_B
I2CA_SDA
SD1_C2
5
O
ePWM-6 Output B
6
I/OD I2C-A Open-Drain Bidirectional Data
7
I
I
SDFM-1 Channel 2 Clock Input
eQEP-2 Input B
EQEP2_B
9
PMBUSA_ALERT
CLB_OUTPUTXBAR1
LINB_RX
10
11
13
14
15
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
69
51
42
42
34
O
I
CLB Output X-BAR Output 1
LIN-B Receive
FSITXA_TDM_D0
HIC_NBE0
I
FSITX-A Time Division Multiplexed Data Input
HIC Byte enable 0
I
Crystal oscillator input or single-ended clock
input. The device initialization software must
configure this pin before the crystal oscillator is
enabled. To use this oscillator, a quartz crystal
circuit must be connected to X1 and X2. This
pin can also be used to feed a single-ended
3.3-V level clock. See the XTAL section for
usage details.
X1
ALT
I/O
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
General-Purpose Input Output 20. This pin
also has analog functions which are described
in the ANALOG section of this table.
GPIO20 (See ANALOG
Section)
0, 4, 8, 12
I/O
EQEP1_A
SPIB_SIMO
SD1_D3
1
6
7
9
I
I/O
I
eQEP-1 Input A
48
33
SPI-B Slave In, Master Out (SIMO)
SDFM-1 Channel 3 Data Input
CAN/CAN FD Transmit
MCAN_TX
O
General-Purpose Input Output 21. This pin
also has analog functions which are described
in the ANALOG section of this table.
GPIO21 (See ANALOG
Section)
0, 4, 8, 12
I/O
EQEP1_B
SPIB_SOMI
SD1_C3
1
I
I/O
I
eQEP-1 Input B
49
34
6
SPI-B Slave Out, Master In (SOMI)
SDFM-1 Channel 3 Clock Input
CAN/CAN FD Receive
General-Purpose Input Output 22
eQEP-1 Strobe
7
MCAN_RX
GPIO22
9
I
0, 4, 8, 12
I/O
I/O
O
I/O
I
EQEP1_STROBE
SCIB_TX
1
3
SCI-B Transmit Data
SPI-B Clock
SPIB_CLK
SD1_D4
6
7
SDFM-1 Channel 4 Data Input
LIN-A Transmit
LINA_TX
9
83
67
56
56
O
O
O
I
CLB_OUTPUTXBAR1
LINB_TX
10
CLB Output X-BAR Output 1
LIN-B Transmit
11
HIC_A5
13
HIC Address 5
EPWM4_A
HIC_D13
14
O
I/O
I/O
I/O
I
ePWM-4 Output A
15
HIC Data 13
GPIO23
0, 4, 8, 12
General-Purpose Input Output 23
eQEP-1 Index
EQEP1_INDEX
SCIB_RX
1
3
SCI-B Receive Data
SPI-B Slave Transmit Enable (STE)
SDFM-1 Channel 4 Clock Input
LIN-A Receive
SPIB_STE
SD1_C4
6
I/O
I
7
LINA_RX
9
81
65
54
54
I
CLB_OUTPUTXBAR3
LINB_RX
10
11
13
14
15
O
I
CLB Output X-BAR Output 3
LIN-B Receive
HIC_A3
I
HIC Address 3
EPWM4_B
HIC_D11
O
I/O
ePWM-4 Output B
HIC Data 11
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO24
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 24
Output X-BAR Output 1
eQEP-2 Input A
OUTPUTXBAR1
EQEP2_A
EPWM8_A
SPIB_SIMO
SD2_D1
1
2
5
O
I/O
I
ePWM-8 Output A
6
SPI-B Slave In, Master Out (SIMO)
SDFM-2 Channel 1 Data Input
LIN-B Transmit
7
56
41
35
35
27
LINB_TX
9
O
PMBUSA_SCL
SCIA_TX
10
11
I/OD PMBus-A Open-Drain Bidirectional Clock
O
SCI-A Transmit Data
Error Status Output. This signal requires an
external pulldown.
ERRORSTS
13
O
HIC_D3
15
I/O
I/O
O
I
HIC Data 3
GPIO25
0, 4, 8, 12
General-Purpose Input Output 25
Output X-BAR Output 2
eQEP-2 Input B
OUTPUTXBAR2
EQEP2_B
1
2
EQEP1_A
5
I
eQEP-1 Input A
SPIB_SOMI
SD2_C1
6
I/O
I
SPI-B Slave Out, Master In (SOMI)
SDFM-2 Channel 1 Clock Input
FSITX-A Optional Additional Data Output
57
58
59
42
43
44
7
FSITXA_D1
PMBUSA_SDA
SCIA_RX
9
O
10
I/OD PMBus-A Open-Drain Bidirectional Data
11
I
I
SCI-A Receive Data
HIC_BASESEL0
GPIO26
14
HIC Base address range select 0
General-Purpose Input Output 26
Output X-BAR Output 3
eQEP-2 Index
0, 4, 8, 12
I/O
O
OUTPUTXBAR3
EQEP2_INDEX
SPIB_CLK
SD2_D2
1, 5
2
I/O
I/O
I
6
SPI-B Clock
7
SDFM-2 Channel 2 Data Input
FSITX-A Primary Data Output
FSITXA_D0
9
O
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
10
I/O
I2CA_SDA
HIC_D0
11
I/OD I2C-A Open-Drain Bidirectional Data
14
I/O
I
HIC Data 0
HIC_A1
15
HIC Address 1
GPIO27
0, 4, 8, 12
I/O
O
General-Purpose Input Output 27
Output X-BAR Output 4
eQEP-2 Strobe
OUTPUTXBAR4
EQEP2_STROBE
SPIB_STE
SD2_C2
1, 5
2
I/O
I/O
I
6
SPI-B Slave Transmit Enable (STE)
SDFM-2 Channel 2 Clock Input
FSITX-A Output Clock
7
FSITXA_CLK
PMBUSA_ALERT
I2CA_SCL
HIC_D1
9
O
10
11
14
15
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I/OD I2C-A Open-Drain Bidirectional Clock
I/O
I
HIC Data 1
HIC_A4
HIC Address 4
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
GPIO28
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
0, 4, 8, 12
I/O
I
General-Purpose Input Output 28
SCI-A Receive Data
ePWM-7 Output A
SCIA_RX
1
3
EPWM7_A
OUTPUTXBAR5
EQEP1_A
O
O
I
5
Output X-BAR Output 5
eQEP-1 Input A
6
SD2_D3
7
I
SDFM-2 Channel 3 Data Input
eQEP-2 Strobe
1
4
2
2
2
EQEP2_STROBE
LINA_TX
9
I/O
O
I/O
10
11
LIN-A Transmit
SPIB_CLK
SPI-B Clock
Error Status Output. This signal requires an
external pulldown.
ERRORSTS
13
O
I2CB_SDA
HIC_NOE
GPIO29
14
I/OD I2C-B Open-Drain Bidirectional Data
15
O
I/O
O
O
O
I
HIC Output enable for data bus
General-Purpose Input Output 29
SCI-A Transmit Data
0, 4, 8, 12
SCIA_TX
1
3
EPWM7_B
OUTPUTXBAR6
EQEP1_B
SD2_C3
ePWM-7 Output B
5
Output X-BAR Output 6
eQEP-1 Input B
6
7
I
SDFM-2 Channel 3 Clock Input
eQEP-2 Index
EQEP2_INDEX
LINA_RX
9
I/O
I
100
3
1
1
1
10
11
LIN-A Receive
SPIB_STE
I/O
SPI-B Slave Transmit Enable (STE)
Error Status Output. This signal requires an
external pulldown.
ERRORSTS
13
O
I2CB_SCL
HIC_NCS
14
I/OD I2C-B Open-Drain Bidirectional Clock
15
I
HIC Chip select input
AUXCLKIN
GPIO30
ALT
0, 4, 8, 12
I/O
I
General-Purpose Input Output 30
CAN-A Receive
CANA_RX
SPIB_SIMO
OUTPUTXBAR7
EQEP1_STROBE
SD2_D4
1
3
I/O
O
I/O
I
SPI-B Slave In, Master Out (SIMO)
Output X-BAR Output 7
eQEP-1 Strobe
5
6
98
1
7
SDFM-2 Channel 4 Data Input
FSIRX-A Input Clock
CAN/CAN FD Receive
ePWM-1 Output A
FSIRXA_CLK
MCAN_RX
EPWM1_A
HIC_D8
9
I
10
11
14
I
O
I/O
HIC Data 8
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO31
0, 4, 8, 12
I/O
O
General-Purpose Input Output 31
CAN-A Transmit
CANA_TX
SPIB_SOMI
OUTPUTXBAR8
EQEP1_INDEX
SD2_C4
1
3
I/O
O
SPI-B Slave Out, Master In (SOMI)
Output X-BAR Output 8
eQEP-1 Index
5
6
I/O
I
99
2
7
SDFM-2 Channel 4 Clock Input
FSIRX-A Optional Additional Data Input
CAN/CAN FD Transmit
FSIRXA_D1
MCAN_TX
EPWM1_B
HIC_D10
9
I
10
O
11
O
ePWM-1 Output B
14
I/O
I/O
HIC Data 10
GPIO32
0, 4, 8, 12
General-Purpose Input Output 32
I2CA_SDA
SPIB_CLK
EPWM8_B
LINA_TX
1
I/OD I2C-A Open-Drain Bidirectional Data
3
I/O
O
O
I
SPI-B Clock
5
ePWM-8 Output B
LIN-A Transmit
6
SD1_D2
7
64
49
40
40
32
SDFM-1 Channel 2 Data Input
FSIRX-A Primary Data Input
CAN-A Transmit
FSIRXA_D0
CANA_TX
PMBUSA_SDA
ADCSOCBO
HIC_INT
9
I
10
O
11
I/OD PMBus-A Open-Drain Bidirectional Data
13
O
O
ADC Start of Conversion B for External ADC
HIC Device interrupt to host
15
GPIO33
0, 4, 8, 12
I/O
General-Purpose Input Output 33
I2CA_SCL
SPIB_STE
OUTPUTXBAR4
LINA_RX
1
I/OD I2C-A Open-Drain Bidirectional Clock
3
I/O
SPI-B Slave Transmit Enable (STE)
Output X-BAR Output 4
LIN-A Receive
5
O
6
I
I
SD1_C2
7
SDFM-1 Channel 2 Clock Input
FSIRX-A Input Clock
53
38
32
32
25
FSIRXA_CLK
CANA_RX
EQEP2_B
ADCSOCAO
SD1_C1
9
I
10
I
CAN-A Receive
11
I
eQEP-2 Input B
13
O
I
ADC Start of Conversion A for External ADC
SDFM-1 Channel 1 Clock Input
HIC Data 0
14
HIC_D0
15
I/O
I/O
O
GPIO34
0, 4, 8, 12
General-Purpose Input Output 34
Output X-BAR Output 1
OUTPUTXBAR1
PMBUSA_SDA
HIC_NBE1
I2CB_SDA
HIC_D9
1
6
I/OD PMBus-A Open-Drain Bidirectional Data
HIC Byte enable 1
I/OD I2C-B Open-Drain Bidirectional Data
I/O HIC Data 9
94
77
13
14
15
I
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
GPIO35
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
0, 4, 8, 12
I/O
I
General-Purpose Input Output 35
SCI-A Receive Data
SCIA_RX
1
3
5
6
7
9
I2CA_SDA
CANA_RX
PMBUSA_SCL
LINA_RX
I/OD I2C-A Open-Drain Bidirectional Data
CAN-A Receive
I/OD PMBus-A Open-Drain Bidirectional Clock
I
I
I
LIN-A Receive
eQEP-1 Input A
EQEP1_A
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
10
I/O
63
48
39
39
31
EPWM5_B
SD2_C1
11
13
14
O
I
ePWM-5 Output B
SDFM-2 Channel 1 Clock Input
HIC Data Write enable from host
HIC_NWE
I
JTAG Test Data Input (TDI) - TDI is the default
mux selection for the pin. The internal pullup is
disabled by default. The internal pullup should
be enabled or an external pullup added on the
board if this pin is used as JTAG TDI to avoid a
floating input.
TDI
15
I
GPIO37
0, 4, 8, 12
I/O
O
General-Purpose Input Output 37
Output X-BAR Output 2
OUTPUTXBAR2
I2CA_SCL
SCIA_TX
1
3
I/OD I2C-A Open-Drain Bidirectional Clock
5
O
O
O
I
SCI-A Transmit Data
CAN-A Transmit
LIN-A Transmit
CANA_TX
6
LINA_TX
7
EQEP1_B
9
eQEP-1 Input B
61
46
37
37
29
PMBUSA_ALERT
HIC_NRDY
10
14
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
O
HIC Ready from device to host
JTAG Test Data Output (TDO) - TDO is the
default mux selection for the pin. The internal
pullup is disabled by default. The TDO function
will tristate when there is no JTAG activity,
leaving this pin floating; the internal pullup
should be enabled or an external pullup added
on the board to avoid a floating GPIO input.
TDO
15
O
GPIO39
0, 4, 8, 12
I/O
I
General-Purpose Input Output 39
CAN/CAN FD Receive
FSIRX-A Input Clock
MCAN_RX
6
7
FSIRXA_CLK
EQEP2_INDEX
CLB_OUTPUTXBAR2
SYNCOUT
I
9
I/O
O
eQEP-2 Index
56
46
11
13
14
15
CLB Output X-BAR Output 2
External ePWM Synchronization Pulse
eQEP-1 Index
O
EQEP1_INDEX
HIC_D7
I/O
I/O
HIC Data 7
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO40
0, 4, 8, 12
I/O
I/O
O
General-Purpose Input Output 40
SPI-B Slave In, Master Out (SIMO)
ePWM-2 Output B
SPIB_SIMO
EPWM2_B
PMBUSA_SDA
FSIRXA_D0
SCIB_TX
1
5
6
I/OD PMBus-A Open-Drain Bidirectional Data
7
I
O
I
FSIRX-A Primary Data Input
SCI-B Transmit Data
eQEP-1 Input A
80
64
53
53
9
EQEP1_A
LINB_TX
10
11
O
I
LIN-B Transmit
HIC_NBE1
HIC_D5
14
HIC Byte enable 1
HIC Data 5
15
I/O
I/O
O
GPIO41
0, 4, 8, 12
General-Purpose Input Output 41
ePWM-2 Output A
EPWM2_A
PMBUSA_SCL
FSIRXA_D1
SCIB_RX
5
6
I/OD PMBus-A Open-Drain Bidirectional Clock
7
I
FSIRX-A Optional Additional Data Input
SCI-B Receive Data
9
I
I
82
66
55
55
EQEP1_B
LINB_RX
10
eQEP-1 Input B
11
I
LIN-B Receive
HIC_A4
13
I
HIC Address 4
SPIB_SOMI
HIC_D12
14
I/O
I/O
I/O
I
SPI-B Slave Out, Master In (SOMI)
HIC Data 12
15
GPIO42
0, 4, 8, 12
General-Purpose Input Output 42
LIN-A Receive
LINA_RX
2
3
OUTPUTXBAR5
O
Output X-BAR Output 5
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
5
I/O
57
I2CA_SDA
6
I/OD I2C-A Open-Drain Bidirectional Data
EQEP1_STROBE
CLB_OUTPUTXBAR3
HIC_D2
10
I/O
O
eQEP-1 Strobe
11
CLB Output X-BAR Output 3
HIC Data 2
14
I/O
I
HIC_A6
15
HIC Address 6
GPIO43
0, 4, 8, 12
I/O
O
General-Purpose Input Output 43
Output X-BAR Output 6
OUTPUTXBAR6
PMBUSA_ALERT
I2CA_SCL
3
5, 9
6
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
I/OD I2C-A Open-Drain Bidirectional Clock
EQEP1_INDEX
CLB_OUTPUTXBAR4
SD2_D3
10
11
13
14
15
54
I/O
O
I
eQEP-1 Index
CLB Output X-BAR Output 4
SDFM-2 Channel 3 Data Input
HIC Data 3
HIC_D3
I/O
I
HIC_A7
HIC Address 7
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
GPIO44
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
0, 4, 8, 12
I/O
O
I
General-Purpose Input Output 44
Output X-BAR Output 7
eQEP-1 Input A
OUTPUTXBAR7
EQEP1_A
3
5
6
7
PMBUSA_SDA
FSITXA_CLK
I/OD PMBus-A Open-Drain Bidirectional Data
O
FSITX-A Output Clock
PMBus-A Control Signal - Slave Input/Master
Output
PMBUSA_CTL
9
85
69
I/O
CLB_OUTPUTXBAR3
FSIRXA_D0
HIC_D7
10
O
I
CLB Output X-BAR Output 3
FSIRX-A Primary Data Input
HIC Data 7
11
13
I/O
O
LINB_TX
14
LIN-B Transmit
HIC_D5
15
I/O
I/O
O
HIC Data 5
GPIO45
0, 4, 8, 12
General-Purpose Input Output 45
Output X-BAR Output 8
FSITX-A Primary Data Output
OUTPUTXBAR8
FSITXA_D0
PMBUSA_ALERT
CLB_OUTPUTXBAR4
SD2_C3
3
7
O
9
73
I/OD PMBus-A Open-Drain Bidirectional Alert Signal
10
O
I
CLB Output X-BAR Output 4
SDFM-2 Channel 3 Clock Input
HIC Data 6
13
HIC_D6
15
I/O
I/O
O
GPIO46
0, 4, 8, 12
General-Purpose Input Output 46
LIN-A Transmit
LINA_TX
3
MCAN_TX
5
O
CAN/CAN FD Transmit
FSITXA_D1
PMBUSA_SDA
SD2_C4
7
6
O
FSITX-A Optional Additional Data Output
9
I/OD PMBus-A Open-Drain Bidirectional Data
13
I
I
SDFM-2 Channel 4 Clock Input
HIC Data Write enable from host
General-Purpose Input Output 47
LIN-A Receive
HIC_NWE
15
GPIO47
0, 4, 8, 12
I/O
I
LINA_RX
3
MCAN_RX
CLB_OUTPUTXBAR2
PMBUSA_SCL
SD2_D4
5
I
CAN/CAN FD Receive
7
O
CLB Output X-BAR Output 2
6
9
I/OD PMBus-A Open-Drain Bidirectional Clock
13
I
I
SDFM-2 Channel 4 Data Input
FSITX-A Time Division Multiplexed Clock Input
HIC Address 6
FSITXA_TDM_CLK
HIC_A6
14
15
I
GPIO48
0, 4, 8, 12
I/O
O
O
O
I
General-Purpose Input Output 48
Output X-BAR Output 3
OUTPUTXBAR3
CANA_TX
1
3
CAN-A Transmit
SCIA_TX
6
7
SCI-A Transmit Data
SD1_D1
7
SDFM-1 Channel 1 Data Input
PMBUSA_SDA
HIC_A7
9
I/OD PMBus-A Open-Drain Bidirectional Data
HIC Address 7
15
I
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO49
0, 4, 8, 12
I/O
General-Purpose Input Output 49
Output X-BAR Output 4
CAN-A Receive
OUTPUTXBAR4
CANA_RX
SCIA_RX
1
O
3
I
6
I
I
SCI-A Receive Data
SD1_C1
7
8
SDFM-1 Channel 1 Clock Input
LIN-A Receive
LINA_RX
9
I
SD2_D1
13
I
SDFM-2 Channel 1 Data Input
FSITX-A Primary Data Output
HIC Data 2
FSITXA_D0
HIC_D2
14
O
I/O
I/O
I
15
GPIO50
0, 4, 8, 12
General-Purpose Input Output 50
eQEP-1 Input A
EQEP1_A
MCAN_TX
SPIB_SIMO
SD1_D2
1
5
O
I/O
I
CAN/CAN FD Transmit
SPI-B Slave In, Master Out (SIMO)
SDFM-1 Channel 2 Data Input
6
7
9
I2CB_SDA
SD2_D2
9
I/OD I2C-B Open-Drain Bidirectional Data
13
I
O
I/O
I/O
I
SDFM-2 Channel 2 Data Input
FSITX-A Optional Additional Data Output
HIC Data 3
FSITXA_D1
HIC_D3
14
15
GPIO51
0, 4, 8, 12
General-Purpose Input Output 51
eQEP-1 Input B
EQEP1_B
MCAN_RX
SPIB_SOMI
SD1_C2
1
5
I
CAN/CAN FD Receive
6
I/O
I
SPI-B Slave Out, Master In (SOMI)
SDFM-1 Channel 2 Clock Input
7
10
11
12
I2CB_SCL
SD2_D3
9
I/OD I2C-B Open-Drain Bidirectional Clock
13
I
O
I/O
I/O
I/O
O
I/O
I
SDFM-2 Channel 3 Data Input
FSITX-A Output Clock
FSITXA_CLK
HIC_D6
14
15
HIC Data 6
GPIO52
0, 4, 8, 12
General-Purpose Input Output 52
eQEP-1 Strobe
EQEP1_STROBE
CLB_OUTPUTXBAR5
SPIB_CLK
SD1_D3
1
5
CLB Output X-BAR Output 5
SPI-B Clock
6
7
SDFM-1 Channel 3 Data Input
External ePWM Synchronization Pulse
SDFM-2 Channel 4 Data Input
FSIRX-A Primary Data Input
HIC Data Write enable from host
General-Purpose Input Output 53
eQEP-1 Index
SYNCOUT
SD2_D4
9
O
I
13
FSIRXA_D0
HIC_NWE
GPIO53
14
I
15
I
0, 4, 8, 12
I/O
I/O
O
I/O
I
EQEP1_INDEX
CLB_OUTPUTXBAR6
SPIB_STE
SD1_C3
1
5
CLB Output X-BAR Output 6
SPI-B Slave Transmit Enable (STE)
SDFM-1 Channel 3 Clock Input
ADC Start of Conversion A for External ADC
CAN-A Receive
6
7
ADCSOCAO
CANA_RX
SD1_C1
9
O
I
10
13
14
I
SDFM-1 Channel 1 Clock Input
FSIRX-A Optional Additional Data Input
FSIRXA_D1
I
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
GPIO54
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 54
SPI-A Slave In, Master Out (SIMO)
eQEP-2 Input A
SPIA_SIMO
EQEP2_A
1
5
OUTPUTXBAR2
SD1_D4
6
O
I
Output X-BAR Output 2
7
SDFM-1 Channel 4 Data Input
13
ADCSOCBO
LINB_TX
9
O
O
I
ADC Start of Conversion B for External ADC
LIN-B Transmit
10
13
14
SD1_C2
SDFM-1 Channel 2 Clock Input
FSIRX-A Input Clock
FSIRXA_CLK
I
FSITX-A Time Division Multiplexed Additional
Data Input
FSITXA_TDM_D1
15
I
GPIO55
0, 4, 8, 12
I/O
I/O
I
General-Purpose Input Output 55
SPI-A Slave Out, Master In (SOMI)
eQEP-2 Input B
SPIA_SOMI
EQEP2_B
OUTPUTXBAR3
SD1_C4
1
5
6
7
O
I
Output X-BAR Output 3
SDFM-1 Channel 4 Clock Input
43
Error Status Output. This signal requires an
external pulldown.
ERRORSTS
9
O
LINB_RX
10
I
I
LIN-B Receive
SD1_C3
13
SDFM-1 Channel 3 Clock Input
HIC Address 0
HIC_A0
15
I
GPIO56
0, 4, 8, 12
I/O
I/O
O
O
I/O
O
I
General-Purpose Input Output 56
SPI-A Clock
SPIA_CLK
CLB_OUTPUTXBAR7
MCAN_TX
EQEP2_STROBE
SCIB_TX
1
2
CLB Output X-BAR Output 7
CAN/CAN FD Transmit
eQEP-2 Strobe
3
5
6
SCI-B Transmit Data
SD2_D1
7
65
SDFM-2 Channel 1 Data Input
SPI-B Slave In, Master Out (SIMO)
SPIB_SIMO
I2CA_SDA
EQEP1_A
9
I/O
10
I/OD I2C-A Open-Drain Bidirectional Data
11
I
I
eQEP-1 Input A
SD1_C4
13
SDFM-1 Channel 4 Clock Input
FSIRX-A Optional Additional Data Input
HIC Data 6
FSIRXA_D1
HIC_D6
14
I
15
I/O
I/O
I/O
O
I
GPIO57
0, 4, 8, 12
General-Purpose Input Output 57
SPI-A Slave Transmit Enable (STE)
CLB Output X-BAR Output 8
CAN/CAN FD Receive
SPIA_STE
CLB_OUTPUTXBAR8
MCAN_RX
EQEP2_INDEX
SCIB_RX
1
2
3
5
I/O
I
eQEP-2 Index
6
SCI-B Receive Data
66
SD2_C1
7
I
SDFM-2 Channel 1 Clock Input
SPI-B Slave Out, Master In (SOMI)
SPIB_SOMI
I2CA_SCL
EQEP1_B
9
I/O
10
11
14
15
I/OD I2C-A Open-Drain Bidirectional Clock
I
I
eQEP-1 Input B
FSIRX-A Input Clock
HIC Data 4
FSIRXA_CLK
HIC_D4
I/O
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
GPIO58
0, 4, 8, 12
I/O
O
I/O
I
General-Purpose Input Output 58
Output X-BAR Output 1
SPI-B Clock
OUTPUTXBAR1
SPIB_CLK
SD2_D2
5
6
7
SDFM-2 Channel 2 Data Input
LIN-A Transmit
LINA_TX
9
O
O
I/O
I
67
CANA_TX
EQEP1_STROBE
SD2_C2
10
CAN-A Transmit
11
eQEP-1 Strobe
13
SDFM-2 Channel 2 Clock Input
FSIRX-A Primary Data Input
HIC Ready from device to host
General-Purpose Input Output 59
Output X-BAR Output 2
SPI-B Slave Transmit Enable (STE)
SDFM-2 Channel 2 Clock Input
LIN-A Receive
FSIRXA_D0
HIC_NRDY
GPIO59
14
I
15
O
I/O
O
I/O
I
0, 4, 8, 12
OUTPUTXBAR2
SPIB_STE
SD2_C2
5
6
7
LINA_RX
9
I
92
CANA_RX
EQEP1_INDEX
SD2_C3
10
11
13
I
CAN-A Receive
I/O
I
eQEP-1 Index
SDFM-2 Channel 3 Clock Input
FSITX-A Time Division Multiplexed Additional
Data Input
FSITXA_TDM_D1
14
I
GPIO60
0, 4, 8, 12
I/O
O
O
I/O
I
General-Purpose Input Output 60
CAN/CAN FD Transmit
MCAN_TX
OUTPUTXBAR3
SPIB_SIMO
SD2_D3
3
5
Output X-BAR Output 3
6
44
SPI-B Slave In, Master Out (SIMO)
SDFM-2 Channel 3 Data Input
SDFM-2 Channel 4 Clock Input
HIC Address 0
7
SD2_C4
13
I
HIC_A0
15
I
GPIO61
0, 4, 8, 12
I/O
I
General-Purpose Input Output 61
CAN/CAN FD Receive
MCAN_RX
OUTPUTXBAR4
SPIB_SOMI
SD2_C3
3
5
O
I/O
I
Output X-BAR Output 4
91
6
SPI-B Slave Out, Master In (SOMI)
SDFM-2 Channel 3 Clock Input
CAN-A Receive
7
CANA_RX
14
I
TEST, JTAG, AND RESET
TCK
TMS
60
62
45
47
36
36
28
I
JTAG test clock with internal pullup.
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
This device does not have a TRSTn pin. An
external pullup resistor (recommended 2.2 kΩ)
on the TMS pin to VDDIO should be placed on
the board to keep JTAG in reset during normal
operation.
38
38
30
I/O
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-1. Pin Attributes (continued)
MUX
POSITION
64
PMQ
PIN
TYPE
SIGNAL NAME
100 PZ 80 PN 64 PM
48 PT
DESCRIPTION
Device Reset (in) and Watchdog Reset (out).
During a power-on condition, this pin is driven
low by the device. An external circuit may also
drive this pin to assert a device reset. This
pin is also driven low by the MCU when a
watchdog reset occurs. During watchdog reset,
the XRSn pin is driven low for the watchdog
reset duration of 512 OSCCLK cycles. A
resistor between 2.2 kΩ and 10 kΩ should
XRSn
2
5
3
3
3
I/OD be placed between XRSn and VDDIO. If a
capacitor is placed between XRSn and VSS
for noise filtering, it should be 100 nF or
smaller. These values will allow the watchdog
to properly drive the XRSn pin to VOL within
512 OSCCLK cycles when the watchdog reset
is asserted. This pin is an open-drain output
with an internal pullup. If this pin is driven by
an external device, it should be done using an
open-drain device.
POWER AND GROUND
4, 46, 8, 31, 4, 27, 4, 27, 23, 36,
1.2-V Digital Logic Power Pins. See the PMM
section for usage details.
VDD
71, 87 53, 71 44, 59 44, 59
45
3.3-V Analog Power Pins. Place a minimum
2.2-µF decoupling capacitor on each pin. See
the PMM section for usage details.
VDDA
VDDIO
34 26 22 22
18
3, 47, 7, 32, 28, 43, 28, 43, 24, 35,
3.3-V Digital I/O Power Pins. See the PMM
section for usage details.
70, 88 52, 72
60
60
46
Internal voltage regulator disable with internal
pulldown. Tie low to VSS to enable internal
VREG. Tie high to VDDIO to use an external
VREGENZ
73
46
I
supply. See the PMM section for usage details.
5, 45, 9, 30, 5, 26, 5, 26, 22, 37,
VSS
Digital Ground
72, 86 55, 70 45, 58 45, 58
44
VSSA
33 25 21 21
17
Analog Ground
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.3 Signal Descriptions
5.3.1 Analog Signals
Table 5-2. Analog Signals
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
19
64 PM PIN
64 PMQ PIN
48 PT PIN
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-A Input 0
ADC-A Input 1
ADC-A Input 2
ADC-A Input 3
ADC-A Input 4
ADC-A Input 5
ADC-A Input 6
ADC-A Input 7
ADC-A Input 8
ADC-A Input 9
ADC-A Input 10
ADC-A Input 11
ADC-A Input 12
ADC-A Input 14
ADC-A Input 15
23
22
17
18
36
35
14
31
37
38
40
20
28
19
15
14
9
15
14
9
11
10
6
A1
18
A2
13
A3
12
8
8
5
A4
27
23
13
6
23
13
6
19
9
A5
17
A6
10
4
A7
23
19
20
24
25
12
18
11
10
9
19
20
24
25
12
18
11
10
9
15
16
20
21
8
A8
24
A9
28
A10
A11
A12
A14
A15
29
16
22
14
15
14
7
6
AIO224
AIO225
AIO226
AIO227
AIO228
AIO229
AIO230
AIO231
AIO232
AIO233
AIO236
AIO237
AIO238
AIO239
AIO240
AIO241
AIO242
AIO244
AIO245
AIO247
AIO248
AIO249
AIO251
Analog Pin Used For Digital Input
224
17
36
15
38
14
18
40
23
22
13
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Pin Used For Digital Input
225
27
11
28
10
23
7
23
7
19
4
Analog Pin Used For Digital Input
226
Analog Pin Used For Digital Input
227
24
6
24
6
20
4
Analog Pin Used For Digital Input
228
Analog Pin Used For Digital Input
229
Analog Pin Used For Digital Input
230
29
19
18
14
28
16
22
15
25
15
14
10
24
12
18
11
25
15
14
10
24
12
18
11
21
11
10
7
Analog Pin Used For Digital Input
231
Analog Pin Used For Digital Input
232
Analog Pin Used For Digital Input
233
Analog Pin Used For Digital Input
236
39
20
28
19
37
20
8
Analog Pin Used For Digital Input
237
Analog Pin Used For Digital Input
238
14
Analog Pin Used For Digital Input
239
Analog Pin Used For Digital Input
240
Analog Pin Used For Digital Input
241
24
12
17
23
20
8
20
8
16
5
Analog Pin Used For Digital Input
242
16
21
31
42
29
35
30
Analog Pin Used For Digital Input
244
13
19
13
19
9
Analog Pin Used For Digital Input
245
15
Analog Pin Used For Digital Input
247
Analog Pin Used For Digital Input
248
22
18
18
14
Analog Pin Used For Digital Input
249
Analog Pin Used For Digital Input
251
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-2. Analog Signals (continued)
SIGNAL NAME
AIO252
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
I
Analog Pin Used For Digital Input
252
48
AIO253
I
Analog Pin Used For Digital Input
253
41
B0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADC-B Input 0
ADC-B Input 1
ADC-B Input 2
ADC-B Input 3
ADC-B Input 4
ADC-B Input 5
ADC-B Input 6
ADC-B Input 7
ADC-B Input 8
ADC-B Input 9
ADC-B Input 10
ADC-B Input 11
ADC-B Input 12
ADC-B Input 14
ADC-B Input 15
ADC-C Input 0
ADC-C Input 1
ADC-C Input 2
ADC-C Input 3
ADC-C Input 4
ADC-C Input 5
ADC-C Input 6
ADC-C Input 7
ADC-C Input 8
ADC-C Input 9
ADC-C Input 10
ADC-C Input 11
ADC-C Input 14
ADC-C Input 15
41
40
24
29
11
12
28
33
13
18
27
14
16
34
17
15
19
16
22
17
23
15
12
11
14
28
13
29
24
27
19
14
20
25
7
20
25
7
16
21
4
B1
B2
15
B3
16
8
8
5
B4
39
24
24
20
B5
32, 48
17
B6
9
9
6
10
19
7
B7
22
14
23
10
12
14
23
10
12
B8
36
B9
18
B10
B11
B12
B14
B15
C0
20
8
30, 49
21
13
11
15
12
18
13
19
11
8
13
11
15
12
18
13
19
11
8
9
19
23
11
8
20
C1
29
14
9
C2
21
C3
31
15
C4
19
C5
28
5
4
C6
15
7
7
C7
18
10
24
9
10
24
9
7
C8
39
20
6
C9
17
C10
C11
C14
C15
CMP1_HN0
40
25
20
23
15
10
25
20
23
15
10
21
16
19
11
7
41
42
23
CMPSS-1 High Comparator Negative
Input 0
CMP1_HN1
CMP1_HP0
CMP1_HP1
CMP1_HP2
CMP1_HP3
CMP1_HP4
CMP1_HP5
CMP1_LN0
CMP1_LN1
CMP1_LP0
CMP1_LP1
CMP1_LP2
CMP1_LP3
I
I
I
I
I
I
I
I
I
I
I
I
I
CMPSS-1 High Comparator Negative
Input 1
20
17
20
14
16
13
16
10
14
18
33
14
16
13
16
10
14
12
9
12
9
8
6
CMPSS-1 High Comparator Positive
Input 0
CMPSS-1 High Comparator Positive
Input 1
12
6
12
6
8
CMPSS-1 High Comparator Positive
Input 2
4
CMPSS-1 High Comparator Positive
Input 3
10
14
10
14
7
CMPSS-1 High Comparator Positive
Input 4
22
10
CMPSS-1 High Comparator Positive
Input 5
32, 48
CMPSS-1 Low Comparator Negative
Input 0
10
12
9
10
12
9
7
8
6
8
4
7
CMPSS-1 Low Comparator Negative
Input 1
20
17
20
14
CMPSS-1 Low Comparator Positive
Input 0
CMPSS-1 Low Comparator Positive
Input 1
12
6
12
6
CMPSS-1 Low Comparator Positive
Input 2
CMPSS-1 Low Comparator Positive
Input 3
10
10
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-2. Analog Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
CMP1_LP4
CMP1_LP5
CMP2_HN0
CMP2_HN1
CMP2_HP0
CMP2_HP1
CMP2_HP2
CMP2_HP3
CMP2_HP4
CMP2_HP5
CMP2_LN0
CMP2_LN1
CMP2_LP0
CMP2_LP1
CMP2_LP2
CMP2_LP3
CMP2_LP4
CMP2_LP5
CMP3_HN0
CMP3_HN1
CMP3_HP0
CMP3_HP1
CMP3_HP2
CMP3_HP3
CMP3_HP4
CMP3_HP5
CMP3_LN0
CMP3_LN1
CMP3_LP0
CMP3_LP1
CMP3_LP2
CMP3_LP3
CMP3_LP4
CMP3_LP5
I
CMPSS-1 Low Comparator Positive
Input 4
22
18
14
14
10
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CMPSS-1 Low Comparator Positive
Input 5
32, 48
40
28
36
28
38
40
41
35
40
28
36
28
38
40
41
35
16
21
15
21
23
16
19
18
16
21
15
21
23
16
19
18
33
29
22
27
22
28
29
24
17
29
22
27
22
28
29
24
17
12
17
11
17
19
12
15
12
12
17
11
17
19
12
15
12
CMPSS-2 High Comparator Negative
Input 0
25
18
23
18
24
25
20
13
25
18
23
18
24
25
20
13
8
25
18
23
18
24
25
20
13
25
18
23
18
24
25
20
13
8
21
14
19
14
20
21
16
9
CMPSS-2 High Comparator Negative
Input 1
CMPSS-2 High Comparator Positive
Input 0
CMPSS-2 High Comparator Positive
Input 1
CMPSS-2 High Comparator Positive
Input 2
CMPSS-2 High Comparator Positive
Input 3
CMPSS-2 High Comparator Positive
Input 4
CMPSS-2 High Comparator Positive
Input 5
CMPSS-2 Low Comparator Negative
Input 0
21
14
19
14
20
21
16
9
CMPSS-2 Low Comparator Negative
Input 1
CMPSS-2 Low Comparator Positive
Input 0
CMPSS-2 Low Comparator Positive
Input 1
CMPSS-2 Low Comparator Positive
Input 2
CMPSS-2 Low Comparator Positive
Input 3
CMPSS-2 Low Comparator Positive
Input 4
CMPSS-2 Low Comparator Positive
Input 5
CMPSS-3 High Comparator Negative
Input 0
5
CMPSS-3 High Comparator Negative
Input 1
13
7
13
7
9
CMPSS-3 High Comparator Positive
Input 0
4
CMPSS-3 High Comparator Positive
Input 1
13
15
8
13
15
8
9
CMPSS-3 High Comparator Positive
Input 2
11
5
CMPSS-3 High Comparator Positive
Input 3
CMPSS-3 High Comparator Positive
Input 4
11
8
11
8
CMPSS-3 High Comparator Positive
Input 5
5
5
CMPSS-3 Low Comparator Negative
Input 0
8
8
CMPSS-3 Low Comparator Negative
Input 1
13
7
13
7
9
CMPSS-3 Low Comparator Positive
Input 0
4
CMPSS-3 Low Comparator Positive
Input 1
13
15
8
13
15
8
9
CMPSS-3 Low Comparator Positive
Input 2
11
5
CMPSS-3 Low Comparator Positive
Input 3
CMPSS-3 Low Comparator Positive
Input 4
11
8
11
8
CMPSS-3 Low Comparator Positive
Input 5
5
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-2. Analog Signals (continued)
SIGNAL NAME
CMP4_HN0
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
I
CMPSS-4 High Comparator Negative
Input 0
42
27
23
23
19
CMP4_HN1
CMP4_HP0
CMP4_HP1
CMP4_HP2
CMP4_HP3
CMP4_HP4
CMP4_HP5
CMP4_LN0
CMP4_LN1
CMP4_LP0
CMP4_LP1
CMP4_LP2
CMP4_LP3
CMP4_LP4
CMP4_LP5
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CMPSS-4 High Comparator Negative
Input 1
31
39
23
28
23
22
27
24
34
27
23
28
23
22
27
24
34
19
24
19
18
23
20
19
24
19
18
23
20
15
20
15
14
19
16
CMPSS-4 High Comparator Positive
Input 0
CMPSS-4 High Comparator Positive
Input 1
31
CMPSS-4 High Comparator Positive
Input 2
29
CMPSS-4 High Comparator Positive
Input 3
42
CMPSS-4 High Comparator Positive
Input 4
37
CMPSS-4 High Comparator Positive
Input 5
30, 49
42
CMPSS-4 Low Comparator Negative
Input 0
23
19
24
19
18
23
20
23
19
24
19
18
23
20
19
15
20
15
14
19
16
CMPSS-4 Low Comparator Negative
Input 1
31
CMPSS-4 Low Comparator Positive
Input 0
39
CMPSS-4 Low Comparator Positive
Input 1
31
CMPSS-4 Low Comparator Positive
Input 2
29
CMPSS-4 Low Comparator Positive
Input 3
42
CMPSS-4 Low Comparator Positive
Input 4
37
CMPSS-4 Low Comparator Positive
Input 5
30, 49
DACA_OUT
DACB_OUT
GPIO20
O
Buffered DAC-A Output.
Buffered DAC-B Output.
General-Purpose Input Output 20
General-Purpose Input Output 21
HIC Address 0
23
22
48
30
14
15
16
17
19
18
33
34
10
11
15
14
15
14
11
10
O
I/O
GPIO21
I/O
HIC_A0
I
I
6
7
6
7
4
4
5
6
7
HIC_A1
HIC Address 1
HIC_A2
I
HIC Address 2
12
13
14
15
16
17
18
19
29
28
24
22
23
27
19
23
28
29
15
16
17
18
10, 24
8
8
HIC_A3
I
HIC Address 3
9
9
HIC_A4
I
HIC Address 4
10
11
12
13
14
15
25
24
20
18
19
23
15
19
24
25
11
12
13
14
20, 6
10
11
12
13
14
15
25
24
20
18
19
23
15
19
24
25
11
12
13
14
20, 6
HIC_A5
I
HIC Address 5
19
20
HIC_A6
I
HIC Address 6
8
HIC_A7
I
HIC Address 7
21
9
HIC_BASESEL0
HIC_BASESEL1
HIC_BASESEL2
HIC_NBE0
HIC_NBE1
HIC_NCS
HIC_NOE
HIC_NWE
SD1_C1
I
HIC Base address range select 0
HIC Base address range select 1
HIC Base address range select 2
HIC Byte enable 0
22
10
11
21
20
16
14
15
19
11
15
20
21
I
23
I
40
I
38
I
HIC Byte enable 1
37
I
HIC Chip select input
28
O
I
HIC Output enable for data bus
HIC Data Write enable from host
SDFM-1 Channel 1 Clock Input
SDFM-1 Channel 2 Clock Input
SDFM-1 Channel 3 Clock Input
SDFM-1 Channel 4 Clock Input
SDFM-1 Channel 1 Data Input
SDFM-1 Channel 2 Data Input
SDFM-1 Channel 3 Data Input
SDFM-1 Channel 4 Data Input
SDFM-2 Channel 1 Clock Input
31
36
I
23
SD1_C2
I
31
SD1_C3
I
38
SD1_C4
I
40
SD1_D1
I
19
SD1_D2
I
20
8
9
SD1_D3
I
21
SD1_D4
I
22
10
SD2_C1
I
14, 37
16, 4
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-2. Analog Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
SD2_C2
SD2_C3
SD2_C4
SD2_D1
SD2_D2
SD2_D3
SD2_D4
VDAC
I
I
I
I
I
I
I
I
SDFM-2 Channel 2 Clock Input
SDFM-2 Channel 3 Clock Input
SDFM-2 Channel 4 Clock Input
SDFM-2 Channel 1 Data Input
SDFM-2 Channel 2 Data Input
SDFM-2 Channel 3 Data Input
SDFM-2 Channel 4 Data Input
36
28
48
27
22
23
18
23
18
19
14
14
12
13
11
12
10
8
10
8
7
5
6
4
5
16
17
15
16
9
9
7
7
Optional external reference voltage
for on-chip DACs.
8
8
VREFHI
I
ADC High Reference. In external
reference mode, externally drive the
high reference voltage onto this pin.
In internal reference mode, a voltage
is driven onto this pin by the device.
In either mode, place at least a
24, 25
20
16
16
12
2.2-µF capacitor on this pin. This
capacitor should be placed as close
to the device as possible between
the VREFHI and VREFLO pins.
VREFLO
I
ADC Low Reference
26, 27
21
17
17
13
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
5.3.2 Digital Signals
Table 5-3. Digital Signals
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
33, 53, 8
10, 32, 54
29
100 PZ PIN
12, 53, 74
13, 64, 93
100
80 PN PIN
38, 58
49, 76
3
64 PM PIN
32, 47
40, 63
1
64 PMQ PIN
32, 47
40, 63
1
48 PT PIN
ADCSOCAO
ADCSOCBO
AUXCLKIN
CANA_RX
O
O
ADC Start of Conversion A for External ADC
ADC Start of Conversion B for External ADC
25
32
1
I
CAN-A Receive
CAN-A Transmit
12, 18, 3, 30, 33,
35, 49, 5, 53, 59,
61
12, 51, 53, 63, 68,
76, 8, 89, 91, 92,
98
1, 36, 38, 48, 50,
60, 74
30, 32, 39, 41, 49, 30, 32, 39, 41, 49,
61 61
25, 31, 33, 39, 47
CANA_TX
O
13, 17, 19, 2, 31,
32, 37, 4, 48, 58
50, 55, 61, 64, 67,
69, 7, 75, 77, 99
2, 35, 40, 46, 49,
51, 59, 61
29, 34, 37, 40, 42, 29, 34, 37, 40, 42,
29, 32, 34, 38, 40
48, 50
42, 56
46, 57
54
48, 50
42, 56
57
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
EPWM1_A
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
CLB Output X-BAR Output 1
CLB Output X-BAR Output 2
CLB Output X-BAR Output 3
CLB Output X-BAR Output 4
CLB Output X-BAR Output 5
CLB Output X-BAR Output 6
CLB Output X-BAR Output 7
CLB Output X-BAR Output 8
ePWM-1 Output A
19, 22
39, 47, 7
23, 42, 44
10, 43, 45
5, 52, 8
15, 4, 53
1, 14, 56
57, 6
69, 83
6, 84
51, 67
56, 68
57, 65, 69
54, 73, 76
58, 74
59, 78
62, 79
63, 80
1, 63
34
43
81, 85
54
93
63
63
11, 74, 89
12, 75, 95
65, 78, 96
66, 79, 97
79, 98
47, 61
48
47, 61
48
47
38
51
51
41
52, 64
52
52, 64
52
42, 48
42
30
EPWM1_B
ePWM-1 Output B
1, 31
78, 99
2, 62
51
51
41
EPWM2_A
ePWM-2 Output A
2, 41
77, 82
61, 66
60, 64
59, 79
74, 78
67, 80
65, 68
39, 58
40, 48, 75
50, 76
37, 51
36, 4
50, 55
49, 53
48
50, 55
49, 53
48
40
EPWM2_B
ePWM-2 Output B
3, 40
76, 80
39
EPWM3_A
ePWM-3 Output A
14, 4
75, 96
38
EPWM3_B
ePWM-3 Output B
15, 5
89, 95
61
61
47
EPWM4_A
ePWM-4 Output A
22, 6
83, 97
56, 64
54, 57
33, 47
34, 39, 62
41, 63
31, 42
2, 30
1, 29
35
56, 64
54, 57
33, 47
34, 39, 62
41, 63
31, 42
2, 30
1, 29
35
48
EPWM4_B
ePWM-4 Output B
23, 7
81, 84
43
EPWM5_A
ePWM-5 Output A
16, 8
54, 74
26
EPWM5_B
ePWM-5 Output B
17, 35, 9
10, 18
11, 19
12, 28
13, 29
14, 24
15, 32
55, 63, 90
68, 93
31
EPWM6_A
ePWM-6 Output A
33
EPWM6_B
ePWM-6 Output B
52, 69
34
EPWM7_A
ePWM-7 Output A
1, 51
2
EPWM7_B
ePWM-7 Output B
100, 50
56, 96
3, 35
1
EPWM8_A
ePWM-8 Output A
41, 79
49, 78
27
EPWM8_B
ePWM-8 Output B
64, 95
40
40
32
EQEP1_A
eQEP-1 Input A
10, 20, 25, 28, 35,
40, 44, 50, 56, 6
1, 48, 57, 63, 65,
80, 85, 9, 93, 97
33, 4, 42, 48, 64,
69, 76, 80
2, 39, 53, 63, 64
2, 39, 53, 63, 64
2, 31, 48
EQEP1_B
I
eQEP-1 Input B
eQEP-1 Index
eQEP-1 Strobe
11, 21, 29, 37, 41, 10, 100, 49, 52, 61, 3, 34, 37, 46, 66,
1, 31, 37, 55, 57
1, 31, 37, 55, 57
29, 34, 52, 54, 62
30, 33, 47, 56
1, 29, 43
42
51, 57, 7
66, 82, 84
68
EQEP1_INDEX
EQEP1_STROBE
I/O
I/O
13, 17, 23, 31, 39, 12, 50, 55, 79, 81,
43, 53, 59, 9 90, 92, 99
2, 35, 40, 54, 56,
63, 65, 75
29, 34, 46, 52, 54,
62
12, 16, 22, 30, 42, 11, 51, 54, 67, 74,
52, 58, 8 83, 98
1, 36, 39, 57, 58,
67
30, 33, 47, 56
26
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-3. Digital Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
37, 41, 50, 79
38, 39, 42, 51, 78
64 PM PIN
31, 35, 41
32, 33, 42
64 PMQ PIN
31, 35, 41
32, 33, 42
48 PT PIN
27, 33
EQEP2_A
EQEP2_B
I
I
eQEP-2 Input A
eQEP-2 Input B
11, 14, 18, 24, 54
13, 52, 56, 68, 96
15, 16, 19, 25, 33, 43, 53, 54, 57, 69,
25, 26, 34
55
95
EQEP2_INDEX
EQEP2_STROBE
ERRORSTS
I/O
I/O
O
eQEP-2 Index
eQEP-2 Strobe
26, 29, 39, 57
27, 28, 4, 56
24, 28, 29, 55
100, 58, 66
1, 59, 65, 75
1, 100, 43, 56
3, 43, 56
4, 44, 59
3, 4, 41
1, 46
2, 48
1
1
2, 48
2, 38
Error Status Output. This signal requires an
external pulldown.
1, 2, 35
1, 2, 35
1, 2, 27
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
I
I
I
FSIRX-A Input Clock
13, 30, 33, 39, 4,
54, 57
13, 50, 53, 66, 75,
79, 98
1, 35, 38, 56, 59,
63
29, 32, 46, 48, 52
30, 40, 49, 53
31, 50, 55
29, 32, 48, 52
30, 40, 49, 53
31, 50, 55
25, 38, 42
32, 39
40
FSIRX-A Primary Data Input
FSIRX-A Optional Additional Data Input
12, 3, 32, 40, 44,
52, 58
11, 51, 64, 67, 76,
80, 85
36, 49, 60, 64, 69
11, 2, 31, 41, 53,
56
12, 52, 65, 77, 82,
99
2, 37, 61, 66
FSITXA_CLK
O
O
O
I
FSITX-A Output Clock
10, 27, 44, 51, 7
26, 45, 49, 6, 9
25, 46, 5, 50, 6, 8
18, 47, 8
10, 59, 84, 85, 93
58, 8, 90, 97
57, 74, 89, 9, 97
6, 68, 74
44, 68, 69, 76
43, 73, 75, 80
42, 58, 6, 74, 80
50, 58
57, 63
62, 64
47, 61, 64
41, 47
42, 63
51
57, 63
62, 64
47, 61, 64
41, 47
42, 63
51
43
48
FSITXA_D0
FSITX-A Primary Data Output
FSITXA_D1
FSITX-A Optional Additional Data Output
FSITX-A Time Division Multiplexed Clock Input
FSITX-A Time Division Multiplexed Data Input
47, 48
33
FSITXA_TDM_CLK
FSITXA_TDM_D0
FSITXA_TDM_D1
I
10, 19
69, 93
51, 76
34
I
FSITX-A Time Division Multiplexed Additional Data
Input
1, 54, 59
13, 78, 92
62
41
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-Purpose Input Output 0
General-Purpose Input Output 1
General-Purpose Input Output 2
General-Purpose Input Output 3
General-Purpose Input Output 4
General-Purpose Input Output 5
General-Purpose Input Output 6
General-Purpose Input Output 7
General-Purpose Input Output 8
General-Purpose Input Output 9
General-Purpose Input Output 10
General-Purpose Input Output 11
General-Purpose Input Output 12
General-Purpose Input Output 13
General-Purpose Input Output 14
General-Purpose Input Output 15
General-Purpose Input Output 16
General-Purpose Input Output 17
General-Purpose Input Output 18
General-Purpose Input Output 19
General-Purpose Input Output 20
General-Purpose Input Output 21
79
78
77
76
75
89
97
84
74
90
93
52
51
50
96
95
54
55
68
69
48
49
63
62
61
60
59
74
80
68
58
75
76
37
36
35
79
78
39
40
50
51
33
34
52
51
50
49
48
61
64
57
47
62
63
31
30
29
52
51
50
49
48
61
64
57
47
62
63
31
30
29
42
41
40
39
38
47
48
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
33
34
41
42
33
34
41
42
26
33
34
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-3. Digital Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
General-Purpose Input Output 22
General-Purpose Input Output 23
General-Purpose Input Output 24
General-Purpose Input Output 25
General-Purpose Input Output 26
General-Purpose Input Output 27
General-Purpose Input Output 28
General-Purpose Input Output 29
General-Purpose Input Output 30
General-Purpose Input Output 31
General-Purpose Input Output 32
General-Purpose Input Output 33
General-Purpose Input Output 34
General-Purpose Input Output 35
General-Purpose Input Output 37
General-Purpose Input Output 39
General-Purpose Input Output 40
General-Purpose Input Output 41
General-Purpose Input Output 42
General-Purpose Input Output 43
General-Purpose Input Output 44
General-Purpose Input Output 45
General-Purpose Input Output 46
General-Purpose Input Output 47
General-Purpose Input Output 48
General-Purpose Input Output 49
General-Purpose Input Output 50
General-Purpose Input Output 51
General-Purpose Input Output 52
General-Purpose Input Output 53
General-Purpose Input Output 54
General-Purpose Input Output 55
General-Purpose Input Output 56
General-Purpose Input Output 57
General-Purpose Input Output 58
General-Purpose Input Output 59
General-Purpose Input Output 60
General-Purpose Input Output 61
HIC Address 0
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO37
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO60
GPIO61
HIC_A0
HIC_A1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
22
83
81
56
57
58
59
1
67
65
41
42
43
44
4
56
54
35
56
54
35
23
24
27
25
26
27
28
2
1
2
1
2
1
29
100
98
99
64
53
94
63
61
3
30
1
31
2
32
49
38
77
48
46
56
64
66
57
54
69
73
6
40
32
40
32
32
25
33
34
35
39
37
46
53
55
39
37
31
29
37
39
40
80
82
53
55
41
42
43
44
85
45
46
47
6
48
7
49
8
9
50
51
10
52
11
53
12
54
13
55
43
56
65
57
66
58
67
59
92
60
44
61
91
55, 60, 8
2, 26
43, 44, 74
58, 77
58
47
50
47
50
I
HIC Address 1
43, 61
40
Copyright © 2021 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-3. Digital Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
62
64 PM PIN
64 PMQ PIN
48 PT PIN
HIC_A2
I
I
HIC Address 2
HIC Address 3
HIC Address 4
HIC Address 5
HIC Address 6
HIC Address 7
1
78
51
51
41
HIC_A3
23
81
65
54
54
HIC_A4
I
27, 41
22
59, 82
83
44, 66
67
55
55
HIC_A5
I
56
56
HIC_A6
I
42, 47, 7
43, 48, 5
25, 9
6, 84
57, 68
54, 74
42, 75
63
57
57
43
47
HIC_A7
I
7, 89
61
61
HIC_BASESEL0
HIC_BASESEL1
HIC_BASESEL2
HIC_D0
I
HIC Base address range select 0
HIC Base address range select 1
HIC Base address range select 2
HIC Data 0
57, 90
79
62
62
I
52
52
42
38
25
26
I
4
26, 33
75
59
48
48
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
53, 58
54, 59
55, 8
38, 43
39, 44
40, 57
41, 54
60, 74
35, 64, 69
37, 73
56, 63, 69
1, 58
32
32
HIC_D1
HIC Data 1
16, 27
33
34
33
HIC_D2
HIC Data 2
17, 42, 49
24, 43, 50
3, 5, 57
13, 40, 44
11, 45, 51, 56
39, 44
34
HIC_D3
HIC Data 3
56, 9
35
35
49, 61
29, 53
31
27
HIC_D4
HIC Data 4
66, 76, 89
50, 80, 85
10, 52, 65
79, 85
74, 98
77, 94
78, 99
50, 81
82, 95
51, 83
84, 97
89, 96
51, 64, 68
52, 69
80, 94, 97
100
49, 61
29, 53
31
39, 47
HIC_D5
HIC Data 5
HIC_D6
HIC Data 6
HIC_D7
HIC Data 7
46, 52
47
52
42
HIC_D8
HIC Data 8
30, 8
47
HIC_D9
HIC Data 9
2, 34
61, 77
2, 62
50
50
40
41
HIC_D10
HIC_D11
HIC_D12
HIC_D13
HIC_D14
HIC_D15
HIC_INT
HIC_NBE0
HIC_NBE1
HIC_NCS
HIC_NOE
HIC_NRDY
HIC_NWE
I2CA_SCL
HIC Data 10
1, 31
51
51
HIC Data 11
13, 23
35, 65
66, 78
36, 67
68, 80
74, 79
36, 49, 50
37, 51
64, 77, 80
3
29, 54
55
29, 54
55
HIC Data 12
15, 41
HIC Data 13
12, 22
30, 56
57, 64
61
30, 56
57, 64
61
HIC Data 14
6, 7
43, 48
HIC Data 15
14, 5
47
HIC Device interrupt to host
HIC Byte enable 0
HIC Byte enable 1
HIC Chip select input
HIC Output enable for data bus
HIC Ready from device to host
HIC Data Write enable from host
I2C-A Open-Drain Bidirectional Clock
12, 18, 32
11, 19
30, 40, 41
31, 42
53, 64
1
30, 40, 41
31, 42
53, 64
1
32, 33
I
34
I
34, 40, 6
29
48
I
1
2, 39
O
28, 3
1, 76
4, 60
2, 49
2, 49
O
37, 58, 9
10, 35, 4, 46, 52
61, 67, 90
11, 63, 75, 93
46, 75
48, 59, 6, 76
37, 62
39, 48, 63
32, 37, 41, 47, 51
37, 62
39, 48, 63
32, 37, 41, 47, 51
29
I
31, 38
I/OD
1, 18, 27, 33, 37,
43, 57, 8
53, 59, 61, 66, 68, 38, 44, 46, 50, 54,
74, 78 58, 62
25, 29, 33, 41
I2CA_SDA
I/OD
I2C-A Open-Drain Bidirectional Data
10, 19, 26, 32, 35, 58, 63, 64, 65, 69, 43, 48, 49, 51, 57,
39, 40, 42, 52, 63
39, 40, 42, 52, 63
31, 32, 34, 42
42, 56
79, 93
63, 76
I2CB_SCL
I2CB_SDA
LINA_RX
I/OD
I/OD
I
I2C-B Open-Drain Bidirectional Clock
I2C-B Open-Drain Bidirectional Data
LIN-A Receive
15, 29, 3, 51, 9
14, 2, 28, 34, 50
10, 100, 76, 90, 95
1, 77, 9, 94, 96
3, 60, 75, 78
4, 61, 77, 79
3, 38, 48, 57, 65
1, 49, 62
2, 50
1, 49, 62
2, 50
1, 39
2, 40
23, 29, 33, 35, 42,
47, 49, 59
100, 53, 6, 63, 8,
81, 92
1, 32, 39, 54
1, 32, 39, 54
1, 25, 31
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-3. Digital Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
LINA_TX
LINB_RX
LINB_TX
MCAN_RX
MCAN_TX
O
LIN-A Transmit
LIN-B Receive
LIN-B Transmit
22, 28, 32, 37, 46,
58
1, 61, 64, 67, 83
4, 46, 49, 6, 67
2, 37, 40, 56
2, 37, 40, 56
2, 29, 32
I
11, 13, 15, 19, 23, 43, 50, 52, 69, 81, 35, 37, 51, 65, 66, 29, 31, 42, 54, 55, 29, 31, 42, 54, 55,
41, 55, 9 82, 90, 95 75, 78 62 62
34
O
I
10, 12, 14, 18, 22, 13, 51, 56, 68, 80, 36, 41, 50, 64, 67, 30, 35, 41, 53, 56, 30, 35, 41, 53, 56,
24, 40, 44, 54
27, 33
42, 47
38, 41
83, 85, 93, 96
69, 76, 79
63
63
CAN/CAN FD Receive
CAN/CAN FD Transmit
12, 21, 30, 39, 47,
5, 51, 57, 61
10, 49, 51, 6, 66,
79, 89, 91, 98
1, 34, 36, 56, 63,
74
30, 46, 52, 61
30, 52, 61
O
1, 13, 20, 31, 4, 46, 44, 48, 50, 65, 75, 2, 33, 35, 59, 6, 62
29, 48, 51
29, 48, 51
50, 56, 60
78, 9, 99
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
O
O
O
Output X-BAR Output 1
Output X-BAR Output 2
Output X-BAR Output 3
2, 24, 34, 58
56, 67, 77, 94
13, 57, 61, 76, 92
41, 61, 77
42, 46, 60
35, 50
37, 49
48, 61
35, 50
37, 49
48, 61
27, 40
29, 39
38, 47
25, 3, 37, 54, 59
14, 26, 4, 48, 5, 55, 43, 44, 58, 7, 75,
43, 59, 74, 79
60
89, 96
OUTPUTXBAR4
O
Output X-BAR Output 4
15, 27, 33, 49, 6,
61
53, 59, 8, 91, 95,
97
38, 44, 78, 80
32, 64
32, 64
25, 48
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
PMBUSA_ALERT
O
O
Output X-BAR Output 5
28, 42, 7
29, 43, 9
1, 84
100, 90
4, 57, 68
3, 54, 75
2, 57
1, 62
2, 57
1, 62
2, 43
1
Output X-BAR Output 6
O
Output X-BAR Output 7
11, 16, 30, 44
17, 31, 45
52, 54, 85, 98
55, 99
1, 37, 39, 69
2, 40, 73
31, 33
34
31, 33
34
26
O
Output X-BAR Output 8
I/OD
PMBus-A Open-Drain Bidirectional Alert Signal
13, 19, 27, 37, 43,
45
50, 59, 61, 69
35, 44, 46, 51, 54,
73
29, 37, 42
29, 37, 42
29, 34
31, 33
PMBUSA_CTL
PMBUSA_SCL
PMBUSA_SDA
SCIA_RX
I/O
I/OD
I/OD
I
PMBus-A Control Signal - Slave Input/Master
Output
12, 18, 26, 35, 42,
44
51, 58, 63, 68, 85
36, 43, 48, 50, 57,
69
30, 39, 41
30, 39, 41
PMBus-A Open-Drain Bidirectional Clock
PMBus-A Open-Drain Bidirectional Data
SCI-A Receive Data
15, 16, 24, 3, 35,
41, 47
54, 56, 6, 63, 76,
82, 95
39, 41, 48, 60, 66,
78
33, 35, 39, 49, 55
34, 40, 50, 53
33, 35, 39, 49, 55
34, 40, 50, 53
26, 27, 31, 39
32, 40
14, 17, 2, 25, 32,
34, 40, 44, 46, 48
55, 57, 64, 7, 77,
80, 85, 94, 96
40, 42, 49, 6, 61,
64, 69, 77, 79
17, 25, 28, 3, 35, 1, 55, 57, 63, 76, 8, 4, 40, 42, 48, 60,
2, 34, 39, 49, 62
2, 34, 39, 49, 62
2, 31, 39
1, 26, 27, 29, 40
34
49, 9
90
75
SCIA_TX
O
SCI-A Transmit Data
16, 2, 24, 29, 37,
48, 8
100, 54, 56, 61, 7,
74, 77
3, 39, 41, 46, 58,
61
1, 33, 35, 37, 47,
50
1, 33, 35, 37, 47,
50
SCIB_RX
I
SCI-B Receive Data
11, 13, 15, 19, 23, 50, 52, 66, 69, 81, 35, 37, 51, 65, 66,
41, 57 82, 95 78
29, 31, 42, 54, 55
29, 31, 42, 54, 55
SCIB_TX
O
SCI-B Transmit Data
10, 12, 14, 18, 22, 51, 65, 68, 80, 83, 36, 50, 64, 67, 75, 30, 41, 53, 56, 62, 30, 41, 53, 56, 62,
33
40, 56, 9
17, 33, 49, 53
19, 33, 51, 54
21, 53, 55
23, 55, 56
16, 48
90, 93, 96
12, 53, 55, 8
10, 13, 53, 69
12, 43, 49
43, 65, 81
54, 7
76, 79
38, 40
38, 51
34
63
63
SD1_C1
SD1_C2
SD1_C3
SD1_C4
SD1_D1
SD1_D2
SD1_D3
SD1_D4
SD2_C1
I
I
I
I
I
I
I
I
I
SDFM-1 Channel 1 Clock Input
SDFM-1 Channel 2 Clock Input
SDFM-1 Channel 3 Clock Input
SDFM-1 Channel 4 Clock Input
SDFM-1 Channel 1 Data Input
SDFM-1 Channel 2 Data Input
SDFM-1 Channel 3 Data Input
SDFM-1 Channel 4 Data Input
SDFM-2 Channel 1 Clock Input
32, 34
32, 42
32, 34
32, 42
25
25, 34
65
54
33
54
33
39
26
18, 32, 50
20, 52
64, 68, 9
11, 48
49, 50
33
40, 41
40, 41
32, 33
22, 54
13, 83
67
56
39
56
39
25, 35, 57
57, 63, 66
42, 48
31
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-3. Digital Signals (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
SDFM-2 Channel 2 Clock Input
SDFM-2 Channel 3 Clock Input
SDFM-2 Channel 4 Clock Input
SDFM-2 Channel 1 Data Input
SDFM-2 Channel 2 Data Input
SDFM-2 Channel 3 Data Input
SDFM-2 Channel 4 Data Input
SPI-A Clock
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
SD2_C2
I
27, 58, 59
59, 67, 92
44
SD2_C3
I
I
29, 45, 59, 61
31, 46, 60
100, 91, 92
44, 99
3, 73
1
35
2
1
35
2
1
27
2
SD2_C4
2, 6
41
SD2_D1
I
24, 49, 56
56, 65, 8
SD2_D2
I
26, 50, 58
58, 67, 9
43
SD2_D3
I
28, 43, 51, 60
30, 47, 52
1, 10, 44
4, 54
SD2_D4
I
11, 6, 98
1
SPIA_CLK
SPIA_SIMO
SPIA_SOMI
SPIA_STE
SPIB_CLK
I/O
I/O
I/O
I/O
I/O
12, 18, 3, 56, 9
11, 16, 2, 54, 8
1, 10, 13, 17, 55
11, 19, 5, 57
51, 65, 68, 76, 90
13, 52, 54, 74, 77
43, 50, 55, 78, 93
52, 66, 69, 79, 89
36, 50, 60, 75
37, 39, 58, 61
35, 40, 62, 76
37, 51, 63, 74
30, 41, 49, 62
31, 33, 47, 50
29, 34, 51, 63
31, 42, 52, 61
2, 40, 48, 56
30, 41, 49, 62
31, 33, 47, 50
29, 34, 51, 63
31, 42, 52, 61
2, 40, 48, 56
33, 39
26, 40
SPI-A Slave In, Master Out (SIMO)
SPI-A Slave Out, Master In (SOMI)
SPI-A Slave Transmit Enable (STE)
SPI-B Clock
41
34, 42, 47
2, 32, 38
14, 22, 26, 28, 32,
4, 52, 58
1, 11, 58, 64, 67,
75, 83, 96
4, 43, 49, 59, 67,
79
SPIB_SIMO
SPIB_SOMI
SPIB_STE
I/O
I/O
I/O
SPI-B Slave In, Master Out (SIMO)
SPI-B Slave Out, Master In (SOMI)
SPI-B Slave Transmit Enable (STE)
External ePWM Synchronization Pulse
20, 24, 30, 40, 50, 44, 48, 56, 65, 80,
56, 60, 7 84, 9, 98
1, 33, 41, 64, 68
35, 53, 57
33, 55, 64
1, 32, 54
35, 53, 57
33, 55, 64
1, 32, 54
27, 43
26, 48
1, 25
16, 21, 25, 31, 41, 10, 49, 54, 57, 66,
51, 57, 6, 61 82, 91, 97, 99
2, 34, 39, 42, 66,
80
15, 23, 27, 29, 33, 100, 12, 53, 59, 81,
3, 38, 44, 65, 78
53, 59
39, 52, 6
35
92, 95
11, 97
63
SYNCOUT
TDI
O
I
56, 80
48
46, 64
39
64
39
48
31
JTAG Test Data Input (TDI) - TDI is the default mux
selection for the pin. The internal pullup is disabled
by default. The internal pullup should be enabled or
an external pullup added on the board if this pin is
used as JTAG TDI to avoid a floating input.
TDO
O
JTAG Test Data Output (TDO) - TDO is the default
mux selection for the pin. The internal pullup is
disabled by default. The TDO function will tristate
when there is no JTAG activity, leaving this pin
floating; the internal pullup should be enabled or
an external pullup added on the board to avoid a
floating GPIO input.
37
19
61
69
46
51
37
42
37
42
29
34
X1
I/O
Crystal oscillator input or single-ended clock input.
The device initialization software must configure
this pin before the crystal oscillator is enabled. To
use this oscillator, a quartz crystal circuit must be
connected to X1 and X2. This pin can also be used
to feed a single-ended 3.3-V level clock. See the
XTAL section for usage details.
X2
I/O
O
Crystal oscillator output.
18
68
50
41
41
33
XCLKOUT
External Clock Output. This pin outputs a divided-
down version of a chosen clock signal from within
the device.
16, 18
54, 68
39, 50
33, 41
33, 41
26, 33
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
5.3.3 Digital Signals by GPIO
Table 5-4. Digital Signals by GPIO
PIN
SIGNAL NAME
TYPE
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO8
GPIO33
GPIO53
ADC Start of Conversion A for External
ADC
GPIO8
GPIO8
GPIO8
ADCSOCAO
O
O
GPIO33
GPIO33 GPIO33 GPIO33
GPIO10
GPIO32
GPIO54
ADC Start of Conversion B for External
ADC
GPIO10 GPIO10 GPIO10
GPIO32 GPIO32 GPIO32
ADCSOCBO
AUXCLKIN
GPIO32
GPIO29 GPIO29 GPIO29 GPIO29 GPIO29
GPIO3
GPIO5
GPIO12
GPIO18
GPIO30 GPIO12
GPIO33 GPIO18
GPIO35/ GPIO30
GPIO3
GPIO5
GPIO3
GPIO5
GPIO12 GPIO12
GPIO18 GPIO18
GPIO33 GPIO33
GPIO35/ GPIO35/
GPIO3
GPIO5
GPIO3
GPIO5
GPIO18
GPIO33
GPIO35/
TDI
CANA_RX
I
CAN-A Receive
TDI
GPIO33
GPIO49 GPIO35/
TDI
TDI
GPIO53
GPIO59
GPIO61
TDI
GPIO2
GPIO4
GPIO13
GPIO17 GPIO13
GPIO19 GPIO17
GPIO31 GPIO19
GPIO32 GPIO31
GPIO37/ GPIO32
GPIO2
GPIO4
GPIO2
GPIO4
GPIO13 GPIO13
GPIO17 GPIO17 GPIO19
GPIO19 GPIO19 GPIO32
GPIO32 GPIO32 GPIO37/
GPIO37/ GPIO37/
TDO TDO
GPIO2
GPIO4
GPIO2
GPIO4
CANA_TX
O
CAN-A Transmit
TDO
TDO
GPIO48
GPIO58
GPIO37/
TDO
GPIO19 GPIO19 GPIO19 GPIO19
GPIO22 GPIO22 GPIO22 GPIO22
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
O
O
CLB Output X-BAR Output 1
CLB Output X-BAR Output 2
GPIO19
GPIO7
GPIO7
GPIO7
GPIO7
GPIO7
GPIO47 GPIO39 GPIO39
GPIO23
GPIO23
GPIO44
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
O
O
O
O
O
O
CLB Output X-BAR Output 3
CLB Output X-BAR Output 4
CLB Output X-BAR Output 5
CLB Output X-BAR Output 6
CLB Output X-BAR Output 7
CLB Output X-BAR Output 8
GPIO42 GPIO23 GPIO23
GPIO44
GPIO10
GPIO10 GPIO43 GPIO10 GPIO10
GPIO45
GPIO5
GPIO8
GPIO52
GPIO5
GPIO8
GPIO5
GPIO8
GPIO5
GPIO8
GPIO5
GPIO4
GPIO1
GPIO4
GPIO15
GPIO53
GPIO4
GPIO15
GPIO4
GPIO1
GPIO4
GPIO1
GPIO1
GPIO14
GPIO56
GPIO1
GPIO14
GPIO0
GPIO6
GPIO57
GPIO0
GPIO6
GPIO0
GPIO6
GPIO0
GPIO6
GPIO0
GPIO6
GPIO0
GPIO0
EPWM1_A
EPWM1_B
O
O
ePWM-1 Output A
ePWM-1 Output B
GPIO0
GPIO1
GPIO0
GPIO1
GPIO0
GPIO1
GPIO30 GPIO30
GPIO1 GPIO1
GPIO31 GPIO31
Copyright © 2021 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO16
GPIO2
GPIO2
GPIO2
GPIO2
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
O
O
O
O
O
O
O
ePWM-2 Output A
GPIO41 GPIO41 GPIO41 GPIO41
GPIO3 GPIO3 GPIO3 GPIO3
GPIO40 GPIO40 GPIO40 GPIO40
ePWM-2 Output B
ePWM-3 Output A
ePWM-3 Output B
ePWM-4 Output A
ePWM-4 Output B
ePWM-5 Output A
GPIO4
GPIO14 GPIO14
GPIO4
GPIO4
GPIO4
GPIO5 GPIO5
GPIO15 GPIO15
GPIO6 GPIO6
GPIO22 GPIO22 GPIO22 GPIO22
GPIO7 GPIO7 GPIO7 GPIO7
GPIO23 GPIO23 GPIO23 GPIO23
GPIO8 GPIO8 GPIO8 GPIO8
GPIO16 GPIO16 GPIO16 GPIO16
GPIO9 GPIO9 GPIO9 GPIO9
GPIO17 GPIO17 GPIO17 GPIO17 GPIO35/
GPIO5
GPIO6
GPIO5
GPIO6
EPWM5_B
O
ePWM-5 Output B
GPIO35/ GPIO35/ GPIO35/ GPIO35/
TDI TDI TDI TDI
TDI
GPIO10 GPIO10 GPIO10 GPIO10
GPIO18 GPIO18 GPIO18 GPIO18
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
EPWM8_A
EPWM8_B
O
O
O
O
O
O
ePWM-6 Output A
ePWM-6 Output B
ePWM-7 Output A
ePWM-7 Output B
ePWM-8 Output A
ePWM-8 Output B
GPIO18
GPIO19
GPIO28
GPIO29
GPIO11 GPIO11 GPIO11 GPIO11
GPIO19 GPIO19 GPIO19 GPIO19
GPIO12 GPIO12 GPIO12 GPIO12
GPIO28 GPIO28 GPIO28 GPIO28
GPIO13 GPIO13 GPIO13 GPIO13
GPIO29 GPIO29 GPIO29 GPIO29
GPIO14 GPIO14
GPIO24 GPIO24
GPIO24 GPIO24 GPIO24
GPIO32 GPIO32 GPIO32
GPIO15 GPIO15
GPIO32 GPIO32
GPIO6
GPIO10
GPIO6
GPIO20 GPIO10
GPIO25 GPIO20
GPIO28 GPIO25
GPIO35/ GPIO28
GPIO6
GPIO10 GPIO10
GPIO28 GPIO28 GPIO28
GPIO35/ GPIO35/ GPIO35/
TDI
GPIO6
GPIO6
EQEP1_A
I
eQEP-1 Input A
TDI
GPIO40
GPIO35/
TDI
TDI
TDI
GPIO40 GPIO40
GPIO44 GPIO40
GPIO50 GPIO44
GPIO56
GPIO7
GPIO11
GPIO7
GPIO7
GPIO11 GPIO11
GPIO29 GPIO29 GPIO29
GPIO37/ GPIO37/ GPIO37/
TDO
GPIO7
GPIO21 GPIO11
GPIO29 GPIO21
GPIO37/ GPIO29
TDO
GPIO41
GPIO7
EQEP1_B
I
eQEP-1 Input B
GPIO37/
TDO
TDO
TDO
GPIO41 GPIO41
GPIO51 GPIO41
GPIO57
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
48 PT
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
GPIO0
GPIO9
GPIO13 GPIO13
GPIO17 GPIO17 GPIO13
GPIO23 GPIO23 GPIO17
GPIO31 GPIO31 GPIO23
GPIO53 GPIO39 GPIO39
GPIO59 GPIO43
GPIO0
GPIO9
GPIO0
GPIO9
GPIO0
GPIO9
GPIO13
GPIO17
GPIO23
EQEP1_INDEX
I/O
I/O
eQEP-1 Index
GPIO0
GPIO8
GPIO8
GPIO12
GPIO12
GPIO8
GPIO8
GPIO16
GPIO22
GPIO30
GPIO52
GPIO58
GPIO16 GPIO12 GPIO12
GPIO22 GPIO16 GPIO16
GPIO30 GPIO22 GPIO22
GPIO42
EQEP1_STROBE
eQEP-1 Strobe
GPIO16
GPIO11
GPIO14
GPIO18
GPIO24
GPIO54
GPIO11
GPIO11 GPIO11
GPIO14
GPIO18
GPIO24
EQEP2_A
EQEP2_B
I
I
eQEP-2 Input A
eQEP-2 Input B
GPIO18 GPIO18
GPIO18
GPIO24 GPIO24
GPIO24
GPIO15
GPIO16
GPIO19
GPIO25
GPIO33
GPIO55
GPIO15
GPIO16 GPIO16 GPIO16 GPIO16
GPIO19 GPIO19 GPIO19 GPIO19
GPIO25 GPIO33 GPIO33 GPIO33
GPIO33
GPIO26 GPIO26
GPIO29 GPIO29
GPIO57 GPIO39
GPIO29
GPIO39
EQEP2_INDEX
I/O
I/O
eQEP-2 Index
GPIO29 GPIO29
GPIO4
GPIO4
GPIO27
GPIO27
GPIO28
GPIO28
GPIO56
GPIO4
GPIO4
GPIO4
EQEP2_STROBE
eQEP-2 Strobe
GPIO28 GPIO28 GPIO28
GPIO24
GPIO24 GPIO24 GPIO24 GPIO24
GPIO28 GPIO28 GPIO28 GPIO28
GPIO29 GPIO29 GPIO29 GPIO29
Error Status Output. This signal requires an GPIO28
ERRORSTS
O
external pulldown.
GPIO29
GPIO55
GPIO0
GPIO4
GPIO0
GPIO0
GPIO4
GPIO13
GPIO30
GPIO33
GPIO39
GPIO0
GPIO4
GPIO13
GPIO33
GPIO13
GPIO30
GPIO33
GPIO54
GPIO57
GPIO4
GPIO13
GPIO33
GPIO39
GPIO0
GPIO4
GPIO33
FSIRXA_CLK
I
FSIRX-A Input Clock
GPIO3
GPIO12
GPIO3
GPIO3
GPIO12 GPIO12
GPIO32 GPIO32 GPIO32
GPIO40 GPIO40
GPIO3
GPIO32 GPIO12
GPIO40 GPIO32
GPIO44 GPIO40
GPIO52 GPIO44
GPIO58
GPIO3
FSIRXA_D0
FSIRXA_D1
I
I
FSIRX-A Primary Data Input
GPIO2
GPIO11
GPIO31 GPIO11
GPIO41 GPIO31
GPIO53 GPIO41
GPIO56
GPIO2
GPIO2
GPIO11 GPIO11
GPIO41 GPIO41
GPIO2
FSIRX-A Optional Additional Data Input
GPIO2
Copyright © 2021 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO7
GPIO10
GPIO27
GPIO44
GPIO51
GPIO7
GPIO10
GPIO27 GPIO10 GPIO10
GPIO44
GPIO7
GPIO7
FSITXA_CLK
FSITXA_D0
FSITXA_D1
O
O
O
FSITX-A Output Clock
GPIO7
GPIO6
GPIO9
GPIO26 GPIO26
GPIO49 GPIO45
GPIO6
GPIO9
GPIO6
GPIO9
GPIO6
GPIO9
FSITX-A Primary Data Output
GPIO6
GPIO5
GPIO6
GPIO8
GPIO25 GPIO25
GPIO50 GPIO46
GPIO5
GPIO6
GPIO8
GPIO5
GPIO6
GPIO8
GPIO5
GPIO6
GPIO8
GPIO5
GPIO6
FSITX-A Optional Additional Data Output
GPIO8
GPIO8
GPIO18
GPIO47
FSITX-A Time Division Multiplexed Clock
Input
GPIO8
GPIO8
FSITXA_TDM_CLK
FSITXA_TDM_D0
FSITXA_TDM_D1
I
I
I
GPIO18
GPIO19
GPIO1
GPIO18 GPIO18 GPIO18
FSITX-A Time Division Multiplexed Data
Input
GPIO10 GPIO10 GPIO10 GPIO10
GPIO19 GPIO19 GPIO19 GPIO19
GPIO1
FSITX-A Time Division Multiplexed
Additional Data Input
GPIO54
GPIO59
GPIO1
GPIO1
GPIO1
GPIO8
GPIO55
GPIO60
A6
GPIO8
A6
GPIO8
A6
GPIO8
A6
HIC_A0
HIC_A1
I
I
HIC Address 0
HIC Address 1
A6
GPIO2
GPIO26 GPIO26
B2/C6
GPIO2
GPIO2
B2/C6
GPIO2
B2/C6
GPIO2
B2/C6
B2/C6
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
HIC_A2
HIC_A3
I
I
HIC Address 2
HIC Address 3
B3/VDAC B3/VDAC B3/VDAC B3/VDAC B3/VDAC
GPIO23 GPIO23 GPIO23 GPIO23
A2/B6/C9
A2/B6/C9 A2/B6/C9 A2/B6/C9 A2/B6/C9
GPIO27
GPIO41
A15
GPIO27
GPIO41
GPIO41 GPIO41
A15 A15
HIC_A4
HIC_A5
I
I
HIC Address 4
HIC Address 5
A15
GPIO22 GPIO22 GPIO22 GPIO22
A14/B14/ A14/B14/ A14/B14/ A14/B14/
C4
C4
C4
C4
GPIO7
GPIO47 GPIO42
A11/B10/ A11/B10/
GPIO7
GPIO7
GPIO7
GPIO7
HIC_A6
HIC_A7
I
I
HIC Address 6
HIC Address 7
A11/B10/ A11/B10/ A11/B10/
C0
C0
C0
C0
C0
GPIO5
GPIO48 GPIO43
C2/B12
GPIO5
GPIO5
C2/B12
GPIO5
C2/B12
GPIO5
C2/B12
C2/B12
GPIO9
GPIO9
GPIO9
A1/B7/
DACB_O DACB_O
GPIO9
A1/B7/
GPIO25 GPIO25
A1/B7/ A1/B7/
DACB_O DACB_O
A1/B7/
DACB_O
UT
HIC_BASESEL0
HIC_BASESEL1
I
I
HIC Base address range select 0
HIC Base address range select 1
UT
UT
UT
UT
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
A0/B15/C A0/B15/C A0/B15/C A0/B15/C A0/B15/C
15/ 15/ 15/ 15/ 15/
DACA_O DACA_O DACA_O DACA_O DACA_O
UT UT UT UT UT
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO4
GPIO4
GPIO4
GPIO4
GPIO4
HIC_BASESEL2
I
HIC Base address range select 2
A10/B1/C A10/B1/C A10/B1/C A10/B1/C A10/B1/C
10 10 10 10 10
GPIO26 GPIO26
GPIO33 GPIO33
HIC_D0
HIC_D1
HIC_D10
HIC_D11
HIC_D12
HIC_D13
HIC_D14
HIC_D15
HIC_D2
HIC_D3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
HIC Data 0
HIC Data 1
HIC Data 10
HIC Data 11
HIC Data 12
HIC Data 13
HIC Data 14
HIC Data 15
HIC Data 2
HIC Data 3
GPIO33 GPIO33 GPIO33
GPIO16 GPIO16 GPIO16
GPIO16 GPIO16
GPIO27 GPIO27
GPIO1
GPIO1
GPIO1
GPIO1
GPIO1
GPIO31 GPIO31
GPIO13 GPIO13 GPIO13 GPIO13
GPIO23 GPIO23 GPIO23 GPIO23
GPIO15 GPIO15
GPIO41 GPIO41
GPIO41 GPIO41
GPIO12 GPIO12 GPIO12 GPIO12
GPIO22 GPIO22 GPIO22 GPIO22
GPIO6
GPIO7
GPIO6
GPIO7
GPIO6
GPIO7
GPIO6
GPIO7
GPIO6
GPIO7
GPIO5
GPIO5
GPIO5
GPIO5
GPIO5
GPIO14 GPIO14
GPIO17 GPIO17
GPIO49 GPIO42
GPIO17 GPIO17
GPIO24 GPIO24 GPIO24
GPIO24 GPIO24
GPIO50 GPIO43
GPIO3
GPIO3
GPIO5
GPIO5
GPIO57
GPIO3
GPIO5
GPIO3
GPIO5
GPIO3
GPIO5
HIC_D4
HIC_D5
HIC_D6
HIC_D7
I/O
I/O
I/O
I/O
HIC Data 4
HIC Data 5
HIC Data 6
HIC Data 7
GPIO13 GPIO13
GPIO40 GPIO40
GPIO44 GPIO44
GPIO13 GPIO13
GPIO40 GPIO40
GPIO11
GPIO11
GPIO51
GPIO45
GPIO56
GPIO11 GPIO11
GPIO0
GPIO0
GPIO0
GPIO0
GPIO39
GPIO39
GPIO44
GPIO0
GPIO2
GPIO44
GPIO8
GPIO8
HIC_D8
HIC_D9
I/O
I/O
HIC Data 8
HIC Data 9
GPIO8
GPIO2
GPIO8
GPIO2
GPIO30 GPIO30
GPIO2 GPIO2
GPIO34 GPIO34
GPIO12 GPIO12 GPIO12 GPIO12
GPIO18 GPIO18 GPIO18 GPIO18
GPIO32 GPIO32 GPIO32 GPIO32
GPIO18
GPIO32
HIC_INT
O
I
HIC Device interrupt to host
HIC Byte enable 0
GPIO11 GPIO11 GPIO11 GPIO11
GPIO19 GPIO19 GPIO19 GPIO19
GPIO19
A9
HIC_NBE0
A9
A9
A9
A9
GPIO6
GPIO34 GPIO34
GPIO40 GPIO40
GPIO6
GPIO6
GPIO40 GPIO40
A8 A8
GPIO6
GPIO6
A8
HIC_NBE1
I
HIC Byte enable 1
A8
A8
GPIO29 GPIO29 GPIO29 GPIO29 GPIO29
HIC_NCS
HIC_NOE
I
HIC Chip select input
A12
A12
A12
A12
A12
GPIO3
GPIO3
GPIO3
GPIO3
GPIO3
O
HIC Output enable for data bus
GPIO28 GPIO28 GPIO28 GPIO28 GPIO28
C3/A7 C3/A7 C3/A7 C3/A7 C3/A7
Copyright © 2021 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO9
GPIO37/
TDO
GPIO9
GPIO9
GPIO9
GPIO37/
TDO
HIC_NRDY
HIC_NWE
O
HIC Ready from device to host
GPIO37/ GPIO37/ GPIO37/
TDO
TDO
TDO
GPIO58
GPIO4
GPIO10 GPIO10
GPIO35/ GPIO35/
GPIO4
GPIO4
GPIO10 GPIO10
GPIO35/ GPIO35/
TDI
A4/B8
GPIO4
GPIO4
GPIO35/
TDI
I
HIC Data Write enable from host
TDI
TDI
TDI
A4/B8
GPIO52 GPIO46
A4/B8
A4/B8
A4/B8
GPIO1
GPIO8
GPIO18 GPIO18
GPIO27 GPIO27 GPIO18 GPIO18
GPIO33 GPIO33 GPIO33 GPIO33
GPIO37/ GPIO37/ GPIO37/ GPIO37/
GPIO1
GPIO8
GPIO1
GPIO8
GPIO1
GPIO8
GPIO1
GPIO18
GPIO33
GPIO37/
TDO
I2CA_SCL
I/OD
I2C-A Open-Drain Bidirectional Clock
TDO
TDO
TDO
TDO
GPIO57 GPIO43
GPIO0 GPIO0
GPIO10 GPIO10
GPIO19 GPIO19 GPIO10 GPIO10
GPIO26 GPIO26 GPIO19 GPIO19
GPIO32 GPIO32 GPIO32 GPIO32
GPIO35/ GPIO35/ GPIO35/ GPIO35/
GPIO0
GPIO0
GPIO0
GPIO19
GPIO32
GPIO35/
TDI
I2CA_SDA
I/OD
I2C-A Open-Drain Bidirectional Data
TDI
TDI
TDI
TDI
GPIO56 GPIO42
GPIO3
GPIO3
GPIO9
GPIO3
GPIO9
GPIO29 GPIO29
GPIO3
GPIO9
GPIO9
GPIO3
GPIO29
I2CB_SCL
I2CB_SDA
I/OD
I/OD
I2C-B Open-Drain Bidirectional Clock
I2C-B Open-Drain Bidirectional Data
GPIO15
GPIO15
GPIO29
GPIO29
GPIO51
GPIO2
GPIO2
GPIO14
GPIO14
GPIO28
GPIO2
GPIO2
GPIO2
GPIO28 GPIO28 GPIO28 GPIO28
GPIO34
GPIO34
GPIO50
GPIO23
GPIO29 GPIO23
GPIO33 GPIO29
GPIO35/ GPIO33
GPIO23 GPIO23
GPIO29 GPIO29
GPIO33 GPIO33
GPIO35/ GPIO35/
GPIO29
GPIO33
GPIO35/
TDI
LINA_RX
LINA_TX
LINB_RX
I
O
I
LIN-A Receive
LIN-A Transmit
LIN-B Receive
TDI
GPIO47
GPIO35/
TDI
TDI
TDI
GPIO49 GPIO42
GPIO59
GPIO22 GPIO22
GPIO28 GPIO28
GPIO32 GPIO32
GPIO37/ GPIO37/
GPIO22 GPIO22
GPIO28 GPIO28
GPIO32 GPIO32
GPIO37/ GPIO37/
GPIO28
GPIO32
GPIO37/
TDO
TDO
TDO
TDO
TDO
GPIO58 GPIO46
GPIO9
GPIO9
GPIO11
GPIO11
GPIO13
GPIO13
GPIO15
GPIO15
GPIO19
GPIO19
GPIO23
GPIO23
GPIO41
GPIO41
GPIO55
GPIO9
GPIO9
GPIO11 GPIO11
GPIO13 GPIO13
GPIO19 GPIO19
GPIO23 GPIO23
GPIO41 GPIO41
GPIO19
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
64 PMQ 48 PT
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO24
GPIO40
GPIO44
GPIO54
GPIO10
GPIO12 GPIO10 GPIO10
GPIO14 GPIO12 GPIO12
GPIO18 GPIO18 GPIO18 GPIO18
GPIO22 GPIO22 GPIO22 GPIO24
GPIO24 GPIO24 GPIO24
GPIO40 GPIO40 GPIO40
GPIO44
LINB_TX
O
LIN-B Transmit
GPIO0
GPIO5
GPIO0
GPIO5
GPIO12
GPIO21 GPIO12
GPIO30 GPIO39
GPIO39
GPIO12
GPIO21
GPIO30
GPIO47
GPIO51
GPIO57
GPIO61
GPIO0
GPIO5
GPIO0
GPIO5
GPIO12
GPIO0
GPIO5
MCAN_RX
I
CAN/CAN FD Receive
GPIO1
GPIO4
GPIO13
GPIO20 GPIO13
GPIO31 GPIO20
GPIO50 GPIO31
GPIO56 GPIO46
GPIO60
GPIO1
GPIO4
GPIO1
GPIO4
GPIO13 GPIO13
GPIO1
GPIO4
GPIO1
GPIO4
MCAN_TX
O
CAN/CAN FD Transmit
GPIO2
GPIO2
GPIO24
GPIO24
GPIO34
GPIO34
GPIO58
GPIO2
GPIO2
GPIO2
OUTPUTXBAR1
OUTPUTXBAR2
O
O
Output X-BAR Output 1
Output X-BAR Output 2
GPIO24 GPIO24 GPIO24
GPIO3
GPIO25
GPIO37/ GPIO25
TDO
GPIO54
GPIO59
GPIO3
GPIO3
GPIO3
GPIO3
GPIO37/ GPIO37/ GPIO37/
TDO
GPIO37/
TDO
TDO
TDO
GPIO4
GPIO5
GPIO4
GPIO5
GPIO14
GPIO26
GPIO14
GPIO26
GPIO48
GPIO55
GPIO60
GPIO4
GPIO5
GPIO4
GPIO5
GPIO4
GPIO5
OUTPUTXBAR3
OUTPUTXBAR4
O
O
Output X-BAR Output 3
Output X-BAR Output 4
GPIO6
GPIO15
GPIO27 GPIO15
GPIO6
GPIO6
GPIO6
GPIO6
GPIO33 GPIO27 GPIO33 GPIO33 GPIO33
GPIO49 GPIO33
GPIO61
GPIO7
GPIO28
GPIO42
GPIO7
GPIO28
GPIO7
GPIO7
GPIO7
OUTPUTXBAR5
OUTPUTXBAR6
O
O
Output X-BAR Output 5
Output X-BAR Output 6
GPIO28 GPIO28 GPIO28
GPIO9
GPIO29
GPIO43
GPIO9
GPIO29
GPIO9
GPIO29 GPIO29
GPIO9
GPIO29
GPIO16
GPIO11 GPIO11
GPIO16 GPIO16 GPIO11 GPIO11
GPIO30 GPIO30 GPIO16 GPIO16
GPIO44 GPIO44
OUTPUTXBAR7
O
Output X-BAR Output 7
Copyright © 2021 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO17
GPIO31 GPIO17 GPIO17
GPIO45
GPIO17
GPIO31
OUTPUTXBAR8
O
Output X-BAR Output 8
GPIO13
GPIO13 GPIO19
GPIO19 GPIO27
GPIO27 GPIO37/
GPIO13 GPIO13
GPIO19 GPIO19
GPIO37/ GPIO37/
GPIO19
GPIO37/
TDO
PMBus-A Open-Drain Bidirectional Alert
Signal
PMBUSA_ALERT
I/OD
GPIO37/
TDO
TDO
GPIO43
GPIO45
TDO
TDO
GPIO12
GPIO18
GPIO26
GPIO35/
TDI
GPIO12
GPIO18
GPIO26
GPIO35/
TDI
GPIO12 GPIO12
GPIO18 GPIO18
GPIO35/ GPIO35/
GPIO18
GPIO35/
TDI
PMBus-A Control Signal - Slave Input/
Master Output
PMBUSA_CTL
PMBUSA_SCL
I/O
TDI
TDI
GPIO42
GPIO44
GPIO44
GPIO3
GPIO15
GPIO16
GPIO24
GPIO35/
TDI
GPIO3
GPIO15
GPIO16
GPIO24
GPIO35/
TDI
GPIO3
GPIO3
GPIO3
GPIO16
GPIO24
GPIO35/
TDI
GPIO16 GPIO16
GPIO24 GPIO24
GPIO35/ GPIO35/
I/OD
PMBus-A Open-Drain Bidirectional Clock
PMBus-A Open-Drain Bidirectional Data
SCI-A Receive Data
TDI
TDI
GPIO41
GPIO47
GPIO41 GPIO41
GPIO41
GPIO2
GPIO2
GPIO14 GPIO14
GPIO17 GPIO17
GPIO25 GPIO25
GPIO32 GPIO32
GPIO34 GPIO34
GPIO40 GPIO40
GPIO44 GPIO44
GPIO48 GPIO46
GPIO2
GPIO2
GPIO17 GPIO17
GPIO32 GPIO32 GPIO32
GPIO40 GPIO40
GPIO2
PMBUSA_SDA
I/OD
GPIO3
GPIO3
GPIO9
GPIO9
GPIO17
GPIO17
GPIO25
GPIO25
GPIO28
GPIO28
GPIO35/
GPIO35/
TDI
GPIO3
GPIO9
GPIO3
GPIO9
GPIO3
GPIO17 GPIO17 GPIO28
GPIO28 GPIO28 GPIO35/
GPIO35/ GPIO35/
SCIA_RX
I
TDI
TDI
TDI
TDI
GPIO49
GPIO2
GPIO2
GPIO8
GPIO8
GPIO16
GPIO2
GPIO8
GPIO2
GPIO8
GPIO2
GPIO16
GPIO24
GPIO29
GPIO37/
TDO
GPIO16 GPIO16 GPIO16
GPIO24 GPIO24 GPIO24
GPIO29 GPIO29 GPIO29
GPIO37/ GPIO37/ GPIO37/
GPIO24
GPIO29
GPIO37/
TDO
SCIA_TX
SCIB_RX
O
SCI-A Transmit Data
TDO
TDO
TDO
GPIO48
GPIO11
GPIO13
GPIO15
GPIO19
GPIO23
GPIO41
GPIO57
GPIO11
GPIO13
GPIO15
GPIO19
GPIO23
GPIO41
GPIO11 GPIO11
GPIO13 GPIO13
GPIO19 GPIO19 GPIO19
GPIO23 GPIO23
I
SCI-B Receive Data
GPIO41 GPIO41
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
48 PT
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
GPIO9
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO40
GPIO56
GPIO9
GPIO10
GPIO12
GPIO14
GPIO18
GPIO22
GPIO40
GPIO9
GPIO9
GPIO10 GPIO10
GPIO12 GPIO12
GPIO18 GPIO18
GPIO22 GPIO22
GPIO40 GPIO40
SCIB_TX
O
SCI-B Transmit Data
GPIO18
GPIO17
GPIO33 GPIO17 GPIO17 GPIO17
GPIO49 GPIO33 GPIO33 GPIO33
GPIO53 A0/B15/C A0/B15/C A0/B15/C
GPIO33
A0/B15/C
15/
DACA_O
UT
SD1_C1
I
SDFM-1 Channel 1 Clock Input
A0/B15/C
15/
15/
DACA_O DACA_O DACA_O
UT UT UT
15/
15/
DACA_O
UT
GPIO19
GPIO33 GPIO19 GPIO19 GPIO19 GPIO19
GPIO51 GPIO33 GPIO33 GPIO33 GPIO33
SD1_C2
SD1_C3
SD1_C4
SD1_D1
I
I
I
I
SDFM-1 Channel 2 Clock Input
SDFM-1 Channel 3 Clock Input
SDFM-1 Channel 4 Clock Input
SDFM-1 Channel 1 Data Input
GPIO54
C3/A7
C3/A7
C3/A7
C3/A7
C3/A7
GPIO21
GPIO53 GPIO21
A9
A9
A9
GPIO55
A9
A9
GPIO23
GPIO55 GPIO23 GPIO23 GPIO23
GPIO56 A10/B1/C A10/B1/C A10/B1/C
A10/B1/C
10
A10/B1/C
10
10
10
10
GPIO16
GPIO48
A14/B14/
C4
GPIO16 GPIO16 GPIO16
A14/B14/ A14/B14/ A14/B14/ GPIO16
C4 C4 C4
GPIO18
GPIO32
GPIO50
A11/B10/
C0
GPIO18 GPIO18 GPIO18 GPIO18
GPIO32 GPIO32 GPIO32 GPIO32
A11/B10/ A11/B10/ A11/B10/ A11/B10/
SD1_D2
SD1_D3
SD1_D4
I
I
I
SDFM-1 Channel 2 Data Input
SDFM-1 Channel 3 Data Input
SDFM-1 Channel 4 Data Input
C0
C0
C0
C0
GPIO20
GPIO52
C2/B12
GPIO20
C2/B12
C2/B12
C2/B12
C2/B12
GPIO22
GPIO54
A1/B7/
DACB_O
UT
GPIO22 GPIO22 GPIO22
A1/B7/ A1/B7/ A1/B7/
DACB_O DACB_O DACB_O
A1/B7/
DACB_O
UT
UT
UT
UT
GPIO25
GPIO35/
TDI
GPIO57
A6
GPIO25
GPIO35/
TDI
GPIO35/ GPIO35/ GPIO35/
TDI
A6
TDI
A6
TDI
A6
SD2_C1
SD2_C2
I
I
SDFM-2 Channel 1 Clock Input
SDFM-2 Channel 2 Clock Input
A6
A8
A8
A8
A8
A8
GPIO27
GPIO58 GPIO27
GPIO59
A4/B8
A4/B8
A4/B8
A4/B8
A4/B8
Copyright © 2021 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
48 PT
GPIO29
GPIO59
GPIO61
A12
GPIO29
GPIO45
A12
GPIO29 GPIO29 GPIO29
A12 A12 A12
SD2_C3
I
SDFM-2 Channel 3 Clock Input
GPIO31
GPIO60
B5
GPIO31
GPIO46
SD2_C4
SD2_D1
I
I
SDFM-2 Channel 4 Clock Input
SDFM-2 Channel 1 Data Input
GPIO24
GPIO49
GPIO56
GPIO24 GPIO24 GPIO24 GPIO24
A15 A15 A15 A15
GPIO26
GPIO50 GPIO26
GPIO58 B3/VDAC
B3/VDAC
SD2_D2
SD2_D3
SD2_D4
I
I
I
SDFM-2 Channel 2 Data Input
SDFM-2 Channel 3 Data Input
SDFM-2 Channel 4 Data Input
B3/VDAC B3/VDAC B3/VDAC
GPIO28
GPIO28
GPIO51
GPIO43
GPIO60
A2/B6/C9
A2/B6/C9
GPIO28 GPIO28 GPIO28
A2/B6/C9 A2/B6/C9 A2/B6/C9
GPIO30
GPIO47 GPIO30
B2/C6
B2/C6
B2/C6
GPIO52
B2/C6
B2/C6
GPIO3
GPIO9
GPIO12
GPIO18
GPIO56
GPIO3
GPIO9
GPIO3
GPIO9
GPIO3
GPIO9
GPIO3
SPIA_CLK
SPIA_SIMO
SPIA_SOMI
SPIA_STE
I/O
I/O
I/O
I/O
SPI-A Clock
GPIO12 GPIO12 GPIO12 GPIO18
GPIO18 GPIO18 GPIO18
GPIO2
GPIO8
GPIO11
GPIO16
GPIO54
GPIO2
GPIO8
GPIO2
GPIO8
GPIO2
GPIO8
GPIO2
SPI-A Slave In, Master Out (SIMO)
SPI-A Slave Out, Master In (SOMI)
SPI-A Slave Transmit Enable (STE)
GPIO11 GPIO11 GPIO11 GPIO16
GPIO16 GPIO16 GPIO16
GPIO1
GPIO10
GPIO13
GPIO17
GPIO55
GPIO1
GPIO1
GPIO1
GPIO10 GPIO10 GPIO10
GPIO13 GPIO13 GPIO13
GPIO17 GPIO17 GPIO17
GPIO1
GPIO0
GPIO5
GPIO11
GPIO19
GPIO57
GPIO0
GPIO5
GPIO0
GPIO5
GPIO0
GPIO5
GPIO0
GPIO5
GPIO19
GPIO11 GPIO11 GPIO11
GPIO19 GPIO19 GPIO19
GPIO4
GPIO14
GPIO4
GPIO22 GPIO14
GPIO4
GPIO4
GPIO4
GPIO28
GPIO32
GPIO26 GPIO22 GPIO22 GPIO22
GPIO28 GPIO26 GPIO28 GPIO28
GPIO32 GPIO28 GPIO32 GPIO32
GPIO52 GPIO32
SPIB_CLK
I/O
SPI-B Clock
GPIO58
GPIO7
GPIO20
GPIO24
GPIO7
GPIO20
GPIO24 GPIO24 GPIO24
GPIO30 GPIO40 GPIO40
GPIO40
GPIO7
GPIO7
GPIO30
GPIO40
GPIO50
GPIO56
GPIO60
GPIO7
GPIO24
SPIB_SIMO
I/O
SPI-B Slave In, Master Out (SIMO)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
48 PT
SPRSP61 – OCTOBER 2021
Table 5-4. Digital Signals by GPIO (continued)
PIN
TYPE
SIGNAL NAME
DESCRIPTION
100 PZ
80 PN
64 PM
64 PMQ
GPIO6
GPIO16
GPIO21
GPIO25
GPIO31
GPIO41
GPIO51
GPIO57
GPIO61
GPIO6
GPIO16
GPIO21
GPIO25
GPIO31
GPIO41
GPIO6
GPIO16 GPIO16
GPIO41 GPIO41
GPIO6
GPIO6
GPIO16
SPIB_SOMI
I/O
SPI-B Slave Out, Master In (SOMI)
GPIO15
GPIO23 GPIO15
GPIO27 GPIO23 GPIO23 GPIO23
GPIO29 GPIO27 GPIO29 GPIO29
GPIO33 GPIO29 GPIO33 GPIO33
GPIO53 GPIO33
GPIO29
GPIO33
SPIB_STE
SYNCOUT
TDI
I/O
O
I
SPI-B Slave Transmit Enable (STE)
External ePWM Synchronization Pulse
GPIO59
GPIO6
GPIO6
GPIO6
GPIO6
GPIO6
GPIO52 GPIO39 GPIO39
JTAG Test Data Input (TDI) - TDI is the
default mux selection for the pin. The
internal pullup is disabled by default. The
internal pullup should be enabled or an
external pullup added on the board if this
pin is used as JTAG TDI to avoid a floating
input.
GPIO35/ GPIO35/ GPIO35/ GPIO35/ GPIO35/
TDI TDI TDI TDI TDI
JTAG Test Data Output (TDO) - TDO is
the default mux selection for the pin. The
internal pullup is disabled by default. The
TDO function will tristate when there is no
JTAG activity, leaving this pin floating; the
internal pullup should be enabled or an
external pullup added on the board to avoid
a floating GPIO input.
GPIO37/ GPIO37/ GPIO37/ GPIO37/ GPIO37/
TDO TDO TDO TDO TDO
TDO
O
Crystal oscillator input or single-ended
clock input. The device initialization
software must configure this pin before the
crystal oscillator is enabled. To use this
oscillator, a quartz crystal circuit must be
connected to X1 and X2. This pin can
also be used to feed a single-ended 3.3-V
level clock. See the XTAL section for usage
details.
X1
I/O
GPIO19 GPIO19 GPIO19 GPIO19 GPIO19
GPIO18 GPIO18 GPIO18 GPIO18 GPIO18
X2
I/O
O
Crystal oscillator output.
External Clock Output. This pin outputs a
divided-down version of a chosen clock
signal from within the device.
GPIO16 GPIO16 GPIO16 GPIO16 GPIO16
GPIO18 GPIO18 GPIO18 GPIO18 GPIO18
XCLKOUT
Copyright © 2021 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.3.4 Power and Ground
Table 5-5. Power and Ground
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO PIN
100 PZ PIN
80 PN PIN
64 PM PIN
64 PMQ PIN
48 PT PIN
VDD
1.2-V Digital Logic Power Pins. See
the PMM section for usage details.
4, 46, 71, 87 31, 53, 71, 8 27, 4, 44, 59 27, 4, 44, 59
23, 36, 45
VDDA
3.3-V Analog Power Pins. Place
a minimum 2.2-µF decoupling
capacitor on each pin. See the PMM
section for usage details.
34
26
22
22
18
VDDIO
3.3-V Digital I/O Power Pins. See the
PMM section for usage details.
3, 47, 70, 88 32, 52, 7, 72
73
28, 43, 60
28, 43, 60
46
24, 35, 46
VREGENZ
I
Internal voltage regulator disable with
internal pulldown. Tie low to VSS to
enable internal VREG. Tie high to
VDDIO to use an external supply.
See the PMM section for usage
details.
VSS
Digital Ground
Analog Ground
45, 5, 72, 86 30, 55, 70, 9 26, 45, 5, 58 26, 45, 5, 58
22, 37, 44
17
VSSA
33
25
21
21
5.3.5 Test, JTAG, and Reset
Table 5-6. Test, JTAG, and Reset
SIGNAL NAME
TCK
PIN TYPE
DESCRIPTION
GPIO
100 PZ
80 PN
64 PM
64 PMQ
48 PT
JTAG test clock with internal
pullup.
I
60
45
36
36
28
JTAG test-mode select
(TMS) with internal pullup.
This serial control input
is clocked into the TAP
controller on the rising edge
of TCK. This device does
not have a TRSTn pin.
An external pullup resistor
(recommended 2.2 kΩ) on
the TMS pin to VDDIO
TMS
I/O
62
47
38
38
30
should be placed on the
board to keep JTAG in reset
during normal operation.
Crystal oscillator input or
single-ended clock input.
The device initialization
software must configure
this pin before the crystal
oscillator is enabled. To
use this oscillator, a quartz
crystal circuit must be
connected to X1 and X2.
This pin can also be used
to feed a single-ended 3.3-V
level clock.
X1
I/O
69
51
42
42
34
X2
I/O
Crystal oscillator output.
68
50
41
41
33
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
48 PT
SPRSP61 – OCTOBER 2021
Table 5-6. Test, JTAG, and Reset (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
GPIO
100 PZ
80 PN
64 PM
64 PMQ
Device Reset (in) and
Watchdog Reset (out).
During a power-on condition,
this pin is driven low by the
device. An external circuit
may also drive this pin to
assert a device reset. This
pin is also driven low by the
MCU when a watchdog reset
occurs. During watchdog
reset, the XRSn pin is driven
low for the watchdog reset
duration of 512 OSCCLK
cycles. A resistor between
2.2 kΩ and 10 kΩ should
be placed between XRSn
and VDDIO. If a capacitor is
placed between XRSn and
VSS for noise filtering, it
should be 100 nF or smaller.
These values will allow
XRSn
I/OD
2
5
3
3
3
the watchdog to properly
drive the XRSn pin to VOL
within 512 OSCCLK cycles
when the watchdog reset
is asserted. This pin is an
open-drain output with an
internal pullup.
Copyright © 2021 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.4 Pin Multiplexing
5.4.1 GPIO Muxed Pins
Section 5.4.1.1 lists the GPIO muxed pins. The default mode for each GPIO pin is the GPIO function, except
GPIO35 and GPIO37, which default to TDI and TDO, respectively. Secondary functions can be selected by
setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be
configured before the GPyMUXn to avoid transient pulses on GPIOs from alternate mux selections. Columns
that are not shown and blank cells are reserved GPIO Mux settings. GPIO ALT functions cannot be configured
with the GPyMUXn and GPyGMUXn registers. These are special functions that need to be configured from the
module.
Note
GPIO36 and GPIO38 do not exist on this device. GPIO62 to GPIO63 exist but are not pinned out on
any packages. Boot ROM enables pullups on GPIO62 to GPIO63. For more details, see Section 5.5.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
5.4.1.1 GPIO Muxed Pins
Table 5-7. GPIO Muxed Pins
0, 4, 8, 12
GPIO0
1
2
3
5
6
7
9
10
11
13
14
15
ALT
CLB_OUTPUTX
BAR8
EPWM1_A
I2CA_SDA
SPIA_STE
FSIRXA_CLK
MCAN_RX
EQEP1_INDEX
HIC_D7
HIC_BASESEL1
HIC_D10
CLB_OUTPUTX
BAR7
FSITXA_TDM_D
1
GPIO1
EPWM1_B
I2CA_SCL
SPIA_SOMI
MCAN_TX
HIC_A2
GPIO2
GPIO3
EPWM2_A
EPWM2_B
OUTPUTXBAR1 PMBUSA_SDA
SPIA_SIMO
SPIA_CLK
SCIA_TX
SCIA_RX
FSIRXA_D1
FSIRXA_D0
I2CB_SDA
I2CB_SCL
HIC_A1
CANA_TX
CANA_RX
HIC_D9
HIC_D4
OUTPUTXBAR2
OUTPUTXBAR4
SCIB_TX
OUTPUTXBAR2
OUTPUTXBAR3
PMBUSA_SCL
CANA_TX
HIC_NOE
EQEP2_STROB
E
CLB_OUTPUTX
BAR6
GPIO4
GPIO5
GPIO6
GPIO7
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
MCAN_TX
OUTPUTXBAR3
SYNCOUT
SPIB_CLK
SPIA_STE
SPIB_SOMI
SPIB_SIMO
FSIRXA_CLK
HIC_BASESEL2
HIC_A7
HIC_NWE
HIC_D15
HIC_D14
HIC_D14
CLB_OUTPUTX
BAR5
MCAN_RX
EQEP1_A
EQEP1_B
CANA_RX
FSITXA_D1
FSITXA_D0
FSITXA_CLK
I2CA_SCL
HIC_D4
CLB_OUTPUTX
BAR8
FSITXA_D1
HIC_NBE1
HIC_A6
CLB_OUTPUTX
BAR2
OUTPUTXBAR5
ADCSOCAO
EQEP1_STROB
E
CLB_OUTPUTX
BAR5
FSITXA_TDM_C
LK
GPIO8
EPWM5_A
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
SCIA_TX
SCIA_RX
SCIB_TX
SCIB_RX
SCIB_TX
SPIA_SIMO
SPIA_CLK
FSITXA_D1
FSITXA_D0
FSITXA_CLK
LINB_RX
HIC_A0
HIC_BASESEL0
HIC_NWE
HIC_D8
GPIO9
OUTPUTXBAR6 EQEP1_INDEX
LINB_RX
LINB_TX
I2CB_SCL
HIC_NRDY
FSITXA_TDM_D CLB_OUTPUTX
GPIO10
GPIO11
GPIO12
ADCSOCBO
OUTPUTXBAR7
MCAN_RX
EQEP1_A
EQEP1_B
SPIA_SOMI
SPIA_STE
I2CA_SDA
FSIRXA_D1
FSIRXA_D0
0
BAR4
EQEP2_A
SPIA_CLK
SPIA_SIMO
CANA_RX
HIC_D6
HIC_NBE0
EQEP1_STROB
E
PMBUSA_CTL
LINB_TX
HIC_D13
HIC_D11
HIC_INT
HIC_D5
PMBUSA_ALER
T
GPIO13
GPIO14
GPIO15
EPWM7_B
EPWM8_A
EPWM8_B
MCAN_TX
EQEP1_INDEX
I2CB_SDA
SCIB_RX
FSIRXA_CLK
SPIB_CLK
SPIB_STE
LINB_RX
EQEP2_A
EQEP2_B
SPIA_SOMI
LINB_TX
CANA_TX
EPWM3_A
EPWM3_B
EQEP2_B
CLB_OUTPUTX
BAR7
SCIB_TX
SCIB_RX
OUTPUTXBAR3 PMBUSA_SDA
HIC_D15
HIC_D12
CLB_OUTPUTX
BAR6
I2CB_SCL
OUTPUTXBAR4
PMBUSA_SCL
LINB_RX
EQEP1_STROB
E
GPIO16
GPIO17
GPIO18
SPIA_SIMO
SPIA_SOMI
SPIA_CLK
OUTPUTXBAR7
OUTPUTXBAR8
CANA_RX
EPWM5_A
EPWM5_B
EPWM6_A
SCIA_TX
SCIA_RX
I2CA_SCL
SD1_D1
SD1_C1
SD1_D2
PMBUSA_SCL
PMBUSA_SDA
PMBUSA_CTL
XCLKOUT
CANA_TX
XCLKOUT
SPIB_SOMI
HIC_D1
HIC_D2
HIC_INT
EQEP1_INDEX
EQEP2_A
FSITXA_TDM_C
LK
SCIB_TX
SCIB_RX
LINB_TX
LINB_RX
X2
X1
PMBUSA_ALER CLB_OUTPUTX
FSITXA_TDM_D
0
GPIO19
SPIA_STE
CANA_TX
EPWM6_B
I2CA_SDA
SD1_C2
EQEP2_B
HIC_NBE0
T
BAR1
GPIO20
GPIO21
EQEP1_A
EQEP1_B
SPIB_SIMO
SPIB_SOMI
SD1_D3
SD1_C3
MCAN_TX
MCAN_RX
EQEP1_STROB
E
CLB_OUTPUTX
BAR1
GPIO22
GPIO23
SCIB_TX
SCIB_RX
SPIB_CLK
SPIB_STE
SD1_D4
SD1_C4
LINA_TX
LINA_RX
LINB_TX
LINB_RX
HIC_A5
EPWM4_A
EPWM4_B
HIC_D13
CLB_OUTPUTX
BAR3
EQEP1_INDEX
HIC_A3
HIC_D11
HIC_D3
GPIO24
GPIO25
GPIO26
OUTPUTXBAR1
OUTPUTXBAR2
EQEP2_A
EQEP2_B
EPWM8_A
EQEP1_A
SPIB_SIMO
SPIB_SOMI
SPIB_CLK
SD2_D1
SD2_C1
SD2_D2
LINB_TX
FSITXA_D1
FSITXA_D0
PMBUSA_SCL
PMBUSA_SDA
PMBUSA_CTL
SCIA_TX
SCIA_RX
I2CA_SDA
ERRORSTS
HIC_BASESEL0
HIC_D0
OUTPUTXBAR3 EQEP2_INDEX
OUTPUTXBAR3
HIC_A1
Copyright © 2021 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
EQEP2_STROB
E
PMBUSA_ALER
T
GPIO27
OUTPUTXBAR4
OUTPUTXBAR4
SPIB_STE
SD2_C2
FSITXA_CLK
I2CA_SCL
HIC_D1
HIC_A4
EQEP2_STROB
E
GPIO28
GPIO29
GPIO30
SCIA_RX
SCIA_TX
CANA_RX
EPWM7_A
EPWM7_B
SPIB_SIMO
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
EQEP1_A
EQEP1_B
SD2_D3
SD2_C3
SD2_D4
LINA_TX
LINA_RX
MCAN_RX
SPIB_CLK
SPIB_STE
EPWM1_A
ERRORSTS
ERRORSTS
I2CB_SDA
I2CB_SCL
HIC_NOE
HIC_NCS
AUX
CLKI
N
EQEP2_INDEX
FSIRXA_CLK
EQEP1_STROB
E
HIC_D8
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
CANA_TX
I2CA_SDA
SPIB_SOMI
SPIB_CLK
SPIB_STE
OUTPUTXBAR8 EQEP1_INDEX
SD2_C4
SD1_D2
SD1_C2
FSIRXA_D1
FSIRXA_D0
FSIRXA_CLK
MCAN_TX
CANA_TX
CANA_RX
EPWM1_B
PMBUSA_SDA
EQEP2_B
HIC_D10
EPWM8_B
LINA_TX
LINA_RX
ADCSOCBO
ADCSOCAO
HIC_NBE1
SD2_C1
HIC_INT
HIC_D0
HIC_D9
TDI
I2CA_SCL
OUTPUTXBAR4
SD1_C1
I2CB_SDA
HIC_NWE
OUTPUTXBAR1
SCIA_RX
PMBUSA_SDA
PMBUSA_SCL
I2CA_SDA
I2CA_SCL
CANA_RX
SCIA_TX
LINA_RX
LINA_TX
EQEP1_A
EQEP1_B
PMBUSA_CTL
EPWM5_B
PMBUSA_ALER
T
GPIO37
GPIO39
OUTPUTXBAR2
CANA_TX
MCAN_RX
HIC_NRDY
TDO
CLB_OUTPUTX
BAR2
FSIRXA_CLK
EQEP2_INDEX
SYNCOUT
HIC_A4
EQEP1_INDEX
HIC_D7
GPIO40
GPIO41
SPIB_SIMO
EPWM2_B
EPWM2_A
PMBUSA_SDA
PMBUSA_SCL
FSIRXA_D0
FSIRXA_D1
SCIB_TX
SCIB_RX
EQEP1_A
EQEP1_B
LINB_TX
LINB_RX
HIC_NBE1
HIC_D5
SPIB_SOMI
HIC_D12
EQEP1_STROB CLB_OUTPUTX
GPIO42
GPIO43
GPIO44
LINA_RX
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
PMBUSA_CTL
I2CA_SDA
I2CA_SCL
HIC_D2
HIC_D3
LINB_TX
HIC_A6
HIC_A7
HIC_D5
E
BAR3
PMBUSA_ALER
T
PMBUSA_ALER
T
CLB_OUTPUTX
BAR4
EQEP1_INDEX
SD2_D3
HIC_D7
CLB_OUTPUTX
BAR3
EQEP1_A
PMBUSA_SDA
FSITXA_CLK
PMBUSA_CTL
FSIRXA_D0
PMBUSA_ALER CLB_OUTPUTX
GPIO45
GPIO46
GPIO47
OUTPUTXBAR8
LINA_TX
FSITXA_D0
FSITXA_D1
SD2_C3
SD2_C4
SD2_D4
HIC_D6
HIC_NWE
HIC_A6
T
BAR4
MCAN_TX
MCAN_RX
PMBUSA_SDA
CLB_OUTPUTX
BAR2
FSITXA_TDM_C
LK
LINA_RX
PMBUSA_SCL
GPIO48
GPIO49
GPIO50
GPIO51
OUTPUTXBAR3
OUTPUTXBAR4
EQEP1_A
CANA_TX
CANA_RX
SCIA_TX
SCIA_RX
SD1_D1
SD1_C1
SD1_D2
SD1_C2
PMBUSA_SDA
LINA_RX
HIC_A7
HIC_D2
HIC_D3
HIC_D6
SD2_D1
SD2_D2
SD2_D3
FSITXA_D0
FSITXA_D1
FSITXA_CLK
MCAN_TX
MCAN_RX
SPIB_SIMO
SPIB_SOMI
I2CB_SDA
I2CB_SCL
EQEP1_B
EQEP1_STROB
E
CLB_OUTPUTX
BAR5
GPIO52
GPIO53
SPIB_CLK
SPIB_STE
SD1_D3
SD1_C3
SYNCOUT
SD2_D4
SD1_C1
FSIRXA_D0
FSIRXA_D1
FSIRXA_CLK
HIC_NWE
CLB_OUTPUTX
BAR6
EQEP1_INDEX
ADCSOCAO
CANA_RX
FSITXA_TDM_D
1
GPIO54
GPIO55
GPIO56
SPIA_SIMO
SPIA_SOMI
SPIA_CLK
EQEP2_A
EQEP2_B
OUTPUTXBAR2
OUTPUTXBAR3
SCIB_TX
SD1_D4
SD1_C4
SD2_D1
ADCSOCBO
ERRORSTS
SPIB_SIMO
LINB_TX
LINB_RX
I2CA_SDA
SD1_C2
SD1_C3
SD1_C4
HIC_A0
HIC_D6
CLB_OUTPUTX
BAR7
EQEP2_STROB
E
MCAN_TX
MCAN_RX
EQEP1_A
EQEP1_B
FSIRXA_D1
CLB_OUTPUTX
BAR8
GPIO57
SPIA_STE
EQEP2_INDEX
SCIB_RX
SD2_C1
SPIB_SOMI
I2CA_SCL
FSIRXA_CLK
HIC_D4
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 5-7. GPIO Muxed Pins (continued)
0, 4, 8, 12
1
2
3
5
6
7
9
10
11
13
14
15
ALT
EQEP1_STROB
E
GPIO58
OUTPUTXBAR1
SPIB_CLK
SD2_D2
LINA_TX
CANA_TX
SD2_C2
FSIRXA_D0
HIC_NRDY
FSITXA_TDM_D
1
GPIO59
OUTPUTXBAR2
SPIB_STE
SD2_C2
LINA_RX
CANA_RX
EQEP1_INDEX
SD2_C3
SD2_C4
GPIO60
GPIO61
AIO224
AIO225
AIO226
AIO227
AIO228
AIO229
AIO230
AIO231
AIO232
AIO233
AIO236
AIO237
AIO238
AIO239
AIO240
AIO241
AIO242
AIO244
AIO245
AIO247
AIO248
AIO249
AIO251
AIO252
AIO253
MCAN_TX
MCAN_RX
OUTPUTXBAR3
OUTPUTXBAR4
SPIB_SIMO
SPIB_SOMI
SD2_D3
SD2_C3
HIC_A0
CANA_RX
SD2_D3
SD2_C2
SD2_D4
SD1_C3
SD2_C1
HIC_A3
HIC_NWE
HIC_A1
HIC_NBE0
HIC_A0
SD1_C4
SD1_C1
SD1_D4
SD2_D1
HIC_BASESEL2
HIC_BASESEL1
HIC_BASESEL0
HIC_A4
SD1_D2
SD2_C3
SD1_D1
SD2_C1
SD2_C1
SD2_D2
SD1_D3
SD1_C2
HIC_A6
HIC_NCS
HIC_A5
HIC_NBE1
HIC_NBE1
HIC_A2
HIC_A7
HIC_NOE
SD2_C4
Copyright © 2021 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.4.2 Digital Inputs on ADC Pins (AIOs)
GPIOs on port H (GPIO224–GPIO253) are multiplexed with analog pins. These are also referred to as AIOs.
These pins can only function in input mode. By default, these pins will function as analog pins and the GPIOs are
in a high-Z state. The GPHAMSEL register is used to configure these pins for digital or analog operation.
Note
If digital signals with sharp edges (high dv/dt) are connected to the AIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AIOs if
adjacent channels are being used for analog functions.
5.4.3 Digital Inputs and Outputs on ADC Pins (AGPIOs)
Some GPIOs on this device are multiplexed with analog pins. These are also referred to as AGPIOs. Unlike
AIOs, AGPIOs have full input and output capability. This device has two GPIOs (GPIO20, GPIO21) that offer this
feature on the 100-Pin PZ and 80-Pin PN packages.
100-Pin PZ: On this package, there are dedicated pins for B5 (pin 32) and B11 (pin 30) which respectively also
have AIO252 and AIO251 functionality. In addition, GPIO20 (pin 48) and GPIO21 (pin 49) are also available as
B5 and B11 respectively. Since B5 and B11 are dedicated pins on this package, it is recommended to use them
instead of the ones on GPIO20/21.
80-Pin PN: On this package, GPIO20 (pin 33) and GPIO21 (pin 34) are also available as B5 and B11
respectively. There are no dedicated pin for B5 and B11.
By default the AGPIOs are not connected and have to be configured. Table 5-8 truth table shows how to
configure the AGPIOs using B5 (pin 32) and GPIO20 (pin 48) on the 100-Pin PZ as an example.
Table 5-8. AGPIO Configuration
B5 CONNECTED TO
GPIO20 CONNECTED TO
AGPIOCTRLA.bit.GPIO20
GPAAMSEL.bit.GPIO20
GPHAMSEL.bit.GPIO252
ADC
Yes
Yes
Yes
-
GPIO20
AIO252
ADC
GPIO20
AIO252
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
Yes
-
-
-
-
-
-
-
-
-
-
Yes
-
-
-
-
Yes
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
-
Yes
-
-
-
Yes
-
Yes
Note
If digital signals with sharp edges (high dv/dt) are connected to the AGPIOs, cross-talk can occur with
adjacent analog signals. The user should therefore limit the edge rate of signals connected to AGPIOs
if adjacent channels are being used for analog functions.
5.4.4 GPIO Input X-BAR
The Input X-BAR is used to route signals from a GPIO to many different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts (see Figure 5-6). Table 5-9 lists the input X-BAR destinations.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
GPIO0
Asynchronous
Synchronous
Sync. + Qual.
Input X-BAR
Other Sources
INPUT[16:1]
127:16
15:0
GPIOx
eCAP
Modules
DCCx Clock Source-1
DCCx Clock Source-0
TZ1,TRIP1
TZ2,TRIP2
TZ3,TRIP3
TRIP6
XINT1
TRIP4
TRIP5
XINT2
XINT3
XINT4
XINT5
ePWM
Modules
CPU PIE
CLA
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
ePWM
X-BAR
Other
Sources
ADCEXTSOC
ADC
EXTSYNCIN1
ePWM and eCAP
Sync Scheme
EXTSYNCIN2
Other Sources
INPUT[1:16]
ERAD
EPG
Output X-BAR
INPUT[13:16]
Figure 5-6. Input X-BAR
Table 5-9. Input X-BAR Destinations
INPUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ECAP / HRCAP
EPWM X-BAR
CLB X-BAR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
OUTPUT X-BAR
CPU XINT
Yes
XINT1 XINT2
XINT3
XINT4 XINT5
TZ1, TZ2, TZ3,
TRIP1 TRIP2 TRIP3
EPWM TRIP
TRIP6
ADC START OF
CONVERSION
ADCEX
TSOC
EPWM / ECAP
SYNC
EXTSY EXTSY
NCIN1
NCIN2
CLK CLK
DCCx
CLK1 CLK0
EPG1 EPG1 EPG1 EPG1
0
0
EPG
IN1
IN2
IN3
IN4
ERAD
Yes
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes Yes Yes Yes
Yes
Yes
Yes
Yes
Copyright © 2021 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.4.5 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
The Output X-BAR has eight outputs that can be selected on the GPIO mux as OUTPUTXBARx. The CLB
X-BAR has eight outputs that are connected to the CLB global mux as AUXSIGx. The CLB Output X-BAR has
eight outputs that can be selected on the GPIO mux as CLB_OUTPUTXBARx. The ePWM X-BAR has eight
outputs that are connected to the TRIPx inputs of the ePWM. The sources for the Output X-BAR, CLB X-BAR,
CLB Output X-BAR, and ePWM X-BAR are shown in Figure 5-7.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
CTRIPOUTH
CTRIPOUTL
(Output X-BAR only)
(ePWM X-BAR only)
CMPSSx
CTRIPH
CTRIPL
ePWM and eCAP
EXTSYNCOUT
Sync Chain
AUXSIG1
AUXSIG2
AUXSIG3
AUXSIG4
AUXSIG5
AUXSIG6
AUXSIG7
AUXSIG8
CLB
Global
Mux
ADCSOCA0
ADCSOCA0
Select Circuit
CLB
X-BAR
ADCSOCB0
ADCSOCB0
Select Circuit
TRIP4
TRIP5
eCAPx
ADCx
ECAPxOUT
EVT1
EVT2
EVT3
EVT4
All
ePWM
Modules
TRIP7
TRIP8
TRIP9
TRIP10
TRIP11
TRIP12
EPWM
X-BAR
INPUT1-6
INPUT7-14
(ePWM X-BAR only)
Input X-BAR
CLAHALT
eQEPx
CLAHALT
OUTPUTXBAR1
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
FLT1.COMPH
FLT1.COMPL
Output
X-BAR
SDFMx
FLT4.COMPH
FLT4.COMPL
GPIO
Mux
X-BAR Flags
(shared)
CLB_OUTPUTXBAR1
CLB_OUTPUTXBAR2
CLB_OUTPUTXBAR3
CLB_OUTPUTXBAR4
CLB_OUTPUTXBAR5
CLB_OUTPUTXBAR6
CLB_OUTPUTXBAR7
CLB_OUTPUTXBAR8
CLB
Output
X-BAR
CLB Input X-BAR
CLB TILEx
Figure 5-7. Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources
Copyright © 2021 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
5.5 Pins With Internal Pullup and Pulldown
Some pins on the device have internal pullups or pulldowns. Table 5-10 lists the pull direction and when it is
active. The pullups on GPIO pins are disabled by default and can be enabled through software. To avoid any
floating unbonded inputs, the Boot ROM will enable internal pullups on GPIO pins that are not bonded out in
a particular package. Other pins noted in Table 5-10 with pullups and pulldowns are always on and cannot be
disabled.
Table 5-10. Pins With Internal Pullup and Pulldown
RESET
(XRSn = 0)
PIN
DEVICE BOOT
APPLICATION
GPIOx
Pullup disabled
Pullup disabled(1)
Application defined
Application defined
Application defined
Application defined
GPIO35/TDI
GPIO37/TDO
AGPIOx
TCK
Pullup disabled
Pullup disabled
Pullup disabled
Pullup disabled
Pullup active
Pullup active
Pullup active
TMS
XRSn
Other pins (including AIOs)
No pullup or pulldown present
(1) Pins not bonded out in a given package will have the internal pullups enabled by the Boot ROM.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
5.6 Connections for Unused Pins
For applications that do not need to use all functions of the device, Table 5-11 lists acceptable conditioning for
any unused pins. When multiple options are listed in Table 5-11, any option is acceptable. Pins not listed in Table
5-11 must be connected according to Section 5.
Table 5-11. Connections for Unused Pins
SIGNAL NAME
ACCEPTABLE PRACTICE
ANALOG
VREFHI
VREFLO
Tie to VDDA (applies only if ADC is not used in the application)
Tie to VSSA
•
•
No Connect
Analog input pins with
DACx_OUT
Tie to VSSA through 4.7-kΩ or larger resistor
•
•
•
No Connect
Analog input pins (except
DACx_OUT)
Tie to VSSA
Tie to VSSA through resistor
•
•
•
No connection (digital input mode with internal pullup enabled)
Analog input pins (shared with
GPIOs)(1)
No connection (digital output mode with internal pullup disabled)
Pullup or pulldown resistor (any value resistor, digital input mode, and with internal pullup disabled)
DIGITAL
•
•
•
No connection (input mode with internal pullup enabled)
No connection (output mode with internal pullup disabled)
GPIOx
Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled)
When TDI mux option is selected (default), the GPIO is in Input mode.
•
•
Internal pullup enabled
External pullup resistor
GPIO35/TDI
When TDO mux option is selected (default), the GPIO is in Output mode only during JTAG activity;
otherwise, it is in a tri-state condition. The pin must be biased to avoid extra current on the input buffer.
GPIO37/TDO
•
•
Internal pullup enabled
External pullup resistor
•
•
No Connect
TCK
TMS
Pullup resistor
Pullup resistor
Turn XTAL off and:
•
•
•
Input mode with internal pullup enabled
GPIO19/X1
GPIO18/X2
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
Turn XTAL off and:
•
•
•
Input mode with internal pullup enabled
Input mode with external pullup or pulldown resistor
Output mode with internal pullup disabled
POWER AND GROUND
VDD
All VDD pins must be connected per Section 5.3. Pins should not be used to bias any external circuits.
If a dedicated analog supply is not used, tie to VDDIO.
VDDA
VDDIO
VSS
All VDDIO pins must be connected per Section 5.3.
All VSS pins must be connected to board ground.
Copyright © 2021 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 5-11. Connections for Unused Pins (continued)
SIGNAL NAME
ACCEPTABLE PRACTICE
VSSA
If an analog ground is not used, tie to VSS.
(1) AGPIO pins share analog and digital functionality. The actions here only apply if these pins are also not being used for analog
functions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6 Specifications
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device beyond the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect
device reliability. All voltage values are with respect to VSS, unless otherwise noted.
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
4.6
4.6
1.5
4.6
4.6
UNIT
VDDIO with respect to VSS
VDDA with respect to VSSA
VDD with respect to VSS
VIN (3.3 V)
Supply voltage
V
Input voltage
V
V
Output voltage
VO
Digital/analog input (per pin), IIK (VIN < VSS/VSSA or VIN > VDDIO/
VDDA)(2)
–20
–20
20
20
Input clamp current
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA)
Output current
Digital output (per pin), IOUT
–20
–40
–40
–65
20
125
150
150
mA
°C
°C
°C
Free-Air temperature
Operating junction temperature
Storage temperature(1)
TA
TJ
Tstg
(1) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
(2) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
6.2 ESD Ratings – Commercial
VALUE
UNIT
F280039C, F280039, F280037C, F280037, F280034, F280033 in 100-pin PZ package
Human-body model (HBM), per ANSI/ESDA/JEDEC
±2000
±500
JS-001(1)
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
F280039C, F280039, F280037C, F280037, F280034, F280033 in 80-pin PN package
Human-body model (HBM), per ANSI/ESDA/JEDEC
±2000
±500
JS-001(1)
V(ESD)
Electrostatic discharge (ESD)
V
V
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
F280039C, F280039, F280037C, F280037, F280034, F280033 in 64-pin PM package
Human-body model (HBM), per ANSI/ESDA/JEDEC
±2000
±500
JS-001(1)
V(ESD)
Electrostatic discharge (ESD)
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
F280037C, F280037, F280034, F280033 in 48-pin PT package
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
Charged-device model (CDM), per ANSI/ESDA/JEDEC
JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2021 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.3 ESD Ratings – Automotive
VALUE
UNIT
F280039C-Q1, F280039-Q1, F280037C-Q1, F280037-Q1 in 100-pin PZ package
Human body model (HBM), per
AEC Q100-002(1)
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
All pins
±500
±750
V
Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100
F280038C-Q1, F280038-Q1, F280036C-Q1, F280036-Q1 in 64-pin PM package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
V
Corner pins on 64-pin PM:
1, 16, 17, 32, 33, 48, 49, 64
F280037C-Q1, F280037-Q1, F280034-Q1 in 48-pin PT package
Human body model (HBM), per
All pins
All pins
±2000
AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
Corner pins on 48-pin PT:
1, 12, 13, 24, 25, 36, 37, 48
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions
MIN
NOM
MAX
3.63
3.63
UNIT
VBOR-VDDIO(MAX) + VBOR-VDDIO-GB
Internal BOR enabled(3)
Internal BOR disabled
3.3
(2)
Device supply voltage, VDDIO and VDDA
V
2.8
3.3
0
Device ground, VSS
Analog ground, VSSA
SRSUPPLY
V
V
0
Supply ramp rate(4)
Digital input voltage
Analog input voltage
VSS – 0.3
VSSA – 0.3
–40
VDDIO + 0.3
VDDA + 0.3
150
V
V
VIN
(1)
Junction temperature, TJ
°C
°C
Free-Air temperature, TA
–40
125
(1) Operation above TJ = 105°C for extended duration will reduce the lifetime of the device. See Calculating Useful Lifetimes of Embedded
Processors for more information.
(2) See the Power Management Module (PMM) section.
(3) Internal BOR is enabled by default.
(4) See the Power Management Module Operating Conditions table.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.5 Power Consumption Summary
Current values listed in this section are representative for the test conditions given and not the absolute
maximum possible. The actual device currents in an application will vary with application code and pin
configurations. Section 6.5.1 lists the system current consumption values. Section 6.5.2 lists the system current
consumption with VREG disabled.
6.5.1 System Current Consumption
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDDIO current consumption during
operational usage
This is an estimation of current
for a typical heavily loaded
application. Actual currents will
vary depending on system
activity, I/O electrical loading
and switching frequency. This
includes Core supply current with
Internal Vreg Enabled.
IDDIO
78.5
106
mA
- CPU is running from RAM
- Flash is powered up
- X1/X2 crystal is powered up
- PLL is enabled, SYSCLK=Max
Device frequency
VDDA current consumption during
operational usage
IDDA
3
6.5
mA
- Analog modules are powered up
- Outputs are static without DC
Load
- Inputs are static high or low
IDLE MODE
VDDIO current consumption while
device is in Idle mode
- CPU is in IDLE mode
- Flash is powered down
- PLL is Enabled, SYSCLK=Max
Device Frequency, CPUCLK is
gated
- X1/X2 crystal is powered up
- Analog Modules are powered
down
IDDIO
28.2
0.01
47.4
0.1
mA
mA
VDDA current consumption while
device is in Idle mode
IDDA
- Outputs are static without DC
Load
- Inputs are static high or low
STANDBY MODE
VDDIO current consumption while
device is in Standby mode
- CPU is in STANDBY mode
- Flash is powered down
- PLL is Enabled, SYSCLK &
CPUCLK are gated
- X1/X2 crystal is powered down
- Analog Modules are powered
down
IDDIO
13.9
0.01
31.3
0.1
mA
mA
VDDA current consumption while
device is in Standby mode
IDDA
- Outputs are static without DC
Load
- Inputs are static high or low
Copyright © 2021 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.5.1 System Current Consumption (continued)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HALT MODE
VDDIO current consumption while
device is in Halt mode
- CPU is in HALT mode
- Flash is powered down
- PLL is Disabled, SYSCLK &
CPUCLK are gated
IDDIO
9.8
27.5
mA
- X1/X2 crystal is powered down
- Analog Modules are powered
down
- Outputs are static without DC
Load
VDDA current consumption while
device is in Halt mode
IDDA
0.01
0.1
mA
mA
- Inputs are static high or low
FLASH ERASE/PROGRAM
VDDIO current consumption during
- CPU is running from RAM
- Flash going through continuous
Program/Erase operation
- PLL is enabled, SYSCLK at 120
MHz.
IDDIO
72
106
Erase/Program cycle(1)
- Peripheral clocks are turned
OFF.
- X1/X2 crystal is powered up
- Analog is powered down
- Outputs are static without DC
Load
VDDA current consumption during
Erase/Program cycle
IDDA
0.1
2.5
mA
- Inputs are static high or low
RESET MODE
VDDIO current consumption while
reset is active(2)
IDDIO
5.8
0.1
mA
mA
VDDA current consumption while reset
is active(2)
IDDA
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, that is XRSn is low.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.5.2 System Current Consumption (VREG Disable - External Supply)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING MODE
VDD current consumption during
operational usage
This is an estimation of current
for a typical heavily loaded
application. Actual currents will
vary depending on system
activity, I/O electrical loading and
switching frequency.
IDD
68
7
90
15
mA
mA
VDDIO current consumption during
operational usage
IDDIO
- CPU is running from RAM
- Flash is powered up
- X1/X2 crystal is powered up
- PLL is enabled, SYSCLK=Max
Device frequency
- Analog modules are powered up
- Outputs are static without DC
Load
VDDA current consumption during
operational usage
IDDA
3
6.5
mA
- Inputs are static high or low
IDLE MODE
VDD current consumption while device - CPU is in IDLE mode
IDD
25
43
mA
mA
is in Idle mode
- Flash is powered down
- PLL is Enabled, SYSCLK=Max
Device Frequency, CPUCLK is
gated
VDDIO current consumption while
device is in Idle mode
IDDIO
1.7
2.2
- X1/X2 crystal is powered up
- Analog Modules are powered
down
- Outputs are static without DC
Load
VDDA current consumption while
device is in Idle mode
IDDA
0.01
0.1
mA
- Inputs are static high or low
STANDBY MODE
VDD current consumption while device - CPU is in STANDBY mode
IDD
11.6
1.7
27.6
2.3
mA
mA
is in Standby mode
- Flash is powered down
- PLL is Enabled, SYSCLK &
CPUCLK are gated
- X1/X2 crystal is powered down
- Analog Modules are powered
down
VDDIO current consumption while
device is in Standby mode
IDDIO
VDDA current consumption while
device is in Standby mode
IDDA
0.01
0.1
mA
- Outputs are static without DC
Load
- Inputs are static high or low
HALT MODE
VDD current consumption while device - CPU is in HALT mode
IDD
8.5
0.8
25
mA
mA
is in Halt mode
- Flash is powered down
- PLL is Disabled, SYSCLK &
CPUCLK are gated
- X1/X2 crystal is powered down
- Analog Modules are powered
down
VDDIO current consumption while
device is in Halt mode
IDDIO
1.2
VDDA current consumption while
device is in Halt mode
IDDA
0.01
0.1
mA
- Outputs are static without DC
Load
- Inputs are static high or low
Copyright © 2021 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.5.2 System Current Consumption (VREG Disable - External Supply) (continued)
over operating free-air temperature range (unless otherwise noted).
TYP : Vnom, 30℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FLASH ERASE/PROGRAM
VDD Current consumption during
Erase/Program cycle(1)
- CPU is running from RAM
- Flash going through continuous
Program/Erase operation
- PLL is enabled, SYSCLK at 120
MHz.
IDD
41
31
60.5
45.5
mA
mA
VDDIO Current consumption during
Erase/Program cycle(1)
IDDIO
- Peripheral clocks are turned
OFF.
- X1/X2 crystal is powered up
- Analog is powered down
- Outputs are static without DC
Load
VDDA Current consumption during
Erase/Program cycle
IDDA
0.1
2.5
mA
- Inputs are static high or low
RESET MODE
VDD current consumption while reset
is active(2)
IDD
3.3
2.2
0.1
mA
mA
mA
VDDIO current consumption while
reset is active(2)
IDDIO
IDDA
VDDA current consumption while reset
is active(2)
(1) Brownout events during flash programming can corrupt flash data and permanently lock the device. Programming environments using
alternate power sources (such as a USB programmer) must be capable of supplying the rated current for the device and other system
components with sufficient margin to avoid supply brownout conditions.
(2) This is the current consumption while reset is active, that is XRSn is low.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.5.3 Operating Mode Test Description
Section 6.5.1 and Section 6.5.4.1 list the current consumption values for the operational mode of the device. The
operational mode provides an estimation of what an application might encounter. The test condition for these
measurements has the following properties:
•
•
•
•
•
•
Code is executing from RAM.
FLASH is read and kept in active state.
No external components are driven by I/O pins.
All peripherals have clocks enabled.
The CPU is actively executing code.
All analog peripherals are powered up. ADCs and DACs are periodically converting.
Copyright © 2021 Texas Instruments Incorporated
78
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.5.4 Reducing Current Consumption
The F28003x devices provide some methods to reduce the device current consumption:
•
One of the two low-power modes—IDLE or STANDBY—could be entered during idle periods in the
application.
•
•
•
The flash module may be powered down if the code is run from RAM.
Disable the pullups on pins that assume an output function.
Each peripheral has an individual clock-enable bit (PCLKCRx). Reduced current consumption may be
achieved by turning off the clock to any peripheral that is not used in a given application. Section 6.5.4.1
lists the typical current reduction that may be achieved by disabling the clocks using the PCLKCRx register.
To realize the lowest VDDA current consumption in an LPM, see the Analog-to-Digital Converter (ADC)
chapter of the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual to ensure each
module is powered down as well.
•
6.5.4.1 Typical Current Reduction per Disabled Peripheral
PERIPHERAL
IDD CURRENT REDUCTION (mA)
ADC(1)
0.73
0.56
0.42
1.41
0.33
0.25
0.04
0.12
1.28
0.12
0.57
0.08
0.29
0.95
0.78
1.56
0.1
CLA
CLA BGCRC
CLB
CMPSS(1)
CPU BGCRC
CPU TIMER
GPDAC
DCAN
DCC
DMA
eCAP1 and eCAP2
eCAP3(2)
ePWM1 to ePWM4(3)
ePWM5 to ePWM8
ERAD
eQEP
FSI RX
0.34
0.27
0.17
0.26
0.35
1.01
0.28
0.16
1.83
0.08
FSI TX
HIC
I2C
LIN
MCAN (CAN FD)
PMBUS
SCI
SDFM
SPI
(1) This current represents the current drawn by the digital portion of the each module.
(2) eCAP3 can also be configured as HRCAP.
(3) ePWM1 to ePWM4 can also be configured as HRPWM.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
Digital and Analog IO
VOH High-level output voltage
IOH = IOH MIN
IOH = –100 μA
IOL = IOL MAX
IOL = 100 µA
VDDIO * 0.8
VDDIO – 0.2
V
0.4
V
VOL
Low-level output voltage
0.2
IOH
High-level output source current for all output pins
Low-level output sink current for all output pins
High-level output impedance for all output pins
Low-level output impedance for all output pins
High-level input voltage
–4
mA
IOL
4
mA
Ω
ROH
70
70
ROL
Ω
VIH
2.0
V
VIL
Low-level input voltage
0.8
V
VHYSTERESIS
Input hysteresis
125
mV
VDDIO = 3.3 V
VIN = VDDIO
IPULLDOWN
IPULLUP
Input current
Input current
Pins with pulldown
120
160
µA
µA
Digital inputs with pullup VDDIO = 3.3 V
enabled(1)
VIN = 0 V
Pullups and outputs
disabled
Digital inputs
0.1
0 V ≤ VIN ≤ VDDIO
ILEAK
Pin leakage
µA
pF
Analog pins (except
ADCINB3/VDAC)
Analog drivers
disabled
0 V ≤ VIN ≤ VDDA
0.1
11
ADCINB3/VDAC
Digital inputs
2
2
CI
Input capacitance
Analog pins(2)
VREG, POR and BOR
VREG, POR,
BOR(3)
(1) See Pins With Internal Pullup and Pulldown table for a list of pins with a pullup or pulldown.
(2) The analog pins are specified separately; see the Per-Channel Parasitic Capacitance tables that are in the ADC Input Model section.
(3) See the Power Management Module (PMM) section.
Copyright © 2021 Texas Instruments Incorporated
80
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.7 Thermal Resistance Characteristics for PZ Package
°C/W(1)
7.6
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
N/A
N/A
0
RΘJB
24.2
46.1
37.3
34.8
32.6
0.2
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.4
150
250
500
0
PsiJT
Junction-to-package top
0.4
0.6
23.8
22.8
22.4
21.9
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.8 Thermal Resistance Characteristics for PN Package
°C/W(1)
14.2
21.9
49.9
38.3
36.7
34.4
0.8
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
N/A
N/A
0
150
250
500
0
RΘJA (High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
1.18
1.34
1.62
21.6
20.7
20.5
20.1
150
250
500
0
PsiJT
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
Copyright © 2021 Texas Instruments Incorporated
82
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.9 Thermal Resistance Characteristics for PM Package
°C/W(1)
12.4
25.6
51.8
42.2
39.4
36.5
0.5
AIR FLOW (lfm)(2)
RΘJC
Junction-to-case thermal resistance
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
N/A
N/A
0
RΘJB
RΘJA (High k PCB)
150
250
500
0
RΘJMA
Junction-to-moving air thermal resistance
0.9
150
250
500
0
PsiJT
Junction-to-package top
1.1
1.4
25.1
23.8
23.4
22.7
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.10 Thermal Resistance Characteristics for PT Package
°C/W(1)
13.6
30.6
64
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
N/A
N/A
0
50.4
48.2
45
150
250
500
0
RΘJA (High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
0.56
0.94
1.1
150
250
500
0
PsiJT
1.38
30.1
28.7
28.4
28
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
6.11 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems
that exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
Copyright © 2021 Texas Instruments Incorporated
84
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12 System
6.12.1 Power Management Module (PMM)
6.12.1.1 Introduction
The Power Management Module (PMM) handles all the power management functions required for device
operation.
6.12.1.2 Overview
The block diagram of the PMM is shown in Figure 6-1. As can be seen, the PMM comprises of various
sub-components which will be described in the subsequent sections.
MCU
To Rest of Chip
PMM
CPU Reset
Release
I/O
POR
RISE
DELAY
(45us)
RISE
DELAY
(80us)
I/O
BOR
Internal
Power
Good
RISE
DELAY
(40us)
Signal
EN
VMONCTL.bit.BORLVMONDIS
VDD
POR
EN
1.2v LDO
VREG
Internal
External
Internal
External
CVDDIO
CVDD
Figure 6-1. PMM Block Diagram
6.12.1.2.1 Power Rail Monitors
The PMM has voltage monitors on the supply rails that release the XRSn signal high once the voltages cross the
set threshold during power up. They also function to trip the XRSn signal low if any of the voltages drop below
the programmed levels. The various voltage monitors are described in the subsequent sections.
Note
Not all the voltage monitors are supported for device operation in an application. In the case where a
voltage monitor is not supported, an external supervisor is recommended if the device needs supply
voltage monitoring.
The three voltage monitors (I/O POR, I/O BOR, VDD POR) all have to release their respective outputs before the
device begins operation (i.e XRSn goes high). However, if any of the voltage monitors trips, XRSn is driven low.
The I/Os are held in high impedance when any of the voltage monitors trip.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
The I/O POR monitor supervises the VDDIO rail. During power-up, this is the first monitor to release (i.e first to
untrip) on VDDIO.
6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
The I/O BOR monitor also supervises the VDDIO rail. During power-up, this is the second monitor to release (i.e
second to untrip) on VDDIO. This monitor has a tighter tolerance compared to the I/O POR.
Any drop in voltage below the recommended operating voltages will trip the I/O BOR and reset the device but
this can be disabled by setting VMONCTL.bit.BORLVMONDIS to 1. The I/O BOR can only be disabled after the
device has fully booted up. If the I/O BOR is disabled, the I/O POR will reset the device for voltage drops.
Note
The level that the I/O POR trips at is well below the minimum recommended voltage for VDDIO and
hence should not be used for device supervision.
Figure 6-2 shows the operating region of the I/O BOR.
3.63 V
+10%
Recommended
System Voltage
Regulator Range
3.3 V
0%
VDDIO
Operating
Range
3.1 V
3.0 V
–6.1%
–9.1%
VBOR-GB
BOR Guard Band
VBOR-VDDIO
Internal BOR Threshold
–14.8%
–15.1%
2.81 V
2.80 V
Figure 6-2. I/O BOR Operating Region
6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
The VDD POR monitor supervises the VDD rail. During power-up, this monitor releases i.e untrips once the
voltage crosses the programmed trip level on VDD.
Note
VDD POR is programmed at a level below the minimum recommended voltage for VDD and hence it
should not be relied upon for VDD supervision if that is required in the application.
6.12.1.2.2 External Supervisor Usage
VDDIO Monitoring: The I/O BOR is supported for application use so an external supervisor is not required to
monitor the I/O rail.
VDD Monitoring: The VDD POR is not supported for application use. If VDD monitoring is required by the
application, an external supervisor should be used to monitor the VDD rail.
Copyright © 2021 Texas Instruments Incorporated
86
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Note
Using an external supervisor with the internal VREG is not supported. If VDD monitoring is required
by the application, it is a requirement to use a package with VREGENZ pin in order to power VDD
externally.
6.12.1.2.3 Delay Blocks
The delay blocks in the path of the voltage monitors work together to delay the release time between the voltage
monitors and XRSn. This is to ensure that the voltages are stable when XRSn releases in external VREG mode.
They are only active during power-up i.e when VDDIO and VDD are ramping up.
They contribute to the minimum slew rates specified in Power Management Module Electrical Data and Timing
for the power rails.
Note
The delay numbers specified in the block diagram are typical numbers.
6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
The internal VREG is supplied by the VDDIO rail and can generate the 1.2V required to power the VDD pins. It
is enabled by tying the VREGENZ pin low. Although it eliminates the need to use an external supply for VDD,
decoupling capacitors are still required on the VDD pins for VREG stability and transients. See VDD Decoupling
for details.
6.12.1.2.5 VREGENZ
The VREGENZ (VREG disable) pin controls the state of the internal VREG. To enable the internal VREG,
VREGENZ pin should be tied low. For applications supplying VDD externally (external VREG), the internal
VREG should be disabled by tying the VREGENZ pin high.
Note
Not all device packages have VREGENZ pinned out. For packages without VREGENZ, external
VREG mode is not supported.
6.12.1.3 External Components
6.12.1.3.1 Decoupling Capacitors
VDDIO and VDD require decoupling capacitors for correct operation. The requirements are outlined in the
subsequent sections.
6.12.1.3.1.1 VDDIO Decoupling
It is recommended to place a minimum amount of decoupling capacitance on VDDIO. See the CVDDIO parameter
in Power Management Module Electrical Data and Timing. The actual amount of decoupling capacitance to use
is a requirement of the power supply driving VDDIO. Either of the configurations outlined below is acceptable:
•
•
Configuration 1: Place a decoupling capacitor on each VDDIO pin per the CVDDIO parameter.
Configuration 2: Install a single decoupling capacitor which is the equivalent of CVDDIO * VDDIO pins.
Note
It is critical to have the decoupling capacitor/s close to the device pins.
6.12.1.3.1.2 VDD Decoupling
It is recommended to place a minimum amount of decoupling capacitance on VDD. See the CVDD TOTAL
parameter in Power Management Module Electrical Data and Timing.
In external VREG mode, the actual amount of decoupling capacitance to use is a requirement of the power
supply driving VDD.
Either of the configurations outlined below is acceptable:
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
•
•
Configuration 1: Divide CVDD TOTAL across the VDD pins.
Configuration 2: Install a single decoupling capacitor with value of CVDD TOTAL.
Note
It is critical to have the decoupling capacitor/s close to the device pins.
6.12.1.4 Power Sequencing
6.12.1.4.1 Supply Pins Ganging
It is strongly recommended that all 3.3v rails be tied together and supplied from a single source. This list
includes:
•
•
VDDIO
VDDA
In addition, no power pin should be left unconnected.
In external VREG mode, the VDD pins should be tied together and supplied from a single source.
In internal VREG mode, tying the VDD pins together is optional as long as each VDD pin has a capacitor on it.
See VDD Decoupling for VDD decoupling configurations.
The analog modules on the device have fairly high PSRR and hence in most cases, noise on VDDA will have to
exceed the recommended operating conditions of the supply rails before the analog modules see performance
degradation. Due to this, supplying VDDA separately typically offers minimal benefits. Nevertheless, for the
purposes of noise improvement, placing a pi filter between VDDIO and VDDA is acceptable.
Note
All the supply pins per rail are tied together internally. For instance, all VDDIO pins are tied together
internally, all VDD pins are tied together internally etc.
6.12.1.4.2 Signal Pins Power Sequence
Before powering the device, no voltage larger than 0.3 V above VDDIO or 0.3 V below VSS should be applied
to any digital pin and no voltage larger than 0.3 V above VDDA or 0.3 V below VSSA should be applied to any
analog pin (including VREFHI and VDAC). Simply, the signal pins should only be driven after XRSn goes high
provided all the 3.3v rails are tied together. This sequencing is still required even if VDDIO and VDDA are not
tied together.
If the above sequence is violated, device malfunction and possibly damage can occur as current will flow through
unintended parasitic paths in the device.
6.12.1.4.3 Supply Pins Power Sequence
6.12.1.4.3.1 External VREG/VDD Mode Sequence
Figure 6-3 depicts the power sequencing requirements for external VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.
Copyright © 2021 Texas Instruments Incorporated
88
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
VDDIO
VDDIO
VDD
(i)
(ii)
VBOR-VDDIO-UP
VBOR-VDDIO-DOWN
VDD
Internal
Internal
Power Good
Signal(iv)
Power Good
Signal(iii)
XRSn
XRSn
SRVDDIO
SRVDD
SRVDDIO
SRVDD
(ii)
(i)
VPOR-VDDIO
VPOR-VDD-DOWN
VPOR-VDD-UP
VPOR-VDDIO
V
DDIO - VDD
Delay
VDDIO-MON-TOT-DELAY
VXRSn-PU-DELAY
VXRSn-PD-DELAY
(i) This trip point is the trip point before XRSn releases. See the PMM Characteris cs table.
(ii) This trip point is the trip point a er XRSn releases. See the PMM Characteris cs table.
(iii) During power up, the Power Good Signal goes high a er all POR and BOR monitors are released. See the PMM Block Diagram.
(iv) During power down, the Power Good Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block Diagram.
Figure 6-3. External VREG Power Up Sequence
•
For Power Up:
1. VDDIO i.e the 3.3 V rail should come up first with the minimum slew rate specified.
2. VDD i.e the 1.2 V rail should come up next with the minimum slew rate specified.
3. The time delta between the VDDIO rail coming up and when the VDD rail can come up is also specified.
4. After the times specified by vddio-mon-tot-delay and vxrsn-pu-delay, XRSn will be released and the
device starts the boot-up sequence.
There is an additional delay between XRSn releasing (i.e going high) and the boot-up sequence starting.
See Figure 6-1.
5. The VDD POR and I/O BOR monitors have different release point during power up.
6. During power up, both VDDIO and VDD rails have to be up before XRSn releases.
For Power-Down:
•
1. There is no requirement between VDDIO and VDD on which should power down first, however, there is a
minimum slew rate spec.
2. The VDD POR and I/O BOR monitors have different trip points during power down.
3. Any of the POR or BOR monitors that trips during power down will cause XRSn to go low after
VXRSN-PD-DELAY
.
Note
The Power Good Signal is an internal signal.
Note
If there is an external circuit driving XRSn e.g a supervisor, the boot-up sequence does not start until
the XRSn pin is released by all internal and external sources.
6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
Figure 6-4 depicts the power sequencing requirements for internal VREG mode. The values for all the
parameters indicated can be found in Power Management Module Electrical Data and Timing.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
89
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
VDDIO
VDDIO
(i)
(ii)
VBOR-VDDIO-UP
VBOR-VDDIO-DOWN
Internal
Power Good
Signal(iii)
Internal
Power Good
Signal(iv)
XRSn
XRSn
SRVDDIO
SRVDDIO
VPOR-VDDIO
VPOR-VDDIO
VDDIO-MON-TOT-DELAY
VXRSn-PU-DELAY
VXRSn-PD-DELAY
(i) This trip point is the trip point before XRSn releases. See the PMM Characteris cs table.
(ii) This trip point is the trip point a er XRSn releases. See the PMM Characteris cs table.
(iii) During power up, the Power Good Signal goes high a er all POR and BOR monitors are released. See the PMM Block Diagram.
(iv) During power down, the Power Good Signal goes low if any of the POR or BOR monitors are tripped. See the PMM Block Diagram.
Figure 6-4. Internal VREG Power Up Sequence
For Power-Up:
•
1. VDDIO i.e the 3.3 V rail should come up with the minimum slew rate specified.
2. The Internal VREG powers up after the I/O monitors (I/O POR and I/O BOR) are released.
3. After the times specified by VDDIO-MON-TOT-DELAY and VXRSN-PU-DELAY, XRSn will be released and the
device starts the boot-up sequence.
There is an additional delay between XRSn releasing (i.e going high) and the boot-up sequence starting.
See Figure 6-1.
4. The I/O BOR monitor has a different release point during power up.
For Power-Down:
•
1. The only requirement on VDDIO during power down is the slew rate.
2. The I/O BOR monitor has a different release point during power down.
3. The I/O BOR tripping will cause XRSn to go low after VXRSN-PD-DELAY and also power down the Internal
VREG.
Note
The Power Good Signal is an internal signal.
Note
If there is an external circuit driving XRSn e.g a supervisor, the boot-up sequence does not start until
the XRSn pin is released by all internal and external sources.
6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
The acceptable power up sequence for the rails is summarized below. Power-up here means the rail in question
has reached the minimum recommended operating voltage. Non-acceptable sequences will lead to reliability
concerns and possibly damage. For simplicity, it is recommended to tie all the 3.3-V rails together and follow the
descriptions in Supply Pins Power Sequence.
Table 6-1. External VREG Sequence Summary
RAILS POWER-UP ORDER
CASE
ACCEPTABLE
VDDIO
VDDA
VDD
A
B
C
D
1
1
2
2
2
3
1
3
3
2
3
1
Yes
Yes
-
-
Copyright © 2021 Texas Instruments Incorporated
90
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 6-1. External VREG Sequence Summary (continued)
RAILS POWER-UP ORDER
CASE
ACCEPTABLE
VDDIO
VDDA
VDD
E
F
3
3
1
2
2
1
1
2
1
2
2
1
-
-
Yes
-
G
H
Table 6-2. Internal VREG Sequence Summary
RAILS POWER-UP ORDER
CASE
ACCEPTABLE
VDDIO
VDDA
A
B
C
1
2
1
2
1
1
Yes
-
Yes
Note
The analog modules on the device should only be powered after VDDA has reached the minimum
recommended operating voltage.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
91
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.1.5 Power Management Module Electrical Data and Timing
6.12.1.5.1 Power Management Module Operating Conditions
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
VDDIO Capacitance Per
Pin(7)
(1) (2)
CVDDIO
0.1
2.2
20
uF
uF
VDDA Capacitance Per
Pin(7)
(1) (2)
CVDDA
Supply Ramp Rate of 3.3V
Rail (VDDIO)
(3)
SRVDDIO
100
mV/us
V
VBOR-VDDIO-GB VDDIO Brown Out Reset
0.1
(5)
Voltage Guardband
External VREG
CVDD
Total VDD Capacitance(7)
10
20
0
uF
mV/us
us
TOTAL(1) (4)
Supply Ramp Rate of 1.2V
Rail (VDD)
(3)
SRVDD
100
VDDIO - VDD
Delay(6)
Ramp Delay Between VDDIO
and VDD
Internal VREG
CVDD
Total VDD Capacitance(7)
10
uF
TOTAL(4)
(1) The exact value of the decoupling capacitance depends on the system voltage regulation solution that is supplying these pins.
(2) It is recommended to tie the 3.3V rails (VDDIO, VDDA) together and supply them from a single source.
(3) Supply ramp rate faster than the max can trigger the on-chip ESD protection.
(4) See the Power Management Module (PMM) section on possible configurations for the total decoupling capacitance.
(5) TI recommends VBOR-VDDIO-GB to avoid BOR-VDDIO resets due to normal supply noise or load-transient events on the 3.3-V VDDIO
system regulator. Good system regulator design and decoupling capacitance (following the system regulator specifications) are
important to prevent activation of the BOR-VDDIO during normal device operation. The value of VBOR-VDDIO-GB is a system-level design
consideration; the voltage listed here is typical for many applications.
(6) Delay between when the 3.3v rail ramps up and when the 1.2v rail ramps up. See the supply sequencing table for the allowable supply
ramp sequences.
(7) Capacitor tolerance should be less than 10%.
6.12.1.5.2 Power Management Module Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Internal Voltage Regulator
Output
VVREG
1.152
1.2
1.248
V
VDDIO Power on Reset
Voltage
Before and After XRSn
Release
VPOR-VDDIO
2.3
2.7
V
V
V
V
V
VBOR-VDDIO-UP VDDIO Brown Out Reset
Before XRSn Release
After XRSn Release
Before XRSn Release
After XRSn Release
(1)
Voltage on Ramp Up
VBOR-VDDIO-
VDDIO Brown Out Reset
Voltage on Ramp Down
2.81
3.0
(1)
DOWN
VPOR-VDD-UP
VDD Power on Reset Voltage
on Ramp Up
0.9
1
(2)
VPOR-VDD-
VDD Power on Reset Voltage
on Ramp Down
(2)
DOWN
XRSn Release Delay after
Supplies are Ramped Up
During Power-Up
VXRSn-PU-
This is the final delay
40
50
us
ns
(3)
DELAY
XRSn Trip Delay after
Supplies are Ramped Down
During Power-Down
VXRSn-PD-
(4)
DELAY
Copyright © 2021 Texas Instruments Incorporated
92
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.1.5.2 Power Management Module Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDDIO-MON-
Total Delays in Path of
VDDIO Monitors (POR, BOR)
45
us
TOT-DELAY
XRSn Release Delay after a
VDDIO BOR/VDD POR Event
40
90
us
us
VXRSn-MON-
Supplies Within Operating
Range
RELEASE-DELAY
XRSn Release Delay after a
VDDIO POR Event
(1) See the Supply Voltages figure.
(2) VPOR-VDD is not supported and it is set to trip at a level below the recommended operating conditions. If monitoring of VDD is needed,
an external supervisor is required.
(3) Supplies are considered fully ramped up after they cross the minimum recommended operating conditions for the respective rail. All
POR and BOR monitors need to be released before this delay takes effect. RC network delay will add to this.
(4) On power down, any of the POR or BOR monitors that trips will immediately trip XRSn. This delay is the time between any of the POR,
BOR monitors tripping and XRSn going low. It is variable and depends on the ramp down rate of the supply. RC network delay will add
to this.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
93
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.2 Reset Timing
XRSn is the device reset pin. It functions as an input and open-drain output. The device has a built-in power-on
reset (POR) and brown-out reset (BOR) monitors. During power up, the monitor circuits keep the XRSn pin low.
For more details, see the Power Management Module (PMM) section. A watchdog or NMI watchdog reset will
also drive the pin low. An external open-drain circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRSn and VDDIO. A capacitor should
be placed between XRSn and VSS for noise filtering, it should be 100 nF or smaller. These values will allow
the watchdog to properly drive the XRSn pin to VOL within 512 OSCCLK cycles when the watchdog reset is
asserted. Figure 6-5 shows the recommended reset circuit.
VDDIO
2.2 kW to 10 kW
Optional open-drain
Reset source
XRSn
£100 nF
Figure 6-5. Reset Circuit
6.12.2.1 Reset Sources
The Reset Signals table summarizes the various reset signals and their effect on the device.
Table 6-3. Reset Signals
Reset Source
CPU Core Reset
(C28x, FPU, TMU)
Peripherals
Reset
JTAG / Debug
Logic Reset
IOs
XRS Output
POR
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
No
No
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
No
Yes
Yes
-
BOR
XRS Pin
WDRS
NMIWDRS
Yes
Yes
No
No
Yes
No
No
SYSRS (Debugger Reset)
SCCRESET
SIMRESET. XRS
SIMRESET. CPU1RS
HWBISTRS
The parameter th(boot-mode) must account for a reset initiated from any of these sources.
See the Resets section of the System Control chapter in the TMS320F28003x Real-Time Microcontrollers
Technical Reference Manual.
CAUTION
Some reset sources are internally driven by the device. Some of these sources will drive XRSn low,
use this to disable any other devices driving the boot pins. The SCCRESET and debugger reset
sources do not drive XRSn; therefore, the pins used for boot mode should not be actively driven by
other devices in the system. The boot configuration has a provision for changing the boot pins in
OTP.
Copyright © 2021 Texas Instruments Incorporated
94
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.2.2 Reset Electrical Data and Timing
6.12.2.2.1 Reset (XRSn) Timing Requirements
MIN
1.5
MAX
UNIT
ms
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRSn low on warm reset
3.2
µs
6.12.2.2.2 Reset (XRSn) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
100
MAX
UNIT
tw(RSL1)
tw(WDRS)
tboot-flash
Pulse duration, XRSn driven low by device after supplies are stable
Pulse duration, reset pulse generated by watchdog
µs
cycles
ms
512tc(OSCCLK)
Boot-ROM execution time to first instruction fetch in flash
1.2
6.12.2.2.3 Reset Timing Diagrams
VDDIO VDDA
(3.3V)
VDD (1.2V)
tw(RSL1)
XRSn(A)
tboot-flash
Boot ROM
CPU
Execution
Phase
User code
User code dependent
(B)
th(boot-mode)
GPIO pins as input
Boot-ROM execution starts
Boot-Mode
Pins
Peripheral/GPIO function
Based on boot code
GPIO pins as input (pullups are disabled)
User code dependent
I/O Pins
A. The XRSn pin can be driven externally by a supervisor or an external pullup resistor, see the Pin Attributes table. On-chip monitors will
hold this pin low until the supplies are in a valid range.
B. After reset from any source (see the Reset Sources section), the boot ROM code samples Boot Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on
conditions (in debugger environment), the boot code execution time is based on the current SYSCLK speed. The SYSCLK will be based
on user environment and could be with or without PLL enabled.
Figure 6-6. Power-on Reset
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
95
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
tw(RSL2)
XRSn
CPU
Execution
Phase
User code
Boot ROM
User code
Boot ROM execution starts
(initiated by any reset source)
(A)
th(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO function
GPIO Pins as Input
Peripheral/GPIO function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (Pullups are Disabled)
User-Code Dependent
User-Code Dependent
A. After reset from any source (see the Reset Sources section), the Boot ROM code samples BOOT Mode pins. Based on the status of
the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on
conditions (in debugger environment), the Boot code execution time is based on the current SYSCLK speed. The SYSCLK will be
based on user environment and could be with or without PLL enabled.
Figure 6-7. Warm Reset
Copyright © 2021 Texas Instruments Incorporated
96
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.3 Clock Specifications
6.12.3.1 Clock Sources
Table 6-4. Possible Reference Clock Sources
CLOCK SOURCE
DESCRIPTION
INTOSC1
INTOSC2(1)
X1 (XTAL)
Internal oscillator 1.
Zero-pin overhead 10-MHz internal oscillator.
Internal oscillator 2.
Zero-pin overhead 10-MHz internal oscillator.
External crystal or resonator connected between the X1 and X2 pins or single-ended clock connected to the X1
pin.
(1) On reset, internal oscillator 2 (INTOSC2) is the default clock source for the PLL (OSCCLK).
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
97
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
SYSCLKDIVSEL
PLLSYSCLK
CPUCLK
NMIWD
Watchdog
Timer
SYS
Divider
PLLRAWCLK
FPU
TMU
Flash
SYSPLL
INTOSC1
INTOSC2
X1 (XTAL)
OSCCLK
SYSPLLCLKEN
OSCCLKSRCSEL
CPU
ePIE
CLA
GPIO
Mx RAMs
LSx RAMs
Boot ROM
Message RAMs
DCSM
System Control
WD
SYSCLK
SYSCLK
GSx RAMs
XINT
CPUTIMERs
CLB
I2C
ADC
ECAP
EQEP
EPWM
HRCAL
PMBUS
LIN
FSI
SDFM
EPG
CMPSS
GPDAC
DCAN
MCAN
HIC
DCC
HWBIST
BGCRC
One per SYSCLK peripheral
PCLKCRx
PERx.SYSCLK
ERAD
AES
One per LSPCLK peripheral
LOSPCP
PCLKCRx
PERx.LSPCLK
SCI
SPI
LSPCLK
LSP
Divider
CLKSRCCTL2.CANxBCLKSEL
CAN Bit Clock
Figure 6-8. Clocking System
Copyright © 2021 Texas Instruments Incorporated
98
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
SYSPLL
OSCCLK
INTCLK
VCOCLK
PLLRAWCLK
÷
(REFDIV+1)
÷
(ODIV+1)
VCO
÷
IMULT
Figure 6-9. System PLL
In Figure 6-9,
IMULT
fOSCCLK
REFDIV +1
=
ì
fPLLRAWCLK
ODIV +1
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
99
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of
the internal clocks, and the frequency and switching characteristics of the output clock.
6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
6.12.3.2.1.1 Input Clock Frequency
MIN
10
MAX
20
UNIT
MHz
MHz
f(XTAL)
f(X1)
Frequency, X1/X2, from external crystal or resonator
Frequency, X1, from external oscillator
10
25
6.12.3.2.1.2 XTAL Oscillator Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
–0.3
TYP
MAX
UNIT
X1 VIL
X1 VIH
Valid low-level input voltage
Valid high-level input voltage
0.3 * VDDIO
VDDIO + 0.3
V
V
0.7 * VDDIO
6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
–0.3
MAX
0.3 * VDDIO
VDDIO + 0.3
UNIT
V
X1 VIL
X1 VIH
Valid low-level input voltage
Valid high-level input voltage
0.7 * VDDIO
V
6.12.3.2.1.4 X1 Timing Requirements
MIN
MAX
UNIT
ns
tf(X1)
Fall time, X1
6
6
tr(X1)
Rise time, X1
ns
tw(X1L)
tw(X1H)
Pulse duration, X1 low as a percentage of tc(X1)
Pulse duration, X1 high as a percentage of tc(X1)
45%
45%
55%
55%
6.12.3.2.1.5 AUXCLKIN Timing Requirements
MIN
MAX
6
UNIT
ns
tf(AUXI)
Fall time, AUXCLKIN
tr(AUXI)
tw(AUXL)
tw(AUXH)
Rise time, AUXCLKIN
6
ns
Pulse duration, AUXCLKIN low as a percentage of tc(XCI)
Pulse duration, AUXCLKIN high as a percentage of tc(XCI)
45%
45%
55%
55%
6.12.3.2.1.6 APLL Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
PLL Lock time
SYS PLL Lock Time(1)
5µs + (1024 * (REFDIV + 1) * tc(OSCCLK)
)
us
(1) The PLL lock time here defines the typical time that takes for the PLL to lock once PLL is enabled (SYSPLLCTL1[PLLENA]=1).
Additional time to verify the PLL clock using Dual Clock Comparator (DCC) is not accounted here. TI recommends using the latest
example software from C2000Ware for initializing the PLLs. For the system PLL, see InitSysPll() or SysCtl_setClock().
Copyright © 2021 Texas Instruments Incorporated
100 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.3.2.1.7 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
MIN
MAX
5
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
tr(XCO)
tw(XCOL)
tw(XCOH)
f(XCO)
Rise time, XCLKOUT
5
ns
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
Frequency, XCLKOUT
H – 2(2)
H – 2(2)
H + 2(2)
H + 2(2)
50
ns
ns
MHz
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
6.12.3.2.1.8 Internal Clock Frequencies
MIN
2
NOM
MAX
120
500
20
UNIT
MHz
ns
f(SYSCLK)
tc(SYSCLK)
f(INTCLK)
f(VCOCLK)
f(PLLRAWCLK)
f(PLL)
Frequency, device (system) clock
Period, device (system) clock
8.33
2
Frequency, system PLL going into VCO (after REFDIV)
Frequency, system PLL VCO (before ODIV)
Frequency, system PLL output (before SYSCLK divider)
Frequency, PLLSYSCLK
MHz
MHz
MHz
MHz
MHz
MHz
ns
220
6
600
240
120
2
f(PLL_LIMP)
f(LSP)
Frequency, PLL Limp Frequency (1)
Frequency, LSPCLK
45/(ODIV+1)
2
120
500
tc(LSPCLK)
Period, LSPCLK
8.33
Frequency, OSCCLK (INTOSC1 or INTOSC2 or XTAL or
X1)
f(OSCCLK)
See respective clock
MHz
f(EPWM)
Frequency, EPWMCLK
Frequency, HRPWMCLK
120
120
MHz
MHz
f(HRPWM)
60
(1) PLL output frequency when OSCCLK is dead (Loss of OSCCLK causes PLL to Limp).
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 101
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.3.3 Input Clocks and PLLs
In addition to the internal 0-pin oscillators, three types of external clock sources are supported:
•
•
•
A single-ended 3.3-V external clock. The clock signal should be connected to X1, as shown in Figure 6-10,
with the XTALCR.SE bit set to 1.
An external crystal. The crystal should be connected across X1 and X2 with its load capacitors connected to
VSS as shown in Figure 6-11.
An external resonator. The resonator should be connected across X1 and X2 with its ground connected to
VSS as shown in Figure 6-12.
Microcontroller
Microcontroller
GPIO19
X1
GPIO18
X2
GPIO18*
X2
GPIO19
X1
VSS
VSS
* Available as a
GPIO when X1 is
used as a clock
+3.3 V
VDD
Out
3.3-V Oscillator
Gnd
Figure 6-11. External Crystal
Figure 6-10. Single-ended 3.3-V External Clock
Microcontroller
GPIO18
X2
GPIO19
X1
VSS
Figure 6-12. External Resonator
6.12.3.4 XTAL Oscillator
6.12.3.4.1 Introduction
The XTAL oscillator in this device is an embedded electrical oscillator that when paired with a compatible crystal
can generate the system clock required by the device.
6.12.3.4.2 Overview
The sections below describe the components of the electrical oscillator and crystal.
6.12.3.4.2.1 Electrical Oscillator
The electrical oscillator in this device is a Pierce oscillator design. It is a positive feedback inverter circuit that
requires a tuning circuit in order to oscillate. When it is paired with a compatible crystal, a tank circuit is formed.
This tank circuit oscillates at the fundamental frequency of the crystal component. On this device, it is designed
to operate in parallel resonance mode due to the shunt capacitor (C0) and required load capacitors (CL). Figure
6-13 illustrates the components of the electrical oscillator and the tank circuit.
Copyright © 2021 Texas Instruments Incorporated
102 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
To Rest of Chip
MCU
XTAL Oscillator
Buffer
0
1
Comp
XCLKOUT
Circuit
[XTAL On]
Rbias
Pierce Inverter
Internal
External
Internal
External
Rd
Crystal
CL1
CL2
GND
GND
Figure 6-13. Electrical Oscillator Block Diagram
6.12.3.4.2.1.1 Modes of Operation
The electrical oscillator in this device has two modes of operation: crystal mode and single-ended mode.
6.12.3.4.2.1.1.1 Crystal Mode of Operation
In crystal mode of operation, a quartz crystal with load capacitors has to be connected to X1 and X2.
This mode of operation is engaged when [XTAL On]=1 which is achieved by setting XTALCR.OSCOFF=0 and
XTALCR.SE=0. There is an internal bias resistor for the feedback loop so an external one should not be used.
Adding an external bias resistor will create a parallel resistance with the internal Rbias, moving the bias point
of operation and possibly leading to clipped waveforms, out of spec duty cycle and reduction in the effective
negative resistance.
In this mode of operation, the resultant clock on X1 is passed through a comparator (Comp) to the rest of the
chip. The clock on X1 needs to meet the VIH and VIL of the comparator. See XTAL Oscillator Characteristics
table for the VIH and VIL requirements of the comparator.
6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
In the single-ended mode of operation, a clock signal is connected to X1 with X2 left unconnected. A quartz
crystal should not be used in this mode.
This mode is enabled when [XTAL On]=0 which can be achieved by setting XTALCR.OSCOFF=1 and
XTALCR.SE=1.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 103
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
In this mode of operation, the clock on X1 is passed through a buffer (Buffer) to the rest of the chip. See X1 Input
Level Characteristics When Using an External Clock Source (Not a Crystal) table for the input requirements of
the buffer.
6.12.3.4.2.1.2 XTAL Output on XCLKOUT
The output of the electrical oscillator that is fed to the rest of the chip can be brought out on XCLKOUT for
observation by configuring CLKSRCCTL3.XCLKOUTSEL and XCLKOUTDIVSEL.XCLKOUTDIV registers . See
the GPIO mux table for a list of GPIOs that XCLKOUT comes out on.
6.12.3.4.2.2 Quartz Crystal
Electrically, a quartz crystal can be represented by an LCR circuit (Inductor-Capacitor-Resistor). However, unlike
an LCR circuit, crystals have very high Q due to the low motional resistance and are also very underdamped.
Components of the crystal are shown in Figure 6-14 and explained below.
Quartz Crystal
Internal
External
Cm
Rm
C0
CL
Lm
Figure 6-14. Crystal Electrical Representation
Cm (Motional capacitance): Denotes the elasticity of the crystal.
Rm (Motional resistance): Denotes the resistive losses within the crystal. This is not the ESR of the crystal but
can be approximated as such depending on the values of the other crystal components.
Lm (Motional inductance): Denotes the vibrating mass of the crystal.
C0 (Shunt capacitance): The capacitance formed from the two crystal electrodes and stray package
capacitance.
CL (Load capacitance): This is the effective capacitance seen by the crystal at its electrodes. It is external to
the crystal. The frequency ppm specified in the crystal datasheet is usually tied to the CL parameter.
Note that most crystal manufacturers specify CL as the effective capacitance seen at the crystal pins while some
crystal manufacturers specify the CL as the capacitance on just one of the crystal pins. Check with the crystal
manufacturer for how the CL is specified in order to use the correct values in calculations.
From Figure 6-13, CL1 and CL2 are in series so to find the equivalent total capacitance seen by the crystal, the
capacitance series formula has to be applied which simply evaluates to [CL1]/2 if CL1=CL2.
It is recommended to add stray PCB capacitance to this value. 3pF to 5pF are reasonable estimates but the
actual value will depend on the PCB in question.
Note that the load capacitance is a requirement of both the electrical oscillator and crystal. The value chosen has
to satisfy both the electrical oscillator and the crystal.
Copyright © 2021 Texas Instruments Incorporated
104 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
The effect of CL on the crystal is frequency pulling. If the effective load capacitance is lower than the target, the
crystal frequency will increase and vice-versa. However, the effect of frequency pulling is usually very minimal
and typically results in less than 10ppm variation from the nominal frequency.
6.12.3.4.2.3 GPIO Modes of Operation
On this device, X1 and X2 can be used as GPIO19 and GPIO18 respectively depending on the operating mode
of the XTAL. Refer to the External Oscillator (XTAL) TRM section.
6.12.3.4.3 Functional Operation
6.12.3.4.3.1 ESR - Effective Series Resistance
This is the resistive load the crystal presents to the electrical oscillator at resonance. The higher the ESR, the
lower the Q and less likelihood the crystal will start-up or maintain oscillation. The relationship between ESR and
the crystal components is indicated below.
2
C0
CL
ESR = Rm * 1 +
(1)
Note that the ESR is not the same as motional resistance of the crystal but can be approximated as such if the
effective load capacitance is much greater than the shunt capacitance.
6.12.3.4.3.2 Rneg - Negative Resistance
Negative resistance is the impedance presented by the electrical oscillator to the crystal. It is the amount of
energy the electrical oscillator must supply to the crystal to overcome the losses incurred during oscillation. It
depicts a circuit that provides rather than consume energy and can also be viewed as the overall gain of the
circuit.
The generally accepted practice is to have Rneg > 3x-5x ESR to ensure the crystal starts up under all
conditions. Note that it takes slightly more energy to start-up the crystal than it does to sustain oscillation and
hence if it can be ensured that the negative resistance requirement is met at start-up, then oscillation sustenance
will not be an issue.
Figure 6-15 and Figure 6-16 show the variation between negative resistance and the crystal components for this
device. As can be seen from the chart, the crystal shunt capacitance (C0) and effective load capacitance (CL)
greatly influence the negative resistance of the electrical oscillator. Note that these are typical graphs so refer to
Table 6-5 for min/max values for design considerations.
6.12.3.4.3.3 Start-up Time
Start-up time is an important consideration when selecting the components of the crystal circuit. As mentioned
in the negative resistance section, for reliable start-up across all conditions, it is recommended that the Rneg >
3x-5x the ESR of the crystal.
Crystal ESR and dampening resistor (Rd) greatly affect the start-up time. The higher the two, the longer the
crystal takes to start-up. Longer start-up times are usually a sign the crystal and components are not a correct
match.
Refer to Crystal Oscillator Specifications for the typical start-up times. Note that the numbers specified here are
typical numbers provided for guidance only. Actual start-up time depends heavily on the crystal in question and
the external components.
6.12.3.4.3.3.1 X1/X2 Precondition
On this device, the GPIO19/18 alternate functionality on X1/X2 can be used to speed up the start-up time of the
crystal if needed. This functionality is achieved by preconditioning the load capacitors CL1 and CL2 to a known
state before the XTAL is turned on. See the TRM for details.
6.12.3.4.3.4 DL - Drive Level
Drive level refers to how much power is provided by the electrical oscillator and dissipated by the crystal. The
maximum drive level specified in the crystal manufacturer’s datasheet is usually the maximum the crystal can
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 105
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
dissipate without damage or significant reduction in operating life. On the other hand, the drive level specified
by the electrical oscillator is the maximum power it can provide. The actual power provided by the electrical
oscillator is not necessarily the max power and depends on the crystal and board components.
For cases where the actual drive level from the electrical oscillator exceeds the maximum drive level
specification of the crystal, a dampening resistor (Rd) should be installed to limit the current and reduce the
power dissipated by the crystal. Note that Rd reduces the circuit gain and hence the actual value to use should
be evaluated to make sure all other conditions for start-up and sustained oscillation are met.
6.12.3.4.4 How to Choose a Crystal
Using Crystal Oscillator Specifications as a reference:
1. Pick a crystal frequency e.g: 20MHz
2. Check that the ESR of the crystal <=50Ω per specifications for 20MHz.
3. Check that the load capacitance requirement of the crystal manufacturer is within 6pF and 12pF per
specifications for 20MHz.
•
•
As mentioned, CL1 and CL2 are in series so provided CL1=CL2, effective load capacitance CL = [CL1]/2
Adding board parasitics to this results in CL = [CL1]/2 + Cstray
4. Check that the maximum drive level of the crystal >= 1mW. If this requirement is not met, a dampening
resistor Rd can be used. Refer to DL - Drive Level on other points to consider when using Rd.
6.12.3.4.5 Testing
It is recommended that the user have the crystal manufacturer completely characterize the crystal with their
board to ensure the crystal always starts up and maintains oscillation.
Below is a brief overview of some measurements that can be performed:
Due to how sensitive the crystal circuit is to capacitance, it is recommended not to connect scope probes to X1
and X2. If scope probes must be used to monitor X1/X2, an active probe with <1pF capacitance should be used.
Frequency
1. Bring out the XTAL on XCLKOUT.
2. Measure this frequency as the crystal frequency.
Negative Resistance
1. Bring out the XTAL on XCLKOUT.
2. Place a potentiometer in series with the crystal between the load capacitors.
3. Increase the resistance of the potentiometer until the clock on XCLKOUT stops.
4. This resistance plus the crystal’s actual ESR is the negative resistance of the electrical oscillator.
Start-Up Time
1. Turn off the XTAL.
2. Bring out the XTAL on XCLKOUT.
3. Turn on the XTAL and measure how long it takes the clock on XCLKOUT to stay within 45% and 55% duty
cycle.
6.12.3.4.6 Common Problems and Debug Tips
Crystal Fails to Start-Up
•
Go through how to select a crystal section and make sure there are no violations.
Crystal Takes a Long Time to Start-Up
•
•
If a dampening resistor Rd is installed, it is too high.
If no dampening resistor is installed, either the crystal ESR is too high or the overall circuit gain is too low due
to high load capacitance.
6.12.3.4.7 Crystal Oscillator Specifications
6.12.3.4.7.1 Crystal Oscillator Parameters
MIN
MAX
UNIT
CL1, CL2
Load capacitance
12
24
pF
Copyright © 2021 Texas Instruments Incorporated
106 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.3.4.7.1 Crystal Oscillator Parameters (continued)
MIN
MAX
UNIT
C0
Crystal shunt capacitance
7
pF
6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
For the Crystal Equivalent Series Resistance (ESR) Requirements table:
1. Crystal shunt capacitance (C0) should be less than or equal to 7 pF.
2. ESR = Negative Resistance/3
Table 6-5. Crystal Equivalent Series Resistance (ESR) Requirements
MAXIMUM ESR (Ω)
(CL1 = CL2 = 12 pF)
MAXIMUM ESR (Ω)
(CL1 = CL2 = 24 pF)
CRYSTAL FREQUENCY (MHz)
10
12
14
16
18
20
55
50
50
45
45
45
110
95
90
75
65
50
Negative Resistance vs. 10MHz Crystal
3000
2500
2000
1500
1000
500
C0 (pF)
1
3
5
7
9
0
2
4
6
8
10
12
14
16
Effective CL (pF)
Figure 6-15. Negative Resistance Variation at 10MHz
Negative Resistance vs. 20MHz Crystal
1600
1400
1200
1000
800
600
400
200
0
C0 (pF)
1
3
5
7
9
2
4
6
8
10
12
14
16
Effective CL (pF)
Figure 6-16. Negative Resistance Variation at 20MHz
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 107
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.3.4.7.3 Crystal Oscillator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ESR MAX = 110 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
f = 10 MHz
4
ms
Start-up
time(1)
ESR MAX = 50 Ω
CL1 = CL2 = 24 pF
C0 = 7 pF
f = 20 MHz
2
ms
Crystal drive level (DL)
1
mW
(1) Start-up time is dependent on the crystal and tank circuit components. TI recommends that the crystal vendor characterize the
application with the chosen crystal.
Copyright © 2021 Texas Instruments Incorporated
108 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.3.5 Internal Oscillators
To reduce production board costs and application development time, all F28003x devices contain two
independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, INTOSC2 is set as the
source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
Applications requiring tighter SCI baud rate matching can use the SCI baud tuning example
(baud_tune_via_uart) available in C2000Ware.
6.12.3.5.1 INTOSC Characteristics
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
9.75 (-2.5%)
9.85 (-1.5%)
TYP
10
MAX
10.15 (1.5%)
10.15 (1.5%)
UNIT
MHz
MHz
Frequency, INTOSC1 and
INTOSC2
-40℃ to 125℃
fINTOSC
Frequency, INTOSC1 and
INTOSC2
-10℃ to 90℃
10
Frequency stability at room
temperature
30°C, Nominal
VDD
fINTOSC-STABILITY
tINT0SC-ST
±0.1
%
Start-up and settling time
20
µs
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 109
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.4 Flash Parameters
Table 6-6 lists the minimum required Flash wait states with different clock sources and frequencies. Wait state is
the value set in register FRDCNTL[RWAIT].
Table 6-6. Minimum Required Flash Wait States with Different Clock Sources and Frequencies
EXTERNAL OSCILLATOR OR CRYSTAL
INTOSC1 OR INTOSC2
CPUCLK (MHz)
NORMAL
OPERATION
BANK OR PUMP
SLEEP(1)
BANK OR PUMP
NORMAL OPERATION
SLEEP(1)
116 < CPUCLK ≤ 120
100 < CPUCLK ≤ 116
97 < CPUCLK ≤ 100
80 < CPUCLK ≤ 97
77 < CPUCLK ≤ 80
60 < CPUCLK ≤ 77
58 < CPUCLK ≤ 60
40 < CPUCLK ≤ 58
38 < CPUCLK ≤ 40
20 < CPUCLK ≤ 38
19 < CPUCLK ≤ 20
CPUCLK ≤ 19
6
5
5
4
4
3
3
2
2
1
1
0
5
4
3
2
1
0
5
4
3
2
1
0
(1) Flash SLEEP operations require an extra wait state when using INTOSC as the clock source for the frequency ranges indicated. Any
wait state FRDCNTL[RWAIT] change must be made before beginning a SLEEP mode operation. This setting impacts both flash banks.
The F28003x devices have an improved 128-bit prefetch buffer that provides high flash code execution efficiency
across wait states. Figure 6-17 and Figure 6-18 illustrate typical efficiency across wait-state settings compared
to previous-generation devices with a 64-bit prefetch buffer. Wait-state execution efficiency with a prefetch buffer
will depend on how many branches are present in application software. Two examples of linear code and
if-then-else code are provided.
100%
90%
80%
70%
60%
50%
40%
30%
100%
95%
90%
85%
80%
75%
70%
65%
60%
55%
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
Flash with 64-Bit Prefetch
Flash with 128-Bit Prefetch
0
1
2
3
4
5
0
1
2
3
4
5
Wait State
Wait State
D005
D006
Figure 6-17. Application Code With Heavy 32-Bit
Floating-Point Math Instructions
Figure 6-18. Application Code With 16-Bit If-Else
Instructions
Copyright © 2021 Texas Instruments Incorporated
110
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Section 6.12.4.1 lists the Flash parameters.
Note
The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit
word may only be programmed once per write/erase cycle.
Note
It is important to provide the correct sector mask for the bank erase command. If the mask is
mistakenly chosen to erase an inaccessible sector (belongs to another security zone), the bank erase
command will continue attempting to erase the sector endlessly and the FSM will never exit (since
erase will not succeed). To avoid such a situation, user must take care to provide the correct mask.
However, given that there is a chance of choosing an incorrect mask, TI suggests to initialize the max
allowed erase pulses to zero after the max number of pulses are issued by the FSM for the bank
erase operation. This will ensure that the FSM will end the bank erase command after trying to erase
the inaccessible sector up to the max allowed erase pulses.
The Example_EraseBanks() function in the C2000Ware’s flash API usage example depicts the
implementation of this sequence (content of the while loop waiting for the FSM to complete the bank
erase command). Users must use this code as-is irrespective of whether or not security is used by the
application to also ensure that the FSM exits from bank erase operations in case of an erase-failure.
6.12.4.1 Flash Parameters
PARAMETER
MIN
TYP
150
50
MAX UNIT
128 data bits + 16 ECC bits
8KB (Sector)
300
100
56
µs
ms
ms
ms
ms
ms
ms
ms
ms
ms
Program Time(1)
< 25 cycles
1k cycles
2k cycles
20k cycles
< 25 cycles
1k cycles
2k cycles
20k cycles
15
26
133
226
1026
78
Sector EraseTime(2) (3)
8KB (Sector)
128KB (Bank)
31
123
21
35
183
310
1410
Bank EraseTime(2) (3)
42
169
Nwec Write/Erase Cycles per Sector
20000 cycles
100000 cycles
Nwec Write/Erase Cycles for Entire Flash
(Combined for all Sectors)
tretention Data retention duration at TJ =
85oC
20
years
(1) Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include
the time to transfer the following into RAM:
• Code that uses flash API to program the flash
• Flash API itself
• Flash data to be programmed
In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for
programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.
Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes
Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.
Erase time includes Erase verify by the CPU and does not involve any data transfer.
(2) Erase time includes Erase verify by the CPU.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
111
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.5 Emulation/JTAG
The JTAG (IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture) port has
four dedicated pins: TMS, TDI, TDO, and TCK. The cJTAG (IEEE Standard 1149.7-2009 for Reduced-Pin and
Enhanced-Functionality Test Access Port and Boundary-Scan Architecture) port is a compact JTAG interface
requiring only two pins (TMS and TCK), which allows other device functionality to be muxed to the traditional
GPIO35 (TDI) and GPIO37 (TDO) pins.
Typically, no buffers are needed on the JTAG signals when the distance between the MCU target and the JTAG
header is smaller than 6 inches (15.24 cm), and no other devices are present on the JTAG chain. Otherwise,
each signal should be buffered. Additionally, for most JTAG debug probe operations at 10 MHz, no series
resistors are needed on the JTAG signals. However, if high emulation speeds are expected (35 MHz or so), 22-Ω
resistors should be placed in series on each JTAG signal.
The PD (Power Detect) pin of the JTAG debug probe header should be connected to the board's 3.3-V supply.
Header GND pins should be connected to board ground. TDIS (Cable Disconnect Sense) should also be
connected to board ground. The JTAG clock should be looped from the header TCK output pin back to the
RTCK input pin of the header (to sense clock continuity by the JTAG debug probe). This MCU does not support
the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers. These signals should
always be pulled up at the emulation header through a pair of board pullup resistors ranging from 2.2 kΩ to
4.7 kΩ (depending on the drive strength of the debugger ports). Typically, a 2.2-kΩ value is used.
Header pin RESET is an open-drain output from the JTAG debug probe header that enables board components
to be reset through JTAG debug probe commands (available only through the 20-pin header). Figure 6-19 shows
how the 14-pin JTAG header connects to the MCU’s JTAG port signals. Figure 6-20 shows how to connect to
the 20-pin JTAG header. The 20-pin JTAG header pins EMU2, EMU3, and EMU4 are not used and should be
grounded.
For more information about hardware breakpoints and watchpoints, see Hardware Breakpoints and Watchpoints
in CCS for C2000 devices.
For more information about JTAG emulation, see the XDS Target Connection Guide.
Note
JTAG Test Data Input (TDI) is the default mux selection for the pin. The internal pullup is disabled by
default. If this pin is used as JTAG TDI, the internal pullup should be enabled or an external pullup
added on the board to avoid a floating input. In the cJTAG option, this pin can be used as GPIO.
JTAG Test Data Output (TDO) is the default mux selection for the pin. The internal pullup is disabled
by default. The TDO function will be in a tri-state condition when there is no JTAG activity, leaving this
pin floating. The internal pullup should be enabled or an external pullup added on the board to avoid a
floating GPIO input. In the cJTAG option, this pin can be used as GPIO.
Copyright © 2021 Texas Instruments Incorporated
112
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
2
1
TMS
TMS
TRST
3.3 V
10 kΩ
3.3 V
10 kΩ
TDI(A)
TDI
TDIS
GND
3
4
MCU
100 Ω
5
7
6
3.3 V
PD
KEY
TDO(A)
TCK
TDO
RTCK
TCK
EMU0
GND
8
9
10
GND
11
13
12
GND
4.7 kΩ
14
4.7 kΩ
3.3 V
EMU1
3.3 V
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 6-19. Connecting to the 14-Pin JTAG Header
Distance between the header and the target
should be less than 6 inches (15.24 cm).
3.3 V
4.7 kΩ
3.3 V
10 kΩ
3.3 V
10 kΩ
2
1
TMS
TMS
TRST
TDI(A)
TDI
TDIS
KEY
GND
3
5
4
MCU
100 Ω
6
3.3V
PD
TDO(A)
TDO
GND
GND
GND
EMU1
GND
EMU3
GND
7
8
9
10
12
14
16
18
20
RTCK
TCK
11
13
15
17
19
TCK
Ω
4.7 kΩ
4.7 k
3.3 V
EMU0
RESET
EMU2
EMU4
3.3 V
Open
Drain
A low pulse from the JTAG debug probe
can be tied with other reset sources
to reset the board.
GND
GND
A. TDI and TDO connections are not required for cJTAG option and these pins can be used as GPIOs instead.
Figure 6-20. Connecting to the 20-Pin JTAG Header
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
113
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.5.1 JTAG Electrical Data and Timing
6.12.5.1.1 JTAG Timing Requirements
NO.
MIN
66.66
26.66
26.66
7
MAX
UNIT
ns
1
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCKH)
tsu(TMS-TCKH)
th(TCKH-TDI)
th(TCKH-TMS)
3
4
ns
ns
7
7
7
6.12.5.1.2 JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
UNIT
2
td(TCKL-TDO)
Delay time, TCK low to TDO valid
6
20
ns
6.12.5.1.3 JTAG Timing Diagram
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
Figure 6-21. JTAG Timing
Copyright © 2021 Texas Instruments Incorporated
114
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.5.2 cJTAG Electrical Data and Timing
6.12.5.2.1 cJTAG Timing Requirements
NO.
MIN
100
40
40
7
MAX
UNIT
ns
1
tc(TCK)
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TMS valid to TCK high
Input setup time, TMS valid to TCK low
Input hold time, TMS valid from TCK high
Input hold time, TMS valid from TCK low
ns
tw(TCKL)
ns
tsu(TMS-TCKH)
tsu(TMS-TCKL)
th(TCKH-TMS)
th(TCKL-TMS)
ns
3
4
7
ns
2
ns
2
ns
6.12.5.2.2 cJTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MIN
MAX
20
UNIT
ns
2
5
td(TCKL-TMS)
Delay time, TCK low to TMS valid
Delay time, TCK high to TMS disable
5
tdis(TCKH-TMS)
20
ns
6.12.5.2.3 cJTAG Timing Diagram
1
1a
1b
2
3
3
4
4
5
TCK
TMS
TMS Input
TMS Output
TMS Input
Figure 6-22. cJTAG Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
115
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.6 GPIO Electrical Data and Timing
The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins
are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to
filter unwanted noise glitches.
The GPIO module contains an Output X-BAR which allows an assortment of internal signals to be routed to
a GPIO in the GPIO mux positions denoted as OUTPUTXBARx. The GPIO module also contains an Input
X-BAR which is used to route signals from any GPIO input to different IP blocks such as the ADCs, eCAPs,
ePWMs, and external interrupts. For more details, see the X-BAR chapter in the TMS320F28003x Real-Time
Microcontrollers Technical Reference Manual.
6.12.6.1 GPIO – Output Timing
6.12.6.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
Rise time, GPIO switching low to high
MIN
MAX
8(1)
8(1)
50
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
All GPIOs
All GPIOs
Fall time, GPIO switching high to low
Toggling frequency, GPIO pins
ns
MHz
(1) Rise time and fall time vary with load. These values assume a 20-pF load.
6.12.6.1.2 General-Purpose Output Timing Diagram
GPIO
tr(GPO)
tf(GPO)
Figure 6-23. General-Purpose Output Timing
Copyright © 2021 Texas Instruments Incorporated
116
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.6.2 GPIO – Input Timing
6.12.6.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SYSCLK)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
QUALPRD ≠ 0
tw(SP)
Sampling period
2tc(SYSCLK) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SYSCLK)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
6.12.6.2.2 Sampling Mode
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
(SYSCLK cycle * 2 * QUALPRD) * 5(C)
Sampling Window
SYSCLK
QUALPRD = 1
(SYSCLK/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n", the qualification sampling period in 2n
SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or greater. In other words,
the inputs should be stable for (5 × QUALPRD × 2) SYSCLK cycles. This would ensure 5 sampling periods for detection to occur.
Because external signals are driven asynchronously, an 13-SYSCLK-wide pulse ensures reliable recognition.
Figure 6-24. Sampling Mode
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
117
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.6.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
Sampling frequency = SYSCLK/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLK, if QUALPRD = 0
Sampling period = SYSCLK cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the previous equations, SYSCLK cycle indicates the time period of SYSCLK.
Sampling period = SYSCLK cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLK cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLK cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 6-25. General-Purpose Input Timing
Copyright © 2021 Texas Instruments Incorporated
118
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.7 Interrupts
The C28x CPU has fourteen peripheral interrupt lines. Two of them (INT13 and INT14) are connected directly
to CPU timers 1 and 2, respectively. The remaining twelve are connected to peripheral interrupt signals through
the enhanced Peripheral Interrupt Expansion (ePIE) module. The ePIE multiplexes up to sixteen peripheral
interrupts into each CPU interrupt line. It also expands the vector table to allow each interrupt to have its own
ISR. This allows the CPU to support a large number of peripherals.
An interrupt path is divided into three stages—the peripheral, the ePIE, and the CPU. Each stage has its
own enable and flag registers. This system allows the CPU to handle one interrupt while others are pending,
implement and prioritize nested interrupts in software, and disable interrupts during certain critical tasks.
Figure 6-26 shows the interrupt architecture for this device.
TINT0
TIMER0
LPMINT
WDINT
LPM Logic
WD
WAKEINT
NMI module
ERAD
NMI
RTOSINT
CPU
INPUTXBAR4
XINT1 Control
INPUTXBAR5
INPUTXBAR6
INPUTXBAR13
INPUTXBAR14
XINT2 Control
XINT3 Control
XINT4 Control
XINT5 Control
GPIO0
to
GPIOx
ePIE
INT1
to
INT12
Input
X-BAR
TIMER1
TIMER2
INT13
INT14
Peripherals
See ePIE Table
Figure 6-26. Device Interrupt Architecture
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
119
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.7.1 External Interrupt (XINT) Electrical Data and Timing
For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.12.7.1.1 External Interrupt Timing Requirements
MIN
2tc(SYSCLK)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
tw(INT)
Pulse duration, INT input low/high
tw(IQSW) + tw(SP) + 1tc(SYSCLK)
6.12.7.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(INT) Delay time, INT low/high to interrupt-vector fetch(1)
tw(IQSW) + 14tc(SYSCLK)
tw(IQSW) + tw(SP) + 14tc(SYSCLK) cycles
(1) This assumes that the ISR is in a single-cycle memory.
6.12.7.1.3 External Interrupt Timing
tw(INT)
XINT1, XINT2, XINT3,
XINT4, XINT5
td(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-27. External Interrupt Timing
Copyright © 2021 Texas Instruments Incorporated
120 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.8 Low-Power Modes
This device has HALT, IDLE and STANDBY as clock-gating low-power modes.
Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low
Power Modes section of the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual.
6.12.8.1 Clock-Gating Low-Power Modes
IDLE and HALT modes on this device are similar to those on other C28x devices. Table 6-7 describes the effect
on the system when any of the clock-gating low-power modes are entered.
Table 6-7. Effect of Clock-Gating Low-Power Modes on the Device
MODULES/
CLOCK DOMAIN
IDLE
STANDBY
HALT
SYSCLK
Active
Gated
Active
Gated
Gated
Gated
Gated
Gated
Gated
CPUCLK
Clock to modules connected
to PERx.SYSCLK
WDCLK
PLL
Active
Active
Gated if CLKSRCCTL1.WDHALTI = 0
Software must power down PLL before entering HALT.
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered down if CLKSRCCTL1.WDHALTI = 0
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
Powered
INTOSC1
INTOSC2
Flash(1)
XTAL(2)
Powered
(1) The Flash module is not powered down by hardware in any LPM. It may be powered down using software if required by the
application. For more information, see the Flash and OTP Memory section of the System Control chapter in the TMS320F28003x
Real-Time Microcontrollers Technical Reference Manual.
(2) The XTAL is not powered down by hardware in any LPM. It may be powered down by software setting the XTALCR.OSCOFF bit to 1.
This can be done at any time during the application if the XTAL is not required.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 121
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.12.8.2 Low-Power Mode Wake-up Timing
For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.12.8.2.1 IDLE Mode Timing Requirements
MIN
2tc(SYSCLK)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE)
Pulse duration, external wake-up signal
cycles
2tc(SYSCLK) + tw(IQSW)
6.12.8.2.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Without input qualifier
With input qualifier
40tc(SYSCLK) cycles
From Flash (active state)
40tc(SYSCLK) + tw(WAKE) cycles
(2)
Without input qualifier
9316tc(SYSCLK)
cycles
cycles
Delay time, external wake signal to
(2)
td(WAKE-IDLE)
From Flash (sleep state)
From RAM
program execution resume(1)
9316tc(SYSCLK)
+
With input qualifier
tw(WAKE)
Without input qualifier
With input qualifier
25tc(SYSCLK) cycles
25tc(SYSCLK) + tw(WAKE) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP].
6.12.8.2.3 IDLE Entry and Exit Timing Diagram
td(WAKE-IDLE)
Address/Data
(internal)
XCLKOUT
tw(WAKE)
WAKE(A)
A. WAKE can be any enabled interrupt, WDINT or XRSn. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.
Figure 6-28. IDLE Entry and Exit Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
122 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
ꢀ
6.12.8.2.4 STANDBY Mode Timing Requirements
MIN
MAX
UNIT
QUALSTDBY = 0 | 2tc(OSCCLK)
3tc(OSCCLK)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
QUALSTDBY > 0 |
(2 + QUALSTDBY) * tc(OSCCLK)
(1)
(2 + QUALSTDBY)tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
6.12.8.2.5 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Delay time, IDLE instruction executed to
XCLKOUT stop
td(IDLE-XCOS)
16tc(INTOSC1) cycles
Wakeup from flash
(Flash module in
active state)
td(WAKE-STBY)
175tc(SYSCLK) + tw(WAKE-INT) cycles
Delay time, external wake signal to program
execution resume(1)
Wakeup from flash
(Flash module in
sleep state)
td(WAKE-STBY)
td(WAKE-STBY)
9316tc(SYSCLK) (2) + tw(WAKE-INT) cycles
Wakeup from RAM
3tc(OSC) + 15tc(SYSCLK) + tw(WAKE-INT) cycles
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP].
6.12.8.2.6 STANDBY Entry and Exit Timing Diagram
(C)
(F)
(A)
(B)
(D)(E)
(G)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
OSCCLK
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wakeup pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 6-29. STANDBY Entry and Exit Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 123
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
ꢀ
6.12.8.2.7 HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal(1)
Pulse duration, XRS wake-up signal(1)
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See Crystal Oscillator (XTAL) section for more information. For applications using INTOSC1 or
INTOSC2 for OSCCLK, see the Internal Oscillators section for toscst. Oscillator start-up time does not apply to applications using a
single-ended crystal on the X1 pin, as it is powered externally to the device.
6.12.8.2.8 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
Delay time, IDLE instruction executed to XCLKOUT
stop
td(IDLE-XCOS)
16tc(INTOSC1) cycles
Delay time, external wake signal end to CPU1 program
execution resume
Wakeup from Flash - Flash module in active state
Wakeup from Flash - Flash module in sleep state
Wakeup from RAM
75tc(OSCCLK)
td(WAKE-HALT)
cycles
(1)
9316tc(SYSCLK)+75tc(OSCCLK)
75tc(OSCCLK)
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP].
Copyright © 2021 Texas Instruments Incorporated
124 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.12.8.2.9 HALT Entry and Exit Timing Diagram
(C)
(F)
(A)
(B)
(D)(E)
HALT
(G)
Device
Status
HALT
Flushing Pipeline
Normal
Execution
GPIOn
td(WAKE-HALT)
tw(WAKE-GPIO)
OSCCLK
Oscillator Start-up Time
XCLKOUT
td(IDLE-XCOS)
A. IDLE instruction is executed to put the device into HALT mode.
B. The LPM block responds to the HALT signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off. This
delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock
source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes very little power. It is possible
to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT MODE. This is done by writing 1
to CLKSRCCTL1.WDHALTI. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up
sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean
clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure,
care should be taken to maintain a low noise environment before entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the
device may not exit low-power mode for subsequent wake-up pulses.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after some latency. The HALT mode is now
exited.
G. Normal operation resumes.
H. The user must relock the PLL upon HALT wakeup to ensure a stable PLL lock.
Figure 6-30. HALT Entry and Exit Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 125
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.13 Analog Peripherals
The analog subsystem module is described in this section.
The analog modules on this device include the ADC, temperature sensor, CMPSS, and buffered DAC.
The analog subsystem has the following features:
•
Flexible voltage references
– The ADCs are referenced to VREFHIx and VSSA pins
•
VREFHIx pin voltage can be driven in externally or can be generated by an internal bandgap voltage
reference
•
The internal voltage reference range can be selected to be 0V to 3.3V or 0V to 2.5V
– The buffered DACs are referenced to VREFHIx and VSSA
Alternately, these DACs can be referenced to the VDAC pin and VSSA
– The comparator DACs are referenced to VDDA and VSSA
Alternately, these DACs can be referenced to the VDAC pin and VSSA
•
•
•
Flexible pin usage
– Buffered DAC outputs, comparator subsystem inputs, and digital inputs (AIOs)/outputs (AGPIOs) are
multiplexed with ADC inputs
– Internal connection to VREFLO on all ADCs for offset self-calibration
Figure 6-31 shows the Analog Subsystem Block Diagram for the 100-pin PZ LQFP.
Figure 6-32 shows the Analog Subsystem Block Diagram for the 80-pin PN LQFP.
Figure 6-33 shows the Analog Subsystem Block Diagram for the 64-pin PM LQFP.
Figure 6-34 shows the Analog Subsystem Block Diagram for the 48-pin PT LQFP.
Figure 6-35 shows the analog group connections. Section 6.13.1 lists the analog pins and internal connections.
Section 6.13.2 lists descriptions of analog signals.
Copyright © 2021 Texas Instruments Incorporated
126 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
VREFHI
Comparator Subsystem 1
CMP1_HP
CTRIP1H
VREFLO
Digital
CMP1_HN
Filter
VDDA or VDAC
CTRIPOUT1H
Reference Circuit
ANAREFSEL
DAC12
DAC12
Misc. Analog
Temp Sensor
(C12)
CTRIP1L
Digital
Filter
CMP1_LN
CMP1_LP
CTRIPOUT1L
Vref
REFLO
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
HPMXSEL4/
HPMXSEL2/
HPMXSEL0/
/LPMXSEL4/
/LPMXSEL2/
/LPMXSEL0/
A1/B7/DACB_OUT
A6
A2/B6/C9
A11/B10/C0
B5, B5/GPIO20
REFHI
DAC12
DAC12
ADC Inputs
A0 to A15
CTRIP2L
Digital
Filter
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
ADC-A
12-bits
CMP2_LN
CMP2_LP
CTRIPOUT2L
HPMXSEL5/
/LPMXSEL5/
AGPIO
B9/C7
AIO
CMPSS1 Input MUX
Comparator Subsystem 3
REFLO
CMP3_HP
CMP3_HN
CTRIP3H
Digital
Filter
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
A10/B1/C10
VDDA or VDAC
CTRIPOUT3H
HPMXSEL2/
HPMXSEL0/
/LPMXSEL2/
/LPMXSEL0/
A9
A4/B8
A12
A5
B0/C11
DAC12
DAC12
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
REFHI
HPMXSEL5/
HPMXSEL4/
/LPMXSEL5/
/LPMXSEL4/
CTRIP3L
Digital
Filter
ADC Inputs
B0 to B15
CMP3_LN
CMP3_LP
CTRIPOUT3L
ADC-B
12-bits
AIO
CMPSS2 Input MUX
C5
B2/C6
B3/VDAC
Comparator Subsystem 4
HPMXSEL0/
/LPMXSEL0/
CMP4_HP
CMP4_HN
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL4/ /LPMXSEL4/
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
REFLO
CTRIP4H
Digital
Filter
A14/B14/C4
B12/C2
VDDA or VDAC
CTRIPOUT4H
HPMXSEL5/
HPMXSEL2/
/LPMXSEL5/
/LPMXSEL2/
A3
DAC12
DAC12
A0/B15/C15/DACA_OUT
CTRIP4L
REFHI
Digital
Filter
AIO
CMP4_LN
CMP4_LP
CMPSS3 Input MUX
ADC Inputs
C0 to C15
CTRIPOUT4L
ADC-C
12-bits
B4/C8
C14
HPMXSEL0/
/LPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL2/
/LPMXSEL2/
C1
A8
HPMXSEL4/
HPMXSEL5/
/LPMXSEL4/
/LPMXSEL5/
REFLO
B11, B11/GPIO21
A7/C3
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
CMPSS Inputs
AGPIO
AGO
AIO
CMPSS4 Input MUX
VREFHI
VDAC
12-bit
Buffered
DACA_OUT
DAC-A
VREFHI
VDAC
12-bit
Buffered
DAC-B
DACB_OUT
Figure 6-31. Analog Subsystem Block Diagram (100-Pin PZ LQFP)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 127
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
VREFHI
VREFLO
Comparator Subsystem 1
Digital
CMP1_HP
CMP1_HN
CTRIP1H
Filter
VDDA or VDAC
CTRIPOUT1H
Reference Circuit
ANAREFSEL
DAC12
DAC12
Misc. Analog
CTRIP1L
Digital
Filter
CMP1_LN
CMP1_LP
CTRIPOUT1L
Temp Sensor
(C12)
Vref
REFLO
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
HPMXSEL4/
HPMXSEL2/
HPMXSEL0/
/LPMXSEL4/
/LPMXSEL2/
/LPMXSEL0/
A1/B7/DACB_OUT
A6
VDDA or VDAC
CTRIPOUT2H
A2/B6/C9
REFHI
DAC12
DAC12
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
HPMXSEL5/ /LPMXSEL5/
A11/B10/C0
B5/GPIO20
A15/B9/C7
ADC Inputs
A0 to A15
CTRIP2L
Digital
Filter
ADC-A
12-bits
CMP2_LN
CMP2_LP
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
CTRIPOUT2L
AGPIO
AIO
CMPSS1 Input MUX
Comparator Subsystem 3
REFLO
CMP3_HP
CMP3_HN
CTRIP3H
Digital
Filter
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
A10/B1/C10
A9/B4/C8
A4/B8/C14
A12/C1
VDDA or VDAC
CTRIPOUT3H
HPMXSEL2/
HPMXSEL0/
/LPMXSEL2/
/LPMXSEL0/
DAC12
DAC12
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
REFHI
HPMXSEL5/
HPMXSEL4/
/LPMXSEL5/
/LPMXSEL4/
CTRIP3L
Digital
Filter
ADC Inputs
B0 to B15
CMP3_LN
CMP3_LP
A8/B0/C11
CTRIPOUT3L
ADC-B
12-bits
AIO
CMPSS2 Input MUX
Comparator Subsystem 4
HPMXSEL0/
/LPMXSEL0/
B2/C6
A3/B3/C5/VDAC
A14/B14/C4
CMP4_HP
CMP4_HN
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL5/
HPMXSEL4/
REFLO
CTRIP4H
Digital
Filter
/LPMXSEL5/
/LPMXSEL4/
VDDA or VDAC
CTRIPOUT4H
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A5/B12/C2
DAC12
DAC12
HPMXSEL2/
/LPMXSEL2/
A0/B15/C15/DACA_OUT
CTRIP4L
REFHI
Digital
Filter
AIO
CMP4_LN
CMP4_LP
CMPSS3 Input MUX
ADC Inputs
C0 to C15
CTRIPOUT4L
ADC-C
12-bits
HPMXSEL0/
/LPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL2/
/LPMXSEL2/
HPMXSEL4/
HPMXSEL5/
/LPMXSEL4/
/LPMXSEL5/
REFLO
B11/GPIO21
A7/C3
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
CMPSS Inputs
AGPIO
AIO
CMPSS4 Input MUX
VREFHI
VDAC
12-bit
Buffered
DACA_OUT
DAC-A
VREFHI
VDAC
12-bit
Buffered
DAC-B
DACB_OUT
Figure 6-32. Analog Subsystem Block Diagram (80-Pin PN LQFP)
Copyright © 2021 Texas Instruments Incorporated
128 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
VREFHI
Comparator Subsystem 1
CMP1_HP
CTRIP1H
VREFLO
Digital
CMP1_HN
Filter
VDDA or VDAC
CTRIPOUT1H
Reference Circuit
ANAREFSEL
DAC12
DAC12
Misc. Analog
Temp Sensor
(C12)
CTRIP1L
Digital
Filter
CMP1_LN
CMP1_LP
CTRIPOUT1L
Vref
REFLO
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
HPMXSEL4/
HPMXSEL2/
HPMXSEL0/
/LPMXSEL4/
/LPMXSEL2/
/LPMXSEL0/
A1/B7/DACB_OUT
A6
REFHI
DAC12
DAC12
ADC Inputs
A0 to A15
A2/B6/C9
A11/B10/C0
CTRIP2L
Digital
Filter
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
ADC-A
12-bits
CMP2_LN
CMP2_LP
CTRIPOUT2L
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
A15/B9/C7
AIO
CMPSS1 Input MUX
Comparator Subsystem 3
REFLO
CMP3_HP
CMP3_HN
CTRIP3H
Digital
Filter
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
A10/B1/C10
A9/B4/C8
A4/B8/C14
A12/C1
VDDA or VDAC
CTRIPOUT3H
HPMXSEL2/
HPMXSEL0/
/LPMXSEL2/
/LPMXSEL0/
DAC12
DAC12
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
REFHI
HPMXSEL5/
HPMXSEL4/
/LPMXSEL5/
/LPMXSEL4/
CTRIP3L
Digital
Filter
ADC Inputs
B0 to B15
CMP3_LN
CMP3_LP
A8/B0/C11
CTRIPOUT3L
ADC-B
12-bits
AIO
CMPSS2 Input MUX
Comparator Subsystem 4
HPMXSEL0/
/LPMXSEL0/
B2/C6
A3/B3/C5/VDAC
A14/B14/C4
CMP4_HP
CMP4_HN
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL5/
HPMXSEL4/
REFLO
CTRIP4H
Digital
Filter
/LPMXSEL5/
/LPMXSEL4/
VDDA or VDAC
CTRIPOUT4H
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A5/B12/C2
DAC12
DAC12
HPMXSEL2/
/LPMXSEL2/
A0/B15/C15/DACA_OUT
CTRIP4L
REFHI
Digital
Filter
AIO
CMP4_LN
CMP4_LP
CMPSS3 Input MUX
ADC Inputs
C0 to C15
CTRIPOUT4L
ADC-C
12-bits
HPMXSEL0/
/LPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL2/
HPMXSEL4/
/LPMXSEL2/
/LPMXSEL4/
REFLO
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A7/C3
CMPSS Inputs
AIO
CMPSS4 Input MUX
VREFHI
VDAC
12-bit
Buffered
DACA_OUT
DAC-A
VREFHI
VDAC
12-bit
Buffered
DAC-B
DACB_OUT
Figure 6-33. Analog Subsystem Block Diagram (64-Pin PM LQFP)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 129
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
VREFHI
VREFLO
Comparator Subsystem 1
Digital
CMP1_HP
CMP1_HN
CTRIP1H
Filter
VDDA or VDAC
CTRIPOUT1H
Reference Circuit
ANAREFSEL
DAC12
DAC12
Misc. Analog
CTRIP1L
Digital
Filter
CMP1_LN
CMP1_LP
CTRIPOUT1L
Temp Sensor
(C12)
Vref
REFLO
Comparator Subsystem 2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
HPMXSEL4/
HPMXSEL2/
HPMXSEL0/
/LPMXSEL4/
/LPMXSEL2/
/LPMXSEL0/
A1/B7/DACB_OUT
A6/B2/C6
REFHI
DAC12
DAC12
ADC Inputs
A0 to A15
A2/B6/C9
A11/B10/C0
CTRIP2L
Digital
Filter
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
ADC-A
12-bits
CMP2_LN
CMP2_LP
CTRIPOUT2L
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
A15/B9/C7
AIO
CMPSS1 Input MUX
Comparator Subsystem 3
REFLO
CMP3_HP
CMP3_HN
CTRIP3H
Digital
Filter
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
A10/B1/C10
A9/B4/C8
A4/B8/C14
A12/C1
VDDA or VDAC
CTRIPOUT3H
HPMXSEL2/
HPMXSEL0/
/LPMXSEL2/
/LPMXSEL0/
DAC12
DAC12
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
REFHI
HPMXSEL5/
HPMXSEL4/
/LPMXSEL5/
/LPMXSEL4/
CTRIP3L
Digital
Filter
ADC Inputs
B0 to B15
CMP3_LN
CMP3_LP
A8/B0/C11
CTRIPOUT3L
AIO
ADC-B
12-bits
CMPSS2 Input MUX
Comparator Subsystem 4
HPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL5/ /LPMXSEL5/
/LPMXSEL0/
CMP4_HP
CMP4_HN
A3/B3/C5/VDAC
CTRIP4H
Digital
Filter
REFLO
REFHI
VDDA or VDAC
CTRIPOUT4H
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A5/B12/C2
DAC12
DAC12
HPMXSEL2/
/LPMXSEL2/
A0/B15/C15/DACA_OUT
CTRIP4L
Digital
Filter
AIO
CMP4_LN
CMP4_LP
CMPSS3 Input MUX
ADC Inputs
C0 to C15
CTRIPOUT4L
ADC-C
12-bits
HPMXSEL0/
/LPMXSEL0/
HPMXSEL3/HNMXSEL0/LPMXSEL3/LNMXSEL0
HPMXSEL2/
HPMXSEL4/
/LPMXSEL2/
/LPMXSEL4/
REFLO
HPMXSEL1/HNMXSEL1/LPMXSEL1/LNMXSEL1
A7/C3
CMPSS Inputs
AIO
CMPSS4 Input MUX
VREFHI
VDAC
12-bit
Buffered
DACA_OUT
DAC-A
VREFHI
VDAC
12-bit
Buffered
DAC-B
DACB_OUT
Figure 6-34. Analog Subsystem Block Diagram (48-Pin PT LQFP)
Copyright © 2021 Texas Instruments Incorporated
130 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
CMPSSx Input MUX
CMPxHPMX
CMPx_HP0
0
1
CMPx_HP1
CMPx_HP2
CMPx_HP3
CMPx_HP4
CMPx_HP5
2
3
4
5
CMPx_HP
CMPxHNMX
CMPxLNMX
CMPxLPMX
CMPx_HN0
CMPx_HN1
0
1
CMPx_HN
CMPx_LN
CMPx_LN0
CMPx_LN1
0
1
CMPx_LP0
CMPx_LP1
CMPx_LP2
CMPx_LP3
CMPx_LP4
0
1
2
3
4
5
CMPx_LP
CMPx_LP5
Gx_ADCA
Gx_ADCB
Gx_ADCA
Gx_ADCB
AIO
AIO
AGPIO
Gx_ADCC
Gx_ADCC
AIO
A. AIOs support digital input mode only.
Figure 6-35. Analog Group Connections
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 131
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
AIO Input
SPRSP61 – OCTOBER 2021
6.13.1 Analog Pins and Internal Connections
Table 6-8. Analog Pins and Internal Connections
Package Pin
Pin Name
ADC
Comparator Subsystem (MUX)
High
Positive
High
Negative
Low
Positive
Low
Negative
100 PZ
80 PN
64 PM
48 PT
A
B
C
VREFHI
VREFLO
24, 25
26, 27
20
21
16
17
12
13
A13
B13
C13
Analog Group 1
CMP1
A6
14
17
-
10
6
9
4(1)
6
A6
A2
A15
-
-
B6
-
-
C9
-
CMP1 (HPMXSEL=2)
CMP1 (HPMXSEL=0)
CMP1 (HPMXSEL=3)
CMP1 (LPMXSEL=2)
CMP1 (LPMXSEL=0)
CMP1 (LPMXSEL=3)
AIO228
AIO224
AIO233
A2/B6/C9
A15
13
CMP1 (HNMXSEL=0)
CMP1 (HNMXSEL=1)
CMP1 (LNMXSEL=0)
CMP1 (LNMXSEL=1)
14
10
7
B9/C7
18
20
22
B9
B10
B7
C7
C0
-
A11/B10/C0
A1/B7/DACB_OUT
16
18
12
14
8
A11
A1
CMP1 (HPMXSEL=1)
CMP1 (HPMXSEL=4)
CMP1 (LPMXSEL=1)
CMP1 (LPMXSEL=4)
CMP2
AIO237
AIO232
10
Analog Group 2
A10/B1/C10
40
29
25
21
4(1)
5
A10
B1
C10
CMP2 (HPMXSEL=3)
CMP2 (HNMXSEL=0)
CMP3 (HNMXSEL=0)
CMP2 (LPMXSEL=3)
CMP3
CMP2 (LNMXSEL=0)
CMP3 (LNMXSEL=0)
AIO230
Analog Group 3
B2/C6
15
16
28
-
11
7
-
-
-
B2
C6
-
CMP3 (HPMXSEL=0)
CMP3 (HPMXSEL=3)
CMP3 (LPMXSEL=0)
CMP3 (LPMXSEL=3)
AIO226
AIO242
B3/VDAC(2)
C5
B3
12
8
-
C5
-
-
-
A3
A3
CMP3 (HPMXSEL=5)
CMP3 (LPMXSEL=5)
18
19
-
-
-
-
-
AIO229
AIO239
A14/B14/C4
15
11
A14
A0
B14
C4
CMP3 (HPMXSEL=4)
CMP3 (HPMXSEL=2)
CMP3 (LPMXSEL=4)
CMP3 (LPMXSEL=2)
A0/B15/C15/
DACA_OUT
23
19
15
11
B15
C15
AIO231
Analog Group 4
23 19
CMP4
A7/C3
31
15
A7
-
C3
CMP4 (HPMXSEL=1)
CMP4 (HNMXSEL=1)
CMP4 (LPMXSEL=1)
CMP2/3
CMP4 (LNMXSEL=1)
AIO245
AIO249
AIO244
Combined Analog Group 2/3
35
-
-
-
-
-
-
-
-
A5
A5
-
CMP2 (HPMXSEL=5)
CMP3 (HPMXSEL=1)
CMP2 (LPMXSEL=5)
17
13
9
B12/C2
21
B12
C2
CMP3 (HNMXSEL=1)
CMP2 (HNMXSEL=1)
CMP3 (LPMXSEL=1)
CMP2/4
CMP3 (LNMXSEL=1)
CMP2 (LNMXSEL=1)
Combined Analog Group 2/4
A12
C1
28
29
37
-
A12
-
-
-
-
-
-
C1
-
CMP2 (HPMXSEL=1)
CMP4 (HPMXSEL=2)
CMP2 (LPMXSEL=1)
CMP4 (LPMXSEL=2)
AIO238
AIO248
AIO240
AIO241
22
-
18
-
14
-
A8
A8
CMP4 (HPMXSEL=4)
CMP2 (HPMXSEL=4)
CMP4 (LPMXSEL=4)
CMP2 (LPMXSEL=4)
-
24
-
20
-
16
-
-
-
-
B0/C11
B0
C11
41
AIO253
Copyright © 2021 Texas Instruments Incorporated
132
Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 6-8. Analog Pins and Internal Connections (continued)
Package Pin
80 PN 64 PM
ADC
Comparator Subsystem (MUX)
Pin Name
AIO Input
Low
Negative
High
Positive
High
Low
100 PZ
48 PT
A
B
C
Negative
Positive
A4/B8
C14
36
-
A4
-
B8
-
-
CMP2 (HPMXSEL=0)
CMP2 (LPMXSEL=0)
AIO225
27
23
19
-
C14
CMP4 (HPMXSEL=3)
CMP4 (HNMXSEL=0)
CMP4 (LPMXSEL=3)
CMP4 (LNMXSEL=0)
42
38
39
-
-
-
-
AIO247
AIO227
AIO236
A9
A9
-
-
-
CMP2 (HPMXSEL=2)
CMP4 (HPMXSEL=0)
CMP2 (LPMXSEL=2)
CMP4 (LPMXSEL=0)
28
24
20
B4/C8
B4
C8
Other Analog
B5
32
48
30
49
-
-
33
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AIO252
GPIO20
AIO251
GPIO21
B5
CMP1 (HPMXSEL=5)
CMP4 (HPMXSEL=5)
CMP1 (LPMXSEL=5)
CMP4 (LPMXSEL=5)
B5/GPIO20(3)
B11
-
-
-
B11
-
B11/GPIO21(3)
TempSensor(4)
34
-
C12
(1) A6 and C6 is double bonded as pin # 4.
(2) Optional external reference voltage for on-chip COMPDACs/GPDACs. There is an internal capacitance to VSSA on this pin whether used for ADC input or COMPDAC/GPDAC reference.
If used as a VDAC reference, place at least a 1-µF capacitor on this pin.
(3) The GPIOs on these analog pins support full digital input and output functionality and are referred to as AGPIOs. By default, the AGPIOs are unconnected; that is, the analog and digital
functions are both disabled. For configuration details, see the Digital Inputs and Outputs on ADC Pins (AGPIOs) section.
(4) Internal connection only; does not come to a device pin.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
133
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.13.2 Analog Signal Descriptions
Table 6-9. Analog Signal Descriptions
Signal Name
AIOx
Description
Digital input on ADC pin
GPIOx
Digital input/output pin with ADC functionality
ADC A Input
Ax
Bx
ADC B Input
Cx
ADC C Input
CMPx_DACH
CMPx_DACL
CMPx_HNy
CMPx_HPy
CMPx_LNy
CMPx_LPy
DACx_OUT
TempSensor
Comparator subsystem high DAC output
Comparator subsystem low DAC output
Comparator subsystem high comparator negative input
Comparator subsystem high comparator positive input
Comparator subsystem low comparator negative input
Comparator subsystem low comparator positive input
Buffered DAC Output
Internal temperature sensor
Optional external reference voltage for on-chip COMPDACs. This pin has a higher capacitance compared to the
other analog pins. See the Per-Channel Parasitic Capacitance table for details. This capacitance is present whether
the pin is being used for ADC input or COMPDAC/GPDAC reference and cannot be disabled. If this pin is being
used as a reference for the on-chip COMPDAC/GPDACs, place at least a 1-μF capacitor on this pin.
VDAC
Copyright © 2021 Texas Instruments Incorporated
134 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.3 Analog-to-Digital Converter (ADC)
The ADC module described here is a successive approximation (SAR) style ADC with resolution of 12 bits.
This section refers to the analog circuits of the converter as the “core,” and includes the channel-select MUX,
the sample-and-hold (S/H) circuit, the successive approximation circuits, voltage reference circuits, and other
analog support circuits. The digital circuits of the converter are referred to as the “wrapper” and include logic
for programmable conversions, result registers, interfaces to analog circuits, interfaces to the peripheral buses,
post-processing circuits, and interfaces to other on-chip modules.
Each ADC module consists of a single sample-and-hold (S/H) circuit. The ADC module is designed to be
duplicated multiple times on the same chip, allowing simultaneous sampling or independent operation of multiple
ADCs. The ADC wrapper is start-of-conversion (SOC)-based (see the SOC Principle of Operation section of
the Analog-to-Digital Converter (ADC) chapter in the TMS320F28003x Real-Time Microcontrollers Technical
Reference Manual).
Each ADC has the following features:
•
•
•
•
•
•
•
•
Resolution of 12 bits
Ratiometric external reference set by VREFHI/VREFLO
Selectable internal reference of 2.5 V or 3.3 V
Single-ended signaling
Input multiplexer with up to 16 channels
16 configurable SOCs
16 individually addressable result registers
Multiple trigger sources
– S/W: software immediate start
– All ePWMs: ADCSOC A or B
– GPIO XINT2
– CPU Timers 0/1/2
– ADCINT1/2
•
•
•
Four flexible PIE interrupts
Burst-mode triggering option
Four post-processing blocks, each with:
– Saturating offset calibration
– Error from setpoint calculation
– High, low, and zero-crossing compare, with interrupt and ePWM trip capability
– Trigger-to-sample delay capture
Note
Not every channel may be pinned out from all ADCs. See the Pin Configuration and Functions section
to determine which channels are available.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 135
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
The block diagram for the ADC core and ADC wrapper are shown in Figure 6-36.
Analog-to-Digital Core
Analog-to-Digital Wrapper Logic
Input Circuit
SOCx (0-15)
CHSEL
[15:0]
[15:0]
[15:0]
SOC Arbitration
& Control
ACQPS
CHSEL
ADCIN0
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
ADCIN8
ADCIN9
ADCIN10
ADCIN11
ADCIN12
ADCIN13
ADCIN14
ADCIN15
0
1
ADCSOC
2
3
.
.
.
.
.
.
4
5
ADCCOUNTER
TRIGGER[15:0]
6
VIN
+
DOUT
7
8
VIN-
9
10
11
12
13
14
15
SOC Delay
Timestamp
Trigger
Timestamp
Converter
S/H Circuit
RESULT
-
+
ADCPPBxOFFCAL
ꢀ
saturate
+
ADCPPBxOFFREF
-
ADCPPBxRESULT
ADCEVT
ꢀ
VREFHI
Event
Logic
CONFIG
ADCEVTINT
Bandgap
Reference Circuit
1.65-V Output
(3.3-V Range)
or
1
Post Processing Block (1-4)
Interrupt Block (1-4)
0
2.5-V Output
(2.5-V Range)
ADCINT1-4
VREFLO
Analog System Control
ANAREFSEL
ANAREFx2PSSEL
Reference Voltage Levels
Figure 6-36. ADC Module Block Diagram
Copyright © 2021 Texas Instruments Incorporated
136 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.3.1 ADC Configurability
Some ADC configurations are individually controlled by the SOCs, while others are globally controlled per ADC
module. Table 6-10 summarizes the basic ADC options and their level of configurability.
Table 6-10. ADC Options and Configuration Levels
OPTIONS
CONFIGURABILITY
Clock
Per module(1)
Resolution
Signal mode
Not configurable (12-bit resolution only)
Not configurable (single-ended signal mode only)
Reference voltage source
Trigger source
Either external or internal for all modules
Per SOC(1)
Converted channel
Acquisition window duration
EOC location
Per SOC
Per SOC(1)
Per module
Per module(1)
Burst mode
(1) Writing these values differently to different ADC modules could cause the ADCs to operate
asynchronously. For guidance on when the ADCs are operating synchronously or asynchronously,
see the Ensuring Synchronous Operation section of the Analog-to-Digital Converter (ADC) chapter
in the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual.
6.13.3.1.1 Signal Mode
The ADC supports single-ended signaling. The input voltage to the converter is sampled through a single pin
(ADCINx), referenced to VREFLO.
Pin Voltage
VREFHI
VREFHI
ADCINx
ADCINx
ADC
VREFHI/2
VREFLO
VREFLO
(VSSA)
Digital Output
2n - 1
ADC Vin
0
Figure 6-37. Single-ended Signaling Mode
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 137
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.13.3.2 ADC Electrical Data and Timing
Note
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this
level, the VREF internal to the device may be disturbed, which can impact results for other ADC inputs
using the same VREF
.
Note
The VREFHI pin must be kept below VDDA + 0.3 V to ensure proper functional operation. If the
VREFHI pin exceeds this level, a blocking circuit may activate, and the internal value of VREFHI may
float to 0 V internally, giving improper ADC conversion.
6.13.3.2.1 ADC Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
ADCCLK (derived from PERx.SYSCLK)
5
MHz
120-MHz SYSCLK
4
MSPS
Sample rate
120-MHz SYSCLK (AGPIO Pin)
With 50 Ω or less Rs
3.75
MSPS
75
90
ns
ns
V
Sample window duration (set by ACQPS and
PERx.SYSCLK)(1)
With 50 Ω or less Rs (AGPIO Pin)
External Reference
VREFHI
2.4
2.5 or 3.0
1.65
VDDA
Internal Reference = 3.3V Range
Internal Reference = 2.5V Range
V
VREFHI(2)
2.5
V
VREFLO
VSSA
VSSA
VDDA
3.3
V
VREFHI - VREFLO
2.4
V
Internal Reference = 3.3 V Range
Internal Reference = 2.5 V Range
External Reference
0
0
V
Conversion range
2.5
V
VREFLO
VREFHI
V
(1) The sample window must also be at least as long as 1 ADCCLK cycle for correct ADC operation.
(2) In internal reference mode, the reference voltage is driven out of the VREFHI pin by the device. The user should not drive a voltage
into the pin in this mode.
Copyright © 2021 Texas Instruments Incorporated
138 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.3.2.2 ADC Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General
ADCCLK Conversion Cycles
Power Up Time
120-MHz SYSCLK
10.1
11 ADCCLKs
External Reference mode
Internal Reference mode
500
µs
µs
5000
5000
Internal Reference mode, when switching between
2.5-V range and 3.3-V range.
µs
µA
µF
VREFHI input current(1)
130
Internal Reference Capacitor
Value(2)
2.2
2.2
External Reference Capacitor
Value(2)
µF
DC Characteristics
Internal reference
External reference
–45
–5
45
5
Gain Error
LSB
±3
±2
2
Offset Error
–5
5
LSB
LSB
Channel-to-Channel Gain Error(4)
Channel-to-Channel Offset
Error(4)
2
LSB
ADC-to-ADC Gain Error(5)
ADC-to-ADC Offset Error(5)
DNL Error
Identical VREFHI and VREFLO for all ADCs
Identical VREFHI and VREFLO for all ADCs
4
2
LSB
LSB
LSB
LSB
LSBs
>–1
–2
±0.5
±1.0
1
2
1
INL Error
ADC-to-ADC Isolation
AC Characteristics
VREFHI = 2.5 V, synchronous ADCs
–1
External VREFHI/Internal VREFHI = 2.5 V, fin =
100 kHz, SYSCLK from X1
70.5
68.2
dB
dB
dB
Internal VREFHI = 1.65 V (0 to 3.3 V range), fin =
100 kHz, SYSCLK from X1
SNR(3)
External/Internal VREFHI, fin = 100 kHz, SYSCLK
from INTOSC
60.1
External VREFHI/Internal VREFHI = 2.5 V, fin =
100 kHz, SYSCLK from X1
–85.0
THD(3)
Internal VREFHI = 1.65 V (0 to 3.3 V range), fin =
100 kHz, SYSCLK from X1
–82.3
79.2
70.4
dB
dB
dB
SFDR(3)
External/Internal VREFHI , fin = 100 kHz
External VREFHI/Internal VREFHI = 2.5V, fin = 100
kHz, SYSCLK from X1
Internal VREFHI = 1.65 V (0 to 3.3 V range), fin =
100 kHz, SYSCLK from X1
SINAD(3)
68.0
60.0
dB
External/Internal VREFHI, fin = 100 kHz, SYSCLK
from INTOSC
External VREFHI/Internal VREFHI = 2.5 V, fin
= 100 kHz, SYSCLK from X1, single and
synchronous ADCs
11.4
11.0
Internal VREFHI = 1.65 V (0 to 3.3 V range),
fin = 100 kHz, SYSCLK from X1, single and
synchronous ADCs
ENOB(3)
bits
Any VREF mode, fin = 100 kHz, SYSCLK from X1,
asynchronous ADCs
Not
Supported
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 139
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
UNIT
SPRSP61 – OCTOBER 2021
6.13.3.2.2 ADC Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VDD = 1.2-V DC + 100mV
DC up to Sine at 1 kHz
60
VDD = 1.2-V DC + 100 mV
DC up to Sine at 300 kHz
57
60
57
PSRR
dB
VDDA = 3.3-V DC + 200 mV
DC up to Sine at 1 kHz
VDDA = 3.3-V DC + 200 mV
Sine at 900 kHz
(1) Load current on VREFHI increases when ADC input is greater than VDDA. This causes inaccurate conversions.
(2) A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable.
(3) IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and
crosstalk.
(4) Variation across all channels belonging to the same ADC module.
(5) Worst case variation compared to other ADC modules.
6.13.3.2.3 ADC Input Model
The ADC input characteristics are given by Table 6-11 and Figure 6-38.
Table 6-11. Input Model Parameters
DESCRIPTION
REFERENCE MODE
VALUE
Cp
Parasitic input capacitance
All
See Table 6-12 to Table 6-15
External Reference, 2.5-V Internal
Reference
500 Ω
860 Ω
Ron
Sampling switch resistance
3.3-V Internal Reference
External Reference, 2.5-V Internal
Reference
12.5 pF
Ch
Rs
Sampling capacitor
3.3-V Internal Reference
All
7.5 pF
50 Ω
Nominal source impedance
ADC
ADCINx
Rs
Switch
Ron
AC
Cp
Ch
VREFLO
Figure 6-38. Input Model
This input model should be used with actual signal source impedance to determine the acquisition window
duration. For more information, see the Choosing an Acquisition Window Duration section of the Analog-
to-Digital Converter (ADC) chapter in the TMS320F28003x Real-Time Microcontrollers Technical Reference
Manual.
Table 6-12. Per-Channel Parasitic Capacitance for 100-Pin PZ LQFP
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
A0/B15/C15/DACA_OUT
9.1
7.4
4.1
3.3
3.8
11.6
9.9
6.6
5.8
6.3
A1/B7/DACB_OUT
A2/B6/C9
A3
A4/B8
Copyright © 2021 Texas Instruments Incorporated
140 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 6-12. Per-Channel Parasitic Capacitance for 100-Pin PZ LQFP
(continued)
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
A5
A6
3.5
3.2
3.8
4.1
3.1
4.7
4
6
5.7
6.3
6.6
5.6
7.2
6.5
5.9
6.3
6.6
6.4
77.5
6.3
6
A7/C3
A8
A9
A10/B1/C10
A11/B11/C0
A12
3.4
3.8
4.1
3.9
75
A14/B14/C4
B0/C11
B2/C6
B3/VDAC
B4/C8
B5
3.8
3.5
3.3
3
B9/C7
B11
5.8
5.5
6.1
5.5
6.1
6.7
5.7
5.6
B12/C2
C1
3.6
3
C5
3.6
4.2
3.2
3.1
C14
AGPIO_B5
AGPIO_B11
Table 6-13. Per-Channel Parasitic Capacitance for 80-Pin PN LQFP
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
A0/B15/C15/DACA_OUT
A1/B7/DACB_OUT
A2/B6/C9
9.1
7.4
4.1
81.9
8
11.6
9.9
6.6
A3/B3/C5/VDAC
A4/B8/C14
A5/B12/C2
A6
89.4
13
7.1
3.2
3.8
8.2
6.9
4.7
4
12.1
5.7
A7/C3
6.3
A8/B0/C11
A9/B4/C8
13.2
11.9
7.2
A10/B1/C10
A11/B11/C0
A12/C1
6.5
6.4
3.8
7.1
3.9
3.2
11.4
6.3
A14/B14/C4
A15/B9/C7
B2/C6
12.1
6.4
AGPIO_B5
5.7
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 141
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 6-13. Per-Channel Parasitic Capacitance for 80-Pin PN LQFP (continued)
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
AGPIO_B11
3.1
5.6
Table 6-14. Per-Channel Parasitic Capacitance for 64-Pin PM LQFP
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
A0/B15/C15/DACA_OUT
A1/B7/DACB_OUT
A2/B6/C9
9.1
7.4
4.1
81.9
8
11.6
9.9
6.6
A3/B3/C5/VDAC
A4/B8/C14
A5/B12/C2
A6
89.4
13
7.1
3.2
3.8
8.2
6.9
4.7
4
12.1
5.7
A7/C3
6.3
A8/B0/C11
A9/B4/C8
13.2
11.9
7.2
A10/B1/C10
A11/B11/C0
A12/C1
6.5
6.4
3.8
7.1
3.9
11.4
6.3
A14/B14/C4
A15/B9/C7
B2/C6
12.1
6.4
Table 6-15. Per-Channel Parasitic Capacitance for 48-Pin PT LQFP
Cp (pF)
ADC CHANNEL
COMPARATOR DISABLED
COMPARATOR ENABLED
A0/B15/C15/DACA_OUT
A1/B7/DACB_OUT
A2/B6/C9
9.1
7.4
4.1
81.9
8
11.6
9.9
6.6
A3/B3/C5/VDAC
A4/B8/C14
89.4
13
A5/B12/C2
7.1
7.1
3.8
8.2
6.9
4.7
4
12.1
12.1
6.3
A6/B2/C6
A7/C3
A8/B0/C11
13.2
11.9
7.2
A9/B4/C8
A10/B1/C10
A11/B11/C0
A12/C1
6.5
6.4
7.1
11.4
12.1
A15/B9/C7
Copyright © 2021 Texas Instruments Incorporated
142 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.3.2.4 ADC Timing Diagrams
Figure 6-39 shows the ADC conversion timings for two SOCs given the following assumptions:
•
•
•
•
SOC0 and SOC1 are configured to use the same trigger.
No other SOCs are converting or pending when the trigger occurs.
The round-robin pointer is in a state that causes SOC0 to convert first.
ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag
propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
Table 6-16 lists the descriptions of the ADC timing parameters. Table 6-17 lists the ADC timings.
Sample n
Input on SOC0.CHSEL
Input on SOC1.CHSEL
Sample n+1
ADC S+H
SOC0
SOC1
SYSCLK
ADCCLK
ADCTRIG
ADCSOCFLG.SOC0
ADCSOCFLG.SOC1
ADCRESULT0
Sample n
(old data)
(old data)
ADCRESULT1
Sample n+1
ADCINTFLG.ADCINTx
tSH
tLAT
tEOC
tINT
Figure 6-39. ADC Timings
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 143
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 6-16. ADC Timing Parameters
PARAMETER
DESCRIPTION
The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital
value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each
SOC, so tSH will not necessarily be the same for different SOCs.
tSH
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window
regardless of device clock settings.
The time from the end of the S+H window until the ADC results latch in the ADCRESULTx register.
tLAT
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
The time from the end of the S+H window until the S+H window for the next ADC conversion can begin. The
subsequent sample can start before the conversion results are latched.
tEOC
The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being
latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the
ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be
taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).
tINT
If the INTPULSEPOS bit is 0, and the OFFSET field in the ADCINTCYCLE register is not 0, then there will be
a delay of OFFSET SYSCLK cycles before the ADCINT flag is set. This delay can be used to enter the ISR or
trigger the DMA at exactly the time the sample is ready.
Table 6-17. ADC Timings
ADCCLK
CYCLES
ADCCLK PRESCALE
SYSCLK CYCLES
ADCCTL2
[PRESCALE]
RATIO
ADCCLK:SYSCLK
(1)
(2)
tEOC
tLAT
tINT(EARLY)
tINT(LATE)
tEOC
0
2
1
2
3
4
5
6
7
8
11
21
31
41
51
61
71
81
13
1
1
1
1
1
1
1
1
11
21
31
41
51
61
71
81
11
23
34
44
55
65
76
86
10.5
10.3
10.3
10.2
10.2
10.1
10.1
4
6
8
10
12
14
(1) Refer to the "ADC: DMA Read of Stale Result" advisory in the TMS320F28003x Real-Time MCUs Silicon Errata.
(2) By default, tINT occurs one SYSCLK cycle after the S+H window if INTPULSEPOS is 0. This can be changed by writing to the OFFSET
field in the ADCINTCYCLE register.
Copyright © 2021 Texas Instruments Incorporated
144 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.4 Temperature Sensor
6.13.4.1 Temperature Sensor Electrical Data and Timing
The temperature sensor can be used to measure the device junction temperature. The temperature sensor
is sampled through an internal connection to the ADC and translated into a temperature through TI-provided
software. When sampling the temperature sensor, the ADC must meet the acquisition time in the Temperature
Sensor Characteristics table.
6.13.4.1.1 Temperature Sensor Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Tacc
tstartup
tacq
Temperature Accuracy
External reference
±15
°C
Start-up time
(TSNSCTL[ENABLE] to
sampling temperature sensor)
500
µs
ns
ADC acquisition time
450
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 145
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.13.5 Comparator Subsystem (CMPSS)
The Comparator Subsystem (CMPSS) consists of analog comparators and supporting circuits that are useful for
power applications such as peak current mode control, switched-mode power, power factor correction, voltage
trip monitoring, and so forth.
The comparator subsystem is built around a number of modules. Each subsystem contains two comparators,
two reference 12-bit DACs, and two digital filters. The subsystem also includes one ramp generator.
Comparators are denoted "H" or "L" within each module where “H” and “L” represent high and low, respectively.
Each comparator generates a digital output which indicates whether the voltage on the positive input is greater
than the voltage on the negative input. The positive input of the comparator is driven from an external pin
(see the Analog Subsystem chapter of the TMS320F28003x Real-Time Microcontrollers Technical Reference
Manual for mux options available to the CMPSS. The negative input can be driven by an external pin or by
the programmable reference 12-bit DAC. Each comparator output passes through a programmable digital filter
that can remove spurious trip signals. An unfiltered output is also available if filtering is not required. A ramp
generator circuit is optionally available to control the reference 12-bit DAC value for the high comparator in the
subsystem.
Each CMPSS includes:
•
•
•
•
•
•
•
•
•
•
•
Two analog comparators
Two programmable reference 12-bit DACs
One ramp generator
Ability to synchronize submodules with EPWMSYNCPER
Ability to extend clear signal with EPWMBLANK
Ability to synchronize output with SYSCLK
Ability to latch output
Ability to invert output
Option to use hysteresis on the input
Option for negative input of comparator to be driven by an external signal or by the reference DAC
Option to choose between VDDA or VDAC to be the DAC reference voltage
Copyright © 2021 Texas Instruments Incorporated
146 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.5.1 CMPSS Connectivity Diagram
Comparator Subsystem1
CMP1_HP
CTRIP1H
CTRIP1L
CTRIP2H
CTRIP2L
CTRIP1H
Digital
CMP1_HN
Filter
VDDA or VDAC
CTRIPOUT1H
DAC12
DAC12
Digital
Filter
CTRIP1L
CTRIPOUT1L
CMP1_LN
CMP1_LP
ePWM X- BAR
ePWMs
Comparator Subsystem2
CMP2_HP
CMP2_HN
CTRIP2H
Digital
Filter
VDDA or VDAC
CTRIPOUT2H
DAC12
DAC12
CTRIP4H
CTRIP4L
Digital
Filter
CTRIP2L
CMP2_LN
CMP2_LP
CTRIPOUT2L
CTRIPOUT1H
CTRIPOUT1L
CTRIPOUT2H
CTRIPOUT2L
Comparator Subsystem4
CMP4_HP
CMP4_HN
CTRIP4H
Digital
Filter
VDDA or VDAC
CTRIPOUT4H
Output X- BAR
GPIO Mux
DAC12
DAC12
Digital
Filter
CTRIP4L
CTRIPOUT4L
CMP4_LN
CMP4_LP
CTRIPOUT4H
CTRIPOUT4L
Figure 6-40. CMPSS Connectivity
6.13.5.2 Block Diagram
The block diagram for the CMPSS is shown in Figure 6-41.
•
CTRIPx(x= "H" or "L") signals are connected to the ePWM X-BAR for ePWM trip response. See the
Enhanced Pulse Width Modulator (ePWM) chapter of the TMS320F28003x Real-Time Microcontrollers
Technical Reference Manual for more details on the ePWM X-BAR mux configuration.
•
CTRIPxOUTx(x= "H" or "L") signals are connected to the Output X-BAR for external signaling. See the
General-Purpose Input/Output (GPIO) chapter of the TMS320F28003x Real-Time Microcontrollers Technical
Reference Manual for more details on the Output X-BAR mux configuration.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 147
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Figure 6-41. CMPSS Module Block Diagram
Copyright © 2021 Texas Instruments Incorporated
148 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.5.3 CMPSS Electrical Data and Timing
6.13.5.3.1 Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
500
UNIT
µs
TPU
Power-up time
Comparator input (CMPINxx) range
Input referred offset error
0
VDDA
V
Low common mode, inverting
input set to 50mV
–20
20
mV
1x
12
24
36
48
21
26
30
46
2x
Hysteresis(1)
LSB
3x
4x
Step response
60
Response time (delay from CMPINx input pin
change to GPIO output pin through either ePWM
X-BAR or Output X-BAR)
ns
Ramp response (1.65V/µs)
Ramp response (8.25mV/µs)
Up to 250 kHz
ns
dB
dB
PSRR
CMRR
Power Supply Rejection Ratio
Common Mode Rejection Ratio
40
(1) The CMPSS DAC is used as the reference to determine how much hysteresis to apply. Therefore, hysteresis will scale with the
CMPSS DAC reference voltage. Hysteresis is available for all comparator input source configurations.
CMPSS Comparator Input Referred Offset and Hysteresis
Note
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a
CMPSS input exceeds this level, an internal blocking circuit isolates the internal comparator from
the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the
internal comparator input is floating and can decay below VDDA within approximately 0.5 µs. After
this time, the comparator could begin to output an incorrect result depending on the value of the other
comparator input.
Input Referred Offset
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 6-42. CMPSS Comparator Input Referred Offset
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 149
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Hysteresis
CTRIPx
Logic Level
CTRIPx = 1
CTRIPx = 0
COMPINxP
Voltage
0
CMPINxN or
DACxVAL
Figure 6-43. CMPSS Comparator Hysteresis
6.13.5.3.2 CMPSS DAC Static Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
0
TYP
MAX
UNIT
Internal reference
VDDA
CMPSS DAC output range
V
External reference
0
VDAC(4)
Static offset error(1)
Static gain error(1)
Static DNL
–25
–2
25
2
mV
% of FSR
LSB
Endpoint corrected
>–1
–16
4
Static INL
Endpoint corrected
16
1
LSB
Settling time
Resolution
Settling to 1LSB after full-scale output change
µs
12
bits
Error induced by comparator trip or CMPSS
DAC code change within the same CMPSS
module
CMPSS DAC output disturbance(2)
–100
100
LSB
CMPSS DAC disturbance time(2)
VDAC reference voltage
VDAC load(3)
200
VDDA
10
ns
V
When VDAC is reference
When VDAC is reference
2.4
6
2.5 or 3.0
8
kΩ
(1) Includes comparator input referred errors.
(2) Disturbance error may be present on the CMPSS DAC output for a certain amount of time after a comparator trip.
(3) Per active CMPSS module.
(4) The maximum output voltage is VDDA when VDAC > VDDA.
Copyright © 2021 Texas Instruments Incorporated
150 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.5.3.3 CMPSS Illustrative Graphs
Offset Error
Figure 6-44. CMPSS DAC Static Offset
Ideal Gain
Actual Gain
Figure 6-45. CMPSS DAC Static Gain
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 151
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Linearity Error
Figure 6-46. CMPSS DAC Static Linearity
Copyright © 2021 Texas Instruments Incorporated
152 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.6 Buffered Digital-to-Analog Converter (DAC)
The buffered DAC module consists of an internal 12-bit DAC and an analog output buffer that can drive an
external load. For driving even higher loads than typical, a trade-off can be made between load size and
output voltage swing. For the load conditions of the buffered DAC, see the Buffered DAC Electrical Data and
Timing section. The buffered DAC is a general-purpose DAC that can be used to generate a DC voltage or AC
waveforms such as sine waves, square waves, triangle waves and so forth. Software writes to the DAC value
register can take effect immediately or can be synchronized with EPWMSYNCO events.
Each buffered DAC has the following features:
•
•
•
•
12-bit resolution
Selectable reference voltage source
x1 and x2 gain modes when using internal VREFHI
Ability to synchronize with EPWMSYNCPER
DACCTL[DACREFSEL]
ANAREFx2P5
VDAC
0
DACREF
1.65 V
0
1
Internal Reference
Circuit
1
2.5 V
0
1
VREFHI
ANAREFxSEL
VDDA
DACCTL[LOADMODE]
>
D
D
SYSCLK
DACVALS
Q
Q
0
DACOUT
12-bit
DAC
Amp
(x1 or x2)
DACVALA
1
EPWM1SYNCPER
EPWM2SYNCPER
0
1
EN
VSSA
VSSA
EPWM3SYNCPER
...
2
...
DACCTL[MODE]
(Select x1 or x2 gain)
EPWMnSYNCPER
n-1
DACCTL[SYNCSEL]
Figure 6-47. DAC Module Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 153
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.13.6.1 Buffered DAC Electrical Data and Timing
6.13.6.1.1 Buffered DAC Operating Conditions
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kΩ
pF
V
RL
CL
Resistive Load(2)
5
Capacitive Load
100
VDDA – 0.3
VDDA – 0.6
VDDA
RL = 5 kΩ
0.3
0.6
2.4
VOUT
Valid Output Voltage Range(3)
RL = 1 kΩ
V
Reference Voltage(4)
VDAC or VREFHI
2.5 or 3.0
V
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) DAC can drive a minimum resistive load of 1 kΩ, but the output range will be limited.
(3) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(4) For best PSRR performance, VDAC or VREFHI should be less than VDDA.
6.13.6.1.2 Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
12
MAX
UNIT
General
Resolution
bits
mV/V
V-ns
Load Regulation
Glitch Energy
–1
1
1.5
Settling to 2 LSBs after 0.3V-
to-3V transition
Voltage Output Settling Time Full-Scale
Voltage Output Settling Time 1/4th Full-Scale
Voltage Output Slew Rate
2
1.6
4.5
µs
µs
Settling to 2 LSBs after 0.3V-
to-0.75V transition
Slew rate from 0.3V-to-3V
transition
2.8
V/µs
5-kΩ Load
328
557
ns
ns
kΩ
µs
µs
Load Transient Settling Time
Reference Input Resistance(2)
1-kΩ Load
VDAC or VREFHI
External Reference mode
Internal Reference mode
160
200
240
500
TPU
Power Up Time
5000
DC Characteristics
Offset
Gain
DNL
INL
Offset Error
Midpoint
–10
–2.5
–1
10
2.5
1
mV
% of FSR
LSB
Gain Error(3)
Differential Non Linearity(4)
Endpoint corrected
Endpoint corrected
±0.4
±2
Integral Non Linearity
–5
5
LSB
AC Characteristics
Integrated noise from 100 Hz
to 100 kHz
600
µVrms
Output Noise
Noise density at 10 kHz
1 kHz, 200 KSPS
800
64
nVrms/√Hz
SNR
THD
Signal to Noise Ratio
dB
dB
Total Harmonic Distortion
1 kHz, 200 KSPS
–64.2
Spurious Free Dynamic
Range
SFDR
1 kHz, 200 KSPS
1 kHz, 200 KSPS
66
dB
dB
Signal to Noise and Distortion
Ratio
SINAD
61.7
Copyright © 2021 Texas Instruments Incorporated
154 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.13.6.1.2 Buffered DAC Electrical Characteristics (continued)
over recommended operating conditions (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
70
MAX
UNIT
dB
DC
100 kHz
Power Supply Rejection
Ratio(5)
PSRR
30
dB
(1) Typical values are measured with VREFHI = 3.3 V and VREFLO = 0 V, unless otherwise noted. Minimum and maximum values are
tested or characterized with VREFHI = 2.5 V and VREFLO = 0 V.
(2) Per active Buffered DAC module.
(3) Gain error is calculated for linear output range.
(4) The DAC output is monotonic.
(5) VREFHI = 3.2 V, VDDA = 3.3 V DC + 100 mV Sine.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 155
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.14 Control Peripherals
6.14.1 Enhanced Pulse Width Modulator (ePWM)
The ePWM peripheral is a key element in controlling many of the power electronic systems found in both
commercial and industrial equipment. The ePWM type-4 module is able to generate complex pulse width
waveforms with minimal CPU overhead by building the peripheral up from smaller modules with separate
resources that can operate together to form a system. Some of the highlights of the ePWM type-4 module
include complex waveform generation, dead-band generation, a flexible synchronization scheme, advanced
trip-zone functionality, and global register reload capabilities.
The ePWM and eCAP synchronization scheme on the device provides flexibility in partitioning the ePWM and
eCAP modules and allows localized synchronization within the modules.
Figure 6-48 shows the ePWM module. Figure 6-49 shows the ePWM trip input connectivity.
Copyright © 2021 Texas Instruments Incorporated
156 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Time-Base (TB)
TBPRD Shadow (24)
ePWM
SYNC
Scheme
EXTSYNCIN
EXTSYNCOUT
TBPRDHR (8)
TBPRD Active (24)
CTR=PRD
EPWMxSYNCI
TBCTL[PHSEN]
TBCTL[SWFSYNC]
DCAEVT1/sync(A)
DCBEVT1/sync(A)
Counter
Up/Down
(16 bit)
CTR=ZERO
CTR_Dir
TBCTR
Active (16)
CTR=PRD
EPWMx_INT
CTR=ZERO
TBPHSHR (8)
EPWMxSOCA
EPWMxSOCB
CTR=PRD or ZERO
CTR=CMPA
16
8
On-chip
ADC
Event
Trigger
And
Interrupt
(ET)
Phase
TBPHS Active (24)
CTR=CMPB
Control
CTR=CMPC
CTR=CMPD
CTR_Dir
DCAEVT1.soc(A)
DCBEVT1.soc(A)
ADCSOCOUTSELECT
Counter Compare (CC)
Action
Qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
Select and pulse stretch
for external ADC
16
HiRes PWM (HRPWM)
CMPAHR (8)
EPWMA
ADCSOCAO
ADCSOCBO
CMPA Active (24)
CMPA Shadow (24)
ePWMxA
Trip
Zone
(TZ)
Dead
Band
(DB)
PWM
Chopper
(DB)
CTR=CMPB
CMPBHR (8)
16
CMPB Active (16)
EPWMB
ePWMxB
CMPB Shadow (16)
CMPBHR (8)
CTR=CMPC
EPWMx_TZ_INT
TZ1 to TZ3
TBCNT (16)
CMPC[15-0]
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
DCAEVT2.inter
EMUSTOP
16
CLOCKFAIL
CMPC Active (16)
EQEPxERR
DCBEVT2.inter
DCAEVT1.force(A)
DCBEVT1.force(A)
DCAEVT2.force(A)
CMPC Shadow (16)
TBCNT (16)
CTR=CMPD
DCBEVT2.force(A)
CMPD[15-0]
16
CMPD Active (16)
CMPD Shadow (16)
A. These events are generated by the ePWM digital compare (DC) submodule based on the levels of the TRIPIN inputs.
Figure 6-48. ePWM Submodules and Critical Internal Signal Interconnects
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 157
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Figure 6-49. ePWM Trip Input Connectivity
Copyright © 2021 Texas Instruments Incorporated
158 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.14.1.1 ePWM Electrical Data and Timing
For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.14.1.1.1 ePWM Timing Requirements
MIN
2tc(EPWMCLK)
MAX
UNIT
Asynchronous
Synchronous
tw(SYNCIN)
Sync input pulse width
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
6.14.1.1.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SYSCLK)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
Delay time, trip input active to PWM Hi-Z
td(TZ-PWM)
25
ns
(1) 20-pF load on pin.
6.14.1.1.3 Trip-Zone Input Timing
For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.14.1.1.3.1 Trip-Zone Input Timing Requirements
MIN
1tc(EPWMCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(EPWMCLK)
cycles
With input qualifier
1tc(EPWMCLK) + tw(IQSW)
cycles
6.14.1.1.3.2 PWM Hi-Z Characteristics Timing Diagram
EPWMCLK
tw(TZ)
TZ(A)
td(TZ-PWM)
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TRIP1–TRIP12
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.
Figure 6-50. PWM Hi-Z Characteristics
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 159
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.14.2 High-Resolution Pulse Width Modulator (HRPWM)
The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module, there are two HR outputs:
•
•
HR Duty and Deadband control on Channel A
HR Duty and Deadband control on Channel B
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A, B,
phase, period and deadband registers of the ePWM module.
6.14.2.1 HRPWM Electrical Data and Timing
6.14.2.1.1 High-Resolution PWM Characteristics
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO functions in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLK period dynamically while the HRPWM is in operation.
6.14.3 External ADC Start-of-Conversion Electrical Data and Timing
6.14.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(SYSCLK)
cycles
6.14.3.2 ADCSOCAO or ADCSOCBO Timing Diagram
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 6-51. ADCSOCAO or ADCSOCBO Timing
Copyright © 2021 Texas Instruments Incorporated
160 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.14.4 Enhanced Capture (eCAP)
The eCAP module can be used in systems where accurate timing of external events is important. eCAP/HRCAP
on this device is Type-2.
Applications for eCAP include:
•
•
•
•
Speed measurements of rotating machinery (for example, toothed sprockets sensed through Hall sensors)
Elapsed time measurements between position sensor pulses
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
4-event time-stamp registers (each 32 bits)
Edge-polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event timestamps
Continuous mode capture of timestamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All of the above resources dedicated to a single input pin
When not used in capture mode, the eCAP module can be configured as a single-channel PWM output
(APWM).
The capture functionality of the Type-1 eCAP is enhanced from the Type-0 eCAP with the following added
features:
•
Event filter reset bit
– Writing a 1 to ECCTL2[CTRFILTRESET] will clear the event filter, the modulo counter, and any pending
interrupts flags. Resetting the bit is useful for initialization and debug.
Modulo counter status bits
•
– The modulo counter (ECCTL2 [MODCTRSTS]) indicates which capture register will be loaded next. In the
Type-0 eCAP, it was not possible to know current state of modulo counter.
DMA trigger source
– eCAPxDMA is added as a DMA trigger. CEVT[1–4] can be configured as the source for eCAPxDMA.
Input multiplexer
•
•
•
– ECCTL0 [INPUTSEL] selects one of 128 input signals.
EALLOW protection
– EALLOW protection is added to critical registers. To maintain software compatibility with the Type-0 eCAP,
configure DEV_CFG_REGS.ECAPTYPE to make these registers unprotected.
The capture functionality of the Type-2 eCAP is enhanced from the Type-1 eCAP with the following added
features:
•
ECAPxSYNCINSEL register
– The ECAPSxYNCINSEL register is added for each eCAP to select an external SYNCIN. Every eCAP can
have a separate SYNCIN signal.
The eCAP inputs connect to any GPIO input through the Input X-BAR. The APWM outputs connect to GPIO pins
through the Output X-BAR to OUTPUTx positions in the GPIO mux. See the GPIO Input X-BAR section and the
GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR section.
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP3) in the PCLKCR3 register turn off the eCAP module individually (for
low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 161
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.14.4.1 eCAP and HRCAP Block Diagram
ECCTL2 [ SYNCI_EN, SYNCOSEL, SWSYNC]
ECCTL2[CAP/APWM]
APWM Mode
CTRPHS
(phase register−32 bit)
ECAPxSYNCIN
OVF
RST
CTR_OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
ECAPxSYNCOUT
PWM
Compare
Logic
Output
X-Bar
(counter−32 bit)
Delta−Mode
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
ECCTL1 [ CAPLDEN, CTRRSTx]
HRCTRL[HRE]
32
32
LD1
CAP1
Polarity
Select
LD
(APRD Active)
APRD
32
shadow
CMP [0−31]
32
HRCTRL[HRE]
32
HRCTRL[HRE]
32
CAP2
Polarity
Select
LD2
LD
Other
Sources
(ACMP Active)
[127:16]
[15:0]
Event
Prescale
Event
32
ACMP
16
qualifier
Input
shadow
ECCTL1[PRESCALE]
HRCTRL[HRE]
32
X-Bar
32
Polarity
Select
LD3
LD4
CAP3
LD
(APRD Shadow)
HRCTRL[HRE]
32
32
CAP4
Polarity
Select
LD
(ACMP Shadow)
Edge Polarity Select
ECCTL1[CAPxPOL]
4
Capture Events
4
CEVT[1:4]
ECAPxDMA_INT
ECCTL2[CTRFILTRESET]
Interrupt
Trigger
and
Continuous /
Oneshot
MODCNTRSTS
CTR_OVF
CTR=PRD
CTR=CMP
Capture Control
ECCTL2[DMAEVTSEL]
Flag
Control
ECAPx
(to ePIE)
ECCTL2 [ REARM, CONT_ONESHT, STOP_WRAP]
Registers: ECEINT, ECFLG, ECCLR, ECFRC
Capture Pulse
HR Input
SYSCLK
HRCLK
(A)
HR Submodule
ECAPx_HRCAL
(to ePIE)
A. The HRCAP submodule is not available on all eCAP modules; in this case, the high-resolution muxes and hardware are not
implemented.
Figure 6-52. eCAP and HRCAP Block Diagram
Copyright © 2021 Texas Instruments Incorporated
162 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.14.4.2 eCAP Synchronization
The eCAP modules can be synchronized with each other by selecting a common SYNCIN source. SYNCIN
source for eCAP can be either software sync-in or external sync-in. The external sync-in signal can come from
EPWM, eCAP, or X-Bar. The SYNC signal is defined by the selection in the ECAPxSYNCINSEL[SEL] bit for
ECAPx as shown in Figure 6-53.
ECAPx
Disable
0x0
0x1
ECAPxSYNCIN
EPWMxSYNCOUT
ECAPxSYNCIN
Signals
ECCTL2[SWSYNC]
CTR=PRD
Disable
EXTSYNCOUT
ECAPxSYNCOUT
(EPWM, ECAP,
INPUTXBAR, …)
Disable
SYNCSELECT[SYNCOUT]
0xn
ECCTL2[SYNCOSEL]
ECAPSYNCINSEL[SEL]
Figure 6-53. eCAP Synchronization Scheme
6.14.4.3 eCAP Electrical Data and Timing
6.14.4.3.1 eCAP Timing Requirements
MIN
2tc(SYSCLK)
NOM
MAX
UNIT
Asynchronous
tw(CAP)
Capture input pulse width
Synchronous
2tc(SYSCLK)
ns
With input qualifier
1tc(SYSCLK) + tw_(IQSW)
6.14.4.3.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 163
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.14.5 High-Resolution Capture (HRCAP)
The eCAP3 module can be configured as high-resolution capture (HRCAP) submodules. The HRCAP
submodule measures the difference, in time, between pulses asynchronously to the system clock. This
submodule is new to the eCAP Type 1 module, and features many enhancements over the Type 0 HRCAP
module.
Applications for the HRCAP include:
•
•
•
•
•
•
•
Capacitive touch applications
High-resolution period and duty-cycle measurements of pulse train cycles
Instantaneous speed measurements
Instantaneous frequency measurements
Voltage measurements across an isolation boundary
Distance/sonar measurement and scanning
Flow measurements
The HRCAP submodule includes the following features:
•
•
•
•
•
•
•
Pulse-width capture in either non-high-resolution or high-resolution modes
Absolute mode pulse-width capture
Continuous or "one-shot" capture
Capture on either falling or rising edge
Continuous mode capture of pulse widths in 4-deep buffer
Hardware calibration logic for precision high-resolution capture
All of the resources in this list are available on any pin using the Input X-BAR.
The HRCAP submodule includes one high-resolution capture channel in addition to a calibration block. The
calibration block allows the HRCAP submodule to be continually recalibrated, at a set interval, with no “down
time”. Because the HRCAP submodule now uses the same hardware as its respective eCAP, if the HRCAP is
used, the corresponding eCAP will be unavailable.
Each high-resolution-capable channel has the following independent key resources.
•
•
•
All hardware of the respective eCAP
High-resolution calibration logic
Dedicated calibration interrupt
6.14.5.1 eCAP and HRCAP Block Diagram
For the HRCAP Block Diagram, see the eCAP and HRCAP Block Diagram in the Enhanced Capture (eCAP)
section.
Copyright © 2021 Texas Instruments Incorporated
164 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.14.5.2 HRCAP Electrical Data and Timing
6.14.5.2.1 HRCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ns
Input pulse width
110
Measurement length ≤ 5 µs
Measurement length > 5 µs
±390
±450
540
ps
Accuracy(1) (2) (3) (4)
1450
ps
See HRCAP
Standard
Standard deviation
Resolution
Deviation
Characteristics
figure
300
ps
(1) Value obtained using an oscillator of 100 PPM, oscillator accuracy directly affects the HRCAP accuracy.
(2) Measurement is completed using rising-rising or falling-falling edges
(3) Opposite polarity edges will have an additional inaccuracy due to the difference between VIH and VIL. This effect is dependent on the
signal’s slew rate.
(4) Accuracy only applies to time-converted measurements.
6.14.5.2.2 HRCAP Figure and Graph
HRCAP’s Mean
Accuracy
Resolution
(Step Size)
Precision
(Standard Deviation)
Actual
Input Signal
A. The HRCAP has some variation in performance, this results in a probability distribution which is described using the following terms:
•
•
•
Accuracy: The time difference between the input signal and the mean of the HRCAP’s distribution.
Precision: The width of the HRCAP’s distribution, this is given as a standard deviation.
Resolution: The minimum measurable increment.
Figure 6-54. HRCAP Accuracy Precision and Resolution
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 165
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
2
7.4
Typical Core Conditions
Noisy Core Supply
1.8
1.6
1.4
1.2
1
6.66
5.92
5.18
4.44
3.7
0.8
0.6
0.4
0.2
2.96
2.22
1.48
0.74
0
1000
2000
3000
4000
5000
Time Between Edges(nS)
6000
7000
8000
9000
10000
A. Typical core conditions: All peripheral clocks are enabled.
B. Noisy core supply: All core clocks are enabled and disabled with a regular period during the measurement.
C. Fluctuations in current and voltage on the 1.2-V rail cause the standard deviation of the HRCAP to rise. Care should be taken to ensure
that the 1.2-V supply is clean, and that noisy internal events, such as enabling and disabling clock trees, have been minimized while
using the HRCAP.
Figure 6-55. HRCAP Standard Deviation Characteristics
Copyright © 2021 Texas Instruments Incorporated
166 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
The eQEP module on this device is Type-2. The eQEP interfaces directly with linear or rotary incremental
encoders to obtain position, direction, and speed information from rotating machines used in high-performance
motion and position control systems.
The eQEP peripheral contains the following major functional units (see Figure 6-56):
•
•
•
•
•
•
•
Programmable input qualification for each pin (part of the GPIO MUX)
Quadrature decoder unit (QDU)
Position counter and control unit for position measurement (PCCU)
Quadrature edge-capture unit for low-speed measurement (QCAP)
Unit time base for speed/frequency measurement (UTIME)
Watchdog timer for detecting stalls (QWDOG)
Quadrature Mode Adapter (QMA)
System
control registers
To CPU
EQEPxENCLK
SYSCLK
QCPRD
Enhanced QEP (eQEP) peripheral
QCAPCTL
16
QCTMR
16
16
Quadrature
capture unit
(QCAP)
QCTMRLAT
QCPRDLAT
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
used by
multiple units
32
16
QDECCTL
16
QEPCTL
QEPSTS
QFLG
UTOUT
UTIME
QWDOG
EQEPx_A
EQEPx_B
EQEPxAIN
WDTOUT
QMA
EQEPxBIN
EQEPxINT
QCLK
PIE
QDIR
EQEPxIIN
Quadrature
32
QI
GPIO
MUX
EQEPx_INDEX
EQEPxIOUT
Position counter/
control unit
(PCCU)
decoder
(QDU)
QS
EQEPxIOE
QPOSLAT
PHE
QPOSSLAT
QPOSILAT
PCSOUT
EQEPxSIN
EQEPx_STROBE
EQEPxSOUT
EQEPxSOE
32
32
16
QEINT
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QFRC
QCLR
QPOSCTL
Figure 6-56. eQEP Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 167
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.14.6.1 eQEP Electrical Data and Timing
For an explanation of the input qualifier parameters, see the General-Purpose Input Timing Requirements table.
6.14.6.1.1 eQEP Timing Requirements
MIN
MAX
UNIT
Synchronous(1)
2tc(SYSCLK)
tw(QEPP)
QEP input period
cycles
Synchronous with input qualifier
Synchronous(1)
2[1tc(SYSCLK) + tw(IQSW)]
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
Synchronous with input qualifier
Synchronous(1)
Synchronous with input qualifier
Synchronous(1)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
2tc(SYSCLK) + tw(IQSW)
2tc(SYSCLK)
Synchronous with input qualifier
Synchronous(1)
Synchronous with input qualifier
2tc(SYSCLK) + tw(IQSW)
(1) The GPIO GPxQSELn Asynchronous mode should not be used for eQEP module input pins.
6.14.6.1.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
5tc(SYSCLK)
7tc(SYSCLK)
UNIT
cycles
cycles
td(CNTR)xin
Delay time, external clock to counter increment
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
Copyright © 2021 Texas Instruments Incorporated
168 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.14.7 Sigma-Delta Filter Module (SDFM)
SDFM features include:
•
Eight external pins per SDFM module
– Four sigma-delta data input pins per SDFM module (SD-Dx, where x = 1 to 4)
– Four sigma-delta clock input pins per SDFM module (SD-Cx, where x = 1 to 4)
Different configurable modulator clock modes supported:
•
•
– Mode 0: Modulator clock rate equals the modulator data rate.
Four independent, configurable secondary filter (comparator) units per SDFM module:
– Four different filter type selection (Sinc1/Sinc2/SincFast/Sinc3) options available
– Ability to detect over-value condition, under-value condition, and Threshold-crossing conditions
1. Two independent Higher Threshold comparators (used to detect over-value condition)
2. Two independent Lower Threshold comparators (used to detect under-value condition)
3. One independent Threshold-Crossing comparator (used to measure duty cycle/frequency with eCAP)
– OSR value for comparator filter unit (COSR) programmable from 1 to 32
Four independent configurable primary filter (data filter) units per SDFM module:
– Four different filter type selection (Sinc1/Sinc2/SincFast/Sinc3) options available
– OSR value for data filter unit (DOSR) programmable from 1 to 256
– Ability to enable or disable (or both) individual filter module
•
– Ability to synchronize all four independent filters of an SDFM module by using the Master Filter Enable
(MFE) bit or by using PWM signals
•
•
Data filter output can be represented in either 16 bits or 32 bits.
Data filter unit has a programmable mode FIFO to reduce interrupt overhead. The FIFO has the following
features:
– The primary filter (data filter) has a 16-deep x 32-bit FIFO.
– The FIFO can interrupt the CPU after programmable number of data-ready events.
– FIFO Wait-for-Sync feature: Ability to ignore data-ready events until the PWM synchronization signal
(SDSYNC) is received. Once the SDSYNC event is received, the FIFO is populated on every data-ready
event.
– Data filter output can be represented in either 16 bits or 32 bits.
•
•
•
•
•
PWMx.SOCA/SOCB can be configured to serve as SDSYNC source on a per-data-filter-channel basis.
PWMs can be used to generate a modulator clock for sigma-delta modulators.
Configurable Input Qualification available for both SD-Cx and SD-Dx
Ability to use one filter channel clock (SD-C1) to provide clock to other filter clock channels.
Configurable digital filter available on comparator filter events to blankout comparator events caused by
spurious noise
Figure 6-57 shows the SDFM module block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 169
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Output XBAR
PWM XBAR
SDyFLTx_CEVT1 SDyFLTx_CEVT2
Comparator
Signals
SDyFLTx.DR
SDFM- Sigma Delta Filter Module
G4
Streams
DMA
Filter Module 1
Secondary
(Comparator)
Filter
Interrupt
Unit
SDy_D1
SDy_C1
Input
Ctrl
SDy_ERR
Primary (Data)
Filter
SDyFLTx.DR
CLA
PWMi.SOCA / SOCB
PWMj.CMPC
FIFO
SDy_D2
SDy_C2
Filter Module 2
SDy_ERR
SDyFLTx.DR
C28x
GPIO
MUX
PWMi.SOCA / SOCB
PWMj.CMPC
SDy_D3
SDy_C3
Filter Module 3
Filter Module 4
SDyFLTx_CEVT1
SDyFLTx_CEVT2
ECAP
PWMi.SOCA / SOCB
PWMj.CMPD
Register
Map
SDy_D4
SDy_C4
PWMi.SOCA / SOCB
PWMj.CMPD
LEGEND
Where,
j
i
=
=
y =
x =
11 for SDFM1 & 12 for SDFM2
1 to Max. no of PWMs
1 for SDFM1 & 2 for SDFM2
1 t 4
Interrupt / trigger sources from SDFM
Internal secondary filter signals
Figure 6-57. Sigma Delta Filter Module (SDFM) Block Diagram
6.14.7.1 SDFM Electrical Data and Timing
WARNING
Special precautions should be taken on both SD-Cx and SD-Dx signals to ensure a clean and
noise-free signal that meets SDFM timing requirements. Precautions such as series termination
resistors for ringing noise due to any impedance mismatch of clock driver and spacing of traces from
other noisy signals are recommended.
Note
The SDFM SD-Cx and SD-Dx signals, when synchronized to PLLRAWCLK, provide protection
against SDFM module corruption due to occasional random noise glitches that may result in a false
comparator trip and filter output. However, the signals do not provide protection against persistent
violations of the above timing requirements. Timing violations will result in data corruption proportional
to the number of bits which violate the requirements.
6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
MIN
MAX
UNIT
Mode 0
tc(SDC)M0
Cycle time, SDx_Cy
4 * tc(PLLRAWCLK)
2 * tc(PLLRAWCLK)
256 * SYSCLK period
ns
ns
ns
ns
tw(SDDHL)M0
tsu(SDDV-SDCH)M0
th(SDCH-SDD)M0
Pulse duration, SDx_Dy (high / Low)
Setup time, SDx_Dy valid before SDx_Cy goes high
Hold time, SDx_Dy wait after SDx_Cy goes high
1 * tc(PLLRAWCLK) + 3
1 * tc(PLLRAWCLK) + 3
Copyright © 2021 Texas Instruments Incorporated
170 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15 Communications Peripherals
6.15.1 Controller Area Network (CAN)
Note
The CAN module uses the IP known as DCAN. This document uses the names CAN and DCAN
interchangeably to reference this peripheral.
The CAN module implements the following features:
•
•
•
•
Complies with ISO11898-1 ( Bosch® CAN protocol specification 2.0 A and B)
Bit rates up to 1 Mbps
Multiple clock sources
32 message objects (mailboxes), each with the following properties:
– Configurable as receive or transmit
– Configurable with standard (11-bit) or extended (29-bit) identifier
– Supports programmable identifier receive mask
– Supports data and remote frames
– Holds 0 to 8 bytes of data
– Parity-checked configuration and data RAM
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loopback modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after bus-off state by a programmable 32-bit timer
Two interrupt lines
•
•
•
•
•
•
•
•
DMA support
Note
For a CAN bit clock of 100 MHz, the smallest bit rate possible is 3.90625 kbps.
Note
The accuracy of the on-chip zero-pin oscillator is in the INTOSC Characteristics table. Depending
on parameters such as the CAN bit timing settings, bit rate, bus length, and propagation delay, the
accuracy of this oscillator may not meet the requirements of the CAN protocol. In this situation, an
external clock source must be used.
Figure 6-58 shows the CAN block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 171
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
CAN_H
CAN_L
CAN Bus
3.3V CAN Transceiver
CANx TX pin
External connections
Device
CANx RX pin
CAN
CAN Core
Message RAM
Message Handler
Message
RAM
Interface
Register and Message
Object Access (IFx)
32
Message
Objects
(Mailboxes)
Test Modes
Only
Module Interface
CANINT0 CANINT1
DMA
CPU Bus
Figure 6-58. CAN Block Diagram
Copyright © 2021 Texas Instruments Incorporated
172 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.2 Modular Controller Area Network (MCAN)
The Controller Area Network (CAN) is a serial communications protocol that efficiently supports distributed
real-time control with a high level of reliability. CAN has high immunity to electrical interference and the ability to
detect various type of errors. In CAN, many short messages are broadcast to the entire network, which provides
data consistency in every node of the system.
The MCAN module supports both classic CAN and CAN FD (CAN with flexible data-rate) protocols. The CAN FD
feature allows higher throughput and increased payload per data frame. Classic CAN and CAN FD devices may
coexist on the same network without any conflict provided that partial network transceivers, which can detect
and ignore CAN FD without generating bus errors, are used by the classic CAN devices. The MCAN module is
compliant to ISO 11898-1:2015.
Note
The availabilty of the CAN FD feature is dependent on the device's part number. Refer to the device
data sheet for more information.
Device
MCANSS
Uncorrectable ECC
NMI
PIE
Correctable ECC
Configurable Interrupts (2 lines)
Counter Overflow and Clock Stop/
Wakeup
mcanss_tx
mcanss_rx
CPU BUS
SYSCLK
Peripheral Clock
Bit Timing Clock
Clock disable/
enable
MCAN Bit Clock
Wakeup
Clock Stop and Wakeup
RESET
Reset
Figure 6-59. MCAN Module Overview
The MCAN module implements the following features:
•
•
•
•
•
•
•
•
•
•
•
•
Conforms with CAN Protocol 2.0 A, B and ISO 11898-1:2015
Full CAN FD support (up to 64 data bytes)
AUTOSAR and SAE J1939 support
Up to 32 dedicated transmit buffers
Configurable transmit FIFO, up to 32 elements
Configurable transmit queue, up to 32 elements
Configurable transmit Event FIFO, up to 32 elements
Up to 64 dedicated receive buffers
Two configurable receive FIFOs, up to 64 elements each
Up to 128 filter elements
Loop-back mode for self-test
Maskable interrupt (two configurable interrupt lines, correctable ECC, counter overflow and clock stop/
wakeup)
•
Non-maskable interrupt (uncorrectable ECC)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 173
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
•
•
•
•
Two clock domains (CAN clock/host clock)
ECC check for Message RAM
Clock stop and wakeup support
Timestamp counter
Non-supported features:
•
•
•
Host bus firewall
Clock calibration
Debug over CAN
Copyright © 2021 Texas Instruments Incorporated
174 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.3 Inter-Integrated Circuit (I2C)
The I2C module has the following features:
•
Compliance with the NXP Semiconductors I2C-bus specification (version 2.1):
– Support for 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (Fast-mode)
Supports voltage thresholds compatible to:
– SMBus 2.0 and below
•
– PMBus 1.2 and below
•
•
One 16-byte receive FIFO and one 16-byte transmit FIFO
Supports two ePIE interrupts
– I2Cx interrupt – Any of the below conditions can be configured to generate an I2Cx interrupt:
•
•
•
•
•
•
•
Transmit Ready
Receive Ready
Register-Access Ready
No-Acknowledgment
Arbitration-Lost
Stop Condition Detected
Addressed-as-Slave
– I2Cx_FIFO interrupts:
•
•
Transmit FIFO interrupt
Receive FIFO interrupt
•
•
Module enable and disable capability
Free data format mode
Figure 6-60 shows how the I2C peripheral module interfaces within the device.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 175
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
I2C module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt
to CPU/PIE
SDA
Peripheral bus
I2CRSR
I2CDRR
Control/status
registers
CPU
Clock
synchronizer
SCL
Prescaler
Noise filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
Figure 6-60. I2C Peripheral Module Interfaces
Copyright © 2021 Texas Instruments Incorporated
176 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.3.1 I2C Electrical Data and Timing
Note
To meet all of the I2C protocol timing specifications, the I2C module clock must be configured in the
range from 7 MHz to 12 MHz.
6.15.3.1.1 I2C Timing Requirements
NO.
MIN
MAX
UNIT
Standard mode
T0
T1
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
th(SDA-SCL)START
4.0
Setup time, Repeated START, SCL rise before SDA
fall delay
T2
tsu(SCL-SDA)START
4.0
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
µs
ns
ns
ns
ns
ns
250
1000
1000
300
tr(SCL)
Rise time, SCL
tf(SDA)
Fall time, SDA
tf(SCL)
Fall time, SCL
300
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
4.0
µs
Pulse duration of spikes that will be suppressed by
filter
T10
tw(SP)
Cb
ns
0
50
T11
capacitance load on each bus line
400
pF
Fast mode
T0
fmod
I2C module frequency
7
12
MHz
µs
Hold time, START condition, SCL fall delay after
SDA fall
T1
T2
th(SDA-SCL)START
0.6
Setup time, Repeated START, SCL rise before SDA
fall delay
tsu(SCL-SDA)START
0.6
µs
T3
T4
T5
T6
T7
T8
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before SDA
rise delay
T9
tsu(SCL-SDA)STOP
0.6
µs
Pulse duration of spikes that will be suppressed by
filter
T10
T11
tw(SP)
Cb
ns
0
50
capacitance load on each bus line
400
pF
6.15.3.1.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
Standard mode
S1
S2
S3
fSCL
SCL clock frequency
SCL clock period
0
10
100
kHz
µs
TSCL
tw(SCLL)
Pulse duration, SCL clock low
4.7
µs
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 177
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.3.1.2 I2C Switching Characteristics (continued)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
S4
tw(SCLH)
tBUF
Pulse duration, SCL clock high
4.0
µs
Bus free time between STOP and START
conditions
S5
4.7
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
3.45
3.45
10
µs
µs
µA
0.1 Vbus < Vi < 0.9 Vbus
–10
Fast mode
S1
S2
S3
S4
fSCL
SCL clock frequency
0
2.5
1.3
0.6
400
kHz
µs
TSCL
SCL clock period
tw(SCLL)
tw(SCLH)
Pulse duration, SCL clock low
Pulse duration, SCL clock high
µs
µs
Bus free time between STOP and START
conditions
S5
tBUF
1.3
µs
S6
S7
S8
tv(SCL-DAT)
tv(SCL-ACK)
II
Valid time, data after SCL fall
Valid time, Acknowledge after SCL fall
Input current on pins
0.9
0.9
10
µs
µs
µA
0.1 Vbus < Vi < 0.9 Vbus
–10
6.15.3.1.3 I2C Timing Diagram
STOP
START
SDA
SCL
ACK
Contd...
Contd...
S7
S6
T10
T5
T7
S3
S4
9th
clock
T6
T8
S2
Repeated
START
STOP
S5
SDA
ACK
T2
T9
T1
SCL
9th
clock
Figure 6-61. I2C Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
178 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.4 Power Management Bus (PMBus) Interface
The PMBus module has the following features:
•
•
Compliance with the SMI Forum PMBus Specification (Part I v1.0 and Part II v1.1)
Supports voltage thresholds compatible to:
– PMBus 1.2 and below
– SMBus 2.0 and below
•
•
•
Support for master and slave modes
Support for I2C mode
Support for two speeds:
– Standard Mode: Up to 100 kHz
– Fast Mode: 400 kHz
•
•
•
•
•
Packet error checking
CONTROL and ALERT signals
Clock high and low time-outs
Four-byte transmit and receive buffers
One maskable interrupt, which can be generated by several conditions:
– Receive data ready
– Transmit buffer empty
– Slave address received
– End of message
– ALERT input asserted
– Clock low time-out
– Clock high time-out
– Bus free
PCLKCR20
SYSCLK
PMBCTRL
Div
ALERT
CTL
DMA
CPU
PIE
Bit clock
Other registers
GPIO Mux
PMBTXBUF
SCL
Shift register
PMBRXBUF
SDA
PMBUSA_INT
PMBus Module
Figure 6-62. PMBus Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 179
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.4.1 PMBus Electrical Data and Timing
6.15.4.1.1 PMBus Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.8
UNIT
V
VIL
VIH
VOL
IOL
Valid low-level input voltage
Valid high-level input voltage
Low-level output voltage
Low-level output current
2.1
VDDIO
0.4
V
At Ipullup = 4 mA
VOL ≤ 0.4 V
V
4
0
mA
Pulse width of spikes that must be
suppressed by the input filter
tSP
50
ns
Ii
Input leakage current on each pin
Capacitance on each pin
0.1 Vbus < Vi < 0.9 Vbus
–10
10
10
µA
pF
Ci
6.15.4.1.2 PMBus Fast Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
400
kHz
Bus free time between STOP and
START conditions
1.3
0.6
0.6
0.6
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
100
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
5% to 95%
95% to 5%
20
20
300
300
ns
ns
Copyright © 2021 Texas Instruments Incorporated
180 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.4.1.3 PMBus Standard Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSCL
tBUF
SCL clock frequency
10
100
kHz
Bus free time between STOP and
START conditions
4.7
4
µs
µs
µs
µs
START condition hold time -- SDA fall
to SCL fall delay
tHD;STA
tSU;STA
tSU;STO
Repeated START setup time -- SCL
rise to SDA fall delay
4.7
4
STOP condition setup time -- SCL rise
to SDA rise delay
tHD;DAT
tSU;DAT
tTimeout
tLOW
Data hold time after SCL fall
Data setup time before SCL rise
Clock low time-out
300
250
25
ns
ns
ms
µs
µs
35
Low period of the SCL clock
High period of the SCL clock
4.7
4
tHIGH
50
25
Cumulative clock low extend time
(slave device)
tLOW;SEXT
tLOW;MEXT
From START to STOP
Within each byte
ms
ms
Cumulative clock low extend time
(master device)
10
tr
tf
Rise time of SDA and SCL
Fall time of SDA and SCL
1000
300
ns
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 181
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.5 Serial Communications Interface (SCI)
The SCI is a 2-wire asynchronous serial port, commonly known as a UART. The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format
The SCI receiver and transmitter each have a 16-level-deep FIFO for reducing servicing overhead, and each has
its own separate enable and interrupt bits. Both can be operated independently for half-duplex communication,
or simultaneously for full-duplex communication. To specify data integrity, the SCI checks received data for break
detection, parity, overrun, and framing errors. The bit rate is programmable to different speeds through a 16-bit
baud-select register.
Features of the SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
– Baud rate programmable to 64K different rates
Data-word format
•
– 1 start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
Auto baud-detect hardware logic
16-level transmit and receive FIFO
•
•
•
•
Note
All registers in this module are 8-bit registers. When a register is accessed, the register data is in the
lower byte (bits 7–0), and the upper byte (bits 15–8) is read as zeros. Writing to the upper byte has no
effect.
Figure 6-63 shows the SCI block diagram.
Copyright © 2021 Texas Instruments Incorporated
182 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
TXSHF
Register
SCITXD
8
TXENA
SCICTL1.1
Frame
Format and Mode
Parity
Even/Odd
TXEMPTY
SCICTL2.6
0
1
SCICCR.6
8
Enable
TX FIFO_0
TX FIFO_1
TXINT
SCICCR.5
To CPU
TX Interrupt
TX FIFO Interrupts
8
Logic
TX FIFO_N
TXINTENA
SCICTL2.0
TXRDY
8
1
0
TXWAKE
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
Auto Baud Detect Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
RXENA
Baud Rate
MSB/LSB
Registers
SCICTL1.0
LSPCLK
RXSHF
Register
SCIRXD
SCIHBAUD.15-8
SCILBAUD.7-0
RXWAKE
8
SCIRXST.1
0
1
8
SCIFFENA
SCIFFTX.14
RX FIFO_0
RX FIFO_1
RXINT
To CPU
8
RX FIFO Interrupts
RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8
1
SCIFFRX.15
0
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
RXERRINTENA
SCICTL1.6
SCICTL1.0
SCIRXST.5
SCI RX Interrupt Select Logic
8
SCIRXST.5-2
BRKDT FE OE PE
RXERROR
Receive Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.7
Figure 6-63. SCI Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 183
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.6 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a high-speed synchronous serial input and output (I/O) port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-
transfer rate. The SPI is normally used for communications between the MCU controller and external peripherals
or another controller. Typical applications include external I/O or peripheral expansion through devices such
as shift registers, display drivers, and analog-to-digital converters (ADCs). Multidevice communications are
supported by the master or slave operation of the SPI. The port supports a 16-level, receive and transmit FIFO
for reducing CPU servicing overhead.
The SPI module features include:
•
•
•
•
•
•
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
Two operational modes: Master and Slave
Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited by the
maximum speed of the I/O buffers used on the SPI pins.
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithm
16-level transmit/receive FIFO
•
•
•
•
•
•
•
•
DMA support
High-speed mode
Delayed transmit control
3-wire SPI mode
SPISTE inversion for digital audio interface receive mode on devices with two SPI modules
Figure 6-64 shows the SPI CPU interfaces.
Copyright © 2021 Texas Instruments Incorporated
184 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
PCLKCR8
Low-Speed
Prescaler
CPU
LSPCLK
SYSCLK
Bit Clock
SYSRS
SPISIMO
SPISOMI
SPICLK
SPISTE
SPI
GPIO MUX
SPIINT
PIE
SPITXINT
SPIRXDMA
SPITXDMA
DMA
Figure 6-64. SPI CPU Interface
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 185
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.6.1 SPI Master Mode Timings
The following section contains the SPI Master Mode Timings. For more information about the SPI in High-Speed
mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28003x Real-Time Microcontrollers
Technical Reference Manual.
Note
All timing parameters for SPI High-Speed Mode assume a load capacitance of 5 pF on SPICLK,
SPISIMO, and SPISOMI.
6.15.6.1.1 SPI Master Mode Timing Requirements
NO.
(BRR + 1) (1)
MIN
MAX UNIT
High-Speed Mode
8
9
tsu(SOMI)M
th(SOMI)M
Setup time, SPISOMI valid before SPICLK
Hold time, SPISOMI valid after SPICLK
Even, Odd
Even, Odd
1
ns
ns
6.5
Normal Mode
8
9
tsu(SOMI)M
th(SOMI)M
Setup time, SPISOMI valid before SPICLK
Hold time, SPISOMI valid after SPICLK
Even, Odd
Even, Odd
15
0
ns
ns
(1) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Copyright © 2021 Texas Instruments Incorporated
186 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.6.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER(1) (2)
(BRR + 1)(3)
MIN
MAX UNIT
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
0.5tc(SPC)M
0.5tc(LSPCLK) + 1
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
0.5tc(SPC)M
0.5tc(LSPCLK) + 1
1.5tc(SPC)M
3tc(SYSCLK) + 3
1.5tc(SPC)M
4tc(SYSCLK) + 3
0.5tc(SPC)M – 3 0.5tc(SPC)M + 3
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
tw(SPC1)M Pulse duration, SPICLK, first pulse
+
Odd
Even
Odd
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
3
tw(SPC2)M Pulse duration, SPICLK, second pulse
ns
ns
ns
–
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
1.5tc(SPC)M – 3tc(SYSCLK) – 3
1.5tc(SPC)M – 4tc(SYSCLK) – 3
–
Even
23
24
td(SPC)M
Delay time, SPISTE active to SPICLK
Valid time, SPICLK to SPISTE inactive
–
Odd
Even
Odd
tv(STE)M
0.5tc(SPC)M
–
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
0.5tc(LSPCLK) + 3
High-Speed Mode
4
td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd
1
ns
ns
Even
Odd
0.5tc(SPC)M – 3
Valid time, SPISIMO valid after
SPICLK
5
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
4
td(SIMO)M Delay time, SPICLK to SPISIMO valid Even, Odd
2
ns
ns
Even
Odd
0.5tc(SPC)M – 3
Valid time, SPISIMO valid after
SPICLK
5
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
(1) 10-pF load on pin for High-Speed Mode.
(2) 20-pF load on pin for Normal Mode.
(3) The (BRR + 1) condition is Even when (SPIBRR + 1) is even or SPIBRR is 0 or 2. It is Odd when (SPIBRR + 1) is odd and SPIBRR is
greater than 3.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 187
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
MAX UNIT
SPRSP61 – OCTOBER 2021
6.15.6.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER(1) (2)
(BRR + 1)
MIN
General
Even
Odd
4tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
0.5tc(SPC)M
0.5tc(LSPCLK) + 1
0.5tc(SPC)M – 1 0.5tc(SPC)M + 1
0.5tc(SPC)M
0.5tc(LSPCLK) + 1
2tc(SPC)M
128tc(LSPCLK)
1
2
tc(SPC)M
Cycle time, SPICLK
ns
ns
127tc(LSPCLK)
Even
tw(SPCH)M Pulse duration, SPICLK, first pulse
–
Odd
Even
Odd
0.5tc(SPC)M – 0.5tc(LSPCLK) – 1
3
tw(SPC2)M Pulse duration, SPICLK, second pulse
ns
+
0.5tc(SPC)M + 0.5tc(LSPCLK) – 1
–
23
24
td(SPC)M
Delay time, SPISTE valid to SPICLK
Delay time, SPICLK to SPISTE invalid
Even, Odd
2tc(SPC)M – 3tc(SYSCLK) – 3
ns
ns
3tc(SYSCLK) + 3
Even
Odd
–3
–3
3
3
td(STE)M
High-Speed Mode
Even
Odd
0.5tc(SPC)M – 2
0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
0.5tc(SPC)M – 3
4
5
td(SIMO)M Delay time, SPISIMO valid to SPICLK
ns
ns
Even
Odd
Valid time, SPISIMO valid after
tv(SIMO)M
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
Normal Mode
Even
Odd
0.5tc(SPC)M – 2
0.5tc(SPC)M + 0.5tc(LSPCLK) – 2
0.5tc(SPC)M – 3
4
5
td(SIMO)M Delay time, SPISIMO valid to SPICLK
ns
ns
Even
Odd
Valid time, SPISIMO valid after
SPICLK
tv(SIMO)M
0.5tc(SPC)M – 0.5tc(LSPCLK) – 3
(1) 10-pF load on pin for High-Speed Mode.
(2) 20-pF load on pin for Normal Mode.
Copyright © 2021 Texas Instruments Incorporated
188 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.6.1.4 SPI Master Mode Timing Diagrams
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.
Figure 6-65. SPI Master Mode External Timing (Clock Phase = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data Must
Be Valid
SPISOMI
SPISTE(A)
24
23
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO
modes.
Figure 6-66. SPI Master Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 189
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.6.2 SPI Slave Mode Timings
The following section contains the SPI Slave Mode Timings. For more information about the SPI in High-Speed
mode, see the Serial Peripheral Interface (SPI) chapter of the TMS320F28003x Real-Time Microcontrollers
Technical Reference Manual.
6.15.6.2.1 SPI Slave Mode Timing Requirements
NO.
12
MIN
4tc(SYSCLK)
MAX UNIT
tc(SPC)S
Cycle time, SPICLK
ns
ns
ns
ns
ns
13
14
19
20
tw(SPC1)S
tw(SPC2)S
tsu(SIMO)S
th(SIMO)S
Pulse duration, SPICLK, first pulse
Pulse duration, SPICLK, second pulse
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO valid after SPICLK
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
1.5tc(SYSCLK)
1.5tc(SYSCLK)
Setup time, SPISTE valid before SPICLK
(Clock Phase = 0)
2tc(SYSCLK) + 15
ns
25
26
tsu(STE)S
Setup time, SPISTE valid before SPICLK
(Clock Phase = 1)
2tc(SYSCLK) + 15
1.5tc(SYSCLK)
ns
ns
th(STE)S
Hold time, SPISTE invalid after SPICLK
6.15.6.2.2 SPI Slave Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO.
15
16
PARAMETER(1)
MIN
MAX UNIT
td(SOMI)S
tv(SOMI)S
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI valid after SPICLK
12
ns
ns
0
(1) 20-pF load on pin.
Copyright © 2021 Texas Instruments Incorporated
190 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.6.2.3 SPI Slave Mode Timing Diagrams
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 6-67. SPI Slave Mode External Timing (Clock Phase = 0)
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
16
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 6-68. SPI Slave Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 191
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.7 Local Interconnect Network (LIN)
This device contains one Local Interconnect Network (LIN) module. The LIN module adheres to the LIN 2.1
standard as defined by the LIN Specification Package Revision 2.1. The LIN is a low-cost serial interface
designed for applications where the CAN protocol may be too expensive to implement, such as small
subnetworks for cabin comfort functions like interior lighting or window control in an automotive application.
The LIN standard is based on the SCI (UART) serial data link format. The communication concept is single-
master and multiple-slave with a message identification for multicast transmission between any network nodes.
The LIN module can be programmed to work either as an SCI or as a LIN as the core of the module is an SCI.
The hardware features of the SCI are augmented to achieve LIN compatibility. The SCI module is a universal
asynchronous receiver-transmitter (UART) that implements the standard non-return-to-zero format.
Though the registers are common for LIN and SCI, the register descriptions have notes to identify the register/bit
usage in different modes. Because of this, code written for this module cannot be directly ported to the stand-
alone SCI module and vice versa.
The LIN module has the following features:
•
•
•
•
•
•
Compatibility with LIN 1.3, 2.0 and 2.1 protocols
Configurable baud rate up to 20 kbps (as per LIN 2.1 protocol)
Two external pins: LINRX and LINTX
Multibuffered receive and transmit units
Identification masks for message filtering
Automatic master header generation
– Programmable synchronization break field
– Synchronization field
– Identifier field
•
Slave automatic synchronization
– Synchronization break detection
– Optional baud rate update
– Synchronization validation
•
•
•
231 programmable transmission rates with 7 fractional bits
Wakeup on LINRX dominant level from transceiver
Automatic wakeup support
– Wakeup signal generation
– Expiration times on wakeup signals
Automatic bus idle detection
Error detection
•
•
– Bit error
– Bus error
– No-response error
– Checksum error
– Synchronization field error
– Parity error
•
•
Capability to use direct memory access (DMA) for transmit and receive data
Two interrupt lines with priority encoding for:
– Receive
– Transmit
– ID, error, and status
•
•
•
•
•
Support for LIN 2.0 checksum
Enhanced synchronizer finite state machine (FSM) support for frame processing
Enhanced handling of extended frames
Enhanced baud rate generator
Update wakeup/go to sleep
Copyright © 2021 Texas Instruments Incorporated
192 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR
INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIME-OUT
CONTROL
COUNTER
COMPARE
LINRX/
SCIRX
LINTX/
SCITX
DMA
CONTROL
MASK
FILTER
8 RECEIVE
BUFFERS
FSM
8 TRANSMIT
BUFFERS
SYNCHRONIZER
Figure 6-69. LIN Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 193
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.8 Fast Serial Interface (FSI)
The Fast Serial Interface (FSI) module is a serial communication peripheral capable of reliable and robust
high-speed communications. The FSI is designed to ensure data robustness across many system conditions
such as chip-to-chip as well as board-to-board across an isolation barrier. Payload integrity checks such as
CRC, start- and end-of-frame patterns, and user-defined tags, are encoded before transmit and then verified
after receipt without additional CPU interaction. Line breaks can be detected using periodic transmissions, all
managed and monitored by hardware. The FSI is also tightly integrated with other control peripherals on the
device. To ensure that the latest sensor data or control parameters are available, frames can be transmitted on
every control loop period. An integrated skew-compensation block has been added on the receiver to handle
skew that may occur between the clock and data signals due to a variety of factors, including trace-length
mismatch and skews induced by an isolation chip. With embedded data robustness checks, data-link integrity
checks, skew compensation, and integration with control peripherals, the FSI can enable high-speed, robust
communication in any system. These and many other features of the FSI follow.
The FSI module includes the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Independent transmitter and receiver cores
Source-synchronous transmission
Dual data rate (DDR)
One or two data lines
Programmable data length
Skew adjustment block to compensate for board and system delay mismatches
Frame error detection
Programmable frame tagging for message filtering
Hardware ping to detect line breaks during communication (ping watchdog)
Two interrupts per FSI core
Externally triggered frame generation
Hardware- or software-calculated CRC
Embedded ECC computation module
Register write protection
DMA support
SPI compatibility mode (limited features available)
Operating the FSI at maximum speed (60 MHz) at dual data rate (120 Mbps) may require the integrated skew
compensation block to be configured according to the specific operating conditions on a case-by-case basis.
The Fast Serial Interface (FSI) Skew Compensation Application Report provides example software on how to
configure and set up the integrated skew compensation block on the Fast Serial Interface.
The FSI consists of independent transmitter (FSITX) and receiver (FSIRX) cores. The FSITX and FSIRX cores
are configured and operated independently. The features available on the FSITX and FSIRX are described in the
FSI Transmitter section and the FSI Receiver section, respectively.
Copyright © 2021 Texas Instruments Incorporated
194 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.8.1 FSI Transmitter
The FSI transmitter module handles the framing of data, CRC generation, signal generation of TXCLK, TXD0,
and TXD1, as well as interrupt generation. The operation of the transmitter core is controlled and configured
through programmable control registers. The transmitter control registers let the CPU program, control, and
monitor the operation of the FSI transmitter. The transmit data buffer is accessible by the CPU and the DMA.
The transmitter has the following features:
•
•
•
•
•
•
•
•
•
Automated ping frame generation
Externally triggered ping frames
Externally triggered data frames
Software-configurable frame lengths
16-word data buffer
Data buffer underrun and overrun detection
Hardware-generated CRC on data bits
Software ECC calculation on select data
DMA support
Figure 6-70 shows the FSITX CPU interface. Figure 6-71 shows the high-level block diagram of the FSITX. Not
all data paths and internal connections are shown. This diagram provides a high-level overview of the internal
modules present in the FSITX.
PLLRAWCLK
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSITXyINT1
FSITXyINT2
CLA
FSITXyCLK
FSITXyD0
FSITXyD1
FSITX
DMA
FSITXyDMA
32
A. The signals connected to the trigger muxes are described in the External Frame Trigger Mux section of the Fast Serial Interface (FSI)
chapter in the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual.
Figure 6-70. FSITX CPU Interface
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 195
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
FSITX
PLLRAWCLK
SYSRSN
SYSCLK
FSI Mode:
TXCLKIN
Transmit Clock
Generator
TXCLK = TXCLKIN/2
SPI Signaling Mode:
TXCLK = TXCLKIN
Register Interface
FSITXINT1
Core Reset
Control Registers,
Interrupt Management
TXCLK
FSITXINT2
Ping Time-out Counter
FSITX_DMA_EVT
TXD0
TXD1
Transmitter Core
External Frame Triggers
Transmit Data
Buffer
ECC Logic
Figure 6-71. FSITX Block Diagram
6.15.8.1.1 FSITX Electrical Data and Timing
6.15.8.1.1.1 FSITX Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER(1)
MIN
MAX
UNIT
ns
1
2
tc(TXCLK)
tw(TXCLK)
Cycle time, TXCLK
16.67
Pulse width, TXCLK low or TXCLK high
(0.5tc(TXCLK)) – 1
(0.25tc(TXCLK)) – 2
(0.5tc(TXCLK)) + 1
(0.25tc(TXCLK)) + 2
ns
Delay time, TXCLK rising or falling toTXD
valid
3
4
5
6
7
td(TXCLK–TXD)
td(TXCLK)
ns
ns
ns
ns
ns
ns
TXCLK delay compensation at
TX_DLYLINE_CTRL[TXCLK_DLY]=31
9.95
9.95
9.95
0.3
30
30
30
1
TXD0 delay compensation at
TX_DLYLINE_CTRL[TXD0_DLY]=31
td(TXD0)
TXD1 delay compensation at
TX_DLYLINE_CTRL[TXD1_DLY]=31
td(TXD1)
Incremental delay of each delay line element
for TXCLK, TXD0, and TXD1
td(DELAY_ELEMENT)
tskew(TDM_CLK-TDM_Dx )
Delay skew introduced between TXCLK-
TDM_CLK delay and TXDx-TDM_Dx delays
TDM1
-2.5
2.5
(1) 10-pF load on pin.
Copyright © 2021 Texas Instruments Incorporated
196 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.8.1.1.2 FSITX Timings
1
2
FSITXCLK
FSITXD0
FSITXD1
3
Figure 6-72. FSITX Timings
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 197
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.8.2 FSI Receiver
The receiver module interfaces to the FSI clock (RXCLK), and data lines (RXD0 and RXD1) after they pass
through an optional programmable delay line. The receiver core handles the data framing, CRC computation,
and frame-related error checking. The receiver bit clock and state machine are run by the RXCLK input, which is
asynchronous to the device system clock.
The receiver control registers let the CPU program, control, and monitor the operation of the FSIRX. The receive
data buffer is accessible by the CPU, HIC, and the DMA.
The receiver core has the following features:
•
•
•
•
•
•
•
•
•
16-word data buffer
Multiple supported frame types
Ping frame watchdog
Frame watchdog
CRC calculation and comparison in hardware
ECC detection
Programmable delay line control on incoming signals
DMA support
SPI compatibility mode
Figure 6-73 shows the FSIRX CPU interface. Figure 6-74 provides a high-level overview of the internal modules
present in the FSIRX. Not all data paths and internal connections are shown.
PCLKCR18
SYSCLK
SYSRSN
C28x
ePIE
FSIRXyINT1
FSIRXyINT2
CLA
FSIRXyCLK
FSIRXyD0
FSIRXyD1
FSIRX
DMA
FSIRXyDMA
Figure 6-73. FSIRX CPU Interface
Copyright © 2021 Texas Instruments Incorporated
198 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
FSIRX
SYSRSn
SYSCLK
Frame Watchdog
Register Interface
FSIRXINT1
Core Reset
Control Registers,
Interrupt Management
FSIRXINT2
RXCLK
Ping Watchdog
FSIRX_DMA_EVT
Receiver Core
Skew
Control
RXD0
RXD1
Receive Data
Buffer
ECC Check
Logic
Figure 6-74. FSIRX Block Diagram
6.15.8.2.1 FSIRX Electrical Data and Timing
6.15.8.2.1.1 FSIRX Timing Requirements
NO.
MIN
16.67
MAX
UNIT
1
2
tc(RXCLK)
tw(RXCLK)
Cycle time, RXCLK
ns
ns
Pulse width, RXCLK low or RXCLK high.
0.35tc(RXCLK)
0.65tc(RXCLK)
Setup time with respect to RXCLK, applies to
both edges of the clock
3
4
tsu(RXCLK–RXD)
th(RXCLK–RXD)
1.7
2
ns
ns
Hold time with respect to RXCLK, applies to
both edges of the clock
6.15.8.2.1.2 FSIRX Switching Characteristics
NO.
PARAMETER(1)
MIN
MAX
UNIT
RXCLK delay compensation at
RX_DLYLINE_CTRL[RXCLK_DLY]=31
1
2
3
4
td(RXCLK)
10
30
ns
RXD0 delay compensation at
RX_DLYLINE_CTRL[RXD0_DLY]=31
td(RXD0)
10
10
0.3
-3
30
30
1
ns
ns
ns
ns
RXD1 delay compensation
at RX_DLYLINE_CTRL[RXD1_DLY]=31
td(RXD1)
Incremental delay of each delay line element
for RXCLK, RXD0, and RXD1
td(DELAY_ELEMENT)
tskew(TDM_CLK-TDM_Dx )
(1) 10-pF load on pin.
Delay skew introduced between RXCLK-
TDM_CLK delay and RXDx-TDM_Dx delays
TDM1
3
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 199
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.8.2.1.3 FSIRX Timings
1
2
FSIRXCLK
FSIRXD0
FSIRXD1
3
4
Figure 6-75. FSIRX Timings
Copyright © 2021 Texas Instruments Incorporated
200 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.8.3 FSI SPI Compatibility Mode
The FSI supports a SPI compatibility mode to enable communication with programmable SPI devices. In this
mode, the FSI transmits its data in the same manner as a SPI in a single clock configuration mode. While the
FSI is able to physically interface with a SPI in this mode, the external device must be able to encode and
decode an FSI frame to communicate successfully. This is because the FSI transmits all SPI frame phases with
the exception of the preamble and postamble. The FSI provides the same data validation and frame checking
as if it was in standard FSI mode, allowing for more robust communication without consuming CPU cycles. The
external SPI is required to send all relevant information and can access standard FSI features such as the ping
frame watchdog on the FSIRX, frame tagging, or custom CRC values. The list of features of SPI compatibility
mode follows:
•
•
•
Data will transmit on rising edge and receive on falling edge of the clock.
Only 16-bit word size is supported.
TXD1 will be driven like an active-low chip-select signal. The signal will be low for the duration of the full
frame transmission.
•
•
•
No receiver chip-select input is required. RXD1 is not used. Data is shifted into the receiver on every active
clock edge.
No preamble or postamble clocks will be transmitted. All signals return to the idle state after the frame phase
is finished.
It is not possible to transmit in the SPI slave configuration because the FSI TXCLK cannot take an external
clock source.
6.15.8.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
Special timings are not required for the FSIRX in SPI signaling mode. FSIRX timings listed in the FSIRX Timing
Requirements table are applicable in SPI compatibility mode. Setup and Hold times are only valid on the falling
edge of FSIRXCLK because this is the active edge in SPI signaling mode.
6.15.8.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER(1)
MIN
16.67
MAX
UNIT
ns
1
2
3
4
5
tc(TXCLK)
Cycle time, TXCLK
tw(TXCLK)
Pulse width, TXCLK low or TXCLK high
Delay time, TXD0 valid after TXCLK high
Delay time, TXCLK high after TXD1 low
Delay time, TXD1 high after TXCLK low
(0.5tc(TXCLK)) – 1
(0.5tc(TXCLK)) + 1
3
ns
td(TXCLKH–TXD0)
td(TXD1-TXCLK)
td(TXCLK-TXD1)
ns
tw(TXCLK) – 3
tw(TXCLK)
ns
ns
(1) 10-pF load on pin
6.15.8.3.1.2 FSITX SPI Signaling Mode Timings
1
2
FSITXCLK
3
FSITXD0
5
4
FSITXD1
Figure 6-76. FSITX SPI Signaling Mode Timings
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 201
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.9 Host Interface Controller (HIC)
The HIC module allows an external host controller (master) to directly access resources of the device (slave)
by emulating the ASRAM protocol. It has two modes of operation: direct access and mailbox access. In direct
access mode, device resources is written to and read from directly by the external host. In mailbox access mode,
external host and device write to and read from a buffer and notify each other when the buffer write/read is
complete. For security reasons, the HIC has to be enabled by the device before the external host can access it.
Features of the HIC include:
•
•
•
•
•
•
•
•
•
Configurable I/O data lines of 8 bits and 16 bits
Direct and mailbox access modes
8 address lines and 8 configurable base addresses for a total of 2048 possible addressable regions
Two 64-byte buffers for external host and device when using mailbox access mode
Interrupt generation on buffer full/empty
High throughput
Trigger HIC activity from other peripherals
Error indicators to the system or interface
Commit feature that blocks writes to configuration registers
Legend
HIC Pins
HIC Registers
HIC
I/O Interface
A[7:0]
Bus Master Interface
A[31:0]
D[15:0]
nBE[1:0]
nCS
H2DINT to PIE
D2HINT to Pin
WDATA[31:0]
RDATA[31:0]
Memory Mapped HIC
Configuration Interface
Host
To
Device
Device
To
Host
CTRL Regs
STATUS Regs
nWE
BASE_ADDR0
BASE_ADDR1
nOE
.
.
Mailbox
Buffer
Mailbox
Buffer
BASESEL[2:0]
nRDY
BASE_ADDRn
EVT_TRIGGER[15:0]
Figure 6-77. HIC Block Diagram
Copyright © 2021 Texas Instruments Incorporated
202 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
6.15.9.1 HIC Electrical Data and Timing
6.15.9.1.1 HIC Timing Requirements
over operating free-air temperature range (unless otherwise noted)
MIN
MAX UNIT
Read/Write Parameters with nOE and nWE pins - Dual Read/Write pins
tsu(ABBV-OEV)
tsu(ABBV-WEV)
tsu(CSV-OEV)
tsu(CSV-WEV)
th(ABBV-OEIV)
th(ABBV-WEIV)
tw(OEV)
Setup time, A/BASESEL/nBE before nOE active
Setup time, A/BASESEL/nBE before nWE active
Setup time, nCS active before nOE active
Setup time, nCS active before nWE active
Hold time, A/BASESEL/nBE/nCS after nOE inactive
Hold time, A/BASESEL/nBE/nCS after nWE inactive
Active pulse width of nOE (Read)(1)
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0.5tc(SYSCLK)
0.5tc(SYSCLK)
6
6
4tc(SYSCLK)
4tc(SYSCLK)
3tc(SYSCLK)
3tc(SYSCLK)
3tc(SYSCLK)
0
tw(WEV)
Active pulse width of nWE (Write)
tw(CSIV)
Inactive pulse width of nCS(2)
tw(OEIV)
Inactive Read pulse width of nOE(2)
tw(WEIV)
Inactive Write pulse width of nWE(2)
tsu(DV-WEV)
th(DV-WEIV)
Setup time, D before nWE active
Hold time, D after nWE inactive
6
Read/Write Parameters with RnW pin - Single Read/Write pin
tsu(ABBV-CSV)
tsu(RNWV-CSV)
th(ABBV-CSIV)
tw(CSV_RD)
tw(CSV_WR)
tw(CSIV)
Setup time, A/BASESEL/nBE before nCS active
Setup time, RnW before nCS active
Hold time, A/BASESEL/nBE/RnW after nCS inactive
Active pulse width of nCS for read operation(1)
Active pulse width of nCS for write operation
Inactive pulse width of nCS(2)
0
0.5tc(SYSCLK)
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
4tc(SYSCLK)
4tc(SYSCLK)
3tc(SYSCLK)
3tc(SYSCLK)
0
tw(RNWIV)
Inactive pulse width of RnW(2)
tsu(DV-CSV)
th(DV-CSIV)
Setup time, D before nCS active
Hold time, D after nCS inactive
5
(1) For accesses to the device region, additional 2 SYSCLK cycles are required.
(2) For accesses to the device region with nRDY pin, additional SYSCLK cycle is required.
6.15.9.1.2 HIC Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
MIN
MAX UNIT
Read/Write Parameters with nOE and nWE pins
td(OEV-DV)
Output data delay time : nOE to D output valid (2)
Output data hold time : nOE invalid to D output invalid (tri-state)
Read Ready delay time : nOE to nRDY output valid
Write Ready delay time : nWE to nRDY output valid
Ready to Data delay time : nRDY output valid to D output valid
Active pulse width of nRDY output
3tc(SYSCLK)
4tc(SYSCLK) + 15 ns
2tc(SYSCLK) + 15 ns
12 ns
td(OEIV-DIV)
td(OEV-RDYV)
td(WEV-RDYV)
td(RDYV-DV)
tw(RDYACT)
1tc(SYSCLK)
0
0
-3
12 ns
3
ns
ns
2tc(SYSCLK)
Read/Write Parameters with RnW pin
td(CSV-DV)
Output delay time : nCS active to D output valid (2)
3tc(SYSCLK)
4tc(SYSCLK) + 14 ns
2tc(SYSCLK) + 14 ns
12 ns
td(CSIV-DIV)
td(CSV-RDYV)
td(RDYV-DV)
Output hold time : nCS inactive to D output invalid (tri-state)
Output delay time : nCS to nRDY output valid
1tc(SYSCLK)
0
Ready to Data delay time : nRDY output valid to D output valid
-3
3
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 203
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
6.15.9.1.2 HIC Switching Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)
MIN
MAX UNIT
tw(RDYACT)
Active pulse width of nRDY output
2tc(SYSCLK)
ns
(1) 10-pF load on pin.
(2) Applicable to mailbox accesses only. Direct memory map (Device) accesses are qualified with nRDY pin.
6.15.9.1.3 HIC Timing Diagrams
SETUP SIGNALS
T9
nCS
A[7:0]
BASESEL[2:0]
nBE[3:0]
READ SIGNALS
T1
T5
T3
T10
nOE
T7
S2
S1
T8
D[15:0]
7
WRITE SIGNALS
T6
T2
T4
T11
nWE
T12
T13
D[15:0]
READY/WAIT SIGNAL
S5
S6
S3
S4
nRDY
Figure 6-78. Read/Write Operation With nOE and nWE Pins
Copyright © 2021 Texas Instruments Incorporated
204 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
SETUP SIGNALS
T19
nCS
T17 or T18
T16
T14
T15
A[7:0]
BASESEL[2:0]
nBE[3:0]
READ SIGNALS
T20
RnW
(Read)
S8
S7
D[15:0]
S10
WRITE SIGNALS
T20
T15
T21
RnW
(Write)
T22
D[15:0]
nRDY
READY/WAIT SIGNAL
S9
S11
Figure 6-79. Read/Write Operation With RnW Pin
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 205
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7 Detailed Description
7.1 Overview
C2000™ 32-bit Real-Time microcontrollers are optimized for processing, sensing, and actuation to improve
closed-loop performance in real-time control applications such as industrial motor drives; solar inverters and
digital power; electrical vehicles and transportation; motor control; and sensing and signal processing.
The TMS320F28003x (F28003x) is a powerful 32-bit floating-point microcontroller unit (MCU) that lets designers
incorporate crucial control peripherals, differentiated analog, and nonvolatile memory on a single device.
The real-time control subsystem is based on TI’s 32-bit C28x CPU, which provides 120 MHz of signal processing
performance. The C28x CPU is further boosted by the FPU, new TMU extended instruction set, which enables
fast execution of algorithms with trigonometric operations commonly found in transforms and torque loop
calculations; and the VCRC extended instruction set, which reduces the latency for complex math operations
commonly found in encoded applications.
The CLA allows significant offloading of common tasks from the main C28x CPU. The CLA is an independent
32-bit floating-point math accelerator that executes in parallel with the CPU. Additionally, the CLA has its own
dedicated memory resources and it can directly access the key peripherals that are required in a typical control
system. Support of a subset of ANSI C is standard, as are key features like hardware breakpoints and hardware
task-switching.
The F28003x supports up to 384KB (192KW) of flash memory divided into three 128KB (64KW) banks, which
enable programming and execution in parallel. Up to 69KB (34.5KW) of on-chip SRAM is also available to
supplement the flash memory.
The Live Firmware Update hardware enhancements on F28003x allow fast context switching from the old
firmware to the new firmware to minimize application downtime when updating the device firmware.
High-performance analog blocks are integrated on the F28003x real-time MCU to further enable system
consolidation. Three separate 12-bit ADCs provide precise and efficient management of multiple analog signals,
which ultimately boosts system throughput. Four analog comparator modules provide continuous monitoring of
input voltage levels for trip conditions.
The TMS320C2000™ devices contain industry-leading control peripherals with frequency-independent ePWM/
HRPWM and eCAP allow for a best-in-class level of control to the system.
Connectivity is supported through various industry-standard communication ports (such as SPI, SCI, I2C,
PMBus, LIN, CAN and CAN FD) and offers multiple muxing options for optimal signal placement in a variety
of applications. New to the C2000™ platform is Host Interface Controller (HIC), a high throughput interface that
allows an external host to access resources of the TMS320F28003x. Additionally, in an industry first, the FSI
enables high-speed, robust communication to complement the rich set of peripherals that are embedded in the
device.
A specially enabled device variant, TMS320F28003xC, allows access to the Configurable Logic Block (CLB) for
additional interfacing features. See Table 4-1 for more information.
The Embedded Real-Time Analysis and Diagnostic (ERAD) module enhances the debug and system analysis
capabilities of the device by providing additional hardware breakpoints and counters for profiling.
To learn more about the C2000 real-time MCUs, visit the C2000™ real-time control MCUs page.
Copyright © 2021 Texas Instruments Incorporated
206 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.2 Functional Block Diagram
Figure 7-1 shows the CPU system and associated peripherals.
Buses Legend
CPU
CLA
DMA
HIC
BGCRC
C28x CPU
(120MHz)
FPU32
TMU
CLA
(120MHz)
VCRC
FINTDIV
SYSTEM CONTROL
CLA to CPU MSG RAM
CPU to CLA MSG RAM
CPU Timers
XTAL
INTOSC1, INTOSC2
PLL
Boot ROM
Secure ROM
Flash Bank0
16 Sectors, 64Kw(128KB)
Windowed WD
ePIE
CLA Data ROM
CLA Program ROM
NMI WD
Flash Bank1
16 Sectors, 64Kw(128KB)
SECURITY
DCSM
JTAG Lock
Secure Boot
CLA to DMA MSG RAM
DMA to CLA MSG RAM
Flash Bank2
16 Sectors, 64Kw(128KB)
M0-M1 RAM
2Kw(4KB)
DIAGNOSTICS
DCC
MPOST
HWBIST
ERAD
JTAG/cJTAG
BGCRC
HIC
LS0-LS7 RAM
16Kw(32KB)
GS0-GS3 RAM
16Kw(32KB)
DMA
6 Channels
OTHERS
EPG
PF10
PF11
PF12
LFU
PF1
PF3
PF4
PF2
PF7 PF7
PF8
PF9
2x LIN(A)
1x AES
1x PMBUS
2x SPI
1x FSI RX
1x FSI TX
2x SCI
2x I2C
4x CLB
Result
3x 12-Bit ADC
Data
55x GPIO
16x ePWM
(8 Hi-Res Capable)
1x
DCAN/ MCAN/
CAN CAN FD
1x
4x CMPSS
Input XBAR
Output XBAR
ePWM XBAR
CLB XBAR
3x eCAP
(1 HRCAP Capable)
2x Bu ered DAC
2x eQEP
(CW/CCW Support)
CLB Input XBAR
CLB Output XBAR
8x SD Filters
A. The LIN module can also work as an SCI.
Figure 7-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 207
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.3 Memory
7.3.1 Memory Map
The Memory Map table describes the memory map. See the Memory Controller Module section of the System
Control chapter in the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual.
Table 7-1. Memory Map
START
ADDRESS
END
ADDRESS
HIC
DMA
CLA
ECC/
ACCESS
MEMORY
SIZE
SECURITY
ACCESS ACCESS ACCESS
PARITY PROTECTION
M0 RAM
M1 RAM
1K x 16
1K x 16
512 x 16
512 x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
2K x 16
4K x 16
4K x 16
4K x 16
4K x 16
2K x 16
8K x 16
0x0000 0000
0x0000 0400
0x0000 0D00
0x0100 0900
0x0000 8000
0x0000 8800
0x0000 9000
0x0000 9800
0x0000 A000
0x0000 A800
0x0000 B000
0x0000 B800
0x0000 03FF
0x0000 07FF
0x0000 0EFF
0x0100 0AFF
0x0000 87FF
0x0000 8FFF
0x0000 97FF
0x0000 9FFF
0x0000 A7FF
0x0000 AFFF
0x0000 B7FF
0x0000 BFFF
-
-
-
ECC
ECC
-
Yes
Yes
-
-
-
-
-
-
PieVectTable
PieVectTable Swap
LS0 RAM
-
-
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
ECC
Parity
Parity
ECC
ECC
ECC
ECC
ECC
ECC
ECC
Parity
Parity
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
Yes
LS1 RAM
-
-
Yes
LS2 RAM
-
-
Yes
LS3 RAM
-
-
Yes
LS4 RAM
-
-
Yes
LS5 RAM
-
-
Yes
LS6 RAM
-
-
Yes
LS7 RAM
-
-
Yes
GS0 RAM
0x0000 C000 0x0000 CFFF
0x0000 D000 0x0000 DFFF
Yes
Yes
-
GS1 RAM
Yes
Yes
-
-
GS2 RAM
0x0000 E000
0x0000 F000
0x0004 9000
0x0005 8000
0x0000 1480
0x0000 1500
0x0000 1680
0x0000 1700
0x0007 0000
0x0007 8000
0x0000 EFFF
0x0000 FFFF
0x0004 97FF
0x0005 9FFF
0x0000 14FF
0x0000 157F
0x0000 16FF
0x0000 177F
0x0007 0BFF
0x0007 8BFF
0x000A FFFF
0x003F 7FFF
0x003F FFFF
Yes
Yes
-
-
GS3 RAM
Yes
Yes
-
-
CAN A Message RAM
MCAN Message RAM
Yes
Yes
-
-
Yes
-
-
-
-
CLA to CPU Message RAM 128 x 16
CPU to CLA Message RAM 128 x 16
CLA to DMA Message RAM 128 x 16
DMA to CLA Message RAM 128 x 16
TI OTP(1)
User OTP
Flash
-
-
-
-
-
-
-
-
-
-
Yes
Yes
Yes
Yes
-
-
-
-
-
-
-
Yes
-
Yes
-
-
3K x 16
3K x 16
-
-
-
-
-
-
Yes(2)
Yes(2)
Yes
Yes
-
-
-
192K x 16 0x0008 0000
-
-
Secure ROM
Boot ROM
24K x 16
32K x 16
0x003F 2000
0x003F 8000
-
-
-
-
Pie Vector Fetch Error (part
of Boot ROM)
1 x 16
0x003F FFBE 0x003F FFBF
0x003F FFC0 0x003F FFFF
-
-
-
-
-
-
Parity
Parity
-
-
-
-
Default Vectors (part of
Boot ROM)
64 x 16
(1) TI OTP is for TI internal use only.
(2) Only a subset is secure.
7.3.1.1 Dedicated RAM (Mx RAM)
The CPU subsystem has two dedicated ECC-capable RAM blocks: M0 and M1. These memories are small
nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them).
7.3.1.2 Local Shared RAM (LSx RAM)
Local shared RAMs (LSx RAMs) are accessible to the CPU, CLA, and BGCRC. All LSx RAM blocks have ECC.
These memories are secure and have CPU access protection (CPU write/CPU fetch).
Copyright © 2021 Texas Instruments Incorporated
208 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.3.1.3 Global Shared RAM (GSx RAM)
Global shared RAMs (GSx RAMs) are accessible from the CPU, HIC, BGCRC and DMA. The CPU, HIC, and
DMA have full read and write access to these memories. All GSx RAM blocks have ECC. The GSx RAMs have
access protection (CPU write/CPU fetch/DMA write/HIC write).
7.3.1.4 Message RAM
There are two types of message RAMs on this device that can be used to share between CPU, CLA and DMA.
CLA-CPU message RAM shares data between the CLA and CPU while the CLA-DMA message RAM shares
data between the CLA and DMA.
7.3.2 Control Law Accelerator (CLA) Memory Map
Table 7-2 shows the CLA data ROM memory map. For information about the CLA program ROM, see the
CLA Program ROM (CLAPROMCRC) chapter in the TMS320F28003x Real-Time Microcontrollers Technical
Reference Manual.
Table 7-2. CLA Data ROM Memory Map
MEMORY
FFT Tables (Load)
Data (Load)
START ADDRESS
0x0100 1070
0x0100 1870
0x0100 1FFA
0x0000 F070
0x0000 F870
0x0000 FFFA
END ADDRESS
0x0100 186F
0x0100 1FF9
0x0100 1FFF
0x0000 F86F
0x0000 FFF9
0x0000 FFFF
LENGTH
0x0800
0x078A
0x0006
0x0800
0x078A
0x0006
Version (Load)
FFT Tables (Run)
Data (Run)
Version (Run)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 209
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.3.3 Flash Memory Map
On the F28003x devices, three flash banks (384KB [192KW]) are available. Code to program the flash should
be executed out of RAM, there should not be any kind of access to the flash bank when an erase or program
operation is in progress. The Addresses of Flash Sectors table lists the addresses of flash sectors available for
each part number.
7.3.3.1 Addresses of Flash Sectors
Table 7-3. Addresses of Flash Sectors
ADDRESS
ECC ADDRESS
START
PART
NUMBER
SECTOR
SIZE
START
END
SIZE
END
OTP Sectors
TI OTP Bank 0
(Unsecure)
1008 x 16
0x0007 0000
0x0007 03EF
126 x 16
0x0107 0000
0x0107 007D
All F28003x
TI OTP Bank 0
(Secure)
16 x 16
1K x 16
1K x 16
0x0007 03F0
0x0007 0400
0x0007 0800
0x0007 03FF
0x0007 07FF
0x0007 0BFF
2 x 16
0x0107 007E
0x0107 0080
0x0107 0100
0x0107 007F
0x0107 00FF
0x0107 017F
TI OTP Bank 1
TI OTP Bank 2
128 x 16
128 x 16
F280039,
F280038
User
configurable
DCSM OTP
Bank 0
1K x 16
1K x 16
1K x 16
0x0007 8000
0x0007 8400
0x0007 8800
0x0007 83FF
0x0007 87FF
0x0007 8BFF
128 x 16
128 x 16
128 x 16
0x0107 1000
0x0107 1080
0x0107 1100
0x0107 107F
0x0107 10FF
0x0107 117F
All F28003x
User
configurable
DCSM OTP
Bank 1
User
F280039,
F280038
configurable
DCSM OTP
Bank 2
Bank 0 Sectors
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
Sector 14
Sector 15
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
0x0008 0000
0x0008 1000
0x0008 2000
0x0008 3000
0x0008 4000
0x0008 5000
0x0008 6000
0x0008 7000
0x0008 8000
0x0008 9000
0x0008 A000
0x0008 B000
0x0008 C000
0x0008 D000
0x0008 E000
0x0008 F000
0x0008 0FFF
0x0008 1FFF
0x0008 2FFF
0x0008 3FFF
0x0008 4FFF
0x0008 5FFF
0x0008 6FFF
0x0008 7FFF
0x0008 8FFF
0x0008 9FFF
0x0008 AFFF
0x0008 BFFF
0x0008 CFFF
0x0008 DFFF
0x0008 EFFF
0x0008 FFFF
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
0x0108 0000
0x0108 0200
0x0108 0400
0x0108 0600
0x0108 0800
0x0108 0A00
0x0108 0C00
0x0108 0E00
0x0108 1000
0x0108 1200
0x0108 1400
0x0108 1600
0x0108 1800
0x0108 1A00
0x0108 1C00
0x0108 1E00
0x0108 01FF
0x0108 03FF
0x0108 05FF
0x0108 07FF
0x0108 09FF
0x0108 0BFF
0x0108 0DFF
0x0108 0FFF
0x0108 11FF
0x0108 13FF
0x0108 15FF
0x0108 17FF
0x0108 19FF
0x0108 1BFF
0x0108 1DFF
0x0108 1FFF
F280039,
F280038,
F280037,
F280036
F280039,
F280038,
F280037,
F280036,
F280034,
F280033
Copyright © 2021 Texas Instruments Incorporated
210 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-3. Addresses of Flash Sectors (continued)
ADDRESS
ECC ADDRESS
START
PART
NUMBER
SECTOR
SIZE
START
END
SIZE
END
Bank 1 Sectors
Sector 0
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
0x0009 0000
0x0009 1000
0x0009 2000
0x0009 3000
0x0009 4000
0x0009 5000
0x0009 6000
0x0009 7000
0x0009 8000
0x0009 9000
0x0009 A000
0x0009 B000
0x0009 C000
0x0009 D000
0x0009 E000
0x0009 F000
0x0009 0FFF
0x0009 1FFF
0x0009 2FFF
0x0009 3FFF
0x0009 4FFF
0x0009 5FFF
0x0009 6FFF
0x0009 7FFF
0x0009 8FFF
0x0009 9FFF
0x0009 AFFF
0x0009 BFFF
0x0009 CFFF
0x0009 DFFF
0x0009 EFFF
0x0009 FFFF
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
0x0108 2000
0x0108 2200
0x0108 2400
0x0108 2600
0x0108 2800
0x0108 2A00
0x0108 2C00
0x0108 2E00
0x0108 3000
0x0108 3200
0x0108 3400
0x0108 3600
0x0108 3800
0x0108 3A00
0x0108 3C00
0x0108 3E00
0x0108 21FF
0x0108 23FF
0x0108 25FF
0x0108 27FF
0x0108 29FF
0x0108 2BFF
0x0108 2DFF
0x0108 2FFF
0x0108 31FF
0x0108 33FF
0x0108 35FF
0x0108 37FF
0x0108 39FF
0x0108 3BFF
0x0108 3DFF
0x0108 3FFF
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
Sector 14
Sector 15
F280039,
F280038,
F280037,
F280036,
F280034,
F280033
F280039,
F280038,
F280037,
F280036
Bank 2 Sectors
Sector 0
Sector 1
Sector 2
Sector 3
Sector 4
Sector 5
Sector 6
Sector 7
Sector 8
Sector 9
Sector 10
Sector 11
Sector 12
Sector 13
Sector 14
Sector 15
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
4K x 16
0x000A 0000
0x000A 1000
0x000A 2000
0x000A 3000
0x000A 4000
0x000A 5000
0x000A 6000
0x000A 7000
0x000A 8000
0x000A 9000
0x000A A000
0x000A B000
0x000A C000
0x000A D000
0x000A E000
0x000A F000
0x000A 0FFF
0x000A 1FFF
0x000A 2FFF
0x000A 3FFF
0x000A 4FFF
0x000A 5FFF
0x000A 6FFF
0x000A 7FFF
0x000A 8FFF
0x000A 9FFF
0x000A AFFF
0x000A BFFF
0x000A CFFF
0x000A DFFF
0x000A EFFF
0x000A FFFF
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
512 x 16
0x0108 4000
0x0108 4200
0x0108 4400
0x0108 4600
0x0108 4800
0x0108 4A00
0x0108 4C00
0x0108 4E00
0x0108 5000
0x0108 5200
0x0108 5400
0x0108 5600
0x0108 5800
0x0108 5A00
0x0108 5C00
0x0108 5E00
0x0108 41FF
0x0108 43FF
0x0108 45FF
0x0108 47FF
0x0108 49FF
0x0108 4BFF
0x0108 4DFF
0x0108 4FFF
0x0108 51FF
0x0108 53FF
0x0108 55FF
0x0108 57FF
0x0108 59FF
0x0108 5BFF
0x0108 5DFF
0x0108 5FFF
F280039,
F280038
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
211
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.3.4 Peripheral Registers Memory Map
The Peripheral Registers Memory Map (C28x) table lists the peripheral registers.
Table 7-4. Peripheral Registers Memory Map (C28)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
CLA
Access
DriverLib Name
Base Address
Instance
Structure
Peripheral Frame 0 (PF0)
-
-
-
M0_RAM_BASE
M1_RAM_BASE
0x0000_0000
0x0000_0400
0x0000_0B00
0x0000_0B20
0x0000_0B40
0x0000_0C00
0x0000_0C00
0x0000_0C08
0x0000_0C10
0x0000_0CE0
0x0000_0CE0
0x0000_0D00
0x0000_1000
0x0000_1020
0x0000_1040
0x0000_1060
0x0000_1080
0x0000_10A0
0x0000_10C0
0x0000_1400
0x0000_8000
0x0000_8800
0x0000_9000
0x0000_9800
0x0000_A000
0x0000_A800
0x0000_B000
0x0000_B800
0x0000_C000
0x0000_D000
0x0000_E000
0x0000_F000
0x0007_8000
0x0007_8200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AdcaResultRegs
ADC_RESULT_REGS
ADCARESULT_BASE
ADCBRESULT_BASE
ADCCRESULT_BASE
CPUTIMER0_BASE
CLA1_ONLY_BASE
CPUTIMER1_BASE
CPUTIMER2_BASE
PIECTRL_BASE
YES
YES
YES
AdcbResultRegs
ADC_RESULT_REGS
YES
YES
YES
AdccResultRegs
ADC_RESULT_REGS
YES
YES
YES
CpuTimer0Regs
CPUTIMER_REGS
-
-
-
Cla1OnlyRegs
CLA_ONLY_REGS
-
-
YES
CpuTimer1Regs
CPUTIMER_REGS
-
-
-
CpuTimer2Regs
CPUTIMER_REGS
-
-
-
PieCtrlRegs
PIE_CTRL_REGS
-
-
-
Cla1SoftIntRegs
CLA_SOFTINT_REGS
CLA1_SOFTINT_BASE
PIEVECTTABLE_BASE
DMA_BASE
-
-
YES
PieVectTable
PIE_VECT_TABLE
-
-
-
DmaRegs
DMA_REGS
-
-
-
Dmach1Regs
DMA_CH_REGS
DMA_CH1_BASE
DMA_CH2_BASE
DMA_CH3_BASE
DMA_CH4_BASE
DMA_CH5_BASE
DMA_CH6_BASE
CLA1_BASE
-
-
-
Dmach2Regs
DMA_CH_REGS
-
-
-
Dmach3Regs
DMA_CH_REGS
-
-
-
Dmach4Regs
DMA_CH_REGS
-
-
-
Dmach5Regs
DMA_CH_REGS
-
-
-
Dmach6Regs
DMA_CH_REGS
-
-
-
Cla1Regs
CLA_REGS
-
-
-
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
LS0_RAM_BASE
LS1_RAM_BASE
LS2_RAM_BASE
LS3_RAM_BASE
LS4_RAM_BASE
LS5_RAM_BASE
LS6_RAM_BASE
LS7_RAM_BASE
GS0_RAM_BASE
GS1_RAM_BASE
GS2_RAM_BASE
GS3_RAM_BASE
DCSM_Z1OTP_BASE
DCSM_Z2OTP_BASE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
YES
YES
YES
YES
-
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
DcsmZ1OtpRegs
DcsmZ2OtpRegs
DCSM_Z1_OTP
DCSM_Z2_OTP
-
-
-
-
Peripheral Frame 1 (PF1)
CLB_LOGIC_CONFIG_ CLB1_LOGICCFG_BAS
Clb1LogicCfgRegs
Clb1LogicCtrlRegs
Clb1DataExchRegs
Clb2LogicCfgRegs
Clb2LogicCtrlRegs
Clb2DataExchRegs
0x0000_3000
0x0000_3100
0x0000_3180
0x0000_3400
0x0000_3500
0x0000_3580
-
-
-
-
-
-
-
-
-
-
-
-
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
REGS
E
CLB_LOGIC_CONTROL CLB1_LOGICCTRL_BA
_REGS SE
CLB_DATA_EXCHANGE CLB1_DATAEXCH_BAS
_REGS
E
CLB_LOGIC_CONFIG_ CLB2_LOGICCFG_BAS
REGS
E
CLB_LOGIC_CONTROL CLB2_LOGICCTRL_BA
_REGS SE
CLB_DATA_EXCHANGE CLB2_DATAEXCH_BAS
_REGS
E
Copyright © 2021 Texas Instruments Incorporated
212 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-4. Peripheral Registers Memory Map (C28) (continued)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
CLA
Access
DriverLib Name
Base Address
Instance
Structure
CLB_LOGIC_CONFIG_ CLB3_LOGICCFG_BAS
Clb3LogicCfgRegs
Clb3LogicCtrlRegs
Clb3DataExchRegs
Clb4LogicCfgRegs
Clb4LogicCtrlRegs
Clb4DataExchRegs
0x0000_3800
0x0000_3900
0x0000_3980
0x0000_3C00
0x0000_3D00
0x0000_3D80
-
-
-
-
-
-
-
-
-
-
-
-
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
REGS
E
CLB_LOGIC_CONTROL CLB3_LOGICCTRL_BA
_REGS SE
CLB_DATA_EXCHANGE CLB3_DATAEXCH_BAS
_REGS
E
CLB_LOGIC_CONFIG_ CLB4_LOGICCFG_BAS
REGS
E
CLB_LOGIC_CONTROL CLB4_LOGICCTRL_BA
_REGS SE
CLB_DATA_EXCHANGE CLB4_DATAEXCH_BAS
_REGS
E
Peripheral Frame 10 (PF10)
WdRegs
WD_REGS
WD_BASE
0x0000_7000
0x0000_7060
YES
YES
-
-
-
-
-
-
NmiIntruptRegs
NMI_INTRUPT_REGS
NMI_BASE
Peripheral Frame 11 (PF11)
XintRegs
SciaRegs
ScibRegs
I2caRegs
I2cbRegs
XINT_REGS
SCI_REGS
SCI_REGS
I2C_REGS
I2C_REGS
XINT_BASE
SCIA_BASE
SCIB_BASE
I2CA_BASE
I2CB_BASE
0x0000_7070
0x0000_7200
0x0000_7210
0x0000_7300
0x0000_7340
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
YES
YES
YES
YES
Peripheral Frame 12 (PF12)
HwbistRegs
MpostRegs
Dcc0Regs
Dcc1Regs
HWBIST_REGS
MPOST_REGS
DCC_REGS
HWBIST_BASE
MPOST_BASE
DCC0_BASE
DCC1_BASE
0x0005_E000
0x0005_E200
0x0005_E700
0x0005_E740
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
DCC_REGS
Peripheral Frame 2 (PF2)
EPwm1Regs
EPwm2Regs
EPwm3Regs
EPwm4Regs
EPwm5Regs
EPwm6Regs
EPwm7Regs
EPwm8Regs
EQep1Regs
EQep2Regs
ECap1Regs
ECap2Regs
ECap3Regs
HRCap3Regs
DacaRegs
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EPWM_REGS
EQEP_REGS
EQEP_REGS
ECAP_REGS
ECAP_REGS
ECAP_REGS
HRCAP_REGS
DAC_REGS
EPWM1_BASE
EPWM2_BASE
EPWM3_BASE
EPWM4_BASE
EPWM5_BASE
EPWM6_BASE
EPWM7_BASE
EPWM8_BASE
EQEP1_BASE
EQEP2_BASE
ECAP1_BASE
ECAP2_BASE
ECAP3_BASE
HRCAP3_BASE
DACA_BASE
0x0000_4000
0x0000_4100
0x0000_4200
0x0000_4300
0x0000_4400
0x0000_4500
0x0000_4600
0x0000_4700
0x0000_5100
0x0000_5140
0x0000_5200
0x0000_5240
0x0000_5280
0x0000_52A0
0x0000_5C00
0x0000_5C10
0x0000_5C80
0x0000_5CA0
0x0000_5CC0
0x0000_5CE0
0x0000_5E00
0x0000_5E80
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
DacbRegs
DAC_REGS
DACB_BASE
Cmpss1Regs
Cmpss2Regs
Cmpss3Regs
Cmpss4Regs
Sdfm1Regs
Sdfm2Regs
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
CMPSS_REGS
SDFM_REGS
SDFM_REGS
CMPSS1_BASE
CMPSS2_BASE
CMPSS3_BASE
CMPSS4_BASE
SDFM1_BASE
SDFM2_BASE
Peripheral Frame 3 (PF3)
SpiaRegs
SPI_REGS
SPIA_BASE
0x0000_6100
YES
YES
YES
YES
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 213
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 7-4. Peripheral Registers Memory Map (C28) (continued)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
CLA
Access
DriverLib Name
Base Address
Instance
SpibRegs
Structure
SPI_REGS
SPIB_BASE
BGCRC_CPU_BASE
BGCRC_CLA1_BASE
PMBUSA_BASE
HIC_BASE
0x0000_6110
0x0000_6340
0x0000_6380
0x0000_6400
0x0000_6500
0x0000_6600
0x0000_6680
YES
YES
YES
YES
YES
YES
YES
YES
-
YES
-
YES
-
BgcrcCpuRegs
BgcrcCla1Regs
PmbusaRegs
HicRegs
BGCRC_REGS
BGCRC_REGS
PMBUS_REGS
HIC_CFG_REGS
FSI_TX_REGS
FSI_RX_REGS
-
-
YES
YES
-
YES
YES
YES
YES
YES
-
FsiTxaRegs
FsiRxaRegs
FSITXA_BASE
YES
YES
YES
YES
FSIRXA_BASE
Peripheral Frame 4 (PF4)
AdcaRegs
AdcbRegs
AdccRegs
ADC_REGS
ADC_REGS
ADC_REGS
ADCA_BASE
ADCB_BASE
ADCC_BASE
0x0000_7400
0x0000_7480
0x0000_7500
YES
YES
YES
-
-
-
-
-
-
YES
YES
YES
Peripheral Frame 5 (PF5)
InputXbarRegs
XbarRegs
INPUT_XBAR_REGS
XBAR_REGS
INPUTXBAR_BASE
XBAR_BASE
0x0000_7900
0x0000_7920
0x0000_7940
0x0000_7960
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
SyncSocRegs
ClbInputXbarRegs
SYNC_SOC_REGS
INPUT_XBAR_REGS
SYNCSOC_BASE
CLBINPUTXBAR_BASE
DMA_CLA_SRC_SEL_R DMACLASRCSEL_BAS
DmaClaSrcSelRegs
0x0000_7980
YES
-
-
-
EGS
E
EPwmXbarRegs
ClbXbarRegs
EPWM_XBAR_REGS
CLB_XBAR_REGS
EPWMXBAR_BASE
CLBXBAR_BASE
0x0000_7A00
0x0000_7A40
0x0000_7A80
YES
YES
YES
-
-
-
-
-
-
-
-
-
OutputXbarRegs
OUTPUT_XBAR_REGS OUTPUTXBAR_BASE
CLBOUTPUTXBAR_BA
ClbOutputXbarRegs
OUTPUT_XBAR_REGS
SE
0x0000_7BC0
YES
-
-
-
GpioCtrlRegs
GpioDataRegs
GPIO_CTRL_REGS
GPIO_DATA_REGS
GPIOCTRL_BASE
GPIODATA_BASE
0x0000_7C00
0x0000_7F00
YES
YES
-
-
-
-
-
YES
GPIO_DATA_READ_RE
GS
GpioDataReadRegs
GPIODATAREAD_BASE
0x0000_7F80
YES
-
YES
YES
ClkCfgRegs
CLK_CFG_REGS
CPU_SYS_REGS
CLKCFG_BASE
CPUSYS_BASE
SYSSTAT_BASE
PERIPHAC_BASE
0x0005_D200
0x0005_D300
0x0005_D400
0x0005_D500
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
CpuSysRegs
SysStatusRegs
PeriphAcRegs
SYS_STATUS_REGS
PERIPH_AC_REGS
ANALOG_SUBSYS_RE ANALOGSUBSYS_BAS
AnalogSubsysRegs
0x0005_D700
YES
-
-
-
GS
E
Peripheral Frame 6 (PF6)
DevCfgRegs
DEV_CFG_REGS
DEVCFG_BASE
0x0005_D000
0x0005_E800
0x0005_E900
0x0005_E908
0x0005_E910
0x0005_E918
0x0005_E920
0x0005_E928
0x0005_E930
0x0005_E938
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EradGlobalRegs
EradHWBP1Regs
EradHWBP2Regs
EradHWBP3Regs
EradHWBP4Regs
EradHWBP5Regs
EradHWBP6Regs
EradHWBP7Regs
EradHWBP8Regs
ERAD_GLOBAL_REGS ERAD_GLOBAL_BASE
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP_REGS
ERAD_HWBP1_BASE
ERAD_HWBP2_BASE
ERAD_HWBP3_BASE
ERAD_HWBP4_BASE
ERAD_HWBP5_BASE
ERAD_HWBP6_BASE
ERAD_HWBP7_BASE
ERAD_HWBP8_BASE
ERAD_COUNTER_REG ERAD_COUNTER1_BA
SE
EradCounter1Regs
EradCounter2Regs
EradCounter3Regs
EradCounter4Regs
0x0005_E980
0x0005_E990
0x0005_E9A0
0x0005_E9B0
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
S
ERAD_COUNTER_REG ERAD_COUNTER2_BA
SE
S
ERAD_COUNTER_REG ERAD_COUNTER3_BA
SE
S
ERAD_COUNTER_REG ERAD_COUNTER4_BA
SE
S
Copyright © 2021 Texas Instruments Incorporated
214 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-4. Peripheral Registers Memory Map (C28) (continued)
Bit Field Name
Pipeline
Protected
DMA
Access
HIC
Access
CLA
Access
DriverLib Name
Base Address
Instance
Structure
ERAD_CRC_GLOBAL_ ERAD_CRC_GLOBAL_
EradCRCGlobalRegs
0x0005_EA00
YES
-
-
-
REGS
BASE
EradCRC1Regs
EradCRC2Regs
EradCRC3Regs
EradCRC4Regs
EradCRC5Regs
EradCRC6Regs
EradCRC7Regs
EradCRC8Regs
Epg1Regs
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
ERAD_CRC_REGS
EPG_REGS
ERAD_CRC1_BASE
ERAD_CRC2_BASE
ERAD_CRC3_BASE
ERAD_CRC4_BASE
ERAD_CRC5_BASE
ERAD_CRC6_BASE
ERAD_CRC7_BASE
ERAD_CRC8_BASE
EPG1_BASE
0x0005_EA10
0x0005_EA20
0x0005_EA30
0x0005_EA40
0x0005_EA50
0x0005_EA60
0x0005_EA70
0x0005_EA80
0x0005_EC00
0x0005_ECD0
0x0005_F000
0x0005_F080
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Epg1MuxRegs
DcsmZ1Regs
EPG_MUX_REGS
DCSM_Z1_REGS
DCSM_Z2_REGS
EPG1MUX_BASE
DCSM_Z1_BASE
DCSM_Z2_BASE
DcsmZ2Regs
DCSM_COMMON_REG
S
DcsmCommonRegs
MemCfgRegs
DCSMCOMMON_BASE
MEMCFG_BASE
0x0005_F0C0
0x0005_F400
0x0005_F500
YES
YES
YES
-
-
-
-
-
-
-
-
-
MEM_CFG_REGS
ACCESS_PROTECTION ACCESSPROTECTION_
_REGS BASE
AccessProtectionRegs
MEMORY_ERROR_RE MEMORYERROR_BAS
MemoryErrorRegs
0x0005_F540
YES
-
-
-
GS
E
TestErrorRegs
Flash0CtrlRegs
Flash0EccRegs
TEST_ERROR_REGS
FLASH_CTRL_REGS
FLASH_ECC_REGS
TESTERROR_BASE
FLASH0CTRL_BASE
FLASH0ECC_BASE
0x0005_F590
0x0005_F800
0x0005_FB00
YES
YES
YES
-
-
-
-
-
-
-
-
-
Peripheral Frame 7 (PF7)
CanaRegs
-
CAN_REGS
-
CANA_BASE
0x0004_8000
0x0004_9000
YES
YES
YES
YES
YES
YES
-
-
CANA_MSG_RAM_BAS
E
MCAN_MSG_RAM_BAS
E
-
-
0x0005_8000
YES
-
YES
-
McanaSsRegs
McanaRegs
MCANASS_REGS
MCANA_REGS
MCANASS_BASE
MCANA_BASE
0x0005_C400
0x0005_C600
0x0005_C800
YES
YES
YES
-
-
-
YES
YES
YES
-
-
-
McanaErrorRegs
MCANA_ERROR_REGS MCANA_ERROR_BASE
Peripheral Frame 8 (PF8)
LinaRegs
LinbRegs
LIN_REGS
LIN_REGS
LINA_BASE
LINB_BASE
0x0000_6A00
0x0000_6B00
YES
YES
YES
YES
YES
YES
YES
YES
ꢀ
LfuRegs
LFU_REGS
AES_IP_REGS
LFU_BASE
AESA_BASE
0x0000_7FE0
0x0004_2000
0x0004_2C00
YES
-
-
-
-
YES
AesaRegs
AesaSsRegs
-
-
YES
YES
-
-
AES_WRAPPER_REGS
AESA_SS_BASE
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 215
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.4 Identification
Table 7-5 lists the Device Identification Registers. Additional information on these device identification registers
can be found in the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual.
Table 7-5. Device Identification Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
Device part identification number
TMS320F280039C
TMS320F280039
TMS320F280038C
TMS320F280038
TMS320F280037C
TMS320F280037
TMS320F280036C
TMS320F280036
TMS320F280034
TMS320F280033
Silicon revision number
Revision 0
0x05FF 0500
0x05FF 0500
0x05FE 0500
0x05FE 0500
0x05FD 0500
0x05FD 0500
0x05FC 0500
0x05FC 0500
0x05FA 0500
0x05F9 0500
PARTIDH
0x0005 D00A
2
REVID
0x0005 D00C
0x0007 01F4
2
2
0x0000 0000
Unique identification number. This number is different on each
individual device with the same PARTIDH. This unique number
can be used as a serial number in the application. This number
is present only on TMS devices.
UID_UNIQUE
Copyright © 2021 Texas Instruments Incorporated
216 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.5 Bus Architecture – Peripheral Connectivity
The Peripheral Connectivity table lists a broad view of the peripheral and configuration register accessibility from
each bus master.
Table 7-6. Peripheral Connectivity
PERIPHERAL
DMA
HIC
BGCRC
CLA
C28
SYSTEM PERIPHERALS
CPU Timers
ERAD
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
GPIO Data
Y
Y
GPIO Pin Mapping and Configuration
XBAR Configuration
System Configuration
AES
EPG
LFU
DCC
Y
Y
Y
MEMORY
M0/M1
LSx
Y
Y
Y
Y
Y
Y
Y
Y
Y
GSx
Y
Y
ROM
FLASH
CONTROL PERIPHERALS
ePWM/HRPWM
eCAP/HRCAP
eQEP(1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
CLB
SDFM
Y
ANALOG PERIPHERALS
CMPSS(1)
DAC(1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
ADC Configuration
ADC Results(1)
Y
Y
COMMUNICATION PERIPHERALS
DCAN
MCAN
FSITX/FSIRX
I2C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
LIN
Y
Y
Y
Y
PMBus
SCI
SPI
Y
Y
(1) These modules are accessible from DMA but cannot trigger a DMA transfer.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 217
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.6 C28x Processor
The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing;
reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets.
The CPU features include a modified Harvard architecture and circular addressing. The RISC features
are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture. The
microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking,
and bit manipulation. The modified Harvard architecture of the CPU enables instruction and data fetches to be
performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the
single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.
For more information on CPU architecture and instruction set, see the TMS320C28x CPU and Instruction Set
Reference Guide.
7.6.1 Floating-Point Unit (FPU)
The C28x plus floating-point (C28x+FPU) processor extends the capabilities of the C28x fixed-point CPU by
adding registers and instructions to support IEEE single-precision floating-point operations.
Devices with the C28x+FPU include the standard C28x register set plus an additional set of floating-point unit
registers. The additional floating-point unit registers are the following:
•
•
•
Eight floating-point result registers, RnH (where n = 0–7)
Floating-point Status Register (STF)
Repeat Block Register (RB)
All of the floating-point registers, except the RB, are shadowed. This shadowing can be used in high-priority
interrupts for fast context save and restore of the floating-point registers.
For more information on the C28x Floating Point Unit (FPU), see the TMS320C28x Extended Instruction Sets
Technical Reference Manual.
7.6.2 Fast Integer Division Unit
The Fast Integer Division (FINTDIV) unit of the C28x CPU uniquely supports three types of integer division
(Truncated, Modulus, Euclidean) of varying data type sizes (16/16, 32/16, 32/32, 64/32, 64/64) in unsigned or
signed formats.
•
•
Truncated integer division is naturally supported by C language (/, % operators).
Modulus and Euclidean divisions are variants that are more efficient for control algorithms and are supported
by C intrinsics.
All three types of integer division produce both a quotient and remainder component, are interruptible, and
execute in a minimum number of deterministic cycles (10 cycles for a 32/32 division). In addition, the Fast
Division capabilities of the C28x CPU uniquely support fast execution of floating-point 32-bit (in 5 cycles) and
64-bit (in 20 cycles) division.
For more information about fast integer division, see the Fast Integer Division – A Differentiated Offering From
C2000™ Product Family Application Report.
7.6.3 Trigonometric Math Unit (TMU)
The trigonometric math unit (TMU) extends the capabilities of a C28x+FPU by adding instructions and
leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic
operations listed in Table 7-7.
Table 7-7. TMU Supported Instructions
Instructions
C Equivalent Operation
Pipeline Cycles
MPY2PIF32 RaH,RbH
DIV2PIF32 RaH,RbH
DIVF32 RaH,RbH,RcH
SQRTF32 RaH,RbH
a = b * 2pi
2/3
2/3
5
a = b / 2pi
a = b/c
a = sqrt(b)
5
Copyright © 2021 Texas Instruments Incorporated
218 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-7. TMU Supported Instructions (continued)
Instructions
C Equivalent Operation
Pipeline Cycles
SINPUF32 RaH,RbH
COSPUF32 RaH,RbH
ATANPUF32 RaH,RbH
QUADF32 RaH,RbH,RcH,RdH
a = sin(b*2pi)
4
4
4
5
a = cos(b*2pi)
a = atan(b)/2pi
Operation to assist in calculating ATANPU2
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions
use the existing FPU register set (R0H to R7H) to carry out their operations.
For more information, see the TMS320C28x Extended Instruction Sets Technical Reference Manual.
7.6.4 VCRC Unit
Cyclic redundancy check (CRC) algorithms provide a straightforward method for verifying data integrity over
large data blocks, communication packets, or code sections. The C28x+VCRC can perform 8-bit, 16-bit, 24-bit,
and 32-bit CRCs. For example, the VCRC can compute the CRC for a block length of 10 bytes in 10 cycles. A
CRC result register contains the current CRC, which is updated whenever a CRC instruction is executed.
The following are the CRC polynomials used by the CRC calculation logic of the VCRC:
•
•
•
•
•
•
CRC8 polynomial = 0x07
CRC16 polynomial 1 = 0x8005
CRC16 polynomial 2 = 0x1021
CRC24 polynomial = 0x5d6dcb
CRC32 polynomial 1 = 0x04c11db7
CRC32 polynomial 2 = 0x1edc6f41
This module can calculate CRCs for a byte of data in a single cycle. The CRC calculation for CRC8, CRC16,
CRC24, and CRC32 is done byte-wise (instead of computing on a complete 16-bit or 32-bit data read by the
C28x core) to match the byte-wise computation requirement mandated by various standards.
The VCRC Unit also allows the user to provide the size (1b-32b) and value of any polynomial to fit custom CRC
requirements. The CRC execution time increases to three cycles when using a custom polynomial.
For more information on the Cyclic Redundancy Check (VCRC) instruction sets, see the TMS320C28x Extended
Instruction Sets Technical Reference Manual.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 219
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.7 Control Law Accelerator (CLA)
The CLA Type-2 is an independent, fully programmable, 32-bit floating-point math processor that brings
concurrent control-loop execution to the C28x family. The low interrupt-latency of the CLA allows it to read
ADC samples "just-in-time." This significantly reduces the ADC sample to output delay to enable faster system
response and higher MHz control loops. By using the CLA to service time-critical control loops, the main CPU is
free to perform other system tasks such as communications and diagnostics.
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-critical
control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster
system response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main
CPU to perform other system and communication functions concurrently.
The following is a list of major features of the CLA:
•
•
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
•
•
Program Address Bus (PAB) and Program Data Bus (PDB)
Data Read Address Bus (DRAB), Data Read Data Bus (DRDB), Data Write Address Bus (DWAB), and
Data Write Data Bus (DWDB)
– Independent 8-stage pipeline.
– 16-bit program counter (MPC)
– Four 32-bit result registers (MR0 to MR3)
– Two 16-bit auxiliary registers (MAR0, MAR1)
– Status register (MSTF)
•
•
Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions
– Conditional branch and call
– Data load/store operations
The CLA program code can consist of up to eight tasks or interrupt service routines, or seven tasks and a
main background task.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the configurable CLA program memory space.
– One task is serviced at a time until its completion. There is no nesting of tasks.
– Upon task completion a task-specific interrupt is flagged within the PIE.
– When a task finishes the next highest-priority pending task is automatically started.
– The Type-2 CLA can have a main task that runs continuously in the background, while other high-priority
events trigger a foreground task.
•
•
Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task8: up to 256 possible trigger sources from peripherals connected to the shared bus on which
the CLA assumes secondary ownership.
– Task8 can be set to be the background task, while Tasks 1 to 7 take peripheral triggers.
Memory and Shared Peripherals:
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
Copyright © 2021 Texas Instruments Incorporated
220 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
CLA Control
Register Set
MIFR(16)
MIOVF(16)
MPERINT1
to
MPERINT8
CLA_INT1
to
CLA_INT8
From Shared
Peripherals
MICLR(16)
MICLROVF(16)
MIFRC(16)
C28x
CPU
PIE
INT11
INT12
MIER(16)
MIRUN(16)
LVF
LUF
MCTLBGRND(16)
MSTSBGRND(16)
CLA1SOFTINTEN(16)
CLA1INTFRC(16)
SYSCLK
CLA Clock Enable
SYSRS
MVECT1(16)
MVECT2(16)
MVECT3(16)
MVECT4(16)
MVECT5(16)
MVECT6(16)
MVECT7(16)
MVECT8(16)
CPU Read/Write Data Bus
CLA Program
Memory (LSx)
CLA Program Bus
LSxMSEL[MSEL_LSx]
LSxCLAPGM[CLAPGM_LSx]
MVECTBGRND(16)
MVECTBGRNDACTIVE(16)
MPSACTL(16)
MPSA1(32)
CLA Data
Memory (LSx)
MPSA2(32)
MCTL(16)
CLA Message
RAMs
CLA Execution
Register Set
MPC(16)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
Shared
Peripherals
MEALLOW
MAR0(16)
MAR1(16)
CPU Read Data Bus
Figure 7-2. CLA Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 221
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.8 Embedded Real-Time Analysis and Diagnostic (ERAD)
The ERAD module enhances the debug and system-analysis capabilities of the device. The debug and system-
analysis enhancements provided by the ERAD module is done outside of the CPU. The ERAD module consists
of the Enhanced Bus Comparator units and the System Event Counter units. The Enhanced Bus Comparator
units are used to generate hardware breakpoints, hardware watch points, and other output events. The System
Event Counter units are used to analyze and profile the system. The ERAD module is accessible by the
debugger and by the application software, which significantly increases the debug capabilities of many real-time
systems, especially in situations where debuggers are not connected. In the TMS320F28003x devices, the
ERAD module contains eight Enhanced Bus Comparator units (which increases the number of Hardware
breakpoints from two to ten) and four Benchmark System Event Counter units.
7.9 Background CRC-32 (BGCRC)
The Background CRC (BGCRC) module computes a CRC-32 on a configurable block of memory. It
accomplishes this by fetching the specified block of memory during idle cycles (when the CPU, HIC, CLA or
DMA is not accessing the memory block). The calculated CRC-32 value is compared against a golden CRC-32
value to indicate a pass or fail. In essence, the BGCRC helps identify memory faults and corruption.
The BGCRC module has the following features:
•
•
•
•
•
•
One cycle CRC-32 computation on 32 bits of data
No CPU bandwidth impact for zero wait state memory
Minimal CPU bandwidth impact for non-zero wait state memory
Dual operation modes (CRC-32 mode and scrub mode)
Watchdog timer to time CRC-32 completion
Ability to pause and resume CRC-32 computation
Copyright © 2021 Texas Instruments Incorporated
222 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.10 Direct Memory Access (DMA)
The DMA module provides a hardware method of transferring data between peripherals and/or memory without
intervention from the CPU, thereby freeing up bandwidth for other system functions. Additionally, the DMA has
the capability to orthogonally rearrange the data as it is transferred as well as “ping-pong” data between buffers.
These features are useful for structuring data into blocks for optimal CPU processing. Figure 7-3 shows a
device-level block diagram of the DMA.
DMA features include:
•
•
Six channels with independent PIE interrupts
Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– External Interrupts
– ePWM SOC signals
– CPU timers
– eCAP
– SPI transmit and receive
– CAN transmit and receive
– LIN transmit and receive
•
Data sources and destinations:
– GSx RAM
– ADC result registers
– Control peripheral registers (ePWM, eQEP, eCAP)
– SPI, LIN, CAN, and PMBus registers
Word Size: 16-bit or 32-bit (SPI limited to 16-bit)
Throughput: Four cycles per word without arbitration
•
•
ADC
WRAPPER
ADC
RESULTS
XINT
TIMER
Global Shared RAM
DCAN
LIN
AES
DMA bus
C28x bus
TINT (0-2)
XINT(1-5)
ADCx.INT(1-5), ADCx.EVT
AESA_ContextIn, AESA_ContextOut, AESA_DataIn, AESA_DataOut
LINxTXDMA, LINxRXDMA
CANxIF(1-3)
C28x
PIE
DMA Trigger
Source Selection
SDxDRINT1-4
ECAP(1-3)DMA
DMACHSRCSEL1.CHx
DMACHSRCSEL2.CHx
CHx.MODE.PERINTSEL
(x = 1 to 6)
DMA
EPWM(1-8).SOCA, EPWM(1-8.SOCB
CLB1-4INT
EPG1INT
SPITXDMA(A-B)
SPIRXDMA(A-B)
HICA_INT
FSITXADMA, FSIRXADMA
FSI_DATA_TAG_MATCH,
FSI_PING_TAG_MATCH
PM
Bus
FSI
HIC
CMPSS
eQEP
eCAP
EPWM
EPG
CLB
SPI
DAC
SDFM
Figure 7-3. DMA Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 223
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.11 Device Boot Modes
This section explains the default boot modes, as well as all the available boot modes supported on this device.
The boot ROM uses the boot mode select, general-purpose input/output (GPIO) pins to determine the boot
mode configuration.
Table 7-8 shows the boot mode options available for selection by the default boot mode select pins. Users have
the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot
mode select pin GPIOs used.
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA,
I2CA, CANA, and so forth). Whenever these boot modes are referred to in this chapter, such as SCI boot, it is
actually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies to
the other peripheral boots.
See Section 6.12.2.2.2 and the Power-on Reset figure for tboot-flash, the boot ROM execution time to first
instruction fetch in flash.
Table 7-8. Device Default Boot Modes
GPIO24
GPIO32
BOOT MODE
(DEFAULT BOOT MODE SELECT PIN 1)
(DEFAULT BOOT MODE SELECT PIN 0)
Parallel IO
SCI / Wait Boot(1)
CAN
0
0
1
1
0
1
0
1
Flash
(1) SCI boot mode can be used as a wait boot mode as long as SCI continues to wait for an 'A' or 'a' during the SCI autobaud lock
process.
Copyright © 2021 Texas Instruments Incorporated
224 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.11.1 Device Boot Configurations
This section details what boot configurations are available and how to configure them. This device supports
from 0 boot mode select pins up to 3 boot mode select pins as well as from 1 configured boot mode up to 8
configured boot modes.
To change and configure the device from the default settings to custom settings for your application, use the
following process:
1. Determine all the various ways you want application to be able to boot. (For example: Primary boot option of
Flash boot for your main application, secondary boot option of CAN boot for firmware updates, tertiary boot
option of SCI boot for debugging, etc)
2. Based on the number of boot modes needed, determine how many boot mode select pins (BMSPs) are
required to select between your selected boot modes. (For example: 2 BMSPs are required to select
between 3 boot mode options)
3. Assign the required BMSPs to a physical GPIO pin. (For example, BMSP0 to GPIO10, BMSP1 to GPIO51,
and BMSP2 left as default which is disabled). Refer to Section 7.11.1.1 for all the details on performing these
configurations.
4. Assign the determined boot mode definitions to indexes in your custom boot table that correlate to
the decoded value of the BMSPs. For example, BOOTDEF0=Boot to Flash, BOOTDEF1=CAN Boot,
BOOTDEF2=SCI Boot; all other BOOTDEFx are left as default/nothing). Refer to Section 7.11.1.2 for all
the details on setting up and configuring the custom boot mode table.
Additionally, the Boot Mode Example Use Cases section of the TMS320F28003x Real-Time Microcontrollers
Technical Reference Manual provides some example use cases on how to configure the BMSPs and custom
boot tables.
Note
The CAN boot mode turns on the XTAL. Be sure an XTAL is installed in the application before using
CAN boot mode.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 225
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.11.1.1 Configuring Boot Mode Pins
This section explains how the boot mode select pins can be customized by the user, by programming
the BOOTPIN-CONFIG location (refer to Table 7-9) in the user-configurable dual-zone security module
(DCSM) OTP. The location in the DCSM OTP is Z1-OTP-BOOTPIN-CONFIG or Z2-OTP-BOOTPIN-CONFIG.
When debugging, EMU-BOOTPIN-CONFIG is the emulation equivalent of Z1-OTP-BOOTPIN-CONFIG/Z2-OTP-
BOOTPIN-CONFIG, and can be programmed to experiment with different boot modes without writing to OTP.
The device can be programmed to use 0, 1, 2, or 3 boot mode select pins as needed.
Note
When using Z2-OTP-BOOTPIN-CONFIG, the configurations programmed in this location will take
priority over the configurations in Z1-OTP-BOOTPIN-CONFIG. It is recommended to use Z1-OTP-
BOOTPIN-CONFIG first and then if OTP configurations need to be altered, switch to using Z2-OTP-
BOOTPIN-CONFIG.
Table 7-9. BOOTPIN-CONFIG Bit Fields
BIT
31:24
23:16
15:8
NAME
DESCRIPTION
Key
Write 0x5A to these 8-bits to indicate the bits in this register are valid
Refer to BMSP0 description except for BMSP2
Refer to BMSP0 description except for BMSP1
Boot Mode Select Pin 2 (BMSP2)
Boot Mode Select Pin 1 (BMSP1)
Set to the GPIO pin to be used during boot (up to 255):
- 0x0 = GPIO0
- 0x01 = GPIO1
7:0
Boot Mode Select Pin 0 (BMSP0)
- and so on
Writing 0xFF disables BMSP0 and this pin is no longer used to select
the boot mode.
The following GPIOs cannot be used as a BMSP. If selected for a particular BMSP, the boot ROM automatically
selects the factory default GPIO (the factory default for BMSP2 is 0xFF, which disables the BMSP).
•
•
•
GPIO 20 and GPIO 21
GPIO 36 and GPIO 38
GPIO 62 to GPIO 223
Copyright © 2021 Texas Instruments Incorporated
226 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-10. Standalone Boot Mode Select Pin Decoding
BOOTPIN_CONFIG
BMSP0
BMSP1
BMSP2
REALIZED BOOT MODE
KEY
!= 0x5A
Don’t Care
Don’t Care
Don’t Care
Boot as defined by the factory default BMSPs
Boot as defined in the boot table for boot mode
0xFF
0xFF
0xFF
0
(All BMSPs disabled)
Boot as defined by the value of BMSP0
(BMSP1 and BMSP2 disabled)
Valid GPIO
0xFF
0xFF
Valid GPIO
0xFF
0xFF
0xFF
Boot as defined by the value of BMSP1
(BMSP0 and BMSP2 disabled)
Boot as defined by the value of BMSP2
(BMSP0 and BMSP1 disabled)
0xFF
Valid GPIO
Boot as defined by the values of BMSP0 and
Valid GPIO
Valid GPIO
Valid GPIO
0xFF
0xFF
BMSP1
(BMSP2 disabled)
Boot as defined by the values of BMSP0 and
BMSP2
Valid GPIO
(BMSP1 disabled)
Boot as defined by the values of BMSP1 and
= 0x5A
0xFF
Valid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
BMSP2
(BMSP0 disabled)
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
Valid GPIO
BMSP0 is reset to the factory default BMSP0
GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
Invalid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
Invalid GPIO
Valid GPIO
Valid GPIO
Valid GPIO
Invalid GPIO
BMSP1 is reset to the factory default BMSP1
GPIO
Boot as defined by the values of BMSP0,
BMSP1, and BMSP2
BMSP2 is reset to the factory default state,
which is disabled
Boot as defined by the values of BMSP0 and
BMSP1
Note
When decoding the boot mode, BMSP0 is the least-significant-bit and BMSP2 is the most-significant-
bit of the boot table index value. It is recommended when disabling BMSPs to start with disabling
BMSP2. For example, in an instance when only using BMSP2 (BMSP1 and BMSP0 are disabled),
then only the boot table indexes of 0 and 4 will be selectable. In the instance when using only BMSP0,
then the selectable boot table indexes are 0 and 1.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 227
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.11.1.2 Configuring Boot Mode Table Options
This section explains how to configure the boot definition table, BOOTDEF, for the device and the associated
boot options. The 64-bit location is located in user-configurable DCSM OTP in the Z1-OTP-BOOTDEF-LOW and
Z1-OTP-BOOTDEF-HIGH locations. When debugging, EMU-BOOTDEF-LOW and EMU-BOOTDEF-HIGH are
the emulation equivalents of Z1-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH, and can be programmed
to experiment with different boot mode options without writing to OTP. The range of customization to the boot
definition table depends on how many boot mode select pins (BMSP) are being used. For example, 0 BMSPs
equals to 1 table entry, 1 BMSP equals to 2 table entries, 2 BMSPs equals to 4 table entries, and 3 BMSPs
equals to 8 table entries. Refer to the TMS320F28003x Real-Time Microcontrollers Technical Reference Manual
for examples on how to set up the BOOTPIN_CONFIG and BOOTDEF values.
Note
The locations Z2-OTP-BOOTDEF-LOW and Z2-OTP-BOOTDEF-HIGH will be used instead of Z1-
OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH locations when Z2-OTP-BOOTPIN-CONFIG is
configured. Refer to Configuring Boot Mode Pins for more details on BOOTPIN_CONFIG usage.
Table 7-11. BOOTDEF Bit Fields
BYTE
POSITION
BOOTDEF NAME
NAME
DESCRIPTION
Set the boot mode for index 0 of the boot table.
Different boot modes and their options can include,
for example, a boot mode that uses different GPIOs
for a specific bootloader or a different flash entry
point address. Any unsupported boot mode will
cause the device to either go to wait boot or boot to
flash.
BOOT_DEF0
7:0
BOOT_DEF0 Mode/Options
Refer to GPIO Assignments for valid BOOTDEF
values to set in the table.
BOOT_DEF1
BOOT_DEF2
BOOT_DEF3
BOOT_DEF4
BOOT_DEF5
BOOT_DEF6
BOOT_DEF7
15:8
BOOT_DEF1 Mode/Options
BOOT_DEF2 Mode/Options
BOOT_DEF3 Mode/Options
BOOT_DEF4 Mode/Options
BOOT_DEF5 Mode/Options
BOOT_DEF6 Mode/Options
BOOT_DEF7 Mode/Options
23:16
31:24
39:32
47:40
55:48
63:56
Refer to BOOT_DEF0 description
Copyright © 2021 Texas Instruments Incorporated
228 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.11.2 GPIO Assignments
This section details the GPIOs and boot option values used for boot mode set in the BOOT_DEF memory
location located at Z1-OTP-BOOTDEF-LOW/ Z2-OTP-BOOTDEF-LOW and Z1-OTP-BOOTDEF-HIGH/ Z2-OTP-
BOOTDEF-HIGH. Refer to Configuring Boot Mode Table Options on how to configure BOOT_DEF. When
selecting a boot mode option, make sure to verify that the necessary pins are available in the pin mux options for
the specific device package being used.
Table 7-12. SCI Boot Options
OPTION
BOOTDEF VALUE
SCITXDA GPIO
SCIRXDA GPIO
GPIO28
GPIO17
GPIO9
0 (default)
0x01
0x21
0x41
0x61
0x81
GPIO29
1
2
3
4
GPIO16
GPIO8
GPIO2
GPIO3
GPIO16
GPIO3
Table 7-13. MCAN Boot Options
OPTION
BOOTDEF VALUE
CANTXA GPIO
CANRXA GPIO
GPIO5
0 (default)
0x08
0x28
0x48
GPIO4
1
2
GPIO1
GPIO0
GPIO13
GPIO12
Table 7-14. DCAN Boot Options
OPTION
BOOTDEF VALUE
CANTXA GPIO
CANRXA GPIO
GPIO5
0 (default)
0x02
0x22
0x42
0x62
GPIO4
1
2
3
GPIO32
GPIO33
GPIO2
GPIO3
GPIO13
GPIO12
Table 7-15. I2C Boot Options
OPTION
BOOTDEF VALUE
SDAA GPIO
GPIO32
GPIO0
SCLA GPIO
GPIO33
GPIO1
0
1
2
0x07
0x27
0x47
GPIO10
GPIO8
Table 7-16. RAM Boot Options
RAM ENTRY POINT
(ADDRESS)
OPTION
BOOTDEF VALUE
0
0x05
0x0000 0000
Table 7-17. Flash Boot Options
FLASH ENTRY POINT
OPTION
BOOTDEF VALUE
FLASH SECTOR
(ADDRESS)
0x0008 0000
0x0008 8000
0x0008 FFF0
0x0009 0000
0x0009 7FF0
0x0009 FFF0
0x000A 0000
0x000A FFF0
0 (default)
0x03
0x23
0x43
0x63
0x83
0xA3
0xC3
0xE3
Bank0 Sector 0
Bank 0 Sector 8
Bank 0 Sector 15
Bank 1, Sector 0
Bank 1, Sector 7
Bank 1, Sector 15
Bank 2, Sector 0
Bank 2, Sector 15
1
2
3
4
5
6
7
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 229
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Table 7-18. LFU Flash Boot Options
FLASH ENTRY POINT
OPTION
BOOTDEF VALUE
(ADDRESS)
BANK
0 (default)
0x0B
0x2B
0x4B
0x6B
0x8B
0x0008 0000
0x0009 0000
0x000A 0000
0x0008 8000
0x0009 8000
0x000A 8000
0x0008 FFF0
0x0009 FFF0
0x000A FFF0
0x0008 8000
0x0009 0000
0x0009 0000
0x0008 EFF0
0x0009 7FF0
0x000A 7FF0
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
1
2
3
4
Table 7-19. Secure LFU Flash Boot Options
FLASH ENTRY POINT
OPTION
BOOTDEF VALUE
(ADDRESS)
BANK
0 (default)
0x0C
0x2C
0x4C
0x6C
0x8C
0x0008 0000
0x0009 0000
0x000A 0000
0x0008 8000
0x0009 8000
0x000A 8000
0x0008 FFF0
0x0009 FFF0
0x000A FFF0
0x0008 8000
0x0009 0000
0x0009 0000
0x0008 EFF0
0x0009 7FF0
0x000A 7FF0
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
Bank0
Bank1
Bank2
1
2
3
4
Table 7-20. Wait Boot Options
OPTION
BOOTDEF VALUE
WATCHDOG
Enabled
0
1
0x04
0x24
Disabled
Copyright © 2021 Texas Instruments Incorporated
230 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-21. SPI Boot Options
OPTION
BOOTDEF VALUE
SPISIMOA
SPISOMIA
SPICLKA
GPIO3
GPIO3
GPIO9
GPIO9
SPISTEA
GPIO5
0
1
2
3
0x06
0x26
0x46
0x66
GPIO2
GPIO1
GPIO16
GPIO8
GPIO1
GPIO0
GPIO10
GPIO17
GPIO11
GPIO11
GPIO8
Table 7-22. Parallel Boot Options
28x(DSP) CONTROL
GPIO
OPTION
BOOTDEF VALUE
0x00
D0-D7 GPIO
HOST CONTROL GPIO
0 (default)
D0 - GPIO28
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
D0 - GPIO0
D1 - GPIO1
D2 - GPIO2
D3 - GPIO3
D4 - GPIO4
D5 - GPIO5
D6 - GPIO6
D7 - GPIO7
GPIO16
GPIO29
1
0x20
GPIO16
GPIO11
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 231
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.12 Dual Code Security Module
The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means
access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for
example, through a debugging tool such as Code Composer Studio™ (CCS).
The code security mechanism offers protection for two zones, Zone 1 (Z1) and Zone 2 (Z2). The security
implementation for both the zones is identical. Each zone has its own dedicated secure resource (OTP memory
and secure ROM) and allocated secure resource (LSx RAM and flash sectors).
The security of each zone is ensured by its own 128-bit password (CSM password). The password for each
zone is stored in an OTP memory location based on a zone-specific link pointer. The link pointer value can be
changed to program a different set of security settings (including passwords) in OTP.
Code Security Module Disclaimer
ꢀ
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
Copyright © 2021 Texas Instruments Incorporated
232 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
7.13 Watchdog
The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional lower
limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the
watchdog is fully backward-compatible.
The watchdog generates either a reset or an interrupt. It is clocked from the internal oscillator with a selectable
frequency divider.
Figure 7-4 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV
WDCR.WDPS
WDCR.WDDIS
WDCNTR
WDCLK
(INTOSC1)
Overflow
1-count
delay
8-bit
Watchdog
Counter
WDCLK
Divider
Watchdog
Prescaler
SYSRSn
Clear
Count
WDWCR.MIN
WDKEY (7:0)
Watchdog
Window
Detector
Out of Window
Good Key
Watchdog
Key Detector
55 + AA
WDCR(WDCHK(2:0))
Bad Key
WDRSTn
WDINTn
Generate
512-WDCLK
Output Pulse
1
0
1
Watchdog Time-out
SCSR.WDENINT
Figure 7-4. Windowed Watchdog
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 233
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.14 C28x Timers
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter
is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it
is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is
connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If
TI-RTOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
SYSCLK (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
X1 (XTAL)
7.15 Dual-Clock Comparator (DCC)
The DCC module is used for evaluating and monitoring the clock input based on a second clock, which can
be a more accurate and reliable version. This instrumentation is used to detect faults in clock source or clock
structures, thereby enhancing the system's safety metrics.
7.15.1 Features
The DCC has the following features:
•
•
•
•
•
Allows the application to ensure that a fixed ratio is maintained between frequencies of two clock signals.
Supports the definition of a programmable tolerance window in terms of the number of reference clock cycles.
Supports continuous monitoring without requiring application intervention.
Supports a single-sequence mode for spot measurements.
Allows the selection of a clock source for each of the counters, resulting in several specific use cases.
7.15.2 Mapping of DCCx Clock Source Inputs
Table 7-23. DCCx Clock Source0 Table
DCCxCLKSRC0[3:0]
CLOCK NAME
0x0
0x1
XTAL/X1
INTOSC1
0x2
INTOSC2
TCK
0x4
0x5
CPU1.SYSCLK
0x8
AUXCLKIN
0xC
others
INPUT XBAR (Output16 of input-xbar)
Reserved
Copyright © 2021 Texas Instruments Incorporated
234 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Table 7-24. DCCx Clock Source1 Table
DCCxCLKSRC1[4:0]
CLOCK NAME
PLLRAWCLK
INTOSC1
0x0
0x2
0x3
INTOSC2
0x6
CPU1.SYSCLK
0x9
Input XBAR (Output15 of the input-xbar)
0xA
0xB
0xC
0xD
0xE
0xF
others
AUXCLKIN
EPWMCLK
LSPCLK
ADCCLK
WDCLK
CAN0BITCLK
Reserved
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 235
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
7.16 Configurable Logic Block (CLB)
The C2000 configurable logic block (CLB) is a collection of blocks that can be interconnected using software to
implement custom digital logic functions or enhance existing on-chip peripherals. The CLB is able to enhance
existing peripherals through a set of crossbar interconnections, which provide a high level of connectivity to
existing control peripherals such as enhanced pulse width modulators (ePWM), enhanced capture modules
(eCAP), and enhanced quadrature encoder pulse modules (eQEP). The crossbars also allow the CLB to be
connected to external GPIO pins. In this way, the CLB can be configured to interact with device peripherals to
perform small logical functions such as comparators, or to implement custom serial data exchange protocols.
Through the CLB, functions that would otherwise be accomplished using external logic devices can now be
implemented inside the MCU.
The CLB peripheral is configured through the CLB tool. For more information on the CLB tool, available
examples, application reports and users guide, please refer to the following location in your C2000Ware for
C2000 MCUs package (C2000Ware_2_00_00_03 and higher):
•
•
•
•
C2000WARE_INSTALL_LOCATION\utilities\clb_tool\clb_syscfg\doc
CLB Tool User's Guide
Designing With the C2000™ Configurable Logic Block (CLB) Application Report
How to Migrate Custom Logic From an FPGA/CPLD to C2000™ Microcontrollers Application Report
The CLB module and its interconnections are shown in Figure 7-5.
GPIO0
to
GPIOx
Asynchronous
Synchronous
Sync. + Qual
Input X-BAR
INPUT1 œ INPUT6
CLBx TILE
OUT4/5
Other Sources
CLB X-BAR
CLB INPUT X-BAR
AUXSIG0 œ AUXSIG7
Other Sources
CLB
CLB TILE1
CELL
GPREG
CLB Global Signals
IN0-7
OUT 0-7
Local
Signals
.
.
.
CLB Tile Outputs
ñ
ñ
Intersect other Peripherals
OUTPUT X-BAR
INPUT1 œ INPUT16
CLB TILEx
CELL
GPREG
IN0-7
OUT 0-7
Local
Signals
All CLB Tile Outputs
CLB OUTPUT X-BAR
GPIO MUX
Figure 7-5. GPIO to CLB Tile Connections
Copyright © 2021 Texas Instruments Incorporated
236 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
Absolute encoder protocol interfaces are now provided as Position Manager solutions in the C2000Ware
MotorControl SDK. Configuration files, application programmer interface (API), and use examples for such
solutions are provided with C2000Ware MotorControl SDK. In some solutions, the TI-configured CLB is used
with other on-chip resources, such as the SPI port or the C28x CPU, to perform more complex functionality.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 237
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
8 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market.
Search and download TI reference designs at Select TI reference designs.
Copyright © 2021 Texas Instruments Incorporated
238 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
9.1 Getting Started and Next Steps
The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all
aspects of development with C2000 devices from hardware to support resources. In addition to key reference
documents, each section provides relevant links and resources to further expand on the information covered.
9.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes:
TMX, TMP, or TMS (for example, TMS320F280039C). Texas Instruments recommends two of three possible
prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
TMP Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
TMS Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PN) and temperature range (for example, S).
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 239
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
Generic Part Number:
Orderable Part Number:
TMS
X
320
F
F
280039C
-Q1
Q1
280039C (blank) PZ
R
PREFIX(A)
AUTOMOTIVE AEC-Q100 QUALIFICATION
TMX (X) = experimental device
TMS (blank) = qualified device
(blank) = Not AEC-Q100 qualified
Q1 = AEC-Q100 Grade 1 qualification
DEVICE FAMILY
SHIPPING OPTIONS
320 = TMS320 MCU Family
(blank) = Tray
R = Tape and Reel
TECHNOLOGY
F = Flash
PACKAGE TYPE
PZ = 100-pin Low-Profile Quad Flatpack (LQFP)
PN = 80-pin LQFP
DEVICE
PM = 64-pin LQFP
PT = 48-pin LQFP
280039
280038
280037
280036
280034
230033
280039C
280038C
280037C
280036C
TEMPERATURE RANGE
(blank), S = –40°C to 125°C (TA); –40°C to 150°C (TJ)
A. Prefix X is used in orderable part numbers.
Figure 9-1. Device Nomenclature
9.3 Markings
Figure 9-2, Figure 9-3, Figure 9-4, and Figure 9-5 show the package symbolization. Table 9-1 lists the silicon
revision codes.
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
2-Digit Year/Month Code
Assembly Lot Code
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
X
F280039CPZQ
$$#−YMLLLLS
G4
$$
#
G4
ECAT
=
Package
Pin 1
Figure 9-2. Package Symbolization for PZ Package
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
2-Digit Year/Month Code
Assembly Lot Code
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
X
F280039CSPN
$$#−YMLLLLS
G4
$$
#
G4
ECAT
=
Package
Pin 1
Figure 9-3. Package Symbolization for PN Package
Copyright © 2021 Texas Instruments Incorporated
240 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
2-Digit Year/Month Code
Assembly Lot Code
Assembly Site Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
X
F280039CSPM
$$#−YMLLLLS
G4
$$
#
G4
ECAT
=
Package
Pin 1
Figure 9-4. Package Symbolization for PM Package
YMLLLLS
Lot Trace Code
=
YM
LLLL
S
980
$$
2-Digit Year/Month Code
Assembly Lot Code
Assembly Site Code
TI E.I.A. Code
Wafer Fab Code (one or two characters) as applicable
Silicon Revision Code
=
=
=
=
=
=
980
PT
X
F280037CS
YMLLLLS
#
$$#
G4
G4
ECAT
=
Package
Pin 1
Figure 9-5. Package Symbolization for PT Package
Table 9-1. Revision Identification
REVID(1)
ADDRESS: 0x5D00C
SILICON REVISION CODE
Blank
SILICON REVISION
COMMENTS
This silicon revision is available as TMX.
0
0x0000 0000
(1) Silicon Revision ID
9.4 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance
of the device, generate code, and develop solutions follow. To view all available tools and software for C2000™
real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
TMDSCNCD280039C Control Card
The F280039C controlCARD is an HSEC180 controlCARD based evaluation and development tool for the
C2000™ F28003x series of microcontroller products. controlCARDs are ideal to use for initial evaluation and
system prototyping. controlCARDs are complete board-level modules that utilize one of two standard form
factors (100-pin DIMM or 180-pin HSEC ) to provide a low-profile single-board controller solution. For first
evaluation controlCARDs are typically purchased bundled with a baseboard or bundled in an application kit.
TI Resource Explorer
To enhance your experience, be sure to check out the TI Resource Explorer to browse examples, libraries, and
documentation for your applications.
HSEC180 controlCARD Baseboard Docking Station
TMDSHSECDOCK is a baseboard that provides header pin access to key signals on compatible HSEC180-
based controlCARDs. A breadboard area is available for rapid prototyping. Board power can be provided by the
provided USB cable or a 5-V barrel supply.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 241
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
XDS110 JTAG Debug Probe
The Texas Instruments XDS110 is a new class of debug probe (emulator) for TI embedded processors. The
XDS110 replaces the XDS100 family while supporting a wider variety of standards (IEEE1149.1, IEEE1149.7,
SWD) in a single pod. Also, all XDS debug probes support Core and System Trace in all Arm® and DSP
processors that feature an Embedded Trace Buffer (ETB). For Core Trace over pins the XDS560v2 PRO TRACE
Receiver & Debug Probe is required.
XDS200 USB Debug Probe
The XDS200 is a debug probe (emulator) used for debugging TI embedded devices. The XDS200 features a
balance of low cost with good performance as compared to the low cost XDS110 and the high performance
XDS560v2. It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a single pod. All XDS
debug probes support Core and System Trace in all Arm® and DSP processors that feature an Embedded Trace
Buffer (ETB). For Core Trace over pins the XDS560v2 PRO TRACE Receiver & Debug Probe is required.
XDS560v2 System Trace USB Debug Probe
The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional
JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).
Software Tools
C2000™ Software Guide
C2000™ real-time controllers are a portfolio of high-performance microcontrollers that are purpose-built
to control power electronics and provide advanced digital signal processing for industrial and automotive
applications. Software components to program various modules in C2000 MCUs are released as part of C2000
software releases. This guide provides an overview of various software components and available functionality.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ MCUs is a cohesive set of software and documentation created to minimize
development time. It includes device-specific drivers, libraries, and peripheral examples.
Digital Power SDK
Digital Power SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based digital power system development time targeted for various AC-DC, DC-DC and DC-AC
power supply applications. The software includes firmware that runs on C2000 digital power evaluation modules
(EVMs) and reference designs, which are targeted for solar, telecom, server, electric vehicle chargers and
industrial power delivery applications. Digital Power SDK provides all the needed resources at every stage of
development and evaluation in a digital power applications.
Motor Control SDK
Motor Control SDK is a cohesive set of software infrastructure, tools, and documentation designed to minimize
C2000 MCU-based motor control system development time targeted for various three-phase motor control
applications. The software includes firmware that runs on C2000 motor control evaluation modules (EVMs) and
reference designs, which are targeted for industrial drive and other motor control, Motor Control SDK provides
all the needed resources at every stage of development and evaluation for high-performance motor control
applications.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and
debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface
taking the user through each step of the application development flow. Familiar tools and interfaces allow
users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse
software framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich
development environment for embedded developers.
SysConfig System configuration tool
SysConfig is a comprehensive collection of graphical utilities for configuring pins, peripherals, radios,
subsystems, and other components. SysConfig helps you manage, expose and resolve conflicts visually so
that you have more time to create differentiated applications. The tool's output includes C header and code files
Copyright © 2021 Texas Instruments Incorporated
242 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
that can be used with software development kit (SDK) examples or used to configure custom software. The
SysConfig tool automatically selects the pinmux settings that satisfy the entered requirements. The SysConfig
tool is delivered integrated in CCS, as a standalone installer, or can be used via the dev.ti.com cloud tools portal.
For more information about the SysConfig system configuration tool, visit the System configuation tool page.
C2000 Third-party search tool
TI has partnered with multiple companies to offer a wide range of solutions and services for TI C2000 devices.
These companies can accelerate your path to production using C2000 devices. Download this search tool to
quickly browse third-party details and find the right third-party to meet your needs.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
C2000 code generation tools - compiler
The TI C2000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C2000
Microcontroller platforms, including the Concerto (F28M3xx), Entry-Performance (280xx), Premium-Performance
Floating-Point (283xx), and C2000 Fixed-Point (2823x/280x/281x) Microcontroller devices.
Models
Various models are available for download from the product Design & development pages. These models
include I/O Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL)
Models. To view all available models, visit the Design tools & simulation section of the Design & development
page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable
hands-on workshops provides an easy means for gaining a complete working knowledge of the C2000
microcontroller family. These training resources have been designed to decrease the learning curve, while
reducing development time, and accelerating product time to market. For more information on the various
training resources, visit the C2000™ real-time control MCUs – Support & training site. Additionally, the C2000
Academy course provides new users with a way to ramp quickly with C2000 devices and their many features.
This is a great entry point for users getting started with C2000, and is available at the C2000 Academy resource
explorer page.
9.5 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
follows.
Errata
TMS320F28003x Real-Time MCUs Silicon Errata describes known advisories on silicon and provides
workarounds.
Technical Reference Manual
TMS320F28003x Real-Time Microcontrollers Technical Reference Manual details the integration, the
environment, the functional description, and the programming models for each peripheral and subsystem in
the F28003x real-time microcontrollers.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This Reference
Guide also describes emulation features available on these DSPs.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 243
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
DSPs.
Tools Guides
TMS320C28x Assembly Language Tools v21.6.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v21.6.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures, and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
Fast Integer Division – A Differentiated Offering From C2000™ Product Family provides an overview of the
different division and modulo (remainder) functions and its associated properties.
C2000™ Key Technology Guide provides a deeper look into the components that differentiate the C2000
Microcontroller Unit (MCU) as it pertains to Real-Time Control Systems.
9.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
Copyright © 2021 Texas Instruments Incorporated
244 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
www.ti.com
SPRSP61 – OCTOBER 2021
9.7 Trademarks
C2000™, TMS320C2000™, Code Composer Studio™, TMS320™, TI E2E™ are trademarks of Texas Instruments.
Bosch® is a registered trademark of Robert Bosch GmbH Corporation.
Arm® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
All trademarks are the property of their respective owners.
9.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.9 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 245
Product Folder Links: TMS320F280039C TMS320F280037C
TMS320F280039C, TMS320F280037C
SPRSP61 – OCTOBER 2021
www.ti.com
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
To learn more about TI packaging, visit the Packaging information website.
Copyright © 2021 Texas Instruments Incorporated
246 Submit Document Feedback
Product Folder Links: TMS320F280039C TMS320F280037C
PACKAGE OPTION ADDENDUM
www.ti.com
23-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
XF280037CSPT
XF280039CSPM
XF280039CSPN
XF280039CSPZ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
PT
PM
PN
PZ
48
64
90
90
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Call TI
Call TI
Call TI
80
119
90
100
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
PM0064A
LQFP - 1.6 mm max height
SCALE 1.400
PLASTIC QUAD FLATPACK
10.2
9.8
B
NOTE 3
64
49
PIN 1 ID
1
48
10.2
9.8
12.2
TYP
11.8
NOTE 3
33
16
32
17
A
0.27
0.17
64X
60X 0.5
4X 7.5
0.08
C A B
C
(0.13) TYP
SEATING PLANE
0.08
SEE DETAIL A
0.25
GAGE PLANE
(1.4)
1.6 MAX
0.05 MIN
0.75
0.45
0 -7
DETAIL
SCALE: 14
A
DETAIL A
TYPICAL
4215162/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
49
64
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
33
16
17
32
(11.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
0.05 MAX
ALL AROUND
EXPOSED METAL
METAL
0.05 MIN
ALL AROUND
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215162/A 03/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004).
www.ti.com
EXAMPLE STENCIL DESIGN
PM0064A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
64
49
64X (1.5)
1
48
64X (0.3)
SYMM
(11.4)
60X (0.5)
(R0.05) TYP
16
33
17
32
(11.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:8X
4215162/A 03/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
0,50
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
TMS320F280037C
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280037C-Q1
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280038-Q1
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280038C-Q1
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280039
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280039-Q1
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280039C
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280039C-Q1
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28003X
TMS320F28003x Real-Time MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280040-Q1
TMS320F28004x MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280040C-Q1
TMS320F28004x MicrocontrollersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F280041
具有 100MHz 频率、FPU、TMU、128kB 闪存、PGA、SDFM 的 C2000™ 32 位 MCUWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明