TMS320F28026FPTT [TI]
具有 60MHz 频率、32KB 闪存、InstaSPIN-FOC 的 C2000™ 32 位 MCU | PT | 48 | -40 to 105;
| 型号： | TMS320F28026FPTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 60MHz 频率、32KB 闪存、InstaSPIN-FOC 的 C2000™ 32 位 MCU | PT | 48 | -40 to 105 时钟 微控制器 外围集成电路 装置 闪存 |
| 文件： | 总140页 (文件大小：4683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
TMS320F2802x 微控制器
• 串行端口外设
1 特性
– 一个串行通信接口(SCI) 通用异步接收器/发送器
• 高效32 位CPU (TMS320C28x)
(UART) 模块
– 一个串行外设接口(SPI) 模块
– 一个内部集成电路(I2C) 模块
• 增强型控制外设
– 60MHz（16.67ns 周期时间）
– 50MHz（20ns 周期时间）
– 40MHz（25ns 周期时间）
– 16 × 16 和32 × 32 MAC 操作
– 16 × 16 双MAC
– 哈佛(Harvard) 总线架构
– 连动运算
– 快速中断响应和处理
– ePWM
– 高分辨率PWM (HRPWM)
– 增强型捕捉(eCAP) 模块
– 模数转换器(ADC)
– 片上温度传感器
– 统一存储器编程模型
– 高效代码（使用C/C++ 和汇编语言）
• 字节序：小端字节序
– 比较器
• 高级仿真特性
– 分析和断点功能
– 通过硬件进行实时调试
• 封装选项
• 器件和系统均可实现低成本：
– 3.3V 单电源
– 无需电源时序
– 集成型加电和欠压复位
– 可采用低至38 引脚小型封装
– 低功耗
– 38 引脚DA Thin Shrink Small-Outline Package
(TSSOP)
– 48 引脚PT Low-Profile Quad Flatpack (LQFP)
• 温度选项
– 无模拟支持引脚
• 时钟：
– T：–40°C 至105°C
– S：–40°C 至125°C
– 两个内部零引脚振荡器
– 片上晶振振荡器和外部时钟输入
– 看门狗计时器模块
– Q：–40°C 至125°C 的环境温度范围
（通过针对汽车应用的AEC Q100 认证）
2 应用
– 丢失时钟检测电路
• 多达22 个具有输入滤波功能且可单独编程的多路
复用GPIO 引脚
• 可支持所有外设中断的外设中断扩展(PIE) 模块
• 三个32 位CPU 计时器
• 空调室外机
• 逆变器和电机控制
• 纺织机
• 微型逆变器
• 每个增强型脉宽调制器(ePWM) 中均有一个独立的
16 位计时器
• 片上存储器
• 交流驱动器功率级模块
• 交流输入BLDC 电机驱动器
• 直流输入BLDC 电机驱动器
• 工业交流/直流电源
• 三相UPS
– 闪存，SARAM，OTP，引导ROM 可用
• 代码安全模块
• 商用直流/直流电源
• 商用网络和服务器PSU
• 商用通信电源整流器
• 128 位安全密钥和锁
– 保护安全内存块
– 防止固件逆向工程
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRS523
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
3 说明
C2000™ 32 位微控制器针对处理、感应和驱动进行了优化，可提高实时控制应用（如工业电机驱动器、光伏逆变
器和数字电源、电动汽车和运输、电机控制以及感应和信号处理）的闭环性能。C2000 系列包括高级性能 MCU
和入门级性能MCU。
F2802x 微控制器系列提供 C28xx 内核的强大功能，同时结合低引脚数器件中高度集成的控制外设。该系列器件
的代码与基于C28x 的旧版代码兼容，同时具有较高的模拟集成度。
内部稳压器实现了单电源轨运行。HRPWM 模块经过强化，可实现双边沿控制（调频）。增设了具有10 位内部基
准的模拟比较器，可直接进行路由以控制PWM 输出。ADC 可在0V 至3.3V 的固定满量程范围内实施转换，支持
VREFHI/VREFLO 基准的比例运算。ADC 接口已针对低开销和延迟进行了优化。
如需详细了解C2000 MCU，请访问“C2000 概述”，地址为www.ti.com/c2000。
器件信息
器件型号(1)
封装
封装尺寸
TMS320F28027PT
TMS320F28026PT
TMS320F28023PT
TMS320F28022PT
TMS320F28021PT
TMS320F28020PT
TMS320F280200PT
TMS320F28027DA
TMS320F28026DA
TMS320F28023DA
TMS320F28022DA
TMS320F28021DA
TMS320F28020DA
TMS320F280200DA
LQFP (48)
LQFP (48)
LQFP (48)
LQFP (48)
LQFP (48)
LQFP (48)
LQFP (48)
TSSOP (38)
TSSOP (38)
TSSOP (38)
TSSOP (38)
TSSOP (38)
TSSOP (38)
TSSOP (38)
7.0mm × 7.0mm
7.0mm × 7.0mm
7.0mm × 7.0mm
7.0mm × 7.0mm
7.0mm × 7.0mm
7.0mm × 7.0mm
7.0mm × 7.0mm
12.5mm x 6.2mm
12.5mm x 6.2mm
12.5mm x 6.2mm
12.5mm x 6.2mm
12.5mm x 6.2mm
12.5mm x 6.2mm
12.5mm x 6.2mm
(1) 有关这些器件的详细信息，请参阅机械、封装和可订购信息。
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
4 功能方框图
功能方框图展示了器件的功能方框图。
OTP 1K × 16
Secure
M0
SARAM 1K × 16
(0-wait)
SARAM
M1
SARAM 1K × 16
(0-wait)
1K/3K/4K × 16
Code
Security
Module
FLASH
8K/16K/32K × 16
Secure
(0-wait)
Secure
Boot-ROM
8K × 16
(0-wait)
OTP/Flash
Wrapper
PSWD
Memory Bus
TRST
TCK
TDI
TMS
TDO
COMP1OUT
GPIO
MUX
C28x
32-Bit CPU
COMP2OUT
GPIO
Mux
COMP1A
COMP1B
COMP2A
COMP2B
COMP
3 External Interrupts
XCLKIN
PIE
OSC1,
OSC2,
Ext,
CPU Timer 0
X1
X2
AIO
CPU Timer 1
CPU Timer 2
Memory Bus
MUX
PLL,
LPM,
WD
LPM Wakeup
XRS
ADC
A7:0
B7:0
POR/
BOR
VREG
32-Bit Peripheral Bus
16-Bit Peripheral Bus
32-Bit Peripheral Bus
ePWM
SCI
(4L FIFO)
SPI
(4L FIFO)
I2C
eCAP
(4L FIFO)
HRPWM
From
COMP1OUT,
COMP2OUT
GPIO MUX
Copyright © 2017, Texas Instruments Incorporated
A. 由于多路复用，所有外设引脚不能同时使用。
图4-1. 功能方框图
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
内容
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 2
4 功能方框图.........................................................................3
5 修订历史记录.....................................................................5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 引脚图......................................................................... 8
7.2 信号说明....................................................................10
8 规格................................................................................. 15
8.1 Absolute Maximum Ratings...................................... 15
8.2 ESD 等级- 汽车........................................................15
8.3 ESD 等级- 商用........................................................16
8.4 建议工作条件............................................................ 16
8.5 功耗摘要....................................................................17
8.6 电气特性....................................................................21
8.7 热阻特性...................................................................23
8.8 散热设计注意事项..................................................... 24
8.9 无信号缓冲情况下MCU 与JTAG 调试探针的连接... 24
8.10 参数信息..................................................................25
8.11 测试负载电路...........................................................25
8.12 电源时序..................................................................26
8.13 时钟规范..................................................................29
8.14 闪存定时..................................................................33
9 详细说明.......................................................................... 36
9.1 Overview...................................................................36
9.2 Memory Maps........................................................... 44
9.3 Register Maps...........................................................51
9.4 Device Emulation Registers......................................52
9.5 VREG/BOR/POR...................................................... 53
9.6 系统控制....................................................................55
9.7 Low-power Modes Block...........................................63
9.8 Interrupts...................................................................64
9.9 外设...........................................................................69
10 应用、实施和布局........................................................119
10.1 TI 参考设计............................................................119
11 器件和文档支持............................................................120
11.1 Device and Development Support Tool
Nomenclature............................................................120
11.2 Tools and Software................................................121
11.3 文档支持................................................................123
11.4 支持资源................................................................123
11.5 商标.......................................................................124
11.6 静电放电警告.........................................................124
11.7 术语表................................................................... 124
12 机械、封装和可订购信息.............................................125
12.1 封装信息................................................................125
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
5 修订历史记录
Changes from OCTOBER 30, 2020 to JANUARY 18, 2021 (from Revision O (October 2020) to
Revision P (January 2021))
Page
• Device Comparison: Updated part numebrs.......................................................................................................6
• ESD 等级- 汽车：更新了器件型号...................................................................................................................15
• ESD 等级- 商用：更新了器件型号...................................................................................................................16
• Device and Development Support Tool Nomenclature: Updated Device Nomenclature image to show -Q1 part
number............................................................................................................................................................120
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
6 Device Comparison
表6-1 lists the features of the TMS320F2802x devices.
表6-1. Device Comparison
28026
28027
28027-Q1
28027F
28026-Q1
28026F
28023
28023-Q1
(50 MHz)
28022
28022-Q1
(50 MHz)
TYPE
28021
(40 MHz)
28020
(40 MHz)
280200
(40 MHz)
FEATURE
(1)
28027F-Q1
28026F-Q1
(60 MHz)(2)
(60 MHz)(2)
38-Pin
DA
48-Pin
PT
38-Pin
DA
48-Pin
PT
38-Pin
DA
48-Pin
PT
38-Pin
DA
48-Pin
PT
38-Pin
DA
48-Pin
PT
38-Pin
DA
48-Pin
PT
38-Pin
DA
48-Pin
PT
Package Type
TSSOP
LQFP
TSSOP
LQFP
TSSOP
LQFP
TSSOP
LQFP
TSSOP
LQFP
TSSOP
LQFP
TSSOP
LQFP
Instruction cycle
16.67 ns
16.67 ns
20 ns
20 ns
25 ns
25 ns
25 ns
–
–
–
On-chip flash (16-bit word)
On-chip SARAM (16-bit word)
32K
6K
16K
6K
32K
6K
16K
6K
32K
5K
16K
3K
8K
3K
Code security for on-chip
flash/SARAM/OTP blocks
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
–
–
–
Boot ROM (8K x 16)
Yes
1K
One-time programmable
(OTP) ROM (16-bit word)
ePWM channels
eCAP inputs
Watchdog timer
MSPS
1
0
8 (ePWM1/2/3/4)
8 (ePWM1/2/3/4)
8 (ePWM1/2/3/4)
8 (ePWM1/2/3/4)
8 (ePWM1/2/3/4)
8 (ePWM1/2/3/4)
8 (ePWM1/2/3/4)
1
1
1
Yes
3
1
Yes
3
1
Yes
2
1
Yes
2
–
Yes
2
Yes
4.6
Yes
4.6
–
Conversion
Time
216.67 ns
216.67 ns
260 ns
260 ns
500 ns
500 ns
500 ns
Channels
7
13
7
13
7
13
7
13
7
13
7
13
7
13
12-Bit ADC
3
Temperature
Sensor
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Dual Sample-
and-Hold
Yes
3
Yes
3
Yes
3
Yes
3
Yes
3
Yes
3
Yes
3
32-Bit CPU timers
–
High-resolution ePWM
Channels
4 (ePWM1A/2A
/3A/4A)
4 (ePWM1A/2A
/3A/4A)
4 (ePWM1A/2A
/3A/4A)
4 (ePWM1A/2A
/3A/4A)
1
–
–
–
Comparators w/ Integrated
DACs
0
0
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Inter-integrated circuit (I2C)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Serial Peripheral Interface
(SPI)
Serial Communications
Interface (SCI) (UART
Compatible)
0
1
1
1
1
1
1
1
Digital (GPIO)
I/O pins
20
22
20
22
20
22
20
22
20
22
20
22
20
22
–
–
–
–
(shared)
Analog (AIO)
6
3
6
3
6
3
6
3
6
3
6
3
6
3
External interrupts
Supply voltage (nominal)
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
T: –40°C to
105°C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
Yes
Yes
–
Yes
Yes
–
Yes
Yes
–
Yes
Yes
–
Yes
Yes
–
–
–
–
Temperature
options
S: –40°C to
125°C
Q: –40°C to
125°C(3)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
(2) TMS320F28027F and TMS320F28026F are InstaSPIN-FOC™-enabled MCUs. For more information, see 节11.3 for a list of InstaSPIN
Technical Reference Manuals.
(3) The letter Q refers to AEC Q100 qualification for automotive applications.
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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6.1 Related Products
For information about similar products, see the following links:
TMS320F2802x Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are
available.
TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2805x Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
TMS320F2806x Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-
count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™
versions are available.
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The
F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable
logic block (CLB) versions are available.
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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7 Terminal Configuration and Functions
7.1 引脚图
图 7-1 显示了 48 引脚 PT 薄型四方扁平封装 (LQFP) 引脚分配。图 7-2 显示了 38 引脚 DA 薄型小外形尺寸封装
(TSSOP) 引脚分配。
GPIO2/EPWM2A 37
GPIO3/EPWM2B/COMP2OUT 38
GPIO4/EPWM3A 39
24 GPIO18/SPICLKA/SCITXDA/XCLKOUT
23 GPIO38/XCLKIN (TCK)
22 GPIO37 (TDO)
GPIO5/EPWM3B/ECAP1 40
21 GPIO36 (TMS)
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 41
GPIO7/EPWM4B/SCIRXDA 42
20 GPIO35 (TDI)
19 GPIO34/COMP2OUT
18 ADCINB7
VDD
VSS
43
44
17 ADCINB6/AIO14
16 ADCINB4/COMP2B/AIO12
15 ADCINB3
X1 45
X2 46
GPIO12/TZ1/SCITXDA 47
GPIO28/SCIRXDA/SDAA/TZ2 48
14 ADCINB2/COMP1B/AIO10
13 ADCINB1
图7-1. 2802x 48 引脚PT LQFP（顶视图）
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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VDD
VSS
1
38 TEST
2
37 GPIO0/EPWM1A
VREGENZ
VDDIO
3
36 GPIO1/EPWM1B/COMP1OUT
35 GPIO16/SPISIMOA/TZ2
34 GPIO17/SPISOMIA/TZ3
33 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1
32 GPIO18/SPICLKA/SCITXDA/XCLKOUT
31 GPIO38/XCLKIN (TCK)
30 GPIO37 (TDO)
4
GPIO2/EPWM2A
GPIO3/EPWM2B
5
6
GPIO4/EPWM3A
7
GPIO5/EPWM3B/ECAP1
8
GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO
GPIO7/EPWM4B/SCIRXDA
VDD
9
10
11
12
13
14
15
16
17
18
19
29 GPIO36 (TMS)
28 GPIO35 (TDI)
VSS
27 GPIO34
GPIO12/TZ1/SCITXDA
GPIO28/SCIRXDA/SDAA/TZ2
GPIO29/SCITXDA/SCLA/TZ3
26 ADCINB6/AIO14
25 ADCINB4/AIO12
24 ADCINB2/COMP1B/AIO10
/VREFLO
23 VSSA
22 VDDA
TRST
XRS
ADCINA6/AIO6
ADCINA4/AIO4
21 ADCINA0/VREFHI
20 ADCINA2/COMP1A/AIO2
图7-2. 2802x 38 引脚DA TSSOP（顶视图）
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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7.2 信号说明
节7.2.1 对这些信号进行了说明。除JTAG 引脚以外，除非另有说明，否则GPIO 功能是复位时的默认功能。它们
下面列出的外设信号是供替换的功能。有些外设功能并不在所有器件上提供。有关详细信息，请参阅表6-1。输入
不可承受 5V 电压。所有 GPIO 引脚为 I/O/Z 且有一个内部上拉电阻，在每个引脚上可选择性启用/禁用此电阻。
这一特性只适用于 GPIO 引脚。复位时不启用 PWM 引脚上的上拉电阻。复位后启用其他 GPIO 引脚上的上拉电
阻。AIO 引脚没有内部上拉电阻。
备注
使用片上 VREG 时，GPIO19、GPIO34、GPIO35、GPIO36、GPIO37 和 GPIO38 引脚在上电期间可
能有毛刺。这种潜在的毛刺将在读取引导模式引脚之前结束，不会影响引导行为。如果应用不能接受毛
刺，可从外部提供 1.8V 电源。或者添加一个与这些引脚串联的限流电阻（例如 470Ω），可考虑使用
外部驱动器限制降级到引脚和/或外部电路的可能性。当使用外部 1.8V 电源时，无需电源时序。然而，
如果 I/O 引脚的电平转换输出缓冲器中的 3.3V 晶体管在 1.8V 晶体管之前上电，输出缓冲器有可能打
开，这会导致上电期间引脚上出现毛刺。为了避免这种情况，VDD 引脚应早于VDDIO 引脚或与之同时上
电，确保VDD 引脚在VDDIO 引脚达到0.7V 之前达到0.7V。
7.2.1 信号说明
终端
I/O/Z
说明
PT
引脚编号
DA
引脚编号
名称(1)
JTAG
具有内部下拉电阻的JTAG 测试复位。驱动为高电平时，TRST 交由扫描系统控制
器件的运行。如果此信号未连接或驱动为低电平，则器件将在功能模式下工作，测
试复位信号将被忽略。
TRST
2
16
I
注意： TRST 是高电平有效的测试引脚，在器件正常工作期间必须始终保持低电
平。此引脚上需要一个外部上拉电阻。此电阻的值应该基于设计适用的调试器Pod
的驱动强度。一个2.2kΩ 电阻器一般可提供足够的保护。由于这是特定于应用的，
所以TI 建议验证每个目标板是否能正常运行调试器和应用。(↓)
TCK
TMS
I
I
参阅GPIO38
参阅GPIO38。带有内部上拉电阻的JTAG 测试时钟(↑)
参阅GPIO36。带有内部上拉电阻的JTAG 测试模式选择(TMS)。此串行控制输入
在TCK 上升沿输入到TAP 控制器。(↑)
参阅GPIO36
参阅GPIO35
参阅GPIO35。带有内部上拉电阻的JTAG 测试数据输入(TDI)。TDI 在TCK 的上
升沿输入到选择的寄存器（指令或数据）。(↑)
TDI
I
参阅GPIO37。JTAG 扫描输出，测试数据输出(TDO)。所选寄存器（指令或数据）
的内容在TCK 下降沿从TDO 移出。
TDO
O/Z
参阅GPIO37
（8mA 驱动）
闪存
TEST
30
38
I/O
测试引脚。为TI 预留。必须保持未连接状态。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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终端
I/O/Z
说明
PT
引脚编号
DA
引脚编号
名称(1)
时钟
参阅GPIO18。源自SYSCLKOUT 的输出时钟。XCLKOUT 频率要么与
SYSCLKOUT 的频率相同，要么是后者的一半或四分之一。这通过XCLK 寄存器中
的位1:0 (XCLKOUTDIV) 控制。复位时，XCLKOUT = SYSCLKOUT/4。通过将
XCLKOUTDIV 设定为3，可关闭XCLKOUT 信号。GPIO18 的多路复用器控制也必
须设定为XCLKOUT，才能使此信号传播到引脚。
XCLKOUT
O/Z
参阅GPIO18
参阅GPIO19 和GPIO38。外部振荡器输入。时钟的引脚源由XCLK 寄存器内的
XCLKINSEL 位控制，默认选择GPIO38。此引脚馈送来自外部3.3V 振荡器的时
钟。在这种情况下，X1 引脚（如果可用）必须连接至GND，而且必须通过
CLKCTL 寄存器内的14 位禁用片上晶体振荡器。如果使用晶振/谐振器，必须通过
CLKCTL 寄存器内的13 位禁用XCLKIN 路径。
XCLKIN
I
参阅GPIO19 和GPIO38
注意：使用GPIO38/TCK/XCLKIN 引脚提供外部时钟以使器件正常工作的设计可能
需要集成一些挂钩，以便在使用JTAG 连接器调试期间禁用此路径。这是为了防止
JTAG 调试会话期间活动的TCK 信号相互竞争。此时可使用零引脚内部振荡器为器
件计时。
1.8V 片上晶体振荡器输入。要使用此振荡器，必须在X1 和X2 之间连接一个石英
晶振或陶瓷谐振器。在这种情况下，必须通过CLKCTL 寄存器内的13 位禁用
XCLKIN 路径。如果此引脚未使用，必须连接至GND。(I)
X1
X2
45
46
-
I
片上晶体振荡器输出。必须在X1 和X2 之间连接一个石英晶振或陶瓷谐振器。如果
X2 未使用，必须保持未连接状态。(O)
O
–
复位
器件复位（进）和看门狗复位（出）。这些器件具有内置上电复位(POR) 电路和欠
压复位(BOR) 电路。在上电或欠压情况下，此引脚由器件驱动为低电平。外部电路
也可能会驱动此引脚使器件复位生效。发生看门狗复位时，此引脚也由MCU 驱动
为低电平。在看门狗复位期间，XRS 引脚在512 个OSCCLK 周期的看门狗复位持
续时间内被驱动为低电平。应在XRS 和VDDIO 之间放置一个值为2.2kΩ至10kΩ
的电阻器。如果在XRS 和VSS 之间放置一个电容器进行噪声滤除，则该电容器的
值应为100nF 或更小。当看门狗复位生效时，这些值将能让看门狗在512 个
OSCCLK 周期内正确地将XRS 引脚驱动至VOL。任何源头的器件复位都会导致器
件终止执行。程序计数器指向位置0x3F FFC0 包含的地址。当复位失效时，从程序
计数器指定的位置开始执行。此引脚的输出缓冲器是一个有内部上拉电阻的开漏器
件。(↑) 如果此引脚由外部器件驱动，则应使用开漏器件进行驱动。
XRS
3
17
I/OD
ADC、比较器、模拟I/O
ADC 组A，通道7 输入
ADC 组A，通道6 输入
数字AIO 6
ADCINA7
ADCINA6
AIO6
6
4
I
–
I
18
I/O
ADCINA4
COMP2A
AIO4
I
ADC 组A，通道4 输入
比较器输入2A（只在48 引脚器件内可用）
数字AIO 4
5
7
9
19
I
I/O
ADCINA3
ADCINA2
COMP1A
AIO2
I
ADC 组A，通道3 输入
ADC 组A，通道2 输入
比较器输入1A
–
I
20
I
I/O
数字AIO 2
ADCINA1
ADCINA0
VREFHI
8
-
I
ADC 组A，通道1 输入
ADC 组A，通道0 输入
ADC 外部基准高- 仅在ADC 外部基准模式下使用。参阅节9.9.1.1，ADC。
ADC 组B，通道7 输入
ADC 组B，通道6 输入
数字AIO 14
I
10
18
17
21
-
I
I
ADCINB7
ADCINB6
AIO14
I
26
I/O
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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终端
I/O/Z
说明
PT
引脚编号
DA
引脚编号
名称(1)
ADCINB4
COMP2B
AIO12
I
ADC 组B，通道4 输入
16
15
14
13
25
-
I
比较器输入2B（只在48 引脚器件内可用）
数字AIO 12
I/O
ADCINB3
ADCINB2
COMP1B
AIO10
I
ADC 组B，通道3 输入
ADC 组B，通道2 输入
比较器输入1B
I
I
24
-
I/O
I
数字AIO 10
ADCINB1
ADC 组B，通道1 输入
CPU 和I/O 电源
VDDA
11
12
22
23
模拟电源引脚。在此引脚附近连接一个2.2μF 电容器（典型值）。
模拟接地引脚
VSSA
VREFLO
I
ADC 外部基准低（始终接地）
32
43
1
CPU 和逻辑数字电源引脚。使用内部VREG 时，在每个VDD 引脚和接地之间放置
一个1.2µF 电容器。可使用值较高的电容器。
VDD
11
数字I/O 缓冲器和闪存电源引脚。启用VREG 时使用单电源。在此引脚上放置一个
去耦电容器。确切值应由系统电压调节解决方案决定。
VDDIO
35
4
33
44
2
VSS
数字接地引脚
12
稳压器控制信号
具有内部下拉电阻的内部稳压器(VREG) 使能。直接连接到VSS（低）以启用内部
1.8V VREG。直接连接到VDDIO（高）以禁用VREG 并使用外部1.8V 电源。
VREGENZ
34
29
28
37
38
39
3
37
36
5
I
GPIO 和外设信号(2)
GPIO0
I/O/Z
通用输入/输出0
EPWM1A
O
增强型PWM1 输出A 和HRPWM 通道
-
-
-
-
-
I/O/Z
O
-
GPIO1
通用输入/输出1
EPWM1B
增强型PWM1 输出B
-
-
COMP1OUT
O
比较器1 的直接输出
GPIO2
I/O/Z
O
通用输入/输出2
EPWM2A
增强型PWM2 输出A 和HRPWM 通道
-
-
-
-
GPIO3
I/O/Z
O
通用输入/输出3
EPWM2B
增强型PWM2 输出B
6
-
-
COMP2OUT
O
I/O/Z
O
比较器2 的直接输出（只在48 引脚器件内可用）
GPIO4
通用输入/输出4
EPWM3A
增强型PWM3 输出A 和HRPWM 通道
7
-
-
-
-
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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终端
I/O/Z
说明
PT
引脚编号
DA
引脚编号
名称(1)
GPIO5
EPWM3B
-
I/O/Z
O
通用输入/输出5
增强型PWM3 输出B
-
40
41
42
47
27
26
8
ECAP1
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
EPWM4B
SCIRXDA
-
I/O
增强型捕捉输入/输出1
通用输入/输出6
增强型PWM4 输出A 和HRPWM 通道
外部ePWM 同步脉冲输入
外部ePWM 同步脉冲输出
通用输入/输出7
增强型PWM4 输出B
SCI-A 接收数据
-
I/O/Z
O
9
I
O
I/O/Z
O
10
13
35
34
I
GPIO12
TZ1
I/O/Z
通用输入/输出12
跳闸区输入1
I
SCITXDA
-
O
SCI-A 发送数据
-
GPIO16
SPISIMOA
-
I/O/Z
I/O
通用输入/输出16
SPI 从器件输入，主器件输出
-
TZ2
I
跳闸区输入2
GPIO17
SPISOMIA
-
I/O/Z
I/O
通用输入/输出17
SPI-A 从器件输出，主器件输入
-
TZ3
I
跳闸区输入3
GPIO18
SPICLKA
SCITXDA
XCLKOUT
I/O/Z
I/O
O
通用输入/输出18
SPI-A 时钟输入/输出
SCI-A 发送
O/Z
源自SYSCLKOUT 的输出时钟。XCLKOUT 频率要么与SYSCLKOUT 的频率相
同，要么是后者的一半或四分之一。这通过XCLK 寄存器中的位1:0
(XCLKOUTDIV) 控制。复位时，XCLKOUT = SYSCLKOUT/4。通过将
XCLKOUTDIV
24
32
设定为3，可关闭XCLKOUT 信号。GPIO18 的多路复用器控制也必须设定为
XCLKOUT，才能使此信号传播到引脚。
GPIO19
I/O/Z
I
通用输入/输出19
XCLKIN
外部振荡器输入。此引脚到时钟块的路径不受此引脚的多路复用器功能控制。如果
此路径用于其他外设功能，必须注意不要启用此路径来计时。
25
48
33
14
SPISTEA
SCIRXDA
ECAP1
GPIO28
SCIRXDA
SDAA
I/O
SPI-A 从器件发送使能输入/输出
SCI-A 接收
I
I/O
I/O/Z
I
增强型捕捉输入/输出1
通用输入/输出28
SCI 接收数据
I/OD
I
I2C 数据开漏双向端口
跳闸区输入2
TZ2
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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终端
I/O/Z
说明
PT
引脚编号
DA
引脚编号
名称(1)
GPIO29
I/O/Z
O
通用输入/输出29。
SCI 发送数据
SCITXDA
SCLA
1
15
I/OD
I
I2C 时钟开漏双向端口
跳闸区输入3
TZ3
GPIO32
SDAA
I/O/Z
I/OD
I
通用输入/输出32
I2C 数据开漏双向端口
增强型PWM 外部同步脉冲输入
ADC 转换启动A
31
36
19
-
EPWMSYNCI
ADCSOCAO
GPIO33
SCLA
O
I/O/Z
I/OD
O
通用输入/输出33
I2C 时钟开漏双向端口
增强型PWM 外部同步脉冲输入
ADC 转换启动B
-
EPWMSYNCO
ADCSOCBO
GPIO34
COMP2OUT
-
O
I/O/Z
O
通用输入/输出34
比较器2 的直接输出。在DA 封装中，COMP2OUT 信号不可用。
27
-
-
-
GPIO35
TDI
I/O/Z
I
通用输入/输出35
20
21
22
28
29
30
带有内部上拉电阻的JTAG 测试数据输入(TDI)。TDI 在TCK 的上升沿输入到选择
的寄存器（指令或数据）
GPIO36
TMS
I/O/Z
I
通用输入/输出36
带有内部上拉电阻的JTAG 测试模式选择(TMS)。此串行控制输入在TCK 上升沿输
入到TAP 控制器。
GPIO37
TDO
I/O/Z
O/Z
通用输入/输出37
JTAG 扫描输出，测试数据输出(TDO)。所选寄存器（指令或数据）的内容在TCK
下降沿从TDO 移出（8mA 驱动）
GPIO38
TCK
I/O/Z
通用输入/输出38
I
I
带有内部上拉电阻的JTAG 测试时钟
23
31
XCLKIN
外部振荡器输入。此引脚到时钟块的路径不受此引脚的多路复用器功能控制。如果
此路径用于其他功能，必须注意不要启用此路径来计时。
(1) I = 输入，O = 输出，Z = 高阻抗，OD = 开漏，↑= 上拉，↓= 下拉
(2) GPIO 功能（以粗斜体显示）在复位时为默认值。它们下面列出的外设信号是供替换的功能。对于GPIO 功能多路复用的JTAG 引脚，
输入到GPIO 块的路径始终有效。根据TRST 信号条件，启用/禁用从GPIO 块输出的路径和从一个引脚到JTAG 块的路径。有关详细信
息，请参阅TMS320F2802x、TMS320F2802xx 技术参考手册中的“系统控制”一章。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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8 规格
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
4.6
2.5
4.6
4.6
2.5
4.6
UNIT
VDDIO (I/O and Flash) with respect to VSS
Supply voltage
V
V
V
V
VDD with respect to VSS
Analog voltage
Input voltage
Output voltage
VDDA with respect to VSSA
VIN (3.3 V)
VIN (X1)
VO
Digital/analog input (per pin), IIK
20
20
20
–20
–20
–20
(3)
(VIN < VSS or VIN > VDDIO
)
Analog input (per pin), IIKANALOG
(VIN < VSSA or VIN > VDDA
Input clamp current
mA
)
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA
)
Output clamp current
Junction temperature(4)
Storage temperature(4)
IOK (VO < 0 or VO > VDDIO
)
20
150
150
mA
°C
–20
–40
–65
TJ
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under 节8.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see Semiconductor and IC Package Thermal Metrics; Calculating Useful Lifetimes of Embedded
Processors; and Calculating FIT for a Mission Profile.
8.2 ESD 等级- 汽车
值
单位
采用48 引脚PT 封装的TMS320F28027-Q1、TMS320F28027F-Q1、TMS320F28026-Q1、TMS320F28026F-Q1、TMS320F28023-Q1、
TMS320F28022-Q
人体放电模型(HBM)，符合AEC Q100-002(1)
±2000
所有引脚
除边角引脚以外的所有引
脚
±500
V(ESD）
V
静电放电
充电器件模型(CDM)，符合AEC Q100-011
48 引脚PT 上的转角引
脚：1、12、13、24、
25、36、37、48
±750
采用38 引脚DA 封装的TMS320F28027-Q1、TMS320F28027F-Q1、TMS320F28026-Q1、TMS320F28026F-Q1、TMS320F28023-Q1、
TMS320F28022-Q1
人体放电模型(HBM)，符合AEC Q100-002(1)
±2000
所有引脚
除边角引脚以外的所有引
脚
±500
V(ESD）
V
静电放电
充电器件模型(CDM)，符合AEC Q100-011
38 引脚DA 上的转角引
脚：1、19、20、38
±750
(1) AEC Q100-002 指示应当按照ANSI/ESDA/JEDEC JS-001 规范执行HBM 应力测试。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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8.3 ESD 等级- 商用
值
单位
采用48 引脚PT 封装的TMS320F28027-Q1、TMS320F28027F-Q1、TMS320F28026-Q1、TMS320F28026F-Q1、TMS320F28023-Q1、
TMS320F28022-Q1、TMS320F28021、TMS320F28020、TMS320F280200
人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001 标准(1)
±2000
V(ESD）
V
静电放电
充电器件模型(CDM)，符合JEDEC 规范JESD22-C101 或ANSI/
±500
ESDA/JEDEC JS-002(2)
采用38 引脚DA 封装的TMS320F28027-Q1、TMS320F28027F-Q1、TMS320F28026-Q1、TMS320F28026F-Q1、TMS320F28023-Q1、
TMS320F28022-Q1、TMS320F28021、TMS320F28020、TMS320F280200
人体放电模型(HBM)，符合ANSI/ESDA/JEDEC JS-001 标准(1)
±2000
V(ESD）
V
静电放电
充电器件模型(CDM)，符合JEDEC 规范JESD22-C101 或ANSI/
±500
ESDA/JEDEC JS-002(2)
(1) JEDEC 文件JEP155 规定：500V HBM 可实现在标准ESD 控制流程下安全生产。
(2) JEDEC 文档JEP157 指出：250V CDM 可实现在标准ESD 控制流程下安全生产。
8.4 建议工作条件
最小值
标称值
最大值
单位
(1)
2.97
3.3
3.63
V
器件电源电压，I/O，VDDIO
器件电源电压CPU，VDD（当内部VREG 禁用并且由1.8V
电源外部供电时）
1.71
2.97
1.8
1.995
V
0
3.3
0
V
V
V
电源接地，VSS
3.63
模拟电源电压，VDDA
模拟接地，VSSA
2
40
28020、28021、280200
2
50
MHz
器件时钟频率（系统时钟）
28022、28023
28026、28027
2
2
60
VDDIO+0.3
V
高电平输入电压，VIH(3.3V)
低电平输入电压，VIL(3.3V)
VSS-0.3
0.8
-4
V
mA
mA
mA
mA
所有GPIO/AIO 引脚
组2(2)
高电平输出源电流，VOH=VOH（最小值），IOH
低电平输出灌电流，VOL=VOL（最大值），IOL
-8
4
所有GPIO/AIO 引脚
组2(2)
8
-40
-40
105
125
T 版本
S 版本
(3)
°C
结温，TJ
Q 版本
（AEC Q100 认证）
-40
125
(1) 如果BOR 未被使用，那么VDDIO 可使用一个±10% 的容差。有关详细信息，请参阅TMS320F2802x、TMS320F2802xx MCU 器件勘
误表。如果BOR 被启用，VDDIO 的容差为±5%。
(2) 组2 引脚如下所示：GPIO16、GPIO17、GPIO18、GPIO19、GPIO28、GPIO29、GPIO36、GPIO37
(3) TA（环境温度）取决于产品和应用，可达到器件的指定TJ 最大值。热性能设计注意事项，请参阅节8.8。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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8.5 功耗摘要
8.5.1 TMS320F2802x/F280200 在40MHz SYSCLKOUT 下的电流消耗
VREG 启用
VREG 禁用
(2)
(3)
(2)
(3)
IDDIO
IDDA
IDD
IDDIO
IDDA
模式(1)
测试条件
典型值
(4)
典型值
(4)
典型值
(4)
典型值
(4)
典型值(4)
最大值
最大值
最大值
最大值
最大值
启用下列外设时钟：
•
•
•
•
•
•
•
•
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
ADC
工作
（闪存）
70mA
80mA
13mA
18mA
62mA
70mA
15mA
18mA
13mA
18mA
I2C
COMP1/2
CPU Timer0/1/2
所有PWM 引脚在40kHz 下切换。
所有I/O 引脚保持未连接状态。(5)
代码即将耗尽有1 个等待状态的闪存。
XCLKOUT 关闭。
闪存断电。
XCLKOUT 关闭。
所有外设时钟关闭。
13mA
3mA
16mA
6mA
15mA
3mA
17mA
6mA
53μA
10μA
10μA
58μA
15μA
15μA
120μA 400μA 53μA
120μA 400μA 10μA
58μA
15μA
15μA
空闲
待机
停机
闪存断电。
外设时钟关闭。
闪存断电。
外设时钟关闭。
输入时钟禁用。(6)
50μA
15μA
25μA
10μA
(1) 对于TMS320F280200 器件，从节8.5.1 中显示的工作模式的IDD（VREG 禁用）/IDDIO（VREG 启用）电流数字中减去eCAP 的IDD 电
流数字（参阅表8-1）。
(2)
IDDIO 电流取决于I/O 引脚上的电力负载。
(3) 要实现空闲、待机、停机模式下的IDDA 电流，必须通过写入PCLKCR0 寄存器来显式关闭ADC 模块的时钟。
(4) 典型值数字适用于室温和标称电压下。
(5) 在循环中完成以下操作：
• 数据持续从SPI-A 和SCI-A 端口中发出。
• 使用硬件乘法器。
• 复位看门狗。
•
•
ADC 执行连续转换。
COMP1/2 是连续开关电压。
• 切换GPIO17。
(6) 如果使用石英晶振或者陶瓷谐振器作为时钟源，停机模式将关闭片上晶体振荡器。
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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8.5.2 TMS320F2802x 在50MHz SYSCLKOUT 下的电流消耗
VREG 启用
VREG 禁用
(1)
(2)
(1)
(2)
IDDIO
IDDA
IDD
IDDIO
IDDA
模式
测试条件
典型值
(3)
典型值
(3)
典型值
(3)
典型值
(3)
典型值(3)
最大值
最大值
最大值
最大值
最大值
启用下列外设时钟：
•
•
•
•
•
•
•
•
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
ADC
工作
（闪存）
80mA
90mA
13mA
18mA
71mA
80mA
15mA
18mA
13mA
18mA
I2C
COMP1/2
CPU Timer0/1/2
所有PWM 引脚在40kHz 下切换。
所有I/O 引脚保持未连接状态。(4)
代码即将耗尽有1 个等待状态的闪存。
XCLKOUT 关闭。
闪存断电。
XCLKOUT 关闭。
所有外设时钟关闭。
16mA
4mA
19mA
7mA
17mA
4mA
20mA
7mA
64μA
10μA
10μA
69μA
15μA
15μA
120μA 400μA 64μA
120μA 400μA 10μA
69μA
15μA
15μA
空闲
待机
停机
闪存断电。
外设时钟关闭。
闪存断电。
外设时钟关闭。
输入时钟禁用。(5)
50μA
15μA
25μA
10μA
(1)
IDDIO 电流取决于I/O 引脚上的电力负载。
(2) 要实现空闲、待机、停机模式下的IDDA 电流，必须通过写入PCLKCR0 寄存器来显式关闭ADC 模块的时钟。
(3) 典型值数字适用于室温和标称电压下。
(4) 在循环中完成以下操作：
• 数据持续从SPI-A 和SCI-A 端口中发出。
• 使用硬件乘法器。
• 复位看门狗。
•
•
ADC 执行连续转换。
COMP1/2 是连续开关电压。
• 切换GPIO17。
(5) 如果使用石英晶振或者陶瓷谐振器作为时钟源，停机模式将关闭片上晶体振荡器。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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8.5.3 TMS320F2802x 在60MHz SYSCLKOUT 下的电流消耗
VREG 启用
VREG 禁用
(1)
(2)
(1)
(2)
IDDIO
典型值(3)
IDDA
IDD
IDDIO
IDDA
模式
测试条件
典型值
(3)
典型值
(3)
典型值
(3)
典型值(3)
最大值
最大值
最大值
最大值
最大值
启用下列外设时钟：
•
•
•
•
•
•
•
•
ePWM1/2/3/4
eCAP1
SCI-A
SPI-A
ADC
I2C
工作
（闪存）
90mA
100mA
13mA
18mA
80mA
90mA
15mA
18mA
13mA
18mA
COMP1/2
CPU-TIMER0/1/2
所有PWM 引脚在60kHz 下切
换。
所有I/O 引脚保持未连接状态。
(4)
代码即将耗尽有2 个等待状态
的闪存。
XCLKOUT 关闭。
闪存断电。
XCLKOUT 关闭。
所有外设时钟关闭。
18mA
4mA
23mA
7mA
19mA
4mA
24mA
7mA
75μA
10μA
10μA
80μA
15μA
15μA
120μA 400μA 75μA
120μA 400μA 10μA
80μA
15μA
15μA
空闲
待机
停机
闪存断电。
外设时钟关闭。
闪存断电。
外设时钟关闭。
输入时钟禁用。(5)
50μA
15μA
25μA
10μA
(1)
IDDIO 电流取决于I/O 引脚上的电力负载。
(2) 要实现空闲、待机、停机模式下的IDDA 电流，必须通过写入PCLKCR0 寄存器来显式关闭ADC 模块的时钟。
(3) 典型值数字适用于室温和标称电压下。
(4) 在循环中完成以下操作：
• 数据持续从SPI-A 和SCI-A 端口中发出。
• 使用硬件乘法器。
• 复位看门狗。
•
•
ADC 执行连续转换。
COMP1/2 是连续开关电压。
• 切换GPIO17。
(5) 如果使用石英晶振或者陶瓷谐振器作为时钟源，停机模式将关闭片上晶体振荡器。
备注
器件中实现的外设 I/O 多路复用可防止同时使用所有可用外设。这是因为多个外设功能可能共享一个
I/O 引脚。然而，可同时打开所有外设的时钟，不过此配置并无用处。如果这么做，器件消耗的电流将
大于电流消耗表中指定的数值。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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8.5.4 Reducing Current Consumption
The 2802x/280200 devices incorporate a method to reduce the device current consumption. Because each
peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved
by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of
the three low-power modes could be taken advantage of to reduce the current consumption even further. 表 8-1
indicates the typical reduction in current consumption achieved by turning off the clocks.
表8-1. Typical Current Consumption by Various
Peripherals (at 60 MHz)
PERIPHERAL
MODULE(1) (3)
IDD CURRENT
REDUCTION (mA)
ADC
2(2)
I2C
ePWM
3
2
eCAP
2
SCI
2
SPI
2
COMP/DAC
HRPWM
1
3
CPU-TIMER
Internal zero-pin oscillator
1
0.5
(1) All peripheral clocks (except CPU Timer clocks) are disabled
upon reset. Writing to/reading from peripheral registers is
possible only after the peripheral clocks are turned on.
(2) This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA) as well.
(3) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for
one ePWM module.
备注
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
备注
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 45 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the
peripherals (enabled by that application) must be added to the baseline IDD current.
Following are other methods to reduce power consumption further:
• The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18
mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
• Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
• To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of
the TMS320F2802x,TMS320F2802xx Technical Reference Manual to ensure each module is powered down
as well.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.5.5 流耗图（VREG 启用）
Operational Current vs Frequency
100
90
80
70
60
50
40
30
20
10
0
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
IDDIO (mA)
IDDA
图8-1. 典型运行电流与频率间的关系(F2802x/F280200)
Operational Power vs Frequency
450
400
350
300
250
200
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
图8-2. 典型运行功率与频率间的关系(F2802x/F280200)
8.6 电气特性
在推荐的运行条件下（除非另有说明）(1)
参数
测试条件
最小值 典型值 最大值 单位
2.4
IOH=IOH 最大值
IOH=50μA
VOH
VOL
V
高电平输出电压
低电平输出电压
VDDIO-0.2
0.4
V
IOL=IOL 最大值
-80
-140
-290
-205
所有GPIO
XRS 引脚
VDDIO=3.3V，VIN=0V
VDDIO=3.3V，VIN=0V
启用上拉的引脚
启用下拉的引脚
输入电流
（低电平）
IIL
-225
-360 μA
±2
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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在推荐的运行条件下（除非另有说明）(1)
参数
测试条件
最小值 典型值 最大值 单位
VDDIO=3.3V，VIN=VDDIO
±2
启用上拉的引脚
启用下拉的引脚
输入电流
（高电平）
IIH
μA
VDDIO=3.3V，VIN=VDDIO
VO = VDDIO 或0V
28
50
80
输出电流，上拉电阻器或者下拉电
阻器被禁用
IOZ
CI
±2
μA
2
2.65
35
pF
V
输入电容
2.42
400
3.135
800
VDDIO BOR 触发点
VDDIO BOR 滞后
下降的VDDIO
mV
μs
V
延迟时间过后，BOR/POR/OVR 事件被移除以释放XRS
内部VREG 打开
监视器复位延迟时间
1.9
VREG VDD 输出
(1) 当片上VREG 被使用时，它的输出由POR/BOR 电路监控，如果内核电压(VDD) 超出范围，此电路将复位器件。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.7 热阻特性
8.7.1 PT 封装
°C/W(1)
13.6
30.6
64
气流(lfm)(2)
RΘJC
RΘJB
结至外壳热阻
不适用
结至电路板热阻
不适用
0
50.4
48.2
45
150
250
500
0
RΘJA
（高k PCB）
结至大气热阻
结至封装顶部
结至电路板
0.56
0.94
1.1
150
250
500
0
PsiJT
1.38
30.1
28.7
28.4
28
150
250
500
PsiJB
(1) 以上值基于JEDEC 定义的2S2P 系统（基于JEDEC 定义的1S0P 系统的Theta JC [RΘJC] 值除外），将随环境和应用的变化而更
改。如需更多信息，请参阅以下EIA/JEDEC 标准：
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = 线性英尺/分钟
8.7.2 DA 封装
°C/W(1)
12.8
33
气流(lfm)(2)
RΘJC
RΘJB
结至外壳热阻
不适用
结至电路板热阻
不适用
0
70.1
56.4
53.9
50.2
0.34
0.61
0.74
0.98
32.5
32.1
31.7
31.1
150
250
500
0
RΘJA
（高k PCB）
结至大气热阻
结至封装顶部
结至电路板
150
250
500
0
PsiJT
150
250
500
PsiJB
(1) 以上值基于JEDEC 定义的2S2P 系统（基于JEDEC 定义的1S0P 系统的Theta JC [RΘJC] 值除外），将随环境和应用的变化而更
改。如需更多信息，请参阅以下EIA/JEDEC 标准：
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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(2) lfm = 线性英尺/分钟
8.8 散热设计注意事项
根据最终应用设计和运行情况，IDD 和 IDDIO 电流可能有所不同。最终产品中超过建议最大功率损耗的系统可能需
要额外的散热增强措施。环境温度 (TA) 因最终应用和产品设计而异。影响可靠性和功能性的关键因素是结温TJ，
而非环境温度。因此，应该注意将 TJ 保持在指定限值内。应该测量 Tcase 以评估运行结温 TJ。通常在封装顶部表
面的中心测量Tcase。热应用报告半导体和IC 封装热指标可帮助您了解各项热指标和相关定义。
8.9 无信号缓冲情况下MCU 与JTAG 调试探针的连接
图8-3 显示了采用单处理器配置时MCU 和JTAG 接头之间的连接。如果JTAG 接头和MCU 之间的距离大于6 英
寸，那么仿真信号必须被缓冲。如果距离小于 6 英寸，通常无需缓冲。图 8-3 显示了较简单、无缓冲的情况。对
于上拉/下拉电阻器的值，请参阅节7.2，信号说明。
6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
PD
4
6
8
TRST
TMS
TDI
GND
1
GND
GND
GND
GND
3
TDI
7
10
12
TDO
TCK
TDO
11
9
TCK
TCK_RET
MCU
JTAG Header
A. 有关JTAG/GPIO 多路复用的信息，请参阅图9-39。
图8-3. 无信号缓冲情况下MCU 与JTAG 调试探针的连接
备注
2802x 器件无 EMU0/EMU1 引脚。对于具有板载 JTAG 接头的设计，接头上的 EMU0/EMU1 引脚必须
通过一个4.7kΩ（典型值）电阻连接至VDDIO
。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.10 参数信息
8.10.1 时序参数符号
所用的时序参数符号是按照 JEDEC 标准 100 创建的。为了缩短符号，有些引脚名称和其他相关术语已如下缩
写：
小写下标及其
意义：
字母和符号及其
意义：
a
c
d
f
H
L
访问时间
高
周期时间（周期）
延迟时间
低
V
X
Z
有效
下降时间
未知、改变或者不关心级别
高阻抗
h
r
保持时间
上升时间
su
t
建立时间
转换时间
v
w
有效时间
脉冲持续时间（宽度）
8.10.2 定时参数的通用注释
所有 28x 器件的输出信号（包括 XCLKOUT）取自一个内部时钟，这样，对于一个指定半周期的所有输出转换在
一个互相之间相对最小转换率时发生。
这个显示在下面时序图中的信号组合也许不一定代表真实的周期。对于真实周期范例，请参见本文档的合适周期
说明部分。
8.11 测试负载电路
此测试负载电路用于测量本文档中提供的所有开关特性。
Tester Pin Electronics
Data Sheet Timing Reference Point
W
3.5 nH
Output
Under
Test
42
Transmission Line
(A)
Z0 = 50 W
Device Pin(B)
4.0 pF
1.85 pF
A. 此数据表中的输入要求是在器件引脚上以小于每纳秒4 伏(4V/ns) 的输入转换率测试得出的。
B. 此数据表提供器件引脚上的时序。在分析输出时序时，必须考虑测试仪引脚电子元件及其传输线路影响。可使用具有2ns 或更长延迟时
间的传输线路实现所需的传输线路效果。传输线路只用作负载。无需从数据表时序中增加或者减去传输线路延迟（2ns 或者更长）。
图8-4. 3.3V 测试负载电路
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
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8.12 电源时序
复位后无需电源时序来确保器件处于正常状态或者防止上电/下电期间的 I/O 上的毛刺脉冲（GPIO19、GPIO34–
38 上没有无毛刺脉冲 I/O）。在器件上电之前，不应将 VDDIO 之上大于二极管压降 (0.7V) 的电压应用于任何数字
引脚（对于模拟引脚，此值是高于 VDDA 0.7V 的电压值）。应用于未加电器件的引脚上的电压会以一种无意的方
式偏置内部p-n 接头并产生无法预料的结果。
VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
t
w(RSL1)
XRS(D)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
User-code execution phase
User-code dependent
t
d(EX)
(C)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Peripheral/GPIO function
Boot-ROM execution starts
(E)
Based on boot code
GPIO pins as input (state depends on internal PU/PD)
I/O Pins
User-code dependent
A. 上电时，SYSCLKOUT 为OSCCLK/4。由于XCLK 寄存器内的XCLKOUTDIV 位出现复位状态0，SYSCLKOUT 在出现在XCLKOUT
上之前会进一步除以4。这个状态期间，XCLKOUT=OSCCLK/16。
B. 引导ROM 将DIVSEL 位配置为/1 运行。在这个状态期间，XCLKOUT=OSCCLK/4。XCLKOUT 只有通过用户代码明确配置，才会显示
在引脚上。
C. 复位后，引导ROM 代码采样引导模式引脚。基于引导模式引脚的状态，引导代码向目的内存或者引导代码函数下达分支指令。如果引导
ROM 代码在加电条件后（在调试器环境中）执行代码，引导代码执行时间由当前的SYSCLKOUT 的速度而定。SYSCLKOUT 将基于用
户环境并可在PLL 启用或者不启用时使用。
D. 由于片上加电复位(POR) 电路，使用XRS 引脚是可选的。
E. 当BOR 被驱动为高电平，内部上拉/下拉将起作用。
图8-5. 加电复位
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.12.1 复位(XRS) 时序要求
最小值
最大值
单位
周期
周期
th（引导模式）
tw(RSL2)
1000tc(SCO)
引导模式引脚的保持时间
32tc(OSCCLK)
脉冲持续时间，热复位时XRS 处于低电平
8.12.2 复位(XRS) 开关特性
在推荐的运行条件下（除非另有说明）
参数
测试条件
最小值
典型值 最大值
单位
tw(RSL1)
tw(WDRS)
td(EX)
600
脉冲持续时间，XRS 由器件驱动
脉冲持续时间，由看门狗生成复位脉冲
延迟时间，XRS 高电平后，地址/数据有效
启动时间，内部零引脚振荡器
μs
512tc(OSCCLK)
周期
周期
μs
32tc(OSCCLK)
tINTOSCST
3
(1)
tOSCST
1
10
ms
片上晶体振荡器启动时间
(1) 取决于晶体/谐振器和电路板设计。
INTOSC1
X1/X2
XCLKOUT
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
User-Code Execution
Control
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. 复位后，引导ROM 代码采样引导模式引脚。基于引导模式引脚的状态，引导代码向目的内存或者引导代码函数下达分支指令。如果引导
ROM 代码在加电条件后（在调试器环境中）执行代码，引导代码执行时间由当前的SYSCLKOUT 的速度而定。SYSCLKOUT 将基于用
户环境并可在PLL 启用或者不启用时使用。
图8-6. 热复位
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图 8-7 显示了写入 PLLCR 寄存器所产生的效果的一个示例。在第一个阶段，PLLCR = 0x0004 且 SYSCLKOUT
= OSCCLK x 2。然后写入 0x0008 到 PLLCR。就在 PLLCR 寄存器被写入后，PLL 锁存阶段开始。在此阶段，
SYSCLKOUT = OSCCLK/2。在PLL 锁存完成后，SYSCLKOUT 表示新的运行频率，OSCCLK x 4。
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
(Current CPU
Frequency)
(Changed CPU frequency)
图8-7. 写入PLLCR 寄存器所产生的结果的示例
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.13 时钟规范
8.13.1 器件时钟表
此部分介绍 2802x MCU 上可用的不同时钟选项的定时要求和开关特性。节 8.13.1.1、节 8.13.1.2 和 节 8.13.1.3
列出了不同时钟的周期时间。
8.13.1.1 2802x 时钟表和命名规则（40MHz 器件）
最小值
25
标称值
最大值
500
单位
ns
tc(SCO)，周期时间
频率
SYSCLKOUT
LSPCLK(1)
2
40
MHz
ns
25
100(2)
10(2)
tc(LCO)，周期时间
频率
40
40
MHz
ns
25
tc(ADCCLK)，周期时间
频率
ADC 时钟
MHz
(1) 更低的LSPCLK 将减少器件功耗。
(2) 如果SYSCLKOUT=40MHz，这个值为缺省复位值。
8.13.1.2 2802x 时钟表和命名规则（50MHz 器件）
最小值
20
标称值
最大值
500
单位
ns
tc(SCO)，周期时间
SYSCLKOUT
2
50
MHz
ns
频率
20
80(2)
tc(LCO)，周期时间
LSPCLK(1)
12.5(2)
50
50
MHz
ns
频率
20
tc(ADCCLK)，周期时间
ADC 时钟
MHz
频率
(1) 更低的LSPCLK 将减少器件功耗。
(2) 如果SYSCLKOUT=50MHz，这个值为缺省复位值。
8.13.1.3 2802x 时钟表和命名规则（60MHz 器件）
最小值
16.67
2
标称值
最大值
500
单位
ns
tc(SCO)，周期时间
SYSCLKOUT
60
MHz
ns
频率
16.67
66.67(2)
15(2)
tc(LCO)，周期时间
LSPCLK(1)
60
60
MHz
ns
频率
16.67
tc(ADCCLK)，周期时间
ADC 时钟
MHz
频率
(1) 更低的LSPCLK 将减少器件功耗。
(2) 如果SYSCLKOUT=60MHz，这个值为缺省复位值。
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.13.1.4 器件计时要求/特性
最小值
标称值
最大值
单位
ns
50
5
200
20
tc(OSC)，周期时间
频率
片上振荡器（X1/X2 引脚）
（晶振/谐振器）
MHz
ns
33.3
5
200
30
tc(CI)，周期时间(C8)
频率
外部振荡器/时钟源
（XCLKIN 引脚）—PLL 启用
MHz
ns
33.33
4
250
30
tc(CI)，周期时间(C8)
频率
外部振荡器/时钟源
（XCLKIN 引脚）—PLL 禁用
MHz
跛行模式SYSCLKOUT
（/2 启用）
MHz
1 至5
频率范围
66.67
0.5
2000
15
ns
MHz
ms
tc(XCO)，周期时间(C1)
XCLKOUT
频率
PLL 锁定时间(1)
tp
1
(1) PLLLOCKPRD 寄存器必须按照OSCCLK 周期的数量进行更新。如果内部零引脚振荡器(10MHz) 被用作时钟源，那么必须将值10,000
（最小值）写入PLLLOCKPRD 寄存器。
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.13.1.5 内部零引脚振荡器(INTOSC1/INTOSC2) 特性
参数
内部零引脚振荡器1 (INTOSC1)(1) (2)
内部零引脚振荡器2 (INTOSC2)(1) (2)
步长尺寸（粗调）
最小值
典型值
最大值
单位
10
MHz
频率
频率
10
55
MHz
kHz
kHz
14
步长尺寸（微调）
温度漂移(3)
3.03
175
4.85 kHz/°C
Hz/mV
电压(VDD) 漂移(3)
(1) 振荡器频率将随温度变化，请参阅图8-8。要补偿振荡器温度漂移，请参阅振荡器补偿指南和C2000Ware。
(2) 只有当VREG 被启用时，才能确保频率范围，VREGENZ=VSS。
(3) 内部振荡器的输出频率由温度梯度和电压(VDD) 梯度确定。例如：
• 温度的上升将引起输出频率按照温度系数增加。
• 电压的下降(VDD) 将引起输出频率按照电压系数下降。
Zero-Pin Oscillator Frequency Movement With Temperature
10.6
10.5
10.4
10.3
10.2
10.1
10
9.9
9.8
9.7
9.6
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
Typical
Max
Temperature (°C)
图8-8. 随温度变化而变化的零引脚振荡器频率
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8.13.2 时钟要求和特性
8.13.2.1 XCLKIN 定时要求- PLL 已启用
编号
最小值
最大值
单位
C9
tf(CI)
6
6
ns
下降时间，XCLKIN
C10
C11
C12
tr(CI)
ns
上升时间，XCLKIN
tw(CIL)
tw(CIH)
45%
45%
55%
55%
脉冲持续时间，XCLKIN 低电平为tc(OSCCLK) 的一个百分比
脉冲持续时间，XCLKIN 高电平为tc(OSCCLK) 的一个百分比
8.13.2.2 XCLKIN 时序要求- PLL 已禁用
编号
最小值
最大值
单位
6
高达20MHz
C9
tf(Cl)
ns
下降时间，XCLKIN
上升时间，XCLKIN
2
6
2
20MHz 至30MHz
高达20MHz
C10 tr(CI)
ns
20MHz 至30MHz
脉冲持续时间，XCLKIN 低电平为tc(OSCCLK) 的一个百分
比
C11
tw(CIL)
45%
45%
55%
55%
脉冲持续时间，XCLKIN 高电平为tc(OSCCLK) 的一个百分
比
C12 tw(CIH)
表9-16 中显示了可能的配置模式。
8.13.2.3 XCLKOUT 开关特性（旁路或启用PLL）
在推荐的运行条件下（除非另有说明）(1) (2)
编号
参数
最小值
最大值
单位
C3
tf(XCO)
11
ns
下降时间，XCLKOUT
上升时间，XCLKOUT
C4
C5
C6
tr(XCO)
11
H + 2
H + 2
ns
ns
ns
tw(XCOL)
tw(XCOH)
脉冲持续时间，XCLKOUT 低电平
脉冲持续时间，XCLKOUT 高电平
H –2
H –2
(1) 这些参数假定有40pF 负载。
(2) H = 0.5tc(XCO)
C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. XCLKIN 与XCLKOUT 的关系取决于所选择的分频系数。所示波形关系仅用于说明时序参数，可能因实际配置而异。
B. 已配置XCLKOUT 以反映SYSCLKOUT。
图8-9. 时钟时序
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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8.14 闪存定时
8.14.1 T 温度材料的闪存/OTP 耐久性
温度
擦除/编程(1)
最小值
典型值
最大值
单位
Nf
20000
50000
闪存对于阵列的耐受度（写入/擦除周期）
0°C 至105°C（环境温度）
0°C 至30°C（环境温度）
周期
写入
NOTP
1
OTP 对于阵列的耐受度（写入周期）
(1) 所示温度范围之外的写入/擦除操作并未说明，有可能影响耐受数。
8.14.2 S 温度材料的闪存/OTP 耐久性
温度
擦除/编程(1)
最小值
典型值
最大值
单位
Nf
20000
50000
闪存对于阵列的耐受度（写入/擦除周期）
OTP 对于阵列的耐受度（写入周期）
0°C 至125°C（环境温度）
0°C 至30°C（环境温度）
周期
写入
NOTP
1
(1) 所示温度范围之外的写入/擦除操作并未说明，有可能影响耐受数。
8.14.3 Q 温度材料的闪存/OTP 耐久性
温度
擦除/编程(1)
最小值
典型值
最大值
单位
周期
Nf
闪存对于阵列的耐受度（写入/擦除周期）
OTP 对于阵列的耐受度（写入周期）
-40°C 至125°C（环境温
度）
20000
50000
NOTP
-40°C 至30°C（环境温
度）
写入
1
(1) 所示温度范围之外的写入/擦除操作并未说明，有可能影响耐受数。
8.14.4 60MHz SYSCLKOUT 下的闪存参数
参数
测试条件
最小值
典型值
最大值
单位
(1)
IDDP
80
60
mA
擦除/编程周期内的VDD 流耗
擦除/编程周期内的VDDIO 流耗
擦除/编程周期内的VDDIO 流耗
VREG 禁用
(1)
(1)
IDDIOP
IDDIOP
mA
mA
120
VREG 启用
(1) 室温下包括函数调用开销在内的典型参数，是在所有外设关闭时的参数。在整个闪存编程过程中保持稳定的电源很重要。可想而知，闪
存编程期间的器件电流消耗可能高于正常工作条件下。如数据表“建议工作条件”中所述，使用的电源应始终确保VMIN 位于电源轨上。
擦除/编程过程中发生任何欠压保护或电源中断，都可能会损坏密码位置并永久锁定器件。不建议通过USB 端口为目标板供电（在闪存
编程期间），因为该端口可能无法响应编程过程中设置的电源需求。
8.14.5 50MHz SYSCLKOUT 上的闪存参数：
参数
测试条件
VREG 禁用
VREG 启用
最小值 典型值 最大值 单位
(1)
IDDP
IDDIOP
IDDIOP
70
擦除/编程周期内的VDD 流耗
擦除/编程周期内的VDDIO 流耗
擦除/编程周期内的VDDIO 流耗
mA
mA
(1)
(1)
60
110
(1) 室温下包括函数调用开销在内的典型参数，是在所有外设关闭时的参数。在整个闪存编程过程中保持稳定的电源很重要。可想而知，闪
存编程期间的器件电流消耗可能高于正常工作条件下。如数据表“建议工作条件”中所述，使用的电源应始终确保VMIN 位于电源轨上。
擦除/编程过程中发生任何欠压保护或电源中断，都可能会损坏密码位置并永久锁定器件。不建议通过USB 端口为目标板供电（在闪存
编程期间），因为该端口可能无法响应编程过程中设置的电源需求。
8.14.6 40MHz SYSCLKOUT 上的闪存参数：
参数
测试条件
VREG 禁用
最小值 典型值 最大值 单位
(1)
IDDP
IDDIOP
60
擦除/编程周期内的VDD 流耗
擦除/编程周期内的VDDIO 流耗
mA
(1)
60
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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参数
测试条件
VREG 启用
最小值 典型值 最大值 单位
100 mA
(1)
IDDIOP
擦除/编程周期内的VDDIO 流耗
(1) 室温下包括函数调用开销在内的典型参数，是在所有外设关闭时的参数。在整个闪存编程过程中保持稳定的电源很重要。可想而知，闪
存编程期间的器件电流消耗可能高于正常工作条件下。如数据表“建议工作条件”中所述，使用的电源应始终确保VMIN 位于电源轨上。
擦除/编程过程中发生任何欠压保护或电源中断，都可能会损坏密码位置并永久锁定器件。不建议通过USB 端口为目标板供电（在闪存
编程期间），因为该端口可能无法响应编程过程中设置的电源需求。
8.14.7 闪存编程/擦除时间
最大值
(2)
参数
测试条件
最小值 典型值
单位
编程时间(1)
擦除时间(3)
8K 扇区
4K 扇区
16 位字
8K 扇区
4K 扇区
250
125
50
2
2000
2000
ms
ms
μs
s
12
12
2
s
(1) 编程时间是最大器件频率下的值。此表中指示的编程时间仅适用于器件RAM 中的所有必需代码/数据都可用并准备好进行编程的情况。
编程时间包括闪存状态机的开销，但不包括将以下项传输到RAM 的时间：
• 使用闪存API 对闪存进行编程的代码
• 闪存API 本身
• 要进行编程的闪存数据
(2) 所提到的最大闪存参数对应于前100 个编程和擦除周期。
(3) 当器件从TI 出货时，片上闪存存储器处于一个被擦除状态。这样，当首次编辑器件时，在编程前无需擦除闪存存储器。然而，对于所有
随后的编程操作，需要执行擦除操作。
8.14.8 闪存/ OTP 访问时序
参数
最小值
40
最大值 单位
ta(fp)
ns
ns
页式闪存访问时间
随机闪存访问时间
OTP 访问时间
ta(fr)
40
ta(OTP)
60
ns
8.14.9 Flash Data Retention Duration
PARAMETER
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX UNIT
tretention
Data retention duration
years
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表8-2. Minimum Required Flash/OTP Wait States at Different Frequencies
SYSCLKOUT
SYSCLKOUT
(ns)
PAGE
RANDOM
OTP
WAIT STATE
(MHz)
WAIT STATE(1)
WAIT STATE(1)
60
16.67
18.18
20
2
2
1
1
1
1
1
0
2
2
1
1
1
1
1
1
3
3
2
2
2
2
1
1
55
50
45
22.22
25
40
35
28.57
33.33
40
30
25
(1) Random wait state must be ≥1.
The equations to compute the Flash page wait state and random wait state in 表8-2 are as follows:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(f ·p)
Flash Page Wait State =
-1 round up to the next highest integer
ú
tc(SCO)
ê
ú
û
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(f ×r)
Flash Random Wait State =
-1 round up to the next highest integer, or 1, whichever is larger
ú
tc(SCO)
ê
ú
û
The equation to compute the OTP wait state in 表8-2 is as follows:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(OTP)
OTP Wait State =
-1 round up to the next highest integer, or 1, whichever is larger
ú
tc(SCO)
ê
ú
û
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9 详细说明
9.1 Overview
9.1.1 CPU
2802x (C28x) 系列是 TMS320C2000™ 微控制器 (MCU) 平台的成员。基于 C28x 的控制器具有与现有 C28x
MCU 一样的32 位定点架构。它是一款高效的 C/C++ 引擎，不仅支持用户使用高级语言开发控制软件，还支持使
用 C/C++ 开发数学算法。此器件在处理 MCU 算术任务时与处理系统控制任务时同样有效，而系统控制任务通常
由微控制器器件处理。鉴于此器件具有高效率，无需像很多系统一样使用第二个处理器。利用32 x 32 位MAC 64
位处理能力，控制器能够高效地处理更高的数值分辨率问题。添加了带有关键寄存器自动环境保存的快速中断响
应，使得一个器件能够用最小的延迟处理很多异步事件。此器件有一个具有流水线式存储器访问的 8 级深受保护
流水线。这个流水线式操作使得此器件能够在高速执行而无需求助于昂贵的高速存储器。特别分支超前硬件大大
减少了条件不连续而带来的延迟。特别存储条件操作进一步提升了性能。
9.1.2 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.
The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist of
32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations. The
multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data
value and write a data value in a single cycle. All peripherals and memories attached to the memory bus
prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
9.1.3 外设总线
为了在多种德州仪器 (TI) MCU 器件系列间实现外设迁移，此器件采用一个针对外设互连的外设总线标准。外设总
线桥对各个总线进行多路复用，使处理器内存总线成为包含 16 条地址线和 16 条或 32 条数据线及关联控制信号
的单个总线。支持外设总线的三个版本。一个版本只支持 16 位访问（被称为外设帧 2）。另外版本支持 16 位和
32 位访问（被称为外设帧1）。
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TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.1.4 Real-Time JTAG and Analysis
1
The devices implement the standard IEEE 1149.1 JTAG interface for in-circuit based debug. Additionally, the
devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and
register locations while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time-critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to
the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that
allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable
break events when a match occurs. These devices do not support boundary scan; however, IDCODE and
BYPASS features are available if the following considerations are taken into account. The IDCODE does not
come by default. The user must go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the
IDCODE. For BYPASS instruction, the first shifted DR value would be 1.
9.1.5 Flash
The F280200 device contains 8K × 16 of embedded flash memory, segregated into two 4K × 16 sectors. The
F28021/23/27 devices contain 32K × 16 of embedded flash memory, segregated into four 8K × 16 sectors. The
F28020/22/26 devices contain 16K × 16 of embedded flash memory, segregated into four 4K × 16 sectors. All
devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to 0x3D 7BFF. The user can
individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not
possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors.
Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP
is mapped to both program and data space; therefore, it can be used to execute code or store data information.
Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data variables and should not contain program code.
备注
The Flash and OTP wait states can be configured by the application. This allows applications running
at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait state, and OTP wait-state registers, see the
System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
9.1.6 M0，M1 SARAM
所有器件包含这两块单周期访问内存，每一个的大小为 1K x 16。复位时，堆栈指针指向块 M1 的开始位置。M0
和M1 块，与所有其它C28x 器件上的内存块一样，被映射到程序和数据空间。因此，用户能够使用M0 和M1 来
执行代码或者用于数据变量。分区在连接器内执行。C28x 器件提供了一个到编程器的统一内存映射。这使得用高
级语言编程变得更加容易。
9.1.7 L0 SARAM
此器件包含高达 4K x 16 的单周期访问 RAM。请参考节 9.2 中的器件专用内存映射图表来确定一个指定器件的准
确大小。这个块被映射到程序和数据空间。
1
IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.1.8 Boot ROM
The Boot ROM is factory-programmed with bootloader software. The Boot ROM uses the boot-mode-select
GPIO pins to determine what boot mode to use upon power up. The user can select to boot normally to
application code, to download new software from an external connection, or to select boot software that is
programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS
waveforms, for use in math-related algorithms. The boot-ROM content, and hence the checksum value, may
vary for different silicon revisions. For details, see the Boot ROM chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
表9-1. Boot Mode Selection
MODE
GPIO37/TDO
GPIO34/COMP2OUT
TRST
MODE
3
2
1
1
0
0
x
1
0
1
0
x
0
0
0
0
1
GetMode
Wait (see 节9.1.9 for description)
1
SCI
0
Parallel IO
Emulation Boot
EMU
9.1.8.1 仿真引导
连接 JTAG 调试探针时，无法使用 GPIO37/TDO 引脚进行引导模式选择。在这种情况下，引导 ROM 会检测已连
接 JTAG 调试探针，并使用 PIE 向量表中的两个保留 SARAM 位置内容来确定引导模式。如果两个位置内的内容
均无效，那么使用等待引导选项。可在仿真引导中访问所有引导模式选项。
9.1.8.2 GetMode
GetMode 的缺省运行状态选项为引导至闪存。通过在 OTP 中设定两个位置，这个运行状态能够被改变为其它的
引导选项。如果两个 OTP 位置的内容均为无效，那么引导至闪存。可以指定以下加载程序之一：SCI、SPI、I2C
或OTP。
9.1.8.3 引导加载器使用的外设引脚
表 9-2 显示了每一个外设引导加载器所使用的 GPIO 引脚。请参阅 GPIO 多路复用器表以检查这些引脚是否与您
希望在应用中使用的任一外设冲突。
表9-2. 外设引导加载引脚
引导加载器
外设加载器引脚
SCI
SCIRXDA (GPIO28)
SCITXDA (GPIO29)
并行引导
数据(GPIO[7:0])
28x 控制(GPIO16)
主机控制(GPIO12)
SPI
I2C
SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
SDAA (GPIO32)(1)
SCLA (GPIO33)(1)
(1) 在您的器件封装上，GPIO 引脚32 和33 也许不可用。在这些器件上，这个引导加载选项不可用。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.1.9 Security
The devices support high levels of security to protect the user firmware from being reverse engineered. The
security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One
code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature
prevents unauthorized users from examining the memory contents through the JTAG port or trying to boot-load
some undesirable software that would export the secure memory contents. To enable access to the secure
blocks, the user must write the correct 128-bit KEY value that matches the value stored in the password
locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized
users from stepping through secure code. Any code or data access to flash, user OTP, or L0 memory while the
JTAG debug probe is connected will trip the ECSL and break the debug probe connection. To allow debug of
secure code, while maintaining the CSM protection against secure memory reads, the user must write the
correct value into the lower 64 bits of the KEY register (KEY0 - KEY3), which matches the value stored in the
lower 64 bits of the password locations (PWL0 - PWL3) within the flash. Dummy reads of all 128 bits of the
password in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match. During debug of secure code, operations like
single-stepping is possible. However, the actual contents of the secure memory cannot be seen in the CCS
window.
When power is applied to a secure device that is connected to a JTAG debug probe, the CPU will start executing
and may execute an instruction that performs an access to a protected area. If this happens, the ECSL will trip
and cause the JTAG circuitry to be deactivated. Under this condition, a host (such as a computer running CCS or
flash programing software) would not be able to establish connection with the device.
The solution is to use the Wait boot option. In this mode, the device loops around a software breakpoint to allow
a JTAG debug probe to be connected without tripping security. The user can then exit this mode once the JTAG
debug probe is connected by using one of the emulation boot options as described in the Boot ROM chapter in
the TMS320F2802x,TMS320F2802xx Technical Reference Manual. These devices do not support a hardware
wait-in-reset mode.
备注
• When the code-security passwords are programmed, all addresses from 0x3F7F80 to 0x3F7FF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
• If reprogramming of a secure device via JTAG may be needed in future, it is important to design
the board in such a way that the device could be put in Wait boot mode upon power-up (when
reprogramming is warranted). Otherwise, ECSL may deactivate the JTAG circuitry and prevent
connection to the device, as mentioned earlier. If reconfiguring the device for Wait boot mode in the
field is not practical, some mechanism must be implemented in the firmware to detect when a
firmware update is warranted. Code could then branch to the desired bootloader in the bootROM. It
could also branch to the Wait bootmode, at which point the JTAG debug probe could be connected,
device unsecured and programming accomplished through JTAG itself.
• If the code security feature is not used, addresses 0x3F7F80 to 0x3F7FEF may be used for code
or data. Addresses 0x3F7FF0 to 0x3F7FF5 are reserved for data and should not contain program
code.
The 128-bit password (at 0x3F 7FF8 to 0x3F 7FFF) must not be programmed to zeros. Doing so
would permanently lock the device.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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备注
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR
FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
9.1.10 外设中断扩展(PIE) 块
PIE 块将许多中断源复用至中断输入的较小的集合中。PIE 块能够支持多达 96 个外设中断。在 F2802x 上，外设
使用96 个可能中断中的 33 个。96 个中断被分成 8 组，每组被提供 12 个CPU 中断线（INT1 或者INT12）中的
1 个。96 个中断中的每一个中断由其存储在一个可被用户写覆盖的专用 RAM 块中的矢量支持。在处理这个中断
时，这个矢量由 CPU 自动抽取。抽取这个矢量以及保存关键CPU 寄存器将花费 8 个CPU 时钟周期。因此 CPU
能够对中断事件作出快速响应。可以通过硬件和软件控制中断的优先级。每个中断都可以在PIE 块内启用/禁用。
9.1.11 外部中断(XINT1-XINT3)
此器件支持 3 个被屏蔽的外部中断 (XINT1-XINT3)。每一个中断可被选择成负边沿、正边沿、或者二者触发并能
够被启用/禁用。这些中断还包含一个 16 位自由运行的上数计数器，当检测到一个有效的中断边沿时，该计数器
复位为 0。这个计数器可被用于为中断精确计时。没有用于外部引脚的专用引脚。XINT1，XINT2，和 XINT3 中
断可接受来自GPIO0-GPIO3 引脚的输入。
9.1.12 内部零引脚振荡器、振荡器和PLL
此器件可由两个内部零引脚振荡器、一个外部振荡器或者一个连接至片上振荡器电路（只适用于 48 引脚器件）的
晶体中的任一个计时。一个提供的 PLL 支持高达 12 个输入时钟缩放比。PLL 比率可用软件中在器件运行时更
改，这使得用户在需要低功耗运行时能够按比例降低运行频率。请参阅节8，电气规格，了解时序详细信息。PLL
块可被设定为旁路模式。
9.1.13 看门狗
每个器件包含两个看门狗：一个是监视内核的 CPU 看门狗，一个是 NMI 看门狗，后者是时钟丢失检测电路。用
户软件必须在特定的时间范围内定期复位 CPU 看门狗计数器；否则，CPU 看门狗将生成对处理器的复位。必要
时可禁用CPU 看门狗。NMI 看门狗仅在发生时钟故障时才起作用，可生成一个中断或者器件复位。
9.1.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to
the CPU clock.
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9.1.15 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
must function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer
will wake the processor from IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
This mode basically shuts down the device and places it in the lowest possible power consumption mode. If the
internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep
these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU watchdog in this mode. If the on-chip crystal oscillator is used as
the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU
watchdog can wake the device from this mode.
The CPU clock (OSCCLK) and watchdog clock source should be from the same clock source before attempting
to put the device into HALT or STANDBY.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.1.16 外设帧0，1，2 (PFn)
此器件将外设分成3 个部分。外设映射如下：
PF0：
PIE：
PIE 中断启用和控制寄存器加上PIE 矢量表
闪存写入状态寄存器
闪存：
定时器：
CSM：
ADC：
GPIO：
ePWM：
eCAP：
比较器：
SYS：
SCI：
CPU - 定时器0，1，2 寄存器
代码安全模块KEY 寄存器
ADC 结果寄存器
PF1：
PF2：
GPIO MUX 配置和控制寄存器
增强型脉冲宽度调制器模块和寄存器
增强型捕捉模块和寄存器
比较器模块：
系统控制寄存器
串行通信接口(SCI) 控制和RX/TX 寄存器
串行端口接口(SPI) 和RX/TX 寄存器
ADC 状态、控制、和配置寄存器
集成电路间模块和寄存器
外部中断寄存器
SPI：
ADC：
IC2：
XINT：
9.1.17 通用输入/输出(GPIO) 复用器
大多数的外设信号与通用输入/输出 (GPIO) 信号复用。这使得用户能够在外设信号或者功能不使用时将一个引脚
用作GPIO。复位时，GPIO 引脚被配置为输入。针对GPIO 模式或者外设信号模式，用户能够独立设定每一个引
脚。对于特定的输入，用户也可以选择输入限定周期的数量。这是为了过滤掉有害的噪音毛刺脉冲。GPIO 信号也
可被用于使器件脱离特定低功耗模式。
9.1.18 32 位CPU 定时器(0，1，2)
CPU 定时器 0，1，和 2 是完全一样的 32 位定时器，这些定时器带有可预先设定的周期和 16 位时钟预分频。此
定时器有一个32 位倒计数寄存器，此寄存器在计数器达到0 时生成一个中断。这个计数器的减量为被预分频值设
置所分频的CPU 时钟速度的值。当此计数器达到0 时，它自动重新载入一个32 位的周期值。
CPU 定时器 0 为通用定时器并被连接至 PIE 块。CPU 定时器 1 为通用定时器并被连接至 CPU 的 INT13。CPU
定时器2 为DSP/BIOS 保留。它被连接至CPU 的INT14。如果DSP/BIOS 未被使用，CPU 定时器2 也可称为通
用定时器。
CPU 定时器2 可由下列任一器件计时：
• SYSCLKOUT（默认）
• 内部零引脚振荡器1 (INTOSC1)
• 内部零引脚振荡器2 (INTOSC2)
• 外部时钟源
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.1.19 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-
band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins
support the HRPWM high resolution duty and period features. The type 1 module found on 2802x devices
also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced
triggering including trip functions based on comparator outputs.
eCAP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
ADC:
The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned out, depending on the
device. It contains two sample-and-hold units for simultaneous sampling.
Comparator:
Each comparator block consists of one analog comparator along with an internal 10-bit reference for
supplying one input of the comparator.
9.1.20 串行端口外设
此器件支持下列的串行通信外设：
SPI：
SPI 是一个高速同步串行I/O 端口，此端口允许编程长度（1 至16 位）的串行位流以可编程的位传输速率移入
和移出器件。通常，SPI 用于MCU 和外部外设或者其他处理器之间的通信。典型应用包括外部I/O 或者通过诸
如移位寄存器、显示驱动器和ADC 等器件进行外设扩展。多器件通信由SPI 的主/从操作支持。SPI 包含用于
减少中断服务开销的4 级接收和发送FIFO。
SCI：
I2C：
串行通信接口是一种双线制异步串行端口，通常称为UART。SCI 包含用于减少中断服务开销的4 级接收和发
送FIFO。
内部集成电路(I2C) 模块在MCU 与符合Philips Semiconductors 内部集成电路总线（I2C 总线®）规范版本2.1
并通过I2C 总线连接的其他器件之间提供一个接口。该双线串行总线上连接的外部元件可以通过I2C 模块向
MCU 发送/从MCU 接收多达8 位数据。I2C 包含用于减少中断服务开销的4 级接收和发送FIFO。
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.2 Memory Maps
In 图9-1, 图9-2, 图9-3, 图9-4, and 图9-5, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory
only. A user program cannot access these memory maps in program space.
• Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x3D7C80 to 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(4K ´ 16, Protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x00 9000
0x3D 7800
0x3D 7C00
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
0x3D 7C80
0x3D 7CC0
0x3D 7CE0
0x3D 7E80
Calibration Data
Get_mode function
Reserved
Calibration Data
Reserved
0x3D 7EB0
0x3D 7FFF
PARTID
0x3D 8000
0x3F 0000
Reserved
FLASH
(32K ´ 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 9000
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
图9-1. 28023-Q1/28027-Q1 Memory Map
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(4K ´ 16, Protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x00 9000
0x3D 7800
0x3D 7C00
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
0x3D 7C80
0x3D 7CC0
Calibration Data
Get_mode function
Reserved
0x3D 7CE0
0x3D 7E80
Calibration Data
Reserved
0x3D 7EB0
0x3D 7FFF
PARTID
0x3D 8000
0x3F 4000
Reserved
FLASH
(16K ´ 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 9000
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
图9-2. 28022-Q1/28026-Q1 Memory Map
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(4K ´ 16, Protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (3K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x00 8C00
0x3D 7800
0x3D 7C00
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
0x3D 7C80
0x3D 7CC0
Calibration Data
Get_mode function
Reserved
0x3D 7CE0
0x3D 7E80
Calibration Data
Reserved
0x3D 7EB0
0x3D 7FFF
PARTID
0x3D 8000
0x3F 0000
Reserved
FLASH
(32K ´ 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (3K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 8C00
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
图9-3. 28021 Memory Map
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(4K ´ 16, Protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x00 8400
0x3D 7800
0x3D 7C00
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
0x3D 7C80
0x3D 7CC0
0x3D 7CE0
0x3D 7E80
Calibration Data
Get_mode function
Reserved
Calibration Data
Reserved
0x3D 7EB0
0x3D 7FFF
PARTID
0x3D 8000
0x3F 4000
Reserved
FLASH
(16K ´ 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 8400
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
图9-4. 28020 Memory Map
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(4K ´ 16, Protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x00 8400
0x3D 7800
0x3D 7C00
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
0x3D 7C80
0x3D 7CC0
Calibration Data
Get_mode function
Reserved
0x3D 7CE0
0x3D 7E80
Calibration Data
Reserved
0x3D 7EB0
0x3D 7FFF
PARTID
0x3D 8000
0x3F 6000
Reserved
FLASH
(8K ´ 16, 2 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual Mapped)
0x3F 8400
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.
图9-5. 280200 Memory Map
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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表9-3. Addresses of Flash Sectors in F28021/28023-Q1/28027-Q1
ADDRESS RANGE
0x3F 0000 to 0x3F 1FFF
0x3F 2000 to 0x3F 3FFF
0x3F 4000 to 0x3F 5FFF
0x3F 6000 to 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (8K × 16)
Sector C (8K × 16)
Sector B (8K × 16)
Sector A (8K × 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 to 0x3F 7FF5
0x3F 7FF6 to 0x3F 7FF7
0x3F 7FF8 to 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
表9-4. Addresses of Flash Sectors in F28020/28022-Q1/28026-Q1
ADDRESS RANGE
0x3F 4000 to 0x3F 4FFF
0x3F 5000 to 0x3F 5FFF
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (4K × 16)
Sector C (4K × 16)
Sector B (4K × 16)
Sector A (4K × 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 to 0x3F 7FF5
0x3F 7FF6 to 0x3F 7FF7
0x3F 7FF8 to 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
表9-5. Addresses of Flash Sectors in F280200
ADDRESS RANGE
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector B (4K × 16)
Sector A (4K × 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 to 0x3F 7FF5
0x3F 7FF6 to 0x3F 7FF7
0x3F 7FF8 to 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
备注
• When the code-security passwords are programmed, all addresses from 0x3F 7F80 to 0x3F 7FF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
• If the code security feature is not used, addresses 0x3F 7F80 to 0x3F 7FEF may be used for code
or data. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and should not contain program
code.
表9-6 shows how to handle these memory locations.
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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表9-6. Impact of Using the Code Security Module
FLASH
ADDRESS
CODE SECURITY ENABLED
CODE SECURITY DISABLED
0x3F 7F80 to 0x3F 7FEF
0x3F 7FF0 to 0x3F 7FF5
Application code and data
Reserved for data only
Fill with 0x0000
Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read
peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written.
Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in
reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where
the user expected the write to occur first (as written). The CPU supports a block protection mode where a region
of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align
the operations). This mode is programmable and by default, it protects the selected zones.
The wait states for the various spaces in the memory map area are listed in 表9-7.
表9-7. Wait States
AREA
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
WAIT STATES (CPU)
0-wait
COMMENTS
Fixed
0-wait
0-wait (writes)
2-wait (reads)
Cycles can be extended by peripheral generated ready.
Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed. Cycles cannot be extended by the peripheral.
L0 SARAM
OTP
0-wait data and program
Programmable
Assumes no CPU conflicts
Programmed through the Flash registers.
1-wait is minimum number of wait states allowed.
Programmed through the Flash registers.
1-wait minimum
Programmable
FLASH
0-wait Paged min
1-wait Random min
Random ≥Paged
FLASH Password
Boot-ROM
16-wait fixed
0-wait
Wait states of password locations are fixed.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.3 Register Maps
The devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
These are peripherals that are mapped directly to the CPU memory bus. See 表9-8.
These are peripherals that are mapped to the 32-bit peripheral bus. See 表9-9.
These are peripherals that are mapped to the 16-bit peripheral bus. See 表9-10.
表9-8. Peripheral Frame 0 Registers
NAME(1)
Device Emulation Registers
System Power Control Registers
FLASH Registers(3)
ADDRESS RANGE
0x00 0880 to 0x00 0984
0x00 0985 to 0x00 0987
0x00 0A80 to 0x00 0ADF
0x00 0AE0 to 0x00 0AEF
0x00 0B00 to 0x00 0B0F
0x00 0C00 to 0x00 0C3F
0x00 0CE0 to 0x00 0CFF
0x00 0D00 to 0x00 0DFF
SIZE (×16)
EALLOW PROTECTED(2)
261
3
Yes
Yes
Yes
Yes
No
96
16
16
64
32
256
Code Security Module Registers
ADC registers (0 wait read only)
CPU–TIMER0/1/2 Registers
PIE Registers
No
No
PIE Vector Table
No
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
表9-9. Peripheral Frame 1 Registers
NAME
Comparator 1 registers
ADDRESS RANGE
0x00 6400 to 0x00 641F
0x00 6420 to 0x00 643F
0x00 6800 to 0x00 683F
0x00 6840 to 0x00 687F
0x00 6880 to 0x00 68BF
0x00 68C0 to 0x00 68FF
0x00 6A00 to 0x00 6A1F
0x00 6F80 to 0x00 6FFF
SIZE (×16)
EALLOW PROTECTED
(1)
32
32
64
64
64
64
32
128
(1)
(1)
(1)
(1)
(1)
Comparator 2 registers
ePWM1 + HRPWM1 registers
ePWM2 + HRPWM2 registers
ePWM3 + HRPWM3 registers
ePWM4 + HRPWM4 registers
eCAP1 registers
No
(1)
GPIO registers
(1) Some registers are EALLOW protected. For more information, see the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
表9-10. Peripheral Frame 2 Registers
NAME
System Control Registers
ADDRESS RANGE
0x00 7010 to 0x00 702F
0x00 7040 to 0x00 704F
0x00 7050 to 0x00 705F
0x00 7060 to 0x00 706F
0x00 7070 to 0x00 707F
0x00 7100 to 0x00 717F
0x00 7900 to 0x00 793F
SIZE (×16)
EALLOW PROTECTED
32
16
Yes
No
SPI-A Registers
SCI-A Registers
16
No
NMI Watchdog Interrupt Registers
External Interrupt Registers
ADC Registers
16
Yes
16
Yes
(1)
128
64
(1)
I2C-A Registers
(1) Some registers are EALLOW protected. For more information, see the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in 表9-11 .
表9-11. Device Emulation Registers
ADDRESS
RANGE
EALLOW
PROTECTED
NAME
SIZE (x16)
DESCRIPTION
Device Configuration Register
Part ID Register
0x0880
0x0881
DEVICECNF
PARTID
2
1
Yes
0x3D 7FFF
TMS320F280200PT
TMS320F280200DA
TMS320F28027PT
TMS320F28027DA
TMS320F28027FPT
TMS320F28027FDA
TMS320F28026PT
TMS320F28026DA
TMS320F28026FPT
TMS320F28026FDA
TMS320F28023PT
TMS320F28023DA
TMS320F28022PT
TMS320F28022DA
TMS320F28021PT
TMS320F28021DA
TMS320F28020PT
TMS320F28020DA
TMS320F280200PT/DA
TMS320F28027PT/DA
0x00C1
0x00C0
0x00CF
0x00CE
0x00CF
0x00CE
0x00C7
0x00C6
0x00C7
0x00C6
0x00CD
0x00CC
0x00C5
0x00C4
0x00CB
0x00CA
0x00C3
0x00C2
0x00C7
0x00CF
No
CLASSID
0x0882
1
Class ID Register
TMS320F28027FPT/DA 0x00CF
TMS320F28026PT/DA 0x00C7
TMS320F28026FPT/DA 0x00C7
No
TMS320F28023PT/DA
TMS320F28022PT/DA
TMS320F28021PT/DA
TMS320F28020PT/DA
0x00CF
0x00C7
0x00CF
0x00C7
REVID
0x0883
1
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMS
0x0001 - Silicon Rev. A - TMS
0x0002 - Silicon Rev. B - TMS
No
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.5 VREG/BOR/POR
虽然内核和 I/O 电路运行在两个不同的电压上，这些器件有一个片载电压稳压器 (VREG) 来生成 VDD 电压，此电
压由 VDDIO 电源提供。这在应用板上免除了第二个外部稳压器的成本和空间的需要。此外，在加电和运行模式期
间，内部加电复位(POR) 和欠压复位(BOR) 电力路监控VDD 和VDDIO 电源轨。
9.5.1 片载电压稳压器(VREG)
一个线性稳压器生成内核电压 (VDD)，此电压由 VDDIO 电源提供。因此，虽然在每一个 VDD 引脚上都需要电容器
来稳定生成的电压，但是运行此器件并不需要为这些引脚供电。相反地，如果功率或者冗余是应用关心的首要问
题，那么可将VREG 禁用。
9.5.1.1 使用片上VREG
要使用片上 VREG，VREGENZ 引脚应连接至低电平并且将建议的适当工作电压应用于 VDDIO 和 VDDA 引脚。在
这种情况下，内核逻辑所需的 VDD 电压将由 VREG 生成。每个 VDD 引脚需要 1.2μF（最小值）级别的电容，以
正确调节VREG。这些电容器应尽可能靠近VDD 引脚。不支持使用内部VREG 驱动外部负载。
9.5.1.2 禁用片载VREG
为了节约能源，也可禁用片载 VREG 并使用一个效率更高的外部稳压器将内核逻辑电压提供给VDD 引脚。为了启
用这个选项，VREGNZ 引脚必须被接至高电平。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden
of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a
clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point
than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is
present on both VDD and VDDIO rails at all times. After initial device power-up, the BOR function is present on
VDDIO at all times, and on VDD when the internal VREG is enabled ( VREGENZ pin is tied low). Both functions tie
the XRS pin low when one of the voltages is below their respective trip point. VDD BOR and overvoltage trip
points are outside of the recommended operating voltages. Proper device operation cannot be ensured. If
overvoltage or undervoltage conditions affecting the system is a concern for an application, an external voltage
supervisor should be added. 图 9-6 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR
functions, a bit is provided in the BORCFG register. For details, see the System Control chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
In
I/O Pin
Out
(Force Hi-Z When High)
DIR (0 = Input, 1 = Output)
Internal
Weak PU
SYSRS
SYSCLKOUT
Deglitch
Filter
Sync
RS
WDRST
C28
Core
MCLKRS
PLL
JTAG
TCK
Detect
Logic
XRS
Pin
+
Clocking
Logic
VREGHALT
WDRST(A)
PBRS(B)
POR/BOR
Generating
Module
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
A. WDRST is the reset signal from the CPU watchdog.
B. PBRS is the reset signal from the POR/BOR module.
图9-6. VREG + POR + BOR + Reset Signal Connectivity
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.6 系统控制
本部分介绍振荡器和时钟机制、看门狗功能以及低功率模式。
表9-12. PLL、时钟、看门狗和低功率模式寄存器
大小(x 16)
说明(1)
名称
BORCFG
地址
0x00 0985
0x00 7010
0x00 7011
0x00 7012
0x00 7013
0x00 7014
0x00 7016
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7025
0x00 7029
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BOR 配置寄存器
XCLK
XCLKOUT 控制
PLLSTS
PLL 状态寄存器
CLKCTL
时钟控制寄存器
PLLLOCKPRD
INTOSC1TRIM
INTOSC2TRIM
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
PCLKCR3
PLLCR
PLL 锁周期
内部振荡器1 调整寄存器
内部振荡器2 调整寄存器
低速外设时钟预分频器寄存器
外设时钟控制寄存器0
外设时钟控制寄存器1
低功耗模式控制寄存器0
外设时钟控制寄存器3
PLL 控制寄存器
SCSR
系统控制与状态寄存器
看门狗计数器寄存器
看门狗复位密钥寄存器
看门狗控制寄存器
WDCNTR
WDKEY
WDCR
(1) 此表中的所有寄存器都受EALLOW 保护。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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图9-7 显示了讨论的各种时钟域。图9-8 显示了能够为器件运行提供时钟的各种时钟源（内部和外部）。
SYSCLKOUT
PCLKCR0/1/3
(System Ctrl Regs)
LOSPCP
(System Ctrl Regs)
C28x Core
CLKIN
Clock Enables
LSPCLK
Peripheral
Registers
SPI-A, SCI-A
I/O
I/O
I/O
I/O
PF2
Clock Enables
eCAP1
Peripheral
Registers
PF1
PF1
PF2
GPIO
Mux
Clock Enables
ePWM1/.../4
Clock Enables
I2C-A
Peripheral
Registers
Peripheral
Registers
Clock Enables
ADC
Registers
PF2
PF0
16 Ch
12-Bit ADC
Analog
GPIO
Mux
Clock Enables
COMP1/2
COMP
Registers
6
PF1
A. CLKIN 为CPU 提供时钟。它作为SYSCLKOUT 从CPU 传出（也就是说，CLKIN 与SYSCLKOUT 频率相同）。
图9-7. 时钟和复位域
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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A. 从TI 基于OTP 的校准功能载入的寄存器。
B. 请参阅节9.6.4 了解有关时钟缺失检测的详情。
图9-8. 时钟树
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.6.1 内部零引脚振荡器
F2802x 器件包含两个独立的内部零引脚振荡器。缺省情况下，两个振荡器在加电时全都打开，此时，内部振荡器
1 是默认时钟源。为了节能，用户可将不使用的振荡器断电。这些振荡器的中心频率由它们各自的振荡器调整寄存
器决定，此寄存器在校准例程中被写入作为引导ROM 执行的一部分。有关这些振荡器的更多信息，请见节8，电
气规范。
9.6.2 Crystal Oscillator Option
The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level signals
applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be connected to
the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it should be used with
X2 and a crystal.
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in 表
9-13. Furthermore, ESR range = 30 to 150 Ω.
表9-13. Typical Specifications for External Quartz Crystal(1)
FREQUENCY (MHz)
CL1 (pF)
CL2 (pF)
Rd (Ω)
2200
470
0
5
18
18
10
15
20
15
15
15
15
0
12
12
(1) Cshunt should be less than or equal to 5 pF.
XCLKIN/GPIO19/38
X1
X2
Rd
Turn off
XCLKIN path
in CLKCTL
register
Crystal
CL1
CL2
A. X1/X2 pins are available in 48-pin package only.
图9-9. Using the On-chip Crystal Oscillator
备注
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and
crystal. The value is usually approximately twice the value of the crystal's load capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the operation of
their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to
tune the tank circuit. The vendor can also advise the customer regarding the proper tank
component values that will produce proper start-up and stability over the entire operating range.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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XCLKIN/GPIO19/38
X1
X2
NC
External Clock Signal
(Toggling 0−V
)
DDIO
图9-10. Using a 3.3-V External Oscillator
9.6.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) is at least 50 MHz.
表9-14. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(2) (3)
PLLSTS[DIVSEL] = 0 or 1(1)
OSCCLK/4 (Default)(2)
(OSCCLK * 1)/4
PLLSTS[DIVSEL] = 2
OSCCLK/2
PLLSTS[DIVSEL] = 3
OSCCLK
0000 (PLL bypass)
0001
(OSCCLK * 1)/2
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
(OSCCLK * 11)/2
(OSCCLK * 12)/2
(OSCCLK * 1)/1
(OSCCLK * 2)/1
(OSCCLK * 3)/1
(OSCCLK * 4)/1
(OSCCLK * 5)/1
(OSCCLK * 6)/1
(OSCCLK * 7)/1
(OSCCLK * 8)/1
(OSCCLK * 9)/1
(OSCCLK * 10)/1
(OSCCLK * 11)/1
(OSCCLK * 12)/1
0010
(OSCCLK * 2)/4
0011
(OSCCLK * 3)/4
0100
(OSCCLK * 4)/4
0101
(OSCCLK * 5)/4
0110
(OSCCLK * 6)/4
0111
(OSCCLK * 7)/4
1000
(OSCCLK * 8)/4
1001
(OSCCLK * 9)/4
1010
(OSCCLK * 10)/4
(OSCCLK * 11)/4
(OSCCLK * 12)/4
1011
1100
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(3) This register is EALLOW protected. See the System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference
Manual for more information.
表9-15. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/4
/4
/2
/1
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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The PLL-based clock module provides four modes of operation:
• INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock
for the Watchdog block, core and CPU-Timer 2
• INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock
for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen
for the Watchdog block, core and CPU-Timer 2.
• Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/
resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2
pins. Some devices may not have the X1/X2 pins. See 节7.2.1 for details.
• External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be
bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. The
XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or
GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input
(forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable
at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock
source must be disabled (using the CLKCTL register) before switching clocks.
表9-16. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low-
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power-up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
0, 1
2
3
OSCCLK * n/4
OSCCLK * n/2
OSCCLK * n/1
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
9.6.4 输入时钟的损耗（NMI 看门狗功能）
2802x 器件可由两个内部零引脚振荡器 (INTOSC1/INTOSC2) 的其中任一个、片上晶体振荡器、或者一个外部时
钟输入提供时钟信号。无论时钟源是什么，在 PLL 启用和 PLL 旁路模式中，如果到 PLL 的输入时钟消失，PLL
将在其输出上发出一个跛行模式时钟。这个跛行模式时钟持续为CPU 和外设提供一个典型值为1-5MHz 的时钟。
当跛行模式被激活时，一个被锁存为 NMI 中断的 CLOCLFAIL 信号被生成。根据 NMIRESETSEL 位的配置方
式，器件复位可能会被立即触发或者 NMI 看门狗计数器溢出时发出复位。除此之外，会设置丢失时钟状态
(MCLKSTS) 位。应用可使用 NMI 中断来检测输入时钟故障并启动所需的校正操作，例如切换到另一个时钟源
（如果有的话）或者为系统启动一个关断过程。
如果软件对于时钟故障情况没有响应，NMI 看门狗将在一个预编程的时间间隔后触发复位。图9-11 显示了涉及的
中断机制。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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NMIFLG[NMINT]
NMIFLGCLR[NMINT]
Clear
Latch
Set
Clear
XRS
Generate
NMIFLG[CLOCKFAIL]
Clear
Latch
1
0
0
Interrupt
Pulse
When
NMIFLGCLR[CLOCKFAIL]
CLOCKFAIL
NMINT
SYNC?
Input = 1
Set
Clear
SYSCLKOUT
NMICFG[CLOCKFAIL]
NMIFLGFRC[CLOCKFAIL]
XRS
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
See System
Control Section
NMI Watchdog
NMIRS
图9-11. NMI 看门狗
9.6.5 CPU 看门狗模块
2802x 器件上的 CPU 看门狗模块与 281x/280x/283x 器件上所使用的类似。只要 8 位看门狗递增计数器达到了它
的最大值，这个模块就生成一个输出脉冲，512 振荡器时钟宽度 (OSCCLK)。为防止这一情况，用户必须禁用计
数器，或者软件必须定期向看门狗键值寄存器写入一个0x55 + 0xAA 序列，用于复位看门狗计数器。图9-12 显示
了看门狗模块内的各种功能块。
通常情况下，当输入时钟出现时，CPU 看门狗计数器会递减，以便启动 CPU 看门狗复位或 WDINT 中断。但
是，当外部输入时钟故障时，CPU 看门狗计数器会停止递减（即看门狗计数器不随跛行模式时钟而变化）。
备注
CPU 看门狗与NMI 看门狗不同。它是出现在所有28x 器件中的老版看门狗。
备注
在正确 CPU 运行频率绝对关键的应用中应该执行一个机制，通过这个机制，只要输入时钟出现故障，
MCU 就被保持在复位状态。例如，只要电容器充满电，一个 R-C 电路可被用于触发 MCU 的 XRS 引
脚。一个 I/O 引脚可被用于定期为电容器放电以防止其被完全充满。这样一个电路也有助于检测闪存存
储器的故障。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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A. WDRST 信号在512 个OSCCLK 周期内被驱动为低电平。
图9-12. CPU 看门狗模块
WDINT 信号支持使用看门狗从空闲/待机模式唤醒。
在待机模式中，器件上的所有外设关闭。唯一保持正常运行的外设是 CPU 看门狗。这个模块将关闭 OSCCLK。
WDINT 信号被馈送到 LPM 块以便它可以将器件从待机唤醒（如已启用）。请参阅节 9.7 低功耗模式块，了解更
多详细信息。
在空闲模式下，WDINT 信号可通过PIE 对CPU 生成一个中断，以便使CPU 退出空闲模式。
在停机模式下，CPU 看门狗可用来通过器件复位唤醒器件。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.7 Low-power Modes Block
表9-17 summarizes the various modes.
表9-17. Low-power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, CPU watchdog interrupt, any
enabled interrupt
IDLE
00
On
On
On
Off
On
XRS, CPU watchdog interrupt, GPIO
Port A signal, debugger(2)
STANDBY
HALT(3)
01
1X
Off
Off
(CPU watchdog still running)
Off
(on-chip crystal oscillator and PLL
turned off, zero-pin oscillator and
CPU watchdog state dependent
on user code.)
XRS, GPIO Port A signal, debugger(2)
CPU watchdog
,
Off
(1) The EXIT column lists which signals or under what conditions the low-power mode is exited. A low signal, on any of the signals, exits
the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-
power mode will not be exited and the device will go back into the indicated low-power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block
performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT Mode:
CPU watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT
mode. The user selects the signal in the GPIOLPMSEL register.
备注
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the System Control
chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual for more details.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.8 Interrupts
图9-13 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, ePWM, I2C, HRPWM, eCAP, ADC)
WDINT
Watchdog
WAKEINT
Sync
LPMINT
Low-Power Modes
SYSCLKOUT
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
XINT1
XINT1
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
INT1
to
INT12
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
Core
GPIOXINT2SEL(4:0)
GPIO0.int
XINT3
TINT0
XINT3
GPIO
MUX
Interrupt Control
XINT3CR(15:0)
XINT3CTR(15:0)
GPIO31.int
GPIOXINT3SEL(4:0)
CPU TIMER 0
CPU TIMER 1
CPU TIMER 2
TINT1
TINT2
INT13
INT14
CPUTMR2CLK
CLOCKFAIL
NMIRS
System Control
(See the System
Control section.)
NMI interrupt with watchdog function
(See the NMI Watchdog section.)
NMI
图9-13. External and PIE Interrupt Sources
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. 表9-18 shows the interrupts used by 2802x devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. The TRAP #0 instruction attempts to transfer program control to the address pointed to by
the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, the TRAP #0
instruction should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the interrupt
service routine corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction
fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.
IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
图9-14. Multiplexing of Interrupts Using the PIE Block
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
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表9-18. PIE MUXed Peripheral Interrupt Vector Table
INTx.8(1)
WAKEINT
(LPM/WD)
0xD4E
INTx.7
INTx.6
ADCINT9
(ADC)
INTx.5
INTx.4
INTx.3
INTx.2
ADCINT2
(ADC)
INTx.1
ADCINT1
(ADC)
INT1.y
INT2.y
INT3.y
INT4.y
INT5.y
INT6.y
INT7.y
INT8.y
INT9.y
INT10.y
INT11.y
INT12.y
TINT0
XINT2
XINT1
Reserved
(TIMER 0)
0xD4C
Ext. int. 2
0xD48
Ext. int. 1
0xD46
–
0xD4A
0xD44
0xD42
0xD40
Reserved
Reserved
Reserved
Reserved
EPWM4_TZINT
(ePWM4)
0xD56
EPWM3_TZINT
(ePWM3)
0xD54
EPWM2_TZINT
(ePWM2)
0xD52
EPWM1_TZINT
(ePWM1)
0xD50
–
–
–
–
0xD5E
0xD5C
0xD5A
0xD58
Reserved
Reserved
Reserved
Reserved
EPWM4_INT
(ePWM4)
0xD66
EPWM3_INT
(ePWM3)
0xD64
EPWM2_INT
(ePWM2)
0xD62
EPWM1_INT
(ePWM1)
0xD60
–
–
–
–
0xD6E
0xD6C
0xD6A
0xD68
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ECAP1_INT
(eCAP1)
0xD70
–
–
–
–
–
–
–
0xD7E
0xD7C
0xD7A
0xD78
0xD76
0xD74
0xD72
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xD8E
0xD8C
0xD8A
0xD88
0xD86
0xD84
0xD82
0xD80
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
–
–
–
–
–
–
0xD9E
0xD9C
0xD9A
0xD98
0xD96
0xD94
0xD92
0xD90
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xDAE
0xDAC
0xDAA
0xDA8
0xDA6
0xDA4
0xDA2
0xDA0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
–
–
–
–
–
–
0xDBE
0xDBC
0xDBA
0xDB8
0xDB6
0xDB4
0xDB2
0xDB0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
–
–
–
–
–
–
0xDCE
0xDCC
0xDCA
0xDC8
0xDC6
0xDC4
0xDC2
0xDC0
ADCINT8
(ADC)
ADCINT7
(ADC)
ADCINT6
(ADC)
ADCINT5
(ADC)
ADCINT4
(ADC)
ADCINT3
(ADC)
ADCINT2
(ADC)
ADCINT1
(ADC)
0xDDE
0xDDC
0xDDA
0xDD8
0xDD6
0xDD4
0xDD2
0xDD0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
–
–
–
–
–
–
0xDEE
0xDEC
0xDEA
0xDE8
0xDE6
0xDE4
0xDE2
0xDE0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XINT3
Ext. Int. 3
0xDF0
–
–
–
–
–
–
–
0xDFE
0xDFC
0xDFA
0xDF8
0xDF6
0xDF4
0xDF2
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
a. No peripheral within the group is asserting interrupts.
b. No peripheral interrupts are assigned to the group (for example, PIE groups 5, 7, or 11) .
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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表9-19. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (x16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA –
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.8.1 External Interrupts
表9-20. External Interrupt Registers
NAME
XINT1CR
XINT2CR
XINT3CR
XINT1CTR
XINT2CTR
XINT3CTR
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7078
0x00 7079
0x00 707A
SIZE (x16)
DESCRIPTION
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT1 counter register
1
1
1
1
1
1
XINT2 counter register
XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control chapter in the TMS320F2802x,TMS320F2802xx
Technical Reference Manual.
9.8.1.1 外部中断电子数据/定时
9.8.1.1.1 External Interrupt Timing Requirements
MIN(1)
1tc(SCO)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
(2)
tw(INT)
Pulse duration, INT input low/high
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
9.8.1.1.2 External Interrupt Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN(1)
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
t
w(INT)
XINT1, XINT2, XINT3
t
d(INT)
Address bus
(internal)
Interrupt Vector
图9-15. External Interrupt Timing
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9 外设
9.9.1 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The
ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing
control of start of conversions. 图 9-16 shows the interaction of the analog module with the rest of the F2802x
system.
For more information on the ADC, see the Analog-to-Digital Converter and Comparator chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
38-Pin
VDDA
48-Pin
VDDA
VREFLO VREFLO
Tied To Tied To
Interface Reference
Diff
VSSA
VSSA
VREFHI VREFHI
Tied To Tied To
VREFHI
A0
B0
A0
A2
A4
A6
A0
A1
A2
A3
A4
A1
B1
COMP1OUT
A2
AIO2
AIO10
10-Bit
DAC
Comp1
Comp2
B2
A6
A7
A3
B3
ADC
COMP2OUT
(See Note A)
A4
B4
B1
B2
B3
B4
AIO4
AIO12
10-Bit
DAC
B2
B4
B6
B5
B6
B7
Temperature Sensor
A5
A6
Signal Pinout
AIO6
AIO14
B6
A7
B7
A. Comparator 2 is available only on the 48-pin PT package.
图9-16. Analog Pin Configurations
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.1 模数转换器(ADC)
9.9.1.1.1 特性
ADC 的内核包含有一个单一 12 位转换器，此转换器由两个采样保持电路供源。可以对这两个采样保持电路进行
同步采样或顺序采样。按顺序，这些电路由总共高达 13 个模拟输入通道供源。此转换器可配置为采用内部带隙基
准运行，以便形成基于实际电压的转换，或者采用一对外部电压基准 (VREFHI/VREFLO) 运行，形成基于比率的转
换。
与之前的 ADC 类型不同，此 ADC 并非基于序列发生器。对于用户来讲，他们可以很容易地从一个单触发来创建
一系列的转换。然而，操作的基本原则是以单个转换的配置为中心，被称为SOC，或者转换启动。
ADC 模块的功能包括：
• 具有内置双采样保持(S/H) 的12 位ADC 内核
• 同步采样模式或顺序采样模式
• 全范围模拟输入：0V 至3.3V 固定电压，或VREFHI/VREFLO 比率。输入模拟电压的数值源自：
– 内部基准（VREFLO=VSSA。当使用内部或者外部基准模式时，VREFHI 不得超过VDDA。）
Digital Value = 0,
when input £ 0 V
Input Analog Voltage -
VREFLO
Digital Value = 4096 ´
when 0 V < input < 3.3 V
3.3
Digital Value = 4095,
when input ³ 3.3 V
– 外部基准（VREFHI/VREFLO 被连接至外部基准。当使用内部或者外部基准模式时，VREFHI 不得超过
VDDA。）
Digital Value = 0,
when input £ 0 V
Input Analog Voltage -
VREFLO
Digital Value = 4096 ´
when 0 V < input <
VREFHI
-
VREFHI VREFLO
Digital Value = 4095,
when input ³
VREFHI
• 多达16 个通道，多路复用输入
• 16 个SOC，可针对触发、采样窗口和通道进行配置
• 用于存储转换值的16 个结果寄存器（可单独寻址）
• 多个触发源
– S/W - 软件立即启动
– ePWM 1-4
– GPIO XINT2
– CPU 计时器0/1/2
– ADCINT1/2
• 9 个灵活的PIE 中断，可在任一个转换后配置中断请求
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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表9-21. ADC 配置和控制寄存器
受EALLOW
保护
大小
(x16)
寄存器名称
地址
说明
ADCCTL1
0x7100
0x7101
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x7110
0x7112
0x7114
0x7115
0x7118
0x711A
0x711C
0x711E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
是
是
否
否
否
否
是
是
是
是
是
是
是
是
是
否
否
否
否
是
控制1 寄存器
ADCCTL2
控制2 寄存器
ADCINTFLG
中断标志寄存器
ADCINTFLGCLR
ADCINTOVF
中断标志清除寄存器
中断溢出寄存器
ADCINTOVFCLR
INTSEL1N2
中断溢出清除寄存器
中断1 和2 选择寄存器
中断3 和4 选择寄存器
中断5 和6 选择寄存器
中断7 和8 选择寄存器
INTSEL3N4
INTSEL5N6
INTSEL7N8
INTSEL9N10
中断9 选择寄存器（被保留的中断10 选择）
SOC 优先级控制寄存器
SOCPRICTL
ADCSAMPLEMODE
ADCINTSOCSEL1
ADCINTSOCSEL2
ADCSOCFLG1
ADCSOCFRC1
ADCSOCOVF1
ADCSOCOVFCLR1
采样模式寄存器
中断SOC 选择1 寄存器（用于8 个通道）
中断SOC 选择2 寄存器（用于8 个通道）
SOC 标志1 寄存器（用于16 个通道）
SOC 强制1 寄存器（用于16 个通道）
SOC 溢出1 寄存器（用于16 个通道）
SOC 溢出清除1 寄存器（用于16 个通道）
SOC0 控制寄存器至SOC15 控制寄存器
0x7120-0x7
12F
ADCSOC0CTL 至
ADCSOC15CTL
ADCREFTRIM
ADCOFFTRIM
COMPHYSTCTL
ADCREV
0x7140
0x7141
0x714C
0x714F
1
1
1
1
是
是
是
否
基准调整寄存器
偏移调整寄存器
比较器滞后控制寄存器
修订版本寄存器
表9-22. ADC 结果寄存器（被映射至PF0）
受EALLOW
大小
(x16)
寄存器名称
地址
说明
保护
1
ADCRESULT0 至ADCRESULT15
0xB00 至0xB0F
否
ADC 结果0 寄存器至ADC 结果15 寄存
器
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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0-Wait
Result
Registers
PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
TINT 0
TINT 1
TINT 2
ADC
Core
12-Bit
CPUTIMER 0
CPUTIMER 1
CPUTIMER 2
AIO
MUX
ADC
Channels
ADCTRIG 1
ADCTRIG 2
ADCTRIG 3
XINT 2SOC
XINT 2
ePWM 1
ePWM 2
ePWM 3
ePWM 4
ADCTRIG 4
SOCA 1
SOCB 1
SOCA 2
SOCB 2
SOCA 3
SOCB 3
SOCA 4
SOCB 4
ADCTRIG 5
ADCTRIG 6
ADCTRIG 7
ADCTRIG 8
ADCTRIG 9
ADCTRIG 10
ADCTRIG 11
ADCTRIG 12
图9-17. ADC 连接
不使用ADC 时的ADC 连接
TI 建议即使不使用 ADC，也应保持模拟电源引脚的连接。下面总结了如果 ADC 未在应用中使用，应该如何连接
ADC 引脚：
• VDDA - 连接到VDDIO
• VSSA - 连接到VSS
• VREFLO - 连接到VSS
• ADCINAn，ADCINBn，VREFHI - 连接到VSSA
当在一个应用中使用ADC 模块时，未使用的ADC 输入引脚应被连接至模拟接地(VSSA)。
备注
与 AIO 功能复用的未使用 ADCIN 引脚不应直接连接到模拟地。它们应该通过一个 1kΩ 电阻器接地。
这是为了防止一个错误代码将这些引脚配置为AIO 输出并将接地的引脚驱动至一个逻辑高电平状态。
当ADC 未被使用时，为了达到节能的目的，请确保到ADC 模块的时钟未被打开。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.1.2 ADC 转换开始电子数据/定时
9.9.1.1.2.1 外部ADC 转换启动开关特性
在推荐的运行条件下（除非另有说明）
参数
最小值
最大值
单位
周期
tw(ADCSOCL)
32tc(HCO)
脉冲持续时间，ADCSOCxO 低电平的时间
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
图9-18. ADCSOCAO 或者ADCSOCBO 时序
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.1.3 片载模数转换器(ADC) 电子数据/定时
9.9.1.1.3.1 ADC Electrical Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
0.001
7
Bits
ADC clock
60-MHz device
28027/26/23/22
28021/20/200
60
64
64
MHz
Sample Window
ADC
Clocks
14
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤30 MHz(1)
–4
–1
4
1
LSB
LSB
DNL (Differential nonlinearity) at ADC Clock ≤30 MHz,
no missing codes
Offset error (2)
Executing Device_Cal
function
0
0
20
4
–20
–4
LSB
Executing periodic self-
recalibration(3)
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ADC temperature coefficient with internal reference
ADC temperature coefficient with external reference
VREFLO
60
40
4
LSB
LSB
–60
–40
–4
LSB
4
LSB
–4
ppm/°C
ppm/°C
µA
–50
–20
–100
100
VREFHI
µA
ANALOG INPUT
Analog input voltage with internal reference
Analog input voltage with external reference
VREFLO input voltage(4)
0
VREFLO
VSSA
3.3
VREFHI
VSSA
V
V
V
VREFHI input voltage(5)
with VREFLO = VSSA
1.98
VDDA
V
Input capacitance
5
pF
μA
Input leakage current
±5
(1) INL will degrade when the ADC input voltage goes above VDDA
.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be
performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset
Calibration" section of the Analog-to-Digital Converter and Comparator chapter in the TMS320F2802x,TMS320F2802xx Technical
Reference Manual.
(4) VREFLO is always connected to VSSA
.
(5) VREFHI must not exceed VDDA when using either internal or external reference modes. Because VREFHI is tied to ADCINA0 , the input
signal on ADCINA0 must not exceed VDDA
.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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9.9.1.1.3.2 ADC 电源模式
IDDA
ADC 工作模式
条件
单位
ADC 时钟启用
带隙开启(ADCBGPWD = 1)
基准开启(ADCREFPWD = 1)
ADC 加电(ADCPWDN = 1)
13
mA
模式A - 工作模式
ADC 时钟启用
带隙开启(ADCBGPWD = 1)
基准开启(ADCREFPWD = 1)
ADC 加电(ADCPWDN = 0)
4
mA
mA
mA
模式B - 快速唤醒模式
模式C - 仅比较器模式
模式D - 关闭模式
ADC 时钟启用
带隙开启(ADCBGPWD = 1)
基准开启(ADCREFPWD = 0)
ADC 加电(ADCPWDN = 0)
1.5
ADC 时钟启用
带隙开启(ADCBGPWD = 0)
基准开启(ADCREFPWD = 0)
ADC 加电(ADCPWDN = 0)
0.075
9.9.1.1.3.3 内部温度传感器
9.9.1.1.3.3.1 Temperature Sensor Coefficient
PARAMETER(1)
MIN
TYP
0.18(3) (2)
1750
MAX
UNIT
°C/LSB
LSB
TSLOPE
Degrees C of temperature movement per measured ADC LSB change
of the temperature sensor
TOFFSET
ADC output at 0°C of the temperature sensor
(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(2) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
(3) ADC temperature coeffieicient is accounted for in this specification
9.9.1.1.3.4 ADC 加电控制位时序
9.9.1.1.3.4.1 ADC 加电延迟
参数(1)
最小值
最大值
单位
td(PWD)
1
ms
加电后，ADC 的延迟时间将稳定
(1) 时序保持与ADC 模块的兼容性。在首次转换前td(PWD) ms，2802x ADC 支持同时驱动所有3 个位。
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
td(PWD)
Request for ADC
Conversion
图9-19. ADC 转换时序
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Ron
3.4 kW
Switch
Rs
ADCIN
Cp
Ch
Source
Signal
ac
5 pF
1.6 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 3.4 kW
Sampling Capacitor (Ch): 1.6 pF
Parasitic Capacitance (Cp): 5 pF
Source Resistance (Rs): 50 W
图9-20. ADC 输入阻抗模型
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.1.3.5 ADC 顺序模式时序和同步模式时序
Analog Input
SOC0 Sample
Window
SOC1 Sample
Window
SOC2 Sample
Window
0
2
9
15
22 24
37
ADCCLK
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0
SOC1
SOC2
Result 0 Latched
2 ADCCLKs
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
ADCINTFLG.ADCINTx
Minimum
7 ADCCLKs
Conversion 0
13 ADC Clocks
1 ADCCLK
6
Minimum
ADCCLKs 7 ADCCLKs
Conversion 1
13 ADC Clocks
图9-21. 顺序模式/后期中断脉冲的时序示例
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Analog Input
SOC0 Sample
Window
SOC1 Sample
Window
SOC2 Sample
Window
0
2
9
15
22 24
37
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0
SOC1
SOC2
Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
7 ADCCLKs
Conversion 0
13 ADC Clocks
2 ADCCLKs
6
Minimum
ADCCLKs 7 ADCCLKs
Conversion 1
13 ADC Clocks
图9-22. 顺序模式/提前中断脉冲的时序示例
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Analog Input A
Analog Input B
SOC0 Sample
A Window
SOC2 Sample
A Window
SOC0 Sample
B Window
SOC2 Sample
B Window
0
2
9
22 24
37
50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0 (A/B)
SOC2 (A/B)
2 ADCCLKs
Result 0 (A) Latched
ADCRESULT 1
Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
1 ADCCLK
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
2 ADCCLKs
19
ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
图9-23. 同步模式/后期中断脉冲的时序示例
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
Analog Input B
SOC0 Sample
B Window
SOC2 Sample
B Window
0
2
9
22 24
37
50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
2 ADCCLKs
Result 0 (B) Latched
ADCRESULT 1
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Conversion 0 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
Minimum
2 ADCCLKs
7 ADCCLKs
19
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
ADCCLKs
图9-24. 同步模式/提前中断脉冲的时序示例
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.2 ADC 多路复用器
To COMPy A or B input
To ADC Channel X
Logic implemented in GPIO MUX block
AIOx Pin
SYSCLK
AIOxIN
1
AIOxINE
AIODAT Reg
(Read)
SYNC
0
AIODAT Reg
(Latch)
AIOMUX 1 Reg
AIOSET,
AIOCLEAR,
AIOTOGGLE
Regs
AIODIR Reg
(Latch)
1
(0 = Input, 1 = Output)
0
0
图9-25. AIOx 引脚多路复用
ADC 通道和比较器功能始终可用。数字 I/O 功能只有当 AIOMUX1 寄存器中的相应位为 0 时可用。在此模式下，
读取AIODAT 寄存器会反映实际引脚状态。
数字 I/O 功能在 AIOMUX1 寄存器中的相应位为 1 时停用。在此模式下，读取 AIODAT 寄存器会反映 AIODAT 寄
存器的输出锁存器，并且输入数字I/O 缓冲器将会停用以防止模拟信号生成噪声。
复位时，数字功能会停用。如果此引脚用作模拟输入，则用户应该确保该引脚持续停用AIO 功能。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.3 比较器块
图9-26 显示了比较器，模块与系统其余部分的相互作用。
COMP x A
+
COMP x B
COMP
TZ1/2/3
-
GPIO
MUX
COMP x
+
DAC x
Wrapper
ePWM
AIO
MUX
COMPxOUT
DAC
Core
10-Bit
图9-26. 比较器块图
表9-23. 比较器控制寄存器
COMP2
COMP1
地址
大小(x
16)
受EALLOW 保
护
寄存器名称
COMPCTL
说明
地址(1)
0x6420
0x6422
0x6424
0x6426
0x6428
0x642A
0x642C
0x642E
0x6430
0x6400
0x6402
0x6404
0x6406
0x6408
0x640A
0x640C
0x640E
0x6410
1
1
1
1
1
1
1
1
1
是
否
是
否
否
否
否
否
否
比较器控制寄存器
比较器状态寄存器
DAC 控制寄存器
DAC 值寄存器
COMPSTS
DACCTL
DACVAL
RAMPMAXREF_ACTIVE
RAMPMAXREF_SHDW
RAMPDECVAL_ACTIVE
RAMPDECVAL_SHDW
RAMPSTS
斜坡发生器最大基准（有效）寄存器
斜坡发生器最大基准（阴影）寄存器
斜坡发生器减量值（有效）寄存器
斜坡发生器减量值（阴影）寄存器
斜坡发生器状态寄存器
(1) 比较器2 只在48 引脚PT 封装内可用。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.1.3.1 片载比较器/ DAC 电子数据/定时
9.9.1.3.1.1 Electrical Characteristics of the Comparator/DAC
PARAMETER
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
Comparator response time to PWM Trip Zone (Async)
Input Offset
V
V
V
SSA –VDDA
30
±5
35
ns
mV
mV
Input Hysteresis(1)
DAC
DAC Output Range
DAC resolution
DAC settling time
DAC Gain
V
SSA –VDDA
10
See 图9-27
–1.5%
10
bits
DAC Offset
Monotonic
mV
Yes
INL
±3
LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩfeedback
resistance between the output of the comparator and the noninverting input of the comparator. There is an option to disable the
hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual for more information on this option if needed in your system.
1100
1000
900
800
700
600
500
400
300
200
100
0
0
50
100
150
200
250
300
350
400
450
500
DAC Step Size (Codes)
DAC Accuracy
15 Codes
7 Codes
3 Codes
1 Code
图9-27. DAC Settling Time
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.2 详细说明
积分非线性
积分非线性是指各个代码与从零到满量程绘制的直线的偏差。在首次代码转换前，作为零点的点出现一半 LSB。
满刻度点被定义为超过最后一次代码转换的级别一半 LSB。这个偏离为每一个特定代码的中心到这两个点之间的
精确直线的距离。
微分非线性
一个理想 ADC 显示分开距离恰好为 1 个 LSB 的代码转换。DNL 是从这个理想值的偏离。一个少于 ±1 LSB 的微
分非线性误差可确保无丢码。
零偏移
当模拟输入为零伏时，应当发生主进位转换。零误差被定义为实际转换到那个点的偏离。
增益误差
第一个代码转换应该出现在高于负满刻度的一个模拟值一半 LSB 上。最后一次转换应该出现在低于标称满刻度的
一个模拟值一倍半LSB 上。增益误差是首次和末次代码转换间的实际差异以及它们之间的理想差异。
信噪比+ 失真(SINAD)
SINAD 是测得的输入信号的均方根值与所有其它低于那奎斯特频率的频谱分量（包括谐波但不包括 dc）的均方根
总和的比。SINAD 的值用分贝表示。
有效位数(ENOB)
(SINAD -1.76)
N =
6.02
对于一个正弦波，SINAD 可用位的数量表示。使用下面的公式，
有可能获得一个用 N（位的
有效数）表达的性能测量值。因此，对于在给定输入频率上用于正弦波输入的器件的有效位数量可从这个测得的
SINAD 直接计算。
总谐波失真(THD)
THD 是头九个谐波分量的均方根总和与测得的输入信号的均方根值的比并表达为一个百分比或者分贝值。
无伪波动态范围(SFDR)
SFDR 是输入信号均方根振幅与峰值寄生信号间以分贝为单位的差异。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.3 Serial Peripheral Interface (SPI) Module
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the MCU and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
• Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
备注
All four pins can be used as GPIO if the SPI module is not used.
• Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to127
when SPIBRR = 0,1, 2
(SPIBRR + 1)
LSPCLK
4
Baud rate =
• Data word length: 1 to 16 data bits
• Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
• Simultaneous receive and transmit operation (transmit function can be disabled in software)
• Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
• Nine SPI module control registers: In control register frame beginning at address 7040h.
备注
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is
read as zeros. Writing to the upper byte has no effect.
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Enhanced feature:
• 4-level transmit/receive FIFO
• Delayed transmit control
• Bidirectional 3 wire SPI mode support
The SPI port operation is configured and controlled by the registers listed in 表9-24 .
表9-24. SPI-A Registers
NAME
SPICCR
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (x16) EALLOW PROTECTED
DESCRIPTION(1)
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
SPICTL
SPISTS
SPIBRR
SPI-A Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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图9-28 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO Registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
-----
SPIINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _3
16
SPIRXBUF
Buffer Register
SPIFFOVF
FLAG
SPIFFRX.15
To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3
TX Interrupt
Logic
TX FIFO Interrupt
-----
TX FIFO _1
SPITX
TX FIFO _0
16
SPI INT
ENA
16
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
TRIWIRE
SPIPRI.0
16
M
S
M
SPIDAT
Data Register
TW
S
SW1
SW2
SPISIMO
M
S
TW
SPIDAT.15 - 0
M
TW
S
SPISOMI
SPISTE
Talk
SPICTL.1
State Control
Master/Slave
SPICTL.2
SPI Char
LSPCLK
SPICCR.3 - 0
S
SW3
3
2
1
0
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
SPIBRR.6 - 0
SPICCR.6
SPICTL.3
SPICLK
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
图9-28. SPI Module Block Diagram (Slave Mode)
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.3.1 SPI 主模式电气数据/时序
节9.9.3.1.1 列出了主模式时序（时钟相位= 0），节9.9.3.1.2 列出了主模式时序（时钟相位= 1）。图9-29 和图
9-30 显示了时序波形。
9.9.3.1.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
0.5tc(SPC)M + 0.5tc(LSPCLK)
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M
+
2
tw(SPC1)M
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
–10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
–
0.5tc(SPC)M
–
3
4
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
ns
ns
ns
ns
ns
ns
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
0.5tc(LSPCLK) –10
Delay time, SPICLK to
SPISIMO valid
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M –
0.5tc(LSPCLK) –10
5
0.5tc(SPC)M –10
Setup time, SPISOMI before
SPICLK
8
26
0
26
Hold time, SPISOMI valid after
SPICLK
9
0
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M
–
23
3tc(SYSCLK) –10
3tc(SYSCLK) –10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M
0.5tc(LSPCLK) –10
–
24
td(STE)M
ns
0.5tc(SPC)M –10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
图9-29. SPI Master Mode External Timing (Clock Phase = 0)
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.3.1.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
0.5tc(LSPCLK) –10
0.5tc(SPC)M
0.5tc(LSPCLK) –10
0.5tc(SPC)M
0.5tc(LSPCLK) –10
0.5tc(SPC)M
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
–
0.5tc(SPC)M
–
2
3
6
tw(SPC1)M
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
+
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
tw(SPC2)M
ns
ns
0.5tc(SPC)M –10
0.5tc(SPC)M –10
0.5tc(LSPCLK) + 10
+
Delay time, SPISIMO valid to
SPICLK
td(SIMO)M
Valid time, SPISIMO valid after
SPICLK
–
7
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
ns
ns
ns
ns
0.5tc(SPC)M –10
0.5tc(LSPCLK) –10
Setup time, SPISOMI before
SPICLK
10
11
23
26
0
26
Hold time, SPISOMI valid after
SPICLK
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) –10
3tc(SYSCLK) –10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
0.5tc(LSPCLK) –10
–
24
td(STE)M
ns
0.5tc(SPC) –10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
图9-30. SPI Master Mode External Timing (Clock Phase = 1)
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.3.2 SPI 从模式电气数据/时序
节9.9.3.2.1 列出了从模式时序（时钟相位= 0），节9.9.3.2.2 列出了从模式时序（时钟相位= 1）。图9-31 和图
9-32 显示了时序波形。
9.9.3.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(4) (3)
(5)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) –1
2tc(SYSCLK) –1
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
21
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
图9-31. SPI Slave Mode External Timing (Clock Phase = 0)
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.3.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(3) (4)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) –1
2tc(SYSCLK) –1
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
21
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
图9-32. SPI Slave Mode External Timing (Clock Phase = 1)
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.4 Serial Communications Interface (SCI) Module
The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
备注
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
16
Baud rate =
• Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– One or 2 stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (nonreturn-to-zero) format
备注
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is
read as zeros. Writing to the upper byte has no effect.
Enhanced features:
• Auto baud-detect hardware logic
• 4-level transmit/receive FIFO
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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The SCI port operation is configured and controlled by the registers listed in 表9-25.
表9-25. SCI-A Registers
EALLOW
PROTECTED
NAME(1)
SCICCRA
ADDRESS
SIZE (x16)
DESCRIPTION
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
No
SCI-A Communications Control Register
SCI-A Control Register 1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
For more information on the SCI, see the Serial Communications Interface (SCI) chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
图9-33 shows the SCI module block diagram.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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TXENA
SCICTL1.1
TXSHF
Register
SCITXD
Frame
Format and Mode
8
Parity
Even/Odd
SCICCR.6
TXEMPTY
SCICTL2.6
0
1
8
Enable
TX FIFO_0
TX FIFO_1
TXINT
To CPU
SCICCR.5
TX Interrupt
Logic
TX FIFO Interrupts
8
TX FIFO_N
TXINTENA
SCICTL2.0
TXRDY
8
1
0
TXWAKE
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB
Registers
SCICTL1.0
LSPCLK
RXSHF
Register
SCIRXD
SCIHBAUD.15-8
SCILBAUD.7-0
RXWAKE
8
SCIRXST.1
0
1
8
SCIFFENA
SCIFFTX.14
RX FIFO_0
RX FIFO_1
RXINT
To CPU
8
RX FIFO Interrupts
RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8
1
SCIFFRX.15
0
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
RXERRINTENA
SCICTL1.6
SCICTL1.0
SCIRXST.5
SCI RX Interrupt Select Logic
8
SCIRXST.5-2
BRKDT FE OE PE
RXERROR
Receive Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.7
图9-33. Serial Communications Interface (SCI) Module Block Diagram
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.9.5 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. 图 9-34 shows how the I2C peripheral module interfaces within the
device.
The I2C module has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable/disable capability
• Free data format mode
For more information on the I2C, see the Inter-Integrated Circuit Module (I2C) chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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I2C Module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
SDA
Peripheral Bus
I2CRSR
I2CDRR
Control/Status
Registers
CPU
Clock
Synchronizer
SCL
Prescaler
Noise Filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
图9-34. I2C Peripheral Module Interfaces
The registers in 表9-26 configure and control the I2C port operation.
表9-26. I2C-A Registers
EALLOW
PROTECTED
NAME
ADDRESS
DESCRIPTION
I2C own address register
I2COAR
I2CIER
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
–
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
–
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.9.5.1 I2C 电气数据/时序
节9.9.5.1.1 显示了I2C 时序要求。节9.9.5.1.2 显示了I2C 开关特性。
9.9.5.1.1 I2C 时序要求
最小值
最大值
单位
保持时间，启动条件，SDA 下降后SCL 下降
延迟
th(SDA-SCL)START
0.6
µs
设置时间，重复启动，SDA 下降延迟之前
SCL 上升
tsu(SCL-SDA)START
0.6
µs
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
0
100
20
µs
ns
ns
ns
ns
ns
保持时间，SCL 下降后的数据
设置时间，SCL 上升前的数据
上升时间，SDA
300
300
300
300
输入容差
输入容差
输入容差
输入容差
tr(SCL)
20
上升时间，SCL
tf(SDA)
11.4
11.4
下降时间，SDA
tf(SCL)
下降时间，SCL
设置时间，停止条件，SDA 上升延迟之前
SCL 上升
tsu(SCL-SDA)STOP
0.6
µs
9.9.5.1.2 I2C 开关特性
在推荐的运行条件下（除非另有说明）
参数
测试条件
最小值
最大值
400
单位
I2C 时钟模块频率介于7MHz 与12MHz 之
间，并且I2C 预分频器和时钟分频寄存器进行
了适当配置。
fSCL
kHz
SCL 时钟频率
Vil
0.3 VDDIO
V
V
V
V
低电平输入电压
高电平输入电压
输入滞后
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
0.4
3mA 灌电流
低电平输出电压
I2C 时钟模块频率介于7MHz 与12MHz 之
间，并且I2C 预分频器和时钟分频寄存器进行
了适当配置。
tLOW
1.3
SCL 时钟的低周期
SCL 时钟的高周期
μs
I2C 时钟模块频率介于7MHz 与12MHz 之
间，并且I2C 预分频器和时钟分频寄存器进行
了适当配置。
tHIGH
0.6
-10
μs
输入电压介于0.1 VDDIO 与0.9 VDDIO（最
大值）之间的输入电流
lI
10
μA
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.9.6 Enhanced PWM Modules (ePWM1/2/3/4)
The devices contain up to four enhanced PWM Modules (ePWM). 图 9-35 shows a block diagram of multiple
ePWM modules. 图 9-36 shows the signal interconnections with the ePWM. For more details, see the Enhanced
Pulse Width Modulator (ePWM) chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
表9-27 shows the complete ePWM register set per module.
EPWMSYNCI
EPWM1SYNCI
EPWM1B
EPWM1TZINT
ePWM1
Module
TZ1 to TZ3
EPWM1INT
EPWM2TZINT
PIE
CLOCKFAIL
EMUSTOP
EPWM2INT
EPWMxTZINT
EPWMxINT
TZ5
TZ6
EPWM1ENCLK
TBCLKSYNC
eCAPI
EPWM1SYNCO
EPWM2SYNCI
EPWM1SYNCO
TZ1 to TZ3
COMPOUT1
COMPOUT2
EPWM2B
ePWM2
Module
COMP
CLOCKFAIL
EMUSTOP
EPWM1A
EPWM2A
TZ5
TZ6
H
R
P
W
M
EPWM2ENCLK
TBCLKSYNC
EPWMxA
G
P
I
EPWM2SYNCO
O
M
U
X
SOCA1
SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
ADC
EPWMxSYNCI
EPWMxB
TZ1 to TZ3
ePWMx
Module
CLOCKFAIL
EMUSTOP
TZ5
TZ6
EPWMxENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2
SPCAx
ADCSOCAO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2
SPCBx
ADCSOCBO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
Copyright © 2017, Texas Instruments Incorporated
图9-35. ePWM
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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NAME
表9-27. ePWM Control and Status Registers
SIZE (x16) /
#SHADOW
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
TBCTL
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6806
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6846
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6886
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C6
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
1 / 0
Time Base Control Register
TBSTS
1 / 0
Time Base Status Register
TBPHSHR
TBPHS
1 / 0
Time Base Phase HRPWM Register
Time Base Phase Register
1 / 0
TBCTR
1 / 0
Time Base Counter Register
TBPRD
1 / 1
Time Base Period Register Set
TBPRDHR
CMPCTL
CMPAHR
CMPA
1 / 1
Time Base Period High Resolution Register(1)
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
1 / 0
1 / 1
1 / 1
CMPB
1 / 1
AQCTLA
AQCTLB
AQSFRC
1 / 0
1 / 0
1 / 0
Action Qualifier Continuous S/W Force
Register Set
AQCSFRC
DBCTL
0x680E
0x680F
0x6810
0x684E
0x684F
0x6850
0x688E
0x688F
0x6890
0x68CE
0x68CF
0x68D0
1 / 1
1 / 1
1 / 0
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
Count Register
DBRED
Dead-Band Generator Falling Edge Delay
Count Register
DBFED
0x6811
0x6851
0x6891
0x68D1
1 / 0
TZSEL
0x6812
0x6813
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6821
0x6826
0x6828
0x682A
0x682B
0x682C
0x682D
0x6830
0x6831
0x6832
0x6833
0x6852
0x6853
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
-
0x6892
0x6893
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
-
0x68D2
0x98D3
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
-
1 / 0
1 / 0
Trip Zone Select Register(1)
TZDCSEL
TZCTL
Trip Zone Digital Compare Register
Trip Zone Control Register(1)
1 / 0
TZEINT
TZFLG
1 / 0
Trip Zone Enable Interrupt Register(1)
Trip Zone Flag Register (1)
1 / 0
TZCLR
1 / 0
Trip Zone Clear Register(1)
TZFRC
1 / 0
Trip Zone Force Register(1)
ETSEL
1 / 0
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
1 / 0
ETFLG
1 / 0
ETCLR
1 / 0
Event Trigger Clear Register
ETFRC
1 / 0
Event Trigger Force Register
PCCTL
1 / 0
PWM Chopper Control Register
HRPWM Configuration Register(1)
HRPWM Power Register
HRCNFG
HRPWR
HRMSTEP
HRPCTL
TBPRDHRM
TBPRDM
CMPAHRM
CMPAM
DCTRIPSEL
DCACTL
DCBCTL
DCFCTL
1 / 0
1 / 0
-
-
-
1 / 0
HRPWM MEP Step Register
0x6868
0x686A
0x686B
0x686C
0x686D
0x6870
0x6871
0x6872
0x6873
0x68A8
0x68AA
0x68AB
0x68AC
0x68AD
0x68B0
0x68B1
0x68B2
0x68B3
0x68E8
0x68EA
0x68EB
0x68EC
0x68ED
0x68F0
0x68F1
0x68F2
0x68F3
1 / 0
High resolution Period Control Register(1)
Time Base Period HRPWM Register Mirror
Time Base Period Register Mirror
Compare A HRPWM Register Mirror
Compare A Register Mirror
1 / W(2)
1 / W(2)
1 / W(2)
1 / W(2)
1 / 0
Digital Compare Trip Select Register (1)
Digital Compare A Control Register(1)
Digital Compare B Control Register(1)
Digital Compare Filter Control Register(1)
1 / 0
1 / 0
1 / 0
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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表9-27. ePWM Control and Status Registers (continued)
SIZE (x16) /
#SHADOW
NAME
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
DCCAPCT
0x6834
0x6835
0x6874
0x6875
0x68B4
0x68B5
0x68F4
0x68F5
1 / 0
Digital Compare Capture Control Register(1)
Digital Compare Filter Offset Register
DCFOFFSET
1 / 1
DCFOFFSETCN
T
0x6836
0x6837
0x6838
0x6839
0x6876
0x6877
0x6878
0x6879
0x68B6
0x68B7
0x68B8
0x68B9
0x68F6
0x68F7
0x68F8
0x68F9
1 / 0
1 / 0
1 / 0
1 / 1
Digital Compare Filter Offset Counter Register
Digital Compare Filter Window Register
DCFWINDOW
DCFWINDOWCN
T
Digital Compare Filter Window Counter
Register
DCCAP
Digital Compare Counter Capture Register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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Time-Base (TB)
CTR=ZERO
Sync
In/Out
TBPRD Shadow (24)
TBPRD Active (24)
EPWMxSYNCO
CTR=CMPB
Disabled
Select
Mux
TBPRDHR (8)
8
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
Counter
Up/Down
(16 Bit)
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=ZERO
CTR_Dir
TCBNT
Active (16)
CTR=PRD
CTR=ZERO
TBPHSHR (8)
EPWMxINT
CTR=PRD or ZERO
CTR=CMPA
Event
Trigger
and
Interrupt
(ET)
16
8
EPWMxSOCA
Phase
Control
CTR=CMPB
CTR_Dir
(A)
DCAEVT1.soc
(A)
TBPHS Active (24)
EPWMxSOCB
EPWMxSOCA
ADC
DCBEVT1.soc
EPWMxSOCB
Action
Qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
16
High-resolution PWM (HRPWM)
CMPA Active (24)
CMPA Shadow (24)
EPWMxA
EPWMA
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
16
CMPB Active (16)
EPWMB
EPWMxB
EPWMxTZINT
TZ1 to TZ3
CMPB Shadow (16)
EMUSTOP
CTR=ZERO
CLOCKFAIL
DCAEVT1.inter
DCBEVT1.inter
(A)
(A)
(A)
(A)
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force
DCBEVT2.force
DCAEVT2.inter
DCBEVT2.inter
A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ
signals.
图9-36. ePWM Submodules Showing Critical Internal Signal Interconnections
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.6.1 ePWM 电气数据/时序
PWM 是指ePWM1-4 上的PWM 输出。节9.9.6.1.1 显示了PWM 时序要求和节9.9.6.1.2，开关特性。
9.9.6.1.1 ePWM Timing Requirements
MIN(1)
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
Asynchronous
Synchronous
tw(SYCIN)
Sync input pulse width
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
9.9.6.1.2 ePWM 开关特性
在推荐的运行条件下（除非另有说明）
参数
测试条件
最小值
33.33
最大值
单位
tw(PWM)
ns
脉冲持续时间，PWMx 输出高电平/低电平的时间
tw(SYNCOUT)
8tc(SCO)
同步输出脉冲宽度
周期
延迟时间，跳闸有源输入到PWM 强制高电平
延迟时间，跳闸有源输入到PWM 强制低电平
td(PWM)tza
25
20
ns
无引脚负载
td(TZ-PWM)HZ
ns
延迟时间，触发输入有效至PWM 高阻抗(Hi-Z) 的时间
9.9.6.2 触发区输入时序
9.9.6.2.1 Trip-Zone Input Timing Requirements
MIN(1)
2tc(TBCLK)
2tc(TBCLK)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
cycles
With input qualifier
2tc(TBCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
SYSCLK
tw(TZ)
TZ(A)
td(TZ-PWM)HZ
PWM(B)
A. TZ - TZ1, TZ2, TZ3
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery
software.
图9-37. PWM Hi-Z Characteristics
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.7 High-Resolution PWM (HRPWM)
This module combines multiple delay lines in a single module and a simplified calibration system by using a
dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
• Significantly extends the time resolution capabilities of conventionally derived digital PWM
• This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge
control for frequency/period modulation.
• Finer time granularity control or edge positioning is controlled through extensions to the Compare A and
Phase registers of the ePWM module.
• HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
备注
The minimum SYSCLKOUT frequency allowed for HRPWM is 50 MHz.
备注
When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output is not
available for use.
9.9.7.1 HRPWM 电气数据/时序
节9.9.7.1.1 显示了高分辨率PWM 的开关特性。
9.9.7.1.1 SYSCLKOUT = 50MHz–60MHz 下的高分辨率PWM 特性
参数(1)
最小值 典型值 最大值 单位
微边沿定位(MEP) 步长(2)
150
310
ps
(1) HRPWM 运行在一个最少50MHz 的SYSCLKOUT 频率上。低于50MHz，在器件过程变化时，MEP 阶跃尺寸有可能下降至低于冷却温
度并且高内核电压达到一个要求的值以至于255 MEP 阶跃将不能跨过整个SYSCLKOUT 周期。
(2) 在高温和VDD 上的电压最低时，MEP 步长将达到最大。MEP 步长会随温度升高和电压降低而增加，同时随温度降低和电压升高而减
小。
使用HRPWM 特性的应用应该使用MEP 比例因子优化器(SFO) 估计软件功能。有关在最终应用中使用SFO 函数的详细信息，请参阅
TI 软件库。SFO 函数有助于在HRPWM 运行时动态地估计每个SYSCLKOUT 周期内的MEP 步数量。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.8 Enhanced Capture Module (eCAP1)
The device contains an enhanced capture (eCAP) module. 图 9-38 shows a functional block diagram of a
module.
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Prescale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
CEVT[1:4]
4
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Copyright © 2017, Texas Instruments Incorporated
图9-38. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low-
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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表9-28. eCAP Control and Status Registers
NAME
TSCTR
CTRPHS
CAP1
eCAP1
0x6A00
SIZE (x16) EALLOW PROTECTED
DESCRIPTION
2
2
2
2
2
2
8
1
1
1
1
1
1
6
Time-Stamp Counter
0x6A02
Counter Phase Offset Value Register
Capture 1 Register
0x6A04
CAP2
0x6A06
Capture 2 Register
CAP3
0x6A08
Capture 3 Register
CAP4
0x6A0A
Capture 4 Register
Reserved
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
Reserved
0x6A0C to 0x6A12
0x6A14
Reserved
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Reserved
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A1A to 0x6A1F
For more information on the eCAP, see the Enhanced Capture (eCAP) Module chapter in the
TMS320F2802x,TMS320F2802xx Technical Reference Manual.
9.9.8.1 eCAP 电气数据/时序
节9.9.8.1.1 显示了eCAP 时序要求，而节9.9.8.1.2 显示了eCAP 开关特性。
9.9.8.1.1 Enhanced Capture (eCAP) Timing Requirement
MIN(1)
2tc(SCO)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
9.9.8.1.2 eCAP 开关特性
在推荐的运行条件下（除非额外注明）
参数
测试条件
最小值
最大值
单位
tw(APWM)
20
ns
脉冲持续时间，APWMx 输出高电平/低电平的时间
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.9 JTAG 端口
在 2802x 器件上，JTAG 端口减少到 5 个引脚（TRST、TCK、TDI、TMS、TDO）。TCK、TDI、TMS 和 TDO
引脚也是 GPIO 引脚。TRST 信号在图 9-39 中为引脚选择 JTAG 或者 GPIO 运行模式。在仿真/调试期间，这些
引脚的 GPIO 功能并不可用。如果GPIO38/TCK/XCLKIN 引脚用于提供外部时钟，则应使用替代时钟源在仿真/调
试期间为器件计时，这是因为TCK 功能需要此引脚。
备注
在2802x 器件中，JTAG 引脚也可被用作 GPIO 引脚。在电路板设计时应该小心以确保连接到这些引脚
的电路不会影响 JTAG 引脚功能的仿真能力。要进行成功调试，连接到这些引脚的任何电路不应导致
JTAG 调试探针无法驱动JTAG 引脚（或无法受其驱动）。
TRST = 0: JTAG Disabled (GPIO Mode)
TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
GPIO38_out
C28x
Core
GPIO37_in
TDO
TDO/GPIO37
1
0
GPIO37_out
GPIO36_in
1
0
TMS
TMS/GPIO36
TDI/GPIO35
1
GPIO36_out
GPIO35_in
1
0
TDI
1
GPIO35_out
图9-39. JTAG/GPIO 多路复用
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
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9.9.10 General-Purpose Input/Output (GPIO) MUX
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to
providing individual pin bit-banging I/O capability.
The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). 表 9-29 shows the GPIO register
mapping.
表9-29. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control Register (GPIO0 to 31)
SIZE (x16)
DESCRIPTION
GPACTRL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
0x6F90
0x6F92
0x6F96
0x6F9A
0x6F9C
0x6FB6
0x6FBA
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pullup Disable Register (GPIO0 to 31)
GPIO B Control Register (GPIO32 to 38)
GPIO B Qualifier Select 1 Register (GPIO32 to 38)
GPIO B MUX 1 Register (GPIO32 to 38)
GPAPUD
GPBCTRL
GPBQSEL1
GPBMUX1
GPBDIR
GPIO B Direction Register (GPIO32 to 38)
GPIO B Pullup Disable Register (GPIO32 to 38)
Analog, I/O mux 1 register (AIO0 to AIO15)
Analog, I/O Direction Register (AIO0 to AIO15)
GPBPUD
AIOMUX1
AIODIR
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
0x6FD8
0x6FDA
0x6FDC
0x6FDE
2
2
2
2
2
2
2
2
2
2
2
2
GPIO A Data Register (GPIO0 to 31)
GPASET
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 38)
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPIO B Data Set Register (GPIO32 to 38)
GPIO B Data Clear Register (GPIO32 to 38)
GPIO B Data Toggle Register (GPIO32 to 38)
Analog I/O Data Register (AIO0 to AIO15)
Analog I/O Data Set Register (AIO0 to AIO15)
Analog I/O Data Clear Register (AIO0 to AIO15)
Analog I/O Data Toggle Register (AIO0 to AIO15)
GPBCLEAR
GPBTOGGLE
AIODAT
AIOSET
AIOCLEAR
AIOTOGGLE
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLPMSEL
0x6FE0
0x6FE1
0x6FE2
0x6FE8
1
1
1
2
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO0 to 31)
LPM GPIO Select Register (GPIO0 to 31)
备注
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and
GPxQSELn registers occurs to when the action is valid.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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表9-30. GPIOA MUX
DEFAULT AT RESET
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
PRIMARY I/O
FUNCTION(1) (2)
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00)
(GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 BITS = 11)
1-0
GPIO0
GPIO1
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
Reserved
Reserved
Reserved
Reserved
COMP1OUT (O)
Reserved
3-2
5-4
GPIO2
Reserved
7-6
GPIO3
Reserved
COMP2OUT(3) (O)
9-8
GPIO4
Reserved
Reserved
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO5
Reserved
ECAP1 (I/O)
EPWMSYNCO (O)
Reserved
GPIO6
EPWMSYNCI (I)
SCIRXDA (I)
Reserved
GPIO7
Reserved
Reserved
Reserved
Reserved
GPIO12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ1 (I)
SCITXDA (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPAMUX2 REGISTER
BITS
(GPAMUX2 BITS = 00)
(GPAMUX2 BITS = 01)
(GPAMUX2 BITS = 10)
(GPAMUX2 BITS = 11)
1-0
GPIO16
GPIO17
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
Reserved
Reserved
Reserved
SCITXDA (O)
SCIRXDA (I)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDAA (I/OD)
SCLA (I/OD)
Reserved
Reserved
TZ2 (I)
TZ3 (I)
3-2
5-4
GPIO18
XCLKOUT (O)
ECAP1 (I/O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TZ2 (I)
7-6
GPIO19/XCLKIN
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO28
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCIRXDA (I)
SCITXDA (O)
Reserved
GPIO29
TZ3 (I)
Reserved
Reserved
Reserved
Reserved
Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These functions are not available in the 38-pin package.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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表9-31. GPIOB MUX
DEFAULT AT RESET
PRIMARY I/O
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
FUNCTION(1)
GPBMUX1 REGISTER
BITS
(GPBMUX1 BITS = 00)
(GPBMUX1 BITS = 01)
(GPBMUX1 BITS = 10)
(GPBMUX1 BITS = 11)
1-0
GPIO32(2)
GPIO33(2)
SDAA(2) (I/OD)
SCLA(2) (I/OD)
COMP2OUT (O)
Reserved
EPWMSYNCI(2) (I)
EPWMSYNCO(2) (O)
Reserved
ADCSOCAO (2) (O)
ADCSOCBO (2) (O)
Reserved
3-2
5-4
GPIO34
7-6
GPIO35 (TDI)
GPIO36 (TMS)
GPIO37 (TDO)
GPIO38/XCLKIN (TCK)
Reserved
Reserved
Reserved
9-8
Reserved
Reserved
Reserved
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1) I = Input, O = Output, OD = Open Drain
(2) These pins are not available in the 38-pin package.
表9-32. Analog MUX for 48-Pin PT Package
DEFAULT AT RESET(1)
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOx AND PERIPHERAL SELECTION 1
AIOMUX1 REGISTER BITS
AIOMUX1 BITS = 0,x
ADCINA0 (I), VREFHI (I)
ADCINA1 (I)
AIOMUX1 BITS = 1,x
ADCINA0 (I), VREFHI (I)
ADCINA1 (I)
1-0
3-2
5-4
AIO2 (I/O)
ADCINA2 (I), COMP1A (I)
ADCINA3 (I)
7-6
ADCINA3 (I)
9-8
AIO4 (I/O)
ADCINA4 (I), COMP2A (I)
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
–
–
AIO6 (I/O)
ADCINA7 (I)
ADCINA6 (I)
ADCINA7 (I)
–
–
ADCINB1 (I)
AIO10 (I/O)
ADCINB3 (I)
AIO12 (I/O)
ADCINB1 (I)
ADCINB2 (I), COMP1B (I)
ADCINB3 (I)
ADCINB4 (I), COMP2B (I)
–
–
AIO14 (I/O)
ADCINB7 (I)
ADCINB6 (I)
ADCINB7 (I)
(1) I = Input, O = Output
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
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表9-33. Analog MUX for 38-Pin DA Package
DEFAULT AT RESET(1)
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOx AND PERIPHERAL SELECTION 1
AIOMUX1 REGISTER BITS
AIOMUX1 BITS = 0,x
AIOMUX1 BITS = 1,x
1-0
ADCINA0 (I), VREFHI (I)
ADCINA0 (I), VREFHI (I)
3-2
–
–
5-4
AIO2 (I/O)
ADCINA2 (I), COMP1A (I)
7-6
–
–
9-8
AIO4 (I/O)
ADCINA4 (I)
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
–
–
AIO6 (I/O)
ADCINA6 (I)
–
–
–
–
–
–
AIO10 (I/O)
ADCINB2 (I), COMP1B (I)
–
–
AIO12 (I/O)
ADCINB4 (I)
–
–
AIO14 (I/O)
ADCINB6 (I)
–
–
(1) I = Input, O = Output
The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
• The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the
same (all 0s or all 1s) as shown in 图9-42 (for 6 sample mode).
• No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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GPIOXINT1SEL
GPIOLMPSEL
LPMCR0
GPIOXINT2SEL
GPIOXINT3SEL
External Interrupt
MUX
Low-Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Peripheral 2 Input
Input
Internal
Pullup
Qualification
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. For pin-specific variations, see the
System Control chapter in the TMS320F2802x,TMS320F2802xx Technical Reference Manual.
图9-40. GPIO Multiplexing
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.10.1 GPIO 电气数据/时序
9.9.10.1.1 GPIO - 输出时序
9.9.10.1.1.1 通用输出开关特性
在推荐的运行条件下（除非另有说明）
参数
上升时间，GPIO 从低电平切换至高电平的时间
下降时间，GPIO 从高电平切换至低电平的时间
切换频率
最小值
最大值
单位
tr(GPO)
tf(GPO)
tfGPO
13(1)
13(1)
15
ns
所有GPIO
所有GPIO
ns
MHz
(1) 上升时间和下降时间随着I/O 引脚上的电力负荷变化。节9.9.10.1.1.1 中指定的值适用于一个I/O 引脚上的40pF 负载。
GPIO
t
r(GPO)
t
f(GPO)
图9-41. 通用输出定时
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.10.1.2 GPIO - 输入时序
9.9.10.1.2.1 通用输入时序要求
最小值
最大值
单位
周期
周期
周期
周期
周期
QUALPRD=0
1tc(SCO)
tw(SP)
采样周期
2tc(SCO)*QUALPRD
tw(SP)*(n(1)-1)
QUALPRD≠0
tw(IQSW)
输入限定器采样窗口
2tc(SCO)
同步模式
脉冲持续时间，GPIO 低电平/高电平的时
间
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
带输入限定器
(1) "n" 代表由GPxQSELn 寄存器定义的限定采样的数量。
(2) 对于tw(GPI)，对于一个低电平有效信号，脉宽在VIL 至VIL 之间进行测量，而对于一个高电平有效信号脉宽在VIH 至VIH 之间进行测量。
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)
]
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. 这个毛刺脉冲将被输入限定器所忽略。QUALPRD 位字段指定了限定采样周期。它可在00 至0xFF 间变化。如果QUALPRD=00，那么
采样周期为1 个SYSCLKOUT 周期。对于任何其它的"n" 值，限定采样周期为2n SYSCLKOUT 周期（也就是说，在每一个
SYSCLKOUT 周期上，GPIO 引脚将被采样）。
B. 通过GPxCTRL 寄存器选择的限定期会应用于8 个GPIO 引脚的组。
C. 此限定块可采样3 个或者6 个样本。GPxQSELn 寄存器选择使用的采样模式。
D. 在所示的示例中，为了使限定器检测到变化，输入应该在10 个SYSCLKOUT 周期或者更长的时间内保持稳定。换句话说，输入应该在
(5 x QUALPRD x 2) SYSCLKOUT 周期内保持稳定。这将确保发生5 个用于检测的采样周期。由于外部信号是异步驱动的，因此一个13
SYSCLKOUT 宽的脉冲将会确保可靠识别。
图9-42. 采样模式
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TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.10.1.3 针对输入信号的采样窗口宽度
下面的部分总结了不同的输入限定器配置下用于输入信号的采样窗口宽度。
采样频率表明相对于SYSCLKOUT 的信号采样频率。
如果QUALPRD≠0 的话，采样频率= SYSCLKOUT/(2*QUALPRD)
如果QUALPRD=0 的话，采样频率= SYSCLKOUT
如果QUALPRD≠0 的话，采样周期= SYSCLKOUT 周期x 2 x QUALPRD
在上面的等式中，SYSCLKOUT 周期表明SYSCLKOUT 的时间周期。
如果QUALPRD=0 的话，采样周期= SYSCLKOUT 周期
在指定的采样窗口中，采取输入信号的 3 个样本或者 6 个样本来确定信号的有效性。这取决于写入 GPxQSELn
寄存器的值。
情况1：
使用3 个样本限定
如果QUALPRD≠0 的话，采样窗口宽度=（SYSCLKOUT 周期x 2 x QUALPRD）× 2
如果QUALPRD=0 的话，采样窗口宽度=（SYSCLKOUT 周期）x 2
情况2：
使用6 个样本限定
如果QUALPRD≠0 的话，采样窗口宽度=（SYSCLKOUT 周期x 2 x QUALPRD）× 5
如果QUALPRD=0 的话，采样窗口宽度=（SYSCLKOUT 周期）x 5
SYSCLK
GPIOxn
tw(GPI)
图9-43. 通用输入时序
VDDIO
> 1 MS
2 pF
VSS
VSS
图9-44. 针对带有内部上拉电阻的GPIO 引脚的输入电阻模型
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.10.1.4 低功耗唤醒时序
节9.9.10.1.4.1 显示时序要求，节9.9.10.1.4.2 显示了开关特性，而图9-45 显示了IDEL 模式下的时序图
9.9.10.1.4.1 IDLE Mode Timing Requirements
MIN(1)
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
9.9.10.1.4.2 IDLE Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER(1)
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program execution resume (2)
cycles
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
•
Wake up from Flash
cycles
– Flash module in active state
20tc(SCO) + tw(IQSW)
1050tc(SCO)
1050tc(SCO)
tw(IQSW)
20tc(SCO)
td(WAKE-IDLE)
•
Wake up from Flash
cycles
cycles
+
– Flash module in sleep state
Without input qualifier
With input qualifier
•
Wake up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see 节9.9.10.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
WAKE INT(A)(B)
A. WAKE INT can be any enabled interrupt, WDINT or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
图9-45. IDLE Entry and Exit Timing
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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9.9.10.1.4.3 待机模式时序要求
最小值 最大值
3tc(OSCCLK)
单位
周期
无输入限定
脉冲持续时间，外部唤醒信
号的时间
tw(WAKE-INT)
带输入限定(1)
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY 是LPMCR0 寄存器中的一个6 位字段。
9.9.10.1.4.4 待机模式开关特性
在推荐的运行条件下（除非另有说明）
参数
测试条件
最小值
最大值
单位
周期
周期
延迟时间，IDLE 指令执行到
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
XCLKOUT 低电平的时间
延迟时间，外部唤醒信号到程序执行重新开始的时间(1)
100tc(SCO)
无输入限定器
带输入限定器
无输入限定器
带输入限定器
• 从闪存唤醒
– 激活状态中的闪存模块
周期
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
td(WAKE-STBY)
• 从闪存唤醒
– 睡眠状态中的闪存模块
周期
周期
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
无输入限定器
带输入限定器
• 从SARAM 中唤醒
100tc(SCO) + tw(WAKE-INT)
(1) 这个时间是在IDLE 指令之后立即开始指令执行的时间。ISR（由唤醒信号触发）的执行需要额外延迟。
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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(C)
(F)
(A)
(B)
(D)(E)
(G)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal(H)
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. 执行IDLE 指令将器件置于待机模式。
B. PLL 块响应待机信号。SYSCLKOUT 在关闭之前保持以下所示数量的周期：
• 当DIVSEL=00 或01 时，16 个周期
• 当DIVSEL=10 时，32 个周期
• 当DIVSEL=11 时，64 个周期
此延迟使得CPU 流水线和其他待定操作适当清除。
C. 外设的时钟关闭。然而，PLL 和看门狗未关闭。此器件现在处于待机模式。
D. 外部唤醒信号驱动为有效。
E. 为唤醒器件而馈送给GPIO 引脚的唤醒信号必须符合最小脉冲宽度要求。此外，此信号不能有毛刺。如果噪声信号馈送到GPIO 引脚，器
件的唤醒行为将是不确定的并且在随后的唤醒脉冲中器件可能不会退出低功耗模式。
F. 在延迟周期后，退出待机模式。
G. 正常执行重新开始。器件将响应中断（如果启用）。
H. 自执行将器件置于低功耗模式(LPM) 的IDLE 指令开始，至少经历4 个OSCCLK 周期后才启动唤醒。
图9-46. 待机进入和退出时序图
9.9.10.1.4.5 HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wake-up signal
9.9.10.1.4.6 停机模式开关特性
在推荐的运行条件下（除非另有说明）
参数
最小值
最大值
45tc(SCO)
1
单位
td(IDLE-XCOL)
tp
32tc(SCO)
延迟时间，IDLE 指令执行到XCLKOUT 低电平的时间
PLL 锁存时间
周期
ms
延迟时间，PLL 锁存到程序执行重新开始的时间
• 从闪存唤醒
1125tc(SCO)
周期
周期
td(WAKE-HALT)
– 睡眠状态中的闪存模块
• 从SARAM 中唤醒
35tc(SCO)
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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(C)
(F)
(A)
(H)
(B)
(G)
(D)(E)
Device
Status
HALT
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn(I)
t
)
d(WAKE−HALT
t
w(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE 指令被执行以将器件置于停机模式。
B. PLL 块响应停机信号。在振荡器被关闭并且到内核的CLKIN 被停止前SYSCLKOUT 在下面所示的一定数量的周期内保持：
• 当DIVSEL=00 或01 时，16 个周期
• 当DIVSEL=10 时，32 个周期
• 当DIVSEL=11 时，64 个周期
此延迟使得CPU 流水线和其他待定操作适当清除。
C. 到外设的时钟被关闭并且PLL 被关断。如果一个石英晶振或者陶瓷谐振器被用作时钟源，内部振荡器也被关断。器件现在处于停机模
式，消耗绝对最小功率。可在停机模式中保持零引脚内部振荡器（INTOSC1 和INTOSC2）以及看门狗可用。可通过对CLKCTL 寄存器
中的适当位进行写入操作来实现此功能。
D. 当GPIOn 引脚（用于使器件脱离停机模式）被驱动为低电平时，振荡器开启并且振荡器唤醒序列被启动。只有当振荡器稳定时，GPIO
才应被驱动为高电平。这样可在PLL 锁序列期间提供一个洁净的时钟信号。由于GPIO 引脚的下降边沿会以异步方式开始唤醒过程，因
此在进入停机模式之前和在此模式期间，应该注意保持低噪声环境。
E. 为唤醒器件而馈送给GPIO 引脚的唤醒信号必须符合最小脉冲宽度要求。此外，此信号不能有毛刺。如果噪声信号馈送到GPIO 引脚，器
件的唤醒行为将是不确定的并且在随后的唤醒脉冲中器件可能不会退出低功耗模式。
F. 一旦振荡器已经稳定，PLL 锁序列被启动（耗时1ms）。
G. 当到内核的CLKIN 被启用时，在一个延迟后，此器件响应此中断（如果被启用）。现在退出停机模式。
H. 正常运行重新开始。
I.
自执行将器件置于低功耗模式(LPM) 的IDLE 指令开始，至少经历4 个OSCCLK 周期后才启动唤醒。
图9-47. 使用GPIOn 唤醒停机模式
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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10 应用、实施和布局
备注
以下部分中的信息不属于 TI 器件规范，TI 不保证其准确性和完整性。TI 客户应负责确定这些元件是否
适用于其应用。客户应验证并测试其设计实现，以确认系统功能。
10.1 TI 参考设计
TI 参考设计库是一个涵盖模拟、嵌入式处理器和连接的强大参考设计资源库。所有参考设计由 TI 专家构建，旨在
帮助您快速开始系统设计，其中包括原理图或方框图、BOM 和设计文件，助您加快产品上市步伐。在精选 TI 参
考设计页面上搜索并下载设计。
具有响应时间小于1us 的堵转电流限制的36V/1kW 无刷直流电机驱动器参考设计
此参考设计可用作电池供电式园艺工具和电动工具中无刷电机的功率级，额定功率高达 1kW，使用 10 节锂离子
电池，电压范围为 36V 至 42V。设计采用 60V、N 沟道 NexFET™ 技术和 SON5x6 SMD 封装，具有极低的
1.8mΩ漏源极电阻 (RDS_ON)，可实现 57mm × 59mm 的小尺寸 PCB。三相栅极驱动器用于驱动三相MOSFET
电桥，该电桥可在 6V 至 60V 的电压范围内工作，支持可编程栅极电流（最高 2.3A 灌电流/1.7A 拉电流）。
C2000 F28027 LaunchPad™ 开发套件 (LAUNCHXL-F28027) 与此功率级结合使用，并在软件中通过霍尔传感器
实现对 BLDC 电机的 120 度梯形控制。栅极驱动器的逐周期电流限制特性将功率级中允许的最大电流限制到安全
级别，从而保护电路板免受电机失速期间导致的过流损害。
使用磁通门传感器通过单端信号调节电路进行电流和电压测量
此设计为集成在微控制器中通过磁通门传感器测量电机电流的单端 SAR ADC 提供 4 通道信号调节解决方案。此
外还提供带有外部 SAR ADC 的备选测量电路以及高速过流和接地故障检测电路。适当的信号调节可在电机驱动
中提高关键电路测量的抗噪性能。此参考设计有助于增加模数转换的有效分辨率，提高电机驱动效率。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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11 器件和文档支持
11.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
™
MCU devices and support tools. Each TMS320 MCU commercial family member has one of three prefixes:
TMX, TMP, or TMS (for example, TMS320F28023). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/
TMDS).
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PT) and temperature range (for example, S). 图 11-1 provides a legend for reading the complete
device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2802x,
TMS320F2802xx MCUs Silicon Errata.
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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A. For more information on peripheral, temperature, and package availability for a specific device, see 表6-1.
图11-1. Device Nomenclature
11.2 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs –Design & development page.
Development Tools
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking you through each step
of the application development flow. Familiar tools and interfaces allow users to get started faster than ever
before. CCS combines the advantages of the Eclipse software framework with advanced embedded debug
capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
C2000 F28027 LaunchPad™ development kit
The C2000 F28027 LaunchPad™ development kit is an inexpensive, modular, and fun evaluation platform,
enabling you to dive into real-time, closed-loop control development with Texas Instruments’ C2000 32-bit
microcontroller family. This platform provides a great starting point for development of many common power
electronics applications, including motor control, digital power supplies, solar inverters, digital LED lighting,
precision sensing, and more.
To view all available C2000 LaunchPad development kits and BoosterPack™ plug-in modules, visit the
Embedded development hardware kits & boards site.
Software Tools
powerSUITE - Digital Power Supply Design Software Tools for C2000™ MCUs
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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powerSUITE is a suite of digital power supply design software tools for Texas Instruments' C2000 real-time
microcontroller (MCU) family. powerSUITE helps power supply engineers drastically reduce development time
as they design digitally-controlled power supplies based on C2000 real-time control MCUs.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs –Support & training site.
Specific TMS320F2802x hands-on training resources can be found at C2000™ MCU Device Workshops.
InstaSPIN-FOC LaunchPad and BoosterPack
This 6-part series provides information about the C2000 InstaSPIN-FOC Motor Control LaunchPad Development
Kit and BoosterPack Plug-in Module.
The InstaSPIN-FOC enabled C2000 F28027 LaunchPad™ development kit is an inexpensive evaluation
platform designed to help you leap right into the world of sensorless motor control using the InstaSPIN-FOC
solution.
• Part 1: Introduction and Overview
• Part 2: Identifying Your Motor
• Part 3: Zero Speed, Low Speed, & Tuning
• Part 4: Accelerations & Speed Reversals with Texas Instruments
• Part 5: High, Higher, Highest Speeds with Texas Instruments
• BOOSTXL-DRV8301 BoosterPack with Texas Instruments
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Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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11.3 文档支持
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
下面列出了介绍处理器、相关外设以及其他配套技术资料的最新文档。
勘误
TMS320F2802x、TMS320F2802xx MCU 器件勘误表介绍了器件上的已知问题并提供了权变措施。
技术参考手册
TMS320F2802x、TMS320F2802xx 技术参考手册详述了器件中每一个外设和子系统的集成、环境、功能说明，
以及编程模型。
InstaSPIN 技术参考手册
InstaSPIN-FOC™ 和InstaSPIN-MOTION™ 用户指南介绍了InstaSPIN-FOC 和InstaSPIN-MOTION 器件。
TMS320F28026F、TMS320F28027F InstaSPIN™-FOC 软件技术参考手册介绍了 TMS320F28026F 和
TMS320F28027F InstaSPIN-FOC 软件。
CPU 用户指南
TMS320C28x CPU 和指令集参考指南描述了 TMS320C28x 定点数字信号处理器 (DSP) 的中央处理器 (CPU) 和
汇编语言指令。此参考指南还介绍了上述DSP 所提供的仿真特性。
外设指南
C2000 实时控制外设参考指南介绍了28x 数字信号处理器(DSP) 的外设参考指南。
工具指南
TMS320C28x 汇编语言工具 v20.2.0.LTS 用户指南介绍了用于 TMS320C28x 器件的汇编语言工具（用于开发汇
编语言代码的汇编器和其他工具）、汇编器指令、宏、通用目标文件格式和符号调试指令。
TMS320C28x 优化 C/C++ 编译器 v20.2.0.LTS 用户指南介绍了 TMS320C28x C/C++ 编译器。此编译器接受
ANSI 标准C/C++ 源代码，并为TMS320C28x 器件生成TMS320 DSP 汇编语言源代码。
应用报告
半导体封装方法介绍了准备半导体器件以发货给最终用户时所用的封装方法。
计算嵌入式处理器的有效使用寿命介绍了如何计算 TI 嵌入式处理器 (EP) 在电子系统中运行时的有效使用寿命。
本文档的目标读者为希望确定TI EP 的可靠性是否符合终端系统可靠性要求的总工程师。
半导体和IC 封装热指标介绍了以前和更新的热指标，并将它们应用于系统级结温估算。
计算任务剖面的FIT 说明了如何使用TI 的可靠性降额工具计算系统任务剖面在加电条件下的元件级FIT。
振荡器补偿指南介绍了一种为内部振荡器补偿温度引起的频率漂移的工厂方法。
IBIS（I/O 缓冲器信息规范）建模简介讨论了 IBIS 的各个方面，包括其历史、优势、兼容性、模型生成流程、输
入/输出结构建模中的数据要求以及未来趋势。
C2000™ 微控制器串行闪存编程讨论了如何使用闪存内核和ROM 加载程序对器件进行串行编程。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
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TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
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11.5 商标
InstaSPIN-FOC™, TMS320C2000™, NexFET™, LaunchPad™, TMS320™, BoosterPack™, InstaSPIN-MOTION™,
and TI E2E™ are trademarks of Texas Instruments.
I2C 总线® is a registered trademark of NXP B.V. Corporation.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1, TMS320F28026
TMS320F28026-Q1, TMS320F28026F, TMS320F28026F-Q1, TMS320F28023
TMS320F28023-Q1, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200
ZHCSA13P –NOVEMBER 2008 –REVISED FEBRUARY 2021
www.ti.com.cn
12 机械、封装和可订购信息
12.1 封装信息
下述页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，
且不会对此文档进行修订。有关此数据表的基于浏览器的版本，请查阅左侧的导航栏。
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback 125
Product Folder Links: TMS320F28027 TMS320F28027-Q1 TMS320F28027F TMS320F28027F-Q1
TMS320F28026 TMS320F28026-Q1 TMS320F28026F TMS320F28026F-Q1 TMS320F28023 TMS320F28023-
Q1 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DA
DA
PT
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320F280200DAS
TMS320F280200DAT
TMS320F280200PTT
TMS320F28020DAS
TMS320F28020DAT
TMS320F28020PTS
TMS320F28020PTT
TMS320F28021DAS
TMS320F28021DAT
TMS320F28021PTS
TMS320F28021PTT
TMS320F28022DAQ
TMS320F28022DAQR
TMS320F28022DAS
TMS320F28022DAT
TMS320F28022PTQ
TMS320F28022PTS
ACTIVE
TSSOP
TSSOP
LQFP
38
38
48
38
38
48
48
38
38
48
48
38
38
38
38
48
48
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
F280200DAS
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
S320
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
40
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F280200DAT
S320
250
40
S320 980
F280200PTT
TSSOP
TSSOP
LQFP
DA
DA
PT
F28020DAS
S320
40
F28020DAT
S320
250
250
40
S320 980
F28020PTS
LQFP
PT
S320 980
F28020PTT
TSSOP
TSSOP
LQFP
DA
DA
PT
F28021DAS
S320
40
F28021DAT
S320
250
250
40
S320 980
F28021PTS
LQFP
PT
(S320, S320 980)
F28021PTT
TSSOP
TSSOP
TSSOP
TSSOP
LQFP
DA
DA
DA
DA
PT
F28022DAQ
S320
2000 RoHS & Green
F28022DAQ
S320
40
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
-40 to 125
-40 to 105
-40 to 125
-40 to 125
F28022DAS
S320
F28022DAT
S320
250
250
(S320, S320 980)
F28022PTQ
LQFP
PT
S320 980
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
F28022PTS
TMS320F28022PTT
TMS320F28023DAQ
TMS320F28023DAS
TMS320F28023DAT
TMS320F28023PTQ
TMS320F28023PTS
TMS320F28023PTT
TMS320F28026DAQ
TMS320F28026DAS
TMS320F28026DAT
TMS320F28026FPTQ
TMS320F28026FPTT
TMS320F28026PTQ
TMS320F28026PTS
TMS320F28026PTT
TMS320F28027DAQ
TMS320F28027DAS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
TSSOP
TSSOP
TSSOP
LQFP
PT
DA
DA
DA
PT
PT
PT
DA
DA
DA
PT
PT
PT
PT
PT
DA
DA
48
38
38
38
48
48
48
38
38
38
48
48
48
48
48
38
38
250
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
S320 980
F28022PTT
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
F28023DAQ
S320
40
F28023DAS
S320
40
F28023DAT
S320
250
250
250
40
(S320, S320 980)
F28023PTQ
LQFP
S320 980
F28023PTS
LQFP
(S320, S320 980)
F28023PTT
TSSOP
TSSOP
TSSOP
LQFP
F28026DAQ
S320
40
F28026DAS
S320
40
F28026DAT
S320
250
250
250
250
250
40
S320F 980
28026FPTQ
LQFP
S320 980
F28026FPTT
LQFP
(S320, S320 980)
F28026PTQ
LQFP
S320 980
F28026PTS
LQFP
(S320, S320 980)
F28026PTT
TSSOP
TSSOP
F28027DAQ
S320
40
F28027DAS
S320
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DA
DA
DA
PT
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320F28027DASR
TMS320F28027DAT
TMS320F28027DATR
TMS320F28027FPTQ
TMS320F28027FPTT
TMS320F28027FPTTR
TMS320F28027PTQ
TMS320F28027PTQR
TMS320F28027PTR
TMS320F28027PTS
TMS320F28027PTT
ACTIVE
TSSOP
TSSOP
TSSOP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
38
38
38
48
48
48
48
48
48
48
48
2000 RoHS & Green
40 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
F28027DAS
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
S320
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F28027DAT
S320
F28027DAT
S320
250
250
RoHS & Green
RoHS & Green
S320
F28027FPTQ
PT
S320 980
F28027FPTT
PT
1000 RoHS & Green
250 RoHS & Green
S320 980
F28027FPTT
PT
(S320, S320 980)
F28027PTQ
PT
1000 RoHS & Green
1000 RoHS & Green
S320
F28027PTQ
PT
S320
F28027PTT
PT
250
250
RoHS & Green
RoHS & Green
S320 980
F28027PTS
PT
S320 980
F28027PTT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jul-2023
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F28022, TMS320F28022-Q1, TMS320F28023, TMS320F28023-Q1, TMS320F28026, TMS320F28026-Q1, TMS320F28026F,
TMS320F28026F-Q1, TMS320F28027, TMS320F28027-Q1, TMS320F28027F, TMS320F28027F-Q1 :
Catalog : TMS320F28022, TMS320F28023, TMS320F28026, TMS320F28026F, TMS320F28027, TMS320F28027F
•
Automotive : TMS320F28022-Q1, TMS320F28023-Q1, TMS320F28026-Q1, TMS320F28026F-Q1, TMS320F28027-Q1, TMS320F28027F-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMS320F28022DAQR
TMS320F28027DASR
TMS320F28027DATR
TMS320F28027PTR
TSSOP
TSSOP
TSSOP
LQFP
DA
DA
DA
PT
38
38
38
48
2000
2000
2000
1000
330.0
330.0
330.0
330.0
24.4
24.4
24.4
16.4
8.6
8.6
8.6
9.6
13.0
13.0
13.0
9.6
1.8
1.8
1.8
1.9
12.0
12.0
12.0
12.0
24.0
24.0
24.0
16.0
Q1
Q1
Q1
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMS320F28022DAQR
TMS320F28027DASR
TMS320F28027DATR
TMS320F28027PTR
TSSOP
TSSOP
TSSOP
LQFP
DA
DA
DA
PT
38
38
38
48
2000
2000
2000
1000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TMS320F280200DAS
TMS320F280200DAT
TMS320F28020DAS
TMS320F28020DAT
TMS320F28021DAS
TMS320F28021DAT
TMS320F28022DAQ
TMS320F28022DAS
TMS320F28022DAT
TMS320F28023DAQ
TMS320F28023DAS
TMS320F28023DAT
TMS320F28026DAQ
TMS320F28026DAS
TMS320F28026DAT
TMS320F28027DAQ
TMS320F28027DAS
TMS320F28027DAT
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
DA
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
38
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
530
530
530
530
530
530
530
530
530
530
530
530
530
530
530
530
530
530
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
11.89
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
3600
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
4.9
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
TRAY
L - Outer tray length without tabs
KO -
Outer
tray
height
W -
Outer
tray
width
Text
P1 - Tray unit pocket pitch
CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
TMS320F280200PTT
TMS320F28020PTT
TMS320F28021PTS
TMS320F28021PTT
TMS320F28022PTQ
TMS320F28022PTS
TMS320F28022PTT
TMS320F28023PTQ
TMS320F28023PTS
TMS320F28023PTT
TMS320F28026FPTQ
TMS320F28026FPTT
TMS320F28026PTQ
TMS320F28026PTS
TMS320F28026PTT
TMS320F28027FPTQ
TMS320F28027FPTT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
PT
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
48
250
250
250
250
250
250
250
250
250
250
250
250
250
250
250
250
250
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
10 x 25
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
11.1 11.25
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jun-2023
Device
Package Package Pins SPQ Unit array
Max
L (mm)
W
K0
P1
CL
CW
Name
Type
matrix temperature
(°C)
(mm) (µm) (mm) (mm) (mm)
TMS320F28027PTQ
TMS320F28027PTS
TMS320F28027PTT
PT
PT
PT
LQFP
LQFP
LQFP
48
48
48
250
250
250
10 x 25
10 x 25
10 x 25
150
150
150
315 135.9 7620 12.2
315 135.9 7620 12.2
315 135.9 7620 12.2
11.1 11.25
11.1 11.25
11.1 11.25
Pack Materials-Page 5
PACKAGE OUTLINE
PT0048A
LQFP - 1.6 mm max height
S
C
A
L
E
2
.
0
0
0
LOW PROFILE QUAD FLATPACK
9.2
8.8
7.2
6.8
B
A
9.2
8.8
7.2
6.8
0.27
48X
0.17
0.08
C A B
44X 0.5
4X 5.5
SEE DETAIL A
1.6 MAX
C
SEATING PLANE
0.1 C
1.45
1.35
0.25
GAGE PLANE
0.75
0.45
0.5 MIN
0 -7
A15.000
DETAIL A
4215159/A 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
4. This may also be a thermally enhanced plastic package with leads conected to the die pads.
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EXAMPLE BOARD LAYOUT
PT0048A
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
PKG
SYMM
48
37
SEE SOLDER MASK
DETAILS
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM
(8.2)
(R0.05) TYP
12
25
13
24
(8.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE 10.000
0.05 MAX
ALLAROUND
0.05 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
METAL EDGE
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215159/A 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PT0048A
LQFP - 1.6 mm max height
LOW PROFILE QUAD FLATPACK
PKG
SYMM
48
37
48X (1.6)
1
36
48X (0.3)
44X (0.5)
PKG SYMM
(8.2)
(R0.05) TYP
12
25
13
24
(8.2)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 10X
4215159/A 12/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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