TMS320F28030-Q1 [TI]
TMS320F2803x Microcontrollers;
| 型号： | TMS320F28030-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F2803x Microcontrollers 微控制器 |
| 文件： | 总167页 (文件大小：2698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
TMS320F2803x Microcontrollers
1 Device Overview
1.1 Features
1
• High-efficiency 32-bit CPU (TMS320C28x)
– 60 MHz (16.67-ns cycle time)
• Code-security module
• 128-bit security key and lock
– Protects secure memory blocks
– Prevents firmware reverse engineering
• Serial port peripherals
– 16 × 16 and 32 × 32 MAC operations
– 16 × 16 dual MAC
– Harvard bus architecture
– Atomic operations
– One Serial Communications Interface (SCI)
Universal Asynchronous Receiver/Transmitter
(UART) module
– Two Serial Peripheral Interface (SPI) modules
– One Inter-Integrated-Circuit (I2C) module
– One Local Interconnect Network (LIN) module
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
• Programmable Control Law Accelerator (CLA)
– 32-bit floating-point math accelerator
– Executes code independently of the main CPU
• Endianness: Little endian
– One Enhanced Controller Area Network (eCAN)
module
• Enhanced control peripherals
– ePWM
• JTAG boundary scan support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
• Low cost for both device and system:
– Single 3.3-V supply
– High-Resolution PWM (HRPWM)
– Enhanced Capture (eCAP) module
– High-Resolution Input Capture (HRCAP) module
– Enhanced Quadrature Encoder Pulse (eQEP)
module
– Analog-to-Digital Converter (ADC)
– On-chip temperature sensor
– Comparator
– No power sequencing requirement
– Integrated power-on reset and brown-out reset
– Low power
– No analog support pins
• Clocking:
• Advanced emulation features
– Analysis and breakpoint functions
– Real-time debug through hardware
• Package options
– 56-Pin RSH Very Thin Quad Flatpack (No lead)
(VQFN)
– 64-Pin PAG Thin Quad Flatpack (TQFP)
– 80-Pin PN Low-Profile Quad Flatpack (LQFP)
• Temperature options
– Two internal zero-pin oscillators
– On-chip crystal oscillator and external clock
input
– Watchdog timer module
– Missing clock detection circuitry
• Up to 45 individually programmable, multiplexed
GPIO pins with input filtering
• Peripheral Interrupt Expansion (PIE) block that
supports all peripheral interrupts
– T: –40°C to 105°C
• Three 32-bit CPU timers
– S: –40°C to 125°C
– Q: –40°C to 125°C
• Independent 16-bit timer in each Enhanced Pulse
Width Modulator (ePWM)
(AEC Q100 qualification for automotive
applications)
• On-chip memory
– Flash, SARAM, OTP, Boot ROM available
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
1.2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Air conditioner outdoor unit
Door operator drive control
DC/DC converter
•
•
•
•
•
•
•
•
•
•
•
•
Micro inverter
Solar power optimizer
String inverter
Inverter & motor control
AC drive control module
Linear motor segment controller
Servo drive power stage module
AC-input BLDC motor drive
DC-input BLDC motor drive
Industrial AC-DC
On-board (OBC) & wireless charger
Automated sorting equipment
Textile machine
Welding machine
AC charging (pile) station
DC charging (pile) station
EV charging station power module
Wireless vehicle charging module
Energy storage power conversion system (PCS)
Three phase UPS
Merchant network & server PSU
Merchant telecom rectifiers
1.3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-
loop performance in real-time control applications such as industrial motor drives; solar inverters and
digital power; electrical vehicles and transportation; motor control; and sensing and signal processing. The
C2000 line includes the Premium performance MCUs and the Entry performance MCUs.
The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator
(CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-
compatible with previous C28x-based code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Enhancements have been made to the
HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit
references have been added and can be routed directly to control the PWM outputs. The ADC converts
from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC
interface has been optimized for low overhead and latency.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information(1)
PART NUMBER
TMS320F28035PN
PACKAGE
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
TQFP (64)
TQFP (64)
TQFP (64)
TQFP (64)
TQFP (64)
TQFP (64)
VQFN (56)
VQFN (56)
BODY SIZE
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
7.0 mm × 7.0 mm
TMS320F28034PN
TMS320F28033PN
TMS320F28032PN
TMS320F28031PN
TMS320F28030PN
TMS320F28035PAG
TMS320F28034PAG
TMS320F28033PAG
TMS320F28032PAG
TMS320F28031PAG
TMS320F28030PAG
TMS320F28035RSH
TMS320F28034RSH
7.0 mm × 7.0 mm
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Device Overview
2
Copyright © 2009–2020, Texas Instruments Incorporated
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
Device Information(1) (continued)
PART NUMBER
TMS320F28033RSH
PACKAGE
VQFN (56)
VQFN (56)
VQFN (56)
VQFN (56)
BODY SIZE
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
7.0 mm × 7.0 mm
TMS320F28032RSH
TMS320F28031RSH
TMS320F28030RSH
Copyright © 2009–2020, Texas Instruments Incorporated
Device Overview
3
Submit Documentation Feedback
Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
1.4 Functional Block Diagram
Functional Block Diagram shows the functional block diagram for the device.
M0
SARAM 1K × 16
(0-wait)
OTP 1K × 16
Secure
SARAM
4K/6K/8K × 16
(CLA Only on
28033 and 28035)
(0-wait)
M1
SARAM 1K × 16
(0-wait)
Code
Security
Module
FLASH
16K/32K/64K × 16
Secure
Secure
Boot-ROM
8K × 16
(0-wait)
OTP/Flash
Wrapper
PSWD
Memory Bus
CLA
TRST
TCK
TDI
TMS
TDO
COMP1OUT
COMP2OUT
COMP3OUT
GPIO
MUX
C28x
32-Bit CPU
GPIO
Mux
COMP1A
COMP1B
COMP2A
COMP2B
COMP3A
COMP3B
COMP
3 External Interrupts
PIE
XCLKIN
OSC1,
OSC2,
Ext,
CPU Timer 0
X1
X2
AIO
CPU Timer 1
CPU Timer 2
Memory Bus
LPM Wakeup
MUX
PLL,
LPM,
WD
XRS
ADC
A7:0
B7:0
POR/
BOR
VREG
32-Bit Peripheral Bus
(CLA-Accessible)
32-Bit Peripheral Bus
16-Bit Peripheral Bus
eCAN
(32-mail
box)
ePWM
SCI
(4L FIFO)
SPI
I2C
LIN
eCAP
eQEP
HRCAP
(4L FIFO)
(4L FIFO)
HRPWM
From
COMP1OUT,
COMP2OUT,
COMP3OUT
GPIO MUX
Copyright © 2017, Texas Instruments Incorporated
A. Not all peripheral pins are available at the same time due to multiplexing.
Figure 1-1. Functional Block Diagram
4
Device Overview
Copyright © 2009–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
Table of Contents
1
Device Overview ......................................... 1
5.14 Flash Timing ........................................ 39
Detailed Description ................................... 41
6.1 Overview ............................................ 41
6.2 Memory Maps ...................................... 50
6.3 Register Maps....................................... 57
6.4 Device Emulation Registers......................... 59
6.5 VREG/BOR/POR.................................... 60
6.6 System Control ...................................... 62
6.7 Low-power Modes Block ............................ 70
6.8 Interrupts ............................................ 71
6.9 Peripherals .......................................... 76
Applications, Implementation, and Layout ...... 145
7.1 TI Reference Design............................... 145
Device and Documentation Support.............. 146
1.1 Features .............................................. 1
1.2 Applications........................................... 2
1.3 Description............................................ 2
1.4 Functional Block Diagram ........................... 4
Revision History ......................................... 6
Device Comparison ..................................... 7
3.1 Related Products ..................................... 9
Terminal Configuration and Functions ............ 10
4.1 Pin Diagrams........................................ 10
4.2 Signal Descriptions.................................. 14
Specifications ........................................... 22
5.1 Absolute Maximum Ratings ........................ 22
5.2 ESD Ratings – Automotive.......................... 22
5.3 ESD Ratings – Commercial......................... 23
5.4 Recommended Operating Conditions............... 23
5.5 Power Consumption Summary...................... 24
5.6 Electrical Characteristics............................ 28
5.7 Thermal Resistance Characteristics ................ 29
5.8 Thermal Design Considerations .................... 31
6
2
3
4
5
7
8
8.1
Device and Development Support Tool
Nomenclature ...................................... 146
8.2 Tools and Software ................................ 147
8.3 Documentation Support............................ 149
8.4 Related Links ...................................... 150
8.5 Support Resources ................................ 150
8.6 Trademarks ........................................ 150
8.7 Electrostatic Discharge Caution ................... 150
8.8 Glossary............................................ 150
5.9
JTAG Debug Probe Connection Without Signal
Buffering for the MCU............................... 31
5.10 Parameter Information .............................. 32
5.11 Test Load Circuit ................................... 32
5.12 Power Sequencing .................................. 33
5.13 Clock Specifications................................. 36
9
Mechanical, Packaging, and Orderable
Information............................................. 151
9.1 Packaging Information ............................. 151
Copyright © 2009–2020, Texas Instruments Incorporated
Table of Contents
5
Submit Documentation Feedback
Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
2 Revision History
Changes from January 8, 2019 to June 24, 2020 (from M Revision (January 2019) to N Revision)
Page
•
•
•
Global: Changed "emulator" to "JTAG debug probe". .......................................................................... 1
Section 1.2 (Applications): Updated section. ..................................................................................... 2
Section 5.1 (Absolute Maximum Ratings): Changed "Input clamp current" condition from "Digital input (per
pin), ..." to "Digital/analog input (per pin), ...". ................................................................................... 22
Section 5.1: Updated footnote about continuous clamp current............................................................... 22
Section 5.1: Updated "Long-term high-temperature storage ..." footnote. .................................................. 22
Section 5.3 (ESD Ratings – Commercial): Added "ANSI/ESDA/JEDEC JS-002" to Charged-device model
•
•
•
(CDM). ............................................................................................................................... 23
Section 5.5.1 (Reducing Current Consumption): Updated list of methods for reducing power consumption. .......... 25
Figure 6-11 (CPU Watchdog Module): Added SCSR(WDOVERRIDE). .................................................... 69
Table 6-37 (SPI Master Mode External Timing (Clock Phase = 0)): Updated MIN values of Parameter 23, td(SPC)M. . 98
Table 6-38 (SPI Master Mode External Timing (Clock Phase = 1)): Updated MIN values of Parameter 23,
•
•
•
•
td(SPC)M. ............................................................................................................................... 99
Figure 6-33 (Serial Communications Interface (SCI) Module Block Diagram): Updated figure. ........................ 105
Section 7.1 (TI Reference Design): Changed section title from "TI Design or Reference Design" to "TI Reference
Design". Updated section. ....................................................................................................... 145
Section 8 (Device and Documentation Support): Removed "Getting Started" section. See the Applications
section and the Related Links table. ............................................................................................ 146
Section 8: Changed "Community Resources" section to "Support Resources" section. Updated section............. 146
Section 8.2 (Tools and Software): Updated section........................................................................... 147
Section 8.3 (Documentation Support): Updated section. .................................................................... 149
•
•
•
•
•
•
6
Revision History
Copyright © 2009–2020, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
3 Device Comparison
Table 3-1 lists the features of the TMS320F2803x devices.
Table 3-1. Device Comparison
28030
(60 MHz)
28031
(60 MHz)
28032
(60 MHz)
28033
(60 MHz)
28034
(60 MHz)
28035
(60 MHz)
FEATURE
TYPE(1)
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
Package Type
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
Instruction cycle
–
0
–
–
16.67 ns
No
16.67 ns
No
16.67 ns
No
16.67 ns
Yes
16.67 ns
No
16.67 ns
Yes
Control Law Accelerator (CLA)
On-chip flash (16-bit word)
On-chip SARAM (16-bit word)
16K
32K
32K
32K
64K
64K
6K
8K
10K
10K
10K
10K
Code security for on-chip
flash/SARAM/OTP blocks
–
–
–
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Boot ROM (8K x 16)
One-time programmable (OTP) ROM
(16-bit word)
ePWM channels
eCAP inputs
1
0
0
–
14
12
8
14
12
8
14
12
8
14
12
8
14
12
8
14
12
8
1
1
1
1
1
1
eQEP modules
Watchdog timer
MSPS
1
Yes
2.0
1
Yes
2.0
1
Yes
4.6
1
Yes
4.6
1
Yes
4.6
1
Yes
4.6
Conversion Time
500.00 ns
14
500.00 ns
14
216.67 ns
14
216.67 ns
14
216.67 ns
14
216.67 ns
14
12-Bit ADC
Channels
3
16
13
16
13
16
13
16
13
16
13
16
13
Temperature Sensor
Dual Sample-and-Hold
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
32-Bit CPU timers
–
1
High-resolution ePWM Channels
–
–
7
2
6
4
–
7
2
6
4
–
7
2
6
4
–
7
2
6
4
–
High-resolution Capture (HRCAP)
Modules
0
–
–
2
2
2
2
Comparators with Integrated DACs
Inter-integrated circuit (I2C)
0
0
3
1
3
1
3
1
3
1
3
1
3
1
Enhanced Controller Area Network
(eCAN)
0
1
1
1
1
1
1
Local Interconnect Network (LIN)
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
0
1
0
–
–
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
GPIO
45
33
6
26
45
33
6
26
45
33
6
26
45
33
6
26
45
33
6
26
45
33
6
26
I/O pins
(shared)
AIO
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the
basic functionality of the module. These device-specific differences are listed in the C2000 Real-Time Control Peripherals Reference Guide and in the TMS320F2803x Technical
Reference Manual.
Copyright © 2009–2020, Texas Instruments Incorporated
Device Comparison
7
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
Table 3-1. Device Comparison (continued)
28030
(60 MHz)
28031
(60 MHz)
28032
(60 MHz)
28033
(60 MHz)
28034
(60 MHz)
28035
(60 MHz)
FEATURE
TYPE(1)
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
80-Pin
PN
64-Pin
PAG
56-Pin
RSH
Package Type
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
LQFP
TQFP
VQFN
External interrupts
–
–
–
–
–
3
3
3
3
3
3
Supply voltage (nominal)
3.3 V
Yes
Yes
3.3 V
Yes
Yes
3.3 V
Yes
Yes
3.3 V
Yes
Yes
3.3 V
Yes
Yes
3.3 V
Yes
Yes
T: –40°C to 105°C
Temperature
options
S: –40°C to 125°C
Q: –40°C to 125°C(2)
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
(2) The letter Q refers to AEC Q100 qualification for automotive applications.
8
Device Comparison
Copyright © 2009–2020, Texas Instruments Incorporated
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
3.1 Related Products
For information about similar products, see the following links:
TMS320F2802x Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions
are available.
TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces
the parallel control law accelerator (CLA) option.
TMS320F2805x Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
TMS320F2806x Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the
pin-count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-
MOTION™ versions are available.
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral
options. The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog
technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
The F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and
configurable logic block (CLB) versions are available.
Copyright © 2009–2020, Texas Instruments Incorporated
Device Comparison
9
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 shows the 56-pin RSH Very Thin Quad Flatpack (No Lead) (VQFN) pin assignments. Figure 4-
2 shows the 64-pin PAG Thin Quad Flatpack (TQFP) pin assignments. Figure 4-3 shows the 80-pin PN
Low-Profile Quad Flatpack (LQFP) pin assignments.
10
Terminal Configuration and Functions
Copyright © 2009–2020, Texas Instruments Incorporated
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Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
43
44
45
46
47
48
49
50
51
52
53
54
55
56
28
GPIO36/TMS
GPIO28/SCIRXDA/SDAA/TZ2
27
26
25
24
23
22
21
20
19
18
17
16
15
GPIO5/EPWM3B/SPISIMOA/ECAP1
TEST2
VDDIO
VSS
GPIO4/EPWM3A
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
GPIO2/EPWM2A
GPIO29/SCITXDA/SCLA/TZ3
GPIO30/CANRXA
GPIO31/CANTXA
ADCINB7
GPIO1/EPWM1B/COMP1OUT
GPIO0/EPWM1A
VDDIO
VSS
ADCINB6/COMP3B/AIO14
ADCINB4/COMP2B/AIO12
ADCINB3
VDD
VREGENZ
GPIO34/COMP2OUT/COMP3OUT
GPIO20/EQEP1A/COMP1OUT
GPIO21/EQEP1B/COMP2OUT
ADCINB2/COMP1B/AIO10
ADCINB1
VSSA/VREFLO
A. This figure shows the top view of the 56-pin RSH package. Shading denotes that the terminals are actually on the
bottom side of the package. See Section 9 for the 56-pin RSH mechanical drawing.
B. Pin 13: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one
another.
C. Pin 15: VREFLO is always connected to VSSA on the 56-pin RSH device.
Figure 4-1. 2803x 56-Pin RSH VQFN (Top View)
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Terminal Configuration and Functions
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SPRS584N –APRIL 2009–REVISED JUNE 2020
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GPIO11/EPWM6B/LINRXA/HRCAP2
GPIO5/EPWM3B/SPSIMOA/ECAP1
GPIO4/EPWM3A
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
GPIO28/SCIRXDA/SDAA/TZ2
GPIO9/EPWM5B/LINTXA/HRCAP1
TEST2
V
DDIO
GPIO10/EPWM6A/ADCSOCBO
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
GPIO2/EPWM2A
V
SS
GPIO29/SCITXDA/SCLA/TZ3
GPIO30/CANRXA
GPIO31/CANTXA
ADCINB7
GPIO1/EPWM1B/COMP1OUT
GPIO0/EPWM1A
V
DDIO
V
ADCINB6/COMP3B/AIO14
ADCINB4/COMP2B/AIO12
ADCINB3
SS
V
DD
V
REGENZ
GPIO34/COMP2OUT/COMP3OUT
GPIO20/EQEP1A/COMP1OUT
GPIO21/EQEP1B/COMP2OUT
GPIO24/ECAP1
ADCINB2/COMP1B/AIO10
ADCINB1
ADCINB0
V /V
SSA REFLO
A. Pin 15: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one
another.
B. Pin 17: VREFLO is always connected to VSSA on the 64-pin PAG device.
Figure 4-2. 2803x 64-Pin PAG TQFP (Top View)
12
Terminal Configuration and Functions
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SPRS584N –APRIL 2009–REVISED JUNE 2020
GPIO11/EPWM6B/LINRXA/HRCAP2
GPIO5/EPWM3B/SPISIMOA/ECAP1
GPIO4/EPWM3A
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GPIO28/SCIRXDA/SDAA/TZ2
GPIO9/EPWM5B/LINTXA/HRCAP1
TEST2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GPIO40/EPWM7A
GPIO26/HRCAP1/SPICLKB
GPIO10/EPWM6A/ADCSOCBO
GPIO3/EPWM2B/SPISOMIA/COMP2OUT
GPIO2/EPWM2A
V
DDIO
V
SS
GPIO29/SCITXDA/SCLA/TZ3
GPIO30/CANRXA
GPIO31/CANTXA
GPIO27/HRCAP2/SPISTEB
ADCINB7
GPIO1/EPWM1B/COMP1OUT
GPIO0/EPWM1A
V
DDIO
V
SS
V
ADCINB6/COMP3B/AIO14
ADCINB5
DD
REGENZ
V
GPIO34/COMP2OUT/COMP3OUT
GPIO15/TZ1/LINRXA/SPISTEB
GPIO13/TZ2/SPISOMIB
ADCINB4/COMP2B/AIO12
ADCINB3
ADCINB2/COMP1B/AIO10
ADCINB1
GPIO14/TZ3/LINTXA/SPICLKB
GPIO20/EQEP1A/COMP1OUT
GPIO21/EQEP1B/COMP2OUT
GPIO24/ECAP1/SPISIMOB
ADCINB0
V
REFLO
SSA
V
Figure 4-3. 2803x 80-Pin PN LQFP (Top View)
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4.2 Signal Descriptions
Table 4-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate
functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs
are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively
enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM
pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do
not have an internal pullup.
NOTE
When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and
GPIO38 pins could glitch during power up. This potential glitch will finish before the boot
mode pins are read and will not affect boot behavior. If glitching is unacceptable in an
application, 1.8 V could be supplied externally. Alternatively, adding a current-limiting resistor
(for example, 470 Ω) in series with these pins and any external driver could be considered to
limit the potential for degradation to the pin and/or external circuitry. There is no power-
sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V
transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V
transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin
during power up. To avoid this behavior, power the VDD pins before or with the VDDIO pins,
ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
Table 4-1. Signal Descriptions(1)
TERMINAL
I/O/Z
DESCRIPTION
PN
PAG
RSH
NAME
PIN NO. PIN NO. PIN NO.
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or
driven low, the device operates in its functional mode, and the test reset signals
are ignored. NOTE: TRST is an active high test pin and must be maintained low
at all times during normal device operation. An external pulldown resistor is
required on this pin. The value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the
application. (↓)
TRST
10
8
6
I
TCK
TMS
See GPIO38
See GPIO36
I
I
See GPIO38. JTAG test clock with internal pullup. (↑)
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising edge of TCK. (↑)
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into
the selected register (instruction or data) on a rising edge of TCK. (↑)
TDI
See GPIO35
See GPIO37
I
See GPIO37. JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) are shifted out of TDO on the falling edge of
TCK. (8 mA drive)
TDO
O/Z
FLASH
TEST2
38
30
27
I/O
Test Pin. Reserved for TI. Must be left unconnected.
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
14
Terminal Configuration and Functions
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SPRS584N –APRIL 2009–REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the
same frequency, one-half the frequency, or one-fourth the frequency of
SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register.
At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by
setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to
XCLKOUT for this signal to propogate to the pin.
XCLKOUT
See GPIO18
–
O/Z
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is
controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default
selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the
X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be
disabled through bit 14 in the CLKCTL register. If a crystal/resonator is used, the
XCLKIN path must be disabled by bit 13 in the CLKCTL register.
XCLKIN
See GPIO19 and GPIO38
I
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock
for normal device operation may need to incorporate some hooks to disable this
path during debug using the JTAG connector. This is to prevent contention with
the TCK signal, which is active during JTAG debug sessions. The zero-pin
internal oscillators may be used during this time to clock the device.
On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a
ceramic resonator must be connected across X1 and X2. In this case, the
XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not
used, it must be tied to GND. (I)
X1
X2
52
51
41
40
36
35
I
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be
connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
O
RESET
Device Reset (in) and Watchdog Reset (out). These devices have a built-in
power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or
brown-out condition, this pin is driven low by the device. An external circuit may
also drive this pin to assert a device reset. This pin is also driven low by the MCU
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low
for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value
from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is
placed between XRS and VSS for noise filtering, it should be 100 nF or smaller.
These values will allow the watchdog to properly drive the XRS pin to VOL within
512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the
source, a device reset causes the device to terminate execution. The program
counter points to the address contained at the location 0x3F FFC0. When reset is
deactivated, execution begins at the location designated by the program counter.
The output buffer of this pin is an open-drain device with an internal pullup. (↑) If
this pin is driven by an external device, it should be done using an open-drain
device.
XRS
9
7
5
I/O
ADC, COMPARATOR, ANALOG I/O
ADCINA7
ADCINA6
COMP3A
AIO6
11
12
13
14
15
16
9
7
8
I
ADC Group A, Channel 7 input
ADC Group A, Channel 6 input
Comparator Input 3A
I
10
–
I
I/O
Digital AIO 6
ADCINA5
ADCINA4
COMP2A
AIO4
–
I
ADC Group A, Channel 5 input
ADC Group A, Channel 4 input
Comparator Input 2A
I
11
12
13
9
I
I/O
Digital AIO 4
ADCINA3
ADCINA2
COMP1A
AIO2
10
11
I
I
ADC Group A, Channel 3 input
ADC Group A, Channel 2 input
Comparator Input 1A
I
I/O
Digital AIO 2
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
ADCINA1
17
14
12
I
ADC Group A, Channel 1 input
ADC Group A, Channel 0 input.
NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and
their use is mutually exclusive to one another.
ADCINA0
18
15
13
I
NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and
their use is mutually exclusive to one another.
ADC External Reference High – only used when in ADC external reference mode.
See Section 6.9.2.1, ADC.
NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and
their use is mutually exclusive to one another.
VREFHI
19
15
13
I
NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and
their use is mutually exclusive to one another.
ADCINB7
ADCINB6
COMP3B
AIO14
30
29
28
27
26
25
24
23
–
21
20
–
I
ADC Group B, Channel 7 input
ADC Group B, Channel 6 input
Comparator Input 3B
I
I
I/O
Digital AIO 14
ADCINB5
ADCINB4
COMP2B
AIO12
I
ADC Group B, Channel 5 input
ADC Group B, Channel 4 input
Comparator Input 2B
I
22
21
20
19
18
17
I
I/O
Digital AIO12
ADCINB3
ADCINB2
COMP1B
AIO10
I
ADC Group B, Channel 3 input
ADC Group B, Channel 2 input
Comparator Input 1B
I
I
I/O
I
Digital AIO 10
ADCINB1
ADCINB0
24
23
19
18
16
–
ADC Group B, Channel 1 input
ADC Group B, Channel 0 input
I
ADC External Reference Low.
VREFLO
22
17
15
I
NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the
56-pin RSH device.
CPU AND I/O POWER
VDDA
VSSA
20
21
16
17
14
15
Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
Analog Ground Pin.
NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the
56-pin RSH device.
7
5
3
CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF
capacitor between each VDD pin and ground. Higher value capacitors may be
used.
VDD
54
72
36
43
59
29
38
52
26
Digital I/O Buffers and Flash Memory Power Pin. Single supply source when
VREG is enabled. Place a decoupling capacitor on each pin. The exact value
should be determined by the system voltage regulation solution.
VDDIO
70
57
50
8
6
4
35
53
71
28
42
58
25
37
51
VSS
Digital Ground Pins
16
Terminal Configuration and Functions
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SPRS584N –APRIL 2009–REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
VOLTAGE REGULATOR CONTROL SIGNAL
Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable
VREG
VREGENZ
73
69
60
56
53
49
I
(2)
GPIO AND PERIPHERAL SIGNALS
GPIO0
EPWM1A
–
I/O/Z
O
General-purpose input/output 0
Enhanced PWM1 Output A and HRPWM channel
–
–
–
–
–
GPIO1
EPWM1B
–
I/O/Z
O
General-purpose input/output 1
Enhanced PWM1 Output B
–
68
67
66
63
62
50
49
43
55
54
53
51
50
39
38
35
48
47
46
45
44
34
33
–
COMP1OUT
GPIO2
EPWM2A
–
O
I/O/Z
O
Direct output of Comparator 1
General-purpose input/output 2
Enhanced PWM2 Output A and HRPWM channel
–
–
–
GPIO3
EPWM2B
SPISOMIA
COMP2OUT
GPIO4
EPWM3A
–
I/O/Z
O
General-purpose input/output 3
Enhanced PWM2 Output B
SPI-A slave out, master in
Direct output of Comparator 2
General-purpose input/output 4
Enhanced PWM3 output A and HRPWM channel
–
I/O
O
I/O/Z
O
–
–
GPIO5
EPWM3B
SPISIMOA
ECAP1
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
EPWM4B
SCIRXDA
–
I/O/Z
O
General-purpose input/output 5
Enhanced PWM3 output B
SPI-A slave in, master out
Enhanced Capture input/output 1
General-purpose input/output 6
Enhanced PWM4 output A and HRPWM channel
External ePWM sync pulse input
External ePWM sync pulse output
General-purpose input/output 7
Enhanced PWM4 output B
SCI-A receive data
I/O
I/O
I/O/Z
O
I
O
I/O/Z
O
I
–
GPIO8
EPWM5A
–
I/O/Z
O
General-purpose input/output 8
Enhanced PWM5 output A and HRPWM channel
–
ADCSOCAO
O
ADC start-of-conversion A
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.
For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the
GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the System
Control chapter in the TMS320F2803x Technical Reference Manual for details.
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
GPIO9
I/O/Z
O
General-purpose input/output 9
Enhanced PWM5 output B
LIN transmit A
EPWM5B
LINTXA
HRCAP1
GPIO10
EPWM6A
–
39
65
61
31
52
49
–
–
–
O
I
High-resolution input capture 1
General-purpose input/output 10
I/O/Z
O
Enhanced PWM6 output A and HRPWM channel
–
ADCSOCBO
GPIO11
EPWM6B
LINRXA
HRCAP2
GPIO12
TZ1
O
ADC start-of-conversion B
General-purpose input/output 11
Enhanced PWM6 output B
LIN receive A
I/O/Z
O
I
I
I/O/Z
I
High-resolution input capture 2
General-purpose input/output 12
Trip Zone input 1
47
37
32
SCITXDA
O
SCI-A transmit data
SPI-B slave in, master out.
NOTE: SPI-B is available only in the PN package.
SPISIMOB
I/O
GPIO13
TZ2
I/O/Z
I
General-purpose input/output 13
Trip Zone input 2
76
77
75
46
42
–
–
–
–
–
–
SPISOMIB
GPIO14
TZ3
I/O
I/O/Z
I
SPI-B slave out, master in
General-purpose input/output 14
Trip zone input 3
LINTXA
SPICLKB
GPIO15
TZ1
O
LIN transmit
I/O
I/O/Z
I
SPI-B clock input/output
General-purpose input/output 15
Trip zone input 1
–
–
LINRXA
SPISTEB
GPIO16
SPISIMOA
–
I
LIN receive
I/O
I/O/Z
I/O
SPI-B slave transmit enable input/output
General-purpose input/output 16
SPI-A slave in, master out
–
36
34
31
30
TZ2
I
Trip Zone input 2
GPIO17
SPISOMIA
–
I/O/Z
I/O
General-purpose input/output 17
SPI-A slave out, master in
–
TZ3
I
Trip zone input 3
18
Terminal Configuration and Functions
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SPRS584N –APRIL 2009–REVISED JUNE 2020
Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
GPIO18
SPICLKA
LINTXA
I/O/Z
I/O
O
General-purpose input/output 18
SPI-A clock input/output
LIN transmit
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,
one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is
controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV
to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to
propogate to the pin.
41
33
29
XCLKOUT
O/Z
GPIO19
I/O/Z
General-purpose input/output 19
External Oscillator Input. The path from this pin to the clock block is not gated by
the mux function of this pin. Care must be taken not to enable this path for
clocking if it is being used for the other periperhal functions
XCLKIN
55
44
39
SPISTEA
LINRXA
ECAP1
GPIO20
EQEP1A
–
I/O
SPI-A slave transmit enable input/output
LIN receive
I
I/O
I/O/Z
I
Enhanced Capture input/output 1
General-purpose input/output 20
Enhanced QEP1 input A
–
78
79
1
62
63
1
55
56
1
COMP1OUT
GPIO21
EQEP1B
–
O
I/O/Z
I
Direct output of Comparator 1
General-purpose input/output 21
Enhanced QEP1 input B
–
COMP2OUT
GPIO22
EQEP1S
–
O
Direct output of Comparator 2
General-purpose input/output 22
Enhanced QEP1 strobe
–
I/O/Z
I/O
LINTXA
GPIO23
EQEP1I
–
O
LIN transmit
I/O/Z
I/O
General-purpose input/output 23
Enhanced QEP1 index
–
4
4
2
–
LINRXA
GPIO24
I
LIN receive
I/O/Z
General-purpose input/output 24
See
GPIO5
and
ECAP1
I/O
Enhanced Capture input/output 1
80
44
64
GPIO19
–
–
SPI-B slave in, master out.
NOTE: SPI-B is available only in the PN and RSH packages.
SPISIMOB
I/O
GPIO25
I/O/Z
General-purpose input/output 25
–
–
–
–
–
–
SPISOMIB
I/O
SPI-B slave out, master in
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Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
GPIO26
I/O/Z
I
General-purpose input/output 26
High-resolution input capture 1
–
HRCAP1
–
37
31
40
34
33
32
2
–
–
–
–
SPICLKB
GPIO27
HRCAP2
–
I/O
I/O/Z
I
SPI-B clock input/output
General-purpose input/output 27
High-resolution input capture 2
–
SPISTEB
GPIO28
SCIRXDA
SDAA
I/O
SPI-B slave transmit enable input/output
General-purpose input/output 28
SCI receive data
I/O/Z
I
32
27
26
25
2
28
24
23
22
–
I/OD
I2C data open-drain bidirectional port
Trip zone input 2
TZ2
I
I/O/Z
O
GPIO29
SCITXDA
SCLA
General-purpose input/output 29
SCI transmit data
I/OD
I
I2C clock open-drain bidirectional port
Trip zone input 3
TZ3
GPIO30
CANRXA
–
I/O/Z
I
General-purpose input/output 30
CAN receive
–
–
–
GPIO31
CANTXA
–
I/O/Z
O
General-purpose input/output 31
CAN transmit
–
–
–
GPIO32
SDAA
I/O/Z
I/OD
I
General-purpose input/output 32
I2C data open-drain bidirectional port
Enhanced PWM external sync pulse input
ADC start-of-conversion A
General-Purpose Input/Output 33
I2C clock open-drain bidirectional port
Enhanced PWM external synch pulse output
ADC start-of-conversion B
General-Purpose Input/Output 34
Direct output of Comparator 2
–
EPWMSYNCI
ADCSOCAO
GPIO33
SCLA
O
I/O/Z
I/OD
O
3
3
–
EPWMSYNCO
ADCSOCBO
GPIO34
COMP2OUT
–
O
I/O/Z
O
74
61
54
COMP3OUT
GPIO35
O
Direct output of Comparator 3
General-Purpose Input/Output 35
I/O/Z
59
60
47
48
42
43
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK
TDI
I
I/O/Z
I
GPIO36
TMS
General-Purpose Input/Output 36
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
20
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions(1) (continued)
TERMINAL
PN
PIN NO. PIN NO. PIN NO.
I/O/Z
DESCRIPTION
PAG
RSH
NAME
GPIO37
I/O/Z
O/Z
General-Purpose Input/Output 37
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA
drive)
58
57
46
45
41
40
TDO
GPIO38
TCK
I/O/Z
I
General-Purpose Input/Output 38
JTAG test clock with internal pullup
External Oscillator Input. The path from this pin to the clock block is not gated by
the mux function of this pin. Care must be taken to not enable this path for
clocking if it is being used for the other functions.
XCLKIN
I
–
–
GPIO39
I/O/Z
General-Purpose Input/Output 39
–
–
56
64
48
5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GPIO40
I/O/Z
O
General-Purpose Input/Output 40
EPWM7A
Enhanced PWM7 output A and HRPWM channel
–
–
–
–
GPIO41
I/O/Z
O
General-Purpose Input/Output 41
EPWM7B
Enhanced PWM7 output B
–
–
–
–
GPIO42
I/O/Z
General-Purpose Input/Output 42
–
–
–
–
COMP1OUT
O
Direct output of Comparator 1
GPIO43
I/O/Z
General-Purpose Input/Output 43
–
–
6
–
–
COMP2OUT
O
Direct output of Comparator 2
GPIO44
I/O/Z
General-Purpose Input/Output 44
–
–
–
–
–
–
45
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5 Specifications
5.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
4.6
2.5
4.6
4.6
2.5
4.6
UNIT
VDDIO (I/O and Flash) with respect to VSS
Supply voltage
V
V
V
V
VDD with respect to VSS
Analog voltage
Input voltage
Output voltage
VDDA with respect to VSSA
VIN (3.3 V)
VIN (X1)
VO
Digital/analog input (per pin), IIK
–20
–20
–20
20
20
20
(3)
(VIN < VSS or VIN > VDDIO
)
Analog input (per pin), IIKANALOG
(VIN < VSSA or VIN > VDDA
Input clamp current
mA
)
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA
)
Output clamp current
Junction temperature(4)
Storage temperature(4)
IOK (VO < 0 or VO > VDDIO
)
–20
–40
–65
20
150
150
mA
°C
TJ
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. Do not operate in this condition continuously as VDDIO/VDDA voltage may internally rise and
impact other electrical specifications.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.
For additional information, see Semiconductor and IC Package Thermal Metrics; Calculating Useful Lifetimes of Embedded Processors;
and Calculating FIT for a Mission Profile.
5.2 ESD Ratings – Automotive
VALUE
UNIT
TMS320F2803x in 80-pin PN package
Human body model (HBM), per AEC Q100-002(1)
All pins
±2000
±500
All pins except corner
pins
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
Corner pins on 80-pin PN:
1, 20, 21, 40, 41, 60, 61,
80
±750
TMS320F2803x in 64-pin PAG package
Human body model (HBM), per AEC Q100-002(1)
All pins
±2000
±500
All pins except corner
pins
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
Corner pins on 64-pin
PAG: 1, 16, 17, 32, 33,
48, 49, 64
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
22
Specifications
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5.3 ESD Ratings – Commercial
TMS320F2803x in 56-pin RSH package
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101
or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO
2.97
3.3
3.63
V
Device supply voltage CPU, VDD (When internal VREG is
disabled and 1.8 V is supplied externally)
1.71
2.97
1.8
1.995
3.63
V
Supply ground, VSS
0
3.3
0
V
V
Analog supply voltage, VDDA
Analog ground, VSSA
V
Device clock frequency (system clock)
High-level input voltage, VIH (3.3 V)
Low-level input voltage, VIL (3.3 V)
2
2
60
MHz
V
VDDIO + 0.3
VSS – 0.3
0.8
–4
–8
4
V
All GPIO/AIO pins
Group 2(1)
mA
mA
mA
mA
High-level output source current, VOH = VOH(MIN) , IOH
Low-level output sink current, VOL = VOL(MAX), IOL
All GPIO/AIO pins
Group 2(1)
8
T version
–40
–40
105
125
S version
Ambient temperature, TA
Junction temperature, TJ
°C
°C
Q version
(AEC Q100 qualification)
–40
–40
125
150
(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37
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5.5 Power Consumption Summary
Table 5-1. TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
VREG ENABLED
VREG DISABLED
(1)
(2)
(1)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP(3)
IDDA
TYP(3)
IDD
IDDIO
TYP(3)
IDDA
TYP(3)
MAX
MAX
TYP(3)
MAX
MAX
MAX
The following peripheral clocks
are enabled:
•
•
•
•
•
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6/7
eCAP1
eQEP1
eCAN
LIN
CLA
HRPWM
SCI-A
Operational
(Flash)
114 mA(6) 135 mA(6) 14 mA
18 mA 101 mA(6) 120 mA(6) 14 mA
18 mA 14 mA
18 mA
SPI-A/B
ADC
I2C
COMP1/2/3
CPU-TIMER0/1/2
All PWM pins are toggled at
60 kHz.
All I/O pins are left
unconnected.(4)(5)
Code is running out of flash
with 2 wait states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
All peripheral clocks are turned
off.
IDLE
13 mA
23 mA
9 mA
10 μA
15 μA
13 mA
24 mA
7 mA
120 μA 400 μA
10 μA
15 μA
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
4 mA
10 μA
10 μA
15 μA
15 μA
4 mA
120 μA 400 μA
24 μA
10 μA
10 μA
15 μA
15 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(7)
46 μA
30 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of SPI-A/B, SCI-A, eCAN, LIN, and I2C ports.
The hardware multiplier is exercised.
Watchdog is reset.
ADC is performing continuous conversion.
COMP1/2 are continuously switching voltages.
GPIO17 is toggled.
(5) CLA is continuously performing polynomial calculations.
(6) For F2803x devices that do not have CLA, subtract the IDD current number for CLA (see Table 5-2) from the IDD (VREG disabled)/IDDIO
(VREG enabled) current numbers shown in Table 5-1 for operational mode.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.
24
Specifications
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5.5.1 Reducing Current Consumption
The 2803x devices incorporate a method to reduce the device current consumption. Because each
peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be
achieved by turning off the clock to any peripheral module that is not used in a given application.
Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current
consumption even further. Table 5-2 indicates the typical reduction in current consumption achieved by
turning off the clocks.
Table 5-2. Typical Current Consumption by Various
Peripherals (at 60 MHz)(1)
PERIPHERAL
MODULE(2)
IDD CURRENT
REDUCTION (mA)
ADC
2(3)
I2C
3
ePWM
2
eCAP
2
eQEP
2
SCI
2
SPI
COMP/DAC
HRPWM
2
1
3
HRCAP
3
CPU-TIMER
Internal zero-pin oscillator
CAN
1
0.5
2.5
1.5
20
LIN
CLA
(1) All peripheral clocks (except CPU Timer clock) are disabled upon
reset. Writing to/reading from peripheral registers is possible only
after the peripheral clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for one
ePWM module.
(3) This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA) as well.
NOTE
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline IDD current (current when the core is executing a dummy loop with no
peripherals enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the
current-drawn by the peripherals (enabled by that application) must be added to the baseline
IDD current.
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Following are other methods to reduce power consumption further:
•
The flash module may be powered down if code is run off SARAM. This results in a current reduction
of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
•
•
Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
To realize the lowest VDDA current consumption in a low-power mode, see the respective analog
chapter of the TMS320F2803x Technical Reference Manual to ensure each module is powered down
as well.
5.5.2 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
140
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
SYSCLKOUT (MHz)
IDDIO IDDA
Figure 5-1. Typical Operational Current Versus Frequency (F2803x)
26
Specifications
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Operational Power vs Frequency
500
450
400
350
300
250
200
0
10
20
30
40
50
60
70
SYSCLKOUT (MHz)
Figure 5-2. Typical Operational Power Versus Frequency (F2803x)
Typical CLA operational current vs SYSCLKOUT
25
20
15
10
5
0
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
Figure 5-3. Typical CLA Operational Current Versus SYSCLKOUT
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5.6 Electrical Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOH MAX
IOH = 50 μA
VOH
VOL
High-level output voltage
Low-level output voltage
V
VDDIO – 0.2
IOL = IOL MAX
0.4
–205
–375
V
All GPIO
XRS pin
–80
–140
–300
Pin with pullup
VDDIO = 3.3 V, VIN = 0 V
enabled
Input current
(low level)
–230
IIL
μA
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
±2
±2
80
Pin with pullup
enabled
Input current
(high level)
IIH
μA
Pin with pulldown
enabled
28
50
Output current, pullup or
pulldown disabled
IOZ
CI
±2 μA
Input capacitance
2
2.78
35
pF
VDDIO BOR trip point
VDDIO BOR hysteresis
Falling VDDIO
2.50
400
2.96
V
mV
Supervisor reset release delay
time
Time after BOR/POR/OVR event is removed to XRS
release
800 μs
VREG VDD output
Internal VREG on
1.9
V
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.
28
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5.7 Thermal Resistance Characteristics
5.7.1 PN Package
°C/W(1)
14.2
21.9
49.9
38.3
36.7
34.4
0.8
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
N/A
N/A
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
1.18
1.34
1.62
21.6
20.7
20.5
20.1
150
250
500
0
PsiJT
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
5.7.2 PAG Package
°C/W(1)
7.6
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
N/A
N/A
0
Junction-to-board thermal resistance
Junction-to-free air thermal resistance
31.3
56.5
44.7
42.9
40.3
0.15
0.42
0.51
0.67
31.1
29.7
29.2
28.4
150
250
500
0
RΘJA
(High k PCB)
150
250
500
0
PsiJT
Junction-to-package top
Junction-to-board
150
250
500
PsiJB
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
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5.7.3 RSH Package
°C/W(1)
14.7
9.2
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
N/A
N/A
0
34.8
23.6
22.3
20.5
0.24
0.36
0.43
0.56
9.2
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
150
250
500
0
PsiJT
8.8
150
250
500
PsiJB
Junction-to-board
8.9
8.8
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
30
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5.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary.
Systems that exceed the recommended maximum power dissipation in the end product may require
additional thermal enhancements. Ambient temperature (TA) varies with the end application and product
design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the
ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be
measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of
the package top-side surface. The thermal application report Semiconductor and IC Package Thermal
Metrics helps to understand the thermal metrics and definitions.
5.9 JTAG Debug Probe Connection Without Signal Buffering for the MCU
Figure 5-4 shows the connection between the MCU and JTAG header for a single-processor configuration.
If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals
must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 5-4 shows
the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 4.2, Signal
Descriptions.
6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
PD
4
6
8
TRST
TMS
TDI
GND
1
GND
GND
GND
GND
3
TDI
7
10
12
TDO
TCK
TDO
11
9
TCK
TCK_RET
MCU
JTAG Header
A. See Figure 6-44 for JTAG/GPIO multiplexing.
Figure 5-4. JTAG Debug Probe Connection Without Signal Buffering for the MCU
NOTE
The 2803x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header
onboard, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ
(typical) resistor.
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5.10 Parameter Information
5.10.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
access time
H
L
High
Low
cycle time (period)
delay time
V
Valid
Unknown, changing, or don't care
level
f
fall time
X
Z
h
r
hold time
High impedance
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
5.10.2 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that
all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual
cycles. For actual cycle examples, see the appropriate cycle description section of this document.
5.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
W
3.5 nH
Output
Under
Test
42
Transmission Line
(A)
Z0 = 50 W
Device Pin(B)
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.
Figure 5-5. 3.3-V Test Load Circuit
32
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5.12 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset
or to prevent the I/Os from glitching during power up/down (GPIO19, GPIO34–38 do not have glitch-free
I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for
analog pins, this value is 0.7 V above VDDA) before powering up the device. Voltages applied to pins on an
unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
t
w(RSL1)
XRS(D)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
User-code execution phase
User-code dependent
t
d(EX)
(C)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Peripheral/GPIO function
Boot-ROM execution starts
(E)
Based on boot code
GPIO pins as input (state depends on internal PU/PD)
I/O Pins
User-code dependent
A. Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a
reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during
this phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not
be visible at the pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in
debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT
will be based on user environment and could be with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.
E. The internal pullup/pulldown will take effect when BOR is driven high.
Figure 5-6. Power-on Reset
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Table 5-3. Reset (XRS) Timing Requirements
MIN
1000tc(SCO)
32tc(OSCCLK)
MAX
MAX
UNIT
cycles
cycles
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRS low on warm reset
Table 5-4. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
tw(RSL1)
Pulse duration, XRS driven by device
600
μs
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
512tc(OSCCLK)
cycles
td(EX)
Delay time, address/data valid after XRS high
Start-up time, internal zero-pin oscillator
On-chip crystal-oscillator start-up time
32tc(OSCCLK)
cycles
μs
tINTOSCST
3
(1)
tOSCST
1
10
ms
(1) Dependent on crystal/resonator and board design.
INTOSC1
X1/X2
XCLKOUT
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
User-Code Execution
Control
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The
SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 5-7. Warm Reset
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Figure 5-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =
0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR
register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the
PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
(Current CPU
Frequency)
(Changed CPU frequency)
Figure 5-8. Example of Effect of Writing Into PLLCR Register
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5.13 Clock Specifications
5.13.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2803x MCUs. Table 5-5 lists the cycle times of various clocks.
Table 5-5. 2803x Clock Table and Nomenclature (60-MHz Devices)
MIN
16.67
2
NOM
MAX UNIT
tc(SCO), Cycle time
Frequency
500
60
ns
MHz
ns
SYSCLKOUT
LSPCLK(1)
ADC clock
tc(LCO), Cycle time
Frequency
16.67
66.67(2)
15(2)
60
60
MHz
ns
tc(ADCCLK), Cycle time
Frequency
16.67
MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This is the default reset value if SYSCLKOUT = 60 MHz.
Table 5-6. Device Clocking Requirements/Characteristics
MIN
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
5
200
20
ns
MHz
ns
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
tc(CI), Cycle time (C8)
Frequency
33.3
5
200
30
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
MHz
ns
tc(CI), Cycle time (C8)
Frequency
33.33
4
250
30
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
MHz
Limp mode SYSCLKOUT
(with /2 enabled)
Frequency range
1 to 5
MHz
tc(XCO), Cycle time (C1)
66.67
0.5
2000
15
ns
MHz
ms
XCLKOUT
Frequency
tp
PLL lock time(1)
1
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
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Table 5-7. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
PARAMETER
MIN
TYP
10.000
10.000
55
MAX
UNIT
MHz
MHz
kHz
Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1)(2)
Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1)(2)
Step size (coarse trim)
Frequency
Frequency
Step size (fine trim)
14
kHz
Temperature drift(3)
Voltage (VDD) drift(3)
3.03
4.85 kHz/°C
Hz/mV
175
(1) Oscillator frequency will vary over temperature, see Figure 5-9. To compensate for oscillator temperature drift, see the Oscillator
Compensation Guide and C2000Ware.
(2) Frequency range ensured only when VREG is enabled, VREGENZ = VSS
.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
•
•
Increase in temperature will cause the output frequency to increase per the temperature coefficient.
Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient.
Zero-Pin Oscillator Frequency Movement With Temperature
10.6
10.5
10.4
10.3
10.2
10.1
10
9.9
9.8
9.7
9.6
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
Typical
Max
Temperature (°C)
Figure 5-9. Zero-Pin Oscillator Frequency Movement With Temperature
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5.13.2 Clock Requirements and Characteristics
Table 5-8. XCLKIN Timing Requirements – PLL Enabled
NO.
C9
MIN
MAX
6
UNIT
ns
tf(CI)
Fall time, XCLKIN
C10
C11
C12
tr(CI)
Rise time, XCLKIN
6
ns
tw(CIL)
tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
45%
55%
55%
Table 5-9. XCLKIN Timing Requirements – PLL Disabled
NO.
MIN
MAX
UNIT
Up to 20 MHz
6
2
6
2
C9
tf(Cl)
Fall time, XCLKIN
20 MHz to 30 MHz
ns
Up to 20 MHz
C10
tr(CI)
Rise time, XCLKIN
20 MHz to 30 MHz
ns
Pulse duration, XCLKIN low as a percentage of
tc(OSCCLK)
C11
C12
tw(CIL)
tw(CIH)
45%
45%
55%
55%
Pulse duration, XCLKIN high as a percentage of
tc(OSCCLK)
The possible configuration modes are shown in Table 6-17.
Table 5-10. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)
over recommended operating conditions (unless otherwise noted)
NO.
C3
C4
C5
C6
PARAMETER
MIN
MAX
5
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
Rise time, XCLKOUT
tr(XCO)
5
ns
tw(XCOL)
tw(XCOH)
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
H – 2
H – 2
H + 2
H + 2
ns
ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is
intended to illustrate the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 5-10. Clock Timing
38
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5.14 Flash Timing
Table 5-11. Flash/OTP Endurance for T Temperature Material(1)
ERASE/PROGRAM
TEMPERATURE
MIN
TYP
MAX
UNIT
Nf
Flash endurance for the array (write/erase cycles)
OTP endurance for the array (write cycles)
0°C to 105°C (ambient)
0°C to 30°C (ambient)
20000
50000
cycles
write
NOTP
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-12. Flash/OTP Endurance for S Temperature Material(1)
ERASE/PROGRAM
MIN
TYP
MAX
UNIT
TEMPERATURE
0°C to 125°C (ambient)
0°C to 30°C (ambient)
Nf
Flash endurance for the array (write/erase cycles)
OTP endurance for the array (write cycles)
20000
50000
cycles
write
NOTP
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-13. Flash/OTP Endurance for Q Temperature Material(1)
ERASE/PROGRAM
TEMPERATURE
MIN
TYP
MAX
UNIT
Nf
Flash endurance for the array (write/erase cycles)
OTP endurance for the array (write cycles)
–40°C to 125°C (ambient)
–40°C to 30°C (ambient)
20000
50000
cycles
write
NOTP
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 5-14. Flash Parameters at 60-MHz SYSCLKOUT
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
Program
Time(1)
8K Sector
4K Sector
16-Bit Word
8K Sector
4K Sector
250 2000(2)
125 2000(2)
50
ms
ms
μs
s
Erase Time(3)
2
2
12(2)
12(2)
s
(4)
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VREG disabled
VREG enabled
80
mA
mA
(4)
IDDIOP
60
(4)
IDDIOP
120
(1) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the required
code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine but does
not include the time to transfer the following into RAM:
•
•
•
the code that uses flash API to program the flash
the Flash API itself
Flash data to be programmed
(2) Maximum flash parameter mentioned are for the first 100 program and erase cycles.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.
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Table 5-15. Flash/OTP Access Timing
PARAMETER
MIN
40
MAX UNIT
ta(fp)
Paged Flash access time
Random Flash access time
OTP access time
ns
ns
ns
ta(fr)
40
ta(OTP)
60
Table 5-16. Flash Data Retention Duration
PARAMETER
Data retention duration
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX UNIT
tretention
years
Table 5-17. Minimum Required Flash/OTP Wait States at Different Frequencies
SYSCLKOUT
SYSCLKOUT
(ns)
PAGE
RANDOM
OTP
WAIT STATE
(MHz)
WAIT STATE(1)
WAIT STATE(1)
60
16.67
18.18
20
2
2
1
1
1
1
1
0
2
2
1
1
1
1
1
1
3
3
2
2
2
2
1
1
55
50
45
22.22
25
40
35
28.57
33.33
40
30
25
(1) Random wait state must be ≥ 1.
The equations to compute the Flash page wait state and random wait state in Table 5-17 are as follows:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(f ·p)
Flash Page Wait State =
-1 round up to the next highest integer
ú
tc(SCO)
ê
ú
û
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(f ×r)
Flash Random Wait State =
-1 round up to the next highest integer, or 1, whichever is larger
ú
tc(SCO)
ê
ú
û
The equation to compute the OTP wait state in Table 5-17 is as follows:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(OTP)
OTP Wait State =
-1 round up to the next highest integer, or 1, whichever is larger
ú
tc(SCO)
ê
ú
û
40
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6 Detailed Description
6.1 Overview
6.1.1 CPU
The 2803x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-
based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level
language, but also enabling development of math algorithms using C/C++. The device is as efficient at
MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This
efficiency removes the need for a second processor in many systems. The 32 × 32-bit MAC 64-bit
processing capabilities enable the controller to handle higher numerical resolution problems efficiently.
Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-
deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high
speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
6.1.2 Control Law Accelerator (CLA)
The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the
capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its
own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be
specified. Each task is started by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0.
The CLA executes one task at a time to completion. When a task completes the main CPU is notified by
an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA
can directly access the ADC Result registers and the ePWM+HRPWM registers. Dedicated message
RAMs provide a method to pass additional data between the main CPU and the CLA.
6.1.3 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple buses are used to move data between the memories and
peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and
data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and
write buses consist of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single
cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x
to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and
memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus
accesses can be summarized as follows:
Highest:
Data Writes
(Simultaneous data and program writes cannot occur on the
memory bus.)
Program Writes
(Simultaneous data and program writes cannot occur on the
memory bus.)
Data Reads
Program Reads
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur on the
memory bus.)
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6.1.4 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various buses that make up the processor Memory Bus into a single bus consisting of 16 address
lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are
supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version
supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports CLA access
and both 16- and 32-bit accesses (called peripheral frame 3).
6.1.5 Real-Time JTAG and Analysis
(1)
The devices implement the standard IEEE 1149.1 JTAG
interface for in-circuit based debug.
Additionally, the devices support real-time mode of operation allowing modification of the contents of
memory, peripheral, and register locations while the processor is running and executing code and
servicing interrupts. The user can also single step through non-time-critical code while enabling time-
critical interrupts to be serviced without interference. The device implements the real-time mode in
hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software
monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or
data/address watch-points and generating various user-selectable break events when a match occurs.
6.1.6 Flash
The F28035/34 devices contain 64K × 16 of embedded flash memory, segregated into eight 8K × 16
sectors. The F28033/32/31 devices contain 32K × 16 of embedded flash memory, segregated into eight
4K × 16 sectors. The F28030 device contains 16K × 16 of embedded flash memory, segregated into four
4K × 16 sectors. All devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to
0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other
sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash
algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash
module to achieve higher performance. The flash/OTP is mapped to both program and data space;
therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 to 0x3F 7FF5
are reserved for data variables and should not contain program code.
NOTE
The Flash and OTP wait states can be configured by the application. This allows applications
running at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the
Flash options register. With this mode enabled, effective performance of linear code
execution will be much faster than the raw performance indicated by the wait-state
configuration alone. The exact performance gain when using the Flash pipeline mode is
application-dependent.
For more information on the Flash options, Flash wait state, and OTP wait-state registers,
see the System Control chapter in the TMS320F2803x Technical Reference Manual.
6.1.7 M0, M1 SARAMs
All devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a
unified memory map to the programmer. This makes for easier programming in high-level languages.
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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6.1.8 L0 SARAM, and L1, L2, and L3 DPSARAMs
The device contains up to 8K × 16 of single-access RAM. To ascertain the exact size for a given device,
see the device-specific memory map figures in Section 6.2. This block is mapped to both program and
data space. Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2
are both 1K in size and are shared with the CLA which can ultilize these blocks for its data space. Block
L3 is 4K (2K on the 28031 device) in size and is shared with the CLA which can ultilize this block for its
program space. DPSARAM refers to the dual-port configuration of these blocks.
6.1.9 Boot ROM
The Boot ROM is factory-programmed with bootloader software. The Boot ROM uses the boot-mode-
select GPIO pins to determine what boot mode to use upon power up. The user can select to boot
normally to application code, to download new software from an external connection, or to select boot
software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables,
such as SIN/COS waveforms, for use in math-related algorithms. The boot-ROM content, and hence the
checksum value, may vary for different silicon revisions. For details, see the Boot ROM chapter in the
TMS320F2803x Technical Reference Manual.
Table 6-1. Boot Mode Selection
GPIO34/COMP2OUT/
MODE
GPIO37/TDO
TRST
MODE
COMP3OUT
3
2
1
1
0
0
x
1
0
1
0
x
0
0
0
0
1
GetMode
Wait (see Section 6.1.10 for description)
1
SCI
0
Parallel IO
Emulation Boot
EMU
6.1.9.1 Emulation Boot
When the JTAG debug probe is connected, the GPIO37/TDO pin cannot be used for boot mode selection.
In this case, the boot ROM detects that a JTAG debug probe is connected and uses the contents of two
reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either
location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation
boot.
6.1.9.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another
boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then
boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.
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6.1.9.3 Peripheral Pins Used by the Bootloader
Table 6-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table
to see if these conflict with any of the peripherals you would like to use in your application.
Table 6-2. Peripheral Bootload Pins
BOOTLOADER
PERIPHERAL LOADER PINS
SCIRXDA (GPIO28)
SCI
SCITXDA (GPIO29)
Parallel Boot
SPI
Data (GPIO31,30,5:0)
28x Control (AIO6)
Host Control (AIO12)
SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C
SDAA (GPIO32)
SCLA (GPIO33)
CAN
CANRXA (GPIO30)
CANTXA (GPIO31)
6.1.10 Security
The devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the
flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.
The security feature prevents unauthorized users from examining the memory contents through the JTAG
port, executing code from external memory or trying to boot-load some undesirable software that would
export the secure memory contents. To enable access to the secure blocks, the user must write the
correct 128-bit KEY value that matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent
unauthorized users from stepping through secure code. Any code or data access to CSM secure memory
while the JTAG debug probe is connected will trip the ECSL and break the emulation connection. To allow
emulation of secure code, while maintaining the CSM protection against secure memory reads, the user
must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in
the lower 64 bits of the password locations within the flash. Dummy reads of all 128 bits of the password
in the flash must still be performed. If the lower 64 bits of the password locations are all ones
(unprogrammed), then the KEY value does not need to match.
When initially debugging a device with the password locations in flash programmed (that is, secured), the
CPU will start running and may execute an instruction that performs an access to a protected ECSL area.
If this happens, the ECSL will trip and cause the JTAG debug probe connection to be cut.
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The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow a
JTAG debug probe to be connected without tripping security. These devices do not support a hardware
wait-in-reset mode.
NOTE
•
•
When the code-security passwords are programmed, all addresses from 0x3F7F80 to
0x3F7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
If the code security feature is not used, addresses 0x3F7F80 to 0x3F7FEF may be used
for code or data. Addresses 0x3F7FF0 to 0x3F7FF5 are reserved for data and should not
contain program code.
The 128-bit password (at 0x3F 7FF8 to 0x3F 7FFF) must not be programmed to zeros.
Doing so would permanently lock the device.
Disclaimer
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY
(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN
ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO
TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR
THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED
MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT
AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS
CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY
OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,
BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR
INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.
6.1.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The
PIE block can support up to 96 peripheral interrupts. On the F2803x, 56 of the possible 96 interrupts are
used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of
12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a
dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU
on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.
Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in
hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.
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6.1.12 External Interrupts (XINT1–XINT3)
The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be
selected for negative, positive, or both negative and positive edge triggering and can also be
enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero
when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.
There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept
inputs from GPIO0–GPIO31 pins.
6.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a
crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling
ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating
frequency if lower power operation is desired. Refer to Section 5, Electrical Specifications, for timing
details. The PLL block can be set in bypass mode.
6.1.14 Watchdog
Each device contains two watchdogs: CPU watchdog that monitors the core and NMI watchdog that is a
missing clock-detect circuit. The user software must regularly reset the CPU watchdog counter within a
certain time frame; otherwise, the CPU watchdog generates a reset to the processor. The CPU watchdog
can be disabled if necessary. The NMI watchdog engages only in case of a clock failure and can either
generate an interrupt or a device reset.
6.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled
relative to the CPU clock.
6.1.16 Low-power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and
only those peripherals that must function during IDLE are left operating. An enabled
interrupt from an active peripheral or the watchdog timer will wake the processor from
IDLE mode.
STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL
functional. An external interrupt event will wake the processor and the peripherals.
Execution begins on the next valid cycle after detection of the interrupt event
HALT:
This mode basically shuts down the device and places it in the lowest possible power
consumption mode. If the internal zero-pin oscillators are used as the clock source,
the HALT mode turns them off, by default. To keep these oscillators from shutting
down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin
oscillators may thus be used to clock the CPU watchdog in this mode. If the on-chip
crystal oscillator is used as the clock source, it is shut down in this mode. A reset or
an external signal (through a GPIO pin) or the CPU watchdog can wake the device
from this mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put
the device into HALT or STANDBY.
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6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0: PIE:
Flash:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Waitstate Registers
Timers:
CSM:
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC:
ADC Result Registers
CLA
Control Law Accelrator Registers and Message RAMs
GPIO MUX Configuration and Control Registers
Enhanced Control Area Network Configuration and Control Registers
Local Interconnect Network Configuration and Control Registers
Enhanced Capture Module and Registers
PF1: GPIO:
eCAN:
LIN:
eCAP:
eQEP:
Enhanced Quadrature Encoder Pulse Module and Registers
High-Resolution Capture Module and Registers
System Control Registers
HRCAP:
PF2: SYS:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Configuration Registers
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
SPI:
ADC:
I2C:
XINT:
PF3: ePWM:
HRPWM:
Enhanced Pulse Width Modulator Module and Registers
High-Resolution Pulse-Width Modulator Registers
Comparators: Comparator Modules
6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
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6.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to
INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
SYSCLKOUT (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTOSC2)
External clock source
6.1.20 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the
HRPWM high resolution duty and period features. The type 1 module found on
2803x devices also supports increased dead-band resolution, enhanced SOC and
interrupt generation, and advanced triggering including trip functions based on
comparator outputs.
eCAP:
eQEP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer. This peripheral has a watchdog timer to detect motor stall and input error
detection logic to identify simultaneous edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter. It has up to 16 single-ended channels pinned
out, depending on the device. It contains two sample-and-hold units for
simultaneous sampling.
Comparator: Each comparator block consists of one analog comparator along with an internal
10-bit reference for supplying one input of the comparator.
HRCAP:
The high-resolution capture peripheral operates in normal capture mode through a
16-bit counter clocked off of the HCCAPCLK or in high-resolution capture mode by
utilizing built-in calibration logic in conjunction with a TI-supplied calibration library.
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6.1.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream
of programmed length (1 to 16 bits) to be shifted into and out of the device at a
programmable bit-transfer rate. Normally, the SPI is used for communications
between the MCU and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multidevice communications are
supported by the master/slave operation of the SPI. The SPI contains a 4-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
I2C:
The serial communications interface is a two-wire asynchronous serial port,
commonly known as UART. The SCI contains a 4-level receive and transmit FIFO
for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between an MCU
and other devices compliant with Philips Semiconductors Inter-IC bus ( I2C-bus®)
specification version 2.1 and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit/receive up to 8-bit data
to/from the MCU through the I2C module. The I2C contains a 4-level receive and
transmit FIFO for reducing interrupt servicing overhead.
eCAN:
LIN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time
stamping of messages, and is compliant with ISO11898-1 (CAN 2.0B).
LIN 1.3 or 2.0 compatible peripheral. Can also be configured as additional SCI
port
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6.2 Memory Maps
In Figure 6-1 through Figure 6-4, the following apply:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
•
Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
•
•
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Locations 0x3D7C80 to 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 1400
Peripheral Frame 0
CLA Registers
0x00 1480
0x00 1500
0x00 1580
0x00 2000
0x00 6000
CLA-to-CPU Message RAM
CPU-to-CLA Message RAM
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
L1 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Prog RAM)
0x00 A000
0x3D 7800
0x3D 7C00
0x3D 7C80
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
Calibration Data
Get_mode function
Reserved
0x3D 7CC0
0x3D 7CE0
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
0x3E 8000
Reserved
FLASH
(64K ´ 16, 8 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
0x3F 8800
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. CLA-specific registers and RAM apply to the 28035 device only.
B. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 6-1. 28034/28035 Memory Map
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 1400
0x00 1480
0x00 1500
0x00 1580
0x00 2000
0x00 6000
Peripheral Frame 0
CLA Registers
CLA-to-CPU Message RAM
CPU-to-CLA Message RAM
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
L1 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Prog RAM)
0x00 A000
0x3D 7800
0x3D 7C00
0x3D 7C80
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
Calibration Data
Get_mode function
Reserved
0x3D 7CC0
0x3D 7CE0
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
0x3F 0000
Reserved
FLASH
(32K ´ 16, 8 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
0x3F 8800
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. CLA-specific registers and RAM apply to the 28033 device only.
B. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 6-2. 28032/28033 Memory Map
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
L1 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
L3 DPSARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Prog RAM)
0x00 9800
0x3D 7800
0x3D 7C00
0x3D 7C80
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
Calibration Data
Get_mode function
Reserved
0x3D 7CC0
0x3D 7CE0
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
0x3F 0000
Reserved
FLASH
(32K ´ 16, 8 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
0x3F 8800
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 6-3. 28031 Memory Map
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
L1 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)
Reserved
0x00 A000
0x3D 7800
0x3D 7C00
0x3D 7C80
Reserved
User OTP (1K ´ 16, Secure Zone + ECSL)
Reserved
Calibration Data
Get_mode function
Reserved
0x3D 7CC0
0x3D 7CE0
0x3D 7E80
PARTID
Calibration Data
0x3D 7EB0
0x3F 4000
Reserved
FLASH
(16K ´ 16, 4 Sectors, Secure Zone + ECSL)
0x3F 7FF8
0x3F 8000
128-Bit Password
L0 SARAM (2K ´ 16)
(0-Wait, Secure Zone + ECSL, Dual-Mapped)
0x3F 8800
0x3F E000
0x3F FFC0
Reserved
Boot ROM (8K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 6-4. 28030 Memory Map
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Table 6-3. Addresses of Flash Sectors in F28034/28035
ADDRESS RANGE
0x3E 8000 to 0x3E 9FFF
0x3E A000 to 0x3E BFFF
0x3E C000 to 0x3E DFFF
0x3E E000 to 0x3E FFFF
0x3F 0000 to 0x3F 1FFF
0x3F 2000 to 0x3F 3FFF
0x3F 4000 to 0x3F 5FFF
0x3F 6000 to 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector H (8K × 16)
Sector G (8K × 16)
Sector F (8K × 16)
Sector E (8K × 16)
Sector D (8K × 16)
Sector C (8K × 16)
Sector B (8K × 16)
Sector A (8K × 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 to 0x3F 7FF5
0x3F 7FF6 to 0x3F 7FF7
0x3F 7FF8 to 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Table 6-4. Addresses of Flash Sectors in F28031/28032/28033
ADDRESS RANGE
PROGRAM AND DATA SPACE
Sector H (4K × 16)
Sector G (4K × 16)
Sector F (4K × 16)
Sector E (4K × 16)
Sector D (4K × 16)
Sector C (4K × 16)
Sector B (4K × 16)
Sector A (4K × 16)
0x3F 0000 to 0x3F 0FFF
0x3F 1000 to 0x3F 1FFF
0x3F 2000 to 0x3F 2FFF
0x3F 3000 to 0x3F 3FFF
0x3F 4000 to 0x3F 4FFF
0x3F 5000 to 0x3F 5FFF
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7F7F
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 to 0x3F 7FF5
0x3F 7FF6 to 0x3F 7FF7
0x3F 7FF8 to 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Table 6-5. Addresses of Flash Sectors in F28030
ADDRESS RANGE
0x3F 4000 to 0x3F 4FFF
0x3F 5000 to 0x3F 5FFF
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (4K × 16)
Sector C (4K × 16)
Sector B (4K × 16)
Sector A (4K × 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 to 0x3F 7FF5
0x3F 7FF6 to 0x3F 7FF7
0x3F 7FF8 to 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
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NOTE
•
•
When the code-security passwords are programmed, all addresses from 0x3F 7F80 to
0x3F 7FF5 cannot be used as program code or data. These locations must be
programmed to 0x0000.
If the code security feature is not used, addresses 0x3F 7F80 to 0x3F 7FEF may be
used for code or data. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and
should not contain program code.
Table 6-6 shows how to handle these memory locations.
Table 6-6. Impact of Using the Code Security Module
FLASH
ADDRESS
CODE SECURITY ENABLED
CODE SECURITY DISABLED
0x3F 7F80 to 0x3F 7FEF
0x3F 7FF0 to 0x3F 7FF5
Application code and data
Reserved for data only
Fill with 0x0000
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these
blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to
these blocks happen as written. Because of the pipeline, a write immediately followed by a read to
different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause
problems in certain peripheral applications where the user expected the write to occur first (as written).
The CPU supports a block protection mode where a region of memory can be protected so that operations
occur as written (the penalty is extra cycles are added to align the operations). This mode is
programmable and by default, it protects the selected zones.
The wait states for the various spaces in the memory map area are listed in Table 6-7.
Table 6-7. Wait States
AREA
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
WAIT STATES (CPU)
0-wait
COMMENTS
Fixed
0-wait
0-wait (writes)
2-wait (reads)
Cycles can be extended by peripheral generated ready.
Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2
Peripheral Frame 3
0-wait (writes)
2-wait (reads)
Fixed. Cycles cannot be extended by the peripheral.
0-wait (writes)
Assumes no conflict between CPU and CLA.
Cycles can be extended by peripheral-generated ready.
Assumes no CPU conflicts
2-wait (reads)
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
OTP
0-wait data and program
0-wait data and program
0-wait data and program
0-wait data and program
Programmable
Assumes no CPU conflicts
Assumes no CPU conflicts
Assumes no CPU conflicts
Programmed through the Flash registers.
1-wait is minimum number of wait states allowed.
Programmed through the Flash registers.
1-wait minimum
FLASH
Programmable
0-wait Paged min
1-wait Random min
Random ≥ Paged
FLASH Password
Boot-ROM
16-wait fixed
0-wait
Wait states of password locations are fixed.
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6.3 Register Maps
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.
See Table 6-8.
Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See
Table 6-9.
Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See
Table 6-10.
Peripheral Frame 3: These are peripherals that are mapped to the 32-bit peripheral bus and are
accessible by the CLA. See Table 6-11.
Table 6-8. Peripheral Frame 0 Registers(1)
NAME
Device Emulation Registers
System Power Control Registers
FLASH Registers(3)
ADDRESS RANGE
0x00 0880 to 0x00 0984
0x00 0985 to 0x00 0987
0x00 0A80 to 0x00 0ADF
0x00 0AE0 to 0x00 0AEF
0x00 0B00 to 0x00 0B0F
0x00 0C00 to 0x00 0C3F
0x00 0CE0 to 0x00 0CFF
0x00 0D00 to 0x00 0DFF
0x00 1400 to 0x00 147F
0x00 1480 to 0x00 14FF
0x00 1500 to 0x00 157F
SIZE (×16)
261
3
EALLOW PROTECTED(2)
Yes
Yes
Yes
Yes
No
96
Code Security Module Registers
ADC registers (0 wait read only)
CPU–TIMER0/1/2 Registers
PIE Registers
16
16
64
No
32
No
PIE Vector Table
256
128
128
128
No
CLA Registers
Yes
NA
NA
CLA to CPU Message RAM (CPU writes ignored)
CPU to CLA Message RAM (CLA writes ignored)
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 6-9. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6000 to 0x00 61FF
0x00 6A00 to 0x00 6A1F
0x00 6AC0 to 0x00 6ADF
0x00 6AE0 to 0x00 6AFF
0x00 6B00 to 0x00 6B3F
0x00 6C00 to 0x00 6C7F
0x00 6F80 to 0x00 6FFF
SIZE (×16)
EALLOW PROTECTED
(1)
eCAN-A registers
eCAP1 registers
HRCAP1 registers
HRCAP2 registers
eQEP1 registers
LIN-A registers
512
32
No
(1)
32
(1)
(1)
(1)
(1)
32
64
128
128
GPIO registers
(1) Some registers are EALLOW protected. For more information, see the TMS320F2803x Technical Reference Manual.
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Table 6-10. Peripheral Frame 2 Registers
NAME
System Control Registers
ADDRESS RANGE
0x00 7010 to 0x00 702F
0x00 7040 to 0x00 704F
0x00 7050 to 0x00 705F
0x00 7060 to 0x00 706F
0x00 7070 to 0x00 707F
0x00 7100 to 0x00 717F
0x00 7900 to 0x00 793F
0x00 7740 to 0x00 774F
SIZE (×16)
EALLOW PROTECTED
32
16
16
16
16
128
64
16
Yes
No
SPI-A Registers
SCI-A Registers
No
NMI Watchdog Interrupt Registers
External Interrupt Registers
ADC Registers
Yes
Yes
(1)
(1)
I2C-A Registers
SPI-B Registers
No
(1) Some registers are EALLOW protected. For more information, see the TMS320F2803x Technical Reference Manual.
Table 6-11. Peripheral Frame 3 Registers
NAME
Comparator 1 registers
ADDRESS RANGE
0x00 6400 to 0x00 641F
0x00 6420 to 0x00 643F
0x00 6440 to 0x00 645F
0x00 6800 to 0x00 683F
0x00 6840 to 0x00 687F
0x00 6880 to 0x00 68BF
0x00 68C0 to 0x00 68FF
0x00 6900 to 0x00 693F
0x00 6940 to 0x00 697F
0x00 6980 to 0x00 69BF
SIZE (×16)
EALLOW PROTECTED
(1)
32
32
32
64
64
64
64
64
64
64
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Comparator 2 registers
Comparator 3 registers
ePWM1 + HRPWM1 registers
ePWM2 + HRPWM2 registers
ePWM3 + HRPWM3 registers
ePWM4 + HRPWM4 registers
ePWM5 + HRPWM5 registers
ePWM6 + HRPWM6 registers
ePWM7 + HRPWM7 registers
(1) Some registers are EALLOW protected. For more information, see the TMS320F2803x Technical Reference Manual.
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6.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical
device signals. The registers are defined in Table 6-12 .
Table 6-12. Device Emulation Registers
ADDRESS
RANGE
EALLOW
PROTECTED
NAME
SIZE (x16)
DESCRIPTION
Device Configuration Register
Part ID Register
0x0880
0x0881
DEVICECNF
PARTID(1)
2
1
Yes
0x3D 7E80
TMS320F28035PN
TMS320F28035PAG
TMS320F28035RSH
TMS320F28034PN
TMS320F28034PAG
TMS320F28034RSH
TMS320F28033PN
TMS320F28033PAG
TMS320F28033RSH
TMS320F28032PN
TMS320F28032PAG
TMS320F28032RSH
TMS320F28031PN
TMS320F28031PAG
TMS320F28031RSH
TMS320F28030PN
TMS320F28030PAG
TMS320F28030RSH
TMS320F28035
0x00BF
0x00BE
0x00BD
0x00BB
0x00BA
0x00B9
0x00B7
0x00B6
0x00B5
0x00B3
0x00B2
0x00B1
0x00AF
0x00AE
0x00AD
0x00AB
0x00AA
0x00A9
0x00BF
0x00BB
0x00B7
0x00B3
0x00AF
0x00AB
No
CLASSID
0x0882
0x0883
1
1
Class ID Register
TMS320F28034
TMS320F28033
No
No
TMS320F28032
TMS320F28031
TMS320F28030
REVID
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMS
0x0001 - Silicon Rev. A - TMS
(1) For TMS320F2803x devices, the PARTID register location differs from the TMS320F2802x devices' location of 0x3D7FFF.
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6.5 VREG/BOR/POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
6.5.1 On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors
are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
6.5.1.1 Using the On-chip VREG
To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by
the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the VDD pins. Driving an external load with the internal VREG is not supported.
6.5.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
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6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the
burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is
to create a clean reset throughout the device during the entire power-up procedure. The trip point is a
looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device
operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-
up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled
(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their
respective trip point. VDD BOR and overvoltage trip points are outside of the recommended operating
voltages. Proper device operation cannot be ensured. If overvoltage or undervoltage conditions affecting
the system is a concern for an application, an external voltage supervisor should be added. Figure 6-5
shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in
the BORCFG register. For details, see the System Control chapter in the TMS320F2803x Technical
Reference Manual.
In
I/O Pin
Out
(Force Hi-Z When High)
DIR (0 = Input, 1 = Output)
Internal
Weak PU
SYSRS
SYSCLKOUT
Deglitch
Filter
Sync
RS
WDRST
C28
Core
MCLKRS
PLL
JTAG
TCK
Detect
Logic
XRS
Pin
+
Clocking
Logic
VREGHALT
WDRST(A)
PBRS(B)
POR/BOR
Generating
Module
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
A. WDRST is the reset signal from the CPU watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 6-5. VREG + POR + BOR + Reset Signal Connectivity
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6.6 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low-power
modes.
Table 6-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
BORCFG
ADDRESS
0x00 0985
0x00 7010
0x00 7011
0x00 7012
0x00 7013
0x00 7014
0x00 7016
0x00 7019
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7025
0x00 7029
SIZE (x16)
DESCRIPTION(1)
BOR Configuration Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
XCLK
XCLKOUT Control
PLLSTS
PLL Status Register
CLKCTL
Clock Control Register
PLLLOCKPRD
INTOSC1TRIM
INTOSC2TRIM
PCLKCR2
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
PCLKCR3
PLLCR
PLL Lock Period
Internal Oscillator 1 Trim Register
Internal Oscillator 2 Trim Register
Peripheral Clock Control Register 2
Low-Speed Peripheral Clock Prescaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low-Power Mode Control Register 0
Peripheral Clock Control Register 3
PLL Control Register
SCSR
System Control and Status Register
Watchdog Counter Register
Watchdog Reset Key Register
Watchdog Control Register
WDCNTR
WDKEY
WDCR
(1) All registers in this table are EALLOW protected.
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Figure 6-6 shows the various clock domains that are discussed. Figure 6-7 shows the various clock
sources (both internal and external) that can provide a clock for device operation.
SYSCLKOUT
PCLKCR0/1/2/3
(System Ctrl Regs)
LOSPCP
(System Ctrl Regs)
C28x Core
CLKIN
Clock Enables
LSPCLK
Peripheral
Registers
SPI-A, SPI-B, SCI-A
Clock Enables
I/O
I/O
I/O
I/O
I/O
PF2
/2
Peripheral
Registers
eCAN-A, LIN-A
PF1
PF1
PF3
PF2
Clock Enables
Peripheral
Registers
GPIO
Mux
eCAP1, eQEP1, HRCAP1/2
Clock Enables
Peripheral
Registers
ePWM1/.../7, HRPWM1/.../7
Clock Enables
Peripheral
Registers
I2C-A
Clock Enables
ADC
Registers
PF2
PF0
16 Ch
12-Bit ADC
Analog
GPIO
Mux
Clock Enables
COMP1/2/3
COMP
Registers
6
PF3
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT).
Figure 6-6. Clock and Reset Domains
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CLKCTL[WDCLKSRCSEL]
Internal
OSC 1
(10 MHz)
0
OSC1CLK
INTOSC1TRIM Reg(A)
OSCCLKSRC1
WDCLK
CPU Watchdog
(OSC1CLK on XRS reset)
OSCE
1
CLKCTL[INTOSC1OFF]
1 = Turn OSC Off
CLKCTL[OSCCLKSRCSEL]
OSCCLK
CLKCTL[INTOSC1HALT]
1 = Ignore HALT
WAKEOSC
OSC2CLK
0
1
Internal
OSC 2
(10 MHz)
INTOSC2TRIM Reg(A)
PLL
Missing-Clock-Detect Circuit(B)
(OSC1CLK on XRS reset)
OSCE
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
1 = Turn OSC Off
10
11
CLKCTL[INTOSC2OFF]
Prescale
/1, /2, /4,
/8, /16
SYNC
Edge
Detect
01, 10, 11
CPUTMR2CLK
1 = Ignore HALT
01
1
0
00
CLKCTL[INTOSC2HALT]
SYSCLKOUT
OSCCLKSRC2
CLKCTL[OSCCLKSRC2SEL]
0 = GPIO38
1 = GPIO19
XCLK[XCLKINSEL]
CLKCTL[XCLKINOFF]
0
1
0
GPIO19
or
XCLKIN
GPIO38
XCLKIN
X1
X2
EXTCLK
(Crystal)
OSC
XTAL
WAKEOSC
(Oscillators enabled when this signal is high)
0 = OSC on (default on reset)
1 = Turn OSC off
CLKCTL[XTALOSCOFF]
A. Register loaded from TI OTP-based calibration function.
B. See Section 6.6.4 for details on missing clock detection.
Figure 6-7. Clock Tree
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6.6.1 Internal Zero Pin Oscillators
The F2803x devices contain two independent internal zero pin oscillators. By default both oscillators are
turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,
unused oscillators may be powered down by the user. The center frequency of these oscillators is
determined by their respective oscillator trim registers, written to in the calibration routine as part of the
boot ROM execution. See Section 5, Electrical Specifications, for more information on these oscillators.
6.6.2 Crystal Oscillator Option
The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level
signals applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be
connected to the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it
should be used with X2 and a crystal.
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in
Table 6-14. Furthermore, ESR range = 30 to 150 Ω.
Table 6-14. Typical Specifications for External Quartz Crystal(1)
FREQUENCY (MHz)
Rd (Ω)
2200
470
0
CL1 (pF)
18
CL2 (pF)
18
5
10
15
20
15
15
15
15
0
12
12
(1) Cshunt should be less than or equal to 5 pF.
XCLKIN/GPIO19/38
X1
X2
Rd
Turn off
XCLKIN path
in CLKCTL
register
CL1
Crystal
CL2
Figure 6-8. Using the On-chip Crystal Oscillator
NOTE
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the
IC and crystal. The value is usually approximately twice the value of the crystal's load
capacitance.
2. The load capacitance of the crystal is described in the crystal specifications of the
manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the
operation of their device with the MCU chip. The resonator/crystal vendor has the
equipment and expertise to tune the tank circuit. The vendor can also advise the
customer regarding the proper tank component values that will produce proper start-up
and stability over the entire operating range.
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XCLKIN/GPIO19/38
X1
X2
NC
External Clock Signal
(Toggling 0−V
)
DDIO
Figure 6-9. Using a 3.3-V External Oscillator
6.6.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control
PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing
to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of
the PLL (VCOCLK) is at least 50 MHz.
Table 6-15. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(1) (2)
PLLSTS[DIVSEL] = 0 or 1(3)
OSCCLK/4 (Default)(1)
(OSCCLK * 1)/4
PLLSTS[DIVSEL] = 2
OSCCLK/2
PLLSTS[DIVSEL] = 3
OSCCLK
0000 (PLL bypass)
0001
(OSCCLK * 1)/2
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
(OSCCLK * 11)/2
(OSCCLK * 12)/2
(OSCCLK * 1)/1
(OSCCLK * 2)/1
(OSCCLK * 3)/1
(OSCCLK * 4)/1
(OSCCLK * 5)/1
(OSCCLK * 6)/1
(OSCCLK * 7)/1
(OSCCLK * 8)/1
(OSCCLK * 9)/1
(OSCCLK * 10)/1
(OSCCLK * 11)/1
(OSCCLK * 12)/1
0010
(OSCCLK * 2)/4
0011
(OSCCLK * 3)/4
0100
(OSCCLK * 4)/4
0101
(OSCCLK * 5)/4
0110
(OSCCLK * 6)/4
0111
(OSCCLK * 7)/4
1000
(OSCCLK * 8)/4
1001
(OSCCLK * 9)/4
1010
(OSCCLK * 10)/4
(OSCCLK * 11)/4
(OSCCLK * 12)/4
1011
1100
(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(2) This register is EALLOW protected. See the System Control chapter in the TMS320F2803x Technical Reference Manual for more
information.
(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
Table 6-16. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/4
/4
/2
/1
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The PLL-based clock module provides four modes of operation:
•
INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide
the clock for the Watchdog block, core and CPU-Timer 2
•
INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide
the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
•
•
Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external
crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to
the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 4-1 for details.
External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to
be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.
The XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as
GPIO19 or GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit
disables this clock input (forced low). If the clock source is not used or the respective pins are used as
GPIOs, the user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that
clock source must be disabled (using the CLKCTL register) before switching clocks.
Table 6-17. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low-
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power-up or after an external
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
0, 1
2
3
OSCCLK * n/4
OSCCLK * n/2
OSCCLK * n/1
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
6.6.4 Loss of Input Clock (NMI Watchdog Function)
The 2803x devices may be clocked from either one of the internal zero-pin oscillators
(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the
clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will
issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at
a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired
immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the
Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect
the input clock failure and initiate necessary corrective action such as switching over to an alternative
clock source (if available) or initiate a shut-down procedure for the system.
If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a
preprogrammed time interval. Figure 6-10 shows the interrupt mechanisms involved.
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NMIFLG[NMINT]
NMIFLGCLR[NMINT]
Clear
Latch
Set
Clear
XRS
Generate
Interrupt
Pulse
When
Input = 1
NMIFLG[CLOCKFAIL]
Clear
Latch
1
0
0
NMIFLGCLR[CLOCKFAIL]
CLOCKFAIL
NMINT
SYNC?
Set
Clear
SYSCLKOUT
NMICFG[CLOCKFAIL]
NMIFLGFRC[CLOCKFAIL]
XRS
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
See System
Control Section
NMI Watchdog
NMIRS
Figure 6-10. NMI Watchdog
6.6.5 CPU Watchdog Module
The CPU watchdog module on the 2803x device is similar to the one used on the 281x/280x/283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter
or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets
the watchdog counter. Figure 6-11 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU watchdog counter decrements to initiate a CPU
watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU watchdog
counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).
NOTE
The CPU watchdog is different from the NMI watchdog. It is the legacy watchdog that is
present in all 28x devices.
NOTE
Applications in which the correct CPU operating frequency is absolutely critical should
implement a mechanism by which the MCU will be held in reset, should the input clocks ever
fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the
capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a
periodic basis to prevent it from getting fully charged. Such a circuit would also help in
detecting failure of the flash memory.
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WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR(7:0)
WDCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
SCSR(WDOVERRIDE)
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Watchdog
55 + AA
Output Pulse
Good K ey
(512 OSCCLKs)
Key Detector
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
1
0
1
(A)
WDRST
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 6-11. CPU Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the CPU watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM
block so that it can wake the device from STANDBY (if enabled). See Section 6.7, Low-power Modes
Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU
out of IDLE mode.
In HALT mode, the CPU watchdog can be used to wake up the device through a device reset.
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6.7 Low-power Modes Block
Table 6-18 summarizes the various modes.
Table 6-18. Low-power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, CPU watchdog interrupt, any
enabled interrupt
IDLE
00
On
On
On
On
XRS, CPU watchdog interrupt, GPIO
Port A signal, debugger(2)
STANDBY
HALT(3)
01
Off
Off
(CPU watchdog still running)
Off
(on-chip crystal oscillator and
PLL turned off, zero-pin oscillator
and CPU watchdog state
dependent on user code.)
XRS, GPIO Port A signal, debugger(2)
CPU watchdog
,
1X
Off
Off
(1) The EXIT column lists which signals or under what conditions the low-power mode is exited. A low signal, on any of the signals, exits
the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-
power mode will not be exited and the device will go back into the indicated low-power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt that is recognized by the
processor. The LPM block performs no tasks during this mode as long as
the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY
mode. The user must select which signal(s) will wake the device in the
GPIOLPMSEL register. The selected signal(s) are also qualified by the
OSCCLK before waking the device. The number of OSCCLKs is specified in
the LPMCR0 register.
HALT Mode:
CPU watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake
the device from HALT mode. The user selects the signal in the
GPIOLPMSEL register.
NOTE
The low-power modes do not affect the state of the output pins (PWM pins included). They
will be in whatever state the code left them in when the IDLE instruction was executed. See
the System Control chapter in the TMS320F2803x Technical Reference Manual for more
details.
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6.8 Interrupts
Figure 6-12 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, ePWM, I2C, HRPWM, HRCAP,
eCAP, ADC, eQEP, CLA, LIN, eCAN)
WDINT
Watchdog
WAKEINT
Sync
LPMINT
Low Power Modes
SYSCLKOUT
XINT1
XINT1
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
XINT2SOC
INT1
to
INT12
ADC
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
Core
GPIOXINT2SEL(4:0)
GPIO0.int
XINT3
TINT0
XINT3
GPIO
MUX
Interrupt Control
XINT3CR(15:0)
XINT3CTR(15:0)
GPIO31.int
GPIOXINT3SEL(4:0)
CPU TIMER 0
CPU TIMER 1
CPU TIMER 2
TINT1
TINT2
INT13
INT14
CPUTMR2CLK
CLOCKFAIL
NMIRS
System Control
(See the System
Control section.)
NMI interrupt with watchdog function
(See the NMI Watchdog section.)
NMI
Figure 6-12. External and PIE Interrupt Sources
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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with
8 interrupts per group equals 96 possible interrupts. Table 6-19 shows the interrupts used by 2803x
devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. The TRAP #0 instruction attempts to transfer program control to the
address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector.
Therefore, the TRAP #0 instruction should not be used when the PIE is enabled. Doing so will result in
undefined behavior.
When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the
interrupt service routine corresponding to the first vector within the PIE group. For example: the TRAP #1
instruction fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so
forth.
IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
Figure 6-13. Multiplexing of Interrupts Using the PIE Block
72
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Table 6-19. PIE MUXed Peripheral Interrupt Vector Table(1)
INTx.8
WAKEINT
(LPM/WD)
0xD4E
Reserved
–
INTx.7
TINT0
INTx.6
ADCINT9
(ADC)
INTx.5
XINT2
INTx.4
XINT1
INTx.3
Reserved
–
INTx.2
ADCINT2
(ADC)
INTx.1
ADCINT1
(ADC)
INT1.y
INT2.y
INT3.y
INT4.y
INT5.y
INT6.y
INT7.y
INT8.y
INT9.y
INT10.y
INT11.y
INT12.y
(TIMER 0)
0xD4C
Ext. int. 2
0xD48
Ext. int. 1
0xD46
0xD4A
0xD44
0xD42
0xD40
EPWM7_TZINT
(ePWM7)
0xD5C
EPWM6_TZINT
(ePWM6)
0xD5A
EPWM5_TZINT
(ePWM5)
0xD58
EPWM4_TZINT
(ePWM4)
0xD56
EPWM3_TZINT
(ePWM3)
0xD54
EPWM2_TZINT
(ePWM2)
0xD52
EPWM1_TZINT
(ePWM1)
0xD50
0xD5E
Reserved
–
EPWM7_INT
(ePWM7)
0xD6C
EPWM6_INT
(ePWM6)
0xD6A
EPWM5_INT
(ePWM5)
0xD68
EPWM4_INT
(ePWM4)
0xD66
EPWM3_INT
(ePWM3)
0xD64
EPWM2_INT
(ePWM2)
0xD62
EPWM1_INT
(ePWM1)
0xD60
0xD6E
HRCAP2_INT
(HRCAP2)
0xD7E
Reserved
–
HRCAP1_INT
(HRCAP1)
0xD7C
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
ECAP1_INT
(eCAP1)
0xD70
0xD7A
0xD78
0xD76
0xD74
0xD72
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
EQEP1_INT
(eQEP1)
0xD80
0xD8E
Reserved
–
0xD8C
0xD8A
0xD88
0xD86
0xD84
0xD82
Reserved
–
Reserved
–
Reserved
–
SPITXINTB
(SPI-B)
0xD96
SPIRXINTB
(SPI-B)
0xD94
SPITXINTA
(SPI-A)
0xD92
SPIRXINTA
(SPI-A)
0xD9E
Reserved
–
0xD9C
0xD9A
0xD98
0xD90
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
0xDAE
Reserved
–
0xDAC
Reserved
–
0xDAA
Reserved
–
0xDA8
0xDA6
0xDA4
0xDA2
0xDA0
Reserved
–
Reserved
–
Reserved
–
I2CINT2A
(I2C-A)
0xDB2
I2CINT1A
(I2C-A)
0xDBE
Reserved
–
0xDBC
Reserved
–
0xDBA
ECAN1_INTA
(CAN-A)
0xDCA
ADCINT6
(ADC)
0xDB8
0xDB6
0xDB4
0xDB0
ECAN0_INTA
(CAN-A)
0xDC8
ADCINT5
(ADC)
LIN1_INTA
(LIN-A)
0xDC6
LIN0_INTA
(LIN-A)
0xDC4
ADCINT3
(ADC)
SCITXINTA
(SCI-A)
0xDC2
SCIRXINTA
(SCI-A)
0xDCE
ADCINT8
(ADC)
0xDCC
ADCINT7
(ADC)
0xDC0
ADCINT4
(ADC)
ADCINT2
(ADC)
ADCINT1
(ADC)
0xDDE
CLA1_INT8
(CLA)
0xDDC
CLA1_INT7
(CLA)
0xDDA
CLA1_INT6
(CLA)
0xDD8
CLA1_INT5
(CLA)
0xDD6
0xDD4
CLA1_INT3
(CLA)
0xDD2
0xDD0
CLA1_INT4
(CLA)
CLA1_INT2
(CLA)
CLA1_INT1
(CLA)
0xDEE
LUF
0xDEC
LVF
0xDEA
Reserved
–
0xDE8
0xDE6
0xDE4
0xDE2
0xDE0
Reserved
–
Reserved
–
Reserved
–
Reserved
–
XINT3
(CLA)
(CLA)
Ext. Int. 3
0xDF0
0xDFE
0xDFC
0xDFA
0xDF8
0xDF6
0xDF4
0xDF2
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
•
•
No peripheral within the group is asserting interrupts.
No peripheral interrupts are assigned to the group (for example, PIE group 7).
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Table 6-20. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (x16)
DESCRIPTION(1)
PIE, Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA –
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table
is protected.
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6.8.1 External Interrupts
Table 6-21. External Interrupt Registers
NAME
XINT1CR
XINT2CR
XINT3CR
XINT1CTR
XINT2CTR
XINT3CTR
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7078
0x00 7079
0x00 707A
SIZE (x16)
DESCRIPTION
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT1 counter register
1
1
1
1
1
1
XINT2 counter register
XINT3 counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control chapter in the TMS320F2803x Technical
Reference Manual.
6.8.1.1 External Interrupt Electrical Data/Timing
Table 6-22. External Interrupt Timing Requirements(1)
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
Synchronous
With qualifier
(2)
tw(INT)
Pulse duration, INT input low/high
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-68.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-23. External Interrupt Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-68.
t
w(INT)
XINT1, XINT2, XINT3
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 6-14. External Interrupt Timing
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6.9 Peripherals
6.9.1 Control Law Accelerator (CLA) Overview
The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-
critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA
enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks
frees up the main CPU to perform other system and communication functions concurently. The following is
a list of major features of the CLA.
•
•
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
–
Complete bus architecture:
•
•
Program address bus and program data bus
Data address bus, data read bus, and data write bus
–
–
–
–
–
Independent eight-stage pipeline.
12-bit program counter (MPC)
Four 32-bit result registers (MR0–MR3)
Two 16-bit auxillary registers (MAR0, MAR1)
Status register (MSTF)
•
Instruction set includes:
–
–
–
–
–
–
–
IEEE single-precision (32-bit) floating-point math operations
Floating-point math with parallel load or store
Floating-point multiply with parallel add or subtract
1/X and 1/sqrt(X) estimations
Data type conversions.
Conditional branch and call
Data load/store operations
•
•
The CLA program code can consist of up to eight tasks or interrupt service routines.
–
–
–
–
–
The start address of each task is specified by the MVECT registers.
No limit on task size as long as the tasks fit within the CLA program memory space.
One task is serviced at a time through to completion. There is no nesting of tasks.
Upon task completion, a task-specific interrupt is flagged within the PIE.
When a task finishes, the next highest-priority pending task is automatically started.
Task trigger mechanisms:
–
–
C28x CPU through the IACK instruction
Task1 to Task7: the corresponding ADC or ePWM module interrupt. For example:
•
•
•
Task1: ADCINT1 or EPWM1_INT
Task2: ADCINT2 or EPWM2_INT
Task7: ADCINT7 or EPWM7_INT
–
Task8: ADCINT8 or by CPU Timer 0.
•
Memory and Shared Peripherals:
–
–
–
Two dedicated message RAMs for communication between the CLA and the main CPU.
The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
The CLA has direct access to the ADC Result registers, comparator registers, and the
ePWM+HRPWM registers.
For more information on the CLA, see the Control Law Accelerator (CLA) chapter in the TMS320F2803x
Technical Reference Manual.
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IACK
Peripheral Interrupts
CLA Control
Registers
ADCINT1 to
ADCINT8
CLA_INT1 to CLA_INT8
MIFR
MIOVF
MICLR
MICLROVF
MIFRC
MIER
EPWM1_INT to
EPWM8_INT
Main
28x
CPU
INT11
INT12
MPERINT1
to
MPERINT8
PIE
CPU Timer 0
LVF
LUF
MIRUN
Main CPU Read/Write Data Bus
MPISRCSEL1
MVECT1
MVECT2
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
CLA Program Address Bus
CLA Program Data Bus
CLA
Program
Memory
CLA
Data
Memory
Map to CLA or
CPU Space
Map to CLA or
CPU Space
MMEMCFG
MCTL
CLA
Shared
Message
RAMs
SYSCLKOUT
CLAENCLK
SYSRS
ADC
Result
Registers
MEALLOW
CLA Execution
Registers
CLA Data Read Address Bus
MPC(12)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
ePWM
and
HRPWM
Registers
CLA Data Read Data Bus
CLA Data Write Address Bus
CLA Data Write Data Bus
Main CPU Read Data Bus
Comparator
Registers
MAR0(32)
MAR1(32)
Figure 6-15. CLA Block Diagram
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Table 6-24. CLA Control Registers
CLA1
ADDRESS
EALLOW
PROTECTED
REGISTER NAME
MVECT1
SIZE (x16)
DESCRIPTION(1)
0x1400
0x1401
0x1402
0x1403
0x1404
0x1405
0x1406
0x1407
0x1410
0x1411
0x1414
0x1420
0x1421
0x1422
0x1423
0x1424
0x1425
0x1426
0x1427
0x1428
0x142A
0x142B
0x142E
0x1430
0x1434
0x1438
0x143C
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
CLA Interrupt/Task 1 Start Address
CLA Interrupt/Task 2 Start Address
CLA Interrupt/Task 3 Start Address
CLA Interrupt/Task 4 Start Address
CLA Interrupt/Task 5 Start Address
CLA Interrupt/Task 6 Start Address
CLA Interrupt/Task 7 Start Address
CLA Interrupt/Task 8 Start Address
CLA Control Register
MVECT2
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
MCTL
MMEMCFG
MPISRCSEL1
MIFR
CLA Memory Configure Register
Peripheral Interrupt Source Select Register 1
Interrupt Flag Register
Interrupt Overflow Register
Interrupt Force Register
Interrupt Clear Register
Interrupt Overflow Clear Register
Interrupt Enable Register
Interrupt RUN Register
Interrupt Priority Control Register
CLA Program Counter
CLA Aux Register 0
MIOVF
MIFRC
MICLR
MICLROVF
MIER
MIRUN
MIPCTL
MPC(2)
MAR0(2)
MAR1(2)
MSTF(2)
MR0(2)
MR1(2)
MR2(2)
MR3(2)
–
–
CLA Aux Register 1
–
CLA STF Register
–
CLA R0H Register
–
CLA R1H Register
–
CLA R2H Register
–
CLA R3H Register
(1) All registers in this table are CSM protected
(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 6-25. CLA Message RAM
ADDRESS RANGE
0x1480 – 0x14FF
0x1500 – 0x157F
SIZE (x16)
128
DESCRIPTION
CLA to CPU Message RAM
CPU to CLA Message RAM
128
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6.9.2 Analog Block
A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.
The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the
timing control of start of conversions. Figure 6-16 shows the interaction of the analog module with the rest
of the F2803x system.
For more information on the ADC, see the Analog-to-Digital Converter and Comparator chapter in the
TMS320F2803x Technical Reference Manual.
56-Pin
80-Pin
(3.3 V) VDDA
(Agnd) VSSA
VREFLO
64-Pin
VDDA
VDDA
VSSA
VREFLO
Tied To
VSSA
Interface Reference
Diff
VREFLO
VREFHI
A0
VREFHI
Tied To
A0
VREFHI
A0
B0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
A1
A2
A3
A4
A1
B1
COMP1OUT
A2
AIO2
AIO10
10-Bit
DAC
Comp1
Comp2
B2
A6
A7
B0
B1
B2
B3
B4
A3
B3
ADC
COMP2OUT
A4
B4
AIO4
AIO12
10-Bit
DAC
B5
Temperature Sensor
B6
B7
A5
A6
COMP3OUT
Signal Pinout
AIO6
AIO14
10-Bit
DAC
Comp3
B6
A7
B7
Figure 6-16. Analog Pin Configurations
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6.9.2.1 Analog-to-Digital Converter (ADC)
6.9.2.1.1 Features
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-
and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to
16 analog input channels. The converter can be configured to run with an internal band-gap reference to
create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to
create ratiometric-based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a
series of conversions from a single trigger. However, the basic principle of operation is centered around
the configurations of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
•
•
•
12-bit ADC core with built-in dual sample-and-hold (S/H)
Simultaneous sampling or sequential sampling modes
Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input
analog voltage is derived by:
–
Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or
external reference modes.)
Digital Value = 0,
when input £ 0 V
Input Analog Voltage -
VREFLO
Digital Value = 4096 ´
when 0 V < input < 3.3 V
3.3
Digital Value = 4095,
when input ³ 3.3 V
–
External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA
when using either internal or external reference modes.)
Digital Value = 0,
when input £ 0 V
Input Analog Voltage -
VREFLO
Digital Value = 4096 ´
when 0 V < input <
VREFHI
-
VREFHI VREFLO
Digital Value = 4095,
when input ³
VREFHI
•
•
•
•
Up to 16-channel, multiplexed inputs
16 SOCs, configurable for trigger, sample window, and channel
16 result registers (individually addressable) to store conversion values
Multiple trigger sources
–
–
–
–
–
S/W – software immediate start
ePWM 1–7
GPIO XINT2
CPU Timers 0/1/2
ADCINT1/2
•
9 flexible PIE interrupts, can configure interrupt request after any conversion
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Table 6-26. ADC Configuration and Control Registers
SIZE
(x16)
EALLOW
PROTECTED
REGISTER NAME
ADDRESS
DESCRIPTION
ADCCTL1
0x7100
0x7101
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x7110
0x7112
0x7114
0x7115
0x7118
0x711A
0x711C
0x711E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Yes
Yes
No
Control 1 Register
ADCCTL2
Control 2 Register
ADCINTFLG
Interrupt Flag Register
ADCINTFLGCLR
ADCINTOVF
No
Interrupt Flag Clear Register
No
Interrupt Overflow Register
ADCINTOVFCLR
INTSEL1N2
No
Interrupt Overflow Clear Register
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Interrupt 1 and 2 Selection Register
Interrupt 3 and 4 Selection Register
Interrupt 5 and 6 Selection Register
Interrupt 7 and 8 Selection Register
Interrupt 9 Selection Register (reserved Interrupt 10 Selection)
SOC Priority Control Register
INTSEL3N4
INTSEL5N6
INTSEL7N8
INTSEL9N10
SOCPRICTL
ADCSAMPLEMODE
ADCINTSOCSEL1
ADCINTSOCSEL2
ADCSOCFLG1
ADCSOCFRC1
ADCSOCOVF1
ADCSOCOVFCLR1
Sampling Mode Register
Interrupt SOC Selection 1 Register (for 8 channels)
Interrupt SOC Selection 2 Register (for 8 channels)
SOC Flag 1 Register (for 16 channels)
SOC Force 1 Register (for 16 channels)
SOC Overflow 1 Register (for 16 channels)
SOC Overflow Clear 1 Register (for 16 channels)
SOC0 Control Register to SOC15 Control Register
No
No
No
ADCSOC0CTL to
ADCSOC15CTL
0x7120 –
0x712F
Yes
ADCREFTRIM
ADCOFFTRIM
COMPHYSTCTL
ADCREV
0x7140
0x7141
0x714C
0x714F
1
1
1
1
Yes
Yes
Yes
No
Reference Trim Register
Offset Trim Register
Comparator Hysteresis Control Register
Revision Register
Table 6-27. ADC Result Registers (Mapped to PF0)
SIZE
(x16)
EALLOW
PROTECTED
REGISTER NAME
ADCRESULT0 to ADCRESULT15
ADDRESS
DESCRIPTION
0xB00 to 0xB0F
1
No
ADC Result 0 Register to ADC Result 15
Register
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0-Wait
Result
Registers
PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
TINT 0
TINT 1
TINT 2
CPUTIMER 0
CPUTIMER 1
CPUTIMER 2
ADCTRIG 1
ADCTRIG 2
ADCTRIG 3
ADC
Core
12-Bit
AIO
MUX
ADC
Channels
XINT 2SOC
XINT 2
EPWM 1
EPWM 2
EPWM 3
EPWM 4
EPWM 5
EPWM 6
EPWM 7
ADCTRIG 4
SOCA 1
SOCB 1
SOCA 2
SOCB 2
SOCA 3
SOCB 3
SOCA 4
SOCB 4
SOCA 5
SOCB 5
SOCA 6
SOCB 6
SOCA 7
SOCB 7
ADCTRIG 5
ADCTRIG 6
ADCTRIG 7
ADCTRIG 8
ADCTRIG 9
ADCTRIG 10
ADCTRIG 11
ADCTRIG 12
ADCTRIG 13
ADCTRIG 14
ADCTRIG 15
ADCTRIG 16
ADCTRIG 17
ADCTRIG 18
Figure 6-17. ADC Connections
ADC Connections if the ADC is Not Used
TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following
is a summary of how the ADC pins should be connected, if the ADC is not used in an application:
•
•
•
•
VDDA – Connect to VDDIO
VSSA – Connect to VSS
VREFLO – Connect to VSS
ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog
ground (VSSA).
NOTE
Unused ADCIN pins that are multiplexed with AIO function should not be directly connected
to analog ground. They should be grounded through a 1-kΩ resistor. This is to prevent an
errant code from configuring these pins as AIO outputs and driving grounded pins to a logic-
high state.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power
savings.
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6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
Table 6-28. External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(HCO)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 6-18. ADCSOCAO or ADCSOCBO Timing
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6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
Table 6-29. ADC Electrical Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
0.001
7
Bits
ADC clock
60-MHz device
28035/34/33/32
28031/30
60
64
64
MHz
Sample Window
ADC
Clocks
24
ACCURACY
INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz(1)
–4
–1
4
1
LSB
LSB
DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz,
no missing codes
(2)
Offset error
Executing a single self-
recalibration(3)
–20
–4
0
0
20
4
LSB
Executing periodic self-
recalibration(4)
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ADC temperature coefficient with internal reference
ADC temperature coefficient with external reference
VREFLO
–60
–40
–4
60
40
4
LSB
LSB
LSB
–4
4
LSB
–50
–20
ppm/°C
ppm/°C
µA
–100
100
VREFHI
µA
ANALOG INPUT
Analog input voltage with internal reference
Analog input voltage with external reference
VREFLO input voltage(5)
0
VREFLO
VSSA
3.3
VREFHI
0.66
V
V
V
VREFHI input voltage(6)
2.64
VDDA
VDDA
V
with VREFLO = VSSA
1.98
Input capacitance
5
pF
Input leakage current
±2
μA
(1) INL will degrade when the ADC input voltage goes above VDDA
.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) For more details, see the TMS320F2803x MCUs Silicon Errata.
(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed
as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"
section of the Analog-to-Digital Converter and Comparator chapter in the TMS320F2803x Technical Reference Manual.
(5) VREFLO is always connected to VSSA on the 64-pin PAG device.
(6) VREFHI must not exceed VDDA when using either internal or external reference modes. Because VREFHI is tied to ADCINA0 on the 64-pin
PAG device, the input signal on ADCINA0 must not exceed VDDA
.
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Table 6-30. ADC Power Modes
ADC OPERATING MODE
CONDITIONS
IDDA
UNITS
ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
Mode A – Operating Mode
13
mA
ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 0)
Mode B – Quick Wake Mode
4
mA
mA
mA
ADC Clock Enabled
Band gap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
Mode C – Comparator-Only Mode
Mode D – Off Mode
1.5
ADC Clock Enabled
Band gap On (ADCBGPWD = 0)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
0.075
6.9.2.1.3.1 Internal Temperature Sensor
Table 6-31. Temperature Sensor Coefficient
PARAMETER(1)
MIN
TYP
0.18(2)(3)
1750
MAX
UNIT
°C/LSB
LSB
TSLOPE
Degrees C of temperature movement per measured ADC LSB change
of the temperature sensor
TOFFSET
ADC output at 0°C of the temperature sensor
(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(2) ADC temperature coeffieicient is accounted for in this specification
(3) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
6.9.2.1.3.2 ADC Power-Up Control Bit Timing
Table 6-32. ADC Power-Up Delays
PARAMETER(1)
MIN
MAX
UNIT
td(PWD)
Delay time for the ADC to be stable after power up
1
ms
(1) Timings maintain compatibility to the ADC module. The 2803x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
td(PWD)
Request for ADC
Conversion
Figure 6-19. ADC Conversion Timing
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Ron
3.4 kW
Switch
Rs
ADCIN
Cp
Ch
Source
Signal
ac
5 pF
1.6 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 3.4 kW
Sampling Capacitor (Ch): 1.6 pF
Parasitic Capacitance (Cp): 5 pF
Source Resistance (Rs): 50 W
Figure 6-20. ADC Input Impedance Model
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6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
Analog Input
SOC0 Sample
Window
SOC1 Sample
Window
SOC2 Sample
Window
0
2
9
15
22 24
37
ADCCLK
ADCCTL 1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0
SOC1
SOC2
Result 0 Latched
2 ADCCLKs
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
ADCINTFLG.ADCINTx
Minimum
7 ADCCLKs
Conversion 0
13 ADC Clocks
1 ADCCLK
6
Minimum
ADCCLKs 7 ADCCLKs
Conversion 1
13 ADC Clocks
Figure 6-21. Timing Example for Sequential Mode / Late Interrupt Pulse
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Analog Input
SOC0 Sample
Window
SOC1 Sample
Window
SOC2 Sample
Window
0
2
9
15
22 24
37
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0
SOC1
SOC2
Result 0 Latched
ADCRESULT 1
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
7 ADCCLKs
Conversion 0
13 ADC Clocks
2 ADCCLKs
6
Minimum
ADCCLKs 7 ADCCLKs
Conversion 1
13 ADC Clocks
Figure 6-22. Timing Example for Sequential Mode / Early Interrupt Pulse
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Analog Input A
Analog Input B
SOC0 Sample
A Window
SOC2 Sample
A Window
SOC0 Sample
B Window
SOC2 Sample
B Window
0
2
9
22 24
37
50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG 1.SOC0
ADCSOCFLG 1.SOC1
ADCSOCFLG 1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
2 ADCCLKs
ADCRESULT 1
Result 0 (B) Latched
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
1 ADCCLK
EOC2 Pulse
ADCINTFLG .ADCINTx
Minimum
7 ADCCLKs
Conversion 0 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
2 ADCCLKs
19
ADCCLKs
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
Figure 6-23. Timing Example for Simultaneous Mode / Late Interrupt Pulse
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Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
Analog Input B
SOC0 Sample
B Window
SOC2 Sample
B Window
0
2
9
22 24
37
50
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
ADCRESULT 0
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
2 ADCCLKs
Result 0 (B) Latched
ADCRESULT 1
ADCRESULT 2
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Conversion 0 (A)
13 ADC Clocks
Conversion 0 (B)
13 ADC Clocks
Minimum
2 ADCCLKs
7 ADCCLKs
19
Minimum
7 ADCCLKs
Conversion 1 (A)
13 ADC Clocks
ADCCLKs
Figure 6-24. Timing Example for Simultaneous Mode / Early Interrupt Pulse
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6.9.2.2 ADC MUX
To COMPy A or B input
To ADC Channel X
Logic implemented in GPIO MUX block
AIOx Pin
SYSCLK
AIOxIN
1
AIOxINE
AIODAT Reg
(Read)
SYNC
0
AIODAT Reg
(Latch)
AIOMUX 1 Reg
AIOSET,
AIOCLEAR,
AIOTOGGLE
Regs
AIODIR Reg
(Latch)
1
(0 = Input, 1 = Output)
0
0
Figure 6-25. AIOx Pin Multiplexing
The ADC channel and Comparator functions are always available. The digital I/O function is available only
when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects
the actual pin state.
The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode,
reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer
is disabled to prevent analog signals from generating noise.
On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO
function disabled for that pin.
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6.9.2.3 Comparator Block
Figure 6-26 shows the interaction of the Comparator modules with the rest of the system.
COMP x A
+
COMP x B
COMP
TZ1/2/3
-
GPIO
MUX
COMP x
+
DAC x
Wrapper
ePWM
AIO
MUX
COMPxOUT
DAC
Core
10-Bit
Figure 6-26. Comparator Block Diagram
Table 6-33. Comparator Control Registers
REGISTER
NAME
COMP1
ADDRESS
COMP2
ADDRESS
COMP3
ADDRESS
SIZE
(x16)
EALLOW
PROTECTED
DESCRIPTION
COMPCTL
0x6400
0x6402
0x6404
0x6406
0x6420
0x6422
0x6424
0x6426
0x6440
0x6442
0x6444
0x6446
1
1
1
1
Yes
No
Comparator Control Register
Comparator Status Register
DAC Control Register
COMPSTS
DACCTL
DACVAL
Yes
No
DAC Value Register
RAMPMAXREF_
ACTIVE
Ramp Generator Maximum Reference
(Active) Register
0x6408
0x640A
0x640C
0x6428
0x642A
0x642C
0x6448
0x644A
0x644C
1
1
1
No
No
No
RAMPMAXREF_
SHDW
Ramp Generator Maximum Reference
(Shadow) Register
RAMPDECVAL_
ACTIVE
Ramp Generator Decrement Value (Active)
Register
RAMPDECVAL_
SHDW
Ramp Generator Decrement Value
(Shadow) Register
0x640E
0x6410
0x642E
0x6430
0x644E
0x6450
1
1
No
No
RAMPSTS
Ramp Generator Status Register
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6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
Table 6-34. Electrical Characteristics of the Comparator/DAC
PARAMETER
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
VSSA – VDDA
V
Comparator response time to PWM Trip Zone (Async)
30
±5
35
ns
Input Offset
Input Hysteresis(1)
mV
mV
DAC
DAC Output Range
DAC resolution
DAC settling time
DAC Gain
VSSA – VDDA
V
10
bits
See Figure 6-27
–1.5%
10
DAC Offset
Monotonic
mV
Yes
±3
INL
LSB
(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback
resistance between the output of the comparator and the noninverting input of the comparator. There is an option to disable the
hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter in the TMS320F2803x
Technical Reference Manual for more information on this option if needed in your system.
1100
1000
900
800
700
600
500
400
300
200
100
0
0
50
100
150
200
250
300
350
400
450
500
DAC Step Size (Codes)
DAC Accuracy
15 Codes
7 Codes
3 Codes
1 Code
Figure 6-27. DAC Settling Time
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6.9.3 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full
scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is
defined as level one-half LSB beyond the last code transition. The deviation is measured from the center
of each particular code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal
value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is
the deviation of the actual difference between first and last code transitions and the ideal difference
between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral
components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is
expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD -1.76)
N =
6.02
it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured
input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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6.9.4 Serial Peripheral Interface (SPI) Module
The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are
available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of
programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer
rate. Normally, the SPI is used for communications between the MCU and external peripherals or another
processor. Typical applications include external I/O or peripheral expansion through devices such as shift
registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave
operation of the SPI.
The SPI module features include:
•
Four external pins:
–
–
–
–
SPISOMI: SPI slave-output/master-input pin
SPISIMO: SPI slave-input/master-output pin
SPISTE: SPI slave transmit-enable pin
SPICLK: SPI serial-clock pin
NOTE
All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to127
when SPIBRR = 0,1, 2
(SPIBRR + 1)
LSPCLK
Baud rate =
4
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
–
–
–
–
Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the
falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the
rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled
algorithms.
•
Nine SPI module control registers: In control register frame beginning at address 7040h.
NOTE
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
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Enhanced feature:
•
•
•
•
4-level transmit/receive FIFO
Delayed transmit control
Bidirectional 3 wire SPI mode support
Audio data receive support through SPISTE inversion
The SPI port operation is configured and controlled by the registers listed in Table 6-35 and Table 6-36.
Table 6-35. SPI-A Registers
NAME
SPICCR
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (x16) EALLOW PROTECTED
DESCRIPTION(1)
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
SPICTL
SPISTS
SPIBRR
SPI-A Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 6-36. SPI-B Registers
NAME
SPICCR
ADDRESS
0x7740
0x7741
0x7742
0x7744
0x7746
0x7747
0x7748
0x7749
0x774A
0x774B
0x774C
0x774F
SIZE (x16) EALLOW PROTECTED
DESCRIPTION(1)
SPI-B Configuration Control Register
SPI-B Operation Control Register
SPI-B Status Register
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
SPICTL
SPISTS
SPIBRR
SPI-B Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-B Receive Emulation Buffer Register
SPI-B Serial Input Buffer Register
SPI-B Serial Output Buffer Register
SPI-B Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-B FIFO Transmit Register
SPI-B FIFO Receive Register
SPI-B FIFO Control Register
SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the TMS320F2803x
Technical Reference Manual.
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Figure 6-28 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
SPISTS.7
RX FIFO Registers
SPICTL.4
SPIRXBUF
RX FIFO _0
RX FIFO _1
-----
SPIINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _3
16
SPIRXBUF
Buffer Register
SPIFFOVF
FLAG
SPIFFRX.15
To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3
TX Interrupt
Logic
TX FIFO Interrupt
-----
TX FIFO _1
SPITX
TX FIFO _0
16
SPI INT
ENA
16
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
TRIWIRE
SPIPRI.0
16
M
S
M
SPIDAT
Data Register
TW
S
SW1
SW2
SPISIMO
M
S
TW
SPIDAT.15 - 0
M
S
TW
SPISOMI
STEINV
SPIPRI.1
STEINV
Talk
SPICTL.1
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
LSPCLK
SPICCR.3 - 0
S
SW3
3
2
1
0
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
SPIBRR.6 - 0
SPICCR.6
SPICTL.3
SPICLK
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 6-28. SPI Module Block Diagram (Slave Mode)
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6.9.4.1 SPI Master Mode Electrical Data/Timing
Table 6-37 lists the master mode timing (clock phase = 0) and Table 6-38 lists the master mode timing
(clock phase = 1). Figure 6-29 and Figure 6-30 show the timing waveforms.
Table 6-37. SPI Master Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
BRR EVEN
MIN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
+
0.5tc(SPC)M
+
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
–
0.5tc(SPC)M
–
3
4
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
5
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
8
26
0
26
Hold time, SPISOMI valid after
SPICLK
9
0
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M
–
23
24
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M
–
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 6-29. SPI Master Mode External Timing (Clock Phase = 0)
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Table 6-38. SPI Master Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)(5)
BRR EVEN
MIN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
–
0.5tc(SPC)M
–
tw(SPC1)M
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
+
3
6
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
26
0
26
Hold time, SPISOMI valid after
SPICLK
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
td(STE)M
0.5tc(SPC) – 10
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 6-30. SPI Master Mode External Timing (Clock Phase = 1)
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6.9.4.2 SPI Slave Mode Electrical Data/Timing
Table 6-39 lists the slave mode timing (clock phase = 0) and Table 6-40 lists the slave mode timing (clock
phase = 1). Figure 6-31 and Figure 6-32 show the timing waveforms.
Table 6-39. SPI Slave Mode External Timing (Clock Phase = 0)(1)(2)(3)(4)(5)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
21
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 6-31. SPI Slave Mode External Timing (Clock Phase = 0)
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Table 6-40. SPI Slave Mode External Timing (Clock Phase = 1)(1)(2)(3)(4)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
21
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 6-32. SPI Slave Mode External Timing (Clock Phase = 1)
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6.9.5 Serial Communications Interface (SCI) Module
The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports
digital communications between the CPU and other asynchronous peripherals that use the standard
nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its
own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-
duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,
and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-
select register.
Features of each SCI module include:
•
Two external pins:
–
–
SCITXD: SCI transmit-output pin
SCIRXD: SCI receive-input pin
NOTE
Both pins can be used as GPIO if not used for SCI.
–
Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
Baud rate =
16
•
Data-word format
–
–
–
–
One start bit
Data-word length programmable from 1 to 8 bits
Optional even/odd/no parity bit
One or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms
with status flags.
–
Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX
EMPTY flag (transmitter-shift register is empty)
–
Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag
(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
•
•
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (nonreturn-to-zero) format
NOTE
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.
When a register is accessed, the register data is in the lower byte (7–0), and the upper byte
(15–8) is read as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
4-level transmit/receive FIFO
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The SCI port operation is configured and controlled by the registers listed in Table 6-41.
Table 6-41. SCI-A Registers(1)
EALLOW
SIZE (x16)
NAME
SCICCRA
ADDRESS
DESCRIPTION
PROTECTED
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
No
SCI-A Communications Control Register
SCI-A Control Register 1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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For more information on the SCI, see the Serial Communications Interface (SCI) chapter in the
TMS320F2803x Technical Reference Manual.
Figure 6-33 shows the SCI module block diagram.
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TXENA
SCICTL1.1
TXSHF
Register
SCITXD
Frame
Format and Mode
8
Parity
Even/Odd
TXEMPTY
SCICTL2.6
0
1
SCICCR.6
8
Enable
TX FIFO_0
TX FIFO_1
TXINT
To CPU
SCICCR.5
TX Interrupt
Logic
TX FIFO Interrupts
8
TX FIFO_N
TXINTENA
SCICTL2.0
TXRDY
8
1
0
TXWAKE
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB
Registers
SCICTL1.0
LSPCLK
RXSHF
Register
SCIRXD
SCIHBAUD.15-8
SCILBAUD.7-0
RXWAKE
8
SCIRXST.1
0
1
8
SCIFFENA
SCITXFF.14
RX FIFO_0
RX FIFO_1
RXINT
To CPU
8
RX FIFO Interrupts
RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8
1
SCIFFRX.15
0
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
RXERRINTENA
SCICTL1.6
SCICTL1.0
SCIRXST.5
SCI RX Interrupt Select Logic
8
SCIRXST.5-2
BRKDT FE OE PE
RXERROR
Receive Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.7
Figure 6-33. Serial Communications Interface (SCI) Module Block Diagram
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6.9.6 Local Interconnect Network (LIN)
The device contains one LIN controller. The LIN standard is based on the SCI (UART) serial data link
format. The LIN module can be configured to work as a SCI as well.
The LIN module has the following features:
•
•
•
•
•
Compatible to LIN 1.3 or 2.0 protocols
Two external pins: LINRX and LINTX
Multibuffered receive and transmit units
Identification masks for message filtering
Automatic master header generation
–
–
–
Programmable sync break field
Sync field
Identifier field
•
Slave automatic synchronization
–
–
–
Sync break detection
Optional baudrate update
Synchronization validation
•
•
•
231 programmable transmission rates with 7 fractional bits
Wakeup on LINRX dominant level from transceiver
Automatic wakeup support
–
–
Wakeup signal generation
Expiration times on wakeup signals
•
•
Automatic bus idle detection
Error detection
–
–
–
–
–
–
Bit error
Bus error
No-response error
Checksum error
Sync field error
Parity error
•
2 Interrupt lines with priority encoding for:
–
–
–
Receive
Transmit
ID, error and status
NOTE
The 2803x devices have passed LIN 2.0 conformance tests (master and slave). Contact TI
for details.
For more information on the LIN, see the Local Interconnect Network (LIN) Module chapter in the
TMS320F2803x Technical Reference Manual.
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The registers in Table 6-42 configure and control the operation of the LIN module.
Table 6-42. LIN-A Registers(1)
NAME
ADDRESS
0x6C00
0x6C02
0x6C04
0x6C06
0x6C08
0x6C0A
0x6C0C
0x6C0E
0x6C10
0x6C12
0x6C14
0x6C16
0x6C18
0x6C1A
0x6C1C
0x6C1E
0x6C22
0x6C24
0x6C30
0x6C32
0x6C34
0x6C36
SIZE (x16)
DESCRIPTION
Global Control Register 0
Global Control Register 1
SCIGCR0
SCIGCR1
SCIGCR2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
10
2
2
2
2
Global Control Register 2
Interrupt Enable Register
Interrupt Disable Register
Set Interrupt Level Register
Clear Interrupt Level Register
Flag Register
SCISETINT
SCICLEARINT
SCISETINTLVL
SCICLEARINTLVL
SCIFLR
SCIINTVECT0
SCIINTVECT1
SCIFORMAT
BRSR
Interrupt Vector Offset Register 0
Interrupt Vector Offset Register 1
Length Control register
Baud Rate Selection Register
Emulation buffer register
Receiver data buffer register
Transmit data buffer register
RSVD
SCIED
SCIRD
SCITD
Reserved
SIPIO2
Pin control register 2
Reserved
LINCOMP
LINRD0
RSVD
Compare register
Receive data register 0
Receive data register 1
Acceptance mask register
LINRD1
LINMASK
Register containing ID- byte, ID-SlaveTask byte, and ID
received fields.
LINID
0x6C38
2
LINTD0
0x6C3A
0x6C3C
0x6C3E
0x6C40
0x6C48
2
2
2
8
2
Transmit Data Register 0
Transmit Data Register 1
Baud Rate Selection Register
RSVD
LINTD1
MBRSR
Reserved
IODFTCTRL
IODFT for BLIN
(1) Some registers and some bits in other registers are EALLOW-protected. For more details, see the Local Interconnect Network (LIN)
Module chapter in the TMS320F2803x Technical Reference Manual.
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Figure 6-34 shows the LIN module block diagram.
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
CHECKSUM
CALCULATOR
INTERFACE
ID PARTY
CHECKER
BIT
MONITOR
TXRX ERROR
DETECTOR (TED)
TIMEOUT
CONTROL
COUNTER
COMPARE
LINRX/
SCIRX
LINTX/
SCITX
MASK
FILTER
8 RECEIVE
BUFFERS
FSM
8 TRANSMIT
BUFFERS
SYNCHRONIZER
Figure 6-34. LIN Block Diagram
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6.9.7 Enhanced Controller Area Network (eCAN) Module
The CAN module (eCAN-A) has the following features:
•
•
•
Fully compliant with ISO11898-1 (CAN 2.0B)
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
–
–
–
–
–
–
–
–
–
–
Configurable as receive or transmit
Configurable with standard or extended identifier
Has a programmable receive mask
Supports data and remote frame
Composed of 0 to 8 bytes of data
Uses a 32-bit time stamp on receive and transmit message
Protects against reception of new message
Holds the dynamically programmable priority of transmit message
Employs a programmable interrupt scheme with two interrupt levels
Employs a programmable alarm on transmission or reception time-out
•
•
•
•
•
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction
with mailbox 16)
•
Self-test mode
–
Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,
thereby eliminating the need for another node to provide the acknowledge bit.
NOTE
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps.
The F2803x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
For information on using the CAN module with the on-chip zero-pin oscillators, see MCU CAN Module
Operation Using the On-Chip Zero-Pin Oscillator.
For more information on the CAN, see the Controller Area Network (CAN) chapter in the TMS320F2803x
Technical Reference Manual.
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eCAN0INT
eCAN1INT
Controls Address
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 ´ 32-Bit Words
Message Objects Control
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 6-35. eCAN Block Diagram and Interface Circuit
Table 6-43. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
SN65HVD234
SN65HVD235
ISO1050
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3–5.5 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 105°C
–
Yes
–
Sleep
Yes
–
None
None
None
None
None
None
None
–
None
None
–
Standby
Standby and Sleep
Standby
None
Adjustable
Adjustable
Adjustable
None
Diagnostic Loopback
–
Autobaud Loopback
Built-in Isolation
Low Prop Delay
Thermal Shutdown
Failsafe Operation
Dominant Time-Out
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eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
Control and Status Registers
6000h
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
603Fh
6040h
Local Acceptance Masks (LAM)
(32 ´ 32-Bit RAM)
607Fh
6080h
Master Control - CANMC
Message Object Time Stamps (MOTS)
(32 ´ 32-Bit RAM)
Bit-Timing Configuration - CANBTC
60BFh
60C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 ´ 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
60FFh
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
6108h-610Fh
6110h-6117h
6118h-611Fh
6120h-6127h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
61E8h-61EFh
61F0h-61F7h
61F8h-61FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
61E8h-61E9h
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
Figure 6-36. eCAN-A Memory Map
NOTE
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,
and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be
enabled for this.
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The CAN registers listed in Table 6-44 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 6-44. CAN Register Map(1)
eCAN-A
REGISTER NAME
CANME
SIZE (x32)
DESCRIPTION
ADDRESS
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
CANMD
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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6.9.8 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 6-37 shows how the I2C peripheral module interfaces
within the device.
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
–
–
–
–
–
–
–
–
Support for 1-bit to 8-bit format transfers
7-bit and 10-bit addressing modes
General call
START byte mode
Support for multiple master-transmitters and slave-receivers
Support for multiple slave-transmitters and master-receivers
Combined master transmit/receive and receive/transmit mode
Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
•
•
One 4-word receive FIFO and one 4-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
–
–
–
–
–
–
–
Transmit-data ready
Receive-data ready
Register-access ready
No-acknowledgment received
Arbitration lost
Stop condition detected
Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
For more information on the I2C, see the Inter-Integrated Circuit Module (I2C) chapter in the
TMS320F2803x Technical Reference Manual.
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I2C Module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
SDA
Peripheral Bus
I2CRSR
I2CDRR
Control/Status
Registers
CPU
Clock
Synchronizer
SCL
Prescaler
Noise Filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are
also at the SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power
operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 6-37. I2C Peripheral Module Interfaces
The registers in Table 6-45 configure and control the I2C port operation.
Table 6-45. I2C-A Registers
EALLOW
PROTECTED
NAME
ADDRESS
DESCRIPTION
I2C own address register
I2COAR
I2CIER
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
–
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
–
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6.9.8.1 I2C Electrical Data/Timing
Table 6-46 shows the I2C timing requirements. Table 6-47 shows the I2C switching characteristics.
Table 6-46. I2C Timing Requirements
MIN
MAX
UNIT
Hold time, START condition, SCL fall delay
after SDA fall
th(SDA-SCL)START
tsu(SCL-SDA)START
0.6
µs
Setup time, Repeated START, SCL rise before
SDA fall delay
0.6
µs
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
ns
ns
ns
ns
Input tolerance
Input tolerance
Input tolerance
Input tolerance
300
300
300
300
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before
SDA rise delay
tsu(SCL-SDA)STOP
0.6
µs
Table 6-47. I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
400
UNIT
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
fSCL
SCL clock frequency
kHz
Vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
Low level output voltage
3-mA sink current
0.4
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
tLOW
Low period of SCL clock
High period of SCL clock
1.3
μs
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
tHIGH
0.6
μs
Input current with an input voltage from
0.1 VDDIO to 0.9 VDDIO MAX
lI
–10
10
μA
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6.9.9 Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
The devices contain up to seven enhanced PWM Modules (ePWM). Figure 6-38 shows a block diagram of
multiple ePWM modules. Figure 6-39 shows the signal interconnections with the ePWM. For more details,
see the Enhanced Pulse Width Modulator (ePWM) chapter in the TMS320F2803x Technical Reference
Manual.
Table 6-48 and Table 6-49 show the complete ePWM register set per module.
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SPRS584N –APRIL 2009–REVISED JUNE 2020
EPWMSYNCI
EPWM1SYNCI
EPWM1B
EPWM1TZINT
EPWM1INT
EPWM1
Module
TZ1 to TZ3
EQEP1ERR(A)
CLOCKFAIL
EMUSTOP
EPWM2TZINT
EPWM2INT
TZ4
TZ5
TZ6
PIE
EPWMxTZINT
EPWMxINT
EPWM1ENCLK
TBCLKSYNC
eCAPI
EPWM1SYNCO
EPWM2SYNCI
EPWM1SYNCO
TZ1 to TZ3
COMPOUT1
COMPOUT2
EPWM2B
EPWM2
Module
EQEP1ERR(A)
CLOCKFAIL
EMUSTOP
COMP
EPWM1A
EPWM2A
TZ4
TZ5
TZ6
H
R
P
W
M
EPWM2ENCLK
TBCLKSYNC
EPWMxA
G
P
I
EPWM2SYNCO
O
M
U
X
SOCA1
SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
ADC
EPWMxB
EPWMxSYNCI
TZ1 to TZ3
EPWMx
Module
EQEP1ERR(A)
CLOCKFAIL
EMUSTOP
EQEP1ERR
TZ4
TZ5
TZ6
eQEP1
EPWMxENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2
SPCAx
ADCSOCAO
ADCSOCBO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2
SPCBx
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
Copyright © 2017, Texas Instruments Incorporated
A. This signal exists only on devices with an eQEP1 module.
Figure 6-38. ePWM
Copyright © 2009–2020, Texas Instruments Incorporated
Detailed Description
117
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Table 6-48. ePWM1–ePWM4 Control and Status Registers
SIZE (x16) /
#SHADOW
NAME
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
Time Base Control Register
TBCTL
TBSTS
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6806
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6811
0x6812
0x6813
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6846
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6851
0x6852
0x6853
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6886
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x6891
0x6892
0x6893
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C6
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
0x68D1
0x68D2
0x98D3
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Time Base Status Register
TBPHSHR
TBPHS
TBCTR
TBPRD
TBPRDHR
CMPCTL
CMPAHR
CMPA
Time Base Phase HRPWM Register
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Time Base Period High Resolution Register(1)
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
CMPB
Counter Compare B Register Set
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
DBRED
DBFED
TZSEL
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register(1)
TZDCSEL
TZCTL
Trip Zone Digital Compare Register
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
TZEINT
TZFLG
(1)
Trip Zone Flag Register
TZCLR
Trip Zone Clear Register(1)
TZFRC
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETSEL
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
(1) Registers that are EALLOW protected.
118 Detailed Description
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SPRS584N –APRIL 2009–REVISED JUNE 2020
Table 6-48. ePWM1–ePWM4 Control and Status Registers (continued)
SIZE (x16) /
#SHADOW
NAME
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
HRPWR
0x6821
0x6826
0x6828
0x682A
0x682B
0x682C
0x682D
0x6830
0x6831
0x6832
0x6833
0x6834
0x6835
0x6836
0x6837
0x6838
0x6839
-
-
-
1 / 0
1 / 0
HRPWM Power Register
HRMSTEP
HRPCTL
-
-
-
HRPWM MEP Step Register
0x6868
0x686A
0x686B
0x686C
0x686D
0x6870
0x6871
0x6872
0x6873
0x6874
0x6875
0x6876
0x6877
0x6878
0x6879
0x68A8
0x68AA
0x68AB
0x68AC
0x68AD
0x68B0
0x68B1
0x68B2
0x68B3
0x68B4
0x68B5
0x68B6
0x68B7
0x68B8
0x68B9
0x68E8
0x68EA
0x68EB
0x68EC
0x68ED
0x68F0
0x68F1
0x68F2
0x68F3
0x68F4
0x68F5
0x68F6
0x68F7
0x68F8
0x68F9
1 / 0
High resolution Period Control Register(1)
Time Base Period HRPWM Register Mirror
Time Base Period Register Mirror
Compare A HRPWM Register Mirror
Compare A Register Mirror
TBPRDHRM
TBPRDM
1 / W(2)
1 / W(2)
1 / W(2)
1 / W(2)
1 / 0
CMPAHRM
CMPAM
(1)
DCTRIPSEL
DCACTL
Digital Compare Trip Select Register
Digital Compare A Control Register(1)
Digital Compare B Control Register(1)
Digital Compare Filter Control Register(1)
Digital Compare Capture Control Register(1)
Digital Compare Filter Offset Register
1 / 0
DCBCTL
1 / 0
DCFCTL
1 / 0
DCCAPCT
DCFOFFSET
DCFOFFSETCNT
DCFWINDOW
DCFWINDOWCNT
DCCAP
1 / 0
1 / 1
1 / 0
Digital Compare Filter Offset Counter Register
Digital Compare Filter Window Register
Digital Compare Filter Window Counter Register
Digital Compare Counter Capture Register
1 / 0
1 / 0
1 / 1
(2) W = Write to shadow register
Table 6-49. ePWM5–ePWM7 Control and Status Registers
SIZE (x16) /
#SHADOW
NAME
ePWM5
ePWM6
ePWM7
DESCRIPTION
TBCTL
0x6900
0x6901
0x6902
0x6903
0x6904
0x6905
0x6906
0x6907
0x6908
0x6909
0x6940
0x6941
0x6942
0x6943
0x6944
0x6945
0x6946
0x6947
0x6948
0x6949
0x6980
0x6981
0x6982
0x6983
0x6984
0x6985
0x6986
0x6987
0x6988
0x6989
1 / 0
Time Base Control Register
Time Base Status Register
TBSTS
1 / 0
TBPHSHR
TBPHS
1 / 0
Time Base Phase HRPWM Register
Time Base Phase Register
1 / 0
TBCTR
1 / 0
Time Base Counter Register
TBPRD
1 / 1
Time Base Period Register Set
TBPRDHR
CMPCTL
CMPAHR
CMPA
1 / 1
Time Base Period High Resolution Register(1)
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
1 / 0
1 / 1
1 / 1
(1) Registers that are EALLOW protected.
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Detailed Description
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Table 6-49. ePWM5–ePWM7 Control and Status Registers (continued)
SIZE (x16) /
#SHADOW
NAME
ePWM5
ePWM6
ePWM7
DESCRIPTION
CMPB
0x690A
0x690B
0x690C
0x690D
0x690E
0x690F
0x6910
0x6911
0x6912
0x6913
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6920
-
0x694A
0x694B
0x694C
0x694D
0x694E
0x694F
0x6950
0x6951
0x6952
0x6953
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
0x6960
-
0x698A
0x698B
0x698C
0x698D
0x698E
0x698F
0x6990
0x6991
0x6992
0x6993
0x6994
0x6995
0x6996
0x6997
0x6998
0x6999
0x699A
0x699B
0x699C
0x699D
0x699E
0x69A0
-
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / W(2)
1 / W(2)
1 / W(2)
1 / W(2)
1 / 0
1 / 0
1 / 0
Counter Compare B Register Set
AQCTLA
AQCTLB
AQSFRC
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay Count Register
Dead-Band Generator Falling Edge Delay Count Register
Trip Zone Select Register(1)
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
TZDCSEL
TZCTL
Trip Zone Digital Compare Register
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
TZEINT
TZFLG
(1)
Trip Zone Flag Register
TZCLR
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
TZFRC
ETSEL
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
ETPS
ETFLG
ETCLR
Event Trigger Clear Register
ETFRC
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
HRPWM Power Register
PCCTL
HRCNFG
HRPWR
HRMSTEP
HRPCTL
TBPRDHRM
TBPRDM
CMPAHRM
CMPAM
DCTRIPSEL
DCACTL
DCBCTL
-
-
-
HRPWM MEP Step Register
0x6928
0x692A
0x692B
0x692C
0x692D
0x6930
0x6931
0x6932
0x6968
0x696A
0x696B
0x696C
0x696D
0x6970
0x6971
0x6972
0x69A8
0x69AA
0x69AB
0x69AC
0x69AD
0x69B0
0x69B1
0x69B2
High resolution Period Control Register(1)
Time Base Period HRPWM Register Mirror
Time Base Period Register Mirror
Compare A HRPWM Register Mirror
Compare A Register Mirror
(1)
Digital Compare Trip Select Register
Digital Compare A Control Register(1)
Digital Compare B Control Register(1)
(2) W = Write to shadow register
120
Detailed Description
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SPRS584N –APRIL 2009–REVISED JUNE 2020
Table 6-49. ePWM5–ePWM7 Control and Status Registers (continued)
SIZE (x16) /
#SHADOW
NAME
ePWM5
ePWM6
ePWM7
DESCRIPTION
DCFCTL
0x6933
0x6934
0x6935
0x6936
0x6937
0x6938
0x6939
0x6973
0x6974
0x6975
0x6976
0x6977
0x6978
0x6979
0x69B3
0x69B4
0x69B5
0x69B6
0x69B7
0x69B8
0x69B9
1 / 0
1 / 0
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
Digital Compare Filter Control Register(1)
Digital Compare Capture Control Register(1)
Digital Compare Filter Offset Register
DCCAPCT
DCFOFFSET
DCFOFFSETCNT
DCFWINDOW
DCFWINDOWCNT
DCCAP
Digital Compare Filter Offset Counter Register
Digital Compare Filter Window Register
Digital Compare Filter Window Counter Register
Digital Compare Counter Capture Register
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Time-Base (TB)
CTR=ZERO
Sync
In/Out
Select
Mux
TBPRD Shadow (24)
EPWMxSYNCO
CTR=CMPB
Disabled
TBPRDHR (8)
TBPRD Active (24)
8
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
Counter
Up/Down
(16 Bit)
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=ZERO
TCBNT
Active (16)
CTR_Dir
CTR=PRD
CTR=ZERO
TBPHSHR (8)
EPWMxINT
CTR=PRD or ZERO
CTR=CMPA
Event
Trigger
and
Interrupt
(ET)
16
8
EPWMxSOCA
Phase
Control
CTR=CMPB
CTR_Dir
(A)
DCAEVT1.soc
(A)
TBPHS Active (24)
EPWMxSOCB
EPWMxSOCA
ADC
DCBEVT1.soc
EPWMxSOCB
Action
Qualifier
(AQ)
CTR=CMPA
CMPAHR (8)
16
High-resolution PWM (HRPWM)
CMPA Active (24)
CMPA Shadow (24)
EPWMxA
EPWMA
EPWMB
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
16
EPWMxB
EPWMxTZINT
TZ1 to TZ3
EMUSTOP
CMPB Active (16)
CMPB Shadow (16)
CLOCKFAIL
(B)
EQEP1ERR
CTR=ZERO
DCAEVT1.inter
DCBEVT1.inter
(A)
(A)
(A)
(A)
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force
DCBEVT2.force
DCAEVT2.inter
DCBEVT2.inter
A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of
the COMPxOUT and TZ signals.
B. This signal exists only on devices with an eQEP1 module.
Figure 6-39. ePWM Submodules Showing Critical Internal Signal Interconnections
122
Detailed Description
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SPRS584N –APRIL 2009–REVISED JUNE 2020
6.9.9.1 ePWM Electrical Data/Timing
PWM refers to PWM outputs on ePWM1–7. Table 6-50 shows the PWM timing requirements and Table 6-
51, switching characteristics.
Table 6-50. ePWM Timing Requirements(1)
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
Asynchronous
Synchronous
tw(SYCIN)
Sync input pulse width
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-68.
Table 6-51. ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
33.33
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SCO)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(PWM)tza
no pin load
25
20
ns
ns
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
6.9.9.2 Trip-Zone Input Timing
Table 6-52. Trip-Zone Input Timing Requirements(1)
MIN
2tc(TBCLK)
MAX UNIT
cycles
Asynchronous
tw(TZ)
Pulse duration, TZx input low
Synchronous
2tc(TBCLK)
cycles
With input qualifier
2tc(TBCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-68.
SYSCLK
tw(TZ)
TZ(A)
td(TZ-PWM)HZ
PWM(B)
A. TZ - TZ1, TZ2, TZ3 , TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-40. PWM Hi-Z Characteristics
Copyright © 2009–2020, Texas Instruments Incorporated
Detailed Description
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6.9.10 High-Resolution PWM (HRPWM)
This module combines multiple delay lines in a single module and a simplified calibration system by using
a dedicated calibration delay line. For each ePWM module there is one HR delay line.
The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual
edge control for frequency/period modulation.
•
•
Finer time granularity control or edge positioning is controlled through extensions to the Compare A
and Phase registers of the ePWM module.
HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an
ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.
NOTE
The minimum SYSCLKOUT frequency allowed for HRPWM is 60 MHz.
NOTE
When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output
is not available for use.
For more information on the HRPWM, see the High-Resolution Pulse Width Modulator (HRPWM) chapter
in the TMS320F2803x Technical Reference Manual.
6.9.10.1 HRPWM Electrical Data/Timing
Table 6-53 shows the high-resolution PWM switching characteristics.
Table 6-53. High-Resolution PWM Characteristics(1)
PARAMETER
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(2)
150
(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 60 MHz.
(2) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
124
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6.9.11 Enhanced Capture Module (eCAP1)
The device contains an enhanced capture (eCAP) module. Figure 6-41 shows a functional block diagram
of a module.
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Prescale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
CEVT[1:4]
4
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Copyright © 2017, Texas Instruments Incorporated
Figure 6-41. eCAP Functional Block Diagram
The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for
low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
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Table 6-54. eCAP Control and Status Registers
NAME
TSCTR
eCAP1
0x6A00
SIZE (x16) EALLOW PROTECTED
DESCRIPTION
Time-Stamp Counter
2
2
2
2
2
2
8
1
1
1
1
1
1
6
CTRPHS
CAP1
0x6A02
Counter Phase Offset Value Register
Capture 1 Register
0x6A04
CAP2
0x6A06
Capture 2 Register
CAP3
0x6A08
Capture 3 Register
CAP4
0x6A0A
Capture 4 Register
Reserved
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
Reserved
0x6A0C to 0x6A12
0x6A14
Reserved
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
Reserved
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A1A to 0x6A1F
For more information on the eCAP, see the Enhanced Capture (eCAP) Module chapter in the
TMS320F2803x Technical Reference Manual.
6.9.11.1 eCAP Electrical Data/Timing
Table 6-55 shows the eCAP timing requirement and Table 6-56 shows the eCAP switching characteristics.
Table 6-55. Enhanced Capture (eCAP) Timing Requirement(1)
MIN
2tc(SCO)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-68.
Table 6-56. eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
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6.9.12 High-Resolution Capture (HRCAP) Module
The High-Resolution Capture (HRCAP) module measures the difference between external pulses with a
typical resolution of 300 ps.
Uses for the HRCAP include:
•
•
•
•
•
•
Capactive touch applications
High-resolution period and duty cycle measurements of pulse train cycles
Instantaneous speed measurements
Instantaneous frequency measurements
Voltage measurements across an isolation boundary
Distance/sonar measurement and scanning
The HRCAP module features include:
•
•
•
•
•
•
•
•
Pulse width capture in either non-high-resolution or high-resolution modes
Difference (Delta) mode pulse width capture
Typical high-resolution capture on the order of 300 ps resolution on each edge
Interrupt on either falling or rising edge
Continuous mode capture of pulse widths in 2-deep buffer
Calibration logic for precision high-resolution capture
All of the above resources are dedicated to a single input pin
HRCAP calibration software library supplied by TI is used for both calibration and calculating fractional
pulse widths
The HRCAP module includes one capture channel in addition to a high-resolution calibration block, which
connects internally to the last available ePWMxA HRPWM channel when calibrating (that is, if there are
eight ePWMs with HRPWM capability, it will be HRPWM8A).
Each HRCAP channel has the following independent key resources:
•
•
Dedicated input capture pin
16-bit HRCAP clock which is either equal to the PLL output frequency (asynchronous to SYSCLK) or
equal to the SYSCLK frequency (synchronous to SYSCLK)
•
High-resolution pulse width capture in a 2-deep buffer
HRCAP Calibration Logic
EPWMx
EPWMxA
HRPWM
HRCAPxENCLK
SYSCLK
HRCAPx
Module
GPIO
Mux
PLLCLK
HRCAP Calibration Signal (Internal)
PIE
HRCAPxINTn
HRCAPx
Figure 6-42. HRCAP Functional Block Diagram
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Table 6-57. HRCAP Registers
NAME
HRCAP1
0x6AC0
0x6AC1
0x6AC2
0x6AC3
0x6AC4
0x6AD0
0x6AD2
0x6AD8
0x6ADA
HRCAP2
0x6AE0
0x6AE1
0x6AE2
0x6AE3
0x6AE4
0x6AF0
0x6AF2
0x6AF8
0x6AFA
SIZE (x16)
DESCRIPTION
HRCAP Control Register(1)
HCCTL
HCIFR
1
1
1
1
1
1
1
1
1
HRCAP Interrupt Flag Register
HRCAP Interrupt Clear Register
HRCAP Interrupt Force Register
HRCAP 16-bit Counter Register
HCICLR
HCIFRC
HCCOUNTER
HCCAPCNTRISE0
HCCAPCNTFALL0
HCCAPCNTRISE1
HCCAPCNTFALL1
HRCAP Capture Counter on Rising Edge 0 Register
HRCAP Capture Counter on Falling Edge 0 Register
HRCAP Capture Counter on Rising Edge 1 Register
HRCAP Capture Counter on Falling Edge 1 Register
(1) Registers that are EALLOW-protected.
For more information on the HRCAP, see the High Resolution Capture (HRCAP) chapter in the
TMS320F2803x Technical Reference Manual.
6.9.12.1 HRCAP Electrical Data/Timing
Table 6-58. High-Resolution Capture (HRCAP) Timing Requirements
MIN
NOM
MAX UNIT
tc(HCCAPCLK)
tw(HRCAP)
Cycle time, HRCAP capture clock
Pulse width, HRCAP capture
HRCAP step size(2)
8.333
10.204
ns
ns
ps
(1)
7tc(HCCAPCLK)
300
(1) The listed minimum pulse width does not take into account the limitation that all relevant HCCAP registers must be read and RISE/FALL
event flags cleared within the pulse width to ensure valid capture data.
(2) HRCAP step size will increase with low voltage and high temperature and decrease with high voltage and low temperature. Applications
that use the HRCAP in high-resolution mode should use the HRCAP calibration functions to dynamically calibrate for varying operating
conditions.
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6.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
The device contains one enhanced quadrature encoder pulse (eQEP) module.
Table 6-59. eQEP Control and Status Registers
eQEP1
eQEP1
ADDRESS
NAME
QPOSCNT
SIZE(x16)/
#SHADOW
REGISTER DESCRIPTION
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
eQEP Position Counter
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
0x6B21 –
0x6B3F
Reserved
31/0
For more information on the eQEP, see the Enhanced QEP (eQEP) Module chapter in the
TMS320F2803x Technical Reference Manual.
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Figure 6-43 shows the eQEP functional block diagram.
System Control
Registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCTMR
QCAPCTL
16
16
16
Quadrature
Capture
Unit
QCTMRLAT
QCPRDLAT
(QCAP)
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
16
PIE
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
eQEP Peripheral
Copyright © 2017, Texas Instruments Incorporated
Figure 6-43. eQEP Functional Block Diagram
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6.9.13.1 eQEP Electrical Data/Timing
Table 6-60 shows the eQEP timing requirement and Table 6-61 shows the eQEP switching
characteristics.
Table 6-60. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements(1)
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
tw(QEPP)
QEP input period
2[1tc(SCO) + tw(IQSW)
]
Asynchronous(2)/synchronous
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
Asynchronous(2)/synchronous
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-68.
(2) Refer to the TMS320F2803x MCUs Silicon Errata for limitations in the asynchronous mode.
Table 6-61. eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
4tc(SCO)
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
cycles
Delay time, QEP input edge to position compare sync
output
td(PCS-OUT)QEP
6tc(SCO)
cycles
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6.9.14 JTAG Port
On the 2803x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS
and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the
pins in Figure 6-44. During emulation/debug, the GPIO function of these pins are not available. If the
GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used
to clock the device during emulation/debug because this pin will be needed for the TCK function.
NOTE
In 2803x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in
the board design to ensure that the circuitry connected to these pins do not affect the
emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should
not prevent the JTAG debug probe from driving (or being driven by) the JTAG pins for
successful debug.
TRST = 0: JTAG Disabled (GPIO Mode)
TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
GPIO38_out
C28x
Core
GPIO37_in
TDO
TDO/GPIO37
1
0
GPIO37_out
GPIO36_in
1
0
TMS
TMS/GPIO36
TDI/GPIO35
1
GPIO36_out
GPIO35_in
1
0
TDI
1
GPIO35_out
Figure 6-44. JTAG/GPIO Multiplexing
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6.9.15 General-Purpose Input/Output (GPIO) MUX
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition
to providing individual pin bit-banging I/O capability.
The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral
Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-62 shows the
GPIO register mapping.
Table 6-62. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control Register (GPIO0 to 31)
SIZE (x16)
DESCRIPTION
GPACTRL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
0x6F90
0x6F92
0x6F96
0x6F9A
0x6F9C
0x6FB6
0x6FBA
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pullup Disable Register (GPIO0 to 31)
GPIO B Control Register (GPIO32 to 44)
GPIO B Qualifier Select 1 Register (GPIO32 to 44)
GPIO B MUX 1 Register (GPIO32 to 44)
GPAPUD
GPBCTRL
GPBQSEL1
GPBMUX1
GPBDIR
GPIO B Direction Register (GPIO32 to 44)
GPIO B Pullup Disable Register (GPIO32 to 44)
Analog, I/O mux 1 register (AIO0 to AIO15)
Analog, I/O Direction Register (AIO0 to AIO15)
GPBPUD
AIOMUX1
AIODIR
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
0x6FD8
0x6FDA
0x6FDC
0x6FDE
2
2
2
2
2
2
2
2
2
2
2
2
GPIO A Data Register (GPIO0 to 31)
GPASET
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 44)
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPIO B Data Set Register (GPIO32 to 44)
GPIO B Data Clear Register (GPIO32 to 44)
GPIO B Data Toggle Register (GPIO32 to 44)
Analog I/O Data Register (AIO0 to AIO15)
Analog I/O Data Set Register (AIO0 to AIO15)
Analog I/O Data Clear Register (AIO0 to AIO15)
Analog I/O Data Toggle Register (AIO0 to AIO15)
GPBCLEAR
GPBTOGGLE
AIODAT
AIOSET
AIOCLEAR
AIOTOGGLE
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLPMSEL
0x6FE0
0x6FE1
0x6FE2
0x6FE8
1
1
1
2
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO0 to 31)
LPM GPIO Select Register (GPIO0 to 31)
NOTE
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn
and GPxQSELn registers occurs to when the action is valid.
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Table 6-63. GPIOA MUX(1) (2)
DEFAULT AT RESET
PRIMARY I/O
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
FUNCTION
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 BITS = 11)
1-0
GPIO0
GPIO1
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
Reserved
Reserved
Reserved
COMP1OUT (O)
Reserved
3-2
5-4
GPIO2
Reserved
7-6
GPIO3
SPISOMIA (I/O)
Reserved
COMP2OUT (O)
Reserved
9-8
GPIO4
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO5
SPISIMOA (I/O)
EPWMSYNCI (I)
SCIRXDA (I)
Reserved
ECAP1 (I/O)
GPIO6
EPWMSYNCO (O)
Reserved
GPIO7
GPIO8
ADCSOCAO (O)
HRCAP1 (I)
GPIO9
LINTXA (O)
Reserved
GPIO10
GPIO11
GPIO12
GPIO13(3)
GPIO14(3)
GPIO15(3)
ADCSOCBO (O)
HRCAP2 (I)
LINRXA (I)
SCITXDA (O)
Reserved
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ2 (I)
TZ3 (I)
LINTXA (O)
LINRXA (I)
TZ1 (I)
GPAMUX2 REGISTER
BITS
(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01)
(GPAMUX2 BITS = 10)
(GPAMUX2 BITS = 11)
1-0
GPIO16
GPIO17
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
Reserved
Reserved
LINTXA (O)
LINRXA (I)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDAA (I/OD)
SCLA (I/OD)
Reserved
Reserved
TZ2 (I)
TZ3 (I)
3-2
5-4
GPIO18
XCLKOUT (O)
ECAP1 (I/O)
COMP1OUT (O)
COMP2OUT (O)
LINTXA (O)
LINRXA (I)
7-6
GPIO19/XCLKIN
GPIO20
9-8
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
GPIO21
EQEP1B (I)
GPIO22
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
Reserved
GPIO23
GPIO24
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ2 (I)
GPIO25(3)
GPIO26(3)
GPIO27(3)
GPIO28
HRCAP1 (I)
HRCAP2 (I)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
CANTXA (O)
GPIO29
TZ3 (I)
GPIO30
Reserved
GPIO31
Reserved
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the
pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(2) I = Input, O = Output, OD = Open Drain
(3) These pins are not available in the 64-pin package.
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SPRS584N –APRIL 2009–REVISED JUNE 2020
Table 6-64. GPIOB MUX(1)
DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPBMUX1 REGISTER
BITS
(GPBMUX1 BITS = 00)
(GPBMUX1 BITS = 01)
(GPBMUX1 BITS = 10)
(GPBMUX1 BITS = 11)
1-0
GPIO32
GPIO33
SDAA (I/OD)
SCLA (I/OD)
COMP2OUT (O)
Reserved
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved
ADCSOCAO (O)
ADCSOCBO (O)
COMP3OUT (O)
Reserved
3-2
5-4
GPIO34
7-6
GPIO35 (TDI)
GPIO36 (TMS)
GPIO37 (TDO)
GPIO38/XCLKIN (TCK)
GPIO39(2)
Reserved
9-8
Reserved
Reserved
Reserved
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO40(2)
GPIO41(2)
GPIO42(2)
GPIO43(2)
EPWM7A (O)
EPWM7B (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
COMP1OUT (O)
COMP2OUT (O)
Reserved
Reserved
Reserved
GPIO44(2)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1) I = Input, O = Output, OD = Open Drain
(2) These pins are not available in the 64-pin package.
Table 6-65. Analog MUX for 80-Pin PN Package(1)
DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOx AND PERIPHERAL SELECTION 1
AIOMUX1 REGISTER BITS
AIOMUX1 BITS = 0,x
ADCINA0 (I)
ADCINA1 (I)
AIO2 (I/O)
AIOMUX1 BITS = 1,x
ADCINA0 (I)
1-0
3-2
ADCINA1 (I)
5-4
ADCINA2 (I), COMP1A (I)
ADCINA3 (I)
7-6
ADCINA3 (I)
AIO4 (I/O)
9-8
ADCINA4 (I), COMP2A (I)
ADCINA5 (I)
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
ADCINA5 (I)
AIO6 (I/O)
ADCINA6 (I), COMP3A (I)
ADCINA7 (I)
ADCINA7 (I)
ADCINB0 (I)
ADCINB1 (I)
AIO10 (I/O)
ADCINB3 (I)
AIO12 (I/O)
ADCINB5 (I)
AIO14 (I/O)
ADCINB7 (I)
ADCINB0 (I)
ADCINB1 (I)
ADCINB2 (I), COMP1B (I)
ADCINB3 (I)
ADCINB4 (I), COMP2B (I)
ADCINB5 (I)
ADCINB6 (I), COMP3B (I)
ADCINB7 (I)
(1) I = Input, O = Output
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Table 6-66. Analog MUX for 56-Pin RSH and 64-Pin PAG Packages(1)
DEFAULT AT RESET
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOx AND PERIPHERAL SELECTION 1
AIOMUX1 REGISTER BITS
AIOMUX1 BITS = 0,x
ADCINA0 (I), VREFHI (I)
ADCINA1 (I)
AIO2 (I/O)
AIOMUX1 BITS = 1,x
ADCINA0 (I), VREFHI (I)
ADCINA1 (I)
1-0
3-2
5-4
ADCINA2 (I), COMP1A (I)
ADCINA3 (I)
7-6
ADCINA3 (I)
AIO4 (I/O)
9-8
ADCINA4 (I), COMP2A (I)
–
11-10
13-12
15-14
17-16
19-18
21-20
23-22
25-24
27-26
29-28
31-30
–
AIO6 (I/O)
ADCINA6 (I), COMP3A (I)
ADCINA7 (I)
ADCINA7 (I)
ADCINB0 (I)
ADCINB1 (I)
AIO10 (I/O)
ADCINB3 (I)
AIO12 (I/O)
–
ADCINB0 (I)
ADCINB1 (I)
ADCINB2 (I), COMP1B (I)
ADCINB3 (I)
ADCINB4 (I), COMP2B (I)
–
AIO14 (I/O)
ADCINB7 (I)
ADCINB6 (I), COMP3B (I)
ADCINB7 (I)
(1) I = Input, O = Output
The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers
from four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,
after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles
before the input is allowed to change.
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The
sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL
samples are the same (all 0s or all 1s) as shown in Figure 6-47 (for 6 sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is
not required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the
input signal will default to either a 0 or 1 state, depending on the peripheral.
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GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
External Interrupt
PIE
MUX
Low-Power
Modes Block
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Input
Internal
Pullup
Qualification
Peripheral 2 Input
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. For pin-specific
variations, see the System Control chapter in the TMS320F2803x Technical Reference Manual.
Figure 6-45. GPIO Multiplexing
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6.9.15.1 GPIO Electrical Data/Timing
6.9.15.1.1 GPIO - Output Timing
Table 6-67. General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
13(1)
13(1)
15
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency
All GPIOs
All GPIOs
ns
MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-67 are applicable for a 40-pF load on I/O pins.
GPIO
t
r(GPO)
t
f(GPO)
Figure 6-46. General-Purpose Output Timing
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6.9.15.1.2 GPIO - Input Timing
Table 6-68. General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)
]
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value
"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO
pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure
5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-
wide pulse ensures reliable recognition.
Figure 6-47. Sampling Mode
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6.9.15.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of
the signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 6-48. General-Purpose Input Timing
VDDIO
> 1 MS
2 pF
VSS
VSS
Figure 6-49. Input Resistance Model for a GPIO Pin With an Internal Pullup
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6.9.15.1.4 Low-Power Mode Wakeup Timing
Table 6-69 shows the timing requirements, Table 6-70 shows the switching characteristics, and Figure 6-
50 shows the timing diagram for IDLE mode.
Table 6-69. IDLE Mode Timing Requirements(1)
MIN
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-68.
Table 6-70. IDLE Mode Switching Characteristics(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(2)
Delay time, external wake signal to program execution resume
cycles
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
•
Wake up from Flash
Flash module in active state
cycles
cycles
cycles
–
20tc(SCO) + tw(IQSW)
1050tc(SCO)
td(WAKE-IDLE)
•
Wake up from Flash
Flash module in sleep state
–
1050tc(SCO) + tw(IQSW)
20tc(SCO)
•
Wake up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-68.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
WAKE INT(A)(B)
A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5
OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-50. IDLE Entry and Exit Timing
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Table 6-71. STANDBY Mode Timing Requirements
MIN
3tc(OSCCLK)
MAX
UNIT
Without input qualification
With input qualification(1)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
Table 6-72. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal to program execution
resume(1)
cycles
cycles
Without input qualifier
100tc(SCO)
•
Wake up from flash
–
Flash module in active state With input qualifier
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
td(WAKE-STBY)
Without input qualifier
•
Wake up from flash
cycles
cycles
–
Flash module in sleep state With input qualifier
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
Without input qualifier
•
Wake up from SARAM
With input qualifier
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
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(C)
(F)
(A)
(B)
(D)(E)
(G)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal(H)
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below
before being turned off:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in
STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the
wake-up signal could be asserted.
D. The external wake-up signal is driven active.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-51. STANDBY Entry and Exit Timing Diagram
Table 6-73. HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wake-up signal
Table 6-74. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
32tc(SCO)
45tc(SCO)
1
cycles
ms
Delay time, PLL lock to program execution resume
1125tc(SCO)
35tc(SCO)
cycles
cycles
•
•
Wake up from flash
Flash module in sleep state
td(WAKE-HALT)
–
Wake up from SARAM
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(C)
(F)
(A)
(H)
(B)
(G)
(D)(E)
Device
Status
HALT
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn(I)
t
)
d(WAKE−HALT
t
w(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before
oscillator is turned off and the CLKIN to the core is stopped:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as
the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes
absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the
watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register. After the IDLE
instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be
asserted.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator
wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This
enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin
asynchronously begins the wake-up procedure, care should be taken to maintain a low noise environment prior to
entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the
device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT
mode is now exited.
H. Normal operation resumes.
I.
From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-52. HALT Mode Wakeup Using GPIOn
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7 Applications, Implementation, and Layout
NOTE
Information in the following sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded
processor, and connectivity. Created by TI experts to help you jump start your system design, all
reference designs include schematic or block diagrams, BOMs, and design files to speed your time to
market. Search and download designs at the Select TI reference designs page.
Multiple Channels of High Density LED Control for Automotive Headlight Applications
This design, featuring the TMS320F2803x microcontroller, implements a high-efficiency, multichannel DC-
DC LED control system for typically automotive lighting systems. The design support up to six channels of
LED controls, each with a maximum of 1.2-A current driving capabilities. With a 2-stage power topology of
boost and buck, the system can be operated with a wide input DC voltage from 8 V to 20 V, which fits
perfectly in automotive applications.
Automotive Digitally Controlled Boost Power Supply
This TI reference design is an automotive voltage boost converter module. The purpose of this module is
to supply a steady voltage to vehicle electronics by boosting during voltage droop events such as engine
crank. The design is based on the C2000 Real-Time Microcontroller, and will provide up to 400 Watts of
power from a 12-V automotive battery system. This solution supports continuous operational input voltage
of 6 V to 16 V with protection against 36-V load dump to provide a stable 12-V output supply with reverse
battery protection.
Copyright © 2009–2020, Texas Instruments Incorporated
Applications, Implementation, and Layout
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TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
8 Device and Documentation Support
8.1 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of
three prefixes: TMX, TMP, or TMS (for example, TMS320F28032). Texas Instruments recommends two of
three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent
evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully
qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications
Final silicon die that conforms to the device's electrical specifications but has not
completed quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PN) and temperature range (for example, T). Figure 8-1 provides a legend for
reading the complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your
TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2803x MCUs
Silicon Errata.
146
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TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
TMS 320
F
28032
PN
T
PREFIX
TEMPERATURE RANGE
experimental device
prototype device
qualified device
TMX =
TMP =
TMS =
T
S
Q
−40°C to 105°C
−40°C to 125°C
=
=
=
−40°C to 125°C
(Q refers to AEC Q100 qualification for automotive applications.)
DEVICE FAMILY
PACKAGE TYPE
320 = TMS320 MCU Family
56-Pin RSH Very Thin Quad Flatpack (No Lead) (VQFN)
64-Pin PAG Thin Quad Flatpack (TQFP)
80-Pin PN Low-Profile Quad Flatpack (LQFP)
DEVICE
TECHNOLOGY
28035
28034
28033
28032
28031
28030
F = Flash
A. For more information on peripheral, temperature, and package availability for a specific device, see Table 3-1.
Figure 8-1. Device Nomenclature
8.2 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the
performance of the device, generate code, and develop solutions are listed below. To view all available
tools and software for C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design
& development page.
Development Tools
Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller
and Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build
environment, debugger, profiler, and many other features. The intuitive IDE provides a single user
interface taking you through each step of the application development flow. Familiar tools and interfaces
allow users to get started faster than ever before. CCS combines the advantages of the Eclipse software
framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich
development environment for embedded developers.
Software Tools
powerSUITE - Digital Power Supply Design Software Tools for C2000™ MCUs
powerSUITE is a suite of digital power supply design software tools for Texas Instruments' C2000 real-
time microcontroller (MCU) family. powerSUITE helps power supply engineers drastically reduce
development time as they design digitally-controlled power supplies based on C2000 real-time control
MCUs.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device
peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your
product.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or
scripting interface.
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Device and Documentation Support
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TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
Models
Various models are available for download from the product Tools & Software pages. These include I/O
Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models.
To view all available models, visit the Models section of the Tools & Software page for each device, which
can be found in Table 8-1.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and
performance, TI has developed a variety of training resources. Utilizing the online training materials and
downloadable hands-on workshops provides an easy means for gaining a complete working knowledge of
the C2000 microcontroller family. These training resources have been designed to decrease the learning
curve, while reducing development time, and accelerating product time to market. For more information on
the various training resources, visit the C2000™ real-time control MCUs – Support & training site.
Specific TMS320F2803x hands-on training resources can be found at C2000™ MCU Device Workshops.
148
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Submit Documentation Feedback
Product Folder Links: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034
TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
8.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the
upper right corner, click on Alert me to register and receive a weekly digest of any product information that
has changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral
is listed below.
Errata
TMS320F2803x MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
Technical Reference Manual
TMS320F2803x Technical Reference Manual details the integration, the environment, the functional
description, and the programming models for each peripheral and subsystem in the device.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and
the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It
also describes emulation features available on these DSPs.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the
28x digital signal processors (DSPs).
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language
tools (assembler and other tools used to develop assembly language code), assembler directives, macros,
common object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare
semiconductor devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful
lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at
general engineers who wish to determine if the reliability of the TI EP meets the end system reliability
requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts
their application in perspective with respect to system-level junction temperature estimation.
Calculating FIT for a Mission Profile explains how use TI’s reliability de-rating tools to calculate a
component level FIT under power on conditions for a system mission profile.
Oscillator Compensation Guide describes a factory supplied method for compensating the internal
oscillators for frequency drift caused by temperature.
MCU CAN Module Operation Using the On-Chip Zero-Pin Oscillator.
The TMS320F2803x/TMS320F2805x/TMS320F2806x series of microcontrollers have an on-chip zero-pin
oscillator that needs no external components. This application report describes how to use the CAN
module with this oscillator to operate at the maximum bit rate and bus length without the added cost of an
external clock source.
Copyright © 2009–2020, Texas Instruments Incorporated
Device and Documentation Support
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TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
SPRS584N –APRIL 2009–REVISED JUNE 2020
www.ti.com
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the
input/output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders
for serial programming a device.
8.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TMS320F28030
TMS320F28031
TMS320F28032
TMS320F28033
TMS320F28034
TMS320F28035
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
8.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help —
straight from the experts. Search existing answers or ask your own question to get the quick design help
you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications
and do not necessarily reflect TI's views; see TI's Terms of Use.
8.6 Trademarks
TMS320C2000, TMS320, TI E2E are trademarks of Texas Instruments.
I2C-bus is a registered trademark of NXP B.V. Corporation.
All other trademarks are the property of their respective owners.
8.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
150
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TMS320F28035
TMS320F28030, TMS320F28031, TMS320F28032
TMS320F28033, TMS320F28034, TMS320F28035
www.ti.com
SPRS584N –APRIL 2009–REVISED JUNE 2020
9 Mechanical, Packaging, and Orderable Information
9.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2020, Texas Instruments Incorporated
Mechanical, Packaging, and Orderable Information
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151
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TMS320F28035
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
PAG
PAG
PAG
PN
Qty
160
160
160
119
119
119
260
260
160
160
160
119
119
119
260
160
160
(1)
(2)
(3)
(4/5)
(6)
TMS320F28030PAGQ
TMS320F28030PAGS
TMS320F28030PAGT
TMS320F28030PNQ
TMS320F28030PNS
TMS320F28030PNT
TMS320F28030RSHS
TMS320F28030RSHT
TMS320F28031PAGQ
TMS320F28031PAGS
TMS320F28031PAGT
TMS320F28031PNQ
TMS320F28031PNS
TMS320F28031PNT
TMS320F28031RSHS
TMS320F28032PAGQ
TMS320F28032PAGS
ACTIVE
TQFP
TQFP
TQFP
LQFP
LQFP
LQFP
VQFN
VQFN
TQFP
TQFP
TQFP
LQFP
LQFP
LQFP
VQFN
TQFP
TQFP
64
64
64
80
80
80
56
56
64
64
64
80
80
80
56
64
64
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 125
F28030PAGQ
TMS320
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F28030PAGS
TMS320
F28030PAGT
TMS320
F28030PNQ
TMS320
PN
F28030PNS
TMS320
PN
F28030PNT
TMS320
RSH
RSH
PAG
PAG
PAG
PN
F28030RSHS
S320 980
F28030RSHT
S320 980
F28031PAGQ
TMS320
F28031PAGS
TMS320
F28031PAGT
TMS320
F28031PNQ
TMS320
PN
F28031PNS
TMS320
PN
F28031PNT
TMS320
RSH
PAG
PAG
F28031RSHS
S320 980
F28032PAGQ
TMS320
F28032PAGS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320
TMS320F28032PAGT
TMS320F28032PNQ
TMS320F28032PNS
TMS320F28032PNT
TMS320F28032PNTR
TMS320F28032RSHS
TMS320F28032RSHT
TMS320F28033P1PAGS
TMS320F28033PAGQ
TMS320F28033PAGS
TMS320F28033PAGT
TMS320F28033PNQ
TMS320F28033PNS
TMS320F28033PNT
TMS320F28033RSHS
TMS320F28033RSHT
TMS320F28034PAGQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TQFP
LQFP
LQFP
LQFP
LQFP
VQFN
VQFN
TQFP
TQFP
TQFP
TQFP
LQFP
LQFP
LQFP
VQFN
VQFN
TQFP
PAG
PN
64
80
80
80
80
56
56
64
64
64
64
80
80
80
56
56
64
160
119
119
119
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
F28032PAGT
TMS320
F28032PNQ
TMS320
PN
F28032PNS
TMS320
PN
F28032PNT
TMS320
PN
1000 RoHS & Green
F28032PNT
TMS320
RSH
RSH
PAG
PAG
PAG
PAG
PN
260
260
160
160
160
160
119
119
119
260
260
160
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
F28032RSHS
S320 980
F28032RSHT
S320 980
F28033PAGS
TMS320
F28033PAGQ
TMS320
F28033PAGS
TMS320
F28033PAGT
TMS320
F28033PNQ
TMS320
PN
F28033PNS
TMS320
PN
F28033PNT
TMS320
RSH
RSH
PAG
F28033RSHS
S320 980
F28033RSHT
S320 980
F28034PAGQ
TMS320
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
PAG
PAG
PAG
PN
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320F28034PAGQR
TMS320F28034PAGS
TMS320F28034PAGT
TMS320F28034PNQ
TMS320F28034PNS
TMS320F28034PNT
TMS320F28034PNTR
TMS320F28034RSHS
TMS320F28034RSHT
TMS320F28035PAGQ
TMS320F28035PAGS
TMS320F28035PAGT
TMS320F28035PAGTR
TMS320F28035PNQ
TMS320F28035PNQR
TMS320F28035PNS
TMS320F28035PNT
TMS320F28035PNTR
ACTIVE
TQFP
TQFP
TQFP
LQFP
LQFP
LQFP
LQFP
VQFN
VQFN
TQFP
TQFP
TQFP
TQFP
LQFP
LQFP
LQFP
LQFP
LQFP
64
64
64
80
80
80
80
56
56
64
64
64
64
80
80
80
80
80
1500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 105
-40 to 125
-40 to 125
-40 to 125
-40 to 105
-40 to 105
F28034PAGQ
TMS320
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
160
160
119
119
119
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F28034PAGS
TMS320
F28034PAGT
TMS320
F28034PNQ
TMS320
PN
F28034PNS
TMS320
PN
F28034PNT
TMS320
PN
1000 RoHS & Green
F28034PNT
TMS320
RSH
RSH
PAG
PAG
PAG
PAG
PN
260
260
160
160
160
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
F28034RSHS
S320 980
F28034RSHT
S320 980
F28035PAGQ
TMS320
F28035PAGS
TMS320
F28035PAGT
TMS320
1500 RoHS & Green
119 RoHS & Green
1000 RoHS & Green
F28035PAGT
TMS320
F28035PNQ
TMS320
PN
F28035PNQ
TMS320
PN
119
119
RoHS & Green
RoHS & Green
F28035PNS
TMS320
PN
F28035PNT
TMS320
PN
1000 RoHS & Green
F28035PNT
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320
TMS320F28035RSHS
TMS320F28035RSHT
ACTIVE
ACTIVE
VQFN
VQFN
RSH
RSH
56
56
260
260
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 105
F28035RSHS
S320 980
F28035RSHT
S320 980
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
OTHER QUALIFIED VERSIONS OF TMS320F28035 :
Enhanced Product: TMS320F28035-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMS320F28032PNTR
LQFP
PN
80
1000
330.0
24.4
16.0
16.0
2.0
24.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
LQFP PN 80
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
TMS320F28032PNTR
1000
Pack Materials-Page 2
PACKAGE OUTLINE
RSH0056D
VQFN - 1 mm max height
S
C
A
L
E
2
.
0
0
0
VQFN
7.15
6.85
A
B
PIN 1 INDEX AREA
7.15
6.85
C
1 MAX
SEATING PLANE
0.05
0.00
5.3 0.1
(0.2)
15
28
14
29
52X 0.4
4X
5.2
1
42
0.25
56X
PIN 1 ID
0.15
43
56
(OPTIONAL)
0.1
C A
C
B
0.6
0.4
56X
0.05
4218794/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RSH0056D
VQFN - 1 mm max height
VQFN
(5.3)
43
SYMM
56
SEE DETAILS
56X (0.7)
56X (0.2)
1
42
52X (0.4)
6X
(1.12)
(1.28)
TYP
SYMM
(6.7)
14
29
(
0.2) TYP
VIA
15
28
(1.28) TYP
6X (1.12)
(6.7)
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDERMASK
OPENING
SOLDERMASK
OPENING
METAL
NON SOLDERMASK
DEFINED
SOLDERMASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4218794/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSH0056D
VQFN - 1 mm max height
VQFN
SYMM
METAL
TYP
(1.28) TYP
43
56
56X (0.7)
1
42
56X (0.2)
52X (0.4)
(1.28)
TYP
SYMM
(6.7)
14
29
15
28
16X (1.08)
(6.7)
SOLDERPASTE EXAMPLE
BASED ON 0.1mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:12X
4218794/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
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Copyright © 2021, Texas Instruments Incorporated
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