TMS320F28054F-Q1 [TI]
TMS320F2805x Microcontrollers;
| 型号： | TMS320F28054F-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F2805x Microcontrollers 微控制器 |
| 文件： | 总151页 (文件大小：3411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F,TMS320F28051,TMS320F28050
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
TMS320F2805x Microcontrollers
– Three Serial Communications Interface (SCI)
(Universal Asynchronous Receiver/Transmitter
[UART]) modules
– One Serial Peripheral Interface (SPI) module
– One Inter-Integrated-Circuit (I2C) bus
– One Enhanced Controller Area Network
(eCAN) bus
1 Features
•
High-efficiency 32-bit CPU (TMS320C28x)
– 60 MHz (16.67-ns cycle time)
– 16 × 16 and 32 × 32 Multiply and Accumulate
(MAC) operations
– 16 × 16 dual MAC
– Harvard bus architecture
– Atomic operations
•
•
Enhanced control peripherals
– Enhanced Pulse Width Modulator (ePWM)
– Enhanced Capture (eCAP) module
– Enhanced Quadrature Encoder Pulse (eQEP)
module
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
Programmable Control Law Accelerator (CLA)
– 32-bit floating-point math accelerator
– Executes code independently of the main CPU
Dual-zone security module
•
Analog peripherals
– One 12-bit Analog-to-Digital Converter (ADC)
– One on-chip temperature sensor for oscillator
compensation
•
•
•
– Up to seven comparators with up to three
integrated Digital-to-Analog Converters (DACs)
– One buffered reference DAC
– Up to four Programmable Gain Amplifiers
(PGAs)
Endianness: Little endian
Low device and system cost:
– Single 3.3-V supply
– No power sequencing requirement
– Integrated power-on reset and brownout reset
– Low power
– Up to four digital filters
Advanced debug features
•
– No analog support pins
– Analysis and breakpoint functions
– Real-time debug through hardware
80-pin PN Low-Profile Quad Flatpack (LQFP)
Temperature options
– T: –40°C to 105°C
– S: –40°C to 125°C
•
Clocking:
– Two internal zero-pin oscillators
– On-chip crystal oscillator and external clock
input
•
•
– Watchdog timer module
– Missing clock detection circuitry
Up to 42 individually programmable, multiplexed
General-Purpose Input/Output (GPIO) pins with
input filtering
– Q: –40°C to 125°C
•
•
•
(AEC Q100 qualification for automotive
applications)
JTAG boundary scan support
2 Applications
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
Peripheral Interrupt Expansion (PIE) block that
supports all peripheral interrupts
Three 32-bit CPU timers
•
•
•
•
•
•
Air conditioner outdoor unit
Door operator drive control
Inverter & motor control
AC drive control module
AC-input BLDC motor drive
DC-input BLDC motor drive
•
•
•
Independent 16-bit timer in each ePWM module
On-chip memory
– Flash, SARAM, Message RAM, OTP, CLA Data
ROM, Boot ROM, Secure ROM available
128-bit security key and lock
– Protects secure memory blocks
– Prevents firmware reverse-engineering
Serial port peripherals
•
•
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
www.ti.com
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Premium performance MCUs and the Entry performance MCUs.
The F2805x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly
integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based
code, and also provides a high level of analog integration.
An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references
have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed
full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for
low overhead and latency.
The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUT
-
buffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three
discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device
number. See Device Comparison for more details.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information (1)
PART NUMBER
TMS320F28055PN
PACKAGE
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
LQFP (80)
BODY SIZE
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
TMS320F28054PN
TMS320F28053PN
TMS320F28052PN
TMS320F28051PN
TMS320F28050PN
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
3.1 Functional Block Diagram
Figure 3-1 shows a functional block diagram of the device.
Z1/Z2 User OTP
Secure
M0
SARAM 1K ´ 16
L0 SARAM (2K ´ 16)
(0-wait, Secure)
CLA Data RAM2
(0-wait)
FLASH
M1
SARAM 1K ´ 16
L1 DPSARAM (1K ´ 16)
(0-wait, Secure)
CLA Data RAM0
28055, 28054: 64K ´ 16, 10 Sectors
28053, 28052, 28051: 32K ´ 16, 5 Sectors
(0-wait)
Dual-
Zone
Security
Module
+
L2 DPSARAM (1K ´ 16)
(0-wait, Secure)
CLA Data RAM1
28050: 16K ´ 16, 3 Sectors
Boot ROM
12K ´ 16
Secure
ECSL
L3 DPSARAM (4K ´ 16)
(0-wait, Secure)
CLA Program RAM
(0-wait)
Nonsecure
PUMP
Secure ROM(A)
2K ´ 16
OTP/Flash Wrapper
CLA Data ROM
(0-wait)
Secure
PSWD
(4K ´ 16)
Memory Bus
TRST
TCK
CLA +
Message RAMs
C28x CPU
(60 MHz)
TDI
GPIO
TMS
Mux
TDO
GPIO
CTRIPnOUT
MUX
X1
X2
COMP
+
CPU Timer 0
OSC1,
OSC2,
Ext,
XRS
Digital
Filter
COMPAn
COMPBn
CPU Timer 1
POR/
BOR
PLL,
LPM,
WD
VREG
Program-
mable
Gain
CPU Timer 2
PIE
(up to 96 interrupts)
XCLKIN
LPM Wakeup
Amps
ADC
0-wait
Result
Regs
GPIO
Mux
3 External Interrupts
ADC
3.75
MSPS
Memory Bus
32-Bit Peripheral Bus
(CLA-accessible)
32-Bit Peripheral Bus
(CLA-accessible)
32-Bit
Peripheral Bus
16-Bit Peripheral Bus
SCI-A,
SCI-B, SCI-C
(4L FIFO)
eCAN-A
SPI-A
I2C-A
eCAP
eQEP
ePWM1–ePWM7
(4L FIFO)
(4L FIFO)
(32-mbox)
GPIO MUX
Copyright © 2017, Texas Instruments Incorporated
A. Stores Secure Copy Code Functions on all devices.
B. Not all peripheral pins are available at the same time due to multiplexing.
Figure 3-1. Functional Block Diagram
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................3
4 Revision History.............................................................. 4
5 Device Comparison.........................................................5
5.1 Related Products........................................................ 6
6 Terminal Configuration and Functions..........................7
6.1 Pin Diagram................................................................ 7
6.2 Signal Descriptions..................................................... 8
7 Specifications................................................................ 16
7.1 Absolute Maximum Ratings (1) (2) .............................16
7.2 ESD Ratings – Commercial...................................... 16
7.3 ESD Ratings – Automotive....................................... 16
7.4 Recommended Operating Conditions.......................17
7.5 Power Consumption Summary................................. 18
7.6 Electrical Characteristics (1) ..................................... 21
7.7 Thermal Resistance Characteristics for PN
Package...................................................................... 22
7.8 Thermal Design Considerations................................22
7.9 JTAG Debug Probe Connection Without Signal
Buffering for the MCU..................................................23
7.10 Parameter Information............................................ 24
7.11 Test Load Circuit..................................................... 24
7.12 Power Sequencing..................................................25
7.13 Clock Specifications................................................28
7.14 Flash Timing............................................................31
8 Detailed Description......................................................33
8.1 Overview...................................................................33
8.2 Memory Maps........................................................... 44
8.3 Register Map.............................................................51
8.4 Device Emulation Registers......................................53
8.5 VREG, BOR, POR.................................................... 55
8.6 System Control......................................................... 57
8.7 Low-power Modes Block...........................................65
8.8 Interrupts...................................................................66
8.9 Peripherals................................................................71
9 Applications, Implementation, and Layout............... 141
9.1 TI Reference Design...............................................141
10 Device and Documentation Support........................142
10.1 Getting Started......................................................142
10.2 Device and Development Support Tool
Nomenclature............................................................142
10.3 Tools and Software............................................... 143
10.4 Documentation Support........................................ 145
10.5 Support Resources............................................... 146
10.6 Trademarks...........................................................146
10.7 Electrostatic Discharge Caution............................146
10.8 Glossary................................................................146
11 Mechanical, Packaging, and Orderable
Information.................................................................. 147
11.1 Packaging Information.......................................... 147
4 Revision History
Changes from June 24, 2020 to February 1, 2021 (from Revision D (June 2020) to Revision E
(February 2021))
Page
•
•
•
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1: Added Q1 Part Numbers....................................................................................................................5
Figure 10-1: Added GPN information............................................................................................................. 142
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
5 Device Comparison
Table 5-1 lists the features of the TMS320F2805x devices.
Table 5-1. Device Comparison
28054
28052
28054-Q1
28054M (1)
28054M-Q1
28054F (1)
28054F-Q1
(60 MHz)
28052-Q1
28052M (1)
28052M-Q1
28052F (1)
28052F-Q1
(60 MHz)
28055
(60 MHz)
28053
(60 MHz)
28051
(60 MHz)
28050
(60 MHz)
FEATURE
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
80-pin PN
LQFP
Package type
Instruction cycle
CLA
16.67 ns
Yes
16.67 ns
No
16.67 ns
Yes
16.67 ns
No
16.67 ns
No
16.67 ns
No
On-chip flash (16-bit word)
64K
64K
32K
32K
32K
16K
10K (28054)
8K (28054M)
8K (28054F)
10K (28052)
8K (28052M)
8K (28052F)
On-chip SARAM (16-bit word)
10K
Yes
10K
Yes
8K
6K
Dual-zone security for on-chip flash,
SARAM, OTP, and secure ROM
blocks
Yes
Yes
Yes
Yes
Boot ROM (12K × 16)
Yes
1K
Yes
1K
Yes
1K
Yes
1K
Yes
1K
Yes
1K
One-time programmable (OTP) ROM
(16-bit word)
ePWM channels
eCAP inputs
eQEP modules
Watchdog timer
MSPS
14
1
14
1
14
1
14
1
14
1
14
1
1
1
1
1
1
1
Yes
3.75
267 ns
16
Yes
3.75
267 ns
16
Yes
3.75
267 ns
16
Yes
3.75
267 ns
16
Yes
2
Yes
2
Conversion time
Channels
500 ns
16
500 ns
16
12-Bit ADC
Temperature
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
sensor
Dual
sample-and-hold
PGA (Gain ≈ 3, 6, or 11)
Fixed Gain Amplifier (Gain ≈ 3)
Comparators
4
3
4
4
3
4
4
3
3
4
3
3
7
7
7
7
7
6
Internal comparator reference DACs
Buffered reference DAC
32-Bit CPU timers
I2C
3
3
3
3
3
2
1
1
1
1
1
1
3
3
3
3
3
3
1
1
1
1
1
1
eCAN
1
1
1
1
1
1
SPI
1
1
1
1
1
1
SCI
3
3
3
3
3
3
0-pin oscillators
2
2
2
2
2
2
I/O pins (shared) GPIO
External interrupts
Supply voltage (nominal)
T: –40°C to 105°C
42
3
42
42
3
42
42
3
42
3
3
3.3 V
3
3.3 V
3.3 V
Yes
Yes
3.3 V
Yes
Yes
3.3 V
Yes
Yes
3.3 V
Yes
Yes
Yes
Yes
Temperature
options
S: –40°C to 125°C
Yes (28054 only)
Yes (28052 only)
Q: –40°C to
125°C(2)
Yes
Yes
Yes
Yes
Yes
Yes
(1) TMS320F2805xM devices are InstaSPIN-MOTION-enabled MCUs. TMS320F2805xF devices are InstaSPIN-FOC-enabled MCUs. On
these devices, TI has secured Zone1 and allocated RAML0 to Zone1. Because of this, Zone1 and RAML0 are not available for
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
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customer applications; only Zone2 is available. For more information, see Section 10.4 for a list of InstaSPIN Technical Reference
Manuals.
(2) The letter Q refers to AEC Q100 qualification for automotive applications.
5.1 Related Products
For information about similar products, see the following links:
TMS320F2802x Microcontrollers
The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are
available.
TMS320F2803x Microcontrollers
The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the
parallel control law accelerator (CLA) option.
TMS320F2805x Microcontrollers
The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).
InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.
TMS320F2806x Microcontrollers
The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-
count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™
versions are available.
TMS320F2807x Microcontrollers
The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.
The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.
TMS320F28004x Microcontrollers
The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.
InstaSPIN-FOC and configurable logic block (CLB) versions are available.
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
6 Terminal Configuration and Functions
6.1 Pin Diagram
Figure 6-1 shows the 80-pin PN Low-Profile Quad Flatpack pin assignments.
GPIO11/EPWM6B/SCIRXDB
GPIO5/EPWM3B/SPISIMOA/ECAP1
GPIO4/EPWM3A
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
GPIO26/SCIRXDC
TEST2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DDIO
V
GPIO40/EPWM7A
SS
GPIO10/EPWM6A/ADCSOCBO
GPIO3/EPWM2B/SPISOMIA
GPIO2/EPWM2A
GPIO9/EPWM5B/SCITXDB
GPIO30/CANRXA/SCIRXDB/EPWM7A
GPIO31/CANTXA/SCITXDB/EPWM7B
GPIO27/SCITXDC
PFCGND
GPIO1/EPWM1B/CTRIPM1OUT
GPIO0/EPWM1A
V
ADCINB7 (op-amp)
ADCINB0
DDIO
VREGENZ
V
V
ADCINB6 (op-amp)
ADCINB5
SS
DD
GPIO34/CTRIPPFCOUT
M2GND
GPIO15/TZ1/CTRIPM1OUT/SCIRXDB
GPIO13/TZ2
ADCINB4 (op-amp)
ADCINB3
GPIO14/TZ3/CTRIPPFCOUT/SCITXDB
GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT
GPIO21/EQEP1B/EPWM7B
ADCINA7
ADCINA6 (op-amp)
V
V
REFLO
SSA
GPIO23/EQEP1I/SCIRXDB
Figure 6-1. 2805x 80-Pin PN Low-Profile Quad Flatpack (Top View)
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
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6.2 Signal Descriptions
Section 6.2.1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at
reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions.
Some peripheral functions may not be available in all devices. See Table 5-1 for details. Inputs are not 5-V
tolerant. All GPIO pins are I/O/Z and have an internal pullup (PU), which can be selectively enabled or disabled
on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at
reset, except as noted in Section 6.2.1. The pullups on other GPIO pins are enabled upon reset.
Note
When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins
could glitch during power up. This potential glitch will finish before the boot mode pins are read and
will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied
externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins
and any external driver could be considered to limit the potential for degradation to the pin and/or
external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply.
However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to
the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin
during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO
pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
6.2.1 Signal Descriptions (1)
TERMINAL
I/O/Z
DESCRIPTION
PN
PIN NO.
NAME
JTAG
JTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an
active high test pin and must be maintained low at all times during normal device operation. An
external pulldown resistor is required on this pin. The value of this resistor should be based on
drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Because the value of the resistor is application-specific, TI recommends
that each target board be validated for proper operation of the debugger and the application.
(↓)
TRST
9
I
See
GPIO38
TCK
TMS
TDI
I
See GPIO38. JTAG test clock with internal pullup. (↑)
See
GPIO36
See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.. (↑)
I
I
See
GPIO35
See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK. (↑)
See
GPIO37
See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive)
TDO
O/Z
FLASH
TEST2
39
I/O
Test Pin. Reserved for TI. Must be left unconnected.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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TERMINAL
NAME
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
I/O/Z
DESCRIPTION
PN
PIN NO.
CLOCK
See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same
frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of
XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The
mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
See
GPIO18
XCLKOUT
O/Z
See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the
XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock
from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and
the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a
crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal
device operation may need to incorporate some hooks to disable this path during debug using
the JTAG connector. This action is to prevent contention with the TCK signal, which is active
during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to
clock the device.
See
GPIO19
and
XCLKIN
I
GPIO38
On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic
resonator must be connected across X1 and X2. In this case, the XCLKIN path must be
disabled by bit 13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND.
(I)
X1
X2
52
51
I
On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected
across X1 and X2. If X2 is not used, X2 must be left unconnected. (O)
O
RESET
Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-on reset
(POR) and brownout reset (BOR) circuitry. During a power-on or brownout condition, this pin is
driven low by the device. An external circuit may also drive this pin to assert a device reset.
This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset,
the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor
with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is
placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values
will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when
the watchdog reset is asserted. Regardless of the source, a device reset causes the device to
terminate execution. The program counter points to the address contained at the location
0x3F FFC0. When reset is deactivated, execution begins at the location designated by the
program counter. The output buffer of this pin is an open-drain with an internal pullup. (↑) If this
pin is driven by an external device, it should be done using an open-drain device.
XRS
8
I/OD
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TERMINAL
I/O/Z
DESCRIPTION
PN
PIN NO.
NAME
ADC, COMPARATOR, ANALOG I/O
ADCINA7
24
23
I
I
ADC Group A, Channel 7 input
ADC Group A, Channel 6 input
ADCINA6
(op-amp)
ADCINA5
ADCINA4
10
11
I
I
ADC Group A, Channel 5 input
ADC Group A, Channel 4 input
ADCINA3
(op-amp)
12
13
14
I
I
I
ADC Group A, Channel 3 input
ADC Group A, Channel 2 input
ADC Group A, Channel 1 input
ADCINA2
ADCINA1
(op-amp)
ADCINA0
VREFOUT
ADC Group A, Channel 0 input
18
I
Voltage Reference out from buffered DAC
ADC External Reference – used when in ADC external reference mode and used as VREFOUT
reference
VREFHI
19
31
I
I
ADCINB7
(op-amp)
ADC Group B, Channel 7 input
ADCINB6
(op-amp)
29
28
26
I
I
I
ADC Group B, Channel 6 input
ADC Group B, Channel 5 input
ADC Group B, Channel 4 input
ADCINB5
ADCINB4
(op-amp)
ADCINB3
ADCINB2
25
16
I
I
ADC Group B, Channel 3 input
ADC Group B, Channel 2 input
ADCINB1
(op-amp)
17
I
ADC Group B, Channel 1 input
ADCINB0
VREFLO
30
22
I
I
ADC Group B, Channel 0 input
ADC Low Reference (always tied to ground)
CPU AND I/O POWER
VDDA
VSSA
20
21
6
Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
Analog Ground Pin
CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor
between each VDD pin and ground. Higher value capacitors may be used.
VDD
54
73
38
Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG is enabled.
Place a decoupling capacitor on each pin. The exact value should be determined by the
system voltage regulation solution.
VDDIO
70
7
37
53
72
15
27
32
VSS
Digital Ground Pins
M1GND
M2GND
PFCGND
Ground pin for amplifier (channels A1, A3, B1)
Ground pin for amplifier (channels A6, B4, B6)
Ground pin for amplifier (channel B7)
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ
71
I
Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG
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TERMINAL
NAME
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
I/O/Z
DESCRIPTION
PN
PIN NO.
GPIO AND PERIPHERAL SIGNALS (2)
General-purpose input/output 0
Enhanced PWM1 Output A
Reserved
GPIO0
I/O/Z
O
EPWM1A
Reserved
Reserved
GPIO1
69
68
67
66
63
62
50
49
45
36
65
–
–
Reserved
I/O/Z
O
General-purpose input/output 1
Enhanced PWM1 Output B
Reserved
EPWM1B
Reserved
CTRIPM1OUT
GPIO2
–
O
CTRIPM1 CTRIPxx output
General-purpose input/output 2
Enhanced PWM2 Output A
Reserved
I/O/Z
O
EPWM2A
Reserved
Reserved
GPIO3
–
–
Reserved
I/O/Z
O
General-purpose input/output 3
Enhanced PWM2 Output B
SPI-A slave out, master in
Reserved
EPWM2B
SPISOMIA
Reserved
GPIO4
I/O
–
I/O/Z
O
General-purpose input/output 4
Enhanced PWM3 output A
Reserved
EPWM3A
Reserved
Reserved
GPIO5
–
–
Reserved
I/O/Z
O
General-purpose input/output 5
Enhanced PWM3 output B
SPI-A slave in, master out
Enhanced Capture input/output 1
General-purpose input/output 6
Enhanced PWM4 output A
External ePWM sync pulse input
External ePWM sync pulse output
General-purpose input/output 7
Enhanced PWM4 output B
SCI-A receive data
EPWM3B
SPISIMOA
ECAP1
I/O
I/O
I/O/Z
O
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
GPIO7
I
O
I/O/Z
O
EPWM4B
SCIRXDA
Reserved
GPIO8
I
–
Reserved
I/O/Z
O
General-purpose input/output 8
Enhanced PWM5 output A
Reserved
EPWM5A
Reserved
ADCSOCAO
GPIO9
–
O
ADC start-of-conversion A
General-purpose input/output 9
Enhanced PWM5 output B
SCI-B transmit data
I/O/Z
O
EPWM5B
SCITXDB
Reserved
GPIO10
O
–
Reserved
I/O/Z
O
General-purpose input/output 10
Enhanced PWM6 output A
Reserved
EPWM6A
Reserved
ADCSOCBO
–
O
ADC start-of-conversion B
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TERMINAL
I/O/Z
DESCRIPTION
PN
PIN NO.
NAME
GPIO11
I/O/Z
General-purpose input/output 11
Enhanced PWM6 output B
SCI-B receive data
EPWM6B
SCIRXDB
Reserved
GPIO12
O
61
48
76
77
I
–
Reserved
I/O/Z
General-purpose input/output 12
Trip Zone input 1
TZ1
I
O
CTRIPM1OUT
SCITXDA
Reserved
GPIO13
CTRIPM1 CTRIPxx output
SCI-A transmit data
Reserved
O
–
I/O/Z
I
General-purpose input/output 13
Trip zone input 2
TZ2
Reserved
Reserved
GPIO14
–
Reserved
–
Reserved
I/O/Z
I
General-purpose input/output 14
Trip zone input 3
TZ3
CTRIPPFCOUT
SCITXDB
Reserved
GPIO15
O
CTRIPPFC output
O
SCI-B transmit data
Reserved
–
I/O/Z
I
General-purpose input/output 15
Trip zone input 1
TZ1
CTRIPM1OUT
SCIRXDB
Reserved
GPIO16
75
47
44
O
CTRIPM1 CTRIPxx output
SCI-B receive data
I
–
Reserved
I/O/Z
I/O
I/O
I
General-purpose input/output 16
SPI-A slave in, master out
Enhanced QEP1 strobe
Trip Zone input 2
SPISIMOA
EQEP1S
TZ2
GPIO17
I/O/Z
I/O
I/O
I
General-purpose input/output 17
SPI-A slave out, master in
Enhanced QEP1 index
Trip zone input 3
SPISOMIA
EQEP1I
TZ3
CTRIPPFCOUT
GPIO18
O
CTRIPPFC output
I/O/Z
I/O
O
General-purpose input/output 18
SPI-A clock input/output
SCI-B transmit data
SPICLKA
SCITXDB
XCLKOUT
43
O/Z
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled
by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The
XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18
must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO19
I/O/Z
I
General-purpose input/output 19
XCLKIN
External Oscillator Input. The path from this pin to the clock block is not gated by the mux
function of this pin. Care must be taken not to enable this path for clocking if this path is being
used for the other periperhal functions
55
SPISTEA
SCIRXDB
ECAP1
I/O
I
SPI-A slave transmit enable input/output
SCI-B receive data
I/O
Enhanced Capture input/output 1
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TERMINAL
NAME
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
I/O/Z
DESCRIPTION
PN
PIN NO.
GPIO20
I/O/Z
General-purpose input/output 20. Internal pullup enabled by default.
Enhanced QEP1 input A
Enhanced PWM7 output A
CTRIPM1 CTRIPxx output
General-purpose input/output 21. Internal pullup enabled by default.
Enhanced QEP1 input B
Enhanced PWM7 output B
Reserved
EQEP1A
EPWM7A
CTRIPM1OUT
GPIO21
I
78
79
1
O
O
I/O/Z
EQEP1B
EPWM7B
Reserved
GPIO22
I
O
–
I/O/Z
General-purpose input/output 22
Enhanced QEP1 strobe
Reserved
EQEP1S
Reserved
SCITXDB
GPIO23
I/O
–
O
SCI-B transmit data
I/O/Z
General-purpose input/output 23
Enhanced QEP1 index
EQEP1I
I/O
80
4
Reserved
SCIRXDB
GPIO24
–
Reserved
I
SCI-B receive data
I/O/Z
General-purpose input/output 24. Internal pullup enabled by default.
Enhanced Capture input/output 1
Enhanced PWM7 output A
Reserved
ECAP1
I/O
EPWM7A
Reserved
GPIO25
O
–
I/O/Z
General-purpose input/output 25
Reserved
Reserved
Reserved
Reserved
GPIO26
–
46
40
33
42
–
Reserved
–
Reserved
I/O/Z
General-purpose input/output 26
Reserved
Reserved
SCIRXDC
Reserved
GPIO27
–
I
SCI-C receive data
–
Reserved
I/O/Z
General-purpose input/output 27
Reserved
Reserved
SCITXDC
Reserved
GPIO28
–
O
SCI-C transmit data
–
Reserved
I/O/Z
General-purpose input/output 28
SCI-A receive data
SCIRXDA
SDAA
I
I/OD
I2C data open-drain bidirectional port
Trip zone input 2
TZ2
I
GPIO29
I/O/Z
General-purpose input/output 29
SCI-A transmit data
SCITXDA
SCLA
O
41
35
I/OD
I2C clock open-drain bidirectional port
Trip zone input 3
TZ3
I
CTRIPPFCOUT
GPIO30
O
CTRIPPFC output
I/O/Z
General-purpose input/output 30. Internal pullup enabled by default.
CAN receive
CANRXA
SCIRXDB
EPWM7A
I
I
SCI-B receive data
O
Enhanced PWM7 output A
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TERMINAL
I/O/Z
DESCRIPTION
PN
PIN NO.
NAME
GPIO31
I/O/Z
O
General-purpose input/output 31. Internal pullup enabled by default.
CAN transmit
CANTXA
SCITXDB
EPWM7B
GPIO32
34
2
O
SCI-B transmit data
O
Enhanced PWM7 output B
I/O/Z
I/OD
I
General-purpose input/output 32
I2C data open-drain bidirectional port
Enhanced PWM external sync pulse input
Enhanced QEP1 strobe
SDAA
EPWMSYNCI
EQEP1S
GPIO33
I/O
I/O/Z
I/OD
O
General-Purpose Input/Output 33
I2C clock open-drain bidirectional port
Enhanced PWM external synch pulse output
Enhanced QEP1 index
SCLA
3
EPWMSYNCO
EQEP1I
I/O
I/O/Z
–
GPIO34
General-Purpose Input/Output 34
Reserved
Reserved
Reserved
CTRIPPFCOUT
GPIO35
74
–
Reserved
O
CTRIPPFC output
I/O/Z
I
General-Purpose Input/Output 35
TDI
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK
59
60
Reserved
Reserved
Reserved
GPIO36
TMS
–
Reserved
–
Reserved
–
I/O/Z
I
Reserved
General-Purpose Input/Output 36
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK.
Reserved
Reserved
Reserved
GPIO37
TDO
–
–
Reserved
Reserved
–
Reserved
I/O/Z
O/Z
General-Purpose Input/Output 37
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
58
57
Reserved
Reserved
Reserved
GPIO38
–
–
Reserved
Reserved
–
Reserved
I/O/Z
General-Purpose Input/Output 38
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TERMINAL
NAME
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
I/O/Z
DESCRIPTION
PN
PIN NO.
I
External Oscillator Input. The path from this pin to the clock block is not gated by the mux
function of this pin. Care must be taken to not enable this path for clocking if this path is being
used for the other functions.
XCLKIN
TCK
I
JTAG test clock with internal pullup
Reserved
Reserved
Reserved
GPIO39
–
Reserved
–
–
Reserved
Reserved
I/O/Z
–
General-Purpose Input/Output 39
Reserved
SCIRXDC
CTRIPPFCOUT
GPIO40
Reserved
56
64
5
I
SCI-C receive data
O
CTRIPPFC output
I/O/Z
O
General-Purpose Input/Output 40. Internal pullup enabled by default.
EPWM7A
Reserved
Reserved
GPIO42
Enhanced PWM7 output A
–
Reserved
–
Reserved
I/O/Z
O
General-Purpose Input/Output 42. Internal pullup enabled by default.
Enhanced PWM7 output B
EPWM7B
SCITXDC
CTRIPM1OUT
O
SCI-C transmit data
O
CTRIPM1 CTRIPxx output
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate
functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output
path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal.
For details, see the System Control and Interrupts chapter of the TMS320x2805x Technical Reference Manual.
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7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–20
MAX
4.6
2.5
4.6
4.6
2.5
4.6
20
UNIT
VDDIO (I/O and flash) with respect to VSS
Supply voltage
V
V
V
V
VDD with respect to VSS
Analog voltage
Input voltage
Output voltage
VDDA with respect to VSSA
VIN (3.3 V)
VIN (X1)
VO
(3)
Digital input (per pin), IIK (VIN < VSS or VIN > VDDIO
Analog input (per pin), IIKANALOG
)
–20
–20
20
20
Input clamp current
(VIN < VSSA or VIN > VDDA
)
mA
Total for all inputs, IIKTOTAL
(VIN < VSS/VSSA or VIN > VDDIO/VDDA
)
Output clamp current
Junction temperature(4)
Storage temperature(4)
IOK (VO < 0 or VO > VDDIO
)
–20
–40
–65
20
150
150
mA
°C
TJ
Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA.
(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device
life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
7.2 ESD Ratings – Commercial
VALUE
UNIT
TMS320F2805x, TMS320F2805xM, TMS320F2805xF in 80-pin PN package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101 or ANSI/ESDA/JEDEC JS-002(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings – Automotive
VALUE
UNIT
TMS320F2805x, TMS320F2805xM, TMS320F2805xF in 80-pin PN package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
±500
±750
V(ESD)
Electrostatic discharge
V
Charged device model (CDM),
per AEC Q100-011
Corner pins on 80-pin PN:
1, 20, 21, 40, 41, 60, 61, 80
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
7.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Device supply voltage, I/O, VDDIO
2.97
3.3
3.63
V
Device supply voltage CPU, VDD (When internal VREG is
disabled and 1.8 V is supplied externally)
1.71
2.97
1.8
1.995
3.63
V
Supply ground, VSS
0
3.3
0
V
V
Analog supply voltage, VDDA
Analog ground, VSSA
V
Device clock frequency (system clock)
High-level input voltage, VIH (3.3 V)
Low-level input voltage, VIL (3.3 V)
2
2
60
MHz
V
VDDIO + 0.3
VSS – 0.3
0.8
–4
–8
4
V
All GPIO pins
Group 2(1)
All GPIO pins
Group 2(1)
T version
High-level output source current, VOH = VOH(MIN) , IOH
Low-level output sink current, VOL = VOL(MAX), IOL
mA
mA
8
–40
–40
105
125
S version
Junction temperature, TJ
°C
Q version
(AEC Q100 qualification)
–40
125
(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO28, GPIO29, GPIO30, GPIO31, GPIO36, GPIO37
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7.5 Power Consumption Summary
Section 7.5.1 lists the current consumption at 60-MHz SYSCLKOUT.
7.5.1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
VREG ENABLED
VREG DISABLED
(1)
(2)
(1)
(2)
MODE
TEST CONDITIONS
IDDIO
TYP(3)
IDDA
TYP(3)
IDD
TYP(3)
IDDIO
IDDA
MAX
MAX
MAX
TYP(3)
MAX
TYP(3)
MAX
The following peripheral clocks are
enabled:
•
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7
•
•
•
•
•
•
•
•
•
eCAP1
eQEP1
eCAN-A
CLA
SCI-A, SCI-B, SCI-C
SPI-A
Operational
(flash)
ADC
95 mA(7)
132 mA
40 mA
60 mA
85 mA(7)
110 mA
14 mA
25 mA
40 mA
60 mA
I2C-A
COMPA1, COMPA3,
COMPB1, COMPB7
•
CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at 60 kHz.
All I/O pins are left unconnected.(4)
(6)
Code is running out of flash with
2 wait-states.
XCLKOUT is turned off.
Flash is powered down.
IDLE
XCLKOUT is turned off.
All peripheral clocks are turned off.
14 mA
9 mA
27 mA
15 mA
15 μA
15 μA
15 μA
25 μA
25 μA
25 μA
14 mA
9 mA
27 mA
15 mA
120 μA
120 μA
24 μA
450 μA
450 μA
15 μA
15 μA
15 μA
25 μA
25 μA
25 μA
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(5)
300 μA
50 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) To realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to
the PCLKCR0 register.
(3) The TYP numbers are applicable over room temperature and nominal voltage.
(4) The following is done in a loop:
•
•
•
•
•
Data is continuously transmitted out of SPI-A, SCI-A, SCI-B, SCI-C, eCAN-A, and I2C-A ports.
The hardware multiplier is exercised.
Watchdog is reset.
ADC is performing continuous conversion.
GPIO17 is toggled.
(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.
(6) CLA is continuously performing polynomial calculations.
(7) For F2805x devices that do not have CLA, subtract the IDD current number for CLA (see Table 7-1) from the IDD (VREG disabled)/IDDIO
(VREG enabled) current numbers listed in Section 7.5.1 for operational mode.
Note
The peripheral-I/O multiplexing implemented in the device prevents simultaneous use of all available
peripherals because more than one peripheral function may share an I/O pin. It is, however, possible
to turn on the clocks to all the peripherals at the same time, although such a configuration is not
useful. If the clocks to all the peripherals are turned on at the same time, the current drawn by the
device will be more than the numbers specified in the current consumption tables.
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7.5.2 Reducing Current Consumption
The 2805x devices incorporate a method to reduce the device current consumption. Because each peripheral
unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning
off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 7-1
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 7-1. Typical Current Consumption by Various
Peripherals (at 60 MHz) (1)
PERIPHERAL
MODULE(3)
IDD CURRENT
REDUCTION (mA)
ADC
2(2)
I2C
3
ePWM
2
eCAP
2
eQEP
2
SCI
2
SPI
COMP/DAC
PGA
2
1
2
CPU-TIMER
Internal zero-pin oscillator
CAN
1
0.5
2.5
20
CLA
(1) All peripheral clocks (except CPU Timer clock) are disabled
upon reset. Writing to or reading from peripheral registers is
possible only after the peripheral clocks are turned on.
(2) This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA) as well.
(3) For peripherals with multiple instances, the current quoted is per
module. For example, the 2 mA value quoted for ePWM is for
one ePWM module.
Note
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Note
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 40 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the
peripherals (enabled by that application) must be added to the baseline IDD current.
Following are other methods to reduce power consumption further:
•
The flash module may be powered down if code is run off SARAM. This method results in a current reduction
of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail.
•
•
Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
To realize the lowest VDDA current consumption in a low-power mode, see the respective analog chapter of
the TMS320x2805x Technical Reference Manual to ensure each module is powered down as well.
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•
Power savings can be achieved by powering down the flash. This must be done by code running off RAM
(not flash).
7.5.3 Current Consumption Graphs (VREG Enabled)
Operational Current vs Frequency
140
120
100
80
60
40
20
0
0
10
20
30
40
50
60
70
SYSCLKOUT (MHz)
IDDIO IDDA
Figure 7-1. Typical Operational Current Versus Frequency (F2805x)
Operational Power vs Frequency
500
450
400
350
300
250
200
0
10
20
30
40
50
60
70
SYSCLKOUT (MHz)
Figure 7-2. Typical Operational Power Versus Frequency (F2805x)
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Typical CLA operational current vs SYSCLKOUT
25
20
15
10
5
0
10
15
20
25
30
35
40
45
50
55
60
SYSCLKOUT (MHz)
Figure 7-3. Typical CLA Operational Current Versus SYSCLKOUT
7.6 Electrical Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOH MAX
IOH = 50 μA
VOH
VOL
High-level output voltage
Low-level output voltage
V
VDDIO – 0.2
IOL = IOL MAX
0.4
–205
–375
V
All GPIO pins
XRS pin
–80 –140
Pin with pullup
VDDIO = 3.3 V, VIN = 0 V
enabled
Input current
(low level)
–230 –300
IIL
μA
Pin with pullup
disabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
±2
±2
80
Pin with pulldown
disabled
Input current
(high level)
IIH
μA
Pin with pulldown
enabled
28
50
Output current, pullup or pulldown
disabled
IOZ
CI
±2 μA
Input capacitance
2
2.78
35
pF
V
VDDIO BOR trip point
VDDIO BOR hysteresis
Falling VDDIO
mV
Supervisor reset release delay
time
Time after BOR/POR/OVR event is removed to XRS
release
400
800 μs
V
VREG VDD output
Internal VREG on
1.9
(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage
(VDD) go out of range.
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7.7 Thermal Resistance Characteristics for PN Package
°C/W(1)
14.2
21.9
49.9
38.3
36.7
34.4
0.8
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
0
0
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
1.18
1.34
1.62
21.6
20.7
20.5
20.1
150
250
500
0
PsiJT
150
250
500
PsiJB
Junction-to-board
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The
Semiconductor and IC Package Thermal Metrics Application Report helps to understand the thermal metrics and
definitions.
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7.9 JTAG Debug Probe Connection Without Signal Buffering for the MCU
Figure 7-4 shows the connection between the MCU and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 7-4 shows the simpler, no-
buffering situation. For the pullup and pulldown resistor values, see Section 6.2.
6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
PD
4
6
8
TRST
TMS
TDI
GND
1
GND
GND
GND
GND
3
TDI
7
10
12
TDO
TCK
TDO
11
9
TCK
TCK_RET
MCU
JTAG Header
A. See Figure 8-42 for JTAG/GPIO multiplexing.
Figure 7-4. JTAG Debug Probe Connection Without Signal Buffering for the MCU
Note
The 2805x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header onboard,
the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor.
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7.10 Parameter Information
7.10.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
7.10.2 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.11 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
W
3.5 nH
Output
Under
Test
42
Transmission Line
(A)
Z0 = 50 W
Device Pin(B)
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-5. 3.3-V Test Load Circuit
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7.12 Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to
prevent the I/Os from glitching during power up or power down (GPIO19, GPIO34 to GPIO38 do not have glitch-
free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for
analog pins, this value is 0.7 V above VDDA) before powering up the device. Voltages applied to pins on an
unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.
VDDIO, VDDA
(3.3 V)
VDD (1.8 V)
INTOSC1
tINTOSCST
X1/X2
tOSCST
(B)
(A)
XCLKOUT
User-code dependent
t
w(RSL1)
XRS(D)
Address/data valid, internal boot-ROM code execution phase
Address/Data/
Control
(Internal)
User-code execution phase
User-code dependent
t
d(EX)
(C)
h(boot-mode)
t
Boot-Mode
Pins
GPIO pins as input
Peripheral/GPIO function
Boot-ROM execution starts
(E)
Based on boot code
GPIO pins as input (state depends on internal PU/PD)
I/O Pins
User-code dependent
A. Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0,
SYSCLKOUT is further divided by 4 before SYSCLKOUT appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase.
B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the
pin until explicitly configured by user code.
C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
D. Using the XRS pin is optional due to the on-chip POR circuitry.
E. The internal pullup or pulldown will take effect when BOR is driven high.
Figure 7-6. Power-on Reset
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7.12.1 Reset ( XRS) Timing Requirements
MIN
1000tc(SCO)
32tc(OSCCLK)
MAX
UNIT
cycles
cycles
th(boot-mode)
tw(RSL2)
Hold time for boot-mode pins
Pulse duration, XRS low on warm reset
7.12.2 Reset ( XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
μs
tw(RSL1)
tw(WDRS)
td(EX)
Pulse duration, XRS driven by device
600
Pulse duration, reset pulse generated by watchdog
Delay time, address/data valid after XRS high
Start-up time, internal zero-pin oscillator
On-chip crystal-oscillator start-up time
512tc(OSCCLK)
cycles
cycles
μs
32tc(OSCCLK)
tINTOSCST
3
(1)
tOSCST
1
10
ms
(1) Dependent on crystal/resonator and board design.
INTOSC1
X1/X2
XCLKOUT
User-Code Dependent
t
w(RSL2)
XRS
User-Code Execution Phase
t
d(EX)
Address/Data/
User-Code Execution
Control
(Internal)
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-7. Warm Reset
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Figure 7-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0008. Immediately after the PLLCR register
is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete, SYSCLKOUT reflects the new operating frequency, OSCCLK × 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(CPU frequency while PLL is stabilizing
with the desired frequency. This period
(PLL lock-up time tp) is 1 ms long.)
(Current CPU
Frequency)
(Changed CPU frequency)
Figure 7-8. Example of Effect of Writing Into PLLCR Register
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7.13 Clock Specifications
7.13.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 2805x MCUs. Section 7.13.1.1 lists the cycle times of various clocks.
7.13.1.1 2805x Clock Table and Nomenclature (60-MHz Devices)
MIN
16.67
2
NOM
MAX UNIT
tc(SCO), Cycle time
Frequency
500
60
ns
MHz
ns
SYSCLKOUT
LSPCLK(1)
ADC clock
tc(LCO), Cycle time
Frequency
16.67
66.67(2)
15(2)
60
60
MHz
ns
tc(ADCCLK), Cycle time
Frequency
16.67
MHz
(1) Lower LSPCLK will reduce device power consumption.
(2) This value is the default reset value if SYSCLKOUT = 60 MHz.
7.13.1.2 Device Clocking Requirements/Characteristics
MIN
50
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
200
20
ns
MHz
ns
On-chip oscillator (X1/X2 pins)
(Crystal/Resonator)
5
tc(CI), Cycle time (C8)
Frequency
33.3
5
200
30
External oscillator/clock source
(XCLKIN pin) — PLL Enabled
MHz
ns
tc(CI), Cycle time (C8)
Frequency
33.33
4
250
30
External oscillator/clock source
(XCLKIN pin) — PLL Disabled
MHz
Limp mode SYSCLKOUT
(with /2 enabled)
Frequency range
1 to 5
MHz
tc(XCO), Cycle time (C1)
66.67
0.5
2000
15
ns
MHz
ms
XCLKOUT
Frequency
tp
PLL lock time(1)
1
(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are
used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).
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7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
PARAMETER
MIN
TYP
10.000
10.000
±1%
55
MAX UNIT
MHz
Internal zero-pin oscillator 1 (INTOSC1) at 30°C(1) (2)
Internal zero-pin oscillator 2 (INTOSC2) at 30°C(1) (2)
Accuracy using oscillator compensation(1) (2)
Step size (coarse trim)
Frequency
Frequency
MHz
kHz
kHz
Step size (fine trim)
14
Temperature drift(3)
3.03
175
4.85 kHz/°C
Hz/mV
Voltage (VDD) drift(3)
(1) To achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, see the Oscillator Compensation Guide. See Figure 7-9 for
TYP and MAX values.
(2) Frequency range is ensured only when VREG is enabled, VREGENZ = VSS
.
(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For
example:
•
•
An increase in temperature causes the output frequency to increase according to the temperature coefficient.
A decrease in voltage (VDD) causes the output frequency to decrease according to the voltage coefficient.
Zero-Pin Oscillator Frequency Movement With Temperature
10.6
10.5
10.4
10.3
10.2
10.1
10
9.9
9.8
9.7
9.6
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
110
120
Typical
Max
Temperature (°C)
Figure 7-9. Zero-Pin Oscillator Frequency Movement With Temperature
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7.13.2 Clock Requirements and Characteristics
7.13.2.1 XCLKIN Timing Requirements - PLL Enabled
NO.
MIN
C9
tf(CI)
Fall time, XCLKIN
6
6
ns
ns
C10 tr(CI)
Rise time, XCLKIN
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
45%
55%
55%
7.13.2.2 XCLKIN Timing Requirements - PLL Disabled
NO.
MIN
MAX UNIT
C9
tf(CI)
Fall time, XCLKIN
Rise time, XCLKIN
Up to 20 MHz
6
ns
2
20 MHz to 30 MHz
Up to 20 MHz
C10 tr(CI)
6
ns
2
20 MHz to 30 MHz
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
45%
55%
55%
The possible configuration modes are shown in Table 8-21.
7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
over recommended operating conditions (unless otherwise noted)
NO.
C3
C4
C5
C6
PARAMETER
MIN
MAX
UNIT
ns
tf(XCO)
Fall time, XCLKOUT
Rise time, XCLKOUT
5
5
tr(XCO)
ns
tw(XCOL)
tw(XCOH)
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
H – 2
H – 2
H + 2
H + 2
ns
ns
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-10. Clock Timing
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7.14 Flash Timing
7.14.1 Flash/OTP Endurance for T Temperature Material (1)
ERASE/PROGRAM
MIN
TYP
MAX
UNIT
TEMPERATURE
0°C to 105°C (ambient)
0°C to 30°C (ambient)
Nf
Flash endurance for the array (write/erase cycles)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.14.2 Flash/OTP Endurance for S Temperature Material (1)
ERASE/PROGRAM
MIN
TYP
MAX
UNIT
TEMPERATURE
0°C to 125°C (ambient)
0°C to 30°C (ambient)
Nf
Flash endurance for the array (write/erase cycles)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.14.3 Flash/OTP Endurance for Q Temperature Material (1)
ERASE/PROGRAM
TEMPERATURE
MIN
TYP
MAX
UNIT
Nf
Flash endurance for the array (write/erase cycles)
–40°C to 125°C (ambient)
–40°C to 30°C (ambient)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.14.4 Flash Parameters at 60-MHz SYSCLKOUT
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX UNIT
Program Time(3) 8K Sector
4K Sector
250 2000(2)
125 2000(2)
50
ms
ms
μs
s
16-Bit Word
Erase Time(1)
8K Sector
4K Sector
2
2
12(2)
12(2)
s
(4)
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
VREG disabled
VREG enabled
80
60
120
mA
mA
(4)
IDDIOP
(4)
IDDIOP
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Maximum flash parameter mentioned are for the first 100 program and erase cycles.
(3) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
•
•
•
the code that uses flash API to program the flash
the Flash API itself
Flash data to be programmed
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
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7.14.5 Flash/OTP Access Timing
PARAMETER
MIN
40
MAX UNIT
ta(fp)
Paged flash access time
Random flash access time
OTP access time
ns
ns
ns
ta(fr)
40
ta(OTP)
60
7.14.6 Flash Data Retention Duration
PARAMETER
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX UNIT
tretention
Data retention duration
years
Table 7-2. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT
SYSCLKOUT
(ns)
PAGE
RANDOM
OTP
WAIT-STATE
(MHz)
WAIT-STATE(1)
WAIT-STATE(1)
60
16.67
18.18
20
2
2
1
1
1
1
1
2
2
1
1
1
1
1
3
3
2
2
2
2
1
55
50
45
22.22
25
40
35
28.57
33.33
30
(1) Page and random wait-state must be ≥ 1.
The equations to compute the Flash page wait-state and random wait-state in Table 7-2 are as follows:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(f ·p)
Flash Page Wait State =
-1 round up to the next highest integer
ú
tc(SCO)
ê
ú
û
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(f ×r)
Flash Random Wait State =
-1 round up to the next highest integer, or 1, whichever is larger
ú
tc(SCO)
ê
ú
û
The equation to compute the OTP wait-state in Table 7-2 is as follows:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(OTP)
OTP Wait State =
-1 round up to the next highest integer, or 1, whichever is larger
ú
tc(SCO)
ê
ú
û
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8 Detailed Description
8.1 Overview
8.1.1 CPU
The 2805x (C28x) family is a member of the TMS320C2000™ MCU platform. The C28x-based controllers have
the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based controller, including the
2805x device, is a very efficient C/C++ engine, enabling users to develop not only their system control software
in a high-level language, but also enabling development of math algorithms using C/C++. The device is as
efficient at MCU math tasks as it is at system control tasks. This efficiency removes the need for a second
processor in many systems. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller to handle
higher numerical resolution problems efficiently. Add to this feature the fast interrupt response with automatic
context save of critical registers, resulting in a device that can service many asynchronous events with minimal
latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining
enables the device to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
8.1.2 Control Law Accelerator
The C28x CLA is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by
adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism,
and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a
peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU-Timer 0. The CLA executes one task at a time to
completion. When a task completes the main CPU is notified by an interrupt to the PIE and the CLA
automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result
registers, ePWM, eCAP, eQEP, and the Comparator and DAC registers. Dedicated message RAMs provide a
method to pass additional data between the main CPU and the CLA.
8.1.3 Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.
The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist of
32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations. The
multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data
value and write a data value in a single cycle. All peripherals and memories attached to the memory bus
prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
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8.1.4 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices
adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various
buses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32
data lines and associated control signals. Three versions of the peripheral bus are supported. One version
supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit
accesses (called peripheral frame 1). The third version supports CLA access and both 16- and 32-bit accesses
(called peripheral frame 3).
8.1.5 Real-Time JTAG and Analysis
1
The devices implement the standard IEEE 1149.1 JTAG interface for in-circuit based debug. Additionally, the
devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and
register locations while the processor is running and executing code and servicing interrupts. The user can also
single step through non-time-critical code while enabling time-critical interrupts to be serviced without
interference. The device implements the real-time mode in hardware within the CPU. This feature is unique to
the 28x family of devices, and requires no software monitor. Additionally, special analysis hardware is provided
that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable
break events when a match occurs.
8.1.6 Flash
The F28055 and F28054 devices contain 64K × 16 of embedded flash memory, segregated into six 8K × 16
sectors and four 4K × 16 sectors. The F28053, F28052, and F28051 devices contain 32K × 16 of embedded
flash memory, segregated into three 8K × 16 sectors and two 4K × 16 sectors. The F28050 device contains 16K
× 16 of embedded flash memory, segregated into one 8K × 16 sector and two 4K × 16 sectors. The devices also
contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to 0x3D 7BFF. The user can individually
erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to
use one sector of the flash or the OTP to execute flash algorithms that erase or program other sectors. Special
memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is
mapped to both program and data space; therefore, the flash/OTP can be used to execute code or store data
information.
Note
The Flash and OTP wait-states can be configured by the application. This feature allows applications
running at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the flash pipeline mode is application-dependent.
For more information on the flash options, Flash wait-state, and OTP wait-state registers, see the
System Control and Interrupts chapter of the TMS320x2805x Technical Reference Manual.
1
IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture
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8.1.7 M0, M1 SARAMs
All devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer points to
the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are
mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data
variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the
programmer, which makes for easier programming in high-level languages.
8.1.8 L0 SARAM, and L1, L2, and L3 DPSARAMs
The device contains up to 8K × 16 of single-access RAM. To ascertain the exact size for a given device, see the
device-specific memory map figures in Section 8.2. This block is mapped to both program and data space. Block
L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2 are both 1K in size, and
together with L0, are shared with the CLA which can use these blocks for its data space. Block L3 is 4K in size
and is shared with the CLA which can use this block for its program space. DPSARAM refers to the dual-port
configuration of these blocks.
8.1.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal flash/
ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related
algorithms. Table 8-1 provides the boot mode selection.
Table 8-1. Boot Mode Selection
GPIO34/COMP2OUT/
MODE
GPIO37/TDO
TRST
MODE
COMP3OUT
3
2
1
1
0
0
x
1
0
1
0
x
0
0
0
0
1
GetMode
Wait (see Section 8.1.10 for description)
1
SCI
0
Parallel IO
Emulation Boot
EMU
8.1.9.1 Emulation Boot
When the JTAG debug probe is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this
case, the boot ROM detects that a JTAG debug probe is connected and uses the contents of two reserved
SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,
then the Wait boot option is used. All boot mode options can be accessed in emulation boot.
8.1.9.2 GetMode
The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot
option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash
is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.
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8.1.9.3 Peripheral Pins Used by the Bootloader
Table 8-2 lists the GPIO pins that are used by each peripheral bootloader. See the GPIO mux table to see if
these conflict with any of the peripherals you want to use in your application.
Table 8-2. Peripheral Bootload Pins
BOOTLOADER
PERIPHERAL LOADER PINS
SCI
SCIRXDA (GPIO28)
SCITXDA (GPIO29)
Parallel Boot
SPI
Data (GPIO31,30,5:0)
28x Control (GPIO26)
Host Control (GPIO27)
SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
I2C
SDAA (GPIO28)
SCLA (GPIO29)
CAN
CANRXA (GPIO30)
CANTXA (GPIO31)
8.1.10 Security
The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect user's
firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop application
software with a third-party or subcontractor by preventing visibility into each other's software IP. The security
features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user programs into the
USER-OTP. Each zone has its own dedicated USER-OTP, which must be programmed by the user with the
required security settings, including the 128-bit password. Because OTP cannot be erased, to provide the user
with the flexibility of changing security-related settings and passwords multiple times, a 32-bit link pointer is
stored at the beginning of each USER-OTP. Because the user can only flip a 1 in USER-OTP to 0, the most
significant bit position in the link pointer, programmed as 0, defines the USER-OTP region (zone-select) for each
zone in which security-related settings and passwords are stored. Table 8-3 provides the location of the zone-
select block based on the link pointer. Table 8-4 shows the zone-select block organization in USER-OTP.
Table 8-3. Location of Zone-Select Block Based on Link Pointer
Zx LINK POINTER VALUE
ADDRESS OFFSET FOR ZONE-SELECT
32’bxx111111111111111111111111111111
32’bxx111111111111111111111111111110
32’bxx11111111111111111111111111110x
32’bxx1111111111111111111111111110xx
32’bxx111111111111111111111111110xxx
32’bxx11111111111111111111111110xxxx
32’bxx1111111111111111111111110xxxxx
32’bxx111111111111111111111110xxxxxx
32’bxx11111111111111111111110xxxxxxx
32’bxx1111111111111111111110xxxxxxxx
32’bxx111111111111111111110xxxxxxxxx
32’bxx11111111111111111110xxxxxxxxxx
32’bxx1111111111111111110xxxxxxxxxxx
32’bxx111111111111111110xxxxxxxxxxxx
32’bxx11111111111111110xxxxxxxxxxxxx
32’bxx1111111111111110xxxxxxxxxxxxxx
32’bxx111111111111110xxxxxxxxxxxxxxx
0x10
0x20
0x30
0x40
0x50
0x60
0x70
0x80
0x90
0xa0
0xb0
0xc0
0xd0
0xe0
0xf0
0x100
0x110
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Table 8-3. Location of Zone-Select Block Based on Link Pointer (continued)
Zx LINK POINTER VALUE
ADDRESS OFFSET FOR ZONE-SELECT
32’bxx11111111111110xxxxxxxxxxxxxxxx
32’bxx1111111111110xxxxxxxxxxxxxxxxx
32’bxx111111111110xxxxxxxxxxxxxxxxxx
32’bxx11111111110xxxxxxxxxxxxxxxxxxx
32’bxx1111111110xxxxxxxxxxxxxxxxxxxx
32’bxx111111110xxxxxxxxxxxxxxxxxxxxx
32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx
32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx
32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx
32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx
32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx
32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
0x120
0x130
0x140
0x150
0x160
0x170
0x180
0x190
0x1a0
0x1b0
0x1c0
0x1d0
0x1e0
0x1f0
Table 8-4. Zone-Select Block Organization in USER-OTP
16-BIT ADDRESS OFFSET
(WITH RESPECT TO OFFSET OF ZONE-
SELECT)
CONTENT
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
Zx-EXEONLYRAM
Zx-EXEONLYSECT
Zx-GRABRAM
Zx-GRABSECT
Zx-CSMPSWD0
Zx-CSMPSWD1
Zx-CSMPSWD2
Zx-CSMPSWD3
The Dual Code Security Module (DCSM) is used to protect the flash/OTP/Lx SARAM blocks/CLA/Secure ROM
content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at start-up time.
Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by) one zone do not have
any access to code running in the other zone when it is secured. Individual flash sectors, as well as SARAM
blocks, can be further protected by enabling the EXEONLY protection. EXEONLY flash sectors or SARAM
blocks do not have READ/WRITE access. Only code execution is allowed from such memory blocks.
The security feature prevents unauthorized users from examining memory contents through the JTAG port,
executing code from external memory, or trying to boot load an undesirable software that would export the
secure memory contents. To enable access to the secure blocks of a particular zone, the user must write a 128-
bit value in the CSMKEY registers of the zone; this value must match the values stored in the password
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locations in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all 1s
(unprogrammed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to the
password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case).
In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone to
prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the ECSL and
break the emulation connection. To allow emulation of secure code while maintaining DCSM protection against
secure memory reads, the user must write the lower 64 bits of the USER-OTP password into the CSMKEY
register of the zone to disable the ECSL. Dummy reads of all 128 bits of the password for that particular zone in
USER-OTP must still be performed. If the lower 64 bits of the password locations of a particular zone are all
zeros, then the ECSL for that zone gets disabled as soon as a dummy read is done to the password locations in
USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this case).
When initially debugging a device with the password locations in OTP (that is, secured), the CPU will start
running and may execute an instruction that performs an access to ECSL-protected area. If the CPU execution
is halted when the program counter belongs to the secure code region, the ECSL will trip and cause the JTAG
debug probe connection to be cut. The solution is to use the Wait boot option. The Wait boot option will sit in a
loop around a software breakpoint to allow a JTAG debug probe to be connected without tripping security. The
user can then exit this mode once the JTAG debug probe is connected by using one of the emulation boot
options as described in the Boot ROM chapter of the TMS320x2805x Technical Reference Manual. The 2805x
devices do not support hardware wait-in-reset mode.
To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from looking at
the CPU registers in the CCS Expressions Window. The values in the Expressions Window for all of these
registers, except for PC and some status bits, display false values when code is running from a secure zone.
This feature gets disabled if the zone is unlocked.
Note
•
•
•
The USER-OTP contains security-related settings for their respective zone. Execution is not
allowed from the USER-OTP; therefore, the user should not keep any code/data in this region.
The 128-bit password must not be programmed to zeros. Doing so would permanently lock the
device.
The user must try not to write into the CPU registers through the debugger watch window when
code is running/halted from/inside secure zone. This may corrupt the execution of the actual
program.
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Note
Dual Code Security Module Disclaimer
THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS DESIGNED
TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM
OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE DCSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT
LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF
BUSINESS OR OTHER ECONOMIC LOSS.
8.1.11 Peripheral Interrupt Expansion Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight
CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence the CPU can quickly
respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual
interrupt can be enabled or disabled within the PIE block.
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8.1.12 External Interrupts (XINT1 to XINT3)
The devices support three masked external interrupts (XINT1 to XINT3). Each of the interrupts can be selected
for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled. These
interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time-stamp the interrupt. There are no dedicated pins for the
external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from the GPIO0 to GPIO31 pins.
8.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal
attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling ratios. The
PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower
power operation is desired. See Section 7.13 for timing details. The PLL block can be set in bypass mode.
8.1.14 Watchdog
Each device contains two watchdogs: CPU-watchdog that monitors the core and NMI-watchdog that is a missing
clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time
frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if
necessary. The NMI-watchdog engages only in case of a clock failure and can either generate an interrupt or a
device reset.
8.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to
the CPU clock.
8.1.16 Low-power Modes
The devices are full-static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
must function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer
will wake the processor from IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
This mode basically shuts down the device and places the device in the lowest possible power consumption
mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default.
To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The
zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is
used as the clock source, the crystal oscillator is shut down in this mode. A reset or an external signal (through a
GPIO pin) or the CPU-watchdog can wake the device from this mode.
The CPU clock (OSCCLK) and WDCLK should be from the same clock source before trying to put the device
into HALT or STANDBY.
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8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Waitstate Registers
Flash:
Timers:
DCSM:
ADC:
CLA
CPU-Timers 0, 1, 2 Registers
Dual Zone Security Module Registers
ADC Result Registers
CLA Registers and Message RAMs
GPIO MUX Configuration and Control Registers
eCAN Configuration and Control Registers
eCAP Module and Registers
PF1:
PF2:
GPIO:
eCAN:
eCAP:
eQEP:
SYS:
eQEP Module and Registers
System Control Registers
SCI:
SCI Control and RX/TX Registers
SPI Control and RX/TX Registers
ADC Status, Control, and Configuration Registers
I2C Module and Registers
SPI:
ADC:
I2C:
XINT:
ePWM:
AFE:
External Interrupt Registers
PF3:
ePWM Module and Registers
Comparator Modules, Digital Filters, and PGA Control Registers
eCAP Module and Registers
eCAP:
eQEP:
ADC:
ADC:
DAC:
eQEP Module and Registers
ADC Status, Control, and Configuration Registers
ADC Result Registers
DAC Control Registers
8.1.18 General-Purpose Input/Output Multiplexer
Most of the peripheral signals are multiplexed with GPIO signals. This muxing enables the user to use a pin as
GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can
individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also
select the number of input qualification cycles. This selection is to filter unwanted noise glitches. The GPIO
signals can also be used to bring the device out of specific low-power modes.
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8.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, the counter is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can
be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS™. CPU-Timer 2 is connected to
INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
•
•
•
•
SYSCLKOUT (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTSOC2)
External clock source
8.1.20 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM:
The ePWM peripheral supports independent/complementary PWM generation, adjustable dead-
band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. The type 1
module found on 2805x devices also supports increased dead-band resolution, enhanced SOC and
interrupt generation, and advanced triggering including trip functions based on comparator outputs.
eCAP:
eQEP:
The eCAP peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The eQEP peripheral uses a 32-bit position counter, supports low-speed measurement using
capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog
timer to detect motor stall and input error detection logic to identify simultaneous edge transition in
QEP signals.
ADC:
The ADC block is a 12-bit converter. The ADC has up to 16 single-ended channels pinned out,
depending on the device. The ADC also contains two sample-and-hold units for simultaneous
sampling. Some ADC channels also have PGAs, which can amplify the input signal by 3, 6, or 11.
Comparator and
Digital Filter Subsystems:
Each comparator block consists of one analog comparator along with an internal 6-bit reference for
supplying one input of the comparator. The comparator output signal filtering is achieved using the
digital filter present on each input line and qualifies the output of the COMP/DAC subsystem. The
filtered or unfiltered output of the COMP/DAC subsystem can be configured to be an input to the
Digital Compare submodule of the ePWM peripheral. There is also a configurable option to bring
the output of the COMP/DAC subsystem onto the GPIOs.
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8.1.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used
for communications between the MCU and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and
ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains
a 4-level receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
I2C:
The SCI is a 2-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive
and transmit FIFO for reducing interrupt servicing overhead.
The I2C module provides an interface between an MCU and other devices compliant with Philips
Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit and receive up to 8-bit data to and from the MCU
through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt servicing
overhead.
eCAN:
The eCAN is the enhanced version of the CAN peripheral. The eCAN supports 32 mailboxes, time-stamping
of messages, and is compliant with ISO 11898-1 (CAN 2.0B).
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8.2 Memory Maps
In Figure 8-1, Figure 8-2, Figure 8-3, and Figure 8-4, the following apply:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are
restricted to data memory only. A user program cannot access these memory maps in program space.
Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
•
•
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 1400
Peripheral Frame 0
CLA Registers
0x00 1480
0x00 1500
0x00 1580
0x00 2000
0x00 6000
CLA-to-CPU Message RAM
CPU-to-CLA Message RAM
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 DPSARAM (2K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2)
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)
0x00 A000
0x00 F000
0x01 0000
Reserved
CLA Data ROM (4K ´ 16)
Reserved
0x3D 7800
0x3D 7A00
0x3D 7C00
User OTP, Zone 2 Passwords (512 ´ 16)
User OTP, Zone 1 Passwords (512 ´ 16)
Reserved
0x3D 7E00
0x3D 7FCB
Calibration Data
Configuration Data
Reserved
0x3D 7FF0
0x3E 8000
FLASH
(64K ´ 16, 10 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
Zone 1 Secure Copy Code ROM
(1K ´ 16)
0x3F 8400
Zone 2 Secure Copy Code ROM
(1K ´ 16)
0x3F 8800
0x3F D000
0x3F FFC0
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. CLA-specific registers and RAM apply to the 28055 device only.
Figure 8-1. 28055 and 28054 Memory Map
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 1400
Peripheral Frame 0
CLA Registers
0x00 1480
0x00 1500
0x00 1580
0x00 2000
0x00 6000
CLA-to-CPU Message RAM
CPU-to-CLA Message RAM
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 DPSARAM (2K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2)
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)
0x00 A000
0x00 F000
0x01 0000
Reserved
CLA Data ROM (4K ´ 16)
Reserved
0x3D 7800
0x3D 7A00
0x3D 7C00
User OTP, Zone 2 Passwords (512 ´ 16)
User OTP, Zone 1 Passwords (512 ´ 16)
Reserved
0x3D 7E00
0x3D 7FCB
Calibration Data
Configuration Data
Reserved
0x3D 7FF0
0x3F 0000
FLASH
(32K ´ 16, 5 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
Zone 1 Secure Copy Code ROM
(1K ´ 16)
0x3F 8400
Zone 2 Secure Copy Code ROM
(1K ´ 16)
0x3F 8800
0x3F D000
0x3F FFC0
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
A. CLA-specific registers and RAM apply to the 28053 device only.
Figure 8-2. 28053 and 28052 Memory Map
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 1400
Peripheral Frame 0
CLA Registers
0x00 1480
0x00 1500
0x00 1580
0x00 2000
0x00 6000
CLA-to-CPU Message RAM
CPU-to-CLA Message RAM
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
Reserved
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)
L3 DPSARAM (4K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)
0x00 A000
0x00 F000
0x01 0000
Reserved
CLA Data ROM (4K ´ 16)
Reserved
0x3D 7800
0x3D 7A00
0x3D 7C00
User OTP, Zone 2 Passwords (512 ´ 16)
User OTP, Zone 1 Passwords (512 ´ 16)
Reserved
0x3D 7E00
0x3D 7FCB
Calibration Data
Configuration Data
Reserved
0x3D 7FF0
0x3F 0000
FLASH
(32K ´ 16, 5 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
Zone 1 Secure Copy Code ROM
(1K ´ 16)
0x3F 8400
Zone 2 Secure Copy Code ROM
(1K ´ 16)
0x3F 8800
0x3F D000
0x3F FFC0
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
Figure 8-3. 28051 Memory Map
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Data Space
Prog Space
0x00 0000
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
M0 Vector RAM (Enabled if VMAP = 0)
M0 SARAM (1K ´ 16, 0-Wait)
M1 SARAM (1K ´ 16, 0-Wait)
Peripheral Frame 0
PIE Vector - RAM
(256 ´ 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 1400
Peripheral Frame 0
Reserved
0x00 1580
0x00 2000
0x00 6000
Peripheral Frame 0
Reserved
Peripheral Frame 1
(1K ´ 16, Protected)
0x00 6400
0x00 6A00
0x00 7000
0x00 8000
0x00 8800
0x00 8C00
0x00 9000
Peripheral Frame 3
(1.5K ´ 16, Protected)
Reserved
Peripheral Frame 1
(1.5K ´ 16, Protected)
Peripheral Frame 2
(4K ´ 16, Protected)
L0 DPSARAM (2K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL)
L1 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL)
L2 DPSARAM (1K ´ 16)
(0-Wait, Z1 or Z2 Secure Zone + ECSL)
Reserved
0x00 A000
0x00 F000
0x01 0000
Reserved
Reserved
Reserved
0x3D 7800
0x3D 7A00
0x3D 7C00
User OTP, Zone 2 Passwords (512 ´ 16)
User OTP, Zone 1 Passwords (512 ´ 16)
Reserved
0x3D 7E00
0x3D 7FCB
Calibration Data
Configuration Data
Reserved
0x3D 7FF0
0x3F 4000
FLASH
(16K ´ 16, 3 Sectors, Dual Secure Zone + ECSL)
(Z1/Z2 User-Selectable Security Zone Per Sector)
0x3F 7FFF
0x3F 8000
Zone 1 Secure Copy Code ROM
(1K ´ 16)
0x3F 8400
Zone 2 Secure Copy Code ROM
(1K ´ 16)
0x3F 8800
0x3F D000
0x3F FFC0
Reserved
Boot ROM (12K ´ 16, 0-Wait)
Vector (32 Vectors, Enabled if VMAP = 1)
Figure 8-4. 28050 Memory Map
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Table 8-5, Table 8-6, and Table 8-7 list the addresses of flash sectors on the TMS320F2805x devices.
Table 8-5. Addresses of Flash Sectors in F28055 and F28054
ADDRESS RANGE
0x3E 8000 to 0x3E 8FFF
0x3E 9000 to 0x3E 9FFF
0x3E A000 to 0x3E BFFF
0x3E C000 to 0x3E DFFF
0x3E E000 to 0x3E FFFF
0x3F 0000 to 0x3F 1FFF
0x3F 2000 to 0x3F 3FFF
0x3F 4000 to 0x3F 5FFF
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7FFF
PROGRAM AND DATA SPACE
Sector J (4K × 16)
Sector I (4K × 16)
Sector H (8K × 16)
Sector G (8K × 16)
Sector F (8K × 16)
Sector E (8K × 16)
Sector D (8K × 16)
Sector C (8K × 16)
Sector B (4K × 16)
Sector A (4K × 16)
Table 8-6. Addresses of Flash Sectors in F28053, F28052, and F28051
ADDRESS RANGE
0x3F 0000 to 0x3F 1FFF
0x3F 2000 to 0x3F 3FFF
0x3F 4000 to 0x3F 5FFF
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7FFF
PROGRAM AND DATA SPACE
Sector E (8K × 16)
Sector D (8K × 16)
Sector C (8K × 16)
Sector B (4K × 16)
Sector A (4K × 16)
Table 8-7. Addresses of Flash Sectors in F28050
ADDRESS RANGE
0x3F 4000 to 0x3F 5FFF
0x3F 6000 to 0x3F 6FFF
0x3F 7000 to 0x3F 7FFF
PROGRAM AND DATA SPACE
Sector C (8K × 16)
Sector B (4K × 16)
Sector A (4K × 16)
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Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to
be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks
happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations
will appear in reverse order on the memory bus of the CPU. This action can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The CPU supports a block protection
mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles
are added to align the operations). This mode is programmable, and by default, it protects the selected zones.
The wait-states for the various spaces in the memory map area are listed in Table 8-8.
Table 8-8. Wait-States
AREA
WAIT-STATES (CPU)
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
Peripheral Frame 1
0-wait
Fixed
0-wait
0-wait (writes)
2-wait (reads)
Cycles can be extended by peripheral generated ready.
Back-to-back write operations to Peripheral Frame 1 registers will incur
a 1-cycle stall (1-cycle delay).
Peripheral Frame 2
Peripheral Frame 3
0-wait (writes)
2-wait (reads)
Fixed. Cycles cannot be extended by the peripheral.
0-wait (writes)
Assumes no conflict between CPU and CLA.
Cycles can be extended by peripheral-generated ready.
Assumes no CPU conflicts
2-wait (reads)
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
OTP
0-wait data and program
0-wait data and program
0-wait data and program
0-wait data and program
Programmable
Assumes no CPU conflicts
Assumes no CPU conflicts
Assumes no CPU conflicts
Programmed through the Flash registers.
1-wait is minimum number of wait states allowed.
Programmed through the Flash registers.
1-wait minimum
Flash
Programmable
0-wait Paged min
1-wait Random min
Random ≥ Paged
Flash Password
Boot-ROM
16-wait fixed
0-wait
Wait states of password locations are fixed.
Secure ROM
0-wait
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8.3 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
Peripheral Frame 3:
These are peripherals that are mapped directly to the CPU memory bus. See Table 8-9.
These are peripherals that are mapped to the 32-bit peripheral bus. See Table 8-10.
These are peripherals that are mapped to the 16-bit peripheral bus. See Table 8-11.
These are peripherals that are mapped to CLA in addition to their respective Peripheral Frame. See
Table 8-12.
Table 8-9. Peripheral Frame 0 Registers (1)
NAME
Device Emulation Registers
System Power Control Registers
FLASH Registers(3)
ADDRESS RANGE
0x00 0880 to 0x00 0984
0x00 0985 to 0x00 0987
0x00 0A80 to 0x00 0ADF
0x00 0B00 to 0x00 0B0F
0x00 0B80 to 0x00 0BBF
0x00 0BC0 to 0x00 0BEF
SIZE (×16)
EALLOW PROTECTED(2)
261
3
Yes
Yes
Yes
No
96
16
64
48
ADC registers (0 wait read only)
DCSM Zone 1 Registers
Yes
Yes
DCSM Zone 2 Registers
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
Registers
0x00 0C00 to 0x00 0C3F
64
No
PIE Registers
0x00 0CE0 to 0x00 0CFF
0x00 0D00 to 0x00 0DFF
0x00 1400 to 0x00 147F
0x00 1480 to 0x00 14FF
0x00 1500 to 0x00 157F
32
No
No
PIE Vector Table
256
128
128
128
CLA Registers
Yes
NA
NA
CLA to CPU Message RAM (CPU writes ignored)
CPU to CLA Message RAM (CLA writes ignored)
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Dual Code Security Module.
Table 8-10. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6000 to 0x00 61FF
0x00 6A00 to 0x00 6A1F
0x00 6B00 to 0x00 6B3F
0x00 6F80 to 0x00 6FFF
SIZE (×16)
EALLOW PROTECTED
(1)
eCAN-A Registers
eCAP1 Registers
eQEP1 Registers
GPIO Registers
512
32
No
(1)
64
(1)
128
(1) Some registers are EALLOW protected. See the module reference guide for more information.
Table 8-11. Peripheral Frame 2 Registers
NAME
System Control Registers
ADDRESS RANGE
0x00 7010 to 0x00 702F
0x00 7040 to 0x00 704F
0x00 7050 to 0x00 705F
0x00 7750 to 0x00 775F
0x00 7770 to 0x00 777F
0x00 7060 to 0x00 706F
0x00 7070 to 0x00 707F
0x00 7100 to 0x00 717F
0x00 7900 to 0x00 793F
SIZE (×16)
EALLOW PROTECTED
32
16
16
16
16
16
16
128
64
Yes
No
No
No
No
Yes
SPI-A Registers
SCI-A Registers
SCI-B Registers
SCI-C Registers
NMI Watchdog Interrupt Registers
External Interrupt Registers
ADC Registers
Yes
(1)
(1)
I2C-A Registers
(1) Some registers are EALLOW protected. See the module reference guide for more information.
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Table 8-12. Peripheral Frame 3 Registers
NAME
ADC registers (0 wait read only)
DAC Control Registers
ADDRESS RANGE
0x00 0B00 to 0x00 0B0F
0x00 6400 to 0x00 640F
SIZE (×16)
EALLOW PROTECTED
16
16
No
Yes
DAC, PGA, Comparator, and Filter Enable
Registers
0x00 6410 to 0x00 641F
16
Yes
SWITCH Registers
Digital Filter and Comparator Control Registers
LOCK Registers
0x00 6420 to 0x00 642F
0x00 6430 to 0x00 647F
0x00 64F0 to 0x00 64FF
0x00 6800 to 0x00 683F
0x00 6840 to 0x00 687F
0x00 6880 to 0x00 68BF
0x00 68C0 to 0x00 68FF
0x00 6900 to 0x00 693F
0x00 6940 to 0x00 697F
0x00 6980 to 0x00 69BF
0x00 6A00 to 0x00 6A1F
0x00 6B00 to 0x00 6B3F
16
80
16
64
64
64
64
64
64
64
32
64
Yes
Yes
Yes
(1)
ePWM1 registers
(1)
(1)
(1)
(1)
(1)
(1)
ePWM2 registers
ePWM3 registers
ePWM4 registers
ePWM5 registers
ePWM6 registers
ePWM7 registers
eCAP1 Registers
No
(1)
eQEP1 Registers
(1) Some registers are EALLOW protected. See the module reference guide for more information.
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8.4 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. Table 8-13 defines the registers.
Table 8-13. Device Emulation Registers
ADDRESS
RANGE
EALLOW
PROTECTED
NAME
SIZE (×16)
DESCRIPTION
Device Configuration Register
DEVICECNF
0x0880 to
0x0881
2
Yes
No
PARTID
0x0882
1
PARTID Register
TMS320F28055
TMS320F28054
TMS320F28054M
TMS320F28054F
TMS320F28053
TMS320F28052
TMS320F28052M
TMS320F28052F
TMS320F28051
TMS320F28050
0x0105
0x0104
0x0184
0x0144
0x0103
0x0102
0x0182
0x0142
0x0101
0x0100
REVID(1)
DC1
0x0883
1
2
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMX
0x0000 - Silicon Rev. A - TMS
No
0x0886 to
0x0887
Device Capability Register 1.
Yes
The Device Capability Register is predefined by the part and
can be used to verify features. If any bit is 0 in this register, the
module is not present. See Table 8-14.
DC2
DC3
0x0888 to
0x0889
2
2
Device Capability Register 2.
Yes
Yes
The Device Capability Register is predefined by the part and
can be used to verify features. If any bit is 0 in this register, the
module is not present. See Table 8-15.
0x088A to
0x088B
Device Capability Register 3.
The Device Capability Register is predefined by the part and
can be used to verify features. If any bit is 0 in this register, the
module is not present. See Table 8-16.
(1) Boot-ROM contents changed from Rev. 0 silicon to Rev. A silicon. For more details, see the TMS320x2805x Technical Reference
Manual.
Table 8-14. Device Capability Register 1 (DC1) Field Descriptions (1)
BIT
FIELD
TYPE
DESCRIPTION
31:30
RSVD
R = 0
Reserved
These 8 bits set the PARTNO field value in the PARTID register for the device. They
are readable in the PARTID[7:0] register bits.
29:22
PARTNO
R
21:14
13
12:7
6
RSVD
CLA
RSVD
L3
R = 0
R
Reserved
CLA is present when this bit is set.
Reserved
R = 0
R
L3 is present when this bit is set.
L2 is present when this bit is set.
L1 is present when this bit is set.
L0 is present when this bit is set.
Reserved
5
L2
R
4
L1
R
3
L0
R
2
RSVD
RSVD
R = 0
R = 0
1:0
Reserved
(1) All reserved bits should not be written to, but if any use case demands that reserved bits must be written to, then software must write
the same value that is read back from the reserved bits. These bits are reserved for future enhancements.
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Table 8-15. Device Capability Register 2 (DC2) Field Descriptions (1)
BIT
31:28
27
FIELD
RSVD
eCAN-A
RSVD
EQEP-1
RSVD
ECAP-1
RSVD
I2C-A
TYPE
R = 0
R
DESCRIPTION
Reserved
eCAN-A is present when this bit is set.
Reserved
26:17
16
R = 0
R
eQEP-1 is present when this bit is set.
Reserved
15:13
12
R = 0
R
eCAP-1 is present when this bit is set.
Reserved
11:9
8
R = 0
R
I2C-A is present when this bit is set.
Reserved
7:5
4
RSVD
SPI-A
R = 0
R
SPI-A is present when this bit is set.
Reserved
3
RSVD
SCI-C
SCI-B
R = 0
R
2
SCI-C is present when this bit is set.
SCI-B is present when this bit is set.
SCI-A is present when this bit is set.
1
R
0
SCI-A
R
(1) All reserved bits should not be written to, but if any use case demands that reserved bits must be written to, then software must write
the same value that is read back from the reserved bits. These bits are reserved for future enhancements.
Table 8-16. Device Capability Register 3 (DC3) Field Descriptions (1)
BIT
31:20
19
18
17
16
15
14
13
12:8
7
FIELD
TYPE
DESCRIPTION
RSVD
R = 0
R
Reserved
CTRIPFIL7
CTRIPFIL6
CTRIPFIL5
CTRIPFIL4
CTRIPFIL3
CTRIPFIL2
CTRIPFIL1
RSVD
CTRIPFIL7(B7) is present when this bit is set.
CTRIPFIL6(B6) is present when this bit is set.
CTRIPFIL5(B4) is present when this bit is set.
CTRIPFIL4(A6) is present when this bit is set.
CTRIPFIL3(B1) is present when this bit is set.
CTRIPFIL2(A3) is present when this bit is set.
CTRIPFIL1(A1) is present when this bit is set.
Reserved
R
R
R
R
R
R
R = 0
R = 0
R
RSVD
Reserved
6
ePWM7
ePWM7 is present when this bit is set.
ePWM6 is present when this bit is set.
ePWM5 is present when this bit is set.
ePWM4 is present when this bit is set.
ePWM3 is present when this bit is set.
ePWM2 is present when this bit is set.
ePWM1 is present when this bit is set.
5
ePWM6
R
4
ePWM5
R
3
ePWM4
R
2
ePWM3
R
1
ePWM2
R
0
ePWM1
R
(1) All reserved bits should not be written to, but if any use case demands that reserved bits must be written to, then software must write
the same value that is read back from the reserved bits. These bits are reserved for future enhancements.
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8.5 VREG, BOR, POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage
regulator (VREG) to generate the VDD voltage from the VDDIO supply. This feature eliminates the cost and space
of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brownout
reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
8.5.1 On-chip VREG
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are
required on each VDD pin to stabilize the generated voltage, supplying power to these pins is not needed to
operate the device. Conversely, the VREG can be disabled, if power or redundancy becomes the primary
concern of the application.
8.5.1.1 Using the On-chip VREG
To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating
voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic
will be generated by the VREG. Each VDD pin requires approximately 1.2 μF (minimum) capacitance for proper
regulation of the VREG. These capacitors should be located as close as possible to the VDD pins.
8.5.1.2 Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD
pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high.
8.5.2 On-chip Power-On Reset and Brownout Reset Circuit
The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure.
The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during
device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-
up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled
( VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below its respective
trip point. Additionally, when the internal voltage regulator is enabled, an overvoltage protection circuit will tie
XRS low if the VDD rail rises above its trip point. See Section 7.6 for the various trip points as well as the delay
time for the device to release the XRS pin after the undervoltage or overvoltage condition is removed. Figure 8-5
shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in the
BORCFG register. For details, see the System Control and Interrupts chapter of the TMS320x2805x Technical
Reference Manual.
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In
I/O Pin
Out
(Force Hi-Z When High)
DIR (0 = Input, 1 = Output)
Internal
Weak Pullup
SYSRS
SYSCLKOUT
Sync
Deglitch
Filter
RS
WDRST
C28x
Core
MCLKRS
JTAG
TCK
PLL
+
Clocking
Logic
Detect
Logic
XRS
Pin
VREGHALT
WDRST(A)
PBRS(B)
POR/BOR
Generating
Module
On-Chip
Voltage
Regulator
(VREG)
VREGENZ
A. WDRST is the reset signal from the CPU-watchdog.
B. PBRS is the reset signal from the POR/BOR module.
Figure 8-5. VREG + POR + BOR + Reset Signal Connectivity
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8.6 System Control
This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes.
Table 8-17 lists the PLL, clocking, watchdog, and low-power mode registers.
Table 8-17. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
BORCFG
ADDRESS
0x00 0985
0x00 7010
0x00 7011
0x00 7012
0x00 7013
0x00 7014
0x00 7016
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
0x00 7029
SIZE (×16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BOR Configuration register
XCLK
XCLKOUT Control
PLLSTS
PLL Status register
CLKCTL
Clock Control register
PLLLOCKPRD
INTOSC1TRIM
INTOSC2TRIM
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
PCLKCR3
PLLCR
PLL Lock Period
Internal Oscillator 1 Trim register
Internal Oscillator 2 Trim register
Low-Speed Peripheral Clock Prescaler register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Peripheral Clock Control Register 3
PLL Control register
SCSR
System Control and Status register
Watchdog Counter register
WDCNTR
PCLKCR4
WDKEY
Peripheral Clock Control Register 4
Watchdog Reset Key register
Watchdog Control register
WDCR
(1) All registers in this table are EALLOW protected.
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Figure 8-6 shows the various clock domains that are discussed. Figure 8-7 shows the various clock sources
(both internal and external) that can provide a clock for device operation.
SYSCLKOUT
PCLKCR0/1/3/4
(System Ctrl Regs)
LOSPCP
(System Ctrl Regs)
C28x Core
CLKIN
Clock Enables
LSPCLK
Peripheral
Registers
SPI-A, SCI-A, SCI-B, SCI-C
Clock Enables
I/O
I/O
I/O
I/O
I/O
Peripheral
Registers
eCAP1, eQEP1
/2
Peripheral
Registers
GPIO
Mux
eCAN-A
Clock Enables
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6, ePWM7
Peripheral
Registers
Clock Enables
I2C-A
Peripheral
Registers
Clock Enables
ADC
Registers
9 Ch
12-Bit ADC
Analog
Clock Enables
AFE
AFE
Registers
7 Ch
A. CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as
SYSCLKOUT).
Figure 8-6. Clock and Reset Domains
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CLKCTL[WDCLKSRCSEL]
Internal
OSC 1
(10 MHz)
0
OSC1CLK
OSCCLKSRC1
INTOSC1TRIM Reg(A)
WDCLK
CPU Watchdog
(OSC1CLK on XRS reset)
OSCE
1
CLKCTL[INTOSC1OFF]
1 = Turn OSC Off
CLKCTL[OSCCLKSRCSEL]
CLKCTL[INTOSC1HALT]
1 = Ignore HALT
WAKEOSC
OSC2CLK
0
1
Internal
OSC 2
(10 MHz)
INTOSC2TRIM Reg(A)
OSCCLK
PLL
Missing-Clock-Detect Circuit(B)
(OSC1CLK on XRS reset)
OSCE
CLKCTL[TRM2CLKPRESCALE]
CLKCTL[TMR2CLKSRCSEL]
1 = Turn OSC Off
10
11
CLKCTL[INTOSC2OFF]
Prescale
/1, /2, /4,
/8, /16
SYNC
Edge
Detect
01, 10, 11
CPUTMR2CLK
1 = Ignore HALT
01
1
0
00
CLKCTL[INTOSC2HALT]
SYSCLKOUT
OSCCLKSRC2
CLKCTL[OSCCLKSRC2SEL]
0 = GPIO38
1 = GPIO19
XCLK[XCLKINSEL]
CLKCTL[XCLKINOFF]
0
1
0
GPIO19
or
XCLKIN
GPIO38
XCLKIN
X1
X2
EXTCLK
(Crystal)
OSC
XTAL
WAKEOSC
(Oscillators enabled when this signal is high)
0 = OSC on (default on reset)
1 = Turn OSC off
CLKCTL[XTALOSCOFF]
A. Register loaded from TI OTP-based calibration function.
B. See Section 8.6.4 for details on missing clock detection.
Figure 8-7. Clock Tree
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8.6.1 Internal Zero-Pin Oscillators
The F2805x devices contain two independent internal zero-pin oscillators. By default both oscillators are turned
on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused
oscillators may be powered down by the user. The center frequency of these oscillators is determined by their
respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See
Section 7.13.1 for more information on these oscillators.
8.6.2 Crystal Oscillator Option
The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level signals
applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be connected to
the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it should be used with
X2 and a crystal.
Table 8-18 lists the typical specifications for the external quartz crystal (fundamental mode, parallel resonant).
Furthermore, ESR range = 30 to 150 Ω.
Table 8-18. Typical Specifications for External Quartz Crystal (1)
FREQUENCY (MHz)
Rd (Ω)
2200
470
0
CL1 (pF)
CL2 (pF)
5
18
18
10
15
20
15
15
15
15
0
12
12
(1) Cshunt should be less than or equal to 5 pF.
XCLKIN/GPIO19/38
X1
X2
Rd
Turn off
XCLKIN path
in CLKCTL
register
Crystal
CL1
CL2
Figure 8-8. Using the On-chip Crystal Oscillator
Note
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and
crystal. The value is usually approximately twice the value of the load capacitance of the crystal.
2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers.
3. TI recommends that customers have the resonator/crystal vendor characterize the operation of
their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to
tune the tank circuit. The vendor can also advise the customer regarding the proper tank
component values that will produce proper start-up and stability over the entire operating range.
XCLKIN/GPIO19/38
X1
X2
NC
External Clock Signal
(Toggling 0−V
)
DDIO
Figure 8-9. Using a 3.3-V External Oscillator
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8.6.3 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
The watchdog module can be re-enabled (if needed) after the PLL module has stabilized, which takes 1 ms. The
input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) is at least 50 MHz.
Table 8-19. PLL Settings
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(2) (3)
PLLSTS[DIVSEL] = 0 or 1(1)
OSCCLK/4 (Default)(2)
(OSCCLK × 1)/4
(OSCCLK × 2)/4
(OSCCLK × 3)/4
(OSCCLK × 4)/4
(OSCCLK × 5)/4
(OSCCLK × 6)/4
(OSCCLK × 7)/4
(OSCCLK × 8)/4
(OSCCLK × 9)/4
(OSCCLK × 10)/4
(OSCCLK × 11)/4
(OSCCLK × 12)/4
PLLSTS[DIVSEL] = 2
OSCCLK/2
PLLSTS[DIVSEL] = 3
OSCCLK
0000 (PLL bypass)
0001
(OSCCLK × 1)/2
(OSCCLK × 2)/2
(OSCCLK × 3)/2
(OSCCLK × 4)/2
(OSCCLK × 5)/2
(OSCCLK × 6)/2
(OSCCLK × 7)/2
(OSCCLK × 8)/2
(OSCCLK × 9)/2
(OSCCLK × 10)/2
(OSCCLK × 11)/2
(OSCCLK × 12)/2
(OSCCLK × 1)/1
(OSCCLK × 2)/1
(OSCCLK × 3)/1
(OSCCLK × 4)/1
(OSCCLK × 5)/1
(OSCCLK × 6)/1
(OSCCLK × 7)/1
(OSCCLK × 8)/1
(OSCCLK × 9)/1
(OSCCLK × 10)/1
(OSCCLK × 11)/1
(OSCCLK × 12)/1
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes the PLLSTS[DIVSEL] configuration to /1.) PLLSTS[DIVSEL]
must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic has no effect.
(3) This register is EALLOW protected. For more information, see the System Control and Interrupts chapter of the TMS320x2805x
Technical Reference Manual.
Table 8-20. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/4
/4
/2
/1
The PLL-based clock module provides four modes of operation:
•
INTOSC1 (Internal Zero-pin Oscillator 1): INTOSC1 is the on-chip internal oscillator 1. INTOSC1 can
provide the clock for the Watchdog block, core and CPU-Timer 2.
•
INTOSC2 (Internal Zero-pin Oscillator 2): INTOSC2 is the on-chip internal oscillator 2. INTOSC2 can
provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be
independently chosen for the Watchdog block, core and CPU-Timer 2.
•
•
Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/
resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2
pins. Some devices may not have the X1/X2 pins. See Section 6.2.1 for details.
External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows the on-chip
(crystal) oscillator to be bypassed. The device clocks are generated from an external clock source input on
the XCLKIN pin. The XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected
as GPIO19 or GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables
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this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the
user should disable at boot time.
Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock
source must be disabled (using the CLKCTL register) before switching clocks.
Table 8-21. Possible PLL Configuration Modes
CLKIN AND
PLL MODE
REMARKS
PLLSTS[DIVSEL]
SYSCLKOUT
OSCCLK/4
OSCCLK/2
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL
block is disabled in this mode. The PLL block being disabled can be useful in
reducing system noise and for low-power operation. The PLLCR register must
first be set to 0x0000 (PLL Bypass) before entering this mode. The CPU clock
(CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
PLL Off
3
OSCCLK/1
PLL Bypass is the default PLL configuration upon power-up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL is bypassed but is not turned off.
0, 1
2
OSCCLK/4
OSCCLK/2
PLL Bypass
PLL Enable
3
OSCCLK/1
0, 1
2
OSCCLK × n/4
OSCCLK × n/2
OSCCLK × n/1
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to
the PLLCR the device will switch to PLL Bypass mode until the PLL locks.
3
8.6.4 Loss of Input Clock (NMI-watchdog Function)
The 2805x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1 or INTOSC2),
the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and
PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This
limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz.
When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.
Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or
the NMI-watchdog counter can issue a reset when the counter overflows. In addition to this action, the Missing
Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock
failure and initiate necessary corrective action such as switching over to an alternative clock source (if available)
or initiate a shutdown procedure for the system.
If software does not respond to the clock-fail condition, the NMI-watchdog triggers a reset after a
preprogrammed time interval. Figure 8-10 shows the interrupt mechanisms involved.
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NMIFLG[NMINT]
NMIFLGCLR[NMINT]
Clear
Latch
Set
Clear
XRS
Generate
Interrupt
Pulse
When
Input = 1
NMIFLG[CLOCKFAIL]
1
0
0
Clear
Latch
Set
NMIFLGCLR[CLOCKFAIL]
CLOCKFAIL
NMINT
SYNC?
Clear
SYSCLKOUT
NMICFG[CLOCKFAIL]
NMIFLGFRC[CLOCKFAIL]
XRS
SYSCLKOUT
SYSRS
NMIWDPRD[15:0]
NMIWDCNT[15:0]
See System
Control Section
NMI Watchdog
NMIRS
Figure 8-10. NMI-watchdog
8.6.5 CPU-watchdog Module
The CPU-watchdog module on the 2805x device is similar to the one used on the 281x, 280x, and 283xx
devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this occurrence, the user must disable the
counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that
resets the watchdog counter. Figure 8-11 shows the various functional blocks within the watchdog module.
Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog
reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops
decrementing (that is, the watchdog counter does not change with the limp-mode clock).
Note
The CPU-watchdog is different from the NMI-watchdog. The CPU-watchdog is the legacy watchdog
that is present in all 28x devices.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an
R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully
charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent the
capacitor from getting fully charged. Such a circuit would also help detect failure of the flash memory.
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WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR(7:0)
WDCLK
WDCLK
8-Bit
Watchdog
Counter
CLR
Watchdog
Prescaler
/512
SCSR(WDOVERRIDE)
Clear Counter
Internal
Pullup
WDKEY(7:0)
WDRST
WDINT
Generate
Watchdog
55 + AA
Output Pulse
Good K ey
(512 OSCCLKs)
Key Detector
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
1
0
1
(A)
WDRST
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 8-11. CPU-watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that the
signal can wake the device from STANDBY (if enabled). For more details, see Section 8.7, Low-power Modes
Block.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.
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8.7 Low-power Modes Block
Table 8-22 summarizes the various modes.
Table 8-22. Low-power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, CPU-watchdog interrupt, any
enabled interrupt
IDLE
00
On
On
On
On
XRS, CPU-watchdog interrupt, GPIO
Port A signal, debugger(2)
STANDBY
HALT(3)
01
1X
Off
Off
Off
Off
(CPU-watchdog still running)
Off
(on-chip crystal oscillator and PLL
turned off, zero-pin oscillator and
CPU-watchdog state dependent
on user code.)
XRS, GPIO Port A signal, debugger(2)
CPU-watchdog
,
(1) The EXIT column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits
the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-
power mode will not be exited and the device will go back into the indicated low power mode.
(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.
(3) The WDCLK must be active for the device to go into HALT mode.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block
performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signals will wake the device in the GPIOLPMSEL register. The selected signals are also
qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT Mode:
CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT
mode. The user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. For more information,
see the System Control and Interrupts chapter of the TMS320x2805x Technical Reference Manual.
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8.8 Interrupts
Figure 8-12 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, ePWM, I2C, eCAP, ADC, eQEP, CLA, eCAN)
WDINT
Watchdog
WAKEINT
Sync
LPMINT
XINT1
Low Power Modes
SYSCLKOUT
XINT1
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
INT1
to
INT12
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
Core
GPIOXINT2SEL(4:0)
GPIO0.int
XINT3
TINT0
XINT3
GPIO
MUX
Interrupt Control
XINT3CR(15:0)
XINT3CTR(15:0)
GPIO31.int
GPIOXINT3SEL(4:0)
CPU TIMER 0
CPU TIMER 1
CPU TIMER 2
TINT1
TINT2
INT13
INT14
CPUTMR2CLK
CLOCKFAIL
NMIRS
System Control
(See the System
Control section.)
NMI interrupt with watchdog function
(See the NMI Watchdog section.)
NMI
Figure 8-12. External and PIE Interrupt Sources
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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. Table 8-23 shows the interrupts used by 2805x devices.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine (ISR)
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by
the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not
be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 to TRAP #12 will transfer program control to the ISR corresponding to the
first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the
vector from INT2.1, and so forth.
IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
Figure 8-13. Multiplexing of Interrupts Using the PIE Block
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Table 8-23. PIE MUXed Peripheral Interrupt Vector Table (1)
INTx.8
WAKEINT
(LPM/WD)
0xD4E
Reserved
–
INTx.7
INTx.6
ADCINT9
(ADC)
INTx.5
INTx.4
INTx.3
Reserved
–
INTx.2
ADCINT2
(ADC)
INTx.1
ADCINT1
(ADC)
INT1.y
INT2.y
INT3.y
INT4.y
INT5.y
INT6.y
INT7.y
INT8.y
INT9.y
INT10.y
TINT0
XINT2
XINT1
(TIMER 0)
0xD4C
EPWM7_TZINT
(ePWM7)
0xD5C
EPWM7_INT
(ePWM7)
0xD6C
Reserved
–
Ext. int. 2
0xD48
Ext. int. 1
0xD46
0xD4A
0xD44
0xD42
0xD40
EPWM6_TZINT
(ePWM6)
0xD5A
EPWM5_TZINT
(ePWM5)
0xD58
EPWM4_TZINT
(ePWM4)
0xD56
EPWM3_TZINT
(ePWM3)
0xD54
EPWM2_TZINT
(ePWM2)
0xD52
EPWM1_TZINT
(ePWM1)
0xD50
0xD5E
Reserved
–
EPWM6_INT
(ePWM6)
0xD6A
EPWM5_INT
(ePWM5)
0xD68
EPWM4_INT
(ePWM4)
0xD66
EPWM3_INT
(ePWM3)
0xD64
EPWM2_INT
(ePWM2)
0xD62
EPWM1_INT
(ePWM1)
0xD60
0xD6E
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
ECAP1_INT
(eCAP1)
0xD70
0xD7E
Reserved
–
0xD7C
Reserved
–
0xD7A
0xD78
0xD76
0xD74
0xD72
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
EQEP1_INT
(eQEP1)
0xD80
0xD8E
Reserved
–
0xD8C
Reserved
–
0xD8A
0xD88
0xD86
0xD84
0xD82
Reserved
–
Reserved
–
Reserved
–
Reserved
–
SPITXINTA
(SPI-A)
0xD92
SPIRXINTA
(SPI-A)
0xD9E
Reserved
–
0xD9C
Reserved
–
0xD9A
0xD98
0xD96
0xD94
0xD90
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
0xDAE
Reserved
–
0xDAC
Reserved
–
0xDAA
0xDA8
0xDA6
0xDA4
Reserved
–
0xDA2
0xDA0
SCITXINTC
(SCI-C)
0xDBA
SCIRXINTC
(SCI-C)
0xDB8
Reserved
–
I2CINT2A
(I2C-A)
0xDB2
I2CINT1A
(I2C-A)
0xDBE
Reserved
–
0xDBC
Reserved
–
0xDB6
0xDB4
SCIRXINTB
(SCI-B)
0xDC4
ADCINT3
(ADC)
0xDB0
ECAN1_INTA
(CAN-A)
0xDCA
ECAN0_INTA
(CAN-A)
0xDC8
SCITXINTB
(SCI-B)
0xDC6
ADCINT4
(ADC)
SCITXINTA
(SCI-A)
0xDC2
SCIRXINTA
(SCI-A)
0xDCE
ADCINT8
(ADC)
(ePWM16)
0xDDE
CLA1_INT8
(CLA)
0xDCC
ADCINT7
(ADC)
0xDC0
ADCINT6
(ADC)
ADCINT5
(ADC)
ADCINT2
(ADC)
ADCINT1
(ADC)
(ePWM15)
0xDDC
CLA1_INT7
(CLA)
(ePWM14)
0xDDA
(ePWM13)
0xDD8
(ePWM12)
0xDD6
CLA1_INT4
(CLA)
(ePWM11)
0xDD4
CLA1_INT3
(CLA)
(ePWM10)
0xDD2
(ePWM9)
0xDD0
INT11.y
INT12.y
CLA1_INT6
(CLA)
CLA1_INT5
(CLA)
CLA1_INT2
(CLA)
CLA1_INT1
(CLA)
(ePWM16)
0xDEE
LUF
(ePWM15)
0xDEC
LVF
(ePWM14)
0xDEA
(ePWM13)
0xDE8
(ePWM12)
0xDE6
(ePWM11)
0xDE4
Reserved
–
(ePWM10)
0xDE2
(ePWM9)
0xDE0
Reserved
–
Reserved
–
Reserved
–
Reserved
–
XINT3
(CLA)
(CLA)
Ext. Int. 3
0xDF0
0xDFE
0xDFC
0xDFA
0xDF8
0xDF6
0xDF4
0xDF2
(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be
used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a
peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
a. No peripheral within the group is asserting interrupts.
b. No peripheral interrupts are assigned to the group (for example, PIE group 7).
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Table 8-24. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (×16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control register
PIE, Acknowledge register
PIE, INT1 Group Enable register
PIE, INT1 Group Flag register
PIE, INT2 Group Enable register
PIE, INT2 Group Flag register
PIE, INT3 Group Enable register
PIE, INT3 Group Flag register
PIE, INT4 Group Enable register
PIE, INT4 Group Flag register
PIE, INT5 Group Enable register
PIE, INT5 Group Flag register
PIE, INT6 Group Enable register
PIE, INT6 Group Flag register
PIE, INT7 Group Enable register
PIE, INT7 Group Flag register
PIE, INT8 Group Enable register
PIE, INT8 Group Flag register
PIE, INT9 Group Enable register
PIE, INT9 Group Flag register
PIE, INT10 Group Enable register
PIE, INT10 Group Flag register
PIE, INT11 Group Enable register
PIE, INT11 Group Flag register
PIE, INT12 Group Enable register
PIE, INT12 Group Flag register
Reserved
0x0CFA –
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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8.8.1 External Interrupts
Table 8-25. External Interrupt Registers
NAME
XINT1CR
XINT2CR
XINT3CR
XINT1CTR
XINT2CTR
XINT3CTR
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7078
0x00 7079
0x00 707A
SIZE (×16)
DESCRIPTION
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT1 counter register
1
1
1
1
1
1
XINT2 counter register
XINT3 counter register
Each external interrupt can be enabled, disabled, or qualified using positive, negative, or both positive and
negative edge. For more information, see the System Control and Interrupts chapter of the TMS320x2805x
Technical Reference Manual.
8.8.1.1 External Interrupt Electrical Data/Timing
8.8.1.1.1 External Interrupt Timing Requirements (1)
TEST CONDITIONS
Synchronous
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
(2)
tw(INT)
Pulse duration, INT input low/high
With qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
8.8.1.1.2 External Interrupt Switching Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
t
w(INT)
XINT1, XINT2, XINT3
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 8-14. External Interrupt Timing
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8.9 Peripherals
8.9.1 Control Law Accelerator
8.9.1.1 CLA Device-Specific Information
The CLA extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops
serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system
response and higher frequency control loops. Using the CLA for time-critical tasks frees up the main CPU to
perform other system and communication functions concurently. The following is a list of major features of the
CLA.
•
•
Clocked at the same rate as the main CPU (SYSCLKOUT).
An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.
– Complete bus architecture:
•
•
Program address bus and program data bus
Data address bus, data read bus, and data write bus
– Independent eight-stage pipeline.
– 12-bit program counter (MPC)
– Four 32-bit result registers (MR0–MR3)
– Two 16-bit auxillary registers (MAR0, MAR1)
– Status register (MSTF)
•
Instruction set includes:
– IEEE single-precision (32-bit) floating-point math operations
– Floating-point math with parallel load or store
– Floating-point multiply with parallel add or subtract
– 1/X and 1/sqrt(X) estimations
– Data type conversions.
– Conditional branch and call
– Data load and store operations
•
•
The CLA program code can consist of up to eight tasks or ISRs.
– The start address of each task is specified by the MVECT registers.
– No limit on task size as long as the tasks fit within the CLA program memory space.
– One task is serviced at a time through to completion. There is no nesting of tasks.
– Upon task completion, a task-specific interrupt is flagged within the PIE.
– When a task finishes, the next highest-priority pending task is automatically started.
Task trigger mechanisms:
– C28x CPU through the IACK instruction
– Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:
•
•
•
•
Task1: ADCINT1 or EPWM1_INT
Task2: ADCINT2 or EPWM2_INT
Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT
Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT
– Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT
Memory and Shared Peripherals:
•
– Two dedicated message RAMs for communication between the CLA and the main CPU.
– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.
– The CLA has direct access to the CLA Data ROM that stores the math tables required by the routines in
the CLA Math Library.
– The CLA has direct access to the ADC Result registers, comparator and DAC registers, eCAP, eQEP, and
ePWM registers.
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Peripheral Interrupts
IACK
CLA Control
Registers
ADCINT1 to ADCINT8
EPWM1_INT to EPWM7_INT
ECAP1_INT
CLA_INT1 to CLA_INT8
MIFR
MIOVF
MICLR
MICLROVF
MIFRC
MIER
Main
28x
CPU
INT11
INT12
MPERINT1
to
MPERINT8
PIE
EQEP1_INT
LVF
LUF
CPU Timer 0
MIRUN
Main CPU Read/Write Data Bus
MPISRCSEL1
MVECT1
MVECT2
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
CLA Program Address Bus
CLA Program Data Bus
CLA
Program
Memory
CLA
Data
Memory
Map to CLA or
CPU Space
Map to CLA or
CPU Space
MMEMCFG
MCTL
SYSCLKOUT
CLAENCLK
SYSRS
CLA
Data
ROM
CLA
Shared
Message
RAMs
MEALLOW
CLA Execution
Registers
CLA Data Read Address Bus
ADC
Result
Registers
MPC(12)
MSTF(32)
MR0(32)
MR1(32)
MR2(32)
MR3(32)
CLA Data Read Data Bus
CLA Data Write Address Bus
CLA Data Write Data Bus
Main CPU Read Data Bus
eCAP
Registers
MAR0(32)
MAR1(32)
eQEP
Registers
ePWM
Registers
Comparator
+ DAC
Registers
Figure 8-15. CLA Block Diagram
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8.9.1.2 CLA Register Descriptions
Table 8-26. CLA Control Registers
CLA1
REGISTER NAME
EALLOW
PROTECTED
SIZE (×16)
DESCRIPTION(1)
ADDRESS
MVECT1
MVECT2
MVECT3
MVECT4
MVECT5
MVECT6
MVECT7
MVECT8
MCTL
0x1400
0x1401
0x1402
0x1403
0x1404
0x1405
0x1406
0x1407
0x1410
0x1411
0x1414
0x1420
0x1421
0x1422
0x1423
0x1424
0x1425
0x1426
0x1428
0x142A
0x142B
0x142E
0x1430
0x1434
0x1438
0x143C
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
CLA Interrupt/Task 1 Start Address
CLA Interrupt/Task 2 Start Address
CLA Interrupt/Task 3 Start Address
CLA Interrupt/Task 4 Start Address
CLA Interrupt/Task 5 Start Address
CLA Interrupt/Task 6 Start Address
CLA Interrupt/Task 7 Start Address
CLA Interrupt/Task 8 Start Address
CLA Control register
MMEMCFG
MPISRCSEL1
MIFR
CLA Memory Configure register
Peripheral Interrupt Source Select Register 1
Interrupt Flag register
MIOVF
Interrupt Overflow register
Interrupt Force register
MIFRC
MICLR
Interrupt Clear register
MICLROVF
MIER
Interrupt Overflow Clear register
Interrupt Enable register
MIRUN
Interrupt RUN register
MPC(2)
CLA Program Counter
MAR0(2)
MAR1(2)
MSTF(2)
MR0(2)
–
CLA Aux Register 0
–
CLA Aux Register 1
–
CLA STF register
–
CLA R0H register
MR1(2)
–
CLA R1H register
MR2(2)
–
CLA R2H register
MR3(2)
–
CLA R3H register
(1) All registers in this table are DCSM protected.
(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes
to this register.
Table 8-27. CLA Message RAM
ADDRESS RANGE
0x1480 to 0x14FF
0x1500 to 0x157F
SIZE (×16)
DESCRIPTION
128
CLA to CPU Message RAM
CPU to CLA Message RAM
128
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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8.9.2 Analog Block
8.9.2.1 Analog-to-Digital Converter
8.9.2.1.1 ADC Device-Specific Information
The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-and-
hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog
input channels. The converter can be configured to run with an internal bandgap reference to create true-
voltage-based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-
based conversions.
Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of
conversions from a single trigger. However, the basic principle of operation is centered around the configurations
of individual conversions, called SOCs, or Start-Of-Conversions.
Functions of the ADC module include:
•
•
•
12-bit ADC core with built-in dual sample-and-hold (S/H)
Simultaneous sampling or sequential sampling modes
Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog
voltage is derived by:
– Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external
reference modes.)
Digital Value = 0,
when input £ 0 V
Input Analog Voltage -
VREFLO
Digital Value = 4096 ´
when 0 V < input < 3.3 V
3.3
Digital Value = 4095,
when input ³ 3.3 V
– External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when
using either internal or external reference modes.)
Digital Value = 0,
when input £ 0 V
Input Analog Voltage -
VREFLO
Digital Value = 4096 ´
when 0 V < input <
VREFHI
-
VREFHI VREFLO
Digital Value = 4095,
when input ³
VREFHI
•
•
•
•
Up to 16-channel, multiplexed inputs
16 SOCs, configurable for trigger, sample window, and channel
16 result registers (individually addressable) to store conversion values
Multiple trigger sources
– S/W – software immediate start
– ePWM 1–7
– GPIO XINT2
– CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
– ADCINT1, ADCINT2
•
9 flexible PIE interrupts, can configure interrupt request after any conversion
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
Table 8-28. ADC Configuration and Control Registers
EALLOW
PROTECTE
D
SIZE
(×16)
REGISTER NAME
ADDRESS
DESCRIPTION
ADCCTL1
0x7100
0x7101
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x7110
0x7112
0x7114
0x7115
0x7118
0x711A
0x711C
0x711E
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Yes
Yes
No
Control 1 register
Control 2 register
Interrupt Flag register
ADCCTL2
ADCINTFLG
ADCINTFLGCLR
ADCINTOVF
No
Interrupt Flag Clear register
No
Interrupt Overflow register
ADCINTOVFCLR
INTSEL1N2
No
Interrupt Overflow Clear register
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Interrupt 1 and 2 Selection register
Interrupt 3 and 4 Selection register
Interrupt 5 and 6 Selection register
Interrupt 7 and 8 Selection register
Interrupt 9 Selection register (reserved Interrupt 10 Selection)
SOC Priority Control register
INTSEL3N4
INTSEL5N6
INTSEL7N8
INTSEL9N10
SOCPRICTL
ADCSAMPLEMODE
ADCINTSOCSEL1
ADCINTSOCSEL2
ADCSOCFLG1
ADCSOCFRC1
ADCSOCOVF1
ADCSOCOVFCLR1
Sampling Mode register
Interrupt SOC Selection 1 register (for 8 channels)
Interrupt SOC Selection 2 register (for 8 channels)
SOC Flag 1 register (for 16 channels)
SOC Force 1 register (for 16 channels)
SOC Overflow 1 register (for 16 channels)
SOC Overflow Clear 1 register (for 16 channels)
No
No
No
ADCSOC0CTL to
ADCSOC15CTL
0x7120 to
0x712F
1
Yes
SOC0 Control Register to SOC15 Control register
ADCREFTRIM
ADCOFFTRIM
ADCREV
0x7140
0x7141
0x714F
1
1
1
Yes
Yes
No
Reference Trim register
Offset Trim register
Revision register
Table 8-29. ADC Result Registers (Mapped to PF0)
SIZE
(×16)
EALLOW
PROTECTED
REGISTER NAME
ADCRESULT0 to ADCRESULT15
ADDRESS
DESCRIPTION
0xB00 to
0xB0F
1
No
ADC Result 0 register to ADC Result 15 register
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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0-Wait
Result
Registers
PF0 (CPU)
PF2 (CPU)
SYSCLKOUT
ADCENCLK
ADCINT 1
PIE
ADCINT 9
TINT 0
CPUTIMER 0
CPUTIMER 1
CPUTIMER 2
ADCTRIG 1
ADCTRIG 2
ADCTRIG 3
TINT 1
TINT 2
ADC
Core
12-Bit
ADC
Channels
XINT 2SOC
XINT 2
EPWM 1
EPWM 2
EPWM 3
EPWM 4
EPWM 5
EPWM 6
EPWM 7
ADCTRIG 4
SOCA 1
SOCB 1
SOCA 2
SOCB 2
SOCA 3
SOCB 3
SOCA 4
SOCB 4
SOCA 5
SOCB 5
SOCA 6
SOCB 6
SOCA 7
SOCB 7
ADCTRIG 5
ADCTRIG 6
ADCTRIG 7
ADCTRIG 8
ADCTRIG 9
ADCTRIG 10
ADCTRIG 11
ADCTRIG 12
ADCTRIG 13
ADCTRIG 14
ADCTRIG 15
ADCTRIG 16
ADCTRIG 17
ADCTRIG 18
Figure 8-16. ADC Connections
ADC Connections if the ADC is Not Used
TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
•
•
•
•
VDDA – Connect to VDDIO
VSSA – Connect to VSS
VREFLO – Connect to VSS
ADCINAn, ADCINBn, VREFHI – Connect to VSSA
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSSA).
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.
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8.9.2.1.2 ADC Electrical Data/Timing
8.9.2.1.2.1 ADC Electrical Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS
Resolution
12
Bits
ADC clock
0.5
60
63
63
MHz
28055, 28054, 28053,
28052
10
24
Sample Window (see Table 8-30)
ADC clocks
28051, 28050
ACCURACY
INL (Integral nonlinearity)(1)
–4
–1
4.5
1.5
LSB
LSB
DNL (Differential nonlinearity), no missing codes
Executing a single self-
recalibration(3)
–20
–4
0
0
20
4
Offset error (2)
LSB
Executing periodic self-
recalibration(4)
Overall gain error with internal reference
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ADC temperature coefficient with internal reference
ADC temperature coefficient with external reference
VREFLO
–60
–40
–4
60
40
4
LSB
LSB
LSB
–4
4
LSB
–50
–20
ppm/°C
ppm/°C
µA
–100
100
VREFHI
µA
ANALOG INPUT
Analog input voltage with internal reference
Analog input voltage with external reference
VREFLO input voltage
0
VREFLO
VSSA
3.3
VREFHI
0.66
V
V
V
2.64
VDDA
VDDA
VREFHI input voltage(5)
V
with VREFLO = VSSA
1.98
Input capacitance
5
pF
μA
Input leakage current
±2
(1) INL will degrade when the ADC input voltage goes above VDDA
.
(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external
reference.
(3) For more details, see the TMS320F2805x MCUs Silicon Errata .
(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be
performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset
Calibration" section in the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Technical Reference Manual .
(5) VREFHI must not exceed VDDA when using either internal or external reference modes.
Table 8-30. ACQPS Values (1)
OVERLAP MODE
{9, 10, 23, 36, 49, 62}
{23, 36, 49, 62}
NONOVERLAP MODE
{15, 16, 28, 29, 41, 42, 54, 55}
{15, 16, 28, 29, 41, 42, 54, 55}
Non-PGA
PGA
(1) ACQPS = 6 can be used for the first sample if it is thrown away.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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8.9.2.1.2.2 ADC Power Modes
ADC OPERATING MODE
Mode A – Operating Mode
CONDITIONS
IDDA
UNITS
ADC Clock Enabled
13
mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 1)
Mode B – Quick Wake Mode
Mode C – Comparator-Only Mode
Mode D – Off Mode
ADC Clock Enabled
4
mA
mA
mA
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 1)
ADC Powered Up (ADCPWDN = 0)
ADC Clock Enabled
1.5
Bandgap On (ADCBGPWD = 1)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
ADC Clock Enabled
0.075
Bandgap On (ADCBGPWD = 0)
Reference On (ADCREFPWD = 0)
ADC Powered Up (ADCPWDN = 0)
8.9.2.1.2.3 External ADC Start-of-Conversion Electrical Data/Timing
8.9.2.1.2.3.1 External ADC Start-of-Conversion Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(HCO)
cycles
tw(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 8-17. ADCSOCAO or ADCSOCBO Timing
8.9.2.1.2.4 Internal Temperature Sensor
8.9.2.1.2.4.1 Temperature Sensor Coefficient (1)
PARAMETER(2)
MIN
TYP
0.18(4) (3)
1750
MAX
UNIT
°C/LSB
LSB
Degrees C of temperature movement per measured ADC LSB change
of the temperature sensor
TSLOPE
TOFFSET
ADC output at 0°C of the temperature sensor
(1) The accuracy of the temperature sensor for sensing absolute temperature (temperature in degrees) is not specified. The primary use
of the temperature sensor should be to compensate the internal oscillator for temperature drift (this operation is assured as per Section
7.13.1.3).
(2) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be
adjusted accordingly in external reference mode to the external reference voltage.
(3) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing
temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values
relative to an initial value.
(4) ADC temperature coeffieicient is accounted for in this specification
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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8.9.2.1.2.5 ADC Power-Up Control Bit Timing
8.9.2.1.2.5.1 ADC Power-Up Delays
PARAMETER(1)
Delay time for the ADC to be stable after power up
MIN
MAX
UNIT
td(PWD)
1
ms
(1) Timings maintain compatibility to the ADC module. The 2805x ADC supports driving all 3 bits at the same time td(PWD) ms before first
conversion.
ADCPWDN/
ADCBGPWD/
ADCREFPWD/
ADCENABLE
td(PWD)
Request for ADC
Conversion
Figure 8-18. ADC Conversion Timing
Ron
3.4 kW
Switch
Rs
ADCIN
Cp
Ch
Source
Signal
ac
5 pF
1.6 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 3.4 kW
Sampling Capacitor (Ch): 1.6 pF
Parasitic Capacitance (Cp): 5 pF
Source Resistance (Rs): 50 W
Figure 8-19. ADC Input Impedance Model
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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8.9.2.1.2.6 ADC Sequential and Simultaneous Timings
Analog Input
SOC0 Sample
Window
SOC1 Sample
Window
SOC2 Sample
Window
0
2
12
18
27 28
43
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
ADCRESULT0
SOC0
SOC1
SOC2
2 ADC clocks
Result 0 Latched
ADCRESULT1
EOC0 Pulse
EOC0 Pulse
ADCINTFLG.ADCINTx
Minimum
Conversion 0
1 ADC clock
10 ADC clocks
13 ADC clocks
6
Minimum
Conversion 1
13 ADC clocks
ADC clocks
10 ADC clocks
Figure 8-20. Timing Example for Sequential Mode / Late Interrupt Pulse
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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Analog Input
ADCCLK
SOC0 Sample
Window
SOC1 Sample
Window
SOC2 Sample
Window
0
2
12
27 28
43
18
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
ADCRESULT0
SOC0
SOC1
SOC2
Result 0 Latched
ADCRESULT1
EOC0 Pulse
EOC0 Pulse
ADCINTFLG.ADCINTx
Minimum
Conversion 0
2 ADC clocks
10 ADC clocks
13 ADC clocks
Minimum
6
Conversion 1
13 ADC clocks
ADC clocks
10 ADC clocks
Figure 8-21. Timing Example for Sequential Mode / Early Interrupt Pulse
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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Analog Input A
SOC0 Sample
A Window
SOC2 Sample
A Window
Analog Input B
SOC0 Sample
B Window
SOC2 Sample
B Window
0
2
12
25 27
31
40 43
56
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
ADCRESULT0
ADCRESULT1
ADCRESULT2
2 ADC clocks
Result 0 (B) Latched
EOC0 Pulse
EOC1 Pulse
1 ADC clock
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
Conversion 0 (A)
13 ADC clocks
Conversion 0 (B)
13 ADC clocks
2 ADC clocks
10 ADC clocks
Conversion 1 (A)
13 ADC clocks
19
Minimum
10 ADC clocks
ADC clocks
Figure 8-22. Timing Example for Simultaneous Mode / Late Interrupt Pulse
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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Analog Input A
Analog Input B
SOC0 Sample
A Window
SOC2 Sample
A Window
SOC0 Sample
B Window
SOC2 Sample
B Window
0
2
12
25 27
40
56
ADCCLK
ADCCTL1.INTPULSEPOS
ADCSOCFLG1.SOC0
ADCSOCFLG1.SOC1
ADCSOCFLG1.SOC2
S/H Window Pulse to Core
SOC0 (A/B)
SOC2 (A/B)
Result 0 (A) Latched
ADCRESULT0
ADCRESULT1
ADCRESULT2
2 ADC clocks
Result 0 (B) Latched
EOC0 Pulse
EOC1 Pulse
EOC2 Pulse
ADCINTFLG.ADCINTx
Minimum
Conversion 0 (A)
13 ADC clocks
Conversion 0 (B)
13 ADC clocks
2 ADC clocks
10 ADC clocks
Minimum
10 ADC clocks
19
Conversion 1 (A)
13 ADC clocks
ADC clocks
Figure 8-23. Timing Example for Simultaneous Mode / Early Interrupt Pulse
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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8.9.2.2 Analog Front End
8.9.2.2.1 AFE Device-Specific Information
The AFE contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to
four PGAs, and up to four digital filters. Figure 8-24 and Figure 8-25 show the AFE.
The comparator output signal filtering is achieved using the digital filter present on selective input line and
qualifies the output of the COMP/DAC subsystem (see Figure 8-27). The filtered or unfiltered output of the
COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the ePWM
peripheral.
Note
The analog inputs are brought in through the AFE subsystem rather than through an AIO Mux, which
is not present.
The ADCINSWITCH register is used to control ADC inputs dynamically, and the setting of this register is
separate from the AFE and digital filter initialization.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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VREFHI
VREFHI
A0
VREFOUT/A0
RPD
_
_
COMPB7
DFSS
Amp
Cmp
+
+
Buffered
DAC Output
6-bit DAC
VSSA
B7
PGA
G » 3, 6, or 11
B7
DAC5 6-bit
PFCGND
B0
A2
A4
B2
B0
A2
A4
B2
DAC1 6-bit
COMPA1H
_
_
COMPA1L
Cmp
Cmp
+
+
ADCIN-
SWITCH
A1
DFSS
DFSS
PGA
G » 3, 6, or 11
A1
A3
M1GND
_
_
COMPA3H
DFSS
COMPA3L
DFSS
Cmp
Cmp
+
+
A3
B1
PGA
G » 3, 6, or 11
_
_
M1GND
M1GND
COMPB1H
DFSS
COMPB1L
DFSS
Cmp
Cmp
+
+
PGA
G » 3, 6, or 11
B1
A5
ADCIN-
SWITCH
ADC
DAC2 6-bit
Temp Sensor
A5
ADCCTL1.TEMPCONV
ADCCTL1.REFLOCONV
VREFLO
VREFLO
B5
B5
A7
B3
A7
B3
ADCIN-
SWITCH
GAIN AMP
G » 3
A6
B4
B6
A6
B4
M2GND
M2GND
M2GND
GAIN AMP
G » 3
GAIN AMP
G » 3
B6
ADCIN-
SWITCH
Legend
Cmp - Comparator
DFSS - Comparator Trip/Digital Filter Subsystem Block
GAIN AMP - Fixed Gain Amplifier
PGA - Programmable Gain Amplifier
Figure 8-24. 28055, 28054, 28053, 28052, and 28051 Analog Front End
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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VREFHI
VREFHI
A0
VREFOUT/A0
_
RPD
Amp
+
6-bit DAC
Buffered
DAC Output
VSSA
GAIN AMP
G » 3
B7
B7
PFCGND
B0
A2
A4
B2
B0
A2
A4
B2
DAC1 6-bit
_
_
COMPA1H
DFSS
COMPA1L
DFSS
Cmp
Cmp
+
+
ADCIN-
SWITCH
A1
PGA
G » 3, 6, or 11
A1
A3
M1GND
_
_
COMPA3H
DFSS
COMPA3L
DFSS
Cmp
Cmp
+
+
A3
B1
PGA
G » 3, 6, or 11
_
_
M1GND
M1GND
COMPB1H
DFSS
COMPB1L
DFSS
Cmp
Cmp
+
+
PGA
G » 3, 6, or 11
B1
ADCIN-
SWITCH
ADC
DAC2 6-bit
Temp Sensor
A5
A5
ADCCTL1.TEMPCONV
ADCCTL1.REFLOCONV
VREFLO
VREFLO
B5
B5
A7
B3
A7
B3
ADCIN-
SWITCH
GAIN AMP
G » 3
A6
B4
B6
A6
B4
M2GND
M2GND
M2GND
GAIN AMP
G » 3
GAIN AMP
G » 3
B6
ADCIN-
SWITCH
Legend
Cmp - Comparator
DFSS - Comparator Trip/Digital Filter Subsystem Block
GAIN AMP - Fixed Gain Amplifier
PGA - Programmable Gain Amplifier
Figure 8-25. 28050 Analog Front End
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VREFHI
6-bit
+
DAC
Op Amp
_
RPD
VSSA
VSSA
Figure 8-26. VREFOUT
ePWM 1-7
DCAH
DCAL
COMPxINPEN
ENABLES
D
CTRIPxx0CTLREGISTER
CTRIPEN
C
T
R
I
P
S
E
L
COMPxxPOL
COMPxxH
CTRIPFILCTRL
REGISTER
1
0
Digital Filter
SYSCLK
0
(to all ePWM modules)
1
DCBH
DCBL
COMPxxPOL
COMPxxL
CTRIPBYP
0
CTRIPxxOUTEN
1
0
CTRIPOUTBYP
1
CTRIPOUTxxSTS
CTRIPOUTxxFLG
CTRIPOUTLATEN
0
1
GPIO
MUX
CTRIPOUTPOL
Figure 8-27. Comparator Trip/Digital Filter Subsystem
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8.9.2.2.2 AFE Register Descriptions
Table 8-31. DAC Control Registers
EALLOW
PROTECTE
D
SIZE
(×16)
REGISTER NAME
ADDRESS
DESCRIPTION
DAC1CTL
0x6400
0x6401
0x6404
0x6405
1
1
1
1
Yes
Yes
Yes
Yes
DAC1 Control register
DAC2 Control register
DAC5 Control register
DAC2CTL
DAC5CTL
VREFOUTCTL
VREF Output Control Register
Table 8-32. DAC, PGA, Comparator, and Filter Enable Registers
EALLOW
PROTECTE
D
SIZE
(×16)
REGISTER NAME
ADDRESS
DESCRIPTION
DACEN
0x6410
0x6411
0x6412
0x6413
0x6414
0x6416
1
1
1
1
1
1
Yes
Yes
Yes
Yes
Yes
Yes
DAC Enables register
VREFOUTEN
PGAEN
VREF Out Enable Register
Programmable Gain Amplifier Enable register
Comparator Enable register
COMPEN
AMPM1_GAIN
AMP_PFC_GAIN
Motor Unit 1 PGA Gain Controls register
PFC PGA Gain Controls register
Table 8-33. SWITCH Registers
EALLOW
SIZE
REGISTER NAME
ADDRESS
PROTECTE
(×16)
DESCRIPTION
D
ADCINSWITCH
Reserved
0x6421
1
7
1
Yes
Yes
Yes
ADC Input-Select Switch Control register
Reserved
0x6422 to
0x6428
COMPHYSTCTL
0x6429
Comparator Hysteresis Control register
Table 8-34. Digital Filter and Comparator Control Registers
EALLOW
PROTECTE
D
SIZE
(×16)
REGISTER NAME
ADDRESS
DESCRIPTION
CTRIPA1ICTL
CTRIPA1FILCTL
CTRIPA1FILCLKCTL
Reserved
0x6430
0x6431
0x6432
0x6433
0x6434
0x6435
0x6436
0x6437
0x6438
0x6439
0x643A
0x643B
0x643C
0x643D
0x643E
0x643F
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
CTRIPA1 Filter Input and Function Control register
CTRIPA1 Filter Parameters register
CTRIPA1 Filter Sample Clock Control register
Reserved
CTRIPA3ICTL
CTRIPA3FILCTL
CTRIPA3FILCLKCTL
Reserved
CTRIPA3 Filter Input and Function Control register
CTRIPA3 Filter Parameters register
CTRIPA3 Filter Sample Clock Control register
Reserved
CTRIPB1ICTL
CTRIPB1FILCTL
CTRIPB1FILCLKCTL
Reserved
CTRIPB1 Filter Input and Function Control register
CTRIPB1 Filter Parameters register
CTRIPB1 Filter Sample Clock Control register
Reserved
Reserved
Reserved
CTRIPM1OCTL
CTRIPM1STS
CTRIPM1FLGCLR
CTRIPM1 CTRIP Filter Output Control register
CTRIPM1 CTRIPxx Outputs Status register
CTRIPM1 CTRIPxx Flag Clear register
0x6440 to
0x645F
Reserved
16
Yes
Reserved
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SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
Table 8-34. Digital Filter and Comparator Control Registers (continued)
EALLOW
PROTECTE
D
SIZE
(×16)
REGISTER NAME
ADDRESS
DESCRIPTION
0x6460 to
0x646F
Reserved
16
Yes
Reserved
CTRIPB7ICTL
0x6470
0x6471
0x6472
1
1
1
Yes
Yes
Yes
CTRIPB7 Filter Input and Function Control register
CTRIPB7 Filter Parameters register
CTRIPB7FILCTL
CTRIPB7FILCLKCTL
CTRIPB7 Filter Sample Clock Control register
0x6473 to
0x647B
Reserved
9
Yes
Reserved
Reserved
0x647C
0x647D
0x647E
0x647F
1
1
1
1
Yes
Yes
Yes
Yes
Reserved
CTRIPPFCOCTL
CTRIPPFCSTS
CTRIPPFCFLGCLR
CTRIPPFC CTRIPxx Outputs Status register
CTRIPPFC CTRIPxx Flag Clear register
CTRIPPFC COMP Test Control register
Table 8-35. LOCK Registers
EALLOW
SIZE
REGISTER NAME
ADDRESS
PROTECTE
(×16)
DESCRIPTION
D
LOCKCTRIP
Reserved
0x64F0
0x64F1
0x64F2
0x64F3
0x64F4
0x64F5
0x64F6
1
1
1
1
1
1
1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Lock Register for CTRIP Filters register
Reserved
LOCKDAC
Lock Register for DACs register
Reserved
Reserved
LOCKAMPCOMP
Reserved
Lock Register for Amplifiers and Comparators register
Reserved
LOCKSWITCH
Lock Register for Switches register
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8.9.2.2.3 PGA Electrical Data/Timing
Table 8-36. Op-Amp Linear Output and ADC Sampling Time Across Gain Settings
MINIMUM
EQUIVALENT GAIN FROM
INPUT TO OUTPUT
LINEAR OUTPUT RANGE
OF OP-AMP
ADC SAMPLING TIME
TO ACHIEVE SETTLING
ACCURACY
INTERNAL RESISTOR RATIO
10
5
11
6
0.6 V to VDDA – 0.6 V
0.6 V to VDDA – 0.6 V
0.6 V to VDDA – 0.6 V
384 ns (ACQPS = 23)
384 ns (ACQPS = 23)
384 ns (ACQPS = 23)
2
3
Table 8-37. PGA Gain Stage: DC Accuracy Across Gain Settings
COMPENSATED
GAIN-ERROR ACROSS
COMPENSATED INPUT
OFFSET-ERROR ACROSS
EQUIVALENT GAIN FROM
INPUT TO OUTPUT
INTERNAL RESISTOR RATIO
TEMPERATURE AND SUPPLY TEMPERATURE AND SUPPLY
VARIATIONS
VARIATIONS IN mV
10
5
11
6
< ±2.5%
< ±8 mV
< ±1.5%
< ±8 mV
2
3
< ±1.0%
< ±8 mV
8.9.2.2.4 Comparator Block Electrical Data/Timing
8.9.2.2.4.1 Electrical Characteristics of the Comparator/DAC
PARAMETER
MIN
TYP
MAX
UNITS
Comparator
Comparator Input Range
VSSA – VDDA
V
Comparator response time to PWM Trip Zone (Async)
Comparator large step response time to PWM Trip Zone (Async)
65
95
ns
ns
DAC
DAC Output Range
DAC resolution
DAC Gain
VDDA / 26 – VDDA
V
6
–1.5%
10
bits
DAC Offset
Monotonic
mV
Yes
INL
0.2
LSB
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8.9.2.2.5 VREFOUT Buffered DAC Electrical Data
8.9.2.2.5.1 Electrical Characteristics of VREFOUT Buffered DAC
PARAMETER
MIN
TYP
MAX
UNITS
LSB
VREFOUT Programmable Range
VREFOUT resolution
VREFOUT Gain
6
56
6
–1.5%
10
bits
VREFOUT Offset
Monotonic
mV
Yes
INL
±0.2
LSB
kΩ
3
Load
RPD
100
pF
20
kΩ
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8.9.3 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as
level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
Zero error is the difference between the ideal input voltage and the actual input voltage that just causes a
transition from an output code of zero to an output code of one.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion
Signal-to-noise ratio + distortion (SINAD) is the ratio of the rms value of the measured input signal to the rms
sum of all other spectral components below the Nyquist frequency, including harmonics but excluding DC. The
value for SINAD is expressed in decibels.
Effective Number of Bits
(SINAD -1.76)
N =
6.02
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the formula
it is possible to get a measure of performance expressed as N, the effective number of bits (ENOB). Thus, the
ENOB for a device for sine wave inputs at a given input frequency can be calculated directly from its measured
SINAD.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of the first nine harmonic components to the rms
value of the measured input signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range
Spurious free dynamic range (SFDR) is the difference in dB between the rms amplitude of the input signal and
the peak spurious signal.
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8.9.4 Serial Peripheral Interface
8.9.4.1 SPI Device-Specific Information
The device includes the four-pin SPI module. The SPI is a high-speed, synchronous serial I/O port that allows a
serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or
another processor. Typical applications include external I/O or peripheral expansion through devices such as
shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave
operation of the SPI.
The SPI module features include:
•
Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to127
when SPIBRR = 0,1, 2
(SPIBRR + 1)
LSPCLK
4
Baud rate =
•
•
Data word length: 1 to 16 data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
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Enhanced feature:
•
•
•
•
4-level transmit/receive FIFO
Delayed transmit control
Bi-directional 3-wire SPI mode support
Audio data receive support through SPISTE inversion
Figure 8-28 is a block diagram of the SPI in slave mode.
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO Registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
-----
SPIINT
RX FIFO Interrupt
RX Interrupt
Logic
RX FIFO _3
16
SPIRXBUF
Buffer Register
SPIFFOVF
FLAG
SPIFFRX.15
To CPU
TX FIFO Registers
SPITXBUF
TX FIFO _3
TX Interrupt
Logic
TX FIFO Interrupt
-----
TX FIFO _1
SPITX
TX FIFO _0
16
SPI INT
ENA
16
SPI INT FLAG
SPITXBUF
Buffer Register
SPISTS.6
SPICTL.0
TRIWIRE
SPIPRI.0
16
M
S
M
SPIDAT
Data Register
TW
S
SW1
SW2
SPISIMO
SPISOMI
M
S
TW
SPIDAT.15 - 0
M
S
TW
STEINV
SPIPRI.1
Talk
STEINV
SPICTL.1
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
LSPCLK
SPICCR.3 - 0
S
SW3
3
2
1
0
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
SPIBRR.6 - 0
SPICCR.6
SPICTL.3
SPICLK
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 8-28. SPI Module Block Diagram (Slave Mode)
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8.9.4.2 SPI Register Descriptions
The SPI port operation is configured and controlled by the registers listed in Table 8-38.
Table 8-38. SPI-A Registers
NAME
SPICCR
SPICTL
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
SIZE (×16) EALLOW PROTECTED
DESCRIPTION(1)
SPI-A Configuration Control register
SPI-A Operation Control register
SPI-A Status register
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Baud Rate register
SPI-A Receive Emulation Buffer register
SPI-A Serial Input Buffer register
SPI-A Serial Output Buffer register
SPI-A Serial Data register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit register
SPI-A FIFO Receive register
SPI-A FIFO Control register
SPI-A Priority Control register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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8.9.4.3 SPI Master Mode Electrical Data/Timing
Section 8.9.4.3.1 lists the master mode timing (clock phase = 0) and Section 8.9.4.3.2 lists the master mode
timing (clock phase = 1). Figure 8-29 and Figure 8-30 show the timing waveforms.
8.9.4.3.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
BRR EVEN
MIN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
+
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
–
3
4
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
5
0.5tc(SPC)M – 10
Setup time, SPISOMI before
SPICLK
8
26
0
26
0
Hold time, SPISOMI valid after
SPICLK
9
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M –
3tc(SYSCLK) – 10
23
24
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 8-29. SPI Master Mode External Timing (Clock Phase = 0)
8.9.4.3.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
BRR EVEN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M
–
0.5tc(SPC)M
–
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
26
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
+
3
6
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
26
Hold time, SPISOMI valid after
SPICLK
0
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
0.5tc(SPC) – 10
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 8-30. SPI Master Mode External Timing (Clock Phase = 1)
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8.9.4.4 SPI Slave Mode Electrical Data/Timing
Section 8.9.4.4.1 lists the slave mode timing (clock phase = 0) and Section 8.9.4.4.2 lists the slave mode timing
(clock phase = 1). Figure 8-31 and Figure 8-32 show the timing waveforms.
8.9.4.4.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (4) (3) (5)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
21
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 8-31. SPI Slave Mode External Timing (Clock Phase = 0)
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8.9.4.4.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
21
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 8-32. SPI Slave Mode External Timing (Clock Phase = 1)
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8.9.5 Serial Communications Interface
8.9.5.1 SCI Device-Specific Information
The 2805x devices include three SCI modules (SCI-A, SCI-B, SCI-C). Each SCI module supports digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
Baud rate =
16
•
Data-word format
– One start bit
– Data-word length programmable from 1 to 8 bits
– Optional even/odd/no parity bit
– 1 or 2 stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ format
•
•
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
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Enhanced features:
•
•
Auto baud-detect hardware logic
4-level transmit/receive FIFO
Figure 8-33 shows the SCI module block diagram.
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TXENA
SCICTL1.1
TXSHF
SCITXD
Register
Frame
Format and Mode
8
Parity
Even/Odd
TXEMPTY
0
1
SCICTL2.6
SCICCR.6
8
Enable
TX FIFO_0
TX FIFO_1
TXINT
To CPU
SCICCR.5
TX Interrupt
Logic
TX FIFO Interrupts
8
TX FIFO_N
TXINTENA
SCICTL2.0
TXRDY
8
1
0
TXWAKE
SCICTL2.7
SCICTL1.3
SCI TX Interrupt Select Logic
8
WUT
Transmit Data
Buffer Register
SCITXBUF.7-0
Auto Baud Detect Logic
RXENA
Baud Rate
MSB/LSB
Registers
SCICTL1.0
LSPCLK
RXSHF
Register
SCIRXD
SCIHBAUD.15-8
SCILBAUD.7-0
RXWAKE
8
SCIRXST.1
0
1
8
SCIFFENA
SCIFFTX.14
RX FIFO_0
RX FIFO_1
RXINT
To CPU
8
RX FIFO Interrupts
RX Interrupt
Logic
RX FIFO_N
RXFFOVF
8
1
SCIFFRX.15
0
RXBKINTENA
SCICTL2.1
RXRDY
SCIRXST.6
RXENA
BRKDT
RXERRINTENA
SCICTL1.6
SCICTL1.0
SCIRXST.5
SCI RX Interrupt Select Logic
8
SCIRXST.5-2
BRKDT FE OE PE
RXERROR
Receive Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.7
Figure 8-33. SCI Module Block Diagram
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8.9.5.2 SCI Register Descriptions
The SCI port operation is configured and controlled by the registers listed in Table 8-39, Table 8-40, and Table
8-41.
Table 8-39. SCI-A Registers (1)
EALLOW
PROTECTED
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
SCICCRA
SCICTL1A
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
No
SCI-A Communications Control register
SCI-A Control Register 1
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud register, high bits
SCI-A Baud register, low bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status register
SCI-A Receive Emulation Data Buffer register
SCI-A Receive Data Buffer register
SCI-A Transmit Data Buffer register
SCI-A FIFO Transmit register
SCI-A FIFO Receive register
SCI-A FIFO Control register
SCI-A Priority Control register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. All 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 8-40. SCI-B Registers (1)
EALLOW
PROTECTED
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
SCICCRB
SCICTL1B
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
No
SCI-B Communications Control register
SCI-B Control Register 1
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud register, high bits
SCI-B Baud register, low bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status register
SCI-B Receive Emulation Data Buffer register
SCI-B Receive Data Buffer register
SCI-B Transmit Data Buffer register
SCI-B FIFO Transmit register
SCI-B FIFO Receive register
SCI-B FIFO Control register
SCI-B Priority Control register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. All 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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Table 8-41. SCI-C Registers (1)
EALLOW
PROTECTED
NAME
ADDRESS
SIZE (×16)
DESCRIPTION
SCICCRC
SCICTL1C
0x7770
0x7771
0x7772
0x7773
0x7774
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
1
1
1
1
1
1
1
1
1
1
1
1
1
No
No
No
No
No
No
No
No
No
No
No
No
No
SCI-C Communications Control register
SCI-C Control Register 1
SCIHBAUDC
SCILBAUDC
SCICTL2C
SCI-C Baud register, high bits
SCI-C Baud register, low bits
SCI-C Control Register 2
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC(2)
SCIFFRXC(2)
SCIFFCTC(2)
SCIPRIC
SCI-C Receive Status register
SCI-C Receive Emulation Data Buffer register
SCI-C Receive Data Buffer register
SCI-C Transmit Data Buffer register
SCI-C FIFO Transmit register
SCI-C FIFO Receive register
SCI-C FIFO Control register
SCI-C Priority Control register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. All 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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8.9.6 Enhanced Controller Area Network
8.9.6.1 eCAN Device-Specific Information
The CAN module (eCAN-A) has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit timestamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
Low-power mode
Programmable wakeup on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
•
•
•
•
•
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps.
The F2805x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
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eCAN0INT
eCAN1INT
Controls Address
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 ´ 32-Bit Words
Message Objects Control
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 8-34. eCAN Block Diagram and Interface Circuit
Table 8-42. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
SN65HVD234
SN65HVD235
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–
Yes
–
Sleep
Yes
–
None
None
None
None
None
None
–
None
None
–
Standby
Standby and Sleep
Standby
Adjustable
Adjustable
Adjustable
Diagnostic Loopback
–
Autobaud Loopback
Built-in Isolation
Low Prop Delay
ISO1050
3–5.5 V
None
None
None
Thermal Shutdown
Failsafe Operation
Dominant Time-Out
–55°C to 105°C
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eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
Control and Status Registers
6000h
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
603Fh
6040h
Local Acceptance Masks (LAM)
(32 ´ 32-Bit RAM)
607Fh
6080h
Master Control - CANMC
Message Object Time Stamps (MOTS)
(32 ´ 32-Bit RAM)
Bit-Timing Configuration - CANBTC
60BFh
60C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 ´ 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
60FFh
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
6108h-610Fh
6110h-6117h
6118h-611Fh
6120h-6127h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
61E8h-61EFh
61F0h-61F7h
61F8h-61FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
61E8h-61E9h
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
Figure 8-35. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled if the
eCAN RAM (LAM, MOTS, MOTO, and mailbox RAM) is used as general-purpose RAM.
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8.9.6.2 eCAN Register Descriptions
The CAN registers listed in Table 8-43 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 8-43. CAN Register Map (1)
eCAN-A
REGISTER NAME
SIZE (×32)
DESCRIPTION
ADDRESS
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
CANME
CANMD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Timestamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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8.9.7 Inter-Integrated Circuit
8.9.7.1 I2C Device-Specific Information
The device contains one I2C serial port. Figure 8-36 shows how the I2C peripheral module interfaces within the
device.
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 4-word receive FIFO and one 4-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
•
•
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
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I2C Module
I2CXSR
I2CDXR
TX FIFO
RX FIFO
FIFO Interrupt to
CPU/PIE
SDA
Peripheral Bus
I2CRSR
I2CDRR
Control/Status
Registers
CPU
Clock
Synchronizer
SCL
Prescaler
Noise Filters
Arbitrator
Interrupt to
CPU/PIE
I2C INT
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 8-36. I2C Peripheral Module Interfaces
8.9.7.2 I2C Register Descriptions
The registers in Table 8-44 configure and control the I2C port operation.
Table 8-44. I2C-A Registers
EALLOW
PROTECTED
NAME
ADDRESS
DESCRIPTION
I2C own address register
I2COAR
I2CIER
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
–
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
–
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8.9.7.3 I2C Electrical Data/Timing
Section 8.9.7.3.1 shows the I2C timing requirements. Section 8.9.7.3.2 shows the I2C switching characteristics.
8.9.7.3.1 I2C Timing Requirements
MIN
MAX UNIT
Hold time, START condition, SCL fall delay
after SDA fall
th(SDA-SCL)START
tsu(SCL-SDA)START
0.6
µs
Setup time, Repeated START, SCL rise
before SDA fall delay
0.6
µs
th(SCL-DAT)
tsu(DAT-SCL)
tr(SDA)
Hold time, data after SCL fall
Setup time, data before SCL rise
Rise time, SDA
0
100
20
µs
ns
Input tolerance
Input tolerance
Input tolerance
Input tolerance
300
300
300
300
ns
ns
ns
ns
tr(SCL)
Rise time, SCL
20
tf(SDA)
Fall time, SDA
11.4
11.4
tf(SCL)
Fall time, SCL
Setup time, STOP condition, SCL rise before
SDA rise delay
tsu(SCL-SDA)STOP
0.6
µs
8.9.7.3.2 I2C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
fSCL
SCL clock frequency
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
400
kHz
Vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
V
Low level output voltage
3 mA sink current
0
0.4
V
tLOW Low period of SCL clock
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
1.3
μs
tHIGH High period of SCL clock
I2C clock module frequency is from 7 MHz to
12 MHz and I2C prescaler and clock divider
registers are configured appropriately.
0.6
μs
lI
Input current with an input voltage from
0.1 VDDIO to 0.9 VDDIO MAX
–10
10
μA
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8.9.8 Enhanced Pulse Width Modulator
8.9.8.1 ePWM Device-Specific Information
The devices contain up to seven enhanced PWM modules (ePWM1 to ePWM7). Figure 8-37 shows a block
diagram of multiple ePWM modules. Figure 8-38 shows the signal interconnections with the ePWM. For more
details, see the Enhanced Pulse Width Modulator (ePWM) Module chapter of the TMS320x2805x Technical
Reference Manual .
EPWMSYNCI
EPWM1SYNCI
EPWM1B
EPWM1TZINT
EPWM1
Module
TZ1 to TZ3
EPWM1INT
EPWM2TZINT
EPWM2INT
EQEP1ERR
CLOCKFAIL
EMUSTOP
TZ4
TZ5
TZ6
PIE
EPWMxTZINT
EPWMxINT
EPWM1ENCLK
TBCLKSYNC
eCAPI
EPWM1SYNCO
EPWM2SYNCI
EPWM1SYNCO
TZ1 to TZ3
EPWM2B
EPWM2
Module
CTRIP
Output
Subsystem
CTRIPxx
EQEP1ERR
CLOCKFAIL
EMUSTOP
EPWM1A
EPWM2A
TZ4
TZ5
TZ6
EPWM2ENCLK
TBCLKSYNC
EPWMxA
G
P
I
EPWM2SYNCO
O
M
U
X
SOCA1
SOCB1
SOCA2
SOCB2
SOCAx
SOCBx
ADC
EPWMxB
EPWMxSYNCI
TZ1 to TZ3
EPWMx
Module
EQEP1ERR
CLOCKFAIL
EMUSTOP
EQEP1ERR
TZ4
TZ5
TZ6
eQEP1
EPWMxENCLK
TBCLKSYNC
System Control
C28x CPU
SOCA1
SOCA2
SPCAx
ADCSOCAO
ADCSOCBO
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
SOCB1
SOCB2
SPCBx
Pulse Stretch
(32 SYSCLKOUT Cycles, Active-Low Output)
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Figure 8-37. ePWM
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Time-Base (TB)
CTR=ZERO
Sync
In/Out
TBPRD Shadow (24)
CTR=CMPB
Select
EPWMxSYNCO
Mux
Disabled
TBPRD Active (24)
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
EPWMxSYNCI
DCAEVT1.sync
DCBEVT1.sync
Counter
Up/Down
(16 Bit)
TBCTL[SWFSYNC]
(Software Forced
Sync)
CTR=ZERO
CTR_Dir
TCBNT
Active (16)
CTR=PRD
CTR=ZERO
EPWMxINT
CTR=PRD or ZERO
CTR=CMPA
Event
Trigger
and
Interrupt
(ET)
16
EPWMxSOCA
Phase
Control
CTR=CMPB
CTR_Dir
(A)
DCAEVT1.soc
(A)
TBPHS Active (24)
EPWMxSOCB
EPWMxSOCA
ADC
DCBEVT1.soc
EPWMxSOCB
Action
Qualifier
(AQ)
CTR=CMPA
16
CMPA Active (24)
CMPA Shadow (24)
EPWMxA
EPWMA
EPWMB
PWM
Chopper
(PC)
Trip
Zone
(TZ)
Dead
Band
(DB)
CTR=CMPB
16
EPWMxB
EPWMxTZINT
TZ1 to TZ3
CMPB Active (16)
CMPB Shadow (16)
EMUSTOP
CLOCKFAIL
CTR=ZERO
EQEP1ERR
DCAEVT1.inter
DCBEVT1.inter
(A)
(A)
(A)
(A)
DCAEVT1.force
DCAEVT2.force
DCBEVT1.force
DCBEVT2.force
DCAEVT2.inter
DCBEVT2.inter
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A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ
signals.
Figure 8-38. ePWM Submodules Showing Critical Internal Signal Interconnections
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8.9.8.2 ePWM Register Descriptions
Table 8-45 and Table 8-46 show the complete ePWM register set per module.
Table 8-45. ePWM1–ePWM4 Control and Status Registers
SIZE (×16) /
#SHADOW
NAME
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
Time Base Control register
TBCTL
TBSTS
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6806
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6811
0x6812
0x6813
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6846
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6851
0x6852
0x6853
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6886
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x6891
0x6892
0x6893
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C6
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
0x68D1
0x68D2
0x98D3
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Time Base Status register
Reserved
TBPHS
TBCTR
TBPRD
Reserved
CMPCTL
Reserved
CMPA
Reserved
Time Base Phase register
Time Base Counter register
Time Base Period Register Set
Reserved
Counter Compare Control register
Reserved
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control register for output A
Action Qualifier Control register for output B
Action Qualifier Software Force register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control register
Dead-Band Generator Rising Edge Delay Count register
Dead-Band Generator Falling Edge Delay Count register
Trip Zone Select register(1)
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
TZDCSEL
TZCTL
Trip Zone Digital Compare register
Trip Zone Control register(1)
TZEINT
TZFLG
Trip Zone Enable Interrupt register(1)
Trip Zone Flag register (1)
TZCLR
Trip Zone Clear register(1)
TZFRC
ETSEL
Trip Zone Force register(1)
Event Trigger Selection register
Event Trigger Prescale register
Event Trigger Flag register
ETPS
ETFLG
ETCLR
Event Trigger Clear register
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Table 8-45. ePWM1–ePWM4 Control and Status Registers (continued)
SIZE (×16) /
#SHADOW
NAME
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
Event Trigger Force register
ETFRC
PCCTL
0x681D
0x681E
0x6820
0x6821
0x6826
0x6828
0x682A
0x682B
0x682C
0x682D
0x6830
0x6831
0x6832
0x6833
0x6834
0x6835
0x6836
0x6837
0x6838
0x6839
0x685D
0x685E
0x6860
-
0x689D
0x689E
0x68A0
-
0x68DD
0x68DE
0x68E0
-
1 / 0
1 / 0
PWM Chopper Control register
Reserved
Reserved
1 / 0
Reserved
1 / 0
Reserved
Reserved
-
-
-
1 / 0
Reserved
Reserved
0x6868
0x686A
0x686B
0x686C
0x686D
0x6870
0x6871
0x6872
0x6873
0x6874
0x6875
0x6876
0x6877
0x6878
0x6879
0x68A8
0x68AA
0x68AB
0x68AC
0x68AD
0x68B0
0x68B1
0x68B2
0x68B3
0x68B4
0x68B5
0x68B6
0x68B7
0x68B8
0x68B9
0x68E8
0x68EA
0x68EB
0x68EC
0x68ED
0x68F0
0x68F1
0x68F2
0x68F3
0x68F4
0x68F5
0x68F6
0x68F7
0x68F8
0x68F9
1 / 0
Reserved
Reserved
1 / W(2)
1 / W(2)
1 / W(2)
1 / W(2)
1 / 0
Reserved
TBPRDM
Time Base Period Register Mirror
Reserved
Reserved
CMPAM
Compare A Register Mirror
Digital Compare Trip Select register (1)
Digital Compare A Control register(1)
Digital Compare B Control register(1)
Digital Compare Filter Control register(1)
Digital Compare Capture Control register(1)
Digital Compare Filter Offset register
Digital Compare Filter Offset Counter register
Digital Compare Filter Window register
Digital Compare Filter Window Counter register
Digital Compare Counter Capture register
DCTRIPSEL
DCACTL
1 / 0
DCBCTL
1 / 0
DCFCTL
1 / 0
DCCAPCT
DCFOFFSET
DCFOFFSETCNT
DCFWINDOW
DCFWINDOWCNT
DCCAP
1 / 0
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
Table 8-46. ePWM5–ePWM7 Control and Status Registers
SIZE (×16) /
#SHADOW
NAME
ePWM5
ePWM6
ePWM7
DESCRIPTION
TBCTL
0x6900
0x6901
0x6902
0x6903
0x6904
0x6905
0x6906
0x6940
0x6941
0x6942
0x6943
0x6944
0x6945
0x6946
0x6980
0x6981
0x6982
0x6983
0x6984
0x6985
0x6986
1 / 0
Time Base Control register
Time Base Status register
Reserved
TBSTS
1 / 0
Reserved
TBPHS
TBCTR
TBPRD
Reserved
1 / 0
1 / 0
Time Base Phase register
Time Base Counter register
1 / 0
1 / 1
Time Base Period Register Set
Reserved
1 / 1
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Table 8-46. ePWM5–ePWM7 Control and Status Registers (continued)
SIZE (×16) /
#SHADOW
NAME
ePWM5
ePWM6
ePWM7
DESCRIPTION
Counter Compare Control register
CMPCTL
Reserved
CMPA
0x6907
0x6908
0x6909
0x690A
0x690B
0x690C
0x690D
0x690E
0x690F
0x6910
0x6911
0x6912
0x6913
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6920
-
0x6947
0x6948
0x6949
0x694A
0x694B
0x694C
0x694D
0x694E
0x694F
0x6950
0x6951
0x6952
0x6953
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
0x6960
-
0x6987
0x6988
0x6989
0x698A
0x698B
0x698C
0x698D
0x698E
0x698F
0x6990
0x6991
0x6992
0x6993
0x6994
0x6995
0x6996
0x6997
0x6998
0x6999
0x699A
0x699B
0x699C
0x699D
0x699E
0x69A0
-
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / W(2)
1 / W(2)
1 / W(2)
1 / W(2)
Reserved
Counter Compare A Register Set
Counter Compare B Register Set
Action Qualifier Control register for output A
Action Qualifier Control register for output B
Action Qualifier Software Force register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control register
Dead-Band Generator Rising Edge Delay Count register
Dead-Band Generator Falling Edge Delay Count register
Trip Zone Select register(1)
Trip Zone Digital Compare register
Trip Zone Control register(1)
Trip Zone Enable Interrupt register(1)
Trip Zone Flag register (1)
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
DBRED
DBFED
TZSEL
TZDCSEL
TZCTL
TZEINT
TZFLG
TZCLR
Trip Zone Clear register(1)
TZFRC
Trip Zone Force register(1)
ETSEL
Event Trigger Selection register
Event Trigger Prescale register
Event Trigger Flag register
Event Trigger Clear register
Event Trigger Force register
PWM Chopper Control register
Reserved
ETPS
ETFLG
ETCLR
ETFRC
PCCTL
Reserved
Reserved
Reserved
Reserved
Reserved
TBPRDM
Reserved
CMPAM
Reserved
-
-
-
Reserved
0x6928
0x692A
0x692B
0x692C
0x692D
0x6968
0x696A
0x696B
0x696C
0x696D
0x69A8
0x69AA
0x69AB
0x69AC
0x69AD
Reserved
Reserved
Time Base Period Register Mirror
Reserved
Compare A Register Mirror
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Table 8-46. ePWM5–ePWM7 Control and Status Registers (continued)
SIZE (×16) /
#SHADOW
NAME
DCTRIPSEL
ePWM5
ePWM6
ePWM7
DESCRIPTION
0x6930
0x6931
0x6932
0x6933
0x6934
0x6935
0x6936
0x6937
0x6938
0x6939
0x6970
0x6971
0x6972
0x6973
0x6974
0x6975
0x6976
0x6977
0x6978
0x6979
0x69B0
0x69B1
0x69B2
0x69B3
0x69B4
0x69B5
0x69B6
0x69B7
0x69B8
0x69B9
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
Digital Compare Trip Select register (1)
DCACTL
Digital Compare A Control register(1)
DCBCTL
Digital Compare B Control register(1)
DCFCTL
Digital Compare Filter Control register(1)
Digital Compare Capture Control register(1)
Digital Compare Filter Offset register
DCCAPCT
DCFOFFSET
DCFOFFSETCNT
DCFWINDOW
DCFWINDOWCNT
DCCAP
Digital Compare Filter Offset Counter register
Digital Compare Filter Window register
Digital Compare Filter Window Counter register
Digital Compare Counter Capture register
(1) Registers that are EALLOW protected.
(2) W = Write to shadow register
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8.9.8.3 ePWM Electrical Data/Timing
PWM refers to PWM outputs on ePWM1 to ePWM7. Section 8.9.8.3.1 shows the PWM timing requirements and
Section 8.9.8.3.2, switching characteristics.
8.9.8.3.1 ePWM Timing Requirements (1)
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
Asynchronous
Synchronous
tw(SYCIN)
Sync input pulse width
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.8.3.2 ePWM Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
33.33
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SCO)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(PWM)tza
no pin load
25
20
ns
ns
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
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8.9.8.3.3 Trip-Zone Input Timing
8.9.8.3.3.1 Trip-Zone Input Timing Requirements (1)
MIN
2tc(TBCLK)
MAX UNIT
cycles
Asynchronous
tw(TZ)
Pulse duration, TZx input low
Synchronous
2tc(TBCLK)
cycles
With input qualifier
2tc(TBCLK) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
SYSCLK
t
w(TZ)
TZ(A)
t
d(TZ-PWM)HZ
PWM(B)
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 8-39. PWM Hi-Z Characteristics
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8.9.9 Enhanced Capture Module
8.9.9.1 eCAP Module Device-Specific Information
The device contains an enhanced capture module (eCAP1). Figure 8-40 shows a functional block diagram of a
module.
CTRPHS
(phase register−32 bit)
APWM mode
SYNCIn
CTR_OVF
OVF
CTR [0−31]
PRD [0−31]
CMP [0−31]
TSCTR
(counter−32 bit)
SYNCOut
PWM
compare
logic
Delta−mode
RST
32
CTR=PRD
CTR=CMP
CTR [0−31]
PRD [0−31]
32
eCAPx
32
LD1
CAP1
(APRD active)
Polarity
select
LD
APRD
shadow
32
CMP [0−31]
32
32
LD2
CAP2
(ACMP active)
Polarity
select
LD
Event
qualifier
Event
Prescale
32
ACMP
shadow
Polarity
select
32
32
LD3
LD4
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
Polarity
select
LD
4
Capture events
CEVT[1:4]
4
Interrupt
Trigger
and
Flag
control
Continuous /
Oneshot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
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Figure 8-40. eCAP Functional Block Diagram
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The eCAP module is clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low
power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.
8.9.9.2 eCAP Module Register Descriptions
Table 8-47 shows the eCAP Control and Status Registers.
Table 8-47. eCAP Control and Status Registers
NAME
TSCTR
CTRPHS
CAP1
eCAP1
0x6A00
SIZE (×16) EALLOW PROTECTED
DESCRIPTION
Timestamp Counter
2
2
2
2
2
2
8
1
1
1
1
1
1
6
0x6A02
Counter Phase Offset Value register
Capture 1 register
0x6A04
CAP2
0x6A06
Capture 2 register
CAP3
0x6A08
Capture 3 register
CAP4
0x6A0A
Capture 4 register
Reserved
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
Reserved
0x6A0C to 0x6A12
0x6A14
Reserved
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable register
Capture Interrupt Flag register
Capture Interrupt Clear register
Capture Interrupt Force register
Reserved
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A1A to 0x6A1F
8.9.9.3 eCAP Module Electrical Data/Timing
Section 8.9.9.3.1 provides the eCAP timing requirement and Section 8.9.9.3.2 provides the eCAP switching
characteristics.
8.9.9.3.1 eCAP Timing Requirement (1)
MIN
2tc(SCO)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.9.3.2 eCAP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
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8.9.10 Enhanced Quadrature Encoder Pulse
8.9.10.1 eQEP Device-Specific Information
The device contains one eQEP module. Figure 8-41 shows the eQEP functional block diagram.
System Control
Registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
Capture
Unit
QCTMRLAT
QCPRDLAT
(QCAP)
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
16
PIE
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
eQEP Peripheral
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Figure 8-41. eQEP Functional Block Diagram
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8.9.10.2 eQEP Register Descriptions
Table 8-48 lists the eQEP Control and Status Registers.
Table 8-48. eQEP Control and Status Registers
eQEP1
eQEP1
ADDRESS
NAME
QPOSCNT
SIZE(×16)/
#SHADOW
REGISTER DESCRIPTION
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
eQEP Position Counter
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period register
eQEP Decoder Control register
eQEP Control register
eQEP Capture Control register
eQEP Position-compare Control register
eQEP Interrupt Enable register
eQEP Interrupt Flag register
eQEP Interrupt Clear register
eQEP Interrupt Force register
eQEP Status register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
0x6B21 to
0x6B3F
Reserved
31/0
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8.9.10.3 eQEP Electrical Data/Timing
Section 8.9.10.3.1 provides the eQEP timing requirement and Section 8.9.10.3.2 provides the eQEP switching
characteristics.
8.9.10.3.1 eQEP Timing Requirements (1)
TEST CONDITIONS
Asynchronous(2)/Synchronous
With input qualifier
MIN
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
tw(QEPP)
QEP input period
2tc(SCO)
2[1tc(SCO) + tw(IQSW)
]
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
Asynchronous(2)/Synchronous
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous(2)/Synchronous
With input qualifier
Asynchronous(2)/Synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
(2) See the TMS320F2805x MCUs Silicon Errata for limitations in the asynchronous mode.
8.9.10.3.2 eQEP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
4tc(SCO)
6tc(SCO)
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
cycles
cycles
td(PCS-OUT)QEP
Delay time, QEP input edge to position compare sync output
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8.9.11 JTAG Port
8.9.11.1 JTAG Port Device-Specific Information
On the 2805x device, the JTAG port is reduced to 5 pins ( TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and
TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in
Figure 8-42. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/
XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device
during emulation/debug because this pin will be needed for the TCK function.
Note
In 2805x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board
design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of
the JTAG pin function. Any circuitry connected to these pins should not prevent the JTAG debug probe
from driving (or being driven by) the JTAG pins for successful debug.
TRST = 0: JTAG Disabled (GPIO Mode)
TRST = 1: JTAG Mode
TRST
TRST
XCLKIN
GPIO38_in
TCK
TCK/GPIO38
GPIO38_out
C28x
Core
GPIO37_in
TDO
TDO/GPIO37
1
0
GPIO37_out
GPIO36_in
1
0
TMS
TMS/GPIO36
TDI/GPIO35
1
GPIO36_out
GPIO35_in
1
0
TDI
1
GPIO35_out
Figure 8-42. JTAG/GPIO Multiplexing
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8.9.12 General-Purpose Input/Output
8.9.12.1 GPIO Device-Specific Information
The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to
providing individual pin bit-banging I/O capability.
Table 8-49. GPIOA MUX (1) (2)
DEFAULT AT RESET
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
PRIMARY I/O
FUNCTION
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00)
(GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 BITS = 11)
1:0
3:2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
Reserved
Reserved
Reserved
CTRIPM1OUT (O)
Reserved
5:4
Reserved
7:6
SPISOMIA (I/O)
Reserved
Reserved
9:8
Reserved
11:10
13:12
15:14
17:16
19:18
21:20
23:22
SPISIMOA (I/O)
EPWMSYNCI (I)
SCIRXDA (I)
Reserved
ECAP1 (I/O)
EPWMSYNCO (O)
Reserved
ADCSOCAO (O)
Reserved
SCITXDB (O)
Reserved
ADCSOCBO (O)
Reserved
SCIRXDB (I)
TZ1 (I)/
CTRIPM1OUT (O)
25:24
27:26
29:28
GPIO12
GPIO13
GPIO14
SCITXDA (O)
Reserved
Reserved
Reserved
Reserved
TZ2 (I)
TZ3 (I)/
CTRIPPFCOUT (O)
SCITXDB (O)
TZ1 (I)/
CTRIPM1OUT (O)
31:30
GPIO15
SCIRXDB (I)
Reserved
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Table 8-49. GPIOA MUX (1) (2) (continued)
DEFAULT AT RESET
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
PRIMARY I/O
FUNCTION
GPAMUX1 REGISTER
BITS
(GPAMUX1 BITS = 00)
(GPAMUX1 BITS = 01)
(GPAMUX1 BITS = 10)
(GPAMUX1 BITS = 11)
GPAMUX2 REGISTER
BITS
(GPAMUX2 BITS = 00)
GPIO16
(GPAMUX2 BITS = 01)
SPISIMOA (I/O)
(GPAMUX2 BITS = 10)
EQEP1S (I/O)
(GPAMUX2 BITS = 11)
1:0
3:2
TZ2 (I)
TZ3 (I)/
CTRIPPFCOUT (O)
GPIO17
SPISOMIA (I/O)
EQEP1I (I/O)
5:4
GPIO18
GPIO19/XCLKIN
GPIO20
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
Reserved
SCITXDB (O)
SCIRXDB (I)
EPWM7A (O)
EPWM7B (O)
Reserved
XCLKOUT (O/Z)
ECAP1 (I/O)
CTRIPM1OUT (O)
Reserved
7:6
9:8
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
GPIO21
GPIO22
SCITXDB (O)
SCIRXDB (I)
Reserved
GPIO23
Reserved
GPIO24
EPWM7A (O)
Reserved
GPIO25
Reserved
GPIO26
Reserved
SCIRXDC (I)
SCITXDC (O)
SDAA (I/OD)
Reserved
GPIO27
Reserved
Reserved
GPIO28
SCIRXDA (I)
TZ2 (I)
TZ3 (I)/
CTRIPPFCOUT (O)
27:26
GPIO29
SCITXDA (O)
SCLA (I/OD)
29:28
31:30
GPIO30
GPIO31
CANRXA (I)
CANTXA (O)
SCIRXDB (I)
SCITXDB (O)
EPWM7A (O)
EPWM7B (O)
(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. If the Reserved GPxMUX1/2
register setting is selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration
for future expansion.
(2) I = Input, O = Output, Z = High Impedance, OD = Open Drain
Table 8-50. GPIOB MUX (1)
DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPBMUX1 REGISTER
BITS
(GPBMUX1 BITS = 00)
(GPBMUX1 BITS = 01)
(GPBMUX1 BITS = 10)
(GPBMUX1 BITS = 11)
1:0
GPIO32
GPIO33
SDAA (I/OD)
SCLA (I/OD)
Reserved
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved
EQEP1S (I/O)
EQEP1I (I/O)
CTRIPPFCOUT (O)
Reserved
3:2
5:4
GPIO34
7:6
GPIO35 (TDI)
GPIO36 (TMS)
GPIO37 (TDO)
GPIO38/XCLKIN (TCK)
GPIO39
Reserved
Reserved
9:8
Reserved
Reserved
Reserved
11:10
13:12
15:14
17:16
19:18
21:20
23:22
25:24
27:26
29:28
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SCIRXDC (I)
Reserved
CTRIPPFCOUT (O)
Reserved
GPIO40
EPWM7A (O)
Reserved
Reserved
Reserved
Reserved
GPIO42
EPWM7B (O)
Reserved
SCITXDC (O)
Reserved
CTRIPM1OUT (O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 8-50. GPIOB MUX (1) (continued)
DEFAULT AT RESET
PRIMARY I/O FUNCTION
PERIPHERAL
SELECTION 1
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
GPBMUX1 REGISTER
(GPBMUX1 BITS = 00)
(GPBMUX1 BITS = 01)
(GPBMUX1 BITS = 10)
(GPBMUX1 BITS = 11)
BITS
31:30
Reserved
Reserved
Reserved
Reserved
(1) I = Input, O = Output, OD = Open Drain
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The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
•
Synchronization to SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This mode is the default mode of all GPIO pins
at reset and this mode simply synchronizes the input signal to the system clock (SYSCLKOUT).
Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
•
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the input
signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when
ALL samples are the same (all 0s or all 1s) as shown in Figure 8-45 (for 6 sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
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GPIOXINT1SEL
GPIOLMPSEL
LPMCR0
GPIOXINT2SEL
GPIOXINT3SEL
External Interrupt
MUX
Low-Power
Modes Block
PIE
Asynchronous
path
GPxDAT (read)
GPxQSEL1/2
GPxCTRL
GPxPUD
N/C
00
01
Peripheral 1 Input
Peripheral 2 Input
Input
Internal
Pullup
Qualification
10
11
Peripheral 3 Input
GPxTOGGLE
Asynchronous path
GPIOx pin
GPxCLEAR
GPxSET
00
01
GPxDAT (latch)
Peripheral 1 Output
10
11
Peripheral 2 Output
Peripheral 3 Output
High Impedance
Output Control
GPxDIR (latch)
00
01
Peripheral 1 Output Enable
Peripheral 2 Output Enable
0 = Input, 1 = Output
XRS
10
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. The letter x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the
particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This diagram is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the Systems Control and
Interrupts chapter of the TMS320x2805x Technical Reference Manual for pin-specific variations.
Figure 8-43. GPIO Multiplexing
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8.9.12.2 GPIO Register Descriptions
The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 8-51 provides the GPIO register
mapping.
Table 8-51. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control register (GPIO0 to 31)
SIZE (×16)
DESCRIPTION
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
0x6F90
0x6F92
0x6F96
0x6F9A
0x6F9C
0x6FB6
0x6FBA
GPIO A Qualifier Select 1 register (GPIO0 to 15)
GPIO A Qualifier Select 2 register (GPIO16 to 31)
GPIO A MUX 1 register (GPIO0 to 15)
GPIO A MUX 2 register (GPIO16 to 31)
GPIO A Direction register (GPIO0 to 31)
GPIO A Pull Up Disable register (GPIO0 to 31)
GPIO B Control register (GPIO32 to 44)
GPIO B Qualifier Select 1 register (GPIO32 to 44)
GPIO B MUX 1 register (GPIO32 to 44)
GPIO B Direction register (GPIO32 to 44)
GPIO B Pull Up Disable register (GPIO32 to 44)
Reserved
GPAPUD
GPBCTRL
GPBQSEL1
GPBMUX1
GPBDIR
GPBPUD
Reserved
Reserved
Reserved
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
0x6FD8
0x6FDA
0x6FDC
0x6FDE
2
2
2
2
2
2
2
2
2
2
2
2
GPIO A Data register (GPIO0 to 31)
GPIO A Data Set register (GPIO0 to 31)
GPIO A Data Clear register (GPIO0 to 31)
GPIO A Data Toggle register (GPIO0 to 31)
GPIO B Data register (GPIO32 to 44)
GPIO B Data Set register (GPIO32 to 44)
GPIO B Data Clear register (GPIO32 to 44)
GPIO B Data Toggle register (GPIO32 to 44)
Reserved
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPBCLEAR
GPBTOGGLE
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLPMSEL
0x6FE0
0x6FE1
0x6FE2
0x6FE8
1
1
1
2
XINT1 GPIO Input Select register (GPIO0 to 31)
XINT2 GPIO Input Select register (GPIO0 to 31)
XINT3 GPIO Input Select register (GPIO0 to 31)
LPM GPIO Select register (GPIO0 to 31)
Note
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn
registers occurs to when the action is valid.
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8.9.12.3 GPIO Electrical Data/Timing
8.9.12.3.1 GPIO - Output Timing
8.9.12.3.1.1 General-Purpose Output Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
MAX
13(1)
13(1)
15
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency
All GPIOs
All GPIOs
ns
MHz
(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Section 8.9.12.3.1.1 are applicable for a 40-pF load on
I/O pins.
GPIO
t
r(GPO)
t
f(GPO)
Figure 8-44. General-Purpose Output Timing
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8.9.12.3.2 GPIO - Input Timing
8.9.12.3.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) The letter n represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
tw(SP)
Sampling Period determined
by GPxCTRL[QUALPRD](B)
tw(IQSW)
[(SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)
]
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. The QUALPRD bit
field value can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value n, the
qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This condition would ensure 5 sampling periods for
detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 8-45. Sampling Mode
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8.9.12.3.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the preceding equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. The number of samples is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
t
w(GPI)
Figure 8-46. General-Purpose Input Timing
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VDDIO
> 1 MS
2 pF
VSS
VSS
Figure 8-47. Input Resistance Model for a GPIO Pin With an Internal Pullup
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
www.ti.com
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8.9.12.3.4 Low-Power Mode Wakeup Timing
Section 8.9.12.3.4.1 provides the timing requirements, Section 8.9.12.3.4.2 provides the switching
characteristics, and Figure 8-48 shows the timing diagram for IDLE mode.
8.9.12.3.4.1 IDLE Mode Timing Requirements (1)
MIN
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
8.9.12.3.4.2 IDLE Mode Switching Characteristics (1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program execution resume (2)
cycles
•
•
Wake up from flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
cycles
cycles
cycles
–
20tc(SCO) + tw(IQSW)
1050tc(SCO)
td(WAKE-IDLE)
Wake up from flash
Flash module in sleep state
–
1050tc(SCO) + tw(IQSW)
20tc(SCO)
•
Wake up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.9.12.3.2.1.
(2) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR
(triggered by the wakeup) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
WAKE INT(A)(B)
A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum)
is needed before the wake-up signal could be asserted.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 8-48. IDLE Entry and Exit Timing
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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8.9.12.3.4.3 STANDBY Mode Timing Requirements
MIN
3tc(OSCCLK)
MAX
UNIT
Without input qualification
With input qualification(1)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
8.9.12.3.4.4 STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO) cycles
cycles
Delay time, external wake signal to program execution
resume(1)
•
Wake up from flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
cycles
–
100tc(SCO) + tw(WAKE-INT)
td(WAKE-STBY)
•
Wake up from flash
Flash module in sleep state
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
cycles
cycles
–
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR
(triggered by the wake up signal) involves additional latency.
(C)
(F)
(A)
(B)
(D)(E)
(G)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal(H)
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated as follows before being turned
off:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After
the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
D. The external wake-up signal is driven active.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. After a latency period, the STANDBY mode is exited.
G. Normal execution resumes. The device will respond to the interrupt (if enabled).
H. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4
OSCCLK cycles have elapsed.
Figure 8-49. STANDBY Entry and Exit Timing Diagram
8.9.12.3.4.5 HALT Mode Timing Requirements
MIN
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
MAX
UNIT
cycles
cycles
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wake-up signal
8.9.12.3.4.6 HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
32tc(SCO)
MAX
45tc(SCO)
1
UNIT
cycles
ms
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
Delay time, PLL lock to program execution resume
•
Wake up from flash
– Flash module in sleep state
1125tc(SCO)
cycles
td(WAKE-HALT)
•
Wake up from SARAM
35tc(SCO)
cycles
(C)
(F)
(A)
(H)
(B)
(G)
(D)(E)
HALT
Device
Status
HALT
Flushing Pipeline
PLL Lock-up Time
Wake-up Latency
Normal
Execution
GPIOn(I)
t
)
d(WAKE−HALT
t
w(WAKE-GPIO)
tp
X1/X2 or
XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated as follows before oscillator is turned
off and the CLKIN to the core is stopped:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to
keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. Keeping INTOSC1, INTOSC2,
and the watchdog alive in HALT mode is done by writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is
executed, a delay of 5 OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized, which enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.
G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.
H. Normal operation resumes.
I. From the time the IDLE instruction is executed to place the device into low-power mode, wakeup should not be initiated until at least 4
OSCCLK cycles have elapsed.
Figure 8-50. HALT Wake-Up Using GPIOn
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at the Select TI reference designs page.
Single-axis Motor Control Reference Design with Integrated Power Factor Correction
This reference design demonstrates best practices for integrating both single-axis motor control and power factor
correction (PFC) into a single microcontroller. This practice is popular when designing variable-frequency
compressors, particularly for HVAC systems. This implementation is optimized to perform using a sensorless
Field Oriented Control (FOC) algorithm to drive a permanent magnet synchronous motor (PMSM) and two phase
interleaved PFC on the TMS320F2805x microcontroller. The FOC algorithm maintains efficiency in a wide range
of speeds and considers torque changes with transient phases by processing a dynamic model of the motor.
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
SPRS797E – NOVEMBER 2012 – REVISED FEBRUARY 2021
www.ti.com
10 Device and Documentation Support
10.1 Getting Started
To get started with C2000 real-time microcontrollers, see C2000 real-time control MCUs – Getting started.
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F28055). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (with TMX for devices and TMDX for tools) through fully
qualified production devices and tools (with TMS for devices and TMDS for tools).
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PN) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI
sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2805x MCUs
Silicon Errata.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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Figure 10-1. Device Nomenclature
10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed here. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.
Development Tools
controlCARD with TMS320F28054MPNT, InstaSPIN-FOC and InstaSPIN-MOTION enabled
Featuring the TMS320F28054M MCU, capable of running the InstaSPIN-FOC™ and InstaSPIN-MOTION™
solutions from on-chip ROM, the TMDSCNCD28054MISO controlCARD provides a convenient and standardized
hardware interface to begin experimentation with the latest motor control technology from Texas Instruments.
F2805x Isolated USB controlCARD
C2000™ controlCARDs from Texas Instruments are a unique set of daughtercards enabling experimentation
with C2000’s broad portfolio of MCUs for device evaluation and application development. Designed with a
DIM100 or larger, plug-in connector, controlCARDs are easily interchangeable throughout C2000’s collection of
development kits, giving users the ability to experiment with various C2000 MCUs to find the correct MCU fit for
an application. controlCARDs give access to all digital I/Os, analog I/Os, and JTAG signals from the C2000
MCU, providing a simple, modular, and standardized board-level interface to the C2000 MCU. Software, support,
and documentation, are provided completely free through C2000’s C2000Ware software platform. Learn more
and download C2000Ware today by clicking the Tools & software tab on the C2000™ 32-bit microcontrollers
page.
F2805x Experimenter Kit
C2000™ Experimenters Kits from Texas Instruments are device evaluation kits, providing a platform for initial
device exploration and prototyping. Each Experimenters Kit includes a docking station and a plug-in compatible
controlCARD, which docks directly onto the docking station. The docking station features onboard USB JTAG
emulation, access to all C2000 MCU signals from the controlCARD, breadboard areas for experimentation, and
JTAG and RS-232 connectors. For software development, Code Composer Studio (CCS) Integrated
Development Environment (IDE) is included for free with use of the onboard XDS100 USB JTAG debug probe.
Device software, support, example projects, libraries, and documentation are provided completely free through
the C2000 C2000Ware software platform. Learn more and download C2000Ware today by clicking the Tools &
software tab on the C2000™ 32-bit microcontrollers page.
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TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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Software Tools
C2000Ware for C2000 MCUs
C2000Ware for C2000 microcontrollers is a cohesive set of development software and documentation designed
to minimize software development time. From device-specific drivers and libraries to device peripheral examples,
C2000Ware provides a solid foundation to begin development and evaluation. C2000Ware is the recommended
content delivery tool versus controlSUITE™.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug embedded
applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,
profiler, and many other features. The intuitive IDE provides a single user interface taking the user through each
step of the application development flow. Familiar tools and interfaces let users get started faster than ever
before. CCS combines the advantages of the Eclipse software framework with advanced embedded debug
capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.
Pin Mux Tool
The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing
settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.
UniFlash Standalone Flash Tool
UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting
interface.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
Training
To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,
TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-
on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller
family. These training resources have been designed to decrease the learning curve, while reducing
development time, and accelerating product time to market. For more information on the various training
resources, visit the C2000™ real-time control MCUs – Support & training site.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper-
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed here.
Errata
TMS320F2805x MCUs Silicon Errata describes known advisories on silicon and provides workarounds.
InstaSPIN Technical Reference Manuals
InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide describes the InstaSPIN-FOC and InstaSPIN-
MOTION devices.
TMS320F28054F, TMS320F28052F InstaSPIN-FOC™ Software Technical Reference Manual describes
TMS320F28054F and TMS320F28052F InstaSPIN-FOC software.
TMS320F28054M, TMS320F28052M InstaSPIN-MOTION™ Software Technical Reference Manual describes
TMS320F28054M and TMS320F28052M InstaSPIN-MOTION software.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This reference
guide also describes emulation features available on these DSPs.
Peripheral Guides and Technical Reference Manuals
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
digital signal processors (DSPs).
TMS320x2805x Technical Reference Manual details the integration, the environment, the functional description,
and the programming models for each peripheral and subsystem in the 2805x microcontrollers.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
Application Reports
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
TMS320F28052, TMS320F28052M, TMS320F28052F, TMS320F28051, TMS320F28050
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MCU CAN Module Operation Using the On-Chip Zero-Pin Oscillator.
The TMS320F2803x/TMS320F2805x/TMS320F2806x series of microcontrollers have an on-chip zero-pin
oscillator that needs no external components. This application report describes how to use the CAN module with
this oscillator to operate at the maximum bit rate and bus length without the added cost of an external clock
source.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
TMS320C2000™, DSP/BIOS™, TMS320™, InstaSPIN-FOC™, InstaSPIN-MOTION™, controlSUITE™, Code
Composer Studio™, and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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TMS320F28055, TMS320F28054, TMS320F28054M, TMS320F28054F, TMS320F28053
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11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28054M TMS320F28054F TMS320F28053
TMS320F28052 TMS320F28052M TMS320F28052F TMS320F28051 TMS320F28050
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
119
(1)
(2)
(3)
(4/5)
(6)
TMS320F28050PNS
TMS320F28051PNS
TMS320F28051PNT
TMS320F28052FPNQ
TMS320F28052FPNT
TMS320F28052MPNQ
TMS320F28052MPNT
TMS320F28052PNQ
TMS320F28052PNS
TMS320F28052PNT
TMS320F28053PNS
TMS320F28054FPNQ
TMS320F28054FPNT
TMS320F28054MPNQ
TMS320F28054MPNT
TMS320F28054PNQ
TMS320F28054PNS
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PN
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
80
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 125
-40 to 105
-40 to 125
-40 to 105
-40 to 125
-40 to 125
F28050PNS
TMS320
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PN
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
F28051PNS
TMS320
PN
F28051PNT
TMS320
PN
F28052FPNQ
TMS320
PN
F28052FPNT
TMS320
PN
F28052MPNQ
TMS320
PN
F28052MPNT
TMS320
PN
F28052PNQ
TMS320
PN
F28052PNS
TMS320
PN
F28052PNT
TMS320
PN
F28053PNS
TMS320
PN
F28054FPNQ
TMS320
PN
F28054FPNT
TMS320
PN
F28054MPNQ
TMS320
PN
F28054MPNT
TMS320
PN
F28054PNQ
TMS320
PN
F28054PNS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320
TMS320F28055PNS
TMS320F28055PNT
ACTIVE
ACTIVE
LQFP
LQFP
PN
PN
80
80
119
119
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 105
F28055PNS
TMS320
F28055PNT
TMS320
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
60
M
0,08
41
61
40
0,13 NOM
80
21
1
20
Gage Plane
9,50 TYP
0,25
12,20
SQ
11,80
0,05 MIN
0°–7°
14,20
SQ
13,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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