TMS320F28069FPZTR_技术文档

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

_{SPRS698I – NOV}T_EM_MBS_E3_R2₂0₀F₁2₀8_–0_R6_E2_V,_IST_EM_DS_FE3_B2_R0_UF_A2_R8_Y0₂6₀2₂F₁

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SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

TMS320F2806x Microcontrollers

– 16 PWM channels total (8 HRPWM-capable)

– Independent 16-bit timer in each module

Three input Enhanced Capture (eCAP) modules

Up to 4 High-Resolution Capture (HRCAP)

modules

Up to 2 Enhanced Quadrature Encoder Pulse

(eQEP) modules

12-bit Analog-to-Digital Converter (ADC), dual

Sample-and-Hold (S/H)

1 Features

•

High-efficiency 32-bit CPU (TMS320C28x)

•

– 90 MHz (11.11-ns cycle time)

– 16 × 16 and 32 × 32 Multiply and Accumulate

(MAC) operations

– 16 × 16 dual MAC

– Harvard bus architecture

•

– Atomic operations

– Fast interrupt response and processing

– Unified memory programming model

– Code-efficient (in C/C++ and Assembly)

Floating-Point Unit (FPU)

– Native single-precision floating-point operations

Programmable Control Law Accelerator (CLA)

– 32-bit floating-point math accelerator

– Executes code independently of the main CPU

Viterbi, Complex Math, CRC Unit (VCU)

– Extends C28x instruction set to support

complex multiply, Viterbi operations, and Cyclic

Redundency Check (CRC)

– Up to 3.46 MSPS

– Up to 16 channels

On-chip temperature sensor

128-bit security key and lock

– Protects secure memory blocks

– Prevents reverse-engineering of firmware

Serial port peripherals

– Two Serial Communications Interface (SCI)

[UART] modules

– Two Serial Peripheral Interface (SPI) modules

– One Inter-Integrated-Circuit (I2C) bus

– One Multichannel Buffered Serial Port (McBSP)

bus

•

Embedded memory

– Up to 256KB of flash

– Up to 100KB of RAM

– One Enhanced Controller Area Network

(eCAN)

– 2KB of One-Time Programmable (OTP) ROM

6-channel Direct Memory Access (DMA)

Low device and system cost

– Universal Serial Bus (USB) 2.0

(see Device Comparison for availability)

•

Full-speed device mode

Full-speed or low-speed host mode

– Single 3.3-V supply

•

Up to 54 individually programmable, multiplexed

General-Purpose Input/Output (GPIO) pins with

input filtering

Advanced emulation features

– Analysis and breakpoint functions

– Real-time debug through hardware

Package options

– 80-pin PFP and 100-pin PZP PowerPAD^™

Thermally Enhanced Thin Quad Flatpacks

(HTQFPs)

– 80-pin PN and 100-pin PZ Low-Profile Quad

Flatpacks (LQFPs)

Temperature options

– T: –40°C to 105°C

– S: –40°C to 125°C

– Q: –40°C to 125°C (AEC Q100 qualification for

automotive applications)

– No power sequencing requirement

– Integrated power-on reset and brownout reset

– Low-power operating modes

– No analog support pin

Endianness: Little endian

JTAG boundary scan support

– IEEE Standard 1149.1-1990 Standard Test

Access Port and Boundary Scan Architecture

Clocking

– Two internal zero-pin oscillators

– On-chip crystal oscillator/external clock input

– Watchdog timer module

– Missing clock detection circuitry

Peripheral Interrupt Expansion (PIE) block that

supports all peripheral interrupts

Three 32-bit CPU timers

•

Advanced control peripherals

Up to 8 Enhanced Pulse-Width Modulator (ePWM)

modules

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

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intellectual property matters and other important disclaimers. PRODUCTION DATA.

Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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•

Micro inverter

Solar power optimizer

String inverter

2 Applications

•

Air conditioner outdoor unit

Door operator drive control

Inverter & motor control

On-board (OBC) & wireless charger

Automated sorting equipment

CNC control

Textile machine

Welding machine

EV charging station power module

Wireless vehicle charging module

Energy storage power conversion system (PCS)

Central inverter

AC drive control module

AC drive power stage module

Linear motor power stage

Servo drive control module

Servo drive power stage module

AC-input BLDC motor drive

DC-input BLDC motor drive

Industrial AC-DC

Three phase UPS

3 Description

C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop

performance in real-time control applications such as industrial motor drives; solar inverters and digital power;

electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes

the Premium performance MCUs and the Entry performance MCUs.

The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly

integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based

code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM

module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references

have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V

fixed full-scale range and supports ratio-metric V_REFHI/V_REFLOreferences. The ADC interface has been

optimized for low overhead and latency.

To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.

Device Information

PART NUMBER⁽¹⁾

TMS320F28069PZP

PACKAGE

HTQFP (100)

HTQFP (80)

LQFP (100)

LQFP (80)

BODY SIZE

14.0 mm × 14.0 mm

12.0 mm × 12.0 mm

14.0 mm × 14.0 mm

12.0 mm × 12.0 mm

TMS320F28069PFP

TMS320F28069PZ

TMS320F28069PN

(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.

2

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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3.1 Functional Block Diagram

Figure 3-1 shows a functional block diagram of the device.

M0 SARAM (1K´16)

(0-wait, Nonsecure)

L0 DPSARAM (2K´16)

(0-wait, Secure)

CLA Data RAM2

OTP 1K´16

Secure

M1 SARAM (1K´16)

(0-wait, Nonsecure)

L1 DPSARAM (1K´16)

(0-wait, Secure)

CLA Data RAM0

FLASH

128K´16

64K´16

L5 DPSARAM (8K´16)

(0-wait, Nonsecure)

DMA RAM0

Code

Security

Module

(CSM)

L2 DPSARAM (1K´16)

(0-wait, Secure)

CLA Data RAM1

8 equal sectors

Secure

L6 DPSARAM (8K´16)

(0-wait, Nonsecure)

DMA RAM1

L3 DPSARAM (4K´16)

(0-wait, Secure)

CLA Program RAM

PUMP

L7 DPSARAM (8K´16)

(0-wait, Nonsecure)

DMA RAM2

OTP/Flash

Wrapper

L4 SARAM (8K´16)

(0-wait, Secure)

PSWD

L8 DPSARAM (8K´16)

(0-wait, Nonsecure)

DMA RAM3

Memory Bus

DMA Bus

Boot-ROM

(32K´16)

(0-wait,

COMP1OUT

Nonsecure)

TRST

COMP2OUT

COMP3OUT

C28x 32-bit CPU

FPU

VCU

TCK, TDI, TMS

TDO

COMP

+

DAC

COMP1A

COMP1B

COMP2A

COMP2B

XCLKIN

CLA +

Message

RAMs

OSC1, OSC2,

Ext, PLLs,

LPM, WD,

LPM Wakeup

3 Ext. Interrupts

CPU Timer 0,

CPU Timer 1,

CPU Timer 2,

PIE

COMP3A

COMP3B

X1

X2

DMA

6-ch

XRS

ADC

0-wait

Result

Regs

CLA Bus

DMA Bus

A7:0

B7:0

Memory Bus

ADC

32-Bit Peripheral

Bus

32-Bit

Peripheral Bus

(CLA accessible)

32-Bit Peripheral Bus

(CLA accessible)

32-Bit Peripheral

Bus

32-Bit Peripheral

Bus

16-Bit Peripheral Bus

HRCAP1

HRCAP2

HRCAP3

HRCAP4

ePWM1 to ePWM8

HRPWM (8ch)

SCI-A SPI-A

SCI-B SPI-B

(4L FIFO) (4L FIFO)

eCAP1

eCAP2

eCAP3

I2C-A

(4L FIFO)

eCAN-A

(32-mbox)

eQEP1

eQEP2

USB-0

McBSP-A

GPIO Mux

A. Not all peripheral pins are available at the same time due to multiplexing.

Figure 3-1. Functional Block Diagram

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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3.2 System Device Diagram

C28x

Core

(90-MHz)

PWM-1A

PWM-1B

PWM1

(DMA-accessible)

ADC

(DMA-

accessible)

V_REFLO

V_REFHI

PWM-2A

PWM-2B

PWM2

(DMA-accessible)

FPU

VCU

V_REF

PWM-3A

PWM-3B

PWM3

(DMA-accessible)

Flash Memory

RAM

A0

A1

A2

A3

A4

A5

A6

A7

B0

B1

B2

B3

B4

B5

B6

B7

PWM-4A

PWM-4B

PWM4

(DMA-accessible)

RAM

(Dual-Access)

12-Bit

3.46-MSPS

Dual

Sample-

and-

Hold

PWM-5A

PWM-5B

PWM5

(DMA-accessible)

PWM-6A

PWM-6B

PWM6

(DMA-accessible)

CLA Core

90-MHz Floating-Point

(Accelerator)

PWM-7A

PWM-7B

PWM7

(DMA-accessible)

SOC-based

(DMA-accessible)

PWM-8A

PWM-8B

PWM8

(DMA-accessible)

Temp

Sensor

6

TZ1

TZ2

TZ3

Trip Zone

CMP1-Out

CMP2-Out

CMP1-out

CMP2-out

CMP3-out

10-Bit

DAC

3

8

4

eCAP

eCAP ´ 3

eQEP ´ 2

10-Bit

DAC

CMP3-Out

eQEP

10-Bit

DAC

Analog

Comparators

HRCAP

HRCAP ´ 4

COMMS

Timers 32-bit

Vreg

Timer-0

Timer-1

Timer-2

4

8

2

6

2

UART ´ 2

SPI ´ 2

Int-Osc-1

Int-Osc-2

WD

PLL

X1

X2

On-chip Osc

POR/BOR

System

GPIO

Control

I2C

CAN

McBSP

(DMA-accessible)

USB

(DMA-accessible)

Figure 3-2. Peripheral Blocks

4

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................2

3 Description.......................................................................2

3.1 Functional Block Diagram...........................................3

3.2 System Device Diagram............................................. 4

4 Revision History.............................................................. 6

5 Device Comparison.........................................................7

5.1 Related Products........................................................ 8

6 Terminal Configuration and Functions..........................9

6.1 Pin Diagrams.............................................................. 9

6.2 Signal Descriptions................................................... 12

7 Specifications................................................................ 21

7.1 Absolute Maximum Ratings...................................... 21

7.2 ESD Ratings – Commercial...................................... 22

7.3 ESD Ratings – Automotive....................................... 22

7.4 Recommended Operating Conditions.......................23

7.5 Power Consumption Summary................................. 24

7.6 Electrical Characteristics...........................................28

7.7 Thermal Resistance Characteristics......................... 29

7.8 Thermal Design Considerations................................32

7.9 Debug Probe Connection Without Signal

7.14 Flash Timing............................................................40

8 Detailed Description......................................................43

8.1 Overview...................................................................43

8.2 Memory Maps........................................................... 53

8.3 Register Maps...........................................................65

8.4 Device Emulation Registers......................................67

8.5 VREG, BOR, POR.................................................... 69

8.6 System Control......................................................... 71

8.7 Low-power Modes Block...........................................80

8.8 Interrupts...................................................................81

8.9 Peripherals................................................................86

9 Applications, Implementation, and Layout............... 163

9.1 TI Reference Design...............................................163

10 Device and Documentation Support........................164

10.1 Device and Development Support Tool

Nomenclature............................................................164

10.2 Tools and Software............................................... 165

10.3 Documentation Support........................................ 167

10.4 Support Resources............................................... 168

10.5 Trademarks...........................................................168

10.6 Electrostatic Discharge Caution............................168

10.7 Glossary................................................................168

11 Mechanical, Packaging, and Orderable

Buffering for the MCU..................................................32

7.10 Parameter Information............................................ 33

7.11 Test Load Circuit..................................................... 33

7.12 Power Sequencing..................................................34

7.13 Clock Specifications................................................37

Information.................................................................. 169

11.1 Packaging Information.......................................... 169

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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4 Revision History

Changes from March 19, 2020 to February 1, 2021 (from Revision H (March 2020) to Revision I

(February 2021))

Page

•

Added Q1 Part Numbers................................................................................................................................ 0

Table 5-1: Added Q1 Part Numbers....................................................................................................................7

Figure 10-1: Added GPN information............................................................................................................. 164

6

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

5 Device Comparison

Table 5-1 lists the features of the TMS320F2806x devices.

Table 5-1. Device Comparison

28069

28069-Q1

28062

28069U^{(2) (5)}

28069M ^{(2) (3)}

28069M-Q1

28069F ^{(2) (3)}

28069F-Q1

(90 MHz)

28068U^{(2) (5)}

28068M ^{(2) (3)}

28068F ^{(2) (3)}

(90 MHz)

28067

28067-Q1

28067U^{(2) (5)}

(90 MHz)

28066

28066-Q1

28066U^{(2) (5)}

(90 MHz)

28065

28065-Q1

28065U^{(2) (5)}

(90 MHz)

28062-Q1

28062U^{(2) (5)}

28062F ^{(2) (3)}

28062F-Q1

(90 MHz)

28064

28063

TYPE

FEATURE

28064U^{(2) (5)}

(90 MHz)

28063U^{(2) (5)}

(90 MHz)

(1)

Package Type

(PFP and PZP are

PowerPAD HTQFPs.

PN and PZ are LQFPs.)

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

PN

PZ

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

Instruction cycle

Floating-Point Unit (FPU)

VCU

–

11.11 ns

Yes

11.11 ns

Yes

11.11 ns

Yes

11.11 ns

Yes

11.11 ns

Yes

11.11 ns

Yes

11.11 ns

Yes

11.11 ns

Yes

No

Yes

No

CLA

0

–

Yes

No

Yes

No

6-Channel DMA

Yes

On-chip Flash (16-bit word)

On-chip SARAM (16-bit word)

128K

50K

128K

50K

128K

50K

128K

34K

64K

50K

64K

34K

64K

26K

50K

Code security for on-chip

Flash, SARAM, and OTP

blocks

–

Yes

1K

Yes

1K

Yes

1K

Yes

1K

Yes

1K

Yes

1K

Yes

1K

Yes

1K

Boot ROM (32K × 16)

One-time programmable

(OTP) ROM

(16-bit word)

ePWM channels

1

16

14

16

14

16

14

16

14

16

14

16

14

16

14

16

14

High-resolution ePWM

Channels

8

3

8

3

8

3

8

3

8

3

8

3

8

3

8

3

eCAP inputs

HRCAP

0

–

4

2

1

4

2

1

4

2

1

4

2

1

4

2

1

4

2

1

4

2

1

4

2

1

eQEP modules

Watchdog timer

MSPS

Yes

3.46

Yes

3.46

Yes

3.46

Yes

3.46

Yes

3.46

Yes

3.46

Yes

3.46

Yes

3.46

Conversion Time

289 ns

Channels

12-Bit

16

12

16

12

16

12

16

12

16

12

16

12

16

12

16

12

3

ADC

Temperature

Sensor

Yes

Dual Sample-

and-Hold

Yes

3

Yes

3

Yes

3

Yes

3

Yes

3

Yes

3

Yes

3

Yes

3

32-Bit CPU timers

–

0

Comparators with Integrated

DACs

3

I2C

0

1

0

1

0

1

McBSP

eCAN

1

SPI

2

SCI

2

USB

1⁽²⁾

1

1⁽²⁾

1

1⁽²⁾

1

1⁽²⁾

1

1⁽²⁾

1

1⁽²⁾

1

1⁽²⁾

1

1⁽²⁾

1

2-pin Oscillator

0-pin Oscillator

2

GPIO

–

54

40

54

40

54

40

54

40

54

40

54

40

54

40

54

40

I/O pins

(shared)

AIO

6

3

6

3

6

3

6

3

6

3

6

3

6

3

6

3

External interrupts

Supply voltage (nominal)

3.3 V

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table 5-1. Device Comparison (continued)

28069

28069-Q1

28062

28069U^{(2) (5)}

28069M ^{(2) (3)}

28069M-Q1

28069F ^{(2) (3)}

28069F-Q1

(90 MHz)

28068U^{(2) (5)}

28068M ^{(2) (3)}

28068F ^{(2) (3)}

(90 MHz)

28067

28067-Q1

28067U^{(2) (5)}

(90 MHz)

28066

28066-Q1

28066U^{(2) (5)}

(90 MHz)

28065

28065-Q1

28065U^{(2) (5)}

(90 MHz)

28062-Q1

28062U^{(2) (5)}

28062F ^{(2) (3)}

28062F-Q1

(90 MHz)

28064

28063

TYPE

FEATURE

28064U^{(2) (5)}

(90 MHz)

28063U^{(2) (5)}

(90 MHz)

(1)

Package Type

(PFP and PZP are

PowerPAD HTQFPs.

PN and PZ are LQFPs.)

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

100-

80-Pin

PN

PZ

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

T: –40°C to

105°C

–

PZ

PN

PZ

PN

PZ

PN

PZ

PN

PZ

PN

PZ

PN

PZ

PN

PZ

PN

Temperatu S: –40°C to

re options 125°C

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

PZP

PFP

Q: –40°C to

125°C^{(5) (4)}

(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor

differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the

C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.

(2) USB is present on TMS320F2806xU, TMS320F2806xM, and TMS320F2806xF devices.

(3) TMS320F2806xM devices are InstaSPIN-MOTION^™-enabled MCUs. TMS320F2806xF devices are InstaSPIN-FOC^™-enabled MCUs.

For more information, see Section 10.3 for a list of InstaSPIN Technical Reference Manuals.

(4) The letter Q refers to AEC Q100 qualification for automotive applications.

(5) The Q temperature option is not available on the TMS320F2806xU devices.

5.1 Related Products

For information about similar products, see the following links:

TMS320F2802x Microcontrollers

The F2802x series offers the lowest pin-count and Flash memory size options. InstaSPIN-FOC™ versions are

available.

TMS320F2803x Microcontrollers

The F2803x series increases the pin-count and memory size options. The F2803x series also introduces the

parallel control law accelerator (CLA) option.

TMS320F2805x Microcontrollers

The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).

InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.

TMS320F2806x Microcontrollers

The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the pin-

count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-MOTION™

versions are available.

TMS320F2807x Microcontrollers

The F2807x series offers the most performance, largest pin counts, flash memory sizes, and peripheral options.

The F2807x series includes the latest generation of accelerators, ePWM peripherals, and analog technology.

TMS320F28004x Microcontrollers

The F28004x series is a reduced version of the F2807x series with the latest generational enhancements. The

F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and configurable

logic block (CLB) versions are available.

8

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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6 Terminal Configuration and Functions

6.1 Pin Diagrams

Figure 6-1 shows the pin assignments on the 80-pin PN and PFP packages. Figure 6-2 shows the pin

assignments on the 100-pin PZ and PZP packages.

GPIO27/HRCAP2/SPISTEB/USB0DM

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

GPIO28/SCIRXDA/SDAA/TZ2

GPIO26/ECAP3/SPICLKB/USB0DP

GPIO9/EPWM5B/SCITXDB/ECAP3

V_DDIO

V_SS

V_DD3VFL

V_DD

TEST2

GPIO3/EPWM2B/SPISOMIA/COMP2OUT

GPIO2/EPWM2A

GPIO12/TZ1/SCITXDA/SPISIMOB

GPIO29/SCITXDA/SCLA/TZ3

GPIO30/CANRXA/EPWM7A

GPIO31/CANTXA/EPWM8A

GPIO25/ECAP2/SPISOMIB

V_DDIO

GPIO1/EPWM1B/COMP1OUT

GPIO0/EPWM1A

GPIO15/ECAP2/SCIRXDB/SPISTEB

VREGENZ

V_DD

V_SS

V_DDIO

ADCINB6/COMP3B/AIO14

ADCINB5

GPIO13/TZ2/SPISOMIB

GPIO14/TZ3/SCITXDB/SPICLKB

GPIO24/ECAP1/SPISIMOB

ADCINB4/COMP2B/AIO12

ADCINB2/COMP1B/AIO10

ADCINB1

GPIO22/EQEP1S/MCLKXA/SCITXDB

ADCINB0

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

V_REFLO, V_SSA

A. Pin 19: V_REFHIand ADCINA0 share the same pin on the 80-pin PN and PFP devices and their use is mutually exclusive to one another.

Pin 21: V_REFLOis always connected to V_SSAon the 80-pin PN and PFP devices.

B. The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must be connected to the

ground plane of the PCB. It should not be left unconnected. For more details, see PowerPAD™ Thermally Enhanced Package.

Figure 6-1. 80-Pin PN and PFP Packages (Top View)

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

GPIO41/EPWM7B/SCIRXDB

76

77

78

79

80

81

82

83

84

85

86

87

88

89

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

GPIO28/SCIRXDA/SDAA/TZ2

GPIO27/HRCAP2/EQEP2S/SPISTEB/USB0DM

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO26/ECAP3/EQEP2I/SPICLKB/USB0DP

GPIO51/EQEP1B/MDRA/TZ2

V_SS

V_DDIO

V_SS

V_DD3VFL

TEST2

V_DD

GPIO40/EPWM7A/SCITXDB

GPIO3/EPWM2B/SPISOMIA/COMP2OUT

GPIO2/EPWM2A

GPIO12/TZ1/SCITXDA/SPISIMOB

GPIO29/SCITXDA/SCLA/TZ3

GPIO50/EQEP1A/MDXA/TZ1

GPIO30/CANRXA/EQEP2I/EPWM7A

GPIO31/CANTXA/EQEP2S/EPWM8A

GPIO25/ECAP2/EQEP2B/SPISOMIB

V_DDIO

GPIO56/SPICLKA/EQEP2I/HRCAP3

GPIO1/EPWM1B/COMP1OUT

GPIO0/EPWM1A

GPIO15/ECAP2/SCIRXDB/SPISTEB

GPIO57/SPISTEA/EQEP2S/HRCAP4

V_DD

V_SS

90

91

92

93

94

95

96

97

98

99

100

VREGENZ

V_DD

ADCINB7

V_SS

ADCINB6/COMP3B/AIO14

ADCINB5

V_DDIO

GPIO58/MCLKRA/SCITXDB/EPWM7A

ADCINB4/COMP2B/AIO12

ADCINB3

GPIO13/TZ2/SPISOMIB

GPIO14/TZ3/SCITXDB/SPICLKB

ADCINB2/COMP1B/AIO10

ADCINB1

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO22/EQEP1S/MCLKXA/SCITXDB

ADCINB0

V_REFLO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

V_SSA

A. The PowerPAD is not connected to the ground on the die. To facilitate effective heat dissipation, the PowerPAD must be connected to the

ground plane of the PCB. It should not be left unconnected. For more details, see PowerPAD™ Thermally Enhanced Package.

Figure 6-2. 100-Pin PZ and PZP Packages (Top View)

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Note

The PowerPAD^™should be soldered to the ground (GND) plane of the PCB because this will provide

the best thermal conduction path. For this device, the PowerPAD is not electrically shorted to the

internal die V_SS; therefore, the PowerPAD does not provide an electrical connection to the PCB

ground. To make optimum use of the thermal efficiencies designed into the PowerPAD package, the

PCB must be designed with this technology in mind. A thermal land is required on the surface of the

PCB directly underneath the body of the PowerPAD. The thermal land should be soldered to the

exposed lead frame die pad of the PowerPad package; the thermal land should be as large as needed

to dissipate the required heat. An array of thermal vias should be used to connect the thermal pad to

the internal GND plane of the board. See PowerPAD™ Thermally Enhanced Package for more details

on using the PowerPAD package.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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6.2 Signal Descriptions

Section 6.2.1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions.

Some peripheral functions may not be available in all devices. See Table 5-1 for details. Inputs are not 5-V

tolerant. All GPIO pins are I/O/Z and have an internal pullup (PU), which can be selectively enabled or disabled

on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at

reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup.

Note

When the on-chip voltage regulator (VREG) is used, the GPIO19, GPIO26–27, and GPIO34–38 pins

could glitch during power up. This potential glitch will finish before the boot mode pins are read and

will not affect boot behavior. If glitching is unacceptable in an application, 1.8 V could be supplied

externally. Alternatively, adding a current-limiting resistor (for example, 470 Ω) in series with these pins

and any external driver could be considered to limit the potential for degradation to the pin and/or

external circuitry. There is no power-sequencing requirement when using an external 1.8-V supply.

However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered before

the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin

during power up. To avoid this behavior, power the V_DDpins before or simultaneously with the V_DDIO

pins, ensuring that the V_DDpins have reached 0.7 V before the V_DDIOpins reach 0.7 V.

6.2.1 Signal Descriptions ⁽¹⁾

PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

JTAG

JTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan

system control of the operations of the device. If this signal is not connected or driven

low, the device operates in its functional mode, and the test reset signals are ignored.

NOTE: TRST is an active-high test pin and must be maintained low at all times during

normal device operation. An external pulldown resistor is required on this pin. The

value of this resistor should be based on drive strength of the debugger pods applicable

to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is

application-specific, TI recommends validating each target board for proper operation of

the debugger and the application. (↓)

TRST

12

10

I

TCK

TMS

See GPIO38

I

See GPIO38. JTAG test clock with internal pullup. (↑)

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input

is clocked into the TAP controller on the rising edge of TCK. (↑)

See GPIO36

See GPIO35

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the

selected register (instruction or data) on a rising edge of TCK. (↑)

TDI

I

See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected

register (instruction or data) are shifted out of TDO on the falling edge of TCK.

(8-mA drive)

TDO

See GPIO37

O/Z

FLASH

V_DD3VFL

TEST2

46

45

37

36

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

Test Pin. Reserved for TI. Must be left unconnected.

I/O

12

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PZP

PN

PFP

CLOCK

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same

frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is

controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3.

The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate

to the pin.

XCLKOUT

See GPIO18

O/Z

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is

controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection.

This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if

available, must be tied to GND and the on-chip crystal oscillator must be disabled

through bit 14 in the CLKCTL register. If a crystal or resonator is used, the XCLKIN

path must be disabled by bit 13 in the CLKCTL register.

NOTE: Designs that use the GPIO38/XCLKIN/TCK pin to supply an external clock for

normal device operation may need to incorporate some hooks to disable this path

during debug using the JTAG connector. This is to prevent contention with the TCK

signal, which is active during JTAG debug sessions. The zero-pin internal oscillators

may be used during this time to clock the device.

See GPIO19 and

GPIO38

XCLKIN

I

On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic

resonator must be connected across X1 and X2. In this case, the XCLKIN path must be

disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND.

X1

X2

60

59

48

47

I

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be

connected across X1 and X2. If X2 is not used, it must be left unconnected.

O

RESET

Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-on

reset (POR) and brownout reset (BOR) circuitry. During a power-on or brownout

condition, this pin is driven low by the device. An external circuit may also drive this pin

to assert a device reset. This pin is also driven low by the MCU when a watchdog reset

occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset

duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be

placed between XRS and V_DDIO. If a capacitor is placed between XRS and V_SSfor

noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to

properly drive the XRS pin to V_OLwithin 512 OSCCLK cycles when the watchdog reset

is asserted. Regardless of the source, a device reset causes the device to terminate

execution. The program counter points to the address contained at the location

0x3F FFC0. When reset is deactivated, execution begins at the location designated by

the program counter. The output buffer of this pin is an open-drain device with an

internal pullup. (↑) If this pin is driven by an external device, it should be done using an

open-drain device.

XRS

11

9

I/OD

ADC, COMPARATOR, ANALOG I/O

ADC Group A, Channel 7 input

ADC Group A, Channel 6 input

Comparator Input 3A

ADCINA7

ADCINA6

COMP3A

AIO6

16

17

18

19

20

21

22

–

I

14

15

16

–

I

I/O

Digital AIO 6

ADCINA5

ADCINA4

COMP2A

AIO4

I

ADC Group A, Channel 5 input

ADC Group A, Channel 4 input

Comparator Input 2A

I

I/O

Digital AIO 4

ADCINA3

ADCINA2

COMP1A

AIO2

I

ADC Group A, Channel 3 input

ADC Group A, Channel 2 input

Comparator Input 1A

I

17

18

I/O

I

Digital AIO 2

ADCINA1

ADC Group A, Channel 1 input

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

ADC Group A, Channel 0 input.

ADCINA0

23

19

I

NOTE: V_REFHIand ADCINA0 share the same pin on the 80-pin PN and PFP devices

and their use is mutually exclusive to one another.

ADC External Reference High – only used when in ADC external reference mode. See

Section 8.9.2.1.

NOTE: V_REFHIand ADCINA0 share the same pin on the 80-pin PN and PFP devices

and their use is mutually exclusive to one another.

V_REFHI

24

35

34

33

32

31

30

19

–

ADCINB7

ADCINB6

COMP3B

AIO14

I

ADC Group B, Channel 7 input

ADC Group B, Channel 6 input

Comparator Input 3B

I

27

26

25

–

I

I/O

Digital AIO 14

ADCINB5

ADCINB4

COMP2B

AIO12

I

ADC Group B, Channel 5 input

ADC Group B, Channel 4 input

Comparator Input 2B

I

I/O

Digital AIO12

ADCINB3

ADCINB2

COMP1B

AIO10

I

ADC Group B, Channel 3 input

ADC Group B, Channel 2 input

Comparator Input 1B

I

24

I

I/O

I

Digital AIO 10

ADCINB1

ADCINB0

29

28

23

22

ADC Group B, Channel 1 input

ADC Group B, Channel 0 input

I

ADC External Reference Low.

NOTE: V_REFLOis always connected to V_SSAon the 80-pin PN and PFP devices.

V_REFLO

27

21

CPU AND I/O POWER

V_DDA

V_SSA

25

26

20

21

Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.

Analog Ground Pin.

NOTE: V_REFLOis always connected to V_SSAon the 80-pin PN and PFP devices.

3

2

14

37

63

81

91

5

12

29

51

65

72

4

CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF

capacitor between each V_DDpin and ground. Higher value capacitors may be used.

V_DD

13

38

61

79

93

4

11

30

49

63

74

3

Digital I/O Buffers Power Pin. Single supply source when VREG is enabled. Place a

decoupling capacitor on each pin. The exact value should be determined by the system

voltage regulation solution.

V_DDIO

15

36

47

62

80

92

13

28

38

50

64

73

V_SS

Digital Ground Pins

14

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

VOLTAGE REGULATOR CONTROL SIGNAL

VREGENZ

90

71

69

I

Internal VREG Enable/Disable. Pull low to enable VREG, pull high to disable VREG.

GPIO AND PERIPHERAL SIGNALS ⁽²⁾

General-purpose input/output 0

Enhanced PWM1 Output A and HRPWM channel

Reserved

GPIO0

I/O/Z

O

EPWM1A

Reserved

GPIO1

87

86

84

83

9

–

Reserved

I/O/Z

O

General-purpose input/output 1

Enhanced PWM1 Output B

Reserved

EPWM1B

Reserved

COMP1OUT

GPIO2

68

67

66

7

–

O

Direct output of Comparator 1

General-purpose input/output 2

Enhanced PWM2 Output A and HRPWM channel

Reserved

I/O/Z

O

EPWM2A

Reserved

GPIO3

–

Reserved

I/O/Z

O

General-purpose input/output 3

Enhanced PWM2 Output B

SPI-A slave out, master in

EPWM2B

SPISOMIA

COMP2OUT

GPIO4

I/O

O

Direct output of Comparator 2

General-purpose input/output 4

Enhanced PWM3 output A and HRPWM channel

Reserved

I/O/Z

O

EPWM3A

Reserved

GPIO5

–

Reserved

I/O/Z

O

General-purpose input/output 5

Enhanced PWM3 output B

EPWM3B

SPISIMOA

ECAP1

10

58

57

54

49

8

I/O

I/O/Z

O

SPI-A slave in, master out

Enhanced Capture input/output 1

General-purpose input/output 6

Enhanced PWM4 output A and HRPWM channel

External ePWM sync pulse input

External ePWM sync pulse output

General-purpose input/output 7

Enhanced PWM4 output B

GPIO6

EPWM4A

EPWMSYNCI

EPWMSYNCO

GPIO7

46

45

43

39

I

O

I/O/Z

O

EPWM4B

SCIRXDA

ECAP2

I

SCI-A receive data

I/O

I/O/Z

O

Enhanced Capture input/output 2

General-purpose input/output 8

Enhanced PWM5 output A and HRPWM channel

Reserved

GPIO8

EPWM5A

Reserved

ADCSOCAO

GPIO9

–

O

ADC start-of-conversion A

I/O/Z

O

General-purpose input/output 9

Enhanced PWM5 output B

EPWM5B

SCITXDB

ECAP3

O

SCI-B transmit data

I/O

Enhanced Capture input/output 3

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

GPIO10

I/O/Z

O

General-purpose input/output 10

EPWM6A

Reserved

ADCSOCBO

GPIO11

EPWM6B

SCIRXDB

ECAP1

Enhanced PWM6 output A and HRPWM channel

Reserved

74

73

44

95

96

88

55

52

60

59

35

75

76

70

44

42

–

O

ADC start-of-conversion B

General-purpose input/output 11

Enhanced PWM6 output B

SCI-B receive data

I/O/Z

O

I

I/O

I/O/Z

I

Enhanced Capture input/output 1

General-purpose input/output 12

Trip Zone input 1

GPIO12

TZ1

SCITXDA

SPISIMOB

GPIO13

TZ2

O

SCI-A transmit data

I/O

I/O/Z

I

SPI-B slave in, master out

General-purpose input/output 13

Trip Zone input 2

Reserved

SPISOMIB

GPIO14

TZ3

–

Reserved

I/O

I/O/Z

I

SPI-B slave out, master in

General-purpose input/output 14

Trip zone input 3

SCITXDB

SPICLKB

GPIO15

ECAP2

O

SCI-B transmit data

I/O

I/O/Z

I/O

I

SPI-B clock input/output

General-purpose input/output 15

Enhanced Capture input/output 2

SCI-B receive data

SCIRXDB

SPISTEB

GPIO16

SPISIMOA

Reserved

TZ2

I/O

I/O/Z

I/O

–

SPI-B slave transmit enable input/output

General-purpose input/output 16

SPI-A slave in, master out

Reserved

I

Trip Zone input 2

GPIO17

SPISOMIA

Reserved

TZ3

I/O/Z

I/O

–

General-purpose input/output 17

SPI-A slave out, master in

Reserved

I

Trip zone input 3

GPIO18

SPICLKA

SCITXDB

I/O/Z

I/O

O

General-purpose input/output 18

SPI-A clock input/output

SCI-B transmit data

51

41

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-

half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by

bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4.

The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control

for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.

XCLKOUT

O/Z

GPIO19

I/O/Z

I

General-purpose input/output 19

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken not to enable this path for clocking if it is

being used for the other peripheral functions.

XCLKIN

64

52

SPISTEA

SCIRXDB

ECAP1

I/O

I

SPI-A slave transmit enable input/output

SCI-B receive data

I/O

Enhanced Capture input/output 1

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

GPIO20

EQEP1A

MDXA

I/O/Z

I

General-purpose input/output 20

Enhanced QEP1 input A

6

5

6

O

McBSP transmit serial data

Direct output of Comparator 1

General-purpose input/output 21

Enhanced QEP1 input B

COMP1OUT

GPIO21

EQEP1B

MDRA

O

I/O/Z

I

7

98

2

I

McBSP receive serial data

Direct output of Comparator 2

General-purpose input/output 22

Enhanced QEP1 strobe

COMP2OUT

GPIO22

EQEP1S

MCLKXA

SCITXDB

GPIO23

EQEP1I

MFSXA

O

I/O/Z

I/O

O

78

1

McBSP transmit clock

SCI-B transmit data

I/O/Z

I/O

I

General-purpose input/output 23

Enhanced QEP1 index

McBSP transmit frame synch

SCI-B receive data

SCIRXDB

GPIO24

ECAP1

I/O/Z

I/O

General-purpose input/output 24

Enhanced Capture input/output 1

Enhanced QEP2 input A.

97

39

77

31

EQEP2A

I

NOTE: eQEP2 is available only in the PZ and PZP packages.

SPISIMOB

GPIO25

ECAP2

I/O

I/O/Z

I/O

SPI-B slave in, master out

General-purpose input/output 25

Enhanced Capture input/output 2

Enhanced QEP2 input B.

NOTE: eQEP2 is available only in the PZ and PZP packages.

EQEP2B

I

SPISOMIB

GPIO26

ECAP3

I/O

I/O/Z

I/O

SPI-B slave out, master in

General-purpose input/output 26

Enhanced Capture input/output 3

Enhanced QEP2 index.

NOTE: eQEP2 is available only in the PZ and PZP packages.

EQEP2I

I/O

78

62

SPICLKB

USB0DP⁽³⁾

SPI-B clock input/output

Positive Differential half of USB signal. To enable USB functionality on this pin, set the

USBIOEN bit in the GPACTRL2 register.

GPIO27

I/O/Z

I

General-purpose input/output 27

High-Resolution Input Capture 2

HRCAP2

Enhanced QEP2 strobe.

NOTE: eQEP2 is available only in the PZ and PZP packages.

EQEP2S

SPISTEB

USB0DM⁽³⁾

I/O

77

50

61

40

SPI-B slave transmit enable input/output

Negative Differential half of USB signal. To enable USB functionality on this pin, set the

USBIOEN bit in the GPACTRL2 register.

GPIO28

SCIRXDA

SDAA

I/O/Z

General-purpose input/output 28

SCI-A receive data

I

I/OD

I

I2C data open-drain bidirectional port

Trip zone input 2

TZ2

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

GPIO29

I/O/Z

General-purpose input/output 29

SCI-A transmit data

SCITXDA

SCLA

O

43

41

34

33

I/OD

I2C clock open-drain bidirectional port

Trip zone input 3

TZ3

I

I/O/Z

I

GPIO30

CANRXA

General-purpose input/output 30

CAN receive

Enhanced QEP2 index.

NOTE: eQEP2 is available only in the PZ and PZP packages.

EQEP2I

I/O

EPWM7A

GPIO31

O

I/O/Z

O

Enhanced PWM7 Output A and HRPWM channel

General-purpose input/output 31

CAN transmit

CANTXA

40

32

Enhanced QEP2 strobe.

NOTE: eQEP2 is available only in the PZ and PZP packages.

EQEP2S

I/O

EPWM8A

GPIO32

O

I/O/Z

I/OD

I

Enhanced PWM8 Output A and HRPWM channel

General-purpose input/output 32

I2C data open-drain bidirectional port

Enhanced PWM external sync pulse input

ADC start-of-conversion A

SDAA

99

100

68

79

80

55

EPWMSYNCI

ADCSOCAO

GPIO33

O

I/O/Z

I/OD

O

General-purpose input/output 33

I2C clock open-drain bidirectional port

Enhanced PWM external synch pulse output

ADC start-of-conversion B

SCLA

EPWMSYNCO

ADCSOCBO

GPIO34

O

I/O/Z

O

General-purpose input/output 34

Direct output of Comparator 2

COMP2OUT

Reserved

COMP3OUT

GPIO35

–

Reserved

O

Direct output of Comparator 3

I/O/Z

General-purpose input/output 35

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDI

I

71

72

70

57

58

56

Reserved

GPIO36

–

Reserved

–

Reserved

I/O/Z

General-purpose input/output 36

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked

into the TAP controller on the rising edge of TCK.

TMS

I

Reserved

GPIO37

–

Reserved

–

Reserved

I/O/Z

General-purpose input/output 37

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).

TDO

O/Z

Reserved

–

Reserved

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

GPIO38

XCLKIN

I/O/Z

I

General-purpose input/output 38

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken to not enable this path for clocking if it is

being used for the other functions.

67

54

TCK

I

JTAG test clock with internal pullup

Reserved

GPIO39

Reserved

GPIO40

EPWM7A

SCITXDB

Reserved

GPIO41

EPWM7B

SCIRXDB

Reserved

GPIO42

EPWM8A

TZ1

–

Reserved

–

Reserved

I/O/Z

General-purpose input/output 39

Reserved

–

66

82

76

1

53

–

Reserved

–

Reserved

I/O/Z

General-purpose input/output 40

Enhanced PWM7 output A and HRPWM channel

SCI-B transmit data

O

–

Reserved

I/O/Z

General-purpose input/output 41

Enhanced PWM7 output B

SCI-B receive data

O

–

I

–

Reserved

I/O/Z

General-purpose input/output 42

Enhanced PWM8 output A and HRPWM channel

Trip zone input 1

O

–

I

COMP1OUT

GPIO43

EPWM8B

TZ2

O

Direct output of Comparator 1

General-purpose input/output 43

Enhanced PWM8 output B

Trip zone input 2

I/O/Z

O

8

–

I

COMP2OUT

GPIO44

MFSRA

SCIRXDB

EPWM7B

GPIO50

EQEP1A

MDXA

O

Direct output of Comparator 2

General-purpose input/output 44

McBSP receive frame synch

SCI-B receive data

I/O/Z

I/O

56

42

48

53

–

I

O

Enhanced PWM7 output B

General-purpose input/output 50

Enhanced QEP1 input A

McBSP transmit serial data

Trip zone input 1

I/O/Z

I

–

O

TZ1

I

GPIO51

EQEP1B

MDRA

I/O/Z

General-purpose input/output 51

Enhanced QEP1 input B

McBSP receive serial data

Trip zone input 2

I

–

I

TZ2

GPIO52

EQEP1S

MCLKXA

TZ3

I/O/Z

I/O

I

General-purpose input/output 52

Enhanced QEP1 strobe

McBSP transmit clock

Trip zone input 3

–

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

PIN NO.

PIN NAME

I/O/Z

DESCRIPTION

PZ

PN

PZP

PFP

GPIO53

I/O/Z

I/O

–

General-purpose input/output 53

Enhanced QEP1 index

EQEP1I

65

69

75

85

89

94

–

MFSXA

McBSP transmit frame synch

Reserved

GPIO54

I/O/Z

I/O

I

General-purpose input/output 54

SPI-A slave in, master out

Enhanced QEP2 input A

SPISIMOA

EQEP2A

HRCAP1

GPIO55

I

High-Resolution Input Capture 1

General-purpose input/output 55

SPI-A slave out, master in

Enhanced QEP2 input B

I/O/Z

I/O

I

SPISOMIA

EQEP2B

HRCAP2

GPIO56

I

High-Resolution Input Capture 2

General-purpose input/output 56

SPI-A clock input/output

I/O/Z

I/O

I

SPICLKA

EQEP2I

Enhanced QEP2 index

HRCAP3

GPIO57

High-Resolution Input Capture 3

General-purpose input/output 57

I/O/Z

I/O

I

SPISTEA

EQEP2S

HRCAP4

GPIO58

SPI-A slave transmit enable input/output

Enhanced QEP2 strobe

High-Resolution Input Capture 4

General-purpose input/output 58

McBSP receive clock

I/O/Z

I/O

O

MCLKRA

SCITXDB

EPWM7A

SCI-B transmit data

O

Enhanced PWM7 output A and HRPWM channel

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate

functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output

path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal.

See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual .

(3) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more

information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Technical Reference Manual .

20

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2)}

MIN

–0.3

–20

MAX

4.6

2.5

4.6

2.5

4.6

20

UNIT

V_DDIO(I/O and Flash) with respect to V_SS

Supply voltage

V

V_DDwith respect to V_SS

Analog voltage

Input voltage

Output voltage

V_DDAwith respect to V_SSA

V_IN(3.3 V)

V_IN(X1)

V_O

(3)

Digital input (per pin), I_IK(V_IN< V_SSor V_IN> V_DDIO

Analog input (per pin), I_IKANALOG

)

–20

20

Input clamp current

(V_IN< V_SSAor V_IN> V_DDA

)

mA

Total for all inputs, I_IKTOTAL

(V_IN< V_SS/V_SSAor V_IN> V_DDIO/V_DDA

)

Output clamp current

Junction temperature⁽⁴⁾

Storage temperature⁽⁴⁾

I_OK(V_O< 0 or V_O> V_DDIO

)

–20

–40

–65

20

150

mA

°C

T_J

T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Continuous clamp current per pin is ±2 mA.

(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device

life. For additional information, see Semiconductor and IC Package Thermal Metrics.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.2 ESD Ratings – Commercial

VALUE

UNIT

TMS320F2806x, TMS320F2806xM, TMS320F2806xF, and TMS320F2806xU in 100-pin PZ package

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge (ESD)

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101 or ANSI/ESDA/JEDEC JS-002⁽²⁾

TMS320F2806x, TMS320F2806xM, TMS320F2806xF, and TMS320F2806xU in 80-pin PN package

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge (ESD)

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101 or ANSI/ESDA/JEDEC JS-002⁽²⁾

TMS320F2806xU in 100-pin PZP package

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge (ESD)

Charged-device model (CDM), per JEDEC specification JESD22-

C101 or ANSI/ESDA/JEDEC JS-002⁽²⁾

TMS320F2806xU in 80-pin PFP package

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge (ESD)

Charged-device model (CDM), per JEDEC specification JESD22-

C101 or ANSI/ESDA/JEDEC JS-002⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 ESD Ratings – Automotive

VALUE

UNIT

TMS320F2806x, TMS320F2806xM, and TMS320F2806xF in 100-pin PZP package

Human body model (HBM), per

AEC Q100-002⁽¹⁾

All pins

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM),

per AEC Q100-011

All pins

±500

±750

V

Corner pins on 100-pin PZP:

1, 25, 26, 50, 51, 75, 76, 100

TMS320F2806x, TMS320F2806xM, and TMS320F2806xF in 80-pin PFP packages

Human body model (HBM), per

AEC Q100-002⁽¹⁾

All pins

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM),

per AEC Q100-011

All pins

±500

±750

V

Corner pins on 80-pin PFP:

1, 20, 21, 40, 41, 60, 61, 80

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

22

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.4 Recommended Operating Conditions

MIN

2.97

1.71

NOM

3.3

MAX

3.63

UNIT

Device supply voltage, I/O, V_DDIO

V

Device supply voltage CPU, V_DD(When internal VREG is

disabled and 1.8 V is supplied externally)

1.8

1.995

V

Supply ground, V_SS

0

3.3

0

V

Analog supply voltage, V_DDA

2.97

3.63

Analog ground, V_SSA

V

Device clock frequency (system clock)

High-level input voltage, V_IH(3.3 V)

Low-level input voltage, V_IL(3.3 V)

High-level output source current, V_OH= V_OH(MIN), I_OH

2

90

MHz

V

V_DDIO+ 0.3

V_SS– 0.3

0.8

–4

V

All GPIO/AIO pins

Group 2⁽¹⁾

mA

–8

Low-level output sink current, V_OL= V_OL(MAX), I_OL

Junction temperature, T_J

All GPIO/AIO pins

Group 2⁽¹⁾

4

8

T version

–40

105

125

°C

S version

Ambient temperature, T_A

Q version⁽²⁾

(AEC Q100 qualification)

(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37.

(2) The Q temperature option is not available on the 2806xU devices.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.5 Power Consumption Summary

7.5.1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(1)

(2)

(1)

(2)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽³⁾

I_DDA

MAX TYP⁽³⁾

I_DD3VFL

MAX TYP⁽³⁾

I_DD

TYP⁽³⁾

I_DDIO

I_DDA

MAX TYP⁽³⁾

I_DD3VFL

MAX

MAX TYP⁽³⁾

MAX

The following

peripheral clocks are

enabled:

•

ePWM1, ePWM2,

ePWM3, ePWM4,

ePWM5, ePWM6,

ePWM7, ePWM8

•

eCAP1, eCAP2,

eCAP3

•

eQEP1, eQEP2

eCAN

CLA

HRPWM

SCI-A, SCI-B

SPI-A, SPI-B

ADC

Operational

(Flash)

185 mA⁽⁷⁾245 mA⁽⁷⁾16 mA 22 mA 35 mA 40 mA 165 mA⁽⁷⁾220 mA⁽⁷⁾15 mA 20 mA 16 mA 22 mA 35 mA 40 mA

I2C

COMP1, COMP2,

COMP3

•

CPU-TIMER0,

CPU-TIMER1,

CPU-TIMER2

•

McBSP

USB

All PWM pins are

toggled at 90 kHz.

All I/O pins are left

unconnected.^{(4) (6)}

Code is running out of

flash with 3 wait states.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks

are turned off.

IDLE

22 mA

9 mA

27 mA

11 mA

15 µA

25 µA

5 µA

10 µA

21 mA

8 mA

26 mA 120 µA 400 µA

10 mA 120 µA 400 µA

15 µA

25 µA

5 µA

10 µA

Flash is powered down.

Peripheral clocks are

off.

STANDBY

Flash is powered down.

Peripheral clocks are

off.

HALT

75 µA

15 µA

25 µA

5 µA

10 µA

25 µA⁽⁸⁾

40 µA

15 µA

25 µA

5 µA

10 µA

Input clock is disabled.

(5)

(1) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(2) To realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to

the PCLKCR0 register.

(3) The TYP numbers are applicable over room temperature and nominal voltage.

(4) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A, SPI-B, SCI-A, eCAN-A, McBSP-A, and I2C ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1 and COMP2 are continuously switching voltages.

GPIO17 is toggled.

(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

(6) CLA is continuously performing polynomial calculations.

(7) For F2806x devices that do not have CLA, subtract the I_DDcurrent number for CLA (see Table 7-1) from the I_DD(VREG disabled)/I_DDIO

(VREG enabled) current numbers listed in Section 7.5.1 for operational mode.

(8) To realize the I_DDnumber shown for HALT mode, the following must be done:

•

PLL2 must be shut down by clearing bit 2 of the PLLCTL register.

A value of 0x00FF must be written to the HRCAL register at address 0x6822.

24

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Note

The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from

being used at the same time. This is because more than one peripheral function may share an I/O pin.

It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a

configuration is not useful. If this is done, the current drawn by the device will be more than the

numbers specified in the current consumption tables.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.5.2 Reducing Current Consumption

The 2806x devices incorporate a method to reduce the device current consumption. Because each peripheral

unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning

off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three

low-power modes could be taken advantage of to reduce the current consumption even further. Table 7-1

indicates the typical reduction in current consumption achieved by turning off the clocks.

Table 7-1. Typical Current Consumption by Various

Peripherals (at 90 MHz) ⁽¹⁾

PERIPHERAL

MODULE⁽³⁾

I_DDCURRENT

REDUCTION (mA)

ADC

2⁽²⁾

I2C

3

ePWM

2

eCAP

2

eQEP

2

SCI

SPI

2

COMP/DAC

HRPWM

1

3

HRCAP

3

USB

12

1

CPU-TIMER

Internal zero-pin oscillator

CAN

0.5

2.5

20

6

CLA

McBSP

(1) All peripheral clocks (except CPU Timer clock) are disabled

upon reset. Writing to or reading from peripheral registers is

possible only after the peripheral clocks are turned on.

(2) This number represents the current drawn by the digital portion

of the ADC module. Turning off the clock to the ADC module

results in the elimination of the current drawn by the analog

portion of the ADC (I_DDA) as well.

(3) For peripherals with multiple instances, the current quoted is per

module. For example, the 2 mA value quoted for ePWM is for

one ePWM module.

Note

I_DDIOcurrent consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

Note

The baseline I_DDcurrent (current when the core is executing a dummy loop with no peripherals

enabled) is 40 mA, typical. To arrive at the I_DDcurrent for a given application, the current-drawn by the

peripherals (enabled by that application) must be added to the baseline I_DDcurrent.

26

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Following are other methods to reduce power consumption further:

•

The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18

mA (typical) in the V_DDrail and 13 mA (typical) in the V_DDIOrail.

•

Savings in I_DDIOmay be realized by disabling the pullups on pins that assume an output function.

To realize the lowest V_DDAcurrent consumption in a low-power mode, see the respective analog chapter of

the TMS320x2806x Technical Reference Manual to ensure each module is powered down as well.

Power savings can be achieved by powering down the flash. This must be done by code running off RAM

(not flash).

•

7.5.3 Current Consumption Graphs (VREG Enabled)

250

200

150

100

50

IDDIO

IDDA

IDD3VFL

Total

0

10

20

30

40

50

60

70

80

90

SYSCLKOUT (MHz)

Figure 7-1. Typical Operational Current (Flash) Versus Frequency (Internal VREG)

900

800

700

600

500

400

300

200

100

0

10

20

30

40

50

60

70

80

90

SYSCLKOUT (MHz)

Figure 7-2. Typical Operational Power Versus Frequency (Internal VREG)

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.6 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

2.4

TYP

MAX UNIT

I_OH= I_OHMAX

I_OH= 50 μA

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

V_DDIO– 0.2

I_OL= I_OLMAX

0.4

–205

–375

V

All GPIO

–80 –140

Pin with pullup

V_DDIO= 3.3 V, V_IN= 0 V

enabled

Input current

(low level)

XRS pin

–230 –300

I_IL

μA

Pin with pulldown

enabled

V_DDIO= 3.3 V, V_IN= 0 V

V_DDIO= 3.3 V, V_IN= V_DDIO

V_O= V_DDIOor 0 V

±2

80

Pin with pullup

enabled

Input current

(high level)

I_IH

μA

Pin with pulldown

enabled

28

50

Output current, pullup or pulldown

disabled

I_OZ

C_I

±2 μA

pF

Input capacitance

2

2.78

35

V_DDIOBOR trip point

V_DDIOBOR hysteresis

Falling V_DDIO

2.50

400

2.96

V

mV

Supervisor reset release delay

time

Time after BOR/POR/OVR event is removed to XRS

release

800 μs

V

VREG V_DDoutput

Internal VREG on

1.9

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(V_DD) go out of range.

28

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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7.7 Thermal Resistance Characteristics

7.7.1 PFP PowerPAD Package

°C/W⁽¹⁾

9.4

AIR FLOW (lfm)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case thermal resistance

Junction-to-board thermal resistance

0

4.6

0

25.8

16.3

15.2

13.6

0.3

0

150

250

500

0

RΘ_JA

(High k PCB)

Junction-to-free air thermal resistance

Junction-to-package top

0.4

150

250

500

0

Psi_JT

0.4

0.5

4.6

4.4

150

250

500

Psi_JB

Junction-to-board

4.3

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

7.7.2 PZP PowerPAD Package

°C/W⁽¹⁾

9.4

AIR FLOW (lfm)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case thermal resistance

0

Junction-to-board thermal resistance

4.4

0

24.4

15.1

13.9

12.4

0.3

0

150

250

500

0

RΘ_JA

(High k PCB)

Junction-to-free air thermal resistance

0.4

150

250

500

0

Psi_JT

Junction-to-package top

Junction-to-board

0.4

0.5

4.5

4.2

150

250

500

Psi_JB

4.2

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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(2) lfm = linear feet per minute

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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7.7.3 PN Package

°C/W⁽¹⁾

7.9

AIR FLOW (lfm)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case thermal resistance

0

Junction-to-board thermal resistance

15.6

41.1

31.2

29.7

27.5

0.4

0

150

250

500

0

RΘ_JA

(High k PCB)

Junction-to-free air thermal resistance

0.6

150

250

500

0

Psi_JT

Junction-to-package top

Junction-to-board

0.7

0.9

15.3

14.6

14.4

14.1

150

250

500

Psi_JB

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

7.7.4 PZ Package

°C/W⁽¹⁾

7.2

AIR FLOW (lfm)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case thermal resistance

0

Junction-to-board thermal resistance

19.6

42.2

32.4

30.9

28.7

0.4

0

150

250

500

0

RΘ_JA

(High k PCB)

Junction-to-free air thermal resistance

0.6

150

250

500

0

Psi_JT

Junction-to-package top

Junction-to-board

0.7

0.9

19.1

18.2

17.9

14.1

150

250

500

Psi_JB

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/

JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.8 Thermal Design Considerations

Based on the end application design and operational profile, the I_DDand I_DDIOcurrents could vary. Systems that

exceed the recommended maximum power dissipation in the end product may require additional thermal

enhancements. Ambient temperature (T_A) varies with the end application and product design. The critical factor

that affects reliability and functionality is T_J, the junction temperature, not the ambient temperature. Hence, care

should be taken to keep T_Jwithin the specified limits. T_caseshould be measured to estimate the operating

junction temperature T_J. T_caseis normally measured at the center of the package top-side surface. The thermal

application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and

definitions.

7.9 Debug Probe Connection Without Signal Buffering for the MCU

Figure 7-3 shows the connection between the MCU and JTAG header for a single-processor configuration. If the

distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be

buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 7-3 shows the simpler, no-

buffering situation. For the pullup and pulldown resistor values, see Section 6.2.

6 inches or less

V_DDIO

13

14

2

5

EMU0

EMU1

TRST

TMS

PD

4

6

8

TRST

TMS

TDI

GND

1

GND

3

TDI

7

10

12

TDO

TCK

TDO

11

9

TCK

TCK_RET

MCU

JTAG Header

A. See Figure 8-54 for JTAG/GPIO multiplexing.

Figure 7-3. Debug Probe Connection Without Signal Buffering for the MCU

Note

The 2806x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header onboard,

the EMU0/EMU1 pins on the header must be tied to V_DDIOthrough a 4.7-kΩ (typical) resistor.

32

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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7.10 Parameter Information

7.10.1 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,

some of the pin names and other related terminology have been abbreviated as follows:

LOWERCASE SUBSCRIPTS AND THEIR MEANINGS:

LETTERS AND SYMBOLS AND THEIR MEANINGS:

a

c

d

f

access time

cycle time (period)

delay time

H

L

High

Low

V

X

Z

Valid

fall time

Unknown, changing, or don't care level

High impedance

h

r

hold time

rise time

su

t

setup time

transition time

valid time

v

w

pulse duration (width)

7.10.2 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all

output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For

actual cycle examples, see the appropriate cycle description section of this document.

7.11 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

Tester Pin Electronics

Data Sheet Timing Reference Point

W

3.5 nH

Output

Under

Test

42

Transmission Line

(A)

Z0 = 50 W

Device Pin^(B)

4.0 pF

1.85 pF

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects

must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line

effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)

from the data sheet timing.

Figure 7-4. 3.3-V Test Load Circuit

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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7.12 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to

prevent the I/Os from glitching during power up or power down (GPIO19, GPIO26–27, GPIO34–38 do not have

glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above V_DDIOshould be applied to any digital pin (for

analog pins, this value is 0.7 V above V_DDA) before powering up the device. Voltages applied to pins on an

unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

V_DDIO, V_DDA

(3.3 V)

V_DD(1.8 V)

INTOSC1

t_INTOSCST

X1/X2

t_OSCST

(B)

(A)

XCLKOUT

User-code dependent

t

w(RSL1)

XRS^(D)

Address/data valid, internal boot-ROM code execution phase

Address/Data/

Control

(Internal)

User-code execution phase

User-code dependent

t

d(EX)

(C)

h(boot-mode)

t

Boot-Mode

Pins

GPIO pins as input

Peripheral/GPIO function

Based on boot code

Boot-ROM execution starts

(E)

GPIO pins as input [state depends on internal pullup/pulldown (PU/PD)]

I/O Pins

User-code dependent

A. Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0,

SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase.

B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not be visible at the

pin until explicitly configured by user code.

C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to

destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot

code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be

with or without PLL enabled.

D. Using the XRS pin is optional due to the on-chip POR circuitry.

E. The internal pullup or pulldown will take effect when BOR is driven high.

Figure 7-5. Power-on Reset

34

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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7.12.1 Reset ( XRS) Timing Requirements

MIN

1000t_c(SCO)

32t_c(OSCCLK)

MAX

UNIT

cycles

t_h(boot-mode)

t_w(RSL2)

Hold time for boot-mode pins

Pulse duration, XRS low on warm reset

7.12.2 Reset ( XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

μs

t_w(RSL1)

t_w(WDRS)

t_d(EX)

Pulse duration, XRS driven by device

600

Pulse duration, reset pulse generated by watchdog

Delay time, address/data valid after XRS high

Start-up time, internal zero-pin oscillator

On-chip crystal-oscillator start-up time

512t_c(OSCCLK)

cycles

μs

32t_c(OSCCLK)

t_INTOSCST

3

(1)

t_OSCST

1

10

ms

(1) Dependent on crystal/resonator and board design.

INTOSC1

X1/X2

XCLKOUT

User-Code Dependent

t

w(RSL2)

XRS

User-Code Execution Phase

t

d(EX)

Address/Data/

User-Code Execution

Control

(Internal)

(A)

t

Boot-ROM Execution Starts

GPIO Pins as Input

h(boot-mode)

Boot-Mode

Pins

Peripheral/GPIO Function

User-Code Dependent

Peripheral/GPIO Function

User-Code Execution Starts

I/O Pins

GPIO Pins as Input (State Depends on Internal PU/PD)

User-Code Dependent

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to

destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot

code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be

with or without PLL enabled.

Figure 7-6. Warm Reset

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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Figure 7-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004

and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is

written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is

complete, SYSCLKOUT reflects the new operating frequency, OSCCLK × 4.

OSCCLK

Write to PLLCR

SYSCLKOUT

OSCCLK * 2

OSCCLK/2

OSCCLK * 4

(CPU frequency while PLL is stabilizing

with the desired frequency. This period

(PLL lock-up time t_p) is 1 ms long.)

(Current CPU

Frequency)

(Changed CPU frequency)

Figure 7-7. Example of Effect of Writing Into PLLCR Register

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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7.13 Clock Specifications

7.13.1 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options

available on the 2806x MCUs. Section 7.13.1.1 lists the cycle times of various clocks.

7.13.1.1 2806x Clock Table and Nomenclature (90-MHz Devices)

MIN

11.11

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

90

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

11.11

44.4⁽²⁾

22.5⁽²⁾

90

45

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

22.22

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 90 MHz.

7.13.1.2 Device Clocking Requirements/Characteristics

MIN

50

NOM

MAX UNIT

t_c(OSC), Cycle time

Frequency

200

20

ns

MHz

ns

On-chip oscillator (X1/X2 pins)

(Crystal/Resonator)

5

t_c(CI), Cycle time (C8)

Frequency

33.3

5

200

30

External oscillator/clock source

(XCLKIN pin) — PLL Enabled

MHz

ns

t_c(CI), Cycle time (C8)

Frequency

11.11

4

250

90

External oscillator/clock source

(XCLKIN pin) — PLL Disabled

MHz

Limp mode SYSCLKOUT

(with /2 enabled)

Frequency range

1 to 5

MHz

t_c(XCO), Cycle time (C1)

44.44

0.5

2000

22.5

1

ns

MHz

ms

XCLKOUT

Frequency

t_p

PLL lock time⁽¹⁾

(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are

used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics

PARAMETER

Internal zero-pin oscillator 1 (INTOSC1) at 30°C^{(1) (2)}

Internal zero-pin oscillator 2 (INTOSC2) at 30°C^{(1) (2)}

Step size (coarse trim)

MIN

TYP

10.000

55

MAX

UNIT

MHz

Frequency

MHz

kHz

Step size (fine trim)

14

kHz

Temperature drift⁽³⁾

3.03

4.85

kHz/°C

Hz/mV

Voltage (V_DD) drift⁽³⁾

175

(1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, refer to the Oscillator Compensation Guide.

(2) Frequency range ensured only when VREG is enabled, VREGENZ = V_SS

.

(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (V_DD) gradient. For

example:

•

Increase in temperature will cause the output frequency to increase per the temperature coefficient.

Decrease in voltage (V_DD) will cause the output frequency to decrease per the voltage coefficient.

10.6

10.5

10.4

10.3

10.2

10.1

10

9.9

9.8

9.7

9.6

–40

–30

–20

–10

0

10

20

30

40

50

60

70

80

90

100

110

120

Typical

Max

Temperature (°C)

Figure 7-8. Zero-Pin Oscillator Frequency Movement With Temperature

38

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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7.13.2 Clock Requirements and Characteristics

7.13.2.1 XCLKIN Timing Requirements – PLL Enabled

NO.

MIN

MAX UNIT

C9

t_f(CI)

Fall time, XCLKIN

6

ns

C10 t_r(CI)

Rise time, XCLKIN

C11 t_w(CIL)

C12 t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45%

55%

7.13.2.2 XCLKIN Timing Requirements – PLL Disabled

NO.

MIN

MAX UNIT

Up to 20 MHz

6

C9

t_f(CI)

Fall time, XCLKIN

Rise time, XCLKIN

ns

2

20 MHz to 90 MHz

Up to 20 MHz

6

C10 t_r(CI)

ns

2

20 MHz to 90 MHz

C11 t_w(CIL)

C12 t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45%

55%

The possible configuration modes are shown in Table 8-15.

7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)

over recommended operating conditions (unless otherwise noted)^{(1) (2)}

NO.

C3

C4

C5

C6

PARAMETER

MIN

MAX

UNIT

ns

t_f(XCO)

Fall time, XCLKOUT

Rise time, XCLKOUT

5

t_r(XCO)

ns

t_w(XCOL)

t_w(XCOH)

Pulse duration, XCLKOUT low

Pulse duration, XCLKOUT high

H – 2

H + 2

ns

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5t_c(XCO)

C10

C9

C8

(A)

XCLKIN

C6

C3

C1

C4

C5

(B)

XCLKOUT

A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate

the timing parameters only and may differ based on actual configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 7-9. Clock Timing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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7.14 Flash Timing

7.14.1 Flash/OTP Endurance for T Temperature Material

ERASE/PROGRAM

MIN

20000

TYP

MAX

UNIT

TEMPERATURE⁽¹⁾

0°C to 105°C (ambient)

0°C to 30°C (ambient)

N_f

Flash endurance for the array (write/erase cycles)

50000

cycles

write

N_OTPOTP endurance for the array (write cycles)

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

7.14.2 Flash/OTP Endurance for S Temperature Material

ERASE/PROGRAM

MIN

TYP

MAX

UNIT

TEMPERATURE⁽¹⁾

0°C to 125°C (ambient)

0°C to 30°C (ambient)

N_f

Flash endurance for the array (write/erase cycles)

20000

50000

cycles

write

N_OTPOTP endurance for the array (write cycles)

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

7.14.3 Flash/OTP Endurance for Q Temperature Material

ERASE/PROGRAM

MIN

TYP

MAX

UNIT

TEMPERATURE^{(1) (2)}

–40°C to 125°C (ambient)

–40°C to 30°C (ambient)

N_f

Flash endurance for the array (write/erase cycles)

20000

50000

cycles

write

N_OTPOTP endurance for the array (write cycles)

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

(2) The "Q" temperature option is not available on the 2806xU devices.

7.14.4 Flash Parameters at 90-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

16-Bit Word

16K Sector

8K Sector

4K Sector

16K Sector

8K Sector

4K Sector

50

500

250

125

2

μs

2000⁽²⁾

ms

Program Time⁽¹⁾

Erase Time⁽³⁾

2000⁽²⁾

15⁽²⁾

2

15⁽²⁾

s

2

15⁽²⁾

(4)

I_DDP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

80

60

120

VREG disabled

VREG enabled

mA

(4)

I_DDIOP

(4)

I_DDIOP

(1) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the

required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine

but does not include the time to transfer the following into RAM:

•

the code that uses flash API to program the flash

the Flash API itself

Flash data to be programmed

(2) The parameters mentioned in the MAX column are for the first 100 Erase/Program cycles.

(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required

before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent

programming operations.

(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a

stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash

programming could be higher than normal operating conditions. The power supply used should ensure V_MINon the supply rails at all

times, as specified in the Recommended Operating Conditions of the data sheet. Any brownout or interruption to power during erasing/

programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash

40

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during

the programming process.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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7.14.5 Flash/OTP Access Timing

PARAMETER

MIN

36

MAX UNIT

t_a(fp)

Paged Flash access time

Random Flash access time

OTP access time

ns

t_a(fr)

36

t_a(OTP)

60

7.14.6 Flash Data Retention Duration

PARAMETER

TEST CONDITIONS

T_J= 55°C

MIN

15

MAX UNIT

t_retention

Data retention duration

years

Table 7-2. Minimum Required Flash/OTP Wait States at Different Frequencies

SYSCLKOUT

(ns)

PAGE

RANDOM

OTP

WAIT STATE

(MHz)

WAIT STATE⁽¹⁾

90

11.11

12.5

3

2

1

3

2

1

5

4

3

2

1

80

70

14.29

16.67

18.18

20

60

55

50

45

22.22

25

40

35

28.57

33.33

30

(1) Page and random wait state must be ≥ 1.

The equations to compute the Flash page wait state and random wait state in Table 7-2 are as follows:

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_{a(f ×p)}

Flash Page Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_{a(f ×r)}

Flash Random Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

The equation to compute the OTP wait state in Table 7-2 is as follows:

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_a(OTP)

OTP Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8 Detailed Description

8.1 Overview

8.1.1 CPU

The 2806x (C28x) family is a member of the TMS320C2000^™microcontroller (MCU) platform. The C28x-based

controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based controller,

including the 2806x device, is a very efficient C/C++ engine, enabling users to develop not only their system

control software in a high-level language, but also enabling development of math algorithms using C/C++. The

device is as efficient at MCU math tasks as it is at system control tasks that typically are handled by

microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 × 32-

bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems

efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a

device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-

deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds

without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency

for conditional discontinuities. Special store conditional operations further improve performance.

8.1.2 Control Law Accelerator (CLA)

The C28x CLA is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by

adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism,

and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a

peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to

completion. When a task completes, the main CPU is notified by an interrupt to the PIE and the CLA

automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result

registers, ePWM+HRPWM, eCAP, and eQEP registers. Dedicated message RAMs provide a method to pass

additional data between the main CPU and the CLA.

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8.1.3 Viterbi, Complex Math, CRC Unit (VCU)

The C28x VCU enhances the processing power of C2000^™devices by adding additional assembly instructions

to target complex math, Viterbi decode, and CRC calculations. The VCU instructions accelerate many

applications, including the following:

•

Orthogonal frequency-division multiplex (OFDM) used in the PRIME and G3 standards for power line

communications

•

Short-range radar complex math calculations

Power calculations

Memory and data communication packet checks (CRC)

The VCU features include:

•

Instructions to support Cyclic Redundancy Checks (CRCs), which is a polynomial code checksum.

– CRC8

– CRC16

– CRC32

•

Instructions to support a flexible software implementation of a Viterbi decoder

– Branch metric calculations for a code rate of 1/2 or 1/3

– Add-Compare Select or Viterbi Butterfly in five cycles per butterfly

– Traceback in three cycles per stage

– Easily supports a constraint length of K = 7 used in PRIME and G3 standards

Complex math arithmetic unit

– Single-cycle Add or Subtract

– 2-cycle multiply

– 2-cycle multiply and accumulate (MAC)

– Single-cycle repeat MAC

Independent register space

•

8.1.4 Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple buses are used to move data between the memories and peripherals

and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus.

The program read bus consists of 22 address lines and 32 data lines. The data read and write buses consist of

32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit operations. The

multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data

value and write a data value in a single cycle. All peripherals and memories attached to the memory bus

prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows:

Highest:

Data Writes

Program Writes

Data Reads

Program Reads

Fetches

(Simultaneous data and program writes cannot occur on the memory bus.)

(Simultaneous program reads and fetches cannot occur on the memory bus.)

Lowest:

44

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8.1.5 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices

adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various

buses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32

data lines and associated control signals. Three versions of the peripheral bus are supported. One version

supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit

accesses (called peripheral frame 1).

8.1.6 Real-Time JTAG and Analysis

1

The devices implement the standard IEEE 1149.1 JTAG interface for in-circuit based debug. Additionally, the

devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and

register locations while the processor is running and executing code and servicing interrupts. The user can also

single step through non-time-critical code while enabling time-critical interrupts to be serviced without

interference. The device implements the real-time mode in hardware within the CPU. This is a feature unique to

the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that

allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable

break events when a match occurs.

8.1.7 Flash

The F28069, F28069F, F28069M, F28068F, F28068M, F28067, and F28066 devices contain 128K × 16 of

embedded flash memory, segregated into eight 16K × 16 sectors. The F28065, F28064, F28063, F28062, and

F28062F devices contain 64K × 16 of embedded flash memory, segregated into eight 8K × 16 sectors. All

devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to 0x3D 7BF9. The user can

individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not

possible to use one sector of the flash or the OTP to execute flash algorithms that erase or program other

sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The

flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data

information. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data variables and should not contain program

code.

Note

The Flash and OTP wait states can be configured by the application. This allows applications running

at slower frequencies to configure the flash to use fewer wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options

register. With this mode enabled, effective performance of linear code execution will be much faster

than the raw performance indicated by the wait-state configuration alone. The exact performance gain

when using the Flash pipeline mode is application-dependent.

For more information on the Flash options, Flash wait state, and OTP wait-state registers, see the

Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual .

1

IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

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TMS320F28062 TMS320F28062F

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8.1.8 M0, M1 SARAMs

All devices contain these two blocks of single-access memory, each 1K × 16 in size. The stack pointer points to

the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are

mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data

variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the

programmer. This makes for easier programming in high-level languages.

8.1.9 L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs

The device contains up to 48K × 16 of single-access RAM. To ascertain the exact size for a given device, see

the device-specific memory map figures in Section 8.2. This block is mapped to both program and data space.

L0 is 2K in size. L1 and L2 are each 1K in size. L3 is 4K in size. L4, L5, L6, L7, and L8 are each 8K in size. L0,

L1, and L2 are shared with the CLA, which can use these blocks for its data space. L3 is shared with the CLA,

which can use this block for its program space. L5, L6, L7, and L8 are shared with the DMA, which can use

these blocks for its data space. DPSARAM refers to the dual-port configuration of these blocks.

8.1.10 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the

bootloader software what boot mode to use on power up. The user can select to boot normally or to download

new software from an external connection or to select boot software that is programmed in the internal Flash/

ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related

algorithms.

Table 8-1. Boot Mode Selection

GPIO34/COMP2OUT/

MODE

GPIO37/TDO

TRST

MODE

COMP3OUT

3

2

1

0

x

1

0

1

0

x

0

1

GetMode

Wait (see Section 8.1.11 for description)

1

SCI

0

Parallel IO

Emulation Boot

EMU

8.1.10.1 Emulation Boot

When the debug probe is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this case,

the boot ROM detects that a debug probe is connected and uses the contents of two reserved SARAM locations

in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot

option is used. All boot mode options can be accessed in emulation boot.

8.1.10.2 GetMode

The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot

option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash

is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.

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8.1.10.3 Peripheral Pins Used by the Bootloader

Table 8-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if

these conflict with any of the peripherals you would like to use in your application.

Table 8-2. Peripheral Bootload Pins

BOOTLOADER

PERIPHERAL LOADER PINS

SCI

SCIRXDA (GPIO28)

SCITXDA (GPIO29)

Parallel Boot

SPI

Data (GPIO31,30,5:0)

28x Control (AIO6)

Host Control (AIO12)

SPISIMOA (GPIO16)

SPISOMIA (GPIO17)

SPICLKA (GPIO18)

SPISTEA (GPIO19)

I2C

SDAA (GPIO28)

SCLA (GPIO29)

CAN

CANRXA (GPIO30)

CANTXA (GPIO31)

8.1.11 Security

The devices support high levels of security to protect the user firmware from being reverse-engineered. The

security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One

code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature

prevents unauthorized users from examining the memory contents through the JTAG port, executing code from

external memory or trying to boot-load some undesirable software that would export the secure memory

contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value that matches

the value stored in the password locations within the Flash.

In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized

users from stepping through secure code. Any code or data access to CSM secure memory while the debug

probe is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code,

while maintaining the CSM protection against secure memory reads, the user must write the correct value into

the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password

locations within the flash. Dummy reads of all 128 bits of the password in the flash must still be performed. If the

lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to

match.

When initially debugging a device with the password locations in flash programmed (that is, secured), the CPU

will start running and may execute an instruction that performs an access to a protected ECSL area. If this

happens, the ECSL will trip and cause the debug probe connection to be broken.

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The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow a debug

probe to be connected without tripping security. These devices do not support a hardware wait-in-reset mode.

Note

•

When the code-security passwords are programmed, all addresses from 0x3F 7F80 to 0x3F 7FF5

cannot be used as program code or data. These locations must be programmed to 0x0000.

If the code security feature is not used, addresses 0x3F 7F80 to 0x3F 7FEF may be used for code

or data. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and should not contain program

code.

•

The 128-bit password (at 0x3F 7FF8 to 0x3F 7FFF) must not be programmed to zeros. Doing so

would permanently lock the device.

Note

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO

PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR

FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS

STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS

FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY

CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH

ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR

OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY

OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,

INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF

YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED

TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR

OTHER ECONOMIC LOSS.

8.1.12 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block

can support up to 96 peripheral interrupts. On the F2806x, 72 of the possible 96 interrupts are used by

peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines

(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that

can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. Eight

CPU clock cycles are needed to fetch the vector and save critical CPU registers. Hence the CPU can quickly

respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual

interrupt can be enabled or disabled within the PIE block.

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8.1.13 External Interrupts (XINT1 to XINT3)

The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for

negative, positive, or both negative and positive edge triggering and can also be enabled or disabled. These

interrupts also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is

detected. This counter can be used to accurately time-stamp the interrupt. There are no dedicated pins for the

external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins.

8.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL

The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal

attached to the on-chip oscillator circuit. A PLL is provided supporting up to 16 input-clock-scaling ratios. The

PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower

power operation is desired. Refer to Section 7, Specifications, for timing details. The PLL block can be set in

bypass mode. A second PLL (PLL2) feeds the HRCAP module.

8.1.15 Watchdog

Each device contains two watchdogs: CPU-watchdog that monitors the core and NMI-watchdog that is a missing

clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time

frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if

necessary. The NMI-watchdog engages only in case of a clock failure and can either generate an interrupt or a

device reset.

8.1.16 Peripheral Clocking

The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to

the CPU clock.

8.1.17 Low-power Modes

The devices are full static CMOS devices. Three low-power modes are provided:

IDLE:

Places CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that

must function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer

will wake the processor from IDLE mode.

STANDBY:

HALT:

Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt

event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the

interrupt event

This mode basically shuts down the device and places it in the lowest possible power-consumption mode. If the

internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep

these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin

oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as

the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU-

watchdog can wake the device from this mode.

The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put the

device into HALT or STANDBY.

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8.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)

The device segregates peripherals into four sections. The mapping of peripherals is as follows:

PF0:

PIE:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash Waitstate Registers

Flash:

Timers:

CSM:

ADC:

CPU-Timers 0, 1, 2 Registers

Code Security Module KEY Registers

ADC Result Registers

CLA:

Control Law Accelrator Registers and Message RAMs

GPIO MUX Configuration and Control Registers

Enhanced Control Area Network Configuration and Control Registers

System Control Registers

PF1:

PF2:

GPIO:

eCAN:

SYS:

SCI:

Serial Communications Interface (SCI) Control and RX/TX Registers

Serial Port Interface (SPI) Control and RX/TX Registers

ADC Status, Control, and Configuration Registers

Inter-Integrated Circuit Module and Registers

External Interrupt Registers

SPI:

ADC:

I2C:

XINT:

PF3:

McBSP:

ePWM:

eCAP:

eQEP:

Comparators:

USB:

Multichannel Buffered Serial Port Registers

Enhanced Pulse Width Modulator Module and Registers

Enhanced Capture Module and Registers

Enhanced Quadrature Encoder Pulse Module and Registers

Comparator Modules

Universal Serial Bus Module and Registers

8.1.19 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables

the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured

as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific

inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.

The GPIO signals can also be used to bring the device out of specific low-power modes.

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8.1.20 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The

timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The

counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches

zero, it is automatically reloaded with a 32-bit period value.

CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can

be connected to INT13 of the CPU. CPU-Timer 2 is reserved for SYS/BIOS. CPU-Timer 2 is connected to INT14

of the CPU. If SYS/BIOS is not being used, CPU-Timer 2 is available for general use.

CPU-Timer 2 can be clocked by any one of the following:

•

SYSCLKOUT (default)

Internal zero-pin oscillator 1 (INTOSC1)

Internal zero-pin oscillator 2 (INTSOC2)

External clock source

8.1.21 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:

ePWM:

The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-

band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins

support the HRPWM high-resolution duty and period features. The type 1 module found on 2806x devices

also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced

triggering including trip functions based on comparator outputs.

eCAP:

eQEP:

The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in

continuous/one-shot capture modes.

This peripheral can also be configured to generate an auxiliary PWM signal.

The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using

capture unit and high-speed measurement using a 32-bit unit timer. This peripheral has a watchdog timer to

detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals.

ADC:

The ADC block is a 12-bit converter. The ADC has up to 16 single-ended channels pinned out, depending on

the device. The ADC also contains two sample-and-hold units for simultaneous sampling.

Comparator:

HRCAP:

Each comparator block consists of one analog comparator along with an internal 10-bit reference for

supplying one input of the comparator.

The high-resolution capture peripheral operates in normal capture mode through a 16-bit counter clocked off

of the HCCAPCLK or in high-resolution capture mode by using built-in calibration logic in conjunction with a

TI-supplied calibration library.

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8.1.22 Serial Port Peripherals

The devices support the following serial communication peripherals:

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to

16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used

for communications between the MCU and external peripherals or another processor. Typical applications

include external I/O or peripheral expansion through devices such as shift registers, display drivers, and

ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI contains

a 4-level receive and transmit FIFO for reducing interrupt servicing overhead.

SCI:

I2C:

The serial communications interface is a 2-wire asynchronous serial port, commonly known as UART. The SCI

contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead.

The inter-integrated circuit (I2C) module provides an interface between an MCU and other devices compliant

with Philips Semiconductors Inter-IC bus ( I2C-bus^®) specification version 2.1 and connected by way of an

I²C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to or from

the MCU through the I2C module. The I2C contains a 4-level receive-and-transmit FIFO for reducing interrupt

servicing overhead.

eCAN:

This is the enhanced version of the CAN peripheral. The eCAN supports 32 mailboxes, time-stamping of

messages, and is compliant with ISO 11898-1 (CAN 2.0B).

McBSP:

The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality codecs for modem

applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are

supported by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module

can be configured as an SPI as required.

USB:

The USB peripheral, which conforms to the USB 2.0 specification, may be used as either a full-speed (12-

Mbps) device controller, or a full-speed (12-Mbps) or low-speed (1.5-Mbps) host controller. The controller

supports a total of six user-configurable endpoints—all of which can be accessed through DMA, in addition to

a dedicated control endpoint for endpoint zero. All packets transmitted or received are buffered in 4KB of

dedicated endpoint memory. The USB peripheral supports all three transfer types: Control, Interrupt, and Bulk.

Because of the complexity of the USB peripheral and the associated protocol overhead, a full software library

with application examples is provided within C2000Ware.

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8.2 Memory Maps

In Figure 8-1 through Figure 8-8, the following apply:

•

Memory blocks are not to scale.

Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are

restricted to data memory only. A user program cannot access these memory maps in program space.

Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Locations 0x3D 7C80–0x3D 7CC0 contain the internal oscillator and ADC calibration routines. These

locations are not programmable by the user.

•

All devices with USB have the USB control registers mapped from 0x4000 to 0x4FFF and 2K ×16 RAM from

0x40000 to 0x40800. When the clock to the USB module is enabled, this RAM is connected to the USB

controller and acts as the FIFO RAM. When the clock to the USB module is disabled, this RAM is remapped

to the CPU-accessible address space and can be used as general-purpose RAM.

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Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

Peripheral Frame 0

CLA Registers

0x00 1480

0x00 1500

0x00 1580

0x00 2000

0x00 4000

CLA-to-CPU Message RAM

CPU-to-CLA Message RAM

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

0x01 0000

0x01 2000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM2)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Program RAM)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

L7 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 2)

L8 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 3)

0x01 4000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3D 8000

FLASH

(128K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

(B)(C)

FAST, SpinTAC, and IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

B. FAST^™and SpinTAC^™libraries exist only on F2806xM and F2806xF devices.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

C. The ROM contents from 0x3F 8000–0x3F F3AF differ between F2806x parts and F2806xM/F2806xF parts. See the respective memory

map figures in the Boot ROM chapter of the TMS320x2806x Technical Reference Manual .

Figure 8-1. 28069, 28069F, 28069M Memory Map

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

0x00 4000

Peripheral Frame 0

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

0x01 0000

0x01 2000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

L7 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 2)

L8 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 3)

0x01 4000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3D 8000

FLASH

(128K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

(B)(C)

FAST, SpinTAC, and IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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B. FAST^™and SpinTAC^™libraries exist only on F2806xM and F2806xF devices.

C. The ROM contents from 0x3F 8000–0x3F F3AF differ between F2806x parts and F2806xM/F2806xF parts. See the respective memory

map figures in the Boot ROM chapter of the TMS320x2806x Technical Reference Manual .

Figure 8-2. 28068F, 28068M Memory Map

56

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

0x00 4000

Peripheral Frame 0

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

0x01 0000

0x01 2000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

L7 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 2)

L8 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 3)

0x01 4000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3D 8000

FLASH

(128K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

Figure 8-3. 28067 Memory Map

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

0x00 4000

Peripheral Frame 0

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

0x01 0000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3D 8000

FLASH

(128K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

Figure 8-4. 28066 Memory Map

58

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

Peripheral Frame 0

CLA Registers

0x00 1480

0x00 1500

0x00 1580

0x00 2000

0x00 4000

CLA-to-CPU Message RAM

CPU-to-CLA Message RAM

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

0x01 0000

0x01 2000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM2)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 0)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Data RAM 1)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL, CLA Program RAM)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

L7 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 2)

L8 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 3)

0x01 4000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3E 8000

FLASH

(64K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

Figure 8-5. 28065 Memory Map

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

0x00 4000

Peripheral Frame 0

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL)

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

0x01 0000

0x01 2000

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

L7 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 2)

L8 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 3)

0x01 4000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3E 8000

FLASH

(64K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

Figure 8-6. 28064 Memory Map

60

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

0x00 4000

Peripheral Frame 0

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

0x00 E000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

L6 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 1)

0x01 0000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3E 8000

FLASH

(64K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

Figure 8-7. 28063 Memory Map

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Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

0x00 4000

Peripheral Frame 0

Reserved

(A)

USB Control Registers

0x00 5000

Peripheral Frame 3

(4K ´ 16, Protected)

DMA-Accessible

Reserved

0x00 6000

0x00 7000

Peripheral Frame 1

(4K ´ 16, Protected)

Peripheral Frame 2

(4K ´ 16, Protected)

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

0x00 A000

0x00 C000

L0 DPSARAM (2K ´ 16)

(0-Wait, Secure Zone + ECSL)

L1 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L2 DPSARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL)

L3 DPSARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL)

L4 SARAM (8K ´ 16)

(0-Wait, Secure Zone + ECSL)

L5 DPSARAM (8K ´ 16)

(0-Wait, DMA RAM 0)

0x00 E000

0x3D 7800

0x3D 7BFA

0x3D 7C80

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

Calibration Data

Get_mode function

Reserved

0x3D 7CC0

0x3D 7CD0

0x3D 7E80

0x3D 7E82

PARTID

Calibration Data

Reserved

0x3D 7EB0

0x3E 8000

FLASH

(64K ´ 16, 8 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

(B)(C)

FAST, SpinTAC, and IQmath Libraries

(16K ´ 16, 0-Wait State)

0x3F F3B0

0x3F FFC0

Boot ROM (16K ´ 16, 0-Wait State)

CPU Vector Table (32 Vectors, Enabled if VMAP = 1)

A. On non-USB devices, 0x00 4000–0x00 4FFF is Reserved.

B. FAST^™and SpinTAC^™libraries exist only on F2806xM and F2806xF devices.

C. The ROM contents from 0x3F 8000–0x3F F3AF differ between F2806x parts and F2806xM/F2806xF parts. See the respective memory

map figures in the Boot ROM chapter of the TMS320x2806x Technical Reference Manual .

Figure 8-8. 28062, 28062F Memory Map

62

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table 8-3. Addresses of Flash Sectors in 28069, 28069F, 28069M,

28068F, 28068M, F28067, F28066

ADDRESS RANGE

0x3D 8000 to 0x3D BFFF

0x3D C000 to 0x3D FFFF

0x3E 0000 to 0x3E 3FFF

0x3E 4000 to 0x3E 7FFF

0x3E 8000 to 0x3E BFFF

0x3E C000 to 0x3E FFFF

0x3F 0000 to 0x3F 3FFF

0x3F 4000 to 0x3F 7FF5

PROGRAM AND DATA SPACE

Sector H (16K × 16)

Sector G (16K × 16)

Sector F (16K × 16)

Sector E (16K × 16)

Sector D (16K × 16)

Sector C (16K × 16)

Sector B (16K × 16)

Sector A (16K × 16)

Boot-to-Flash Entry Point

(program branch instruction here)

0x3F 7FF6 to 0x3F 7FF7

0x3F 7FF8 to 0x3F 7FFF

Security Password (128-Bit)

(Do not program to all zeros)

Table 8-4. Addresses of Flash Sectors in F28065, F28064, F28063, 28062,

28062F

ADDRESS RANGE

0x3E 8000 to 0x3E 9FFF

0x3E A000 to 0x3E BFFF

0x3E C000 to 0x3E DFFF

0x3E E000 to 0x3E FFFF

0x3F 0000 to 0x3F 1FFF

0x3F 2000 to 0x3F 3FFF

0x3F 4000 to 0x3F 5FFF

0x3F 6000 to 0x3F 7FF5

PROGRAM AND DATA SPACE

Sector H (8K × 16)

Sector G (8K × 16)

Sector F (8K × 16)

Sector E (8K × 16)

Sector D (8K × 16)

Sector C (8K × 16)

Sector B (8K × 16)

Sector A (8K × 16)

Boot-to-Flash Entry Point

(program branch instruction here)

0x3F 7FF6 to 0x3F 7FF7

0x3F 7FF8 to 0x3F 7FFF

Security Password (128-Bit)

(Do not program to all zeros)

Note

Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and should not contain program code.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read

peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written.

Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in

reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where

the user expected the write to occur first (as written). The CPU supports a block protection mode where a region

of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align

the operations). This mode is programmable and by default, it protects the selected zones.

The wait states for the various spaces in the memory map area are listed in Table 8-5.

Table 8-5. Wait States

AREA

WAIT STATES (CPU)

COMMENTS

M0 and M1 SARAMs

Peripheral Frame 0

Peripheral Frame 1

0-wait

Fixed

0-wait

0-wait (writes)

2-wait (reads)

Cycles can be extended by peripheral-generated ready.

Back-to-back write operations to Peripheral Frame 1 registers will incur

a 1-cycle stall (1-cycle delay).

Peripheral Frame 2

Peripheral Frame 3

0-wait (writes)

2-wait (reads)

0-wait (writes)

Fixed. Cycles cannot be extended by the peripheral.

Assumes no conflict between CPU and CLA/DMA cycles. The wait

states can be extended by peripheral-generated ready.

2-wait (reads)

0-wait data and program

Programmable

L0–L8 SARAM

OTP

Assumes no CPU conflicts

Programmed through the Flash registers.

1-wait is minimum number of wait states allowed.

Programmed through the Flash registers.

1-wait minimum

FLASH

Programmable

0-wait Paged min

1-wait Random min

Random ≥ Paged

FLASH Password

Boot-ROM

16-wait fixed

0-wait

Wait states of password locations are fixed.

64

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.3 Register Maps

The devices contain four peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0:

Peripheral Frame 1:

Peripheral Frame 2:

Peripheral Frame 3:

These are peripherals that are mapped directly to the CPU memory bus. See Table 8-6.

These are peripherals that are mapped to the 32-bit peripheral bus. See Table 8-7.

These are peripherals that are mapped to the 16-bit peripheral bus. See Table 8-8.

McBSP registers are mapped to this. See Table 8-9.

Table 8-6. Peripheral Frame 0 Registers

NAME⁽¹⁾

Device Emulation registers

System Power Control registers

FLASH registers⁽³⁾

ADDRESS RANGE

0x00 0880 to 0x00 0984

0x00 0985 to 0x00 0987

0x00 0A80 to 0x00 0ADF

0x00 0AE0 to 0x00 0AEF

0x00 0B00 to 0x00 0B0F

SIZE (×16)

EALLOW PROTECTED⁽²⁾

261

3

Yes

No

96

16

Code Security Module registers

ADC registers (0 wait read only)

CPU-TIMER0, CPU-TIMER1, CPU-TIMER2

registers

0x00 0C00 to 0x00 0C3F

64

No

PIE registers

0x00 0CE0 to 0x00 0CFF

0x00 0D00 to 0x00 0DFF

0x00 1000 to 0x00 11FF

0x00 1400 to 0x00 147F

0x00 1480 to 0x00 14FF

0x00 1500 to 0x00 157F

32

No

Yes

NA

PIE Vector Table

256

512

128

DMA registers

CLA registers

CLA to CPU Message RAM (CPU writes ignored)

CPU to CLA Message RAM (CLA writes ignored)

(1) Registers in Frame 0 support 16-bit and 32-bit accesses.

(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Code Security Module (CSM).

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Table 8-7. Peripheral Frame 1 Registers

NAME

ADDRESS RANGE

0x00 6000 to 0x00 61FF

0x00 6AC0 to 0x00 6ADF

0x00 6AE0 to 0x00 6AFF

0x00 6C80 to 0x00 6C9F

0x00 6CA0 to 0x00 6CBF

0x00 6F80 to 0x00 6FFF

SIZE (×16)

EALLOW PROTECTED

(1)

eCAN-A registers

HRCAP1 registers

HRCAP2 registers

HRCAP3 registers

HRCAP4 registers

GPIO registers

512

32

128

(1) Some registers are EALLOW protected. See the module reference guide for more information.

Table 8-8. Peripheral Frame 2 Registers

NAME

System Control registers

ADDRESS RANGE

0x00 7010 to 0x00 702F

0x00 7040 to 0x00 704F

0x00 7050 to 0x00 705F

0x00 7060 to 0x00 706F

0x00 7070 to 0x00 707F

0x00 7100 to 0x00 717F

0x00 7740 to 0x00 774F

0x00 7750 to 0x00 775F

0x00 7900 to 0x00 793F

SIZE (×16)

EALLOW PROTECTED

32

16

128

16

64

Yes

No

SPI-A registers

SCI-A registers

No

NMI Watchdog Interrupt registers

External Interrupt registers

ADC registers

Yes

(1)

SPI-B registers

No

SCI-B registers

No

(1)

I2C-A registers

(1) Some registers are EALLOW protected. See the module reference guide for more information.

Table 8-9. Peripheral Frame 3 Registers

NAME

ADDRESS RANGE

0x00 4000 to 0x00 4FFF

0x00 5000 to 0x00 503F

0x00 6400 to 0x00 641F

0x00 6420 to 0x00 643F

0x00 6440 to 0x00 645F

0x00 6800 to 0x00 683F

0x00 6840 to 0x00 687F

0x00 6880 to 0x00 68BF

0x00 68C0 to 0x00 68FF

0x00 6900 to 0x00 693F

0x00 6940 to 0x00 697F

0x00 6980 to 0x00 69BF

0x00 69C0 to 0x00 69FF

0x00 6A00 to 0x00 6A1F

0x00 6A20 to 0x00 6A3F

0x00 6A40 to 0x00 6A57

0x00 6B00 to 0x00 6B3F

0x00 6B40 to 0x00 6B7F

SIZE (×16)

4096

64

EALLOW PROTECTED

USB0 registers

No

McBSP-A registers

No

(1)

Comparator 1 registers

Comparator 2 registers

Comparator 3 registers

ePWM1 + HRPWM1 registers

ePWM2 + HRPWM2 registers

ePWM3 + HRPWM3 registers

ePWM4 + HRPWM4 registers

ePWM5 + HRPWM5 registers

ePWM6 + HRPWM6 registers

ePWM7 + HRPWM7 registers

ePWM8 + HRPWM8 registers

eCAP1 registers

32

(1)

32

64

32

No

eCAP2 registers

32

eCAP3 registers

32

No

(1)

eQEP1 registers

64

(1)

eQEP2 registers

64

(1) Some registers are EALLOW protected. See the module reference guide for more information.

66

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical device

signals. The registers are defined in Table 8-10.

Table 8-10. Device Emulation Registers

EALLOW

PROTECTED

NAME

ADDRESS RANGE

SIZE (×16)

DESCRIPTION

Device Configuration Register

Part ID Register

0x0880–

0x0881

DEVICECNF

PARTID

2

1

Yes

0x3D 7E80

TMS320F28069PZP/PZ

TMS320F28069UPZP/PZ

TMS320F28069MPZP/PZ

TMS320F28069FPZP/PZ

TMS320F28069PFP/PN

TMS320F28069UPFP/PN

TMS320F28069MPFP/PN

TMS320F28069FPFP/PN

TMS320F28068UPZP/PZ

TMS320F28068MPZP/PZ

TMS320F28068FPZP/PZ

TMS320F28068UPFP/PN

TMS320F28068MPFP/PN

TMS320F28068FPFP/PN

TMS320F28067PZP/PZ

TMS320F28067UPZP/PZ

TMS320F28067PFP/PN

TMS320F28067UPFP/PN

TMS320F28066PZP/PZ

TMS320F28066UPZP/PZ

TMS320F28066PFP/PN

TMS320F28066UPFP/PN

TMS320F28065PZP/PZ

TMS320F28065UPZP/PZ

TMS320F28065PFP/PN

TMS320F28065UPFP/PN

TMS320F28064PZP/PZ

TMS320F28064UPZP/PZ

TMS320F28064PFP/PN

TMS320F28064UPFP/PN

TMS320F28063PZP/PZ

TMS320F28063UPZP/PZ

TMS320F28063PFP/PN

TMS320F28063UPFP/PN

TMS320F28062PZP/PZ

TMS320F28062UPZP/PZ

TMS320F28062FPZP/PZ

TMS320F28062PFP/PN

TMS320F28062UPFP/PN

TMS320F28062FPFP/PN

0x009E

0x009F

0x009E

0x009C

0x009D

0x009C

0x008F

0x008E

0x008D

0x008C

0x008A

0x008B

0x0088

0x0089

0x0086

0x0087

0x0084

0x0085

0x007E

0x007F

0x007C

0x007D

0x006E

0x006F

0x006C

0x006D

0x006A

0x006B

0x0068

0x0069

0x0066

0x0067

0x0066

0x0064

0x0065

0x0064

No

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Table 8-10. Device Emulation Registers (continued)

EALLOW

PROTECTED

NAME

CLASSID

ADDRESS RANGE

SIZE (×16)

DESCRIPTION

0x0882

1

Class ID Register

TMS320F28069

0x009F

0x008F

0x007F

0x006F

TMS320F28069U

TMS320F28069M

TMS320F28069F

TMS320F28068U

TMS320F28068M

TMS320F28068F

TMS320F28067

TMS320F28067U

TMS320F28066

No

TMS320F28066U

TMS320F28065

TMS320F28065U

TMS320F28064

TMS320F28064U

TMS320F28063

TMS320F28063U

TMS320F28062

TMS320F28062U

TMS320F28062F

0x0000 - Silicon Rev. 0 - TMX

0x0001 - Silicon Rev. A - TMS

0x0002 - Silicon Rev. B - TMS

REVID

0x0883

1

Revision ID Register

No

68

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.5 VREG, BOR, POR

Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip VREG to

generate the V_DDvoltage from the V_DDIOsupply. This eliminates the cost and space of a second external

regulator on an application board. Additionally, internal power-on reset (POR) and brownout reset (BOR) circuits

monitor both the V_DDand V_DDIOrails during power-up and run mode.

8.5.1 On-chip VREG

A linear regulator generates the core voltage (V_DD) from the V_DDIOsupply. Therefore, although capacitors are

required on each V_DDpin to stabilize the generated voltage, power need not be supplied to these pins to operate

the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the

application.

8.5.1.1 Using the On-chip VREG

To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating

voltage should be supplied to the V_DDIOand V_DDApins. In this case, the V_DDvoltage needed by the core logic

will be generated by the VREG. Each V_DDpin requires on the order of 1.2 μF (minimum) capacitance for proper

regulation of the VREG. These capacitors should be located as close as possible to the V_DDpins. Driving an

external load with the internal VREG is not supported.

8.5.1.2 Disabling the On-chip VREG

To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the V_DD

pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high.

8.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit

Two on-chip supervisory circuits, the power-on reset (POR) and the brownout reset (BOR) remove the burden of

monitoring the V_DDand V_DDIOsupply rails from the application board. The purpose of the POR is to create a

clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point

than the BOR, which watches for dips in the V_DDor V_DDIOrail during device operation. The POR function is

present on both V_DDand V_DDIOrails at all times. After initial device power-up, the BOR function is present on

V_DDIOat all times, and on V_DDwhen the internal VREG is enabled ( VREGENZ pin is tied low). Both functions tie

the XRS pin low when one of the voltages is below their respective trip point. V_DDBOR and overvoltage trip

points are outside of the recommended operating voltages. Proper device operation cannot be ensured. If

overvoltage or undervoltage conditions affecting the system is a concern for an application, an external voltage

supervisor should be added. Figure 8-9 shows the VREG, POR, and BOR. To disable both the V_DDand V_DDIO

BOR functions, a bit is provided in the BORCFG register. For details, see the Systems Control and Interrupts

chapter of the TMS320x2806x Technical Reference Manual .

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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In

I/O Pin

Out

(Force Hi-Z When High)

DIR (0 = Input, 1 = Output)

SYSRS

Internal

Weak PU

SYSCLKOUT

Sync

Deglitch

Filter

RS

WDRST

C28

Core

MCLKRS

JTAG

TCK

PLL

Detect

Logic

XRS

+

Clocking

Logic

VREGHALT

WDRST^(A)

PBRS^(B)

POR/BOR

On-Chip

Generating

Voltage

VREGENZ

Module

Regulator

(VREG)

A. WDRST is the reset signal from the CPU-watchdog.

B. PBRS is the reset signal from the POR/BOR module.

Figure 8-9. VREG + POR + BOR + Reset Signal Connectivity

70

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.6 System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low-power modes.

Table 8-11. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME

ADDRESS

0x00 0985

0x00 7010

0x00 7011

0x00 7012

0x00 7013

0x00 7014

0x00 7016

0x00 7019

0x00 701B

0x00 701C

0x00 701D

0x00 701E

0x00 7020

0x00 7021

0x00 7022

0x00 7023

0x00 7025

0x00 7029

0x00 702A

0x00 7030

0x00 7032

0x00 7034

0x00 7036

0x00 703A

SIZE (×16)

DESCRIPTION⁽¹⁾

BORCFG

XCLK

1

BOR Configuration Register

XCLKOUT Control

PLLSTS

CLKCTL

PLL Status Register

Clock Control Register

PLLLOCKPRD

INTOSC1TRIM

INTOSC2TRIM

PCLKCR2

LOSPCP

PLL Lock Period

Internal Oscillator 1 Trim Register

Internal Oscillator 2 Trim Register

Peripheral Clock Control Register 2

Low-Speed Peripheral Clock Prescaler Register

Peripheral Clock Control Register 0

Peripheral Clock Control Register 1

Low-Power Mode Control Register 0

Peripheral Clock Control Register 3

PLL Control Register

PCLKCR0

PCLKCR1

LPMCR0

PCLKCR3

PLLCR

SCSR

System Control and Status Register

Watchdog Counter Register

Watchdog Reset Key Register

Watchdog Control Register

WDCNTR

WDKEY

WDCR

JTAGDEBUG

PLL2CTL

JTAG Port Debug Register

PLL2 Configuration Register

PLL2 Multiplier Register

PLL2MULT

PLL2STS

PLL2 Lock Status Register

SYSCLK2CNTR

EPWMCFG

SYSCLK2 Clock Counter Register

ePWM DMA/CLA Configuration Register

(1) All registers in this table are EALLOW protected.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Figure 8-10 shows the various clock domains that are discussed. Figure 8-11 shows the various clock sources

(both internal and external) that can provide a clock for device operation.

SYSCLKOUT

PCLKCR0/1/2/3

(System Ctrl Regs)

LOSPCP

(System Ctrl Regs)

PLL2

C28x Core

CLKIN

LSPCLK

Clock Enables

SPI-A, SPI-B, SCI-A, SCI-B

Clock Enables

USB

Peripheral

Registers

I/O

PF2

Peripheral

Registers

PF3

LOSPCP

(System Ctrl Regs)

Clock Enables

LSPCLK

Peripheral

Registers

I/O

McBSP

Clock Enables

eCAN-A

PF3

PF1

PF3

PF2

PF1

/2

Peripheral

Registers

GPIO

Mux

Clock Enables

Peripheral

Registers

eCAP1, eCAP2, eCAP3

eQEP1, eQEP2

Clock Enables

ePWM1, ePWM2,

ePWM3, ePWM4, ePWM5,

ePWM6, ePWM7, ePWM8

Peripheral

Registers

Clock Enables

Peripheral

Registers

I2C-A

I/O

Clock Enables

Peripheral

Registers

HRCAP1, HRCAP2,

HRCAP3, HRCAP4

Clock Enables

12-Bit ADC

ADC

Registers

PF2

PF0

16 Ch

Analog

GPIO

Mux

Clock Enables

COMP

Registers

COMP1, COMP2, COMP3

6

PF3

A. CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as

SYSCLKOUT).

Figure 8-10. Clock and Reset Domains

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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CLKCTL[WDCLKSRCSEL]

Internal

OSC 1

(10 MHz)

0

OSC1CLK

INTOSC1TRIM Reg^(A)

OSCCLKSRC1

WDCLK

CPU-Watchdog

(OSC1CLK on XRS reset)

OSCE

1

CLKCTL[INTOSC1OFF]

1 = Turn OSC Off

CLKCTL[OSCCLKSRCSEL]

CLKCTL[INTOSC1HALT]

1 = Ignore HALT

WAKEOSC

OSC2CLK

0

1

Internal

OSC 2

(10 MHz)

INTOSC2TRIM Reg^(A)

OSCCLK

PLL

Missing-Clock-Detect Circuit^(B)

SYSCLKOUT

(OSC1CLK on XRS reset)

OSCE

CLKCTL[TRM2CLKPRESCALE]

CLKCTL[TMR2CLKSRCSEL]

1 = Turn OSC Off

10

11

CLKCTL[INTOSC2OFF]

Prescale

/1, /2, /4,

/8, /16

SYNC

Edge

Detect

01, 10, 11

CPUTMR2CLK

1 = Ignore HALT

01

1

0

00

CLKCTL[INTOSC2HALT]

SYSCLKOUT

OSCCLKSRC2

CLKCTL[OSCCLKSRC2SEL]

0 = GPIO38

1 = GPIO19

XCLK[XCLKINSEL]

PLL2CTL.PLL2CLKSRCSEL

PLL2CTL.PLL2EN

CLKCTL[XCLKINOFF]

0

1

0

DEVICECNF[SYSCLK2DIV2DIS]

PLL2

GPIO19

or

XCLKIN

0

/2

GPIO38

XCLKIN

SYSCLK2 to USB

HRCAP

1

X1

X2

PLL2CLK

EXTCLK

(Crystal)

OSC

XTAL

WAKEOSC

(Oscillators enabled when this signal is high)

0 = OSC on (default on reset)

1 = Turn OSC off

CLKCTL[XTALOSCOFF]

A. Register loaded from TI OTP-based calibration function.

B. See Section 8.6.5 for details on missing clock detection.

Figure 8-11. Clock Tree

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.6.1 Internal Zero Pin Oscillators

The F2806x devices contain two independent internal zero pin oscillators. By default both oscillators are turned

on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused

oscillators may be powered down by the user. The center frequency of these oscillators is determined by their

respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See

Section 8.9 for more information on these oscillators.

8.6.2 Crystal Oscillator Option

The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level signals

applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be connected to

the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it should be used with

X2 and a crystal.

The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table

8-12. Furthermore, ESR range = 30 to 150 Ω.

Table 8-12. Typical Specifications for External Quartz Crystal ⁽¹⁾

FREQUENCY (MHz)

R_d(Ω)

2200

470

0

C_L1(pF)

C_L2(pF)

5

18

10

15

20

15

0

12

(1) C_shuntshould be less than or equal to 5 pF.

XCLKIN/GPIO19/38

X1

X2

R_d

Turn off

XCLKIN path

in CLKCTL

register

Crystal

C_L1

C_L2

Figure 8-12. Using the On-chip Crystal Oscillator

Note

1. C_L1and C_L2are the total capacitance of the circuit board and components excluding the IC and

crystal. The value is usually approximately twice the value of the load capacitance of the crystal.

2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers.

3. TI recommends that customers have the resonator/crystal vendor characterize the operation of

their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to

tune the tank circuit. The vendor can also advise the customer regarding the proper tank

component values that will produce proper start-up and stability over the entire operating range.

XCLKIN/GPIO19/38

X1

X2

NC

External Clock Signal

(Toggling 0−V

)

DDIO

Figure 8-13. Using a 3.3-V External Oscillator

74

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.6.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals

for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to

select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.

The watchdog module can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms.

The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL

(VCOCLK) is at least 50 MHz.

Table 8-13. PLL Settings

SYSCLKOUT (CLKIN)

PLLCR[DIV] VALUE^{(2) (3)}

PLLSTS[DIVSEL] = 0 or 1⁽¹⁾

OSCCLK/4 (Default)⁽²⁾

(OSCCLK * 1)/4

(OSCCLK * 2)/4

(OSCCLK * 3)/4

(OSCCLK * 4)/4

(OSCCLK * 5)/4

(OSCCLK * 6)/4

(OSCCLK * 7)/4

(OSCCLK * 8)/4

(OSCCLK * 9)/4

(OSCCLK * 10)/4

(OSCCLK * 11)/4

(OSCCLK * 12)/4

(OSCCLK * 13)/4

(OSCCLK * 14)/4

(OSCCLK * 15)/4

(OSCCLK * 16)/4

(OSCCLK * 17)/4

(OSCCLK * 18)/4

PLLSTS[DIVSEL] = 2

OSCCLK/2

PLLSTS[DIVSEL] = 3

OSCCLK

00000 (PLL bypass)

00001

00010

00011

(OSCCLK * 1)/2

(OSCCLK * 2)/2

(OSCCLK * 3)/2

(OSCCLK * 4)/2

(OSCCLK * 5)/2

(OSCCLK * 6)/2

(OSCCLK * 7)/2

(OSCCLK * 8)/2

(OSCCLK * 9)/2

(OSCCLK * 10)/2

(OSCCLK * 11)/2

(OSCCLK * 12)/2

(OSCCLK * 13)/2

(OSCCLK * 14)/2

(OSCCLK * 15)/2

(OSCCLK * 16)/2

(OSCCLK * 17)/2

(OSCCLK * 18)/2

(OSCCLK * 1)/1

(OSCCLK * 2)/1

(OSCCLK * 3)/1

(OSCCLK * 4)/1

(OSCCLK * 5)/1

(OSCCLK * 6)/1

(OSCCLK * 7)/1

(OSCCLK * 8)/1

(OSCCLK * 9)/1

(OSCCLK * 10)/1

(OSCCLK * 11)/1

(OSCCLK * 12)/1

(OSCCLK * 13)/1

(OSCCLK * 14)/1

(OSCCLK * 15)/1

(OSCCLK * 16)/1

(OSCCLK * 17)/1

(OSCCLK * 18)/1

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the

PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic has no effect.

(3) This register is EALLOW protected. See the Systems Control and Interrupts chapter of the TMS320x2806x Technical Reference

Manual for more information.

Table 8-14. CLKIN Divide Options

PLLSTS [DIVSEL]

CLKIN DIVIDE

0

1

2

3

/4

/2

/1

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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The PLL-based clock module provides four modes of operation:

•

INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock

for the Watchdog block, core and CPU-Timer 2

•

INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock

for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen

for the Watchdog block, core and CPU-Timer 2.

•

Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/

resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2

pins. Some devices may not have the X1/X2 pins. See Section 6.2.1 for details.

External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be

bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. The

XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or

GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input

(forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable

at boot time.

Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock

source must be disabled (using the CLKCTL register) before switching clocks.

Table 8-15. Possible PLL Configuration Modes

PLL MODE

REMARKS

PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT

PLL Off

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The

PLL block is disabled in this mode. This can be useful to reduce system

noise and for low-power operation. The PLLCR register must first be set

to 0x0000 (PLL Bypass) before entering this mode. The CPU clock

(CLKIN) is derived directly from the input clock on either X1/X2, X1 or

XCLKIN.

0, 1

2

OSCCLK/4

OSCCLK/2

OSCCLK/1

3

PLL Bypass PLL Bypass is the default PLL configuration upon power-up or after an

external reset ( XRS). This mode is selected when the PLLCR register is

set to 0x0000 or while the PLL locks to a new frequency after the PLLCR

register has been modified. In this mode, the PLL is bypassed but the

PLL is not turned off.

0, 1

2

OSCCLK/4

OSCCLK/2

OSCCLK/1

3

PLL Enable Achieved by writing a non-zero value n into the PLLCR register. Upon

writing to the PLLCR the device will switch to PLL Bypass mode until the

PLL locks.

0, 1

2

OSCCLK * n/4

OSCCLK * n/2

OSCCLK * n/1

3

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.6.4 USB and HRCAP PLL Module (PLL2)

In addition to the main system PLL, these devices also contain a second PLL (PLL2) which can be used to clock

the USB and HRCAP peripherals. The PLL supports multipliers of 1 to 15 and has a fixed divide-by-two on its

output.

PLL2 may be clocked from the following three sources by modifying the PLL2CLKSRCSEL bits appropriately in

the PLL2CTL register:

•

INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1 and provides a 10-MHz

clock. If used as a clock source for HRCAP, the oscillator compensation routine should be called frequently.

Because of accuracy requirements, INTOSC1 cannot be used as a clock source for the USB.

Crystal/Resonator Operation: The (crystal) oscillator enables the use of an external crystal or resonator

attached to the device to provide the time base. The crystal or resonator is connected to the X1/X2 pins.

External Clock Source Operation: This mode allows the reference clock to be derived from an external single-

ended clock source connected to either GPIO19 or GPIO38. The XCLKINSEL bit in the XCLK register should

be set appropriately to enable the selected GPIO to drive XCLKIN.

•

Note

For proper operation of the USB module, PLL2 should be configured to generate a 120-MHz clock.

This will be divided by two to yield the desired 60 MHz for the USB peripheral.

HRCAP supports a maximum clock input frequency of 120 MHz.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.6.5 Loss of Input Clock (NMI Watchdog Function)

The 2806x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the

on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and

PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This

limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz.

When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.

Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or

the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status

(MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and

initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a

shut-down procedure for the system.

If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a

preprogrammed time interval. Figure 8-14 shows the interrupt mechanisms involved.

NMIFLG[NMINT]

NMIFLGCLR[NMINT]

Clear

Latch

Set

Clear

XRS

Generate

Interrupt

Pulse

When

Input = 1

NMIFLG[CLOCKFAIL]

Clear

Latch

1

0

NMIFLGCLR[CLOCKFAIL]

CLOCKFAIL

NMINT

SYNC?

Set

Clear

SYSCLKOUT

NMICFG[CLOCKFAIL]

NMIFLGFRC[CLOCKFAIL]

XRS

SYSCLKOUT

SYSRS

NMIWDPRD[15:0]

NMIWDCNT[15:0]

See System

Control Section

NMI Watchdog

NMIRS

Figure 8-14. NMI-Watchdog

8.6.6 CPU Watchdog Module

The CPU watchdog module on the 2806x device is similar to the one used on the 281x/280x/283xx devices. This

module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up

counter has reached its maximum value. To prevent this, the user must disable the counter or the software must

periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter.

Figure 8-15 shows the various functional blocks within the watchdog module.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog

reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops

decrementing (that is, the watchdog counter does not change with the limp-mode clock).

Note

The CPU-watchdog is different from the NMI watchdog. The CPU-watchdog is the legacy watchdog

that is present in all 28x devices.

Note

Applications in which the correct CPU operating frequency is absolutely critical should implement a

mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an

R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully

charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from

getting fully charged. Such a circuit would also help in detecting failure of the flash memory.

WDCR (WDPS[2:0])

WDCR (WDDIS)

WDCNTR(7:0)

WDCLK

8-Bit

Watchdog

Counter

CLR

Watchdog

Prescaler

/512

SCSR(WDOVERRIDE)

Clear Counter

Internal

Pullup

WDKEY(7:0)

WDRST

WDINT

Generate

Watchdog

55 + AA

Output Pulse

(512 OSCCLKs)

Good Key

Key Detector

XRS

Bad

WDCHK

Key

Core-reset

SCSR (WDENINT)

WDCR (WDCHK[2:0])

1

0

1

(A)

WDRST

A. The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 8-15. CPU Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is

the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can

wake the device from STANDBY (if enabled). See Section 8.7 for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of

IDLE mode.

In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8.7 Low-power Modes Block

Table 8-16 summarizes the various modes.

Table 8-16. Low-power Modes

MODE

LPMCR0(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT⁽¹⁾

XRS, CPU-watchdog interrupt, any

enabled interrupt

IDLE

00

On

XRS, CPU-watchdog interrupt, GPIO

Port A signal, debugger⁽²⁾

STANDBY

HALT⁽³⁾

01

1X

Off

(CPU-watchdog still running)

Off

(on-chip crystal oscillator and PLL

turned off, zero-pin oscillator and

CPU-watchdog state dependent

on user code.)

XRS, GPIO Port A signal, debugger⁽²⁾

CPU-watchdog

,

(1) The EXIT column lists which signals or under what conditions the low-power mode is exited. A low signal, on any of the signals, exits

the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-

power mode will not be exited and the device will go back into the indicated low-power mode.

(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(3) The WDCLK must be active for the device to go into HALT mode.

The various low-power modes operate as follows:

IDLE Mode:

This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block

performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must

select which signals will wake the device in the GPIOLPMSEL register. The selected signals are also

qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the

LPMCR0 register.

HALT Mode:

CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT

mode. The user selects the signal in the GPIOLPMSEL register.

Note

The low-power modes do not affect the state of the output pins (PWM pins included). They will be in

whatever state the code left them in when the IDLE instruction was executed. See the Systems

Control and Interrupts chapter of the TMS320x2806x Technical Reference Manual for more details.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.8 Interrupts

Figure 8-16 shows how the various interrupt sources are multiplexed.

Peripherals

(SPI, SCI, I²C, eCAN, eCAP, eQEP,

HRCAP, CLA)

Peripherals

(USB, McBSP, ePWM, ADC)

clear

DMA

C28x

Core

WDINT

Watchdog

WAKEINT

Sync

LPMINT

Low-Power Modes

SYSCLKOUT

DMA

M

U

X

XINT1

Interrupt Control

XINT1CR[15:0]

XINT1CTR[15:0]

INT1

to

INT12

GPIOXINT1SEL[4:0]

XINT2SOC

DMA

ADC

M

U

X

XINT2

Interrupt Control

XINT2CR[15:0]

XINT2CTR[15:0]

GPIOXINT2SEL[4:0]

GPIO0.int

DMA

M

XINT3

U

GPIO

MUX

Interrupt Control

XINT3CR[15:0]

XINT3CTR[15:0]

X

GPIO31.int

GPIOXINT3SEL[4:0]

TINT0

TINT1

TINT2

CPU TIMER 0

CPU TIMER 1

CPU TIMER 2

TOUT1

Flash Wrapper

INT13

INT14

CPUTMR2CLK

CLOCKFAIL

NMIRS

NMI Interrupt With Watchdog Function

(See the NMI Watchdog section.)

System Control

(See the System Control section.)

NMI

Figure 8-16. External and PIE Interrupt Sources

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TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts

per group equals 96 possible interrupts. Table 8-17 shows the interrupts used by 2806x devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine (ISR)

corresponding to the vector specified. The TRAP #0 instruction attempts to transfer program control to the

address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,

the TRAP #0 instruction should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the ISR

corresponding to the first vector within the PIE group. For example: the TRAP #1 instruction fetches the vector

from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so forth.

IFR[12:1]

IER[12:1]

INTM

INT1

INT2

1

CPU

MUX

0

INT11

INT12

Global

Enable

(Flag)

(Enable)

INTx.1

INTx.2

INTx.3

INTx.4

INTx.5

From

Peripherals

or

External

Interrupts

INTx

MUX

INTx.6

INTx.7

INTx.8

PIEACKx

(Enable)

(Flag)

(Enable/Flag)

PIEIERx[8:1]

PIEIFRx[8:1]

Figure 8-17. Multiplexing of Interrupts Using the PIE Block

82

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table 8-17. PIE MUXed Peripheral Interrupt Vector Table ⁽¹⁾

INTx.8

WAKEINT

(LPM/WD)

0xD4E

INTx.7

INTx.6

ADCINT9

(ADC)

INTx.5

INTx.4

INTx.3

Reserved

–

INTx.2

ADCINT2

(ADC)

INTx.1

ADCINT1

(ADC)

INT1.y

INT2.y

INT3.y

INT4.y

INT5.y

INT6.y

INT7.y

INT8.y

INT9.y

INT10.y

INT11.y

INT12.y

TINT0

XINT2

XINT1

(TIMER 0)

0xD4C

Ext. int. 2

0xD48

Ext. int. 1

0xD46

0xD4A

0xD44

0xD42

0xD40

EPWM8_TZINT

(ePWM8)

0xD5E

EPWM7_TZINT

(ePWM7)

0xD5C

EPWM6_TZINT

(ePWM6)

0xD5A

EPWM5_TZINT

(ePWM5)

0xD58

EPWM4_TZINT

(ePWM4)

0xD56

EPWM3_TZINT

(ePWM3)

0xD54

EPWM2_TZINT

(ePWM2)

0xD52

EPWM1_TZINT

(ePWM1)

0xD50

EPWM8_INT

(ePWM8)

0xD6E

EPWM7_INT

(ePWM7)

0xD6C

EPWM6_INT

(ePWM6)

0xD6A

EPWM5_INT

(ePWM5)

0xD68

EPWM4_INT

(ePWM4)

0xD66

EPWM3_INT

(ePWM3)

0xD64

EPWM2_INT

(ePWM2)

0xD62

EPWM1_INT

(ePWM1)

0xD60

HRCAP2_INT

(HRCAP2)

0xD7E

HRCAP1_INT

(HRCAP1)

0xD7C

Reserved

–

Reserved

–

Reserved

–

ECAP3_INT

(eCAP3)

0xD74

ECAP2_INT

(eCAP2)

0xD72

ECAP1_INT

(eCAP1)

0xD70

0xD7A

0xD78

0xD76

USB0_INT

(USB0)

0xD8E

Reserved

–

Reserved

–

HRCAP4_INT

(HRCAP4)

0xD88

HRCAP3_INT

(HRCAP3)

0xD86

Reserved

–

EQEP2_INT

(eQEP2)

0xD82

EQEP1_INT

(eQEP1)

0xD80

0xD8C

0xD8A

0xD84

Reserved

–

Reserved

–

MXINTA

(McBSP-A)

0xD9A

MRINTA

(McBSP-A)

0xD98

SPITXINTB

(SPI-B)

0xD96

SPIRXINTB

(SPI-B)

0xD94

SPITXINTA

(SPI-A)

SPIRXINTA

(SPI-A)

0xD9E

0xD9C

0xD92

0xD90

Reserved

–

Reserved

–

DINTCH6

(DMA)

DINTCH5

(DMA)

DINTCH4

(DMA)

DINTCH3

(DMA)

DINTCH2

(DMA)

DINTCH1

(DMA)

0xDAE

0xDAC

Reserved

–

0xDAA

0xDA8

0xDA6

0xDA4

0xDA2

0xDA0

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

I2CINT2A

(I2C-A)

I2CINT1A

(I2C-A)

0xDBE

0xDBC

Reserved

–

0xDBA

0xDB8

0xDB6

0xDB4

0xDB2

0xDB0

Reserved

–

ECAN1_INTA

(CAN-A)

0xDCA

ECAN0_INTA

(CAN-A)

0xDC8

SCITXINTB

(SCI-B)

0xDC6

SCIRXINTB

(SCI-B)

0xDC4

SCITXINTA

(SCI-A)

SCIRXINTA

(SCI-A)

0xDCE

0xDCC

ADCINT7

(ADC)

0xDC2

0xDC0

ADCINT8

(ADC)

ADCINT6

(ADC)

ADCINT5

(ADC)

ADCINT4

(ADC)

ADCINT3

(ADC)

ADCINT2

(ADC)

ADCINT1

(ADC)

0xDDE

0xDDC

CLA1_INT7

(CLA)

0xDDA

0xDD8

0xDD6

0xDD4

0xDD2

0xDD0

CLA1_INT8

(CLA)

CLA1_INT6

(CLA)

CLA1_INT5

(CLA)

CLA1_INT4

(CLA)

CLA1_INT3

(CLA)

CLA1_INT2

(CLA)

CLA1_INT1

(CLA)

0xDEE

0xDEC

LVF

0xDEA

0xDE8

0xDE6

0xDE4

0xDE2

0xDE0

LUF

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

XINT3

(CLA)

Ext. Int. 3

0xDF0

0xDFE

0xDFC

0xDFA

0xDF8

0xDF6

0xDF4

0xDF2

(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be

used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a

peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.

To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

a. No peripheral within the group is asserting interrupts.

b. No peripheral interrupts are assigned to the group (for example, PIE group 7).

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table 8-18. PIE Configuration and Control Registers

NAME

PIECTRL

ADDRESS

0x0CE0

0x0CE1

0x0CE2

0x0CE3

0x0CE4

0x0CE5

0x0CE6

0x0CE7

0x0CE8

0x0CE9

0x0CEA

0x0CEB

0x0CEC

0x0CED

0x0CEE

0x0CEF

0x0CF0

0x0CF1

0x0CF2

0x0CF3

0x0CF4

0x0CF5

0x0CF6

0x0CF7

0x0CF8

0x0CF9

SIZE (×16)

DESCRIPTION⁽¹⁾

1

6

PIE, Control Register

PIEACK

PIEIER1

PIEIFR1

PIEIER2

PIEIFR2

PIEIER3

PIEIFR3

PIEIER4

PIEIFR4

PIEIER5

PIEIFR5

PIEIER6

PIEIFR6

PIEIER7

PIEIFR7

PIEIER8

PIEIFR8

PIEIER9

PIEIFR9

PIEIER10

PIEIFR10

PIEIER11

PIEIFR11

PIEIER12

PIEIFR12

Reserved

PIE, Acknowledge Register

PIE, INT1 Group Enable Register

PIE, INT1 Group Flag Register

PIE, INT2 Group Enable Register

PIE, INT2 Group Flag Register

PIE, INT3 Group Enable Register

PIE, INT3 Group Flag Register

PIE, INT4 Group Enable Register

PIE, INT4 Group Flag Register

PIE, INT5 Group Enable Register

PIE, INT5 Group Flag Register

PIE, INT6 Group Enable Register

PIE, INT6 Group Flag Register

PIE, INT7 Group Enable Register

PIE, INT7 Group Flag Register

PIE, INT8 Group Enable Register

PIE, INT8 Group Flag Register

PIE, INT9 Group Enable Register

PIE, INT9 Group Flag Register

PIE, INT10 Group Enable Register

PIE, INT10 Group Flag Register

PIE, INT11 Group Enable Register

PIE, INT11 Group Flag Register

PIE, INT12 Group Enable Register

PIE, INT12 Group Flag Register

Reserved

0x0CFA –

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector

table is protected.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.8.1 External Interrupts

Table 8-19. External Interrupt Registers

NAME

XINT1CR

ADDRESS

0x00 7070

0x00 7071

0x00 7072

0x00 7078

0x00 7079

0x00 707A

SIZE (×16)

DESCRIPTION

XINT1 configuration register

XINT2 configuration register

XINT3 configuration register

XINT1 counter register

1

XINT2CR

XINT3CR

XINT1CTR

XINT2CTR

XINT3CTR

XINT2 counter register

XINT3 counter register

Each external interrupt can be enabled or disabled or qualified using positive, negative, or both positive and

negative edge. For more information, see the Systems Control and Interrupts chapter of the TMS320x2806x

Technical Reference Manual .

8.8.1.1 External Interrupt Electrical Data/Timing

8.8.1.1.1 External Interrupt Timing Requirements

MIN⁽¹⁾

1t_c(SCO)

MAX

UNIT

cycles

Synchronous

With qualifier

(2)

t_w(INT)

Pulse duration, INT input low/high

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.

8.8.1.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

MAX

t_w(IQSW)+ 12t_c(SCO)

UNIT

t_d(INT)

Delay time, INT low/high to interrupt-vector fetch

cycles

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

t

w(INT)

XINT1, XINT2, XINT3

t

d(INT)

Address bus

(internal)

Interrupt Vector

Figure 8-18. External Interrupt Timing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9 Peripherals

8.9.1 CLA Overview

The CLA extends the capabilities of the C28x CPU by adding parallel processing. Time-critical control loops

serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system

response and higher frequency control loops. Using the CLA for time-critical tasks frees the main CPU to

perform other system and communication functions concurently. A list of major features of the CLA follows.

•

Clocked at the same rate as the main CPU (SYSCLKOUT)

An independent architecture allowing CLA algorithm execution independent of the main C28x CPU

– Complete bus architecture:

•

Program address bus and program data bus

Data address bus, data read bus, and data write bus

– Independent eight-stage pipeline

– 12-bit program counter (MPC)

– Four 32-bit result registers (MR0 to MR3)

– Two 16-bit auxillary registers (MAR0, MAR1)

– Status register (MSTF)

•

Instruction set includes:

– IEEE single-precision (32-bit) floating-point math operations

– Floating-point math with parallel load or store

– Floating-point multiply with parallel add or subtract

– 1/X and 1/sqrt(X) estimations

– Data type conversions

– Conditional branch and call

– Data load and store operations

•

The CLA program code can consist of up to eight tasks or ISRs.

– The start address of each task is specified by the MVECT registers.

– No limit on task size as long as the tasks fit within the CLA program memory space.

– One task at a time is serviced to completion. Tasks are not nested.

– Upon task completion, a task-specific interrupt is flagged within the PIE.

– When a task finishes, the next highest-priority pending task is automatically started.

Task trigger mechanisms:

– C28x CPU through the IACK instruction

– Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:

•

Task1: ADCINT1 or EPWM1_INT

Task2: ADCINT2 or EPWM2_INT

Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT

Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT

– Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT.

Memory and Shared Peripherals:

•

– Two dedicated message RAMs for communication between the CLA and the main CPU

– The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.

– The CLA has direct access to the ADC Result registers, comparator registers, and the eCAP, eQEP, and

ePWM+HRPWM registers.

Figure 8-19 shows the CLA block diagram. Table 8-20 lists the CLA control registers.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Peripheral Interrupts

CLA Control

Registers

IACK

ADCINT1 to ADCINT8

ECAP1_INT to ECAP3_INT

EQEP1_INT and EQEP2_INT

EPWM1_INT to EPWM8_INT

CPU Timer 0

MIFR

MIOVF

MICLR

MICLROVF

MIFRC

MIER

CLA_INT1 to CLA_INT8

Main

28x

CPU

INT11

INT12

MPERINT1

to

MPERINT8

PIE

LVF

LUF

MIRUN

Main CPU Read/Write Data Bus

MPISRCSEL1

MVECT1

MVECT2

MVECT3

MVECT4

MVECT5

MVECT6

MVECT7

MVECT8

CLA Program Address Bus

CLA Program Data Bus

CLA

Program

Memory

CLA

Data

Memory

Map to CLA or

CPU Space

Map to CLA or

CPU Space

MMEMCFG

MCTL

CLA

Shared

Message

RAMs

SYSCLKOUT

CLAENCLK

SYSRS

ADC

Result

Registers

MEALLOW

CLA Execution

Registers

ePWM

and

CLA Data Read Address Bus

HRPWM

Registers

MPC(12)

MSTF(32)

MR0(32)

MR1(32)

MR2(32)

MR3(32)

CLA Data Read Data Bus

CLA Data Write Address Bus

CLA Data Write Data Bus

Main CPU Read Data Bus

Comparator

Registers

MAR0(32)

MAR1(32)

eCAP

Registers

eQEP

Registers

Figure 8-19. CLA Block Diagram

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Table 8-20. CLA Control Registers

CLA1

ADDRESS

EALLOW

PROTECTED

REGISTER NAME

MVECT1

SIZE (×16)

DESCRIPTION⁽¹⁾

0x1400

0x1401

0x1402

0x1403

0x1404

0x1405

0x1406

0x1407

0x1410

0x1411

0x1414

0x1420

0x1421

0x1422

0x1423

0x1424

0x1425

0x1426

0x1427

0x1428

0x142A

0x142B

0x142E

0x1430

0x1434

0x1438

0x143C

1

2

1

2

Yes

–

CLA Interrupt/Task 1 Start Address

CLA Interrupt/Task 2 Start Address

CLA Interrupt/Task 3 Start Address

CLA Interrupt/Task 4 Start Address

CLA Interrupt/Task 5 Start Address

CLA Interrupt/Task 6 Start Address

CLA Interrupt/Task 7 Start Address

CLA Interrupt/Task 8 Start Address

CLA Control Register

MVECT2

MVECT3

MVECT4

MVECT5

MVECT6

MVECT7

MVECT8

MCTL

MMEMCFG

MPISRCSEL1

MIFR

CLA Memory Configure Register

Peripheral Interrupt Source Select Register 1

Interrupt Flag Register

Interrupt Overflow Register

Interrupt Force Register

Interrupt Clear Register

Interrupt Overflow Clear Register

Interrupt Enable Register

Interrupt RUN Register

Interrupt Priority Control Register

CLA Program Counter

CLA Aux Register 0

MIOVF

MIFRC

MICLR

MICLROVF

MIER

MIRUN

MIPCTL

MPC⁽²⁾

MAR0⁽²⁾

MAR1⁽²⁾

MSTF⁽²⁾

MR0⁽²⁾

–

CLA Aux Register 1

–

CLA STF Register

–

CLA R0H Register

MR1⁽²⁾

–

CLA R1H Register

MR2⁽²⁾

–

CLA R2H Register

MR3⁽²⁾

–

CLA R3H Register

(1) All registers in this table are CSM-protected.

(2) The main C28x CPU has read-only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes

to this register.

Table 8-21. CLA Message RAM

ADDRESS RANGE

0x1480 – 0x14FF

0x1500 – 0x157F

SIZE (×16)

DESCRIPTION

128

CLA to CPU Message RAM

CPU to CLA Message RAM

128

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.2 Analog Block

A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on the F280x and F2833x

devices. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve

the timing control of start of conversions. Figure 8-20 shows the interaction of the analog module with the rest of

the F2806x system.

80-Pin 100-Pin

(3.3 V) VDDA

(Agnd) VSSA

VDDA

VSSA

VREFLO

Tied To

VSSA

Interface Reference

Diff

VREFLO

VREFHI

A0

VREFHI

Tied To

A0

VREFHI

A0

B0

A1

A2

A3

A4

A5

A6

A7

B0

B1

B2

B3

B4

B5

B6

B7

A1

A2

A1

B1

COMP1OUT

A2

A4

A5

A6

AIO2

AIO10

10-Bit

DAC

Comp1

Comp2

B2

A3

B3

ADC

B0

B1

B2

COMP2OUT

A4

B4

AIO4

AIO12

10-Bit

DAC

B4

B5

B6

B5

Temperature Sensor

A5

A6

COMP3OUT

Signal Pinout

AIO6

AIO14

10-Bit

DAC

Comp3

B6

A7

B7

Figure 8-20. Analog Pin Configurations

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.2.1 Analog-to-Digital Converter (ADC)

8.9.2.1.1 Features

The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-and-

hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog

input channels. The converter can be configured to run with an internal band-gap reference to create true-

voltage based conversions or with a pair of external voltage references (V_REFHI/V_REFLO) to create ratiometric-

based conversions.

Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of

conversions from a single trigger. However, the basic principle of operation is centered around the configurations

of individual conversions, called SOCs, or Start-Of-Conversions.

Functions of the ADC module include:

•

12-bit ADC core with built-in dual sample-and-hold (S/H)

Simultaneous sampling or sequential sampling modes

Full range analog input: 0 V to 3.3 V fixed, or V_REFHI/V_REFLOratiometric. The digital value of the input analog

voltage is derived by:

– Internal Reference (V_REFLO= V_SSA. V_REFHImust not exceed V_DDAwhen using either internal or external

reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input < 3.3 V

3.3

Digital Value = 4095,

when input ³ 3.3 V

– External Reference (V_REFHI/V_REFLOconnected to external references. V_REFHImust not exceed V_DDAwhen

using either internal or external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input <

V_REFHI

-

V_REFHIV_REFLO

Digital Value = 4095,

when input ³

V_REFHI

•

Up to 16-channel, multiplexed inputs

16 SOCs, configurable for trigger, sample window, and channel

16 result registers (individually addressable) to store conversion values

Multiple trigger sources

– S/W – software immediate start

– ePWM 1–8

– GPIO XINT2

– CPU Timer 0, CPU Timer 1, CPU Timer 2

– ADCINT1, ADCINT2

•

9 flexible PIE interrupts, can configure interrupt request after any conversion

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Table 8-22. ADC Configuration and Control Registers

EALLOW

PROTECTE

D

SIZE

(×16)

REGISTER NAME

ADDRESS

DESCRIPTION

ADCCTL1

0x7100

0x7101

0x7104

0x7105

0x7106

0x7107

0x7108

0x7109

0x710A

0x710B

0x710C

0x7110

0x7112

0x7114

0x7115

0x7118

0x711A

0x711C

0x711E

1

Yes

No

Control 1 Register

Control 2 Register

Interrupt Flag Register

ADCCTL2

ADCINTFLG

ADCINTFLGCLR

ADCINTOVF

No

Interrupt Flag Clear Register

No

Interrupt Overflow Register

ADCINTOVFCLR

INTSEL1N2

No

Interrupt Overflow Clear Register

Yes

No

Interrupt 1 and 2 Selection Register

INTSEL3N4

Interrupt 3 and 4 Selection Register

INTSEL5N6

Interrupt 5 and 6 Selection Register

INTSEL7N8

Interrupt 7 and 8 Selection Register

INTSEL9N10

Interrupt 9 Selection Register (reserved Interrupt 10 Selection)

SOC Priority Control Register

SOCPRICTL

ADCSAMPLEMODE

ADCINTSOCSEL1

ADCINTSOCSEL2

ADCSOCFLG1

ADCSOCFRC1

ADCSOCOVF1

ADCSOCOVFCLR1

Sampling Mode Register

Interrupt SOC Selection 1 Register (for 8 channels)

Interrupt SOC Selection 2 Register (for 8 channels)

SOC Flag 1 Register (for 16 channels)

SOC Force 1 Register (for 16 channels)

SOC Overflow 1 Register (for 16 channels)

SOC Overflow Clear 1 Register (for 16 channels)

SOC0 Control Register to SOC15 Control Register

No

ADCSOC0CTL to

ADCSOC15CTL

0x7120 –

0x712F

1

Yes

ADCREFTRIM

ADCOFFTRIM

COMPHYSTCTL

ADCREV

0x7140

0x7141

0x714C

0x714F

1

Yes

No

Reference Trim Register

Offset Trim Register

Comparator Hysteresis Control Register

Revision Register

Table 8-23. ADC Result Registers (Mapped to PF0)

SIZE

(×16)

EALLOW

PROTECTED

REGISTER NAME

ADCRESULT0 to ADCRESULT15

ADDRESS

DESCRIPTION

0xB00 to

0xB0F

1

No

ADC Result 0 Register to ADC Result 15 Register

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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0-Wait

Result

Registers

PF0 (CPU)

PF2 (CPU)

SYSCLKOUT

ADCENCLK

ADCINT 1

PIE

ADCINT 9

TINT 0

CPUTIMER 0

CPUTIMER 1

CPUTIMER 2

ADCTRIG 1

ADCTRIG 2

ADCTRIG 3

TINT 1

TINT 2

ADC

Core

12-Bit

XINT 2SOC

AIO

MUX

ADC

Channels

XINT 2

EPWM 1

EPWM 2

EPWM 3

EPWM 4

EPWM 5

EPWM 6

EPWM 7

EPWM 8

ADCTRIG 4

SOCA 1

SOCB 1

SOCA 2

SOCB 2

SOCA 3

SOCB 3

SOCA 4

SOCB 4

SOCA 5

SOCB 5

SOCA 6

SOCB 6

SOCA 7

SOCB 7

SOCA 8

SOCB 8

ADCTRIG 5

ADCTRIG 6

ADCTRIG 7

ADCTRIG 8

ADCTRIG 9

ADCTRIG 10

ADCTRIG 11

ADCTRIG 12

ADCTRIG 13

ADCTRIG 14

ADCTRIG 15

ADCTRIG 16

ADCTRIG 17

ADCTRIG 18

ADCTRIG 19

ADCTRIG 20

Figure 8-21. ADC Connections

ADC Connections if the ADC is Not Used

TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following is a

summary of how the ADC pins should be connected, if the ADC is not used in an application:

•

V_DDA– Connect to V_DDIO

V_SSA– Connect to V_SS

V_REFLO– Connect to V_SS

ADCINAn, ADCINBn, V_REFHI– Connect to V_SSA

When the ADC module is used in an application, unused ADC input pins should be connected to analog ground

(V_SSA).

Note

TI recommends that unused ADCIN pins which are multiplexed with AIO function be grounded through

a 1-kΩ resistor. This recommendation is intended to prevent any inadvertent software activation of the

AIO output logic-high driving directly to ground; this condition can cause permanent device damage by

exceeding I_OHAbsolute Maximum.

When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing

8.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_w(ADCSOCL)

Pulse duration, ADCSOCxO low

32t_c(HCO)

cycles

t_w(ADCSOCL)

ADCSOCAO

or

ADCSOCBO

Figure 8-22. ADCSOCAO or ADCSOCBO Timing

8.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing

8.9.2.1.3.1 ADC Electrical Characteristics

PARAMETER

DC SPECIFICATIONS

MIN

TYP

MAX

UNIT

Resolution

12

Bits

ADC clock

90-MHz device

0.001

45

64

MHz

ADC

Clocks

Sample Window

7

ACCURACY

INL (Integral nonlinearity)⁽¹⁾

–4

–1

4

LSB

DNL (Differential nonlinearity), no missing codes

1.5

Executing a single self-

recalibration⁽³⁾

–20

–4

20

4

Offset error ⁽²⁾

LSB

Executing periodic self-

recalibration⁽⁴⁾

Overall gain error with internal reference

Overall gain error with external reference

Channel-to-channel offset variation

Channel-to-channel gain variation

ADC temperature coefficient with internal reference

ADC temperature coefficient with external reference

V_REFLO

–60

–40

–4

60

40

4

LSB

–4

4

LSB

–50

–20

ppm/°C

µA

–100

100

V_REFHI

µA

ANALOG INPUT

Analog input voltage with internal reference

Analog input voltage with external reference

V_REFLOinput voltage⁽⁵⁾

0

V_REFLO

V_SSA

3.3

V_REFHI

0.66

V

2.64

V_DDA

V_REFHIinput voltage⁽⁶⁾

V

with V_REFLO= V_SSA

1.98

Input capacitance

5

pF

μA

Input leakage current

±2

(1) INL will degrade when the ADC input voltage goes above V_DDA

.

(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and V_REFHI- V_REFLOfor external

reference.

(3) For more details, see the TMS320F2806x MCUs Silicon Errata.

(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error.

(5) V_REFLOis always connected to V_SSAon the 80-pin PN and PFP devices.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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(6) V_REFHImust not exceed V_DDAwhen using either internal or external reference modes. Because V_REFHIis tied to ADCINA0 on the 80-

pin PN and PFP devices, the input signal on ADCINA0 must not exceed V_DDA

.

8.9.2.1.3.2 ADC Power Modes

ADC OPERATING MODE

CONDITIONS

I_DDA

UNIT

ADC Clock Enabled

Band gap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWDN = 1)

Mode A – Operating Mode

16

mA

ADC Clock Enabled

Band gap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWDN = 0)

Mode B – Quick Wake Mode

Mode C – Comparator-Only Mode

Mode D – Off Mode

4

mA

ADC Clock Enabled

Band gap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWDN = 0)

1.5

ADC Clock Enabled

Band gap On (ADCBGPWD = 0)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWDN = 0)

0.075

8.9.2.1.3.3 Internal Temperature Sensor

8.9.2.1.3.3.1 Temperature Sensor Coefficient

PARAMETER⁽¹⁾

MIN

TYP

0.18^{(3) (2)}

1750

MAX

UNIT

°C/LSB

LSB

Degrees C of temperature movement per measured ADC LSB change of

the temperature sensor

T_SLOPE

T_OFFSET

ADC output at 0°C of the temperature sensor

(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be

adjusted accordingly in external reference mode to the external reference voltage.

(2) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing

temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values

relative to an initial value.

(3) ADC temperature coeffieicient is accounted for in this specification

8.9.2.1.3.4 ADC Power-Up Control Bit Timing

8.9.2.1.3.4.1 ADC Power-Up Delays

PARAMETER⁽¹⁾

MIN

MAX

UNIT

t_d(PWD)

Delay time for the ADC to be stable after power up

1

ms

(1) Timings maintain compatibility to the ADC module. The 2806x ADC supports driving all 3 bits at the same time t_d(PWD)ms before first

conversion.

ADCPWDN/

ADCBGPWD/

ADCREFPWD/

ADCENABLE

t_d(PWD)

Request for ADC

Conversion

Figure 8-23. ADC Conversion Timing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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R_on

3.4 kW

Switch

R_s

ADCIN

C_p

C_h

Source

Signal

ac

5 pF

1.6 pF

28x DSP

Typical Values of the Input Circuit Components:

Switch Resistance (R_on): 3.4 kW

Sampling Capacitor (C_h): 1.6 pF

Parasitic Capacitance (C_p): 5 pF

Source Resistance (R_s): 50 W

Figure 8-24. ADC Input Impedance Model

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.2.1.3.5 ADC Sequential and Simultaneous Timings

Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG1.SOC0

ADCSOCFLG1.SOC1

ADCSOCFLG1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

2 ADCCLKs

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

1 ADCCLK

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

Figure 8-25. Timing Example for Sequential Mode / Late Interrupt Pulse

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG1.SOC0

ADCSOCFLG1.SOC1

ADCSOCFLG1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

2 ADCCLKs

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

Figure 8-26. Timing Example for Sequential Mode / Early Interrupt Pulse

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Analog Input A

SOC0 Sample

A Window

SOC2 Sample

A Window

Analog Input B

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG1.SOC0

ADCSOCFLG1.SOC1

ADCSOCFLG1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

2 ADCCLKs

Result 0 (A) Latched

ADCRESULT 1

Result 0 (B) Latched

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

1 ADCCLK

EOC2 Pulse

ADCINTFLG .ADCINTx

Minimum

7 ADCCLKs

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

2 ADCCLKs

19

ADCCLKs

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

Figure 8-27. Timing Example for Simultaneous Mode / Late Interrupt Pulse

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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Analog Input A

Analog Input B

SOC0 Sample

A Window

SOC2 Sample

A Window

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG1.SOC0

ADCSOCFLG1.SOC1

ADCSOCFLG1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

Result 0 (A) Latched

2 ADCCLKs

Result 0 (B) Latched

ADCRESULT 1

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

Minimum

2 ADCCLKs

7 ADCCLKs

19

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

ADCCLKs

Figure 8-28. Timing Example for Simultaneous Mode / Early Interrupt Pulse

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.9.2.2 ADC MUX

To COMPy A or B input

To ADC Channel X

Logic implemented in GPIO MUX block

AIOx Pin

SYSCLK

AIOxIN

1

AIOxINE

AIODAT Reg

(Read)

SYNC

0

AIODAT Reg

(Latch)

AIOMUX 1 Reg

AIOSET,

AIOCLEAR,

AIOTOGGLE

Regs

AIODIR Reg

(Latch)

1

(0 = Input, 1 = Output)

0

Figure 8-29. AIOx Pin Multiplexing

The ADC channel and Comparator functions are always available. The digital I/O function is available only when

the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects the actual pin

state.

The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode, reading

the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to

prevent analog signals from generating noise.

On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO

function disabled for that pin.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.2.3 Comparator Block

Figure 8-30 shows the interaction of the Comparator modules with the rest of the system.

COMP x A

+

COMP x B

COMP

TZ1/2/3

-

GPIO

MUX

COMP x

+

DAC x

Wrapper

ePWM

AIO

MUX

COMPxOUT

DAC

Core

10-Bit

Figure 8-30. Comparator Block Diagram

Table 8-24. Comparator Control Registers

REGISTER

NAME

COMP1

ADDRESS

COMP2

ADDRESS

COMP3

ADDRESS

SIZE

(×16)

EALLOW

PROTECTED

DESCRIPTION

COMPCTL

0x6400

0x6402

0x6404

0x6406

0x6420

0x6422

0x6424

0x6426

0x6440

0x6442

0x6444

0x6446

1

Yes

No

Comparator Control Register

Comparator Status Register

DAC Control Register

COMPSTS

DACCTL

DACVAL

Yes

No

DAC Value Register

RAMPMAXREF_

ACTIVE

Ramp Generator Maximum Reference

(Active) Register

0x6408

0x640A

0x640C

0x6428

0x642A

0x642C

0x6448

0x644A

0x644C

1

No

RAMPMAXREF_

SHDW

Ramp Generator Maximum Reference

(Shadow) Register

RAMPDECVAL_

ACTIVE

Ramp Generator Decrement Value

(Active) Register

RAMPDECVAL_

SHDW

Ramp Generator Decrement Value

(Shadow) Register

0x640E

0x6410

0x642E

0x6430

0x644E

0x6450

1

No

RAMPSTS

Ramp Generator Status Register

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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UNIT

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

8.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing

8.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC

CHARACTERISTIC

MIN

TYP

MAX

Comparator

Comparator Input Range

V_SSA– V_DDA

V

Comparator response time to PWM Trip Zone (Async)

30

±5

35

ns

Input Offset

mV

Input Hysteresis⁽¹⁾

DAC

DAC Output Range

DAC resolution

DAC settling time

DAC Gain

V_SSA– V_DDA

V

10

bits

See Figure 8-31.

–1.5%

10

DAC Offset

Monotonic

mV

Yes

±3

INL

LSB

(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback

resistance between the output of the comparator and the non-inverting input of the comparator.

1100

1000

900

800

700

600

500

400

300

200

100

0

50

100

150

200

250

300

350

400

450

500

DAC Step Size (Codes)

DAC Accuracy

15 Codes

7 Codes

3 Codes

1 Code

Figure 8-31. DAC Settling Time

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.9.3 Detailed Descriptions

Integral Nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The

point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level

one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code

to the true straight line between these two points.

Differential Nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A

differential nonlinearity error of less than ±1 LSB ensures no missing codes.

Zero Offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value one-half LSB above negative full scale. The last

transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the

deviation of the actual difference between first and last code transitions and the ideal difference between first

and last code transitions.

Signal-to-Noise Ratio + Distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components

below the Nyquist frequency, including harmonics but excluding DC. The value for SINAD is expressed in

decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

(SINAD -1.76)

N =

6.02

it is possible to get a measure of performance expressed as N, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated

directly from its measured SINAD.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input

signal and is expressed as a percentage or in decibels.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.4 Serial Peripheral Interface (SPI) Module

The device includes the 4-pin serial peripheral interface (SPI) module. Up to two SPI modules are available. The

SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to

16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for

communications between the MCU and external peripherals or another processor. Typical applications include

external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.

Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

•

Four external pins:

– SPISOMI: SPI slave-output/master-input pin

– SPISIMO: SPI slave-input/master-output pin

– SPISTE: SPI slave transmit-enable pin

– SPICLK: SPI serial-clock pin

Note

All four pins can be used as GPIO if the SPI module is not used.

•

Two operational modes: master and slave

Baud rate: 125 different programmable rates.

LSPCLK

Baud rate =

when SPIBRR = 3 to127

when SPIBRR = 0,1, 2

(SPIBRR + 1)

LSPCLK

4

•

Data word length: 1 to 16 data bits

Four clocking schemes (controlled by clock polarity and clock phase bits) include:

– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling

edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising

edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

Simultaneous receive and transmit operation (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.

Nine SPI module control registers: In control register frame beginning at address 7040h.

•

Note

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a

register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read

as zeros. Writing to the upper byte has no effect.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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Enhanced feature:

•

4-level transmit/receive FIFO

Delayed transmit control

Bidirectional 3 wire SPI mode support

Audio data receive support through SPISTE inversion

The SPI port operation is configured and controlled by the registers listed in Table 8-25 and Table 8-26.

Table 8-25. SPI-A Registers

NAME

SPICCR

ADDRESS

0x7040

0x7041

0x7042

0x7044

0x7046

0x7047

0x7048

0x7049

0x704A

0x704B

0x704C

0x704F

SIZE (×16) EALLOW PROTECTED

DESCRIPTION⁽¹⁾

SPI-A Configuration Control Register

SPI-A Operation Control Register

SPI-A Status Register

1

No

SPICTL

SPISTS

SPIBRR

SPI-A Baud Rate Register

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPI-A Receive Emulation Buffer Register

SPI-A Serial Input Buffer Register

SPI-A Serial Output Buffer Register

SPI-A Serial Data Register

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

SPI-A FIFO Transmit Register

SPI-A FIFO Receive Register

SPI-A FIFO Control Register

SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

Table 8-26. SPI-B Registers

NAME

SPICCR

ADDRESS

0x7740

0x7741

0x7742

0x7744

0x7746

0x7747

0x7748

0x7749

0x774A

0x774B

0x774C

0x774F

SIZE (×16) EALLOW PROTECTED

DESCRIPTION⁽¹⁾

SPI-B Configuration Control Register

SPI-B Operation Control Register

SPI-B Status Register

1

No

SPICTL

SPISTS

SPIBRR

SPI-B Baud Rate Register

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPI-B Receive Emulation Buffer Register

SPI-B Serial Input Buffer Register

SPI-B Serial Output Buffer Register

SPI-B Serial Data Register

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

SPI-B FIFO Transmit Register

SPI-B FIFO Receive Register

SPI-B FIFO Control Register

SPI-B Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Figure 8-32 is a block diagram of the SPI in slave mode.

SPIFFENA

Overrun

INT ENA

Receiver

Overrun Flag

SPIFFTX.14

RX FIFO Registers

SPIRXBUF

SPISTS.7

SPICTL.4

RX FIFO _0

RX FIFO _1

-----

SPIINT

RX FIFO Interrupt

RX Interrupt

Logic

RX FIFO _3

16

SPIRXBUF

Buffer Register

SPIFFOVF

FLAG

SPIFFRX.15

To CPU

TX FIFO Registers

SPITXBUF

TX FIFO _3

TX Interrupt

Logic

TX FIFO Interrupt

-----

TX FIFO _1

SPITX

TX FIFO _0

16

SPI INT

ENA

16

SPI INT FLAG

SPITXBUF

Buffer Register

SPISTS.6

SPICTL.0

TRIWIRE

SPIPRI.0

16

M

S

M

SPIDAT

Data Register

TW

S

SW1

SW2

SPISIMO

SPISOMI

M

S

TW

SPIDAT.15 - 0

M

S

TW

STEINV

SPIPRI.1

Talk

STEINV

SPICTL.1

SPISTE

State Control

Master/Slave

SPICTL.2

SPI Char

LSPCLK

SPICCR.3 - 0

S

SW3

3

2

1

0

Clock

Polarity

Clock

Phase

M

S

SPI Bit Rate

SPIBRR.6 - 0

SPICCR.6

SPICTL.3

SPICLK

M

6

5

4

3

2

1

0

A. SPISTE is driven low by the master for a slave device.

Figure 8-32. SPI Module Block Diagram (Slave Mode)

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.4.1 SPI Master Mode Electrical Data/Timing

Section 8.9.4.1.1 lists the master mode timing (clock phase = 0) and Section 8.9.4.1.2 lists the master mode

timing (clock phase = 1). Figure 8-33 and Figure 8-34 show the timing waveforms.

8.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)

NO.⁽¹⁾

BRR EVEN

MIN

BRR ODD

MIN

(2) (3) (4)

PARAMETER

UNIT

(5)

MAX

1

t_c(SPC)M

Cycle time, SPICLK

4t_c(LSPCLK)

128t_c(LSPCLK)

5t_c(LSPCLK)

127t_c(LSPCLK)

ns

Pulse duration, SPICLK first

pulse

0.5t_c(SPC)M+ 0.5t_c(LSPCLK)

– 10

0.5t_c(SPC)M

+

2

3

t_w(SPC1)M

0.5t_c(SPC)M– 10

0.5t_c(SPC)M+ 10

10

0.5t_c(LSPCLK)+ 10

Pulse duration, SPICLK second

pulse

0.5t_c(SPC)M– 0.5t_c(LSPCLK)

– 10

0.5t_c(SPC)M

–

t_w(SPC2)M

t_d(SIMO)M

t_v(SIMO)M

t_su(SOMI)M

t_h(SOMI)M

t_d(SPC)M

t_d(STE)M

0.5t_c(SPC)M– 10

ns

0.5t_c(LSPCLK)+ 10

Delay time, SPICLK to

SPISIMO valid

4

10

Valid time, SPISIMO valid after

SPICLK

0.5t_c(SPC)M– 0.5t_c(LSPCLK)

– 10

5

0.5t_c(SPC)M– 10

Setup time, SPISOMI before

SPICLK

8

26

0

26

0

Hold time, SPISOMI valid after

SPICLK

9

Delay time, SPISTE active to

SPICLK

1.5t_c(SPC)M

–

1.5t_c(SPC)M–

3t_c(SYSCLK)– 10

23

24

3t_c(SYSCLK)– 10

Delay time, SPICLK to SPISTE

inactive

0.5t_c(SPC)M– 0.5t_c(LSPCLK)

– 10

0.5t_c(SPC)M– 10

(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)

(3) t_c(LCO)= LSPCLK cycle time

(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

8

9

Master In Data

Must Be Valid

SPISOMI

SPISTE

24

23

Figure 8-33. SPI Master Mode External Timing (Clock Phase = 0)

8.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)

NO.⁽¹⁾

BRR EVEN

MIN

BRR ODD

MIN

(2) (3) (4)

PARAMETER

UNIT

(5)

MAX

127t_c(LSPCLK)

0.5t_c(SPC)M–

1

t_c(SPC)M

Cycle time, SPICLK

4t_c(LSPCLK)

128t_c(LSPCLK)

5t_c(LSPCLK)

0.5t_c(SPC)M

ns

Pulse duration, SPICLK first

pulse

–

2

3

t_w(SPC1)M

0.5t_c(SPC)M– 10

0.5t_c(SPC)M+ 10

0.5t_c(LSPCLK)– 10

0.5t_c(LSPCLK)+ 10

Pulse duration, SPICLK second

pulse

0.5t_c(SPC)M

+

0.5t_c(SPC)M

0.5t_c(LSPCLK)+ 10

+

t_w(SPC2)M

t_d(SIMO)M

t_v(SIMO)M

t_su(SOMI)M

t_h(SOMI)M

t_d(SPC)M

t_d(STE)M

0.5t_c(SPC)M– 10

ns

0.5t_c(LSPCLK)– 10

Delay time, SPISIMO valid to

SPICLK

0.5t_c(SPC)M

+

6

0.5t_c(SPC)M– 10

0.5t_c(LSPCLK)– 10

Valid time, SPISIMO valid after

SPICLK

0.5t_c(SPC)M

–

7

0.5t_c(SPC)M– 10

0.5t_c(LSPCLK)– 10

Setup time, SPISOMI before

SPICLK

10

11

23

24

26

0

26

Hold time, SPISOMI valid after

SPICLK

0

Delay time, SPISTE active to

SPICLK

2t_c(SPC)M

–

2t_c(SPC)M

–

3t_c(SYSCLK)– 10

Delay time, SPICLK to SPISTE

inactive

0.5t_c(SPC)

–

0.5t_c(SPC)– 10

0.5t_c(LSPCLK)– 10

(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX

Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.

(4) t_c(LCO)= LSPCLK cycle time

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

6

7

SPISIMO

Master Out Data Is Valid

10

11

Master In Data Must

Be Valid

SPISOMI

SPISTE

24

23

Figure 8-34. SPI Master Mode External Timing (Clock Phase = 1)

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.9.4.2 SPI Slave Mode Electrical Data/Timing

Section 8.9.4.2.1 lists the slave mode timing (clock phase = 0) and Section 8.9.4.2.2 lists the slave mode timing

(clock phase = 1). Figure 8-35 and Figure 8-36 show the timing waveforms.

8.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0) ^{(1) (2) (4) (3) (5)}

NO.

PARAMETER

Cycle time, SPICLK

MIN

4t_c(SYSCLK)

MAX UNIT

12 t_c(SPC)S

13 t_w(SPC1)S

14 t_w(SPC2)S

15 t_d(SOMI)S

16 t_v(SOMI)S

19 t_su(SIMO)S

20 t_h(SIMO)S

25 t_su(STE)S

26 t_h(STE)S

ns

Pulse duration, SPICLK first pulse

2t_c(SYSCLK)– 1

Pulse duration, SPICLK second pulse

Delay time, SPICLK to SPISOMI valid

Valid time, SPISOMI data valid after SPICLK

Setup time, SPISIMO valid before SPICLK

Hold time, SPISIMO data valid after SPICLK

Setup time, SPISTE active before SPICLK

Hold time, SPISTE inactive after SPICLK

21

ns

0

1.5t_c(SYSCLK)

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) t_c(LCO)= LSPCLK cycle time

(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

15

16

SPISOMI

SPISOMI Data Is Valid

19

20

SPISIMO Data

Must Be Valid

SPISIMO

SPISTE

25

26

Figure 8-35. SPI Slave Mode External Timing (Clock Phase = 0)

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1) ^{(1) (2) (3) (4)}

NO.

PARAMETER

Cycle time, SPICLK

MIN

4t_c(SYSCLK)

MAX UNIT

12 t_c(SPC)S

13 t_w(SPC1)S

14 t_w(SPC2)S

17 t_d(SOMI)S

18 t_v(SOMI)S

21 t_su(SIMO)S

22 t_h(SIMO)S

25 t_su(STE)S

26 t_h(STE)S

ns

Pulse duration, SPICLK first pulse

2t_c(SYSCLK)– 1

Pulse duration, SPICLK second pulse

Delay time, SPICLK to SPISOMI valid

Valid time, SPISOMI data valid after SPICLK

Setup time, SPISIMO valid before SPICLK

Hold time, SPISIMO data valid after SPICLK

Setup time, SPISTE active before SPICLK

Hold time, SPISTE inactive after SPICLK

21

ns

0

1.5t_c(SYSCLK)

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

17

SPISOMI

SPISOMI Data Is Valid

Data Valid

18

21

22

SPISIMO Data

Must Be Valid

SPISIMO

SPISTE

26

25

Figure 8-36. SPI Slave Mode External Timing (Clock Phase = 1)

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

8.9.5 Serial Communications Interface (SCI) Module

The devices include two serial communications interface (SCI) modules (SCI-A, SCI-B). The SCI module

supports digital communications between the CPU and other asynchronous peripherals that use the standard

non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own

separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex

mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing

errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

•

Two external pins:

– SCITXD: SCI transmit-output pin

– SCIRXD: SCI receive-input pin

Note

Both pins can be used as GPIO if not used for SCI.

– Baud rate programmable to 64K different rates:

LSPCLK

Baud rate =

when BRR ¹ 0

when BRR = 0

(BRR + 1) * 8

LSPCLK

16

•

Data-word format

– One start bit

– Data-word length programmable from 1 to 8 bits

– Optional even/odd/no parity bit

– One or 2 stop bits

•

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: idle-line and address bit

Half- or full-duplex operation

Double-buffered receive and transmit functions

Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with

status flags.

– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY

flag (transmitter-shift register is empty)

– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break

condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

Separate enable bits for transmitter and receiver interrupts (except BRKDT)

NRZ (non-return-to-zero) format

•

Note

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a

register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read

as zeros. Writing to the upper byte has no effect.

Enhanced features:

•

Auto baud-detect hardware logic

4-level transmit/receive FIFO

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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The SCI port operation is configured and controlled by the registers listed in Table 8-27 and Table 8-28.

Table 8-27. SCI-A Registers

EALLOW

PROTECTED

NAME⁽¹⁾

SCICCRA

ADDRESS

SIZE (×16)

DESCRIPTION

0x7050

0x7051

0x7052

0x7053

0x7054

0x7055

0x7056

0x7057

0x7059

0x705A

0x705B

0x705C

0x705F

1

No

SCI-A Communications Control Register

SCI-A Control Register 1

SCICTL1A

SCIHBAUDA

SCILBAUDA

SCICTL2A

SCI-A Baud Register, High Bits

SCI-A Baud Register, Low Bits

SCI-A Control Register 2

SCIRXSTA

SCIRXEMUA

SCIRXBUFA

SCITXBUFA

SCIFFTXA⁽²⁾

SCIFFRXA⁽²⁾

SCIFFCTA⁽²⁾

SCIPRIA

SCI-A Receive Status Register

SCI-A Receive Emulation Data Buffer Register

SCI-A Receive Data Buffer Register

SCI-A Transmit Data Buffer Register

SCI-A FIFO Transmit Register

SCI-A FIFO Receive Register

SCI-A FIFO Control Register

SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

Table 8-28. SCI-B Registers

NAME⁽¹⁾

SCICCRB

ADDRESS

0x7750

0x7751

0x7752

0x7753

0x7754

0x7755

0x7756

0x7757

0x7759

0x775A

0x775B

0x775C

0x775F

SIZE (×16)

DESCRIPTION

SCI-B Communications Control Register

SCI-B Control Register 1

1

SCICTL1B

SCIHBAUDB

SCILBAUDB

SCICTL2B

SCI-B Baud Register, High Bits

SCI-B Baud Register, Low Bits

SCI-B Control Register 2

SCIRXSTB

SCIRXEMUB

SCIRXBUFB

SCITXBUFB

SCIFFTXB⁽²⁾

SCIFFRXB⁽²⁾

SCIFFCTB⁽²⁾

SCIPRIB

SCI-B Receive Status Register

SCI-B Receive Emulation Data Buffer Register

SCI-B Receive Data Buffer Register

SCI-B Transmit Data Buffer Register

SCI-B FIFO Transmit Register

SCI-B FIFO Receive Register

SCI-B FIFO Control Register

SCI-B Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

Figure 8-37 shows the SCI module block diagram.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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TXENA

SCICTL1.1

Frame Format and Mode

Parity

SCITXD

TXSHF

Register

TXEMPTY

SCICTL2.6

Even/Odd

Enable

TXINTENA

SCICTL2.0

8

SCICCR.6 SCICCR.5

TXRDY

Transmitter Data

Buffer register

SCICTL2.7

SCITXBUF.7−0

8

TXWAKE

SCICTL1.3

TX FIFO_0

TX FIFO_1

−−−−−

TXINT

TX Interrupt

Logic

1

TX FIFO Interrupt

To CPU

TX FIFO_3

SCI TX Interrupt select logic

Auto baud detect logic

WUT

SCITXBUF.7−0

TX FIFO

SCIFFENA

SCIFFTX.14

RXENA

SCICTL1.0

SCIHBAUD. 15 − 8

SCIRXD

RXSHF

Register

Baud Rate

MSbyte

SCIRXD

Register

RXWAKE

LSPCLK

SCIRXST.1

SCILBAUD. 7 − 0

RXENA

SCICTL1.0

8

Baud Rate

LSbyte

RXBKINTENA

SCICTL2.1

Register

RXRDY

Receive Data

Buffer register

SCIRXST.6

SCIRXBUF.7−0

8

BRKDT

SCIRXST.5

RX FIFO_0

−−−−−

RX FIFO_2

RX FIFO_3

SCIRXBUF.7−0

RX Interrupt

Logic

RXINT

RX FIFO Interrupt

To CPU

RX FIFO

RXFFOVF

SCIFFRX.15

SCIRXST.7

RX Error

SCIRXST.5 – 2

BRKDT FE OE PE

RX Error

RXERRINTENA

SCICTL1.6

SCI RX Interrupt select logic

Figure 8-37. Serial Communications Interface (SCI) Module Block Diagram

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.6 Multichannel Buffered Serial Port (McBSP) Module

The McBSP module has the following features:

•

Compatible to McBSP in TMS320C28x/TMS320F28x DSP devices

Full-duplex communication

Double-buffered data registers that allow a continuous data stream

Independent framing and clocking for receive and transmit

External shift clock generation or an internal programmable frequency shift clock

A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits

8-bit data transfers with LSB or MSB first

Programmable polarity for both frame synchronization and data clocks

Highly programmable internal clock and frame generation

Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected

analog-to-digital (A/D) and digital-to-analog (D/A) devices

Works with SPI-compatible devices

•

The following application interfaces can be supported on the McBSP:

– T1/E1 framers

– IOM-2 compliant devices

– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)

– IIS-compliant devices

– SPI

•

McBSP clock rate,

CLKSRG

CLKG =

1+ CLKGDV

(

)

where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer

switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O

buffer speed limit.

Note

See Section 8.9 for maximum I/O pin toggling speed.

Note

On the 80-pin package, only the clock-stop mode (SPI) of the McBSP is supported.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Figure 8-38 shows the block diagram of the McBSP module.

TX

Interrupt

MXINT

Peripheral Write Bus

CPU

TX Interrupt Logic

To CPU

16

McBSP Transmit

Interrupt Select Logic

DXR2 Transmit Buffer

16

DXR1 Transmit Buffer

16

LSPCLK

MFSXx

MCLKXx

Compand Logic

XSR2

XSR1

MDXx

MDRx

CPU

DMA Bus

RSR1

16

RSR2

16

MCLKRx

Expand Logic

MFSRx

RBR2 Register

16

RBR1 Register

16

DRR2 Receive Buffer

DRR1 Receive Buffer

McBSP Receive

16

Interrupt Select Logic

RX

Interrupt

RX Interrupt Logic

MRINT

CPU

Peripheral Read Bus

To CPU

Figure 8-38. McBSP Module

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table 8-29 provides a summary of the McBSP registers.

Table 8-29. McBSP Register Summary

McBSP-A

ADDRESS

NAME

TYPE

RESET VALUE

DESCRIPTION

Data Registers, Receive, Transmit

DRR2

DRR1

DXR2

DXR1

0x5000

0x5001

0x5002

0x5003

R

0x0000

McBSP Data Receive Register 2

McBSP Data Receive Register 1

W

McBSP Data Transmit Register 2

McBSP Data Transmit Register 1

McBSP Control Registers

SPCR2

SPCR1

RCR2

0x5004

0x5005

0x5006

0x5007

0x5008

0x5009

0x500A

0x500B

R/W

0x0000

McBSP Serial Port Control Register 2

McBSP Serial Port Control Register 1

McBSP Receive Control Register 2

McBSP Receive Control Register 1

McBSP Transmit Control Register 2

McBSP Transmit Control Register 1

McBSP Sample Rate Generator Register 2

McBSP Sample Rate Generator Register 1

RCR1

XCR2

XCR1

SRGR2

SRGR1

Multichannel Control Registers

McBSP Multichannel Register 2

MCR2

0x500C

0x500D

0x500E

0x500F

0x5010

0x5011

0x5012

0x5013

0x5014

0x5015

0x5016

0x5017

0x5018

0x5019

0x501A

0x501B

0x501C

0x501D

0x501E

0x5023

R/W

0x0000

MCR1

McBSP Multichannel Register 1

RCERA

RCERB

XCERA

XCERB

PCR

McBSP Receive Channel Enable Register Partition A

McBSP Receive Channel Enable Register Partition B

McBSP Transmit Channel Enable Register Partition A

McBSP Transmit Channel Enable Register Partition B

McBSP Pin Control Register

RCERC

RCERD

XCERC

XCERD

RCERE

RCERF

XCERE

XCERF

RCERG

RCERH

XCERG

XCERH

MFFINT

McBSP Receive Channel Enable Register Partition C

McBSP Receive Channel Enable Register Partition D

McBSP Transmit Channel Enable Register Partition C

McBSP Transmit Channel Enable Register Partition D

McBSP Receive Channel Enable Register Partition E

McBSP Receive Channel Enable Register Partition F

McBSP Transmit Channel Enable Register Partition E

McBSP Transmit Channel Enable Register Partition F

McBSP Receive Channel Enable Register Partition G

McBSP Receive Channel Enable Register Partition H

McBSP Transmit Channel Enable Register Partition G

McBSP Transmit Channel Enable Register Partition H

McBSP Interrupt Enable Register

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.6.1 McBSP Electrical Data/Timing

8.9.6.1.1 McBSP Transmit and Receive Timing

8.9.6.1.1.1 McBSP Timing Requirements

NO.⁽¹⁾

MIN

MAX

UNIT

(2)

1

kHz

MHz

ns

McBSP module clock (CLKG, CLKX, CLKR) range

McBSP module cycle time (CLKG, CLKX, CLKR) range

20^{(3) (4)}

50⁽⁴⁾

1

ms

ns

M11 t_c(CKRX)

M12 t_w(CKRX)

M13 t_r(CKRX)

M14 t_f(CKRX)

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

2P

Pulse duration, CLKR/X high or CLKR/X low

Rise time, CLKR/X

P – 7

ns

7

ns

Fall time, CLKR/X

ns

18

2

M15 t_su(FRH-CKRL)

M16 t_h(CKRL-FRH)

M17 t_su(DRV-CKRL)

M18 t_h(CKRL-DRV)

M19 t_su(FXH-CKXL)

M20 t_h(CKXL-FXH)

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

0

6

18

2

0

Hold time, DR valid after CLKR low

6

18

2

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

CLKX ext

CLKX int

0

CLKX ext

6

(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that

signal are also inverted.

(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV). CLKSRG can be LSPCLK,

CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.

(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer

speed limit (20 MHz).

(4) Maximum McBSP module clock frequency decreases to 10 MHz for internal CLKR.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.9.6.1.1.2 McBSP Switching Characteristics

over recommended operating conditions (unless otherwise noted)^{(1) (2)}

NO.

M1

M2

M3

PARAMETER

MIN

MAX UNIT

t_c(CKRX)

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

2P

ns

t_w(CKRXH)

t_w(CKRXL)

Pulse duration, CLKR/X high

Pulse duration, CLKR/X low

D – 5⁽³⁾

D + 5⁽³⁾

ns

C – 5⁽³⁾

C + 5⁽³⁾

0

3

0

3

4

27

4

M4

M5

M6

t_d(CKRH-FRV)

t_d(CKXH-FXV)

t_{dis(CKXH-DXHZ)}

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

ns

27

8

Disable time, CLKX high to DX high impedance

following last data bit

14

9

Delay time, CLKX high to DX valid.

This applies to all bits except the first bit transmitted.

28

8

Delay time, CLKX high to DX valid

DXENA = 0

M7

t_d(CKXH-DXV)

ns

14

P + 8

Only applies to first bit transmitted when

in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1

10b) modes

CLKX ext

P + 14

CLKX int

CLKX ext

CLKX int

0

6

Enable time, CLKX high to DX driven

Only applies to first bit transmitted when

in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1

10b) modes

DXENA = 0

M8

M9

t_en(CKXH-DX)

P

CLKX ext

P + 6

FSX int

FSX ext

FSX int

FSX ext

FSX int

FSX ext

FSX int

FSX ext

8

14

Delay time, FSX high to DX valid

DXENA = 0

DXENA = 1

DXENA = 0

DXENA = 1

t_d(FXH-DXV)

ns

P + 8

P + 14

Only applies to first bit transmitted when

in Data Delay 0 (XDATDLY=00b) mode.

0

6

Enable time, FSX high to DX driven

M10 t_en(FXH-DX)

P

Only applies to first bit transmitted when

in Data Delay 0 (XDATDLY=00b) mode

P + 6

(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that

signal are also inverted.

(2) 2P = 1/CLKG in ns.

(3) C = CLKRX low pulse width = P

D = CLKRX high pulse width = P

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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M1, M11

M2, M12

M3, M12

M13

CLKR

M4

M14

FSR (int)

M15

M16

FSR (ext)

M18

M17

DR

(RDATDLY=00b)

Bit (n−1)

M17

(n−2)

(n−3)

(n−2)

(n−4)

M18

DR

(RDATDLY=01b)

Bit (n−1)

(n−3)

(n−2)

M17

M18

DR

(RDATDLY=10b)

Bit (n−1)

Figure 8-39. McBSP Receive Timing

M1, M11

M2, M12

M13

M14

M3, M12

CLKX

FSX (int)

FSX (ext)

M5

M19

M20

M9

M7

M10

Bit 0

DX

(XDATDLY=00b)

Bit (n−1)

(n−2)

(n−3)

(n−2)

(n−4)

(n−3)

(n−2)

M7

M8

DX

(XDATDLY=01b)

Bit (n−1)

M8

Bit 0

M6

M7

DX

(XDATDLY=10b)

Bit 0

Bit (n−1)

Figure 8-40. McBSP Transmit Timing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.6.1.2 McBSP as SPI Master or Slave Timing

8.9.6.1.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)

MASTER

SLAVE

MIN MAX

NO.⁽¹⁾

UNIT

MIN

30

1

MAX

M30 t_su(DRV-CKXL)

M31 t_h(CKXL-DRV)

M32 t_{su(BFXL-CKXH)}

M33 t_c(CKX)

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

Setup time, FSX low before CLKX high

Cycle time, CLKX

8P – 10

ns

8P – 10

8P + 10

16P

2P⁽²⁾

(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =

CLKGDV = 1.

(2) 2P = 1/CLKG

8.9.6.1.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)

over recommended operating conditions (unless otherwise noted)

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

UNIT

MAX

M24

M25

M26

t_h(CKXL-FXL)

t_d(FXL-CKXH)

t_d(CKXH-DXV)

Hold time, FSX low after CLKX low

Delay time, FSX low to CLKX high

Delay time, CLKX high to DX valid

2P⁽¹⁾

ns

P

–2

0

3P + 6

5P + 20

Disable time, DX high impedance following

last data bit from FSX high

M28

M29

t_{dis(FXH-DXHZ)}

t_d(FXL-DXV)

6

6P + 6

4P + 6

ns

Delay time, FSX low to DX valid

(1) 2P = 1/CLKG

M33

M32

MSB

LSB

CLKX

M25

M26

M24

FSX

M28

M29

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

M30

M31

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Figure 8-41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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UNIT

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

8.9.6.1.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)

MASTER

SLAVE

MIN MAX

NO.⁽¹⁾

MIN

30

1

MAX

M39 t_su(DRV-CKXH)

M40 t_h(CKXH-DRV)

M41 t_su(FXL-CKXH)

M42 t_c(CKX)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

Setup time, FSX low before CLKX high

Cycle time, CLKX

8P – 10

ns

8P – 10

16P + 10

16P

2P⁽²⁾

(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =

CLKGDV = 1.

(2) 2P = 1/CLKG

8.9.6.1.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)

over recommended operating conditions (unless otherwise noted)

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

UNIT

MAX

M34 t_h(CKXL-FXL)

M35 t_d(FXL-CKXH)

M36 t_d(CKXL-DXV)

Hold time, FSX low after CLKX low

Delay time, FSX low to CLKX high

Delay time, CLKX low to DX valid

P

2P⁽¹⁾

–2

ns

0

3P + 6 5P + 20

7P + 6

Disable time, DX high impedance following last data bit

from CLKX low

M37 t_{dis(CKXL-DXHZ)}

M38 t_d(FXL-DXV)

P + 6

6

ns

Delay time, FSX low to DX valid

4P + 6

(1) 2P = 1/CLKG

M42

MSB

LSB

M41

CLKX

M36

M35

M34

FSX

M37

M38

DX

DR

Bit 0

Bit(n-1)

(n-2)

M40

(n-2)

(n-3)

(n-4)

M39

Bit 0

(n-3)

(n-4)

Figure 8-42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.6.1.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)

MASTER

SLAVE

MIN MAX

NO.⁽¹⁾

UNIT

MIN

30

1

MAX

M49 t_su(DRV-CKXH)

M50 t_h(CKXH-DRV)

M51 t_su(FXL-CKXL)

M52 t_c(CKX)

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

Setup time, FSX low before CLKX low

Cycle time, CLKX

8P – 10

ns

8P – 10

8P + 10

16P

2P⁽²⁾

(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =

CLKGDV = 1.

(2) 2P = 1/CLKG

8.9.6.1.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)

over recommended operating conditions (unless otherwise noted)

MASTER

SLAVE

MIN MAX

NO.

PARAMETER

UNIT

MIN

2P⁽¹⁾

P

MAX

M43 t_h(CKXH-FXL)

M44 t_d(FXL-CKXL)

M45 t_d(CKXL-DXV)

Hold time, FSX low after CLKX high

Delay time, FSX low to CLKX low

Delay time, CLKX low to DX valid

ns

–2

0

3P + 6 5P + 20

6P + 6

Disable time, DX high impedance following last data bit from

FSX high

M47 t_{dis(FXH-DXHZ)}

M48 t_d(FXL-DXV)

6

ns

Delay time, FSX low to DX valid

4P + 6

(1) 2P = 1/CLKG

M52

M51

MSB

LSB

CLKX

M45

M43

M44

FSX

M48

M47

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

M49

M50

(n-2)

Bit 0

(n-3)

Figure 8-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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UNIT

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

8.9.6.1.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)

MASTER

SLAVE

MIN MAX

NO.⁽¹⁾

MIN

30

1

MAX

M58 t_su(DRV-CKXL)

M59 t_h(CKXL-DRV)

M60 t_su(FXL-CKXL)

M61 t_c(CKX)

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

Setup time, FSX low before CLKX low

Cycle time, CLKX

8P – 10

ns

8P – 10

16P + 10

16P

2P⁽²⁾

(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =

CLKGDV = 1.

(2) 2P = 1/CLKG

8.9.6.1.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)

over recommended operating conditions (unless otherwise noted)⁽¹⁾

MASTER

MIN

SLAVE

MIN

NO.

PARAMETER

UNIT

MAX

M53 t_h(CKXH-FXL)

M54 t_d(FXL-CKXL)

M55 t_d(CKXH-DXV)

Hold time, FSX low after CLKX high

Delay time, FSX low to CLKX low

Delay time, CLKX high to DX valid

P

ns

2P⁽¹⁾

–2

0

3P + 6

5P + 20

Disable time, DX high impedance following last data

bit from CLKX high

M56 t_{dis(CKXH-DXHZ)}

M57 t_d(FXL-DXV)

P + 6

6

7P + 6

4P + 6

ns

Delay time, FSX low to DX valid

(1) 2P = 1/CLKG

M61

M60

MSB

LSB

CLKX

M53

M54

FSX

M56

M55

M57

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

M58

M59

Bit 0

Bit(n-1)

(n-2)

(n-3)

Figure 8-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.7 Enhanced Controller Area Network (eCAN) Module

The CAN module (eCAN-A) has the following features:

•

Fully compliant with CAN protocol, version 2.0B

Supports data rates up to 1 Mbps

Thirty-two mailboxes, each with the following properties:

– Configurable as receive or transmit

– Configurable with standard or extended identifier

– Has a programmable receive mask

– Supports data and remote frame

– Composed of 0 to 8 bytes of data

– Uses a 32-bit timestamp on receive and transmit message

– Protects against reception of new message

– Holds the dynamically programmable priority of transmit message

– Employs a programmable interrupt scheme with two interrupt levels

– Employs a programmable alarm on transmission or reception time-out

Low-power mode

Programmable wake-up on bus activity

Automatic reply to a remote request message

Automatic retransmission of a frame in case of loss of arbitration or error

32-bit local network time counter synchronized by a specific message (communication in conjunction with

mailbox 16)

•

Self-test mode

– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby

eliminating the need for another node to provide the acknowledge bit.

Note

For a SYSCLKOUT of 90 MHz, the smallest bit rate possible is 6.25 kbps.

The F2806x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and

exceptions.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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eCAN0INT

eCAN1INT

Controls Address

Data

32

Enhanced CAN Controller

Message Controller

Mailbox RAM

(512 Bytes)

Memory Management

Unit

eCAN Memory

(512 Bytes)

Registers and

CPU Interface,

Receive Control Unit,

Timer Management Unit

32-Message Mailbox

of 4 ´ 32-Bit Words

Message Objects Control

32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

Figure 8-45. eCAN Block Diagram and Interface Circuit

Table 8-30. 3.3-V eCAN Transceivers

SUPPLY

VOLTAGE

LOW-POWER

MODE

SLOPE

CONTROL

PART NUMBER

VREF

OTHER

T_A

–40°C to 85°C

SN65HVD230

SN65HVD230Q

SN65HVD231

SN65HVD231Q

SN65HVD232

SN65HVD232Q

SN65HVD233

SN65HVD234

SN65HVD235

3.3 V

Standby

Sleep

Adjustable

None

Yes

–

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

Yes

–

Sleep

Yes

–

None

–

None

–

Standby

Standby and Sleep

Standby

Adjustable

Diagnostic Loopback

–

Autobaud Loopback

Built-in Isolation

Low Prop Delay

ISO1050

3–5.5 V

None

Thermal Shutdown

Fail-safe Operation

Dominant Time-Out

–55°C to 105°C

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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eCAN-A Control and Status Registers

Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

eCAN-A Memory (512 Bytes)

Control and Status Registers

Abort Acknowledge - CANAA

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

6000h

603Fh

6040h

Local Acceptance Masks (LAM)

(32 ´ 32-Bit RAM)

607Fh

6080h

Master Control - CANMC

Message Object Timestamps (MOTS)

(32 ´ 32-Bit RAM)

Bit-Timing Configuration - CANBTC

60BFh

60C0h

Error and Status - CANES

Message Object Time-Out (MOTO)

(32 ´ 32-Bit RAM)

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Global Interrupt Flag 1 - CANGIF1

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

60FFh

eCAN-A Memory RAM (512 Bytes)

6100h-6107h

6108h-610Fh

6110h-6117h

6118h-611Fh

6120h-6127h

Mailbox 0

Mailbox 1

Mailbox 2

Mailbox 3

Mailbox 4

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Timestamp Counter - CANTSC

Time-Out Control - CANTOC

Time-Out Status - CANTOS

61E0h-61E7h

61E8h-61EFh

61F0h-61F7h

61F8h-61FFh

Mailbox 28

Mailbox 29

Mailbox 30

Mailbox 31

Reserved

Message Mailbox (16 Bytes)

Message Identifier - MSGID

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

61E8h-61E9h

61EAh-61EBh

61ECh-61EDh

61EEh-61EFh

Figure 8-46. eCAN-A Memory Map

Note

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and

mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for

this.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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The CAN registers listed in Table 8-31 are used by the CPU to configure and control the CAN controller and the

message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be

accessed as 16 bits or 32 bits. All 32-bit accesses are aligned to an even boundary.

Table 8-31. CAN Registers

eCAN-A

REGISTER NAME⁽¹⁾

SIZE (×32)

DESCRIPTION

ADDRESS

0x6000

0x6002

0x6004

0x6006

0x6008

0x600A

0x600C

0x600E

0x6010

0x6012

0x6014

0x6016

0x6018

0x601A

0x601C

0x601E

0x6020

0x6022

0x6024

0x6026

0x6028

0x602A

0x602C

0x602E

0x6030

0x6032

CANME

1

Mailbox enable

CANMD

Mailbox direction

CANTRS

CANTRR

CANTA

Transmit request set

Transmit request reset

Transmission acknowledge

Abort acknowledge

Receive message pending

Receive message lost

Remote frame pending

Global acceptance mask

Master control

CANAA

CANRMP

CANRML

CANRFP

CANGAM

CANMC

CANBTC

CANES

Bit-timing configuration

Error and status

CANTEC

CANREC

CANGIF0

CANGIM

CANGIF1

CANMIM

CANMIL

CANOPC

CANTIOC

CANRIOC

CANTSC

CANTOC

CANTOS

Transmit error counter

Receive error counter

Global interrupt flag 0

Global interrupt mask

Global interrupt flag 1

Mailbox interrupt mask

Mailbox interrupt level

Overwrite protection control

TX I/O control

RX I/O control

Timestamp counter (Reserved in SCC mode)

Time-out control (Reserved in SCC mode)

Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.8 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 8-47 shows how the I2C peripheral module interfaces within the

device.

The I2C module has the following features:

•

Compliance with the Philips Semiconductors I²C-bus specification (version 2.1):

– Support for 1-bit to 8-bit format transfers

– 7-bit and 10-bit addressing modes

– General call

– START byte mode

– Support for multiple master-transmitters and slave-receivers

– Support for multiple slave-transmitters and master-receivers

– Combined master transmit/receive and receive/transmit mode

– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)

One 4-word receive FIFO and one 4-word transmit FIFO

One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following

conditions:

•

– Transmit-data ready

– Receive-data ready

– Register-access ready

– No-acknowledgment received

– Arbitration lost

– Stop condition detected

– Addressed as slave

•

An additional interrupt that can be used by the CPU when in FIFO mode

Module enable/disable capability

Free data format mode

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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I2C Module

I2CXSR

I2CDXR

TX FIFO

RX FIFO

FIFO Interrupt to

CPU/PIE

SDA

Peripheral Bus

I2CRSR

I2CDRR

Control/Status

Registers

CPU

Clock

Synchronizer

SCL

Prescaler

Noise Filters

Arbitrator

Interrupt to

CPU/PIE

I2C INT

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the

SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power operation. Upon reset,

I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 8-47. I2C Peripheral Module Interfaces

The registers in Table 8-32 configure and control the I2C port operation.

Table 8-32. I2C-A Registers

EALLOW

PROTECTED

NAME

ADDRESS

DESCRIPTION

I2C own address register

I2COAR

I2CIER

0x7900

0x7901

0x7902

0x7903

0x7904

0x7905

0x7906

0x7907

0x7908

0x7909

0x790A

0x790C

0x7920

0x7921

–

No

I2C interrupt enable register

I2C status register

I2CSTR

I2CCLKL

I2CCLKH

I2CCNT

I2CDRR

I2CSAR

I2CDXR

I2CMDR

I2CISRC

I2CPSC

I2CFFTX

I2CFFRX

I2CRSR

I2C clock low-time divider register

I2C clock high-time divider register

I2C data count register

I2C data receive register

I2C slave address register

I2C data transmit register

I2C mode register

I2C interrupt source register

I2C prescaler register

I2C FIFO transmit register

I2C FIFO receive register

I2C receive shift register (not accessible to the CPU)

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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Table 8-32. I2C-A Registers (continued)

EALLOW

PROTECTED

NAME

ADDRESS

DESCRIPTION

I2CXSR

–

No

I2C transmit shift register (not accessible to the CPU)

8.9.8.1 I2C Electrical Data/Timing

Section 8.9.8.1.1 shows the I2C timing requirements. Section 8.9.8.1.2 shows the I2C switching characteristics.

8.9.8.1.1 I2C Timing Requirements

MIN

MAX UNIT

Hold time, START condition, SCL fall delay

after SDA fall

t_{h(SDA-SCL)START}

t_{su(SCL-SDA)START}

0.6

µs

Setup time, Repeated START, SCL rise

before SDA fall delay

0.6

µs

t_h(SCL-DAT)

t_su(DAT-SCL)

t_r(SDA)

Hold time, data after SCL fall

Setup time, data before SCL rise

Rise time, SDA

0

100

20

µs

ns

Input tolerance

300

ns

t_r(SCL)

Rise time, SCL

20

t_f(SDA)

Fall time, SDA

11.4

t_f(SCL)

Fall time, SCL

Setup time, STOP condition, SCL rise before

SDA rise delay

t_{su(SCL-SDA)STOP}

0.6

µs

8.9.8.1.2 I2C Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

I2C clock module frequency is from 7 MHz to

12 MHz and I2C prescaler and clock divider

registers are configured appropriately.

f_SCL

SCL clock frequency

400

kHz

V_il

Low level input voltage

High level input voltage

Input hysteresis

0.3 V_DDIO

V

V_ih

V_hys

V_ol

0.7 V_DDIO

0.05 V_DDIO

0

Low level output voltage

3-mA sink current

0.4

I2C clock module frequency is from 7 MHz to

12 MHz and I2C prescaler and clock divider

registers are configured appropriately.

t_LOWLow period of SCL clock

t_HIGHHigh period of SCL clock

1.3

μs

I2C clock module frequency is from 7 MHz to

12 MHz and I2C prescaler and clock divider

registers are configured appropriately.

0.6

μs

Input current with an input voltage from

0.1 V_DDIOto 0.9 V_DDIOMAX

l_I

–10

10

μA

Submit Document Feedback 131

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

8.9.9 Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)

The devices contain up to eight enhanced PWM (ePWM) modules. Figure 8-48 shows a block diagram of

multiple ePWM modules. Figure 8-49 shows the signal interconnections with the ePWM.

Table 8-33 and Table 8-34 show the complete ePWM register set per module.

EPWMSYNCI

EPWM1SYNCI

EPWM1B

EPWM1TZINT

EPWM1

Module

TZ1 to TZ3

EPWM1INT

EQEP1ERR^(A)

EPWM2TZINT

TZ4

PIE

EPWM2INT

CLOCKFAIL

TZ5

EPWMxTZINT

EMUSTOP

TZ6

EPWMxINT

EPWM1ENCLK

TBCLKSYNC

eCAPI

EPWM1SYNCO

EPWM2SYNCI

EPWM1SYNCO

TZ1 to TZ3

COMPOUT1

COMPOUT2

EPWM2B

EPWM2

Module

EQEP1ERR^(A)

CLOCKFAIL

EMUSTOP

COMP

EPWM1A

EPWM2A

TZ4

TZ5

TZ6

H

R

P

W

M

EPWM2ENCLK

TBCLKSYNC

EPWMxA

G

P

I

EPWM2SYNCO

O

M

U

X

SOCA1

SOCB1

SOCA2

SOCB2

SOCAx

SOCBx

ADC

EPWMxB

EPWMxSYNCI

TZ1 to TZ3

EPWMx

Module

EQEP1ERR^(A)

CLOCKFAIL

EMUSTOP

EQEP1ERR

TZ4

TZ5

TZ6

eQEP1

EPWMxENCLK

TBCLKSYNC

System Control

C28x CPU

SOCA1

SOCA2

SPCAx

ADCSOCAO

ADCSOCBO

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

SOCB1

SOCB2

SPCBx

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

A. This signal exists only on devices with an eQEP1 module.

Figure 8-48. ePWM

132 Submit Document Feedback

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

www.ti.com

NAME

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

Table 8-33. ePWM1–ePWM4 Control and Status Registers

SIZE (×16)/

#SHADOW

ePWM1

ePWM2

ePWM3

ePWM4

DESCRIPTION

TBCTL

0x6800

0x6801

0x6802

0x6803

0x6804

0x6805

0x6806

0x6807

0x6808

0x6809

0x680A

0x680B

0x680C

0x680D

0x6840

0x6841

0x6842

0x6843

0x6844

0x6845

0x6846

0x6847

0x6848

0x6849

0x684A

0x684B

0x684C

0x684D

0x6880

0x6881

0x6882

0x6883

0x6884

0x6885

0x6886

0x6887

0x6888

0x6889

0x688A

0x688B

0x688C

0x688D

0x68C0

0x68C1

0x68C2

0x68C3

0x68C4

0x68C5

0x68C6

0x68C7

0x68C8

0x68C9

0x68CA

0x68CB

0x68CC

0x68CD

1/0

Time Base Control Register

TBSTS

1/0

Time Base Status Register

TBPHSHR

TBPHS

1/0

Time Base Phase HRPWM Register

Time Base Phase Register

1/0

TBCTR

1/0

Time Base Counter Register

TBPRD

1/1

Time Base Period Register Set

TBPRDHR

CMPCTL

CMPAHR

CMPA

1/1

Time Base Period High-Resolution Register⁽¹⁾

Counter Compare Control Register

Time Base Compare A HRPWM Register

Counter Compare A Register Set

Counter Compare B Register Set

Action Qualifier Control Register For Output A

Action Qualifier Control Register For Output B

Action Qualifier Software Force Register

1/0

1/1

CMPB

1/1

AQCTLA

AQCTLB

AQSFRC

1/0

Action Qualifier Continuous S/W Force

Register Set

AQCSFRC

DBCTL

0x680E

0x680F

0x6810

0x684E

0x684F

0x6850

0x688E

0x688F

0x6890

0x68CE

0x68CF

0x68D0

1/1

1/0

Dead-Band Generator Control Register

Dead-Band Generator Rising Edge Delay

Count Register

DBRED

Dead-Band Generator Falling Edge Delay

Count Register

DBFED

0x6811

0x6851

0x6891

0x68D1

1/0

TZSEL

0x6812

0x6813

0x6814

0x6815

0x6816

0x6817

0x6818

0x6819

0x681A

0x681B

0x681C

0x681D

0x681E

0x6820

0x6826

0x6828

0x682A

0x682B

0x682C

0x682D

0x6830

0x6831

0x6832

0x6833

0x6834

0x6852

0x6853

0x6854

0x6855

0x6856

0x6857

0x6858

0x6859

0x685A

0x685B

0x685C

0x685D

0x685E

0x6860

-

0x6892

0x6893

0x6894

0x6895

0x6896

0x6897

0x6898

0x6899

0x689A

0x689B

0x689C

0x689D

0x689E

0x68A0

-

0x68D2

0x68D3

0x68D4

0x68D5

0x68D6

0x68D7

0x68D8

0x68D9

0x68DA

0x68DB

0x68DC

0x68DD

0x68DE

0x68E0

-

1/0

Trip Zone Select Register⁽¹⁾

TZDCSEL

TZCTL

Trip Zone Digital Compare Register

Trip Zone Control Register⁽¹⁾

1/0

TZEINT

1/0

Trip Zone Enable Interrupt Register⁽¹⁾

Trip Zone Flag Register ⁽¹⁾

TZFLG

1/0

TZCLR

1/0

Trip Zone Clear Register⁽¹⁾

TZFRC

1/0

Trip Zone Force Register⁽¹⁾

ETSEL

1/0

Event Trigger Selection Register

Event Trigger Prescale Register

Event Trigger Flag Register

ETPS

1/0

ETFLG

1/0

ETCLR

1/0

Event Trigger Clear Register

ETFRC

1/0

Event Trigger Force Register

PCCTL

1/0

PWM Chopper Control Register

HRPWM Configuration Register⁽¹⁾

HRPWM MEP Step Register

HRCNFG

HRMSTEP

HRPCTL

TBPRDHRM

TBPRDM

CMPAHRM

CMPAM

DCTRIPSEL

DCACTL

DCBCTL

DCFCTL

DCCAPCT

1/0

0x6868

0x686A

0x686B

0x686C

0x686D

0x6870

0x6871

0x6872

0x6873

0x6874

0x68A8

0x68AA

0x68AB

0x68AC

0x68AD

0x68B0

0x68B1

0x68B2

0x68B3

0x68B4

0x68E8

0x68EA

0x68EB

0x68EC

0x68ED

0x68F0

0x68F1

0x68F2

0x68F3

0x68F4

1/0

High-resolution Period Control Register⁽¹⁾

Time Base Period HRPWM Register Mirror

Time Base Period Register Mirror

Compare A HRPWM Register Mirror

Compare A Register Mirror

1/W⁽²⁾

1/0

Digital Compare Trip Select Register ⁽¹⁾

Digital Compare A Control Register⁽¹⁾

Digital Compare B Control Register⁽¹⁾

Digital Compare Filter Control Register⁽¹⁾

Digital Compare Capture Control Register⁽¹⁾

1/0

Submit Document Feedback 133

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Table 8-33. ePWM1–ePWM4 Control and Status Registers (continued)

SIZE (×16)/

#SHADOW

NAME

ePWM1

0x6835

0x6836

0x6837

0x6838

0x6839

ePWM2

0x6875

0x6876

0x6877

0x6878

0x6879

ePWM3

0x68B5

0x68B6

0x68B7

0x68B8

0x68B9

ePWM4

0x68F5

0x68F6

0x68F7

0x68F8

0x68F9

DESCRIPTION

DCFOFFSET

1/1

Digital Compare Filter Offset Register

Digital Compare Filter Offset Counter Register

Digital Compare Filter Window Register

DCFOFFSETCN

T

1/0

1/1

DCFWINDOW

DCFWINDOWCN

T

Digital Compare Filter Window Counter

Register

DCCAP

Digital Compare Counter Capture Register

(1) Registers that are EALLOW protected.

(2) W = Write to shadow register

134 Submit Document Feedback

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Table 8-34. ePWM5–ePWM8 Control and Status Registers

SIZE (×16)/

#SHADOW

NAME

ePWM5

ePWM6

ePWM7

ePWM8

DESCRIPTION

TBCTL

0x6900

0x6901

0x6902

0x6903

0x6904

0x6905

0x6940

0x6941

0x6942

0x6943

0x6944

0x6945

0x6980

0x6981

0x6982

0x6983

0x6984

0x6985

0x69C0

0x69C1

0x69C2

0x69C3

0x69C4

0x69C5

1/0

1/1

Time Base Control Register

Time Base Status Register

Time Base Phase HRPWM Register

Time Base Phase Register

Time Base Counter Register

Time Base Period Register Set

TBSTS

TBPHSHR

TBPHS

TBCTR

TBPRD

Time Base Period High-Resolution

Register⁽¹⁾

TBPRDHR

0x6906

0x6946

0x6986

0x69C6

1/1

CMPCTL

CMPAHR

CMPA

0x6907

0x6908

0x6909

0x690A

0x6947

0x6948

0x6949

0x694A

0x6987

0x6988

0x6989

0x698A

0x69C7

0x69C8

0x69C9

0x69CA

1/0

1/1

Counter Compare Control Register

Time Base Compare A HRPWM Register

Counter Compare A Register Set

Counter Compare B Register Set

CMPB

Action Qualifier Control Register For

Output A

AQCTLA

0x690B

0x694B

0x698B

0x69CB

1/0

Action Qualifier Control Register For

Output B

AQCTLB

AQSFRC

AQCSFRC

DBCTL

0x690C

0x690D

0x690E

0x690F

0x6910

0x694C

0x694D

0x694E

0x694F

0x6950

0x698C

0x698D

0x698E

0x698F

0x6990

0x69CC

0x69CD

0x69CE

0x69CF

0x69D0

1/0

1/1

1/0

Action Qualifier Software Force Register

Action Qualifier Continuous S/W Force

Register Set

Dead-Band Generator Control Register

Dead-Band Generator Rising Edge Delay

Count Register

DBRED

Dead-Band Generator Falling Edge Delay

Count Register

DBFED

0x6911

0x6951

0x6991

0x69D1

1/0

TZSEL

0x6912

0x6913

0x6914

0x6915

0x6916

0x6917

0x6918

0x6919

0x691A

0x691B

0x691C

0x691D

0x691E

0x6920

-

0x6952

0x6953

0x6954

0x6955

0x6956

0x6957

0x6958

0x6959

0x695A

0x695B

0x695C

0x695D

0x695E

0x6960

-

0x6992

0x6993

0x6994

0x6995

0x6996

0x6997

0x6998

0x6999

0x699A

0x699B

0x699C

0x699D

0x699E

0x69A0

-

0x69D2

0x69D3

0x69D4

0x69D5

0x69D6

0x69D7

0x69D8

0x69D9

0x69DA

0x69DB

0x69DC

0x69DD

0x69DE

0x69E0

-

1/0

Trip Zone Select Register⁽¹⁾

TZDCSEL

TZCTL

Trip Zone Digital Compare Register

Trip Zone Control Register⁽¹⁾

1/0

TZEINT

TZFLG

1/0

Trip Zone Enable Interrupt Register⁽¹⁾

Trip Zone Flag Register ⁽¹⁾

1/0

TZCLR

1/0

Trip Zone Clear Register⁽¹⁾

TZFRC

1/0

Trip Zone Force Register⁽¹⁾

ETSEL

1/0

Event Trigger Selection Register

Event Trigger Prescale Register

Event Trigger Flag Register

ETPS

1/0

ETFLG

1/0

ETCLR

1/0

Event Trigger Clear Register

ETFRC

1/0

Event Trigger Force Register

PCCTL

1/0

PWM Chopper Control Register

HRPWM Configuration Register⁽¹⁾

HRPWM MEP Step Register

HRCNFG

HRMSTEP

HRPCTL

TBPRDHRM

TBPRDM

CMPAHRM

CMPAM

DCTRIPSEL

DCACTL

DCBCTL

1/0

0x6928

0x692A

0x692B

0x692C

0x692D

0x6930

0x6931

0x6932

0x6968

0x696A

0x696B

0x696C

0x696D

0x6970

0x6971

0x6972

0x69A8

0x69AA

0x69AB

0x69AC

0x69AD

0x69B0

0x69B1

0x69B2

0x69E8

0x69EA

0x69EB

0x69EC

0x69ED

0x69F0

0x69F1

0x69F2

1/0

High-resolution Period Control Register⁽¹⁾

Time Base Period HRPWM Register Mirror

Time Base Period Register Mirror

Compare A HRPWM Register Mirror

Compare A Register Mirror

1/W⁽²⁾

1/0

Digital Compare Trip Select Register ⁽¹⁾

Digital Compare A Control Register⁽¹⁾

Digital Compare B Control Register⁽¹⁾

1/0

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Table 8-34. ePWM5–ePWM8 Control and Status Registers (continued)

SIZE (×16)/

#SHADOW

NAME

DCFCTL

ePWM5

0x6933

0x6934

0x6935

0x6936

0x6937

0x6938

0x6939

ePWM6

0x6973

0x6974

0x6975

0x6976

0x6977

0x6978

0x6979

ePWM7

0x69B3

0x69B4

0x69B5

0x69B6

0x69B7

0x69B8

0x69B9

ePWM8

0x69F3

0x69F4

0x69F5

0x69F6

0x69F7

0x69F8

0x69F9

DESCRIPTION

1/0

Digital Compare Filter Control Register⁽¹⁾

Digital Compare Capture Control

Register⁽¹⁾

DCCAPCT

1/0

1/1

1/0

1/1

DCFOFFSET

DCFOFFSETCNT

DCFWINDOW

DCFWINDOWCNT

DCCAP

Digital Compare Filter Offset Register

Digital Compare Filter Offset Counter

Register

Digital Compare Filter Window Register

Digital Compare Filter Window Counter

Register

Digital Compare Counter Capture Register

(1) Registers that are EALLOW protected.

(2) W = Write to shadow register

136 Submit Document Feedback

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

Time-Base (TB)

CTR=ZERO

Sync

In/Out

TBPRD Shadow (24)

TBPRD Active (24)

EPWMxSYNCO

CTR=CMPB

Disabled

Select

Mux

TBPRDHR (8)

8

CTR=PRD

TBCTL[SYNCOSEL]

TBCTL[PHSEN]

EPWMxSYNCI

DCAEVT1.sync

DCBEVT1.sync

Counter

Up/Down

(16 Bit)

TBCTL[SWFSYNC]

(Software Forced

Sync)

CTR=ZERO

CTR_Dir

TCBNT

Active (16)

CTR=PRD

CTR=ZERO

TBPHSHR (8)

EPWMxINT

CTR=PRD or ZERO

CTR=CMPA

Event

Trigger

and

Interrupt

(ET)

16

8

EPWMxSOCA

Phase

Control

CTR=CMPB

CTR_Dir

(A)

DCAEVT1.soc

(A)

TBPHS Active (24)

EPWMxSOCB

EPWMxSOCA

ADC

DCBEVT1.soc

EPWMxSOCB

Action

Qualifier

(AQ)

CTR=CMPA

CMPAHR (8)

16

High-resolution PWM (HRPWM)

CMPA Active (24)

CMPA Shadow (24)

EPWMxA

EPWMA

EPWMB

PWM

Chopper

(PC)

Trip

Zone

(TZ)

Dead

Band

(DB)

CTR=CMPB

16

EPWMxB

EPWMxTZINT

TZ1 to TZ3

EMUSTOP

CMPB Active (16)

CMPB Shadow (16)

CLOCKFAIL

(B)

EQEP1ERR

CTR=ZERO

DCAEVT1.inter

DCBEVT1.inter

(A)

DCAEVT1.force

DCAEVT2.force

DCBEVT1.force

DCBEVT2.force

DCAEVT2.inter

DCBEVT2.inter

A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ

signals.

B. This signal exists only on devices with an eQEP1 module.

Figure 8-49. ePWM Submodules Showing Critical Internal Signal Interconnections

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.9.1 ePWM Electrical Data/Timing

PWM refers to PWM outputs on ePWM1–8. Section 8.9.9.1.1 shows the PWM timing requirements and Section

8.9.9.1.2, switching characteristics.

8.9.9.1.1 ePWM Timing Requirements

MIN⁽¹⁾

2t_c(SCO)

MAX

UNIT

cycles

Asynchronous

Synchronous

t_w(SYCIN)

Sync input pulse width

2t_c(SCO)

With input qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

8.9.9.1.2 ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

33.33

MAX

UNIT

ns

t_w(PWM)

Pulse duration, PWMx output high/low

Sync output pulse width

t_w(SYNCOUT)

8t_c(SCO)

cycles

Delay time, trip input active to PWM forced high

Delay time, trip input active to PWM forced low

t_d(PWM)tza

no pin load

25

20

ns

t_d(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

8.9.9.2 Trip-Zone Input Timing

Section 8.9.9.2.1 lists the trip-zone input timing requirements. Figure 8-50 shows the PWM Hi-Z characteristics.

8.9.9.2.1 Trip-Zone Input Timing Requirements

MIN⁽¹⁾

2t_c(TBCLK)

MAX UNIT

cycles

Asynchronous

Synchronous

t_w(TZ)

Pulse duration, TZx input low

2t_c(TBCLK)

cycles

With input qualifier

2t_c(TBCLK)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

SYSCLK

t_w(TZ)

TZ^(A)

t_d(TZ-PWM)HZ

PWM^(B)

A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.

Figure 8-50. PWM Hi-Z Characteristics

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8.9.10 High-Resolution PWM (HRPWM)

This module combines multiple delay lines in a single module and a simplified calibration system by using a

dedicated calibration delay line. For each ePWM module there is one HR delay line.

The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be

achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

•

Significantly extends the time resolution capabilities of conventionally derived digital PWM

This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual edge

control for frequency/period modulation.

•

Finer time granularity control or edge positioning is controlled through extensions to the Compare A and

Phase registers of the ePWM module.

HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an

ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

Note

The minimum SYSCLKOUT frequency allowed for HRPWM is 60 MHz.

Note

When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB channel will

have ±1–2 TBCLK cycles of jitter on the output.

8.9.10.1 HRPWM Electrical Data/Timing

Section 8.9.10.1.1 shows the high-resolution PWM switching characteristics.

8.9.10.1.1 High-Resolution PWM Characteristics

PARAMETER⁽¹⁾

MIN

TYP

MAX UNIT

310 ps

Micro Edge Positioning (MEP) step size⁽²⁾

150

(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 60 MHz.

(2) The MEP step size will be largest at high temperature and minimum voltage on V_DD. MEP step size will increase with higher

temperature and lower voltage and decrease with lower temperature and higher voltage.

Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI

software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per

SYSCLKOUT period dynamically while the HRPWM is in operation.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.9.11 Enhanced Capture Module (eCAP1)

The device contains an enhanced capture (eCAP) module. Figure 8-51 shows a functional block diagram of a

module.

CTRPHS

(phase register−32 bit)

APWM mode

SYNCIn

CTR_OVF

OVF

CTR [0−31]

PRD [0−31]

CMP [0−31]

TSCTR

(counter−32 bit)

SYNCOut

PWM

compare

logic

Delta−mode

RST

32

CTR=PRD

CTR=CMP

CTR [0−31]

PRD [0−31]

32

eCAPx

32

LD1

CAP1

(APRD active)

Polarity

select

LD

APRD

shadow

32

CMP [0−31]

32

LD2

CAP2

(ACMP active)

Polarity

select

LD

Event

qualifier

Event

Pre-scale

32

ACMP

shadow

Polarity

select

32

LD3

LD4

CAP3

(APRD shadow)

LD

CAP4

(ACMP shadow)

Polarity

select

LD

4

Capture events

4

CEVT[1:4]

Interrupt

Trigger

and

Flag

control

Continuous /

Oneshot

Capture Control

to PIE

CTR_OVF

CTR=PRD

CTR=CMP

Figure 8-51. eCAP Functional Block Diagram

The eCAP module is clocked at the SYSCLKOUT rate.

The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low-

power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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NAME

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

Table 8-35. eCAP Control and Status Registers

EALLOW

PROTECTED

eCAP1

eCAP2

eCAP3

SIZE (×16)

DESCRIPTION

Timestamp Counter

TSCTR

CTRPHS

CAP1

0x6A00

0x6A02

0x6A04

0x6A06

0x6A08

0x6A0A

0x6A20

0x6A22

0x6A24

0x6A26

0x6A28

0x6A2A

0x6A40

0x6A42

0x6A44

0x6A46

0x6A48

0x6A4A

2

No

Counter Phase Offset Value Register

Capture 1 Register

CAP2

Capture 2 Register

CAP3

Capture 3 Register

CAP4

Capture 4 Register

0x6A0C to

0x6A12

0x6A2C to

0x6A32

0x6A4C to

0x6A52

Reserved

8

No

Reserved

ECCTL1

ECCTL2

ECEINT

ECFLG

ECCLR

ECFRC

0x6A14

0x6A15

0x6A16

0x6A17

0x6A18

0x6A19

0x6A34

0x6A35

0x6A36

0x6A37

0x6A38

0x6A39

0x6A54

0x6A55

0x6A56

0x6A57

0x6A58

0x6A59

1

No

Capture Control Register 1

Capture Control Register 2

Capture Interrupt Enable Register

Capture Interrupt Flag Register

Capture Interrupt Clear Register

Capture Interrupt Force Register

0x6A1A to

0x6A1F

0x6A3A to

0x6A3F

0x6A5A to

0x6A5F

Reserved

6

No

Reserved

8.9.11.1 eCAP Electrical Data/Timing

Section 8.9.11.1.1 shows the eCAP timing requirement and Section 8.9.11.1.2 shows the eCAP switching

characteristics.

8.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement

MIN⁽¹⁾

2t_c(SCO)

MAX UNIT

Asynchronous

Synchronous

t_w(CAP)

Capture input pulse width

2t_c(SCO)

cycles

With input qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

8.9.11.1.2 eCAP Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_w(APWM)

Pulse duration, APWMx output high/low

20

ns

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)

The device contains up to four high-resolution capture (HRCAP) modules. The High-Resolution Capture

(HRCAP) module measures the difference between external pulses with a typical resolution of 300 ps.

Uses for the HRCAP include:

•

Capacitive touch applications

High-resolution period and duty cycle measurements of pulse train cycles

Instantaneous speed measurements

Instantaneous frequency measurements

Voltage measurements across an isolation boundary

Distance measurement (sonar) and scanning

The HRCAP module features include:

•

Pulse width capture in either non-high-resolution or high-resolution modes

Difference (Delta) mode pulse width capture

Typical high-resolution capture on the order of 300 ps resolution on each edge

Interrupt on either falling or rising edge

Continuous mode capture of pulse widths in 2-deep buffer

Calibration logic for precision high-resolution capture

All of the above resources are dedicated to a single input pin

HRCAP calibration software library supplied by TI is used for both calibration and calculating fractional pulse

widths

The HRCAP module includes one capture channel in addition to a high-resolution calibration block, which

connects internally to the last available ePWMxA HRPWM channel when calibrating (that is, if there are eight

ePWMs with HRPWM capability, it will be HRPWM8A).

Each HRCAP channel has the following independent key resources:

•

Dedicated input capture pin

16-bit HRCAP clock which is either equal to the PLL2 output frequency (asynchronous to SYSCLK2) or

SYSCLKOUT

•

High-resolution pulse width capture in a 2-deep buffer

HRCAP Calibration Logic

EPWMx

EPWMxA

HRPWM

HRCAPxENCLK

SYSCLKOUT

PLL2CLK

HRCAPx

Module

GPIO

Mux

HRCAP Calibration Signal (Internal)

PIE

HRCAPxINTn

HRCAPx

Figure 8-52. HRCAP Functional Block Diagram

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TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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Table 8-36. HRCAP Registers

SIZE

(×16)

NAME

HRCAP1

HRCAP2

HRCAP3

HRCAP4

DESCRIPTION

HCCTL

0x6AC0

0x6AC1

0x6AC2

0x6AC3

0x6AC4

0x6AE0

0x6AE1

0x6AE2

0x6AE3

0x6AE4

0x6C80

0x6C81

0x6C82

0x6C83

0x6C84

0x6CA0

0x6CA1

0x6CA2

0x6CA3

0x6CA4

1

HRCAP Control Register⁽¹⁾

HCIFR

HRCAP Interrupt Flag Register

HRCAP Interrupt Clear Register⁽¹⁾

HRCAP Interrupt Force Register⁽¹⁾

HRCAP 16-bit Counter Register

HCICLR

HCIFRC

HCCOUNTER

HRCAP Capture Counter on Rising Edge

0 Register

HCCAPCNTRISE0

HCCAPCNTFALL0

HCCAPCNTRISE1

HCCAPCNTFALL1

0x6AD0

0x6AD2

0x6AD8

0x6ADA

0x6AF0

0x6AF2

0x6AF8

0x6AFA

0x6C90

0x6C92

0x6C98

0x6C9A

0x6CB0

0x6CB2

0x6CB8

0x6CBA

1

HRCAP Capture Counter on

Falling Edge 0 Register

HRCAP Capture Counter on Rising Edge

1 Register

HRCAP Capture Counter on

Falling Edge 1 Register

(1) Registers that are EALLOW-protected.

8.9.12.1 HRCAP Electrical Data/Timing

8.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements

MIN

NOM

MAX UNIT

t_c(HCCAPCLK)

t_w(HRCAP)

Cycle time, HRCAP capture clock

Pulse width, HRCAP capture

HRCAP step size⁽²⁾

8.333

10.204

ns

ps

(1)

7t_c(HCCAPCLK)

300

(1) The listed minimum pulse width does not take into account the limitation that all relevant HCCAP registers must be read and RISE/

FALL event flags cleared within the pulse width to ensure valid capture data.

(2) HRCAP step size will increase with low voltage and high temperature and decrease with high voltage and low temperature.

Applications that use the HRCAP in high-resolution mode should use the HRCAP calibration functions to dynamically calibrate for

varying operating conditions.

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TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)

The device contains up to two enhanced quadrature encoder (eQEP) modules. Table 8-37 provides a summary

of the eQEP registers.

Table 8-37. eQEP Control and Status Registers

eQEP1

SIZE(×16)/

#SHADOW

eQEP1

ADDRESS

eQEP2

ADDRESS

NAME

QPOSCNT

REGISTER DESCRIPTION

0x6B00

0x6B02

0x6B04

0x6B06

0x6B08

0x6B0A

0x6B0C

0x6B0E

0x6B10

0x6B12

0x6B13

0x6B14

0x6B15

0x6B16

0x6B17

0x6B18

0x6B19

0x6B1A

0x6B1B

0x6B1C

0x6B1D

0x6B1E

0x6B1F

0x6B20

0x6B40

0x6B42

0x6B44

0x6B46

0x6B48

0x6B4A

0x6B4C

0x6B4E

0x6B50

0x6B52

0x6B53

0x6B54

0x6B55

0x6B56

0x6B57

0x6B58

0x6B59

0x6B5A

0x6B5B

0x6B5C

0x6B5D

0x6B5E

0x6B5F

0x6B60

2/0

2/1

2/0

1/0

eQEP Position Counter

QPOSINIT

QPOSMAX

QPOSCMP

QPOSILAT

QPOSSLAT

QPOSLAT

QUTMR

eQEP Initialization Position Count

eQEP Maximum Position Count

eQEP Position-compare

eQEP Index Position Latch

eQEP Strobe Position Latch

eQEP Position Latch

eQEP Unit Timer

QUPRD

eQEP Unit Period Register

eQEP Watchdog Timer

QWDTMR

QWDPRD

QDECCTL

QEPCTL

QCAPCTL

QPOSCTL

QEINT

eQEP Watchdog Period Register

eQEP Decoder Control Register

eQEP Control Register

eQEP Capture Control Register

eQEP Position-compare Control Register

eQEP Interrupt Enable Register

eQEP Interrupt Flag Register

eQEP Interrupt Clear Register

eQEP Interrupt Force Register

eQEP Status Register

QFLG

QCLR

QFRC

QEPSTS

QCTMR

eQEP Capture Timer

QCPRD

eQEP Capture Period Register

eQEP Capture Timer Latch

eQEP Capture Period Latch

QCTMRLAT

QCPRDLAT

0x6B21 to

0x6B3F

0x6B61 to

0x6B7F

Reserved

31/0

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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Figure 8-53 shows the block diagram of the eQEP module.

System Control

Registers

To CPU

EQEPxENCLK

SYSCLKOUT

QCPRD

QCAPCTL

16

QCTMR

16

Quadrature

Capture

Unit

QCTMRLAT

QCPRDLAT

(QCAP)

QUTMR

QUPRD

QWDTMR

QWDPRD

Registers

Used by

Multiple Units

32

16

QEPCTL

QEPSTS

QFLG

UTOUT

QWDOG

UTIME

QDECCTL

16

WDTOUT

EQEPxAIN

EQEPxBIN

EQEPxIIN

EQEPxA/XCLK

EQEPxB/XDIR

EQEPxI

QCLK

QDIR

QI

EQEPxINT

16

PIE

Position Counter/

Control Unit

(PCCU)

EQEPxIOUT

EQEPxIOE

EQEPxSIN

EQEPxSOUT

EQEPxSOE

Quadrature

Decoder

(QDU)

QS

GPIO

MUX

QPOSLAT

QPOSSLAT

QPOSILAT

PHE

PCSOUT

EQEPxS

32

16

QPOSCNT

QPOSINIT

QPOSMAX

QEINT

QFRC

QPOSCMP

QCLR

QPOSCTL

Enhanced QEP (eQEP) Peripheral

Figure 8-53. eQEP Functional Block Diagram

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TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.13.1 eQEP Electrical Data/Timing

Section 8.9.13.1.1 shows the eQEP timing requirement and Section 8.9.13.1.2 shows the eQEP switching

characteristics.

8.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements

MIN⁽¹⁾

MAX

UNIT

Asynchronous⁽²⁾/Synchronous

With input qualifier

2t_c(SCO)

t_w(QEPP)

QEP input period

cycles

2[1t_c(SCO)+ t_w(IQSW)

]

Asynchronous⁽²⁾/Synchronous

2t_c(SCO)

2t_c(SCO)+t_w(IQSW)

2t_c(SCO)

t_w(INDEXH)

t_w(INDEXL)

t_w(STROBH)

t_w(STROBL)

QEP Index Input High time

QEP Index Input Low time

QEP Strobe High time

QEP Strobe Input Low time

cycles

With input qualifier

Asynchronous⁽²⁾/Synchronous

With input qualifier

2t_c(SCO)+ t_w(IQSW)

2t_c(SCO)

2t_c(SCO)+ t_w(IQSW)

2t_c(SCO)

Asynchronous⁽²⁾/Synchronous

With input qualifier

Asynchronous⁽²⁾/Synchronous

With input qualifier

2t_c(SCO)+t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

(2) Refer to the TMS320F2806x MCUs Silicon Errata for limitations in the asynchronous mode.

8.9.13.1.2 eQEP Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

4t_c(SCO)

6t_c(SCO)

UNIT

cycles

t_d(CNTR)xin

Delay time, external clock to counter increment

t_{d(PCS-OUT)QEP}

Delay time, QEP input edge to position compare sync output

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8.9.14 JTAG Port

On the 2806x device, the JTAG port is reduced to five pins ( TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS, and

TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in

Figure 8-54. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/

XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device

during emulation/debug because this pin will be needed for the TCK function.

Note

In 2806x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board

design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of

the JTAG pin function. Any circuitry connected to these pins should not prevent the debug probe from

driving (or being driven by) the JTAG pins for successful debug.

TRST = 0: JTAG Disabled (GPIO Mode)

TRST = 1: JTAG Mode

TRST

XCLKIN

GPIO38_in

TCK

TCK/GPIO38

GPIO38_out

C28x

Core

GPIO37_in

TDO

TDO/GPIO37

1

0

GPIO37_out

GPIO36_in

1

0

TMS

TMS/GPIO36

TDI/GPIO35

1

GPIO36_out

GPIO35_in

1

0

TDI

1

GPIO35_out

Figure 8-54. JTAG/GPIO Multiplexing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.15 General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to

providing individual pin bit-banging I/O capability.

The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to

enable 32-bit operations on the registers (along with 16-bit operations). Table 8-38 shows the GPIO register

mapping.

Table 8-38. GPIO Registers

NAME

ADDRESS

SIZE (×16)

DESCRIPTION

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

GPACTRL

GPAQSEL1

GPAQSEL2

GPAMUX1

GPAMUX2

GPADIR

0x6F80

0x6F82

0x6F84

0x6F86

0x6F88

0x6F8A

0x6F8C

0x6F90

0x6F92

0x6F94

0x6F96

0x6F98

0x6F9A

0x6F9C

0x6FB6

0x6FBA

2

GPIO A Control Register (GPIO0 to 31)

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPIO A MUX 1 Register (GPIO0 to 15)

GPIO A MUX 2 Register (GPIO16 to 31)

GPIO A Direction Register (GPIO0 to 31)

GPIO A Pullup Disable Register (GPIO0 to 31)

GPIO B Control Register (GPIO32 to 44)

GPIO B Qualifier Select 1 Register (GPIO32 to 44)

GPIO B Qualifier Select 2 Register

GPAPUD

GPBCTRL

GPBQSEL1

GPBQSEL2

GPBMUX1

GPBMUX2

GPBDIR

GPIO B MUX 1 Register (GPIO32 to 44)

GPIO B MUX 2 Register (GPIO50 to 58)

GPIO B Direction Register (GPIO32 to 44)

GPIO B Pullup Disable Register (GPIO32 to 44)

Analog, I/O mux 1 register (AIO0 to AIO15)

Analog, I/O Direction Register (AIO0 to AIO15)

GPBPUD

AIOMUX1

AIODIR

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT

0x6FC0

0x6FC2

0x6FC4

0x6FC6

0x6FC8

0x6FCA

0x6FCC

0x6FCE

0x6FD8

0x6FDA

0x6FDC

0x6FDE

2

GPIO A Data Register (GPIO0 to 31)

GPASET

GPIO A Data Set Register (GPIO0 to 31)

GPIO A Data Clear Register (GPIO0 to 31)

GPIO A Data Toggle Register (GPIO0 to 31)

GPIO B Data Register (GPIO32 to 44)

GPACLEAR

GPATOGGLE

GPBDAT

GPBSET

GPIO B Data Set Register (GPIO32 to 44)

GPIO B Data Clear Register (GPIO32 to 44)

GPIO B Data Toggle Register (GPIO32 to 44)

Analog I/O Data Register (AIO0 to AIO15)

Analog I/O Data Set Register (AIO0 to AIO15)

Analog I/O Data Clear Register (AIO0 to AIO15)

Analog I/O Data Toggle Register (AIO0 to AIO15)

GPBCLEAR

GPBTOGGLE

AIODAT

AIOSET

AIOCLEAR

AIOTOGGLE

GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL

GPIOLPMSEL

0x6FE0

0x6FE1

0x6FE2

0x6FE8

1

2

XINT1 GPIO Input Select Register (GPIO0 to 31)

XINT2 GPIO Input Select Register (GPIO0 to 31)

XINT3 GPIO Input Select Register (GPIO0 to 31)

LPM GPIO Select Register (GPIO0 to 31)

Note

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and

GPxQSELn registers occurs to when the action is valid.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Table 8-39. GPIOA MUX

DEFAULT AT RESET

PRIMARY I/O

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

FUNCTION^{(1) (2)}

GPAMUX1 REGISTER

(GPAMUX1 BITS = 00)

(GPAMUX1 BITS = 01)

(GPAMUX1 BITS = 10)

(GPAMUX1 BITS = 11)

BITS

1-0

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

EPWM1A (O)

EPWM1B (O)

EPWM2A (O)

EPWM2B (O)

EPWM3A (O)

EPWM3B (O)

EPWM4A (O)

EPWM4B (O)

EPWM5A (O)

EPWM5B (O)

EPWM6A (O)

EPWM6B (O)

TZ1 (I)

Reserved

COMP1OUT (O)

Reserved

3-2

5-4

Reserved

7-6

SPISOMIA (I/O)

Reserved

COMP2OUT (O)

Reserved

9-8

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

SPISIMOA (I/O)

EPWMSYNCI (I)

SCIRXDA (I)

Reserved

ECAP1 (I/O)

EPWMSYNCO (O)

ECAP2 (I/O)

ADCSOCAO (O)

ECAP3 (I/O)

SCITXDB (O)

Reserved

ADCSOCBO (O)

ECAP1 (I/O)

SCIRXDB (I)

SCITXDA (O)

Reserved

SPISIMOB (I/O)

SPISOMIB (I/O)

SPICLKB (I/O)

SPISTEB (I/O)

TZ2 (I)

TZ3 (I)

SCITXDB (O)

SCIRXDB (I)

ECAP2 (I/O)

GPAMUX2 REGISTER

BITS

(GPAMUX2 BITS = 00)

(GPAMUX2 BITS = 01)

(GPAMUX2 BITS = 10)

(GPAMUX2 BITS = 11)

1-0

GPIO16

GPIO17

SPISIMOA (I/O)

SPISOMIA (I/O)

SPICLKA (I/O)

SPISTEA (I/O)

EQEP1A (I)

Reserved

TZ2 (I)

3-2

TZ3 (I)

5-4

GPIO18

SCITXDB (O)

SCIRXDB (I)

MDXA (O)

XCLKOUT (O)

ECAP1 (I/O)

COMP1OUT (O)

COMP2OUT (O)

SCITXDB (O)

SCIRXDB (I)

SPISIMOB (I/O)

SPISOMIB (I/O)

SPICLKB (I/O)

SPISTEB (I/O)

TZ2 (I)

7-6

GPIO19/XCLKIN

GPIO20

9-8

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

GPIO21

EQEP1B (I)

MDRA (I)

GPIO22

EQEP1S (I/O)

EQEP1I (I/O)

ECAP1 (I/O)

ECAP2 (I/O)

ECAP3 (I/O)

HRCAP2 (I)

MCLKXA (I/O)

MFSXA (I/O)

EQEP2A⁽³⁾(I)

EQEP2B⁽³⁾(I)

EQEP2I⁽³⁾(I/O)

EQEP2S⁽³⁾(I/O)

SDAA (I/OD)

SCLA (I/OD)

EQEP2I⁽³⁾(I/O)

EQEP2S⁽³⁾(I/O)

GPIO23

GPIO24

GPIO25

GPIO26⁽⁴⁾

GPIO27⁽⁴⁾

GPIO28

SCIRXDA (I)

SCITXDA (O)

CANRXA (I)

CANTXA (O)

GPIO29

TZ3 (I)

GPIO30

EPWM7A (O)

EPWM8A (O)

GPIO31

(1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of

the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(2) I = Input, O = Output, OD = Open Drain

(3) The eQEP2 peripheral is not available on the 80-pin PN or PFP package.

(4) To enable the USB functionality on GPIO26 (USB0DP, positive differential half of the USB signal) and GPIO27 (USB0DM, negative

differential half of the USB signal), set the USBIOEN bit in the GPACTRL2 register. Depending on your USB application, additional pins

may be required to maintain compliance with the USB 2.0 Specification. For more information, see the Universal Serial Bus (USB)

Controller chapter of the TMS320x2806x Technical Reference Manual .

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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Table 8-40. GPIOB MUX

DEFAULT AT RESET

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

PRIMARY I/O

FUNCTION^{(1) (2)}

GPBMUX1 REGISTER

BITS

(GPBMUX1 BITS = 00)

(GPBMUX1 BITS = 01)

(GPBMUX1 BITS = 10)

(GPBMUX1 BITS = 11)

1-0

GPIO32

GPIO33

SDAA (I/OD)

SCLA (I/OD)

COMP2OUT (O)

Reserved

EPWMSYNCI (I)

EPWMSYNCO (O)

Reserved

ADCSOCAO (O)

ADCSOCBO (O)

COMP3OUT (O)

Reserved

3-2

5-4

GPIO34

7-6

GPIO35 (TDI)

GPIO36 (TMS)

GPIO37 (TDO)

GPIO38/XCLKIN (TCK)

GPIO39

Reserved

9-8

Reserved

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

GPIO40⁽³⁾

EPWM7A (O)

EPWM7B (O)

EPWM8A (O)

EPWM8B (O)

MFSRA (I/O)

Reserved

SCITXDB (O)

SCIRXDB (I)

TZ1 (I)

Reserved

GPIO41⁽³⁾

Reserved

GPIO42⁽³⁾

COMP1OUT (O)

COMP2OUT (O)

EPWM7B (O)

Reserved

GPIO43⁽³⁾

TZ2 (I)

GPIO44⁽³⁾

SCIRXDB (I)

Reserved

GPBMUX2 REGISTER

BITS

(GPBMUX2 BITS = 00)

(GPBMUX2 BITS = 01)

(GPBMUX2 BITS = 10)

(GPBMUX2 BITS = 11)

1-0

Reserved

GPIO50⁽³⁾

GPIO51⁽³⁾

GPIO52⁽³⁾

GPIO53⁽³⁾

GPIO54⁽³⁾

GPIO55⁽³⁾

GPIO56⁽³⁾

GPIO57⁽³⁾

GPIO58⁽³⁾

Reserved

TZ1 (I)

3-2

5-4

EQEP1A (I)

EQEP1B (I)

EQEP1S (I/O)

EQEP1I (I/O)

SPISIMOA (I/O)

SPISOMIA (I/O)

SPICLKA (I/O)

SPISTEA (I/O)

MCLKRA (I/O)

Reserved

MDXA (O)

MDRA (I)

7-6

TZ2 (I)

9-8

MCLKXA (I/O)

MFSXA (I/O)

EQEP2A (I)

EQEP2B (I)

EQEP2I (I/O)

EQEP2S (I/O)

SCITXDB (O)

Reserved

TZ3 (I)

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

HRCAP1 (I)

HRCAP2 (I)

HRCAP3 (I)

HRCAP4 (I)

EPWM7A (O)

Reserved

(1) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of

the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(2) I = Input, O = Output, OD = Open Drain

(3) This pin is not available in the 80-pin PN or PFP package.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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Table 8-41. Analog MUX for 100-Pin PZ and 100-Pin PZP Packages

DEFAULT AT RESET⁽¹⁾

PERIPHERAL SELECTION 2 AND

AIOx AND PERIPHERAL SELECTION 1

PERIPHERAL SELECTION 3

AIOMUX1 REGISTER BITS

AIOMUX1 BITS = 0,x

ADCINA0 (I)

ADCINA1 (I)

AIO2 (I/O)

AIOMUX1 BITS = 1,x

ADCINA0 (I)

1-0

3-2

ADCINA1 (I)

5-4

ADCINA2 (I), COMP1A (I)

ADCINA3 (I)

7-6

ADCINA3 (I)

AIO4 (I/O)

9-8

ADCINA4 (I), COMP2A (I)

ADCINA5 (I)

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

ADCINA5 (I)

AIO6 (I/O)

ADCINA6 (I), COMP3A (I)

ADCINA7 (I)

ADCINB0 (I)

ADCINB1 (I)

AIO10 (I/O)

ADCINB3 (I)

AIO12 (I/O)

ADCINB5 (I)

AIO14 (I/O)

ADCINB7 (I)

ADCINB0 (I)

ADCINB1 (I)

ADCINB2 (I), COMP1B (I)

ADCINB3 (I)

ADCINB4 (I), COMP2B (I)

ADCINB5 (I)

ADCINB6 (I), COMP3B (I)

ADCINB7 (I)

(1) I = Input, O = Output

Table 8-42. Analog MUX for 80-Pin PN and 80-Pin PFP Packages

DEFAULT AT RESET⁽¹⁾

PERIPHERAL SELECTION 2 AND

PERIPHERAL SELECTION 3

AIOx AND PERIPHERAL SELECTION 1

AIOMUX1 REGISTER BITS

AIOMUX1 BITS = 0,x

ADCINA0 (I), V_REFHI(I)

ADCINA1 (I)

AIO2 (I/O)

–

AIOMUX1 BITS = 1,x

ADCINA0 (I), V_REFHI(I)

ADCINA1 (I)

1-0

3-2

5-4

ADCINA2 (I), COMP1A (I)

–

7-6

9-8

AIO4 (I/O)

ADCINA5 (I)

AIO6 (I/O)

–

ADCINA4 (I), COMP2A (I)

ADCINA5 (I)

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

ADCINA6 (I), COMP3A (I)

–

ADCINB0 (I)

ADCINB1 (I)

AIO10 (I/O)

–

ADCINB0 (I)

ADCINB1 (I)

ADCINB2 (I), COMP1B (I)

–

AIO12 (I/O)

ADCINB5 (I)

AIO14 (I/O)

–

ADCINB4 (I), COMP2B (I)

ADCINB5 (I)

ADCINB6 (I), COMP3B (I)

–

(1) I = Input, O = Output

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from

four choices:

•

Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at

reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after

synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the

input is allowed to change.

•

The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in

groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the input

signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when

ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode).

No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not

required (synchronization is performed within the peripheral).

Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input

signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will

default to either a 0 or 1 state, depending on the peripheral.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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GPIOXINT1SEL

GPIOLMPSEL

LPMCR0

GPIOXINT2SEL

GPIOXINT3SEL

External Interrupt

MUX

Low-Power

Modes Block

PIE

Asynchronous

path

GPxDAT (read)

GPxQSEL1/2

GPxCTRL

GPxPUD

N/C

00

01

Peripheral 1 Input

Peripheral 2 Input

Input

Internal

Pullup

Qualification

10

11

Peripheral 3 Input

GPxTOGGLE

Asynchronous path

GPIOx pin

GPxCLEAR

GPxSET

00

01

GPxDAT (latch)

Peripheral 1 Output

10

11

Peripheral 2 Output

Peripheral 3 Output

High Impedance

Output Control

GPxDIR (latch)

00

01

Peripheral 1 Output Enable

Peripheral 2 Output Enable

0 = Input, 1 = Output

XRS

10

11

Peripheral 3 Output Enable

= Default at Reset

GPxMUX1/2

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular

GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the Systems Control and Interrupts

chapter of the TMS320x2806x Technical Reference Manual for pin-specific variations.

Figure 8-55. GPIO Multiplexing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.15.1 GPIO Electrical Data/Timing

8.9.15.1.1 GPIO Output Timing

8.9.15.1.1.1 General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

13⁽¹⁾

22.5

UNIT

ns

t_r(GPO)

t_f(GPO)

f_GPO

Rise time, GPIO switching low to high

Fall time, GPIO switching high to low

Toggling frequency

All GPIOs

ns

MHz

(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Section 8.9.15.1.1.1 are applicable for a 40-pF load on

I/O pins.

GPIO

t

r(GPO)

t

f(GPO)

Figure 8-56. General-Purpose Output Timing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

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8.9.15.1.2 GPIO Input Timing

8.9.15.1.2.1 General-Purpose Input Timing Requirements

MIN

1t_c(SCO)

MAX

UNIT

cycles

QUALPRD = 0

t_w(SP)

Sampling period

QUALPRD ≠ 0

2t_c(SCO)* QUALPRD

t_w(SP)* (n⁽¹⁾– 1)

2t_c(SCO)

t_w(IQSW)

Input qualifier sampling window

Pulse duration, GPIO low/high

Synchronous mode

With input qualifier

(2)

t_w(GPI)

t_w(IQSW)+ t_w(SP)+ 1t_c(SCO)

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For t_w(GPI), pulse width is measured from V_ILto V_ILfor an active-low signal and V_IHto V_IHfor an active-high signal.

(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

0

1

0

1

t_w(SP)

Sampling Period determined

by GPxCTRL[QUALPRD]^(B)

t_w(IQSW)

[(SYSCLKOUT cycle * 2 * QUALPRD) * 5^(C)

]

Sampling Window

SYSCLKOUT

QUALPRD = 1

(SYSCLKOUT/2)

(D)

Output From

Qualifier

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. The QUALPRD bit

field value can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is one SYSCLKOUT cycle. For any other value "n", the

qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).

B. The qualification period selected through the GPxCTRL register applies to groups of eight GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other

words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure five sampling periods for detection to

occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.

Figure 8-57. Sampling Mode

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TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

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8.9.15.1.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier

configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.

Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0

Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0

In the preceding samples, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.

Sampling period = SYSCLKOUT cycle, if QUALPRD = 0

In a given sampling window, either three or six samples of the input signal are taken to determine the validity of

the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using three samples

Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0

Case 2:

Qualification using six samples

Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0

SYSCLK

GPIOxn

t_w(GPI)

Figure 8-58. General-Purpose Input Timing

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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V_DDIO

> 1 MS

2 pF

V_SS

Figure 8-59. Input Resistance Model for a GPIO Pin With an Internal Pullup

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.15.1.4 Low-Power Mode Wakeup Timing

Section 8.9.15.1.4.1 shows the timing requirements, Section 8.9.15.1.4.2 shows the switching characteristics,

and Figure 8-60 shows the timing diagram for IDLE mode.

8.9.15.1.4.1 IDLE Mode Timing Requirements

MIN⁽¹⁾

2t_c(SCO)

MAX

UNIT

Without input qualifier

With input qualifier

t_w(WAKE-INT)

Pulse duration, external wake-up signal

cycles

5t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

8.9.15.1.4.2 IDLE Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, external wake signal to program execution resume ⁽²⁾

cycles

•

Wake up from flash

Flash module in active state

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

20t_c(SCO)

cycles

–

20t_c(SCO)+ t_w(IQSW)

1050t_c(SCO)

t_d(WAKE-IDLE)

Wake up from flash

Flash module in sleep state

–

1050t_c(SCO)+ t_w(IQSW)

20t_c(SCO)

•

Wake up from SARAM

20t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Section 8.9.15.1.2.1.

(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up signal) involves additional latency.

t

d(WAKE−IDLE)

Address/Data

(internal)

XCLKOUT

t

w(WAKE−INT)

WAKE INT^(A)(B)

A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK cycles

(minimum) is needed before the wake-up signal could be asserted.

B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at

least four OSCCLK cycles have elapsed.

Figure 8-60. IDLE Entry and Exit Timing

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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8.9.15.1.4.3 STANDBY Mode Timing Requirements

MIN MAX

3t_c(OSCCLK)

UNIT

Without input qualification

Pulse duration, external

t_w(WAKE-INT)

cycles

(2 + QUALSTDBY) *

t_c(OSCCLK)

With input qualification⁽¹⁾

wake-up signal

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

8.9.15.1.4.4 STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, IDLE instruction

executed to XCLKOUT low

t_d(IDLE-XCOL)

32t_c(SCO)

45t_c(SCO)cycles

cycles

Delay time, external wake signal to program execution

resume⁽¹⁾

•

Wake up from flash

Flash module in active state

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

100t_c(SCO)

cycles

–

100t_c(SCO)+ t_w(WAKE-INT)

t_d(WAKE-STBY)

•

Wake up from flash

Flash module in sleep state

1125t_c(SCO)

1125t_c(SCO)+ t_w(WAKE-INT)

100t_c(SCO)

cycles

–

•

Wake up from SARAM

100t_c(SCO)+ t_w(WAKE-INT)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up signal) involves additional latency.

(C)

(F)

(A)

(B)

(D)(E)

(G)

Device

Status

STANDBY

Normal Execution

Flushing Pipeline

Wake-up

Signal^(H)

t

w(WAKE-INT)

t

d(WAKE-STBY)

X1/X2 or

XCLKIN

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. After

the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

D. The external wake-up signal is driven active.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal

must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device

may not exit low-power mode for subsequent wake-up pulses.

F. After a latency period, the STANDBY mode is exited.

G. Normal execution resumes. The device will respond to the interrupt (if enabled).

H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at

least four OSCCLK cycles have elapsed.

Figure 8-61. STANDBY Entry and Exit Timing Diagram

8.9.15.1.4.5 HALT Mode Timing Requirements

MIN

t_oscst+ 2t_c(OSCCLK)

t_oscst+ 8t_c(OSCCLK)

MAX

UNIT

cycles

t_w(WAKE-GPIO)

t_w(WAKE-XRS)

Pulse duration, GPIO wake-up signal

Pulse duration, XRS wake-up signal

8.9.15.1.4.6 HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

45t_c(SCO)

1

UNIT

cycles

ms

t_d(IDLE-XCOL)

t_p

Delay time, IDLE instruction executed to XCLKOUT low

PLL lock-up time

32t_c(SCO)

Delay time, PLL lock to program execution resume

•

Wake up from flash

– Flash module in sleep state

1125t_c(SCO)

cycles

t_d(WAKE-HALT)

•

Wake up from SARAM

35t_c(SCO)

cycles

(C)

(F)

(A)

(H)

(B)

(G)

(D)(E)

Device

Status

HALT

Flushing Pipeline

PLL Lock-up Time

Normal

Execution

Wake-up Latency

GPIOn^(I)

t

)

d(WAKE−HALT

t

w(WAKE-GPIO)

t_p

X1/X2 or

XCLKIN

Oscillator Start-up Time

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off

and the CLKIN to the core is stopped:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,

the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to

keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. This is done by writing to the

appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed

before the wake-up signal could be asserted.

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TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

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D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence

is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal

during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wake-up procedure, care should be

taken to maintain a low-noise environment before entering and during HALT mode.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal

must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device

may not exit low-power mode for subsequent wake-up pulses.

F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.

G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.

H. Normal operation resumes.

I. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at

least four OSCCLK cycles have elapsed.

Figure 8-62. HALT Mode Wakeup Using GPIOn

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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8.9.16 Universal Serial Bus (USB)

8.9.16.1 USB Electrical Data/Timing

8.9.16.1.1 USB Input Ports DP and DM Timing Requirements

V_CC

MIN

0.8

MAX

UNIT

V

V(CM)

Z(IN)

VCRS

V_IL

Differential input common mode range

Input impedance

2.5

300

1.3

kΩ

V

Crossover voltage

2.0

Static SE input logic-low level

Static SE input logic-high level

Differential input voltage

0.8

V

V_IH

2.0

0.2

V

VDI

V

8.9.16.1.2 USB Output Ports DP and DM Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

D+, D– single-ended

D+, D– impedance

TEST CONDITIONS

V_CC

MIN

MAX

UNIT

V

V_OH

USB 2.0 load conditions

2.8

0

3.6

0.3

50

V_OL

USB 2.0 load conditions

V

Z(DRV)

28

Ω

Full speed, differential, C_L= 50 pF,

10%/90%, Rpu on D+

t_r

t_f

Rise time

Fall time

4

20

ns

Full speed, differential, C_L= 50 pF,

10%/90%, Rpu on D+

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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9 Applications, Implementation, and Layout

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 TI Reference Design

The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,

and connectivity. Created by TI experts to help you jump start your system design, all reference designs include

schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download

designs at the Select TI reference designs page.

Digitally Controlled Non-Isolated DC/DC Buck Converter Reference Design

This design implements a non-isolated DC/DC buck converter that is digitally controlled using a C2000

microcontroller. The main purpose of this design is to evaluate the powerSUITE Digital Power Software tools.

The design consists of two separate boards: 1) Digital Power BoosterPack^™Plug-in Module and 2) C2000

F28069M LaunchPad^™Development Kit or C2000 F28377S LaunchPad Development Kit.

672W Highly Integrated Reference Design for Automotive Bidirectional 48V-12V Converter

Today's automotive power consumption is 3KW, which will increase to 10KW in the next 5 years. A 12-V battery

is unable to provide that much power. The 48-12V bidirectional convertor provides a high-power requirement

solution with two phases, each capable of running 28 A. This solution allows bidirectional current control of both

phases using a C2000 control stick and firmware OCP and OVP. The 48-12V bidirectional converter removes the

voltage conditioner need and distributes loads more evenly. The 48-V battery is used to power high-torque

motors and other high-power components, such as A/C compressors and EPS, with no change to 12-V battery

loads.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

10 Device and Documentation Support

10.1 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320^™MCU devices and support tools. Each TMS320 MCU commercial family member has one of three

prefixes: TMX, TMP, or TMS (for example, TMS320F28069). Texas Instruments recommends two of three

possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages

of product development from engineering prototypes (with TMX for devices and TMDX for tools) to fully qualified

production devices/tools (with TMS for devices and TMDS for tools).

Device development evolutionary flow:

TMX

TMP

Experimental device that is not necessarily representative of the final device's electrical specifications

Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability

verification

TMS

Fully qualified production device

Support tool development evolutionary flow:

TMDX

TMDS

Development-support product that has not yet completed Texas Instruments internal qualification testing

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, PZP) and temperature range (for example, S). Figure 10-1 provides a legend for reading the

complete device name for any family member.

For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your TI

sales representative.

For additional description of the device nomenclature markings on the die, see the TMS320F2806x MCUs

Silicon Errata.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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A. USB is present on TMS320F2806xU, TMS320F2806xM, and TMS320F2806xF devices.

B. TMS320F2806xM devices are InstaSPIN-MOTION-enabled MCUs. TMS320F2806xF devices are InstaSPIN-FOC-enabled MCUs. For

more information, see Section 10.3 for a list of InstaSPIN Technical Reference Manuals.

C. For more information on peripheral, temperature, and package availability for a specific device, see Table 5-1.

Figure 10-1. Device Nomenclature

10.2 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of

the device, generate code, and develop solutions are listed below. To view all available tools and software for

C2000™ real-time control MCUs, visit the C2000 real-time control MCUs – Design & development page.

Development Tools

C2000 F28069M LaunchPad™ development kit

LAUNCHXL-F28069M is a low cost evaluation and development tool for the F2806x series as well as the

InstaSPIN-FOC and InstaSPIN-MOTION enabled F2806x series in the TI MCU LaunchPad ecosystem which is

compatible with various plug-on BoosterPacks. This extended version of the LaunchPad supports the connection

of two BoosterPacks. The LaunchPad provides a standardized and easy to use platform to use while developing

your next application.

F28069 controlCARD

The C2000 controlCARDs from Texas Instruments are ideal products for OEMs to use for initial software

development and short-run builds for system prototypes, test stands, and many other projects that require easy

access to high-performance controllers. The controlCARDs are complete board-level modules that use an

industry-standard DIMM form factor to provide a low-profile, single-board controller solution. All of the C2000

controlCARDs use the same 100-pin connector footprint to provide the analog and digital I/Os onboard controller

and are completely interchangeable. The host system must provide only a single 5-V power rail to the

controlCARD for it to function fully.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

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F28069 Experimenter Kit

The C2000 experimenter kits from Texas Instruments are ideal products for OEMs to use for initial device

exploration and testing. The F28069 Experimenter Kit has a docking station that features onboard USB JTAG

emulation, access to all controlCARD signals, breadboard areas, and RS-232 and JTAG connectors. Each kit

contains an F28069 controlCARD. The controlCARD is a complete board-level module that uses an industry-

standard DIMM form factor to provide a low-profile, single-board controller solution. The kit is complete with

Code Composer Studio IDE and USB cable.

Software Tools

C2000Ware for C2000 MCUs

C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation

designed to minimize software development time. From device-specific drivers and libraries to device peripheral

examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.

Code Composer Studio^™(CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and

Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug embedded

applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger,

profiler, and many other features. The intuitive IDE provides a single user interface taking the user through each

step of the application development flow. Familiar tools and interfaces let users get started faster than ever

before. CCS combines the advantages of the Eclipse software framework with advanced embedded debug

capabilities from TI resulting in a compelling feature-rich development environment for embedded developers.

Pin Mux Tool

The Pin Mux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing

settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs.

UniFlash Standalone Flash Tool

UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or scripting

interface.

Models

Various models are available for download from the product Tools & Software pages. These include I/O Buffer

Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all

available models, visit the Models section of the Tools & Software page for each device.

Training

To help assist design engineers in taking full advantage of the C2000 microcontroller features and performance,

TI has developed a variety of training resources. Utilizing the online training materials and downloadable hands-

on workshops provides an easy means for gaining a complete working knowledge of the C2000 microcontroller

family. These training resources have been designed to decrease the learning curve, while reducing

development time, and accelerating product time to market. For more information on the various training

resources, visit the C2000™ real-time control MCUs – Support & training site.

Specific TMS320F2806x hands-on training resources can be found at C2000™ MCU Device Workshops.

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TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

10.3 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper-

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

The current documentation that describes the processor, related peripherals, and other technical collateral is

listed below.

Errata

TMS320F2806x MCUs Silicon Errata describes known advisories on silicon and provides workarounds.

InstaSPIN Technical Reference Manuals

InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide describes the InstaSPIN-FOC and InstaSPIN-

MOTION devices.

TMS320F28069F, TMS320F28068F, TMS320F28062F InstaSPIN-FOC™ Software Technical Reference Manual

describes the TMS320F28069F, TMS320F28068F, and TMS320F28062F InstaSPIN-FOC™ software.

TMS320F28069M, TMS320F28068M InstaSPIN-MOTION™ Software Technical Reference Manual describes

the TMS320F28069M and TMS320F28068M InstaSPIN-MOTION™ software.

CPU User's Guides

TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the

assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This reference

guide also describes emulation features available on these DSPs.

Peripheral Guides and Technical Reference Manuals

C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x

digital signal processors (DSPs).

TMS320x2806x Technical Reference Manual details the integration, the environment, the functional description,

and the programming models for each peripheral and subsystem in the device.

Tools Guides

TMS320C28x Assembly Language Tools v19.6.0.STS User's Guide describes the assembly language tools

(assembler and other tools used to develop assembly language code), assembler directives, macros, common

object file format, and symbolic debugging directives for the TMS320C28x device.

TMS320C28x Optimizing C/C++ Compiler v19.6.0.STS User's Guide describes the TMS320C28x C/C++

compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly

language source code for the TMS320C28x device.

Application Reports

Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor

devices for shipment to end users.

Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime

of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general

engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.

An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS

including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/

output structures and future trends.

Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for

serial programming a device.

Submit Document Feedback 167

Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

10.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

PowerPAD^™, InstaSPIN-MOTION^™, InstaSPIN-FOC^™, TMS320C2000^™, C2000^™, FAST^™, BoosterPack^™,

LaunchPad^™, TMS320^™, Code Composer Studio^™, and TI E2E^™are trademarks of Texas Instruments.

SpinTAC^™are trademarks of LineStream Technologies, Inc.

I2C-bus^®is a registered trademark of NXP B.V. Corporation.

All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

10.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

168 Submit Document Feedback

Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

TMS320F28069, TMS320F28069M, TMS320F28069F, TMS320F28068M, TMS320F28068F

TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063

TMS320F28062, TMS320F28062F

SPRS698I – NOVEMBER 2010 – REVISED FEBRUARY 2021

www.ti.com

11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

For packages with a thermal pad, the MECHANICAL DATA figure shows a generic thermal pad without

dimensions. For the actual thermal pad dimensions that are applicable to this device, see the THERMAL PAD

MECHANICAL DATA figure.

Submit Document Feedback 169

Product Folder Links: TMS320F28069 TMS320F28069M TMS320F28069F TMS320F28068M

TMS320F28068F TMS320F28067 TMS320F28066 TMS320F28065 TMS320F28064 TMS320F28063

TMS320F28062 TMS320F28062F

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMS320F28062PFPQR HTQFP

TMS320F28069FPZTR LQFP

PFP

PZ

80

1000

330.0

24.4

32.4

15.0

16.9

15.0

16.9

1.5

2.0

20.0

24.0

32.0

Q2

100

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMS320F28062PFPQR

TMS320F28069FPZTR

HTQFP

LQFP

PFP

PZ

80

1000

367.0

55.0

100

Pack Materials-Page 2

www.ti.com

MECHANICAL DATA

MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996

PN (S-PQFP-G80)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

60

M

0,08

41

61

40

0,13 NOM

80

21

1

20

Gage Plane

9,50 TYP

0,25

12,20

SQ

11,80

0,05 MIN

0°–7°

14,20

SQ

13,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040135 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996

PZ (S-PQFP-G100)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

75

M

0,08

51

50

76

26

100

0,13 NOM

1

25

12,00 TYP

Gage Plane

14,20

SQ

13,80

0,25

16,20

SQ

0,05 MIN

0°–7°

15,80

1,45

1,35

0,75

0,45

Seating Plane

0,08

1,60 MAX

4040149/B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMS320F28069FPZTR
厂家：	TEXAS INSTRUMENTS
描述：	TMS320F2806x Microcontrollers 微控制器
文件：	总185页 (文件大小：5091K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320F28069FPZTR [TI]

相关型号：

TMS320F28069M

TMS320F28069M-Q1

TMS320F28069MPFPQ

TMS320F28069MPNT

TMS320F28069MPZPQ

TMS320F28069MPZT

TMS320F28069PFPQ

TMS320F28069PFPS

TMS320F28069PNT

TMS320F28069PZA

TMS320F28069PZPQ

TMS320F28069PZPS