TMS320F2809_V03 [TI]
TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors;型号: | TMS320F2809_V03 |
厂家: | TEXAS INSTRUMENTS |
描述: | TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors |
文件: | 总154页 (文件大小:3881K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors
•
•
Three 32-bit CPU timers
Enhanced control peripherals
– Up to 16 PWM outputs
– Up to 6 HRPWM outputs with 150-ps MEP
resolution
– Up to four capture inputs
– Up to two quadrature encoder interfaces
– Up to six 32-bit/six 16-bit timers
Serial port peripherals
– Up to 4 SPI modules
– Up to 2 SCI (UART) modules
– Up to 2 CAN modules
– One Inter-Integrated-Circuit (I2C) bus
12-bit ADC, 16 channels
1 Features
•
High-performance static CMOS technology
– 100 MHz (10-ns cycle time)
– 60 MHz (16.67-ns cycle time)
– Low-power (1.8-V core, 3.3-V I/O) design
JTAG boundary scan support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
High-performance 32-bit CPU (TMS320C28x)
– 16 × 16 and 32 × 32 MAC operations
– 16 × 16 dual MAC
•
•
•
•
– Harvard bus architecture
– Atomic operations
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
On-chip memory
– 2 × 8 channel input multiplexer
– Two sample-and-hold
– Single/simultaneous conversions
– Fast conversion rate:
•
– F2809: 128K × 16 flash, 18K × 16 SARAM
F2808: 64K × 16 flash, 18K × 16 SARAM
F2806: 32K × 16 flash, 10K × 16 SARAM
F2802: 32K × 16 flash, 6K × 16 SARAM
F2801: 16K × 16 flash, 6K × 16 SARAM
F2801x: 16K × 16 flash, 6K × 16 SARAM
– 1K × 16 OTP ROM (flash devices only)
– C2802: 32K × 16 ROM, 6K × 16 SARAM
C2801: 16K × 16 ROM, 6K × 16 SARAM
Boot ROM (4K × 16)
– With software boot modes (via SCI, SPI, CAN,
I2C, and parallel I/O)
– Standard math tables
Clock and system control
– On-chip oscillator
– Watchdog timer module
Any GPIO A pin can be connected to one of the
three external core interrupts
Peripheral Interrupt Expansion (PIE) block that
supports all 43 peripheral interrupts
Endianness: Little endian
128-bit security key/lock
– Protects flash/OTP/L0/L1 blocks
– Prevents firmware reverse-engineering
80 ns - 12.5 MSPS (F2809 only)
160 ns - 6.25 MSPS (280x)
267 ns - 3.75 MSPS (F2801x)
– Internal or external reference
Up to 35 individually programmable, multiplexed
GPIO pins with input filtering
Advanced emulation features
– Analysis and breakpoint functions
– Real-time debug via hardware
Development support includes
– ANSI C/C++ compiler/assembler/linker
– Code Composer Studio™ IDE
– SYS/BIOS
– Digital motor control and digital power software
libraries
Low-power modes and power savings
– IDLE, STANDBY, HALT modes supported
– Disable individual peripheral clocks
Package options
•
•
•
•
•
•
•
•
•
•
– Thin quad flatpack (PZ)
– MicroStar BGA™ (GGM, ZGM)
Temperature options
– A: –40°C to 85°C (PZ, GGM, ZGM)
– S: –40°C to 125°C (PZ, GGM, ZGM)
– Q: –40°C to 125°C (PZ)
•
•
(AEC-Q100 qualification for automotive
applications)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
•
Digital power
2 Applications
•
Motor drive and control
3 Description
The TMS320F2809, TMS320F2809-Q1, TMS320F2808, TMS320F2808-Q1 TMS320F2806, TMS320F2802,
TMS320F2801-Q1, TMS320F28015-Q1, TMS320F28016-Q1, TMS320C2802-Q1, and TMS320C2801 devices,
members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding
control applications.
Throughout this document, TMS320F2809, TMS320F2809-Q1 TMS320F2808, TMS320F2808-Q1
TMS320F2806, TMS320F2802-Q1, TMS320F2801-Q1, TMS320C2802, TMS320C2801, TMS320F28015-Q1,
and TMS320F28016-Q1 are abbreviated as F2809, F2808, F2806, F2802-Q1, F2801-Q1, C2802, C2801,
F28015-Q1, and F28016-Q1, respectively. TMS320F28015-Q1 and TMS320F28016-Q1 are abbreviated as
F2801x. Device Comparison (100-MHz Devices) and Device Comparison (60-MHz Devices) provide a summary
of features for each device.
Device Information
PART NUMBER(1)
TMS320F2809ZGM
PACKAGE
BODY SIZE
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
BGA MicroStar (100)
LQFP (100)
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
10.0 mm × 10.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
TMS320F2808ZGM
TMS320F2806ZGM
TMS320F2802ZGM
TMS320F2801ZGM
TMS320C2802ZGM
TMS320C2801ZGM
TMS320F28016ZGM
TMS320F28015ZGM
TMS320F2809GGM
TMS320F2808GGM
TMS320F2806GGM
TMS320F2802GGM
TMS320F2801GGM
TMS320C2802GGM
TMS320C2801GGM
TMS320F28016GGM
TMS320F28015GGM
TMS320F2809PZ
TMS320F2808PZ
LQFP (100)
TMS320F2806PZ
LQFP (100)
TMS320F2802PZ
LQFP (100)
TMS320F2801PZ
LQFP (100)
TMS320C2802PZ
TMS320C2801PZ
TMS320F28016PZ
TMS320F28015PZ
LQFP (100)
LQFP (100)
LQFP (100)
LQFP (100)
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
4 Functional Block Diagram
Memory Bus
Real-Time JTAG
(TDI, TDO, TRST, TCK,
TMS, EMU0, EMU1)
TINT0
32-bit CPU TIMER 0
TINT1
TINT2
7
32-bit CPU TIMER 1
32-bit CPU TIMER 2
INT14
M0 SARAM
1K x 16
PIE
(96 Interrupts)(A)
M1 SARAM
1K x 16
INT[12:1]
NMI, INT13
L0 SARAM
4K x 16
(0-wait)
External Interrupt
Control
32
4
L1 SARAM(B)
4K x 16
(0-wait)
SCI-A/B
SPI-A/B/C/D
I2C-A
FIFO
FIFO
FIFO
16
2
H0 SARAM(C)
8K x 16
(0-wait)
4
eCAN-A/B (32 mbox)
eQEP1/2
8
GPIOs
(35)
4
ROM
32K x 16 (C2802)
16K x 16 (C2801)
C28x CPU
(100 MHz)
eCAP1/2/3/4
(4 32-bit Timers)
12
6
ePWM1/2/3/4/5/6
(12 PWM Outputs,
6 Trip Zones,
6 16-bit Timers)
FLASH
128K x 16 (F2809)
64K x 16 (F2808)
32K x 16 (F2806)
32K x 16 (F2802)
16K x 16 (F2801)
16K x 16 (F2801x)
SYSCLKOUT
32
System Control
RS
XCLKOUT
XRS
(Oscillator, PLL,
Peripheral Clocking,
Low-Power Modes,
Watchdog)
CLKIN
XCLKIN
X1
OTP(D)
1K x 16
X2
ADCSOCA/B
Boot ROM
4K x 16
(1-wait state)
SOCA/B
12-Bit ADC
16 Channels
Peripheral Bus
Protected by the code-security module.
Copyright © 2016, Texas Instruments Incorporated
A. 43 of the possible 96 interrupts are used on the devices.
B. Not available in F2802, F2801, C2802, and C2801.
C. Not available in F2806, F2802, F2801, C2802, and C2801.
D. The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.
Figure 4-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 8
7 Terminal Configuration and Functions..........................9
7.1 Pin Diagrams.............................................................. 9
7.2 Signal Descriptions................................................... 14
8 Specifications................................................................ 20
8.1 Absolute Maximum Ratings...................................... 20
8.2 ESD Ratings – Automotive....................................... 21
8.3 ESD Ratings – Commercial...................................... 21
8.4 Recommended Operating Conditions.......................21
8.5 Power Consumption Summary................................. 23
8.6 Electrical Characteristics...........................................29
8.7 Thermal Resistance Characteristics for F280x
8.13 Thermal Design Considerations..............................33
8.14 Timing and Switching Characteristics..................... 34
8.15 On-Chip Analog-to-Digital Converter...................... 60
8.16 Migrating From F280x Devices to C280x Devices..66
8.17 ROM Timing (C280x only).......................................67
9 Detailed Description......................................................68
9.1 Brief Descriptions......................................................68
9.2 Peripherals................................................................75
9.3 Memory Maps ........................................................ 108
9.4 Register Map...........................................................116
9.5 Interrupts.................................................................119
9.6 System Control....................................................... 124
9.7 Low-Power Modes Block........................................ 130
10 Applications, Implementation, and Layout............. 131
10.1 TI Design or Reference Design.............................131
11 Device and Documentation Support........................132
11.1 Getting Started......................................................132
11.2 Device and Development Support Tool
100-Ball GGM Package...............................................31
8.8 Thermal Resistance Characteristics for F280x
100-Pin PZ Package................................................... 31
8.9 Thermal Resistance Characteristics for C280x
100-Ball GGM Package...............................................32
8.10 Thermal Resistance Characteristics for C280x
100-Pin PZ Package................................................... 32
8.11 Thermal Resistance Characteristics for F2809
Nomenclature............................................................133
11.3 Tools and Software................................................135
11.4 Documentation Support........................................ 136
11.5 Support Resources............................................... 138
11.6 Trademarks........................................................... 138
11.7 Electrostatic Discharge Caution............................138
11.8 Glossary................................................................138
12 Mechanical, Packaging, and Orderable
100-Ball GGM Package...............................................33
8.12 Thermal Resistance Characteristics for F2809
Information.................................................................. 139
12.1 Packaging Information.......................................... 139
100-Pin PZ Package................................................... 33
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
5 Revision History
Changes from March 11, 2019 to February 3, 2021 (from Revision O (March 2019) to Revision P
(February 2021))
Page
•
•
•
•
•
Global: Updated the numbering format for tables, figures and cross-references throughout the document...... 1
Decsription: Updated part numbers....................................................................................................................2
Device Comparison: Updated part numbers.......................................................................................................6
Pin Diagrams: Updated part numbers................................................................................................................ 9
Device and Development Support Tool Nomenclature: Updated Device Nomenclature image to show -Q1 part
number............................................................................................................................................................133
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
6 Device Comparison
Table 6-1. Device Comparison (100-MHz Devices)
F2809
F2809-Q1
F2808
F2808-Q1
F2806
F2806-Q1
F2802
F2802-Q1
F2801
F2801-Q1
FEATURE
TYPE(1)
C2802
10 ns
6K
C2801
10 ns
6K
Instruction cycle (at 100 MHz)
–
10 ns
10 ns
10 ns
10 ns
10 ns
18K
(L0, L1, M0,
M1, H0)
18K
(L0, L1, M0,
M1, H0)
10K
(L0, L1, M0,
M1)
Single-access RAM (SARAM) (16-bit
word)
6K
6K
–
(L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)
3.3-V on-chip flash (16-bit word)
On-chip ROM (16-bit word)
–
–
128K
–
64K
–
32K
–
32K
–
16K
–
–
–
32K
16K
Code security for on-chip flash/
SARAM/OTP blocks
–
–
–
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
–
Yes
Yes
–
Boot ROM (4K x 16)
One-time programmable (OTP) ROM
(16-bit word)
ePWM1/2/3/4 ePWM1/2/3/4 ePWM1/2/3/4
PWM channels
0
0
ePWM1/2/3
ePWM1/2/3
ePWM1/2/3
ePWM1/2/3
/5/6
/5/6
/5/6
ePWM1A/2A/
3A/
4A/5A/6A
ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/ ePWM1A/2A/
HRPWM channels
3A/4A
3A/4A
3A
3A
3A
3A
32-bit CAPTURE inputs or auxiliary
PWM outputs
0
0
eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4
eCAP1/2
eQEP1
eCAP1/2
eQEP1
eCAP1/2
eQEP1
eCAP1/2
eQEP1
32-bit QEP channels (four inputs/
channel)
eQEP1/2
eQEP1/2
eQEP1/2
Watchdog timer
–
1
–
0
0
Yes
80 ns
3
Yes
160 ns
3
Yes
160 ns
3
Yes
160 ns
3
Yes
160 ns
3
Yes
160 ns
3
Yes
160 ns
3
12-Bit, 16-channel ADC conversion time
32-Bit CPU timers
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D
SPI-A/B
SCI-A
SPI-A/B
SCI-A
SPI-A/B
SCI-A
SPI-A/B
SCI-A
SCI-A/B
SCI-A/B
SCI-A/B
eCAN-A
Enhanced Controller Area Network
(eCAN)
0
eCAN-A/B
eCAN-A/B
eCAN-A
eCAN-A
eCAN-A
eCAN-A
Inter-Integrated Circuit (I2C)
Digital I/O pins (shared)
External interrupts
0
–
–
I2C-A
35
I2C-A
35
I2C-A
35
I2C-A
35
I2C-A
35
I2C-A
35
I2C-A
35
3
3
3
3
3
3
3
1.8-V Core, 3.3-V
Supply voltage
I/O
–
–
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100-Pin PZ
Packaging
100-Ball GGM,
ZGM
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
A: –40°C to 85°C
–
–
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
(PZ, GGM,
ZGM)
Temperature
options
S: –40°C to 125°C
Q: –40°C to 125°C
(AEC-Q100
–
(PZ)
(PZ)
(PZ)
(PZ)
(PZ)
(PZ)
(PZ)
Qualification)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
Table 6-2. Device Comparison (60-MHz Devices)
F28016
F28016-Q1
F28015
F28015-Q1
FEATURE
TYPE(1)
F2802-60
F2801-60
Instruction cycle (at 60 MHz)
–
–
16.67 ns
16.67 ns
16.67 ns
16.67 ns
6K
6K
6K
6K
Single-access RAM (SARAM) (16-bit word)
(L0, M0, M1)
(L0, M0, M1)
(L0, M0, M1)
(L0, M0, M1)
3.3-V on-chip flash (16-bit word)
On-chip ROM (16-bit word)
–
–
32K
–
16K
–
16K
–
16K
–
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
Table 6-2. Device Comparison (60-MHz Devices) (continued)
F28016
F28016-Q1
F28015
F28015-Q1
FEATURE
TYPE(1)
F2802-60
F2801-60
Code security for on-chip flash/SARAM/OTP
blocks
–
–
–
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Yes
Yes
1K
Boot ROM (4K x 16)
One-time programmable (OTP) ROM
(16-bit word)
PWM channels
0
0
ePWM1/2/3
ePWM1/2/3
ePWM1/2/3/4
ePWM1/2/3/4
HRPWM channels
ePWM1A/2A/3A
ePWM1A/2A/3A
ePWM1A/2A/3A/4A
ePWM1A/2A/3A/4A
32-bit CAPTURE inputs or auxiliary PWM
outputs
0
eCAP1/2
eCAP1/2
eCAP1/2
eCAP1/2
32-bit QEP channels (four inputs/channel)
Watchdog timer
0
–
eQEP1
Yes
eQEP1
Yes
-
Yes
-
Yes
16
No. of channels
16
16
16
12-Bit ADC
MSPS
1
3.75
3.75
3.75
267 ns
3
3.75
267 ns
3
Conversion time
267 ns
3
267 ns
3
32-Bit CPU timers
–
0
0
0
0
–
–
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
Enhanced Controller Area Network (eCAN)
Inter-Integrated Circuit (I2C)
Digital I/O pins (shared)
SPI-A/B
SCI-A
eCAN-A
I2C-A
35
SPI-A/B
SCI-A
eCAN-A
I2C-A
35
SPI-A
SCI-A
eCAN-A
I2C-A
35
SPI-A
SCI-A
-
I2C-A
35
External interrupts
3
3
3
3
1.8-V Core,
3.3-V I/O
1.8-V Core,
3.3-V I/O
1.8-V Core,
3.3-V I/O
1.8-V Core,
3.3-V I/O
Supply voltage
–
100-Pin PZ
Packaging
–
–
–
–
Yes
Yes
Yes
Yes
100-Ball GGM, ZGM
Yes
Yes
Yes
Yes
A: –40°C to 85°C
(PZ, GGM, ZGM)
(PZ GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
(PZ, GGM, ZGM)
S: –40°C to 125°C
Temperature options
Q: –40°C to 125°C
(AEC-Q100
–
(PZ)
(PZ)
(PZ)
(PZ)
Qualification)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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6.1 Related Products
For information about other devices in this family of products, see the following links:
TMS320F2837xS Delfino™ Microcontrollers
The Delfino™ TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for
advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and
converters; digital power; transportation; and power line communications. Complete development packages for
digital power and industrial drives are available as part of the powerSUITE and DesignDRIVE initiatives.
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
The TMS320F2809, TMS320F2808, TMS320F2808-Q1, TMS320F2806, TMS320F2806-Q1, TMS320F2802,
TMS320F2802-Q1, TMS320F2801, TMS320F2801-Q1, TMS320C2802, TMS320C2801, TMS320F28015,
TMS320F28015-Q1, and TMS320F28016, TMS320F28016-Q1 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 7-1, Figure 7-2, Figure 7-3, and Figure 7-4. The 100-ball GGM and ZGM ball
grid array (BGA) terminal assignments are shown in Figure 7-5. Table 7-1 describes the function(s) of each pin.
TDO 76
50
49
GPIO16/SPISIMOA/CANTXB/TZ5
VSS
VSS
77
78
79
48 GPIO3/EPWM2B/SPISOMID
47 GPIO0/EPWM1A
XRS
GPIO27/ECAP4/EQEP2S/SPISTEB
VDDIO
EMU0 80
EMU1 81
46
45 GPIO2/EPWM2A
44 GPIO1/EPWM1B/SPISIMOD
43 GPIO34
VDDIO
82
83
84
85
GPIO24/ECAP1/EQEP2A/SPISIMOB
VDD
42
41
40
39
TRST
VDD
VSS
VDD2A18
VSS2AGND
X2 86
VSS
87
X1 88
38 ADCRESEXT
37 ADCREFP
36 ADCREFM
35 ADCREFIN
34 ADCINB7
33 ADCINB6
32 ADCINB5
31 ADCINB4
30 ADCINB3
29 ADCINB2
28 ADCINB1
27 ADCINB0
VSS
89
XCLKIN 90
GPIO25/ECAP2/EQEP2B/SPISOMIB
91
92
93
94
95
96
GPIO28/SCIRXDA/TZ5
VDD
VSS
GPIO13/TZ2/CANRXB/SPISOMIB
VDD3VFL
TEST1 97
TEST2 98
GPIO26/ECAP3/EQEP2I/SPICLKB
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
99
VDDAIO
100
26
Figure 7-1. TMS320F2809, TMS320F2808-Q1 100-Pin PZ LQFP (Top View)
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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TDO 76
50
49
GPIO16/SPISIMOA/TZ5
VSS
VSS
77
78
79
48 GPIO3/EPWM2B/SPISOMID
47 GPIO0/EPWM1A
XRS
GPIO27/ECAP4/EQEP2S/SPISTEB
VDDIO
EMU0 80
EMU1 81
46
45 GPIO2/EPWM2A
44 GPIO1/EPWM1B/SPISIMOD
43 GPIO34
VDDIO
82
83
84
85
GPIO24/ECAP1/EQEP2A/SPISIMOB
VDD
42
41
40
39
TRST
VDD
VSS
VDD2A18
VSS2AGND
X2 86
VSS
87
X1 88
38 ADCRESEXT
37 ADCREFP
36 ADCREFM
35 ADCREFIN
34 ADCINB7
33 ADCINB6
32 ADCINB5
31 ADCINB4
30 ADCINB3
29 ADCINB2
28 ADCINB1
27 ADCINB0
VSS
89
XCLKIN 90
GPIO25/ECAP2/EQEP2B/SPISOMIB
91
92
93
94
95
96
GPIO28/SCIRXDA/TZ5
VDD
VSS
GPIO13/TZ2/SPISOMIB
VDD3VFL
TEST1 97
TEST2 98
GPIO26/ECAP3/EQEP2I/SPICLKB
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
99
VDDAIO
100
26
Figure 7-2. TMS320F2806 100-Pin PZ LQFP (Top View)
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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TDO 76
50
49
GPIO16/SPISIMOA/TZ5
VSS
VSS
77
78
79
48 GPIO3/EPWM2B
47 GPIO0/EPWM1A
XRS
SPISTEB/GPIO27
VDDIO
EMU0 80
EMU1 81
46
45 GPIO2/EPWM2A
44 GPIO1/EPWM1B
43 GPIO34
VDDIO
82
83
84
85
SPISIMOB/GPIO24/ECAP1
VDD
42
41
40
39
TRST
VDD
VSS
VDD2A18
VSS2AGND
X2 86
VSS
87
X1 88
38 ADCRESEXT
37 ADCREFP
36 ADCREFM
35 ADCREFIN
34 ADCINB7
33 ADCINB6
32 ADCINB5
31 ADCINB4
30 ADCINB3
29 ADCINB2
28 ADCINB1
27 ADCINB0
VSS
89
XCLKIN 90
GPIO25/ECAP2/SPISOMIB
91
92
93
94
95
96
GPIO28/SCIRXDA/TZ5
VDD
VSS
SPISOMIB/GPIO13/TZ2
(A)
VDD3VFL
TEST1 97
TEST2 98
SPICLKB/GPIO26
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
99
VDDAIO
100
26
A. On the C280x devices, the VDD3VFL pin is VDDIO
.
Figure 7-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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TDO 76
50
49
GPIO16/SPISIMOA/TZ5
VSS
VSS
77
78
79
48 GPIO3/EPWM2B
47 GPIO0/EPWM1A
XRS
GPIO27
VDDIO
EMU0 80
EMU1 81
46
45 GPIO2/EPWM2A
44 GPIO1/EPWM1B
43 GPIO34
VDDIO
82
83
84
85
GPIO24/ECAP1
VDD
42
41
40
39
TRST
VDD
VSS
VDD2A18
VSS2AGND
X2 86
VSS
87
X1 88
38 ADCRESEXT
37 ADCREFP
36 ADCREFM
35 ADCREFIN
34 ADCINB7
33 ADCINB6
32 ADCINB5
31 ADCINB4
30 ADCINB3
29 ADCINB2
28 ADCINB1
27 ADCINB0
VSS
89
XCLKIN 90
GPIO25/ECAP2
91
92
93
94
95
96
GPIO28/SCIRXDA/TZ5
VDD
VSS
GPIO13/TZ2
VDD3VFL
TEST1 97
TEST2 98
GPIO26 99
VDDAIO
100
26
GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.
Figure 7-4. TMS320F2801x 100-Pin PZ LQFP (Top View)
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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VSSAIO
VSS2AGND
VDD2A18
VSS
VSS
ADCINB0
ADCINB3
ADCINB1
ADCINB2
ADCINA2
ADCINB5
ADCINB4
ADCINB6
ADCINA5
ADCINB7
ADCREFIN
ADCREFM
ADCREFP
GPIO1
GPIO0
GPIO3
GPIO16
K
J
VDDAIO
ADCLO
GPIO2
GPIO4
GPIO5
GPIO6
GPIO17
VDDIO
VSS
ADCINA1
ADCINA0
ADCINA3
VDDA2
GPIO18
H
G
F
VDD
ADCINA4
GPIO34
GPIO7
GPIO19
VSSA2
VSS
VDD
ADCINA7
ADCINA6
ADCRESEXT
GPIO20
GPIO9
GPIO8
VDD
VSS
VDD1A18
VSS1AGND
VDDIO
GPIO15
GPIO31
X1
GPIO21
XCLKOUT
GPIO22
GPIO27
XRS
GPIO10
E
D
C
B
A
VDD
VSS
VDD
VSS
GPIO30
GPIO14
GPIO29
TEST2
TEST1
GPIO28
GPIO11
VDDIO
VDD3VFL
GPIO33
GPIO25
XCLKIN
VSS
X2
GPIO24
EMU1
VDDIO
TDI
TDO
VSS
GPIO23
VSS
VDD
GPIO12
GPIO26
GPIO13
TMS
VSS
GPIO32
EMU0
TCK
TRST
1
2
3
4
5
6
7
8
9
10
Bottom View
Figure 7-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801, TMS320F28016,
TMS320F28015, TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)
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Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
7.2 Signal Descriptions
Table 7-1 describes the signals. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels.
Inputs are not 5-V tolerant.
Table 7-1. Signal Descriptions
PIN NO.
DESCRIPTION (1)
GGM/
ZGM
BALL #
NAME
PZ
PIN #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the
operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. An external
pulldown resistor is required on this pin. The value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate
protection. Since this is application-specific, it is recommended that each target board be validated
for proper operation of the debugger and the application. (I, ↓)
TRST
84
A6
TCK
TMS
75
74
A10
B10
JTAG test clock with internal pullup (I, ↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
TDI
73
76
C9
B9
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are
shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
TDO
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA
drive ↑)
EMU0
80
A8
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the device
into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low
state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA
drive ↑)
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.
EMU1
81
96
B7
C4
FLASH
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM
VDD3VFL
parts (C280x), this pin should be connected to VDDIO
.
TEST1
TEST2
97
98
A3
B3
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0
(XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal
can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKOUT
XCLKIN
66
90
E8
B5
External Oscillator Input. This pin is used to feed a clock from an external 3.3-V oscillator. In this
case, tie the X1 pin to GND. Alternately, when a crystal/resonator is used (or if an external 1.8-V
oscillator is fed into the X1 pin), tie the XCLKIN pin to GND. (I)
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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NAME
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
GGM/
ZGM
PZ
PIN #
BALL #
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital
power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN
pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)
X1
X2
88
86
E6
C6
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and
X2. If X2 is not used it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
XRS
78
B8
The output buffer of this pin is an open-drain with an internal pullup. If this pin is driven by an
external device, it should be done using an open-drain device.
ADC SIGNALS
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
External reference input (I)
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
16
17
18
19
20
21
22
23
34
33
32
31
30
29
28
27
24
38
35
F3
F4
G4
G1
G2
G3
H1
H2
K5
H4
K4
J4
K3
H3
J3
K2
J1
ADCRESEXT
ADCREFIN
F5
J5
Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
ADCREFP
ADCREFM
37
36
G5
H5
Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of
2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is
used in the system.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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Table 7-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
GGM/
ZGM
BALL #
NAME
PZ
PIN #
CPU AND I/O POWER PINS
ADC Analog Power Pin (3.3 V)
VDDA2
VSSA2
15
14
26
25
12
13
40
39
10
42
59
68
85
93
3
F2
F1
ADC Analog Ground Pin
VDDAIO
VSSAIO
VDD1A18
VSS1AGND
VDD2A18
VSS2AGND
VDD
J2
ADC Analog I/O Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
K1
E4
E5
J6
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
K6
E2
G6
F10
D7
B6
D4
C2
H7
E9
A7
B1
E3
H6
K9
H10
F7
VDD
VDD
CPU and Logic Digital Power Pins (1.8 V)
VDD
VDD
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VSS
46
65
82
2
Digital I/O Power Pin (3.3 V)
VSS
11
41
49
55
62
69
77
87
89
94
VSS
VSS
VSS
VSS
Digital Ground Pins
VSS
D10
A9
D6
A5
A4
VSS
VSS
VSS
VSS
GPIOA AND PERIPHERAL SIGNALS (2) (3)
GPIO0
General-purpose input/output 0 (I/O/Z) (4)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
47
44
45
K8
K7
J7
GPIO1
EPWM1B
SPISIMOD
-
General-purpose input/output 1 (I/O/Z)(4)
Enhanced PWM1 Output B (O)
SPI-D slave in, master out (I/O) (not available on 2801, 2802)
-
GPIO2
EPWM2A
-
-
General-purpose input/output 2 (I/O/Z)(4)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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NAME
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
GGM/
ZGM
PZ
PIN #
BALL #
GPIO3
EPWM2B
SPISOMID
-
General-purpose input/output 3 (I/O/Z)(4)
Enhanced PWM2 Output B (O)
SPI-D slave out, master in (I/O) (not available on 2801, 2802)
-
48
51
53
56
58
60
61
64
70
1
J8
J9
GPIO4
EPWM3A
-
-
General-purpose input/output 4 (I/O/Z)(4)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
General-purpose input/output 5 (I/O/Z)(4)
Enhanced PWM3 output B (O)
SPI-D clock (I/O) (not available on 2801, 2802)
Enhanced capture input/output 1 (I/O)
EPWM3B
SPICLKD
ECAP1
H9
G9
G8
F9
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
General-purpose input/output 6 (I/O/Z)(4)
Enhanced PWM4 output A and HRPWM channel (O) (not available on 2801, 2802)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
General-purpose input/output 7 (I/O/Z)(4)
Enhanced PWM4 output B (O) (not available on 2801, 2802)
SPI-D slave transmit enable (I/O) (not available on 2801, 2802)
Enhanced capture input/output 2 (I/O)
EPWM4B
SPISTED
ECAP2
GPIO8
General-purpose input/output 8 (I/O/Z)(4)
Enhanced PWM5 output A and HRPWM channel (O) (not available on 2801, 2802)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
ADC start-of-conversion A (O)
EPWM5A
CANTXB
ADCSOCAO
GPIO9
General-purpose input/output 9 (I/O/Z)(4)
Enhanced PWM5 output B (O) (not available on 2801, 2802)
SCI-B transmit data (O) (not available on 2801, 2802)
Enhanced capture input/output 3 (I/O) (not available on 2801, 2802)
EPWM5B
SCITXDB
ECAP3
F8
GPIO10
General-purpose input/output 10 (I/O/Z)(4)
Enhanced PWM6 output A and HRPWM channel (O) (not available on 2801, 2802)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
ADC start-of-conversion B (O)
EPWM6A
CANRXB
ADCSOCBO
E10
D9
B2
B4
D3
E1
K10
GPIO11
General-purpose input/output 11 (I/O/Z)(4)
Enhanced PWM6 output B (O) (not available on 2801, 2802)
SCI-B receive data (I) (not available on 2801, 2802)
Enhanced CAP Input/Output 4 (I/O) (not available on 2801, 2802)
EPWM6B
SCIRXDB
ECAP4
GPIO12
TZ1
CANTXB
SPISIMOB
General-purpose input/output 12 (I/O/Z)(5)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
SPI-B Slave in, Master out (I/O)
GPIO13
TZ2
CANRXB
SPISOMIB
General-purpose input/output 13 (I/O/Z)(5)
Trip zone input 2 (I)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
SPI-B slave out, master in (I/O)
95
8
GPIO14
TZ3
SCITXDB
SPICLKB
General-purpose input/output 14 (I/O/Z)(5)
Trip zone input 3 (I)
SCI-B transmit (O) (not available on 2801, 2802)
SPI-B clock input/output (I/O)
GPIO15
TZ4
SCIRXDB
SPISTEB
General-purpose input/output 15 (I/O/Z)(5)
Trip zone input 4 (I)
SCI-B receive (I) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)
9
GPIO16
SPISIMOA
CANTXB
TZ5
General-purpose input/output 16 (I/O/Z)(5)
SPI-A slave in, master out (I/O)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
Trip zone input 5 (I)
50
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Table 7-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
GGM/
ZGM
BALL #
NAME
PZ
PIN #
GPIO17
General-purpose input/output 17 (I/O/Z)(5)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
Trip zone input 6 (I)
SPISOMIA
CANRXB
TZ6
52
54
J10
H8
GPIO18
SPICLKA
SCITXDB
General-purpose input/output 18 (I/O/Z)(5)
SPI-A clock input/output (I/O)
SCI-B transmit (O) (not available on 2801, 2802)
-
-
-
-
GPIO19
General-purpose input/output 19 (I/O/Z)(5)
SPISTEA
SPI-A slave transmit enable input/output (I/O)
SCIRXDB
57
G10
SCI-B receive (I) (not available on 2801, 2802)
-
-
-
-
GPIO20
General-purpose input/output 20 (I/O/Z)(5)
EQEP1A
SPISIMOC
CANTXB
Enhanced QEP1 input A (I)
SPI-C slave in, master out (I/O) (not available on 2801, 2802)
Enhanced CAN-B transmit (O) (not available on 2801, 2802, F2806)
63
67
71
72
83
91
99
79
92
4
F6
E7
D8
C10
C7
C5
A2
C8
D5
C3
GPIO21
General-purpose input/output 21 (I/O/Z)(5)
Enhanced QEP1 input A (I)
SPI-C master in, slave out (I/O) (not available on 2801, 2802)
Enhanced CAN-B receive (I) (not available on 2801, 2802, F2806)
EQEP1B
SPISOMIC
CANRXB
GPIO22
General-purpose input/output 22 (I/O/Z)(5)
Enhanced QEP1 strobe (I/O)
SPI-C clock (I/O) (not available on 2801, 2802)
SCI-B transmit (O) (not available on 2801, 2802)
EQEP1S
SPICLKC
SCITXDB
GPIO23
EQEP1I
SPISTEC
SCIRXDB
General-purpose input/output 23 (I/O/Z)(5)
Enhanced QEP1 index (I/O)
SPI-C slave transmit enable (I/O) (not available on 2801, 2802)
SCI-B receive (I) (not available on 2801, 2802)
GPIO24
ECAP1
EQEP2A
SPISIMOB
General-purpose input/output 24 (I/O/Z)(5)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I) (not available on 2801, 2802)
SPI-B slave in, master out (I/O)
GPIO25
ECAP2
EQEP2B
SPISOMIB
General-purpose input/output 25 (I/O/Z)(5)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I) (not available on 2801, 2802)
SPI-B master in, slave out (I/O)
GPIO26
ECAP3
EQEP2I
SPICLKB
General-purpose input/output 26 (I/O/Z)(5)
Enhanced capture 3 (I/O) (not available on 2801, 2802)
Enhanced QEP2 index (I/O) (not available on 2801, 2802)
SPI-B clock (I/O)
GPIO27
ECAP4
EQEP2S
SPISTEB
General-purpose input/output 27 (I/O/Z)(5)
Enhanced capture 4 (I/O) (not available on 2801, 2802)
Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)
SPI-B slave transmit enable (I/O)
GPIO28
SCIRXDA
-
General-purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
SCI receive data (I)
-
TZ5
Trip zone input 5 (I)
GPIO29
SCITXDA
-
General-purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
SCI transmit data (O)
-
TZ6
Trip zone 6 input (I)
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NAME
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
Table 7-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
GGM/
ZGM
PZ
PIN #
BALL #
GPIO30
General-purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
CANRXA
-
-
Enhanced CAN-A receive data (I)
-
-
6
7
D2
D1
A1
C1
G7
GPIO31
CANTXA
-
-
General-purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)(5)
Enhanced CAN-A transmit data (O)
-
-
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
General-purpose input/output 32 (I/O/Z)(5)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion (O)
100
5
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
General-Purpose Input/Output 33 (I/O/Z)(5)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion (O)
GPIO34
General-Purpose Input/Output 34 (I/O/Z)(5)
-
-
-
-
-
-
43
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
(2) Some peripheral functions may not be available in TMS320F2801x devices. See Table 6-2 for details.
(3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively enabled/
disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at reset. The
peripheral signals that are listed under them are alternate functions.
(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.
(5) The pullups on GPIO12-GPIO34 are enabled upon reset.
Note
Some peripheral functions may not be available in TMS320F2801x devices. See Table 6-2 for details.
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TMS320C2801, TMS320F28016, TMS320F28015
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8 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
8.1 Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. (1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
VDDIO, VDD3VFL with respect to VSS
VDDA2, VDDAIO with respect to VSSA
VDD with respect to VSS
4.6
4.6
2.5
Supply voltage
V
VDD1A18, VDD2A18 with respect to VSSA
2.5
VSSA2, VSSAIO, VSS1AGND, VSS2AGND with respect
to VSS
–0.3
0.3
Input voltage
VIN
–0.3
–0.3
–20
–20
–40
–40
–40
–40
–65
4.6
4.6
20
V
V
Output voltage
VO
(3)
Input clamp current
Output clamp current
IIK (VIN < 0 or VIN > VDDIO
)
mA
mA
IOK (VO < 0 or VO > VDDIO
)
20
A version (GGM, ZGM, PZ)(4)
S version (GGM, ZGM, PZ)(4)
Q version (PZ)(4)
85
Operating ambient temperature, TA
125
125
150
150
°C
(4)
Junction temperature
Storage temperature
TJ
°C
°C
(4)
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 8.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2
.
(4) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall
device life. For additional information, see Semiconductor and IC package thermal metrics.
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TMS320C2801, TMS320F28016, TMS320F28015
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8.2 ESD Ratings – Automotive
VALUE
UNIT
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, and
TMS320F28015 in 100-pin PZ package
Human body model (HBM), per AEC-Q100-002(1)
±2000
±500
±750
Charged device model (CDM),
per AEC-Q100-011
All pins
V(ESD)
Electrostatic discharge
V
Corner pins on 100-pin PZ:
1, 25, 26, 50, 51, 75, 76, 100
(1) AEC-Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 ESD Ratings – Commercial
VALUE
UNIT
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, and
TMS320F28015 in 100-ball ZGM package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28016, and
TMS320F28015 in 100-ball GGM package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.14
1.71
NOM
3.3
1.8
0
MAX
3.47
1.89
UNIT
V
Device supply voltage, I/O, VDDIO
Device supply voltage CPU, VDD
Supply ground, VSS, VSSIO
V
V
ADC supply voltage (3.3 V), VDDA2, VDDAIO
ADC supply voltage (1.8 V), VDD1A18, VDD2A18
Flash supply voltage, VDD3VFL
3.14
3.3
1.8
3.3
3.47
V
1.71
1.89
V
3.14
3.47
V
Device clock frequency (system clock),
fSYSCLKOUT
100-MHz devices
60-MHz devices
All inputs except X1
X1
2
100
MHz
MHz
V
2
2
60
High-level input voltage, VIH
VDDIO + 0.3
0.7 * VDD – 0.05
VSS – 0.3
VDD
Low-level input voltage, VIL
All inputs except X1
X1
0.8
V
0.3 * VDD + 0.05
All I/Os except Group 2
Group 2(1)
–4
–8
4
mA
mA
High-level output source current,
VOH = 2.4 V, IOH
All I/Os except Group 2
Group 2(1)
Low-level output sink current,
VOL = VOL MAX, IOL
8
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over operating free-air temperature range (unless otherwise noted)
MIN
–40
–40
–40
NOM
MAX
85
UNIT
A version
S version
°C
125
125
Ambient temperature, TA
Q version
(AEC-Q100
Qualification)
(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, and EMU1
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TMS320C2801, TMS320F28016, TMS320F28015
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8.5 Power Consumption Summary
8.5.1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
(1)
(2)
(3)
(4)
IDD
IDDIO
TYP(5)
IDD3VFL
TYP
IDDA18
TYP(5)
IDDA33
TYP(5)
MODE
TEST CONDITIONS
TYP(5)
MAX(6)
MAX(6)
MAX(6)
MAX(6)
MAX(6)
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4
eQEP1/2
eCAN-A
SCI-A/B
SPI-A
ADC
I2C
Operational
(Flash)
195 mA
230 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled
at 100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the
SCI-A, SCI-B, and
eCAN-A ports. The
hardware multiplier is
exercised.
Code is running out of
flash with 3 wait-states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
75 mA
90 mA
12 mA
500 μA
2 mA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
6 mA
100 μA
60 μA
500 μA
120 μA
2 μA
2 μA
10 μA
10 μA
5 μA
5 μA
50 μA
50 μA
15 μA
15 μA
30 μA
30 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 8.14.6.3. If the user
application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply
stage.
(3) IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) IDDA33 includes current into VDDA2 and VDDAIO pins.
(5) TYP numbers are applicable over room temperature and nominal voltage.
(6) MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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TMS320C2801, TMS320F28016, TMS320F28015
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8.5.2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
(1)
(2)
(3)
(4)
IDD
IDDIO
TYP(5)
IDD3VFL
IDDA18
TYP(5)
IDDA33
MODE
TEST CONDITIONS
TYP(5)
MAX(6)
MAX(6)
TYP(5)
MAX(6)
MAX(6)
TYP(5)
MAX(6)
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3/4/5/6
eCAP1/2/3/4
eQEP1/2
eCAN-A
SCI-A/B
SPI-A
ADC
I2C
Operational
(Flash)
195 mA 230 mA 15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
75 mA
90 mA
12 mA
500 μA
2 mA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
6 mA
100 μA
60 μA
500 μA
120 μA
2 μA
2 μA
10 μA
10 μA
5 μA
5 μA
50 μA
50 μA
15 μA
15 μA
30 μA
30 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 8.14.6.3. If the user
application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply
stage.
(3) IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) IDDA33 includes current into VDDA2 and VDDAIO pins.
(5) TYP numbers are applicable over room temperature and nominal voltage.
(6) MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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8.5.3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
(1)
(2)
(3)
(4)
IDD
IDDIO
TYP(5)
IDD3VFL
TYP(5)
IDDA18
TYP(5)
IDDA33
TYP(5)
MODE
TEST CONDITIONS
TYP(5)
MAX(6)
MAX(6)
MAX(6)
MAX(6)
MAX(6)
The following peripheral
clocks are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3
eCAP1/2
eQEP1
eCAN-A
SCI-A
SPI-A
ADC
I2C
Operational
(Flash)
180 mA
210 mA
15 mA
27 mA
35 mA
40 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled at
100 kHz.
All I/O pins are left
unconnected.
Data is continuously
transmitted out of the SCI-A,
SCI-B, and eCAN-A ports.
The hardware multiplier is
exercised.
Code is running out of flash
with 3 wait-states.
XCLKOUT is turned off.
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
75 mA
90 mA
12 mA
500 μA
2 mA
2 μA
10 μA
5 μA
50 μA
15 μA
30 μA
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT
6 mA
100 μA
60 μA
500 μA
120 μA
2 μA
2 μA
10 μA
10 μA
5 μA
5 μA
50 μA
50 μA
15 μA
15 μA
30 μA
30 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.
70 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 8.14.6.3. If the user
application involves on-board flash programming, this extra current must be taken into account while architecting the power-supply
stage.
(3) IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4) IDDA33 includes current into VDDA2 and VDDAIO pins.
(5) TYP numbers are applicable over room temperature and nominal voltage.
(6) MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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8.5.4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at
100-MHz SYSCLKOUT
(1)
(2)
(3)
IDD
IDDIO
TYP(4)
IDDA18
TYP(4)
IDDA33
MODE
TEST CONDITIONS
TYP(4)
MAX(5)
MAX(5)
MAX(5)
TYP(4)
MAX(5)
The following peripheral clocks
are enabled:
•
•
•
•
•
•
•
•
ePWM1/2/3
eCAP1/2
eQEP1
eCAN-A
SCI-A
SPI-A
ADC
Operational
(ROM)
I2C
150 mA
165 mA
5 mA
10 mA
30 mA
38 mA
1.5 mA
2 mA
All PWM pins are toggled at
100 kHz.
All I/O pins are left unconnected.
Data is continuously transmitted
out of the SCI-A, SCI-B, and
eCAN-A ports. The hardware
multiplier is exercised.
Code is running out of ROM with
3 wait-states.
XCLKOUT is turned off.
XCLKOUT is turned off.
The following peripheral clocks
are enabled:
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
IDLE
75 mA
90 mA
12 mA
500 μA
2 mA
5 μA
50 μA
15 μA
30 μA
STANDBY
HALT
Peripheral clocks are off.
6 mA
100 μA
80 μA
500 μA
120 μA
5 μA
5 μA
50 μA
50 μA
15 μA
15 μA
30 μA
30 μA
Peripheral clocks are off.
Input clock is disabled.
70 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) TYP numbers are applicable over room temperature and nominal voltage.
(5) MAX numbers are at 125°C and MAX voltage.
Note
The peripheral - I/O multiplexing implemented in the 280x devices prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may share an
I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although
such a configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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8.5.5 Reducing Current Consumption
280x devices have a richer peripheral mix compared to the 281x family. While the McBSP has been removed,
the following new peripherals have been added on the 280x:
•
•
•
3 SPI modules
1 CAN module
1 I2C module
The two event manager modules of the 281x have been enhanced and replaced with separate ePWM (6), eCAP
(4) and eQEP (2) modules, providing tremendous flexibility in applications. Like 281x, 280x DSPs incorporate a
unique method to reduce the device current consumption. Since each peripheral unit has an individual clock-
enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral
module that is not used in a given application. Furthermore, any one of the three low-power modes could be
taken advantage of to reduce the current consumption even further. Table 8-1 indicates the typical reduction in
current consumption achieved by turning off the clocks.
Table 8-1. Typical Current Consumption by Various
Peripherals (at 100 MHz)
PERIPHERAL
MODULE(1)
IDD CURRENT
REDUCTION (mA)(2)
ADC
I2C
8(3)
5
eQEP
ePWM
eCAP
SCI
5
5
2
4
SPI
5
eCAN
11
(1) All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral
clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for
one ePWM module.
(3) This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA18) as well.
Note
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Note
The baseline IDD current (current when the core is executing a dummy loop with no peripherals
enabled) is 110 mA, typical. To arrive at the IDD current for a given application, the current-drawn by
the peripherals (enabled by that application) must be added to the baseline IDD current.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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8.5.6 Current Consumption Graphs
250.0
200.0
150.0
100.0
50.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
1.8-V current
IDD
IDDA18
IDDIO
IDD3VFL
3.3-V current
Figure 8-1. Typical Operational Current Versus Frequency (F2808)
600.0
500.0
400.0
300.0
200.0
100.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
TOTAL POWER
Figure 8-2. Typical Operational Power Versus Frequency (F2808)
Note
Typical operational current for 60-MHz devices can be estimated from Figure 8-1. For IDD current
alone, subtract the current contribution of non-existent peripherals after scaling the peripheral currents
for 60 MHz. For example, to compute the current of F2801-60 device, the contribution by the following
peripherals must be subtracted from IDD: ePWM4/5/6, eCAP3/4, eQEP2, SCI-B.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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Current Vs SYSCLKOUT
200
180
160
140
120
100
80
60
40
20
0
10
20
30
40
50
60
70
80
90
10
SYSCLKOUT (MHz)
IDD
IDDA18
1.8v current IDDIO
IDD3VFL
3.3v current
Figure 8-3. Typical Operational Current Versus Frequency (C280x)
Device Power Vs SYSCLKOUT
400.0
300.0
200.0
100.0
0.0
10
20
30
40
50
60
70
80
90
100
SYSCLKOUT (MHz)
TOTAL POWER
Figure 8-4. Typical Operational Power Versus Frequency (C280x)
8.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOH MAX
IOH = 50 μA
VOH High-level output voltage
V
VDDIO – 0.2
VOL
Low-level output voltage
IOL = IOL MAX
0.4
V
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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MAX UNIT
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Pin with pullup
enabled
VDDIO = 3.3 V, VIN = 0 V All I/Os (including XRS)
–80
–140
–190
μA
Input current
(low level)
IIL
Pin with pulldown
enabled
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
±2
Pin with pullup
enabled
±2
Input current Pin with pulldown
IIH
VDDIO = 3.3 V, VIN = VDDIO (F280x)
VDDIO = 3.3 V, VIN = VDDIO (C280x)
VO = VDDIO or 0 V
28
80
50
80
190
±2
μA
(high level)
enabled
Pin with pulldown
enabled
140
Output current, pullup or pulldown
disabled
IOZ
CI
μA
pF
Input capacitance
2
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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8.7 Thermal Resistance Characteristics for F280x 100-Ball GGM Package
°C/W(1)
12.08
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
N/A
N/A
0
16.46
30.58
29.31
28.09
26.62
0.4184
0.32
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
150
250
500
PsiJT
0.3725
0.4887
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
8.8 Thermal Resistance Characteristics for F280x 100-Pin PZ Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
12.89
29.58
48.16
40.06
37.96
35.17
0.3425
0.85
N/A
N/A
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
150
250
500
PsiJT
1.0575
1.410
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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8.9 Thermal Resistance Characteristics for C280x 100-Ball GGM Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
14.18
21.36
36.33
35.01
33.81
32.31
0.57
N/A
N/A
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
0.43
150
250
500
PsiJT
0.52
0.67
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
8.10 Thermal Resistance Characteristics for C280x 100-Pin PZ Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
13.52
54.78
69.81
60.34
57.46
53.63
0.42
N/A
N/A
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
1.23
150
250
500
PsiJT
1.54
2.11
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
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8.11 Thermal Resistance Characteristics for F2809 100-Ball GGM Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
10.36
13.3
N/A
N/A
0
28.15
26.89
25.68
24.22
0.38
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
0.35
150
250
500
PsiJT
0.33
0.44
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
8.12 Thermal Resistance Characteristics for F2809 100-Pin PZ Package
°C/W(1)
AIR FLOW (lfm)(2)
RΘJC
RΘJB
Junction-to-case thermal resistance
Junction-to-board thermal resistance
7.06
28.76
44.02
28.34
36.28
33.68
0.2
N/A
N/A
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air thermal resistance
Junction-to-package top
0.56
0.7
150
250
500
PsiJT
0.95
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) lfm = linear feet per minute
8.13 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems with
more than 1 Watt power dissipation may require a product level thermal design. Care should be taken to keep Tj
within specified limits. In the end applications, Tcase should be measured to estimate the operating junction
temperature Tj. Tcase is normally measured at the center of the package top side surface. The thermal
application note Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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8.14 Timing and Switching Characteristics
8.14.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
8.14.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
8.14.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
W
3.5 nH
Output
Under
Test
42
Transmission Line
(A)
Z0 = 50 W
Device Pin(B)
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 8-5. 3.3-V Test Load Circuit
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8.14.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the 280x DSPs. Section 8.14.1.3.1 and Section 8.14.1.3.2 list the cycle times of various clocks.
8.14.1.3.1 TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
MIN
28.6
20
10
4
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator
clock
tc(CI), Cycle time
250
100
500
100
2000
100
XCLKIN(1)
Frequency
MHz
ns
tc(SCO), Cycle time
Frequency
10
2
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
MHz
ns
tc(XCO), Cycle time
Frequency
10
0.5
10
MHz
ns
tc(HCO), Cycle time
Frequency
20(3)
50(3)
40(3)
25(3)
100
100
12.5
25
MHz
ns
tc(LCO), Cycle time
Frequency
10
80
40
MHz
ns
tc(ADCCLK), Cycle time (All devices except F2809)
Frequency (All devices except F2809)
tc(ADCCLK), Cycle time (F2809)
Frequency (F2809)
MHz
ns
ADC clock
MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 100 MHz.
8.14.1.3.2 TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices)
MIN
28.6
20
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator
clock
tc(CI), Cycle time
Frequency
16.67
4
250
60
XCLKIN(1)
SYSCLKOUT
XCLKOUT
HSPCLK(2)
LSPCLK(2)
ADC clock
MHz
ns
tc(SCO), Cycle time
Frequency
16.67
2
500
60
MHz
ns
tc(XCO), Cycle time
Frequency
16.67
0.5
2000
60
MHz
ns
tc(HCO), Cycle time
Frequency
16.67
33.3(3)
30(3)
60
60
MHz
ns
tc(LCO), Cycle time
Frequency
16.67
66.7(3)
15(3)
MHz
ns
tc(ADCCLK), Cycle time
Frequency
133.33
7.5
MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default reset value if SYSCLKOUT = 60 MHz.
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8.14.2 Power Sequencing
No requirements are placed on the power up/down sequence of the various power pins to ensure the correct
reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins
are powered prior to the 1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur
on the pin during power up. To avoid this behavior, power the VDD (core voltage) pins prior to or simultaneously
with the VDDIO (input/output voltage) pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins
reach 0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Section
8.14.2.1). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. This is to
enhance flash reliability.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, it is
0.7 V above VDDA) prior to powering up the device. Voltages applied to pins on an unpowered device can bias
internal p-n junctions in unintended ways and produce unpredictable results.
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8.14.2.1 Reset ( XRS) Timing Requirements
MIN
8tc(OSCCLK)
8tc(OSCCLK)
NOM
MAX UNIT
cycles
(1)
tw(RSL1)
tw(RSL2)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Warm reset
cycles
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
td(EX)
512tc(OSCCLK)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
tOSCST
1
th(boot-mode)
Hold time for boot-mode pins
200tc(OSCCLK)
cycles
(1) In addition to the tw(RSL1) requirement, XRS has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Internal)
(Don’t Care)
User-Code Execution
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 8-6. Warm Reset
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Figure 8-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is
written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency, OSCCLK x
4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t ) is
(Changed CPU Frequency)
p
131072 OSCCLK Cycles Long.)
Figure 8-7. Example of Effect of Writing Into PLLCR Register
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8.14.3 Clock Requirements and Characteristics
8.14.3.1 Input Clock Frequency
PARAMETER
MIN
20
20
4
TYP MAX UNIT
Resonator (X1/X2)
35
Crystal (X1/X2)
35
MHz
100
fx
Input clock frequency
100-MHz device
60-MHz device
External oscillator/clock
source (XCLKIN or X1 pin)
4
60
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1–5
MHz
8.14.3.2 XCLKIN Timing Requirements - PLL Enabled
NO.(1)
MIN
MAX UNIT
C8
C9
tc(CI)
tf(CI)
Cycle time, XCLKIN
33.3
200
6
ns
ns
ns
Fall time, XCLKIN
C10 tr(CI)
Rise time, XCLKIN
6
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
45%
55%
55%
(1) This applies to the X1 pin also.
8.14.3.3 XCLKIN Timing Requirements - PLL Disabled
NO.(1)
MIN
10
MAX UNIT
100-MHz device
60-MHz device
Up to 20 MHz
250
ns
250
C8 tc(CI)
C9 tf(CI)
C10 tr(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
Rise time, XCLKIN
16.67
6
2
ns
ns
ns
ns
20 MHz to 100 MHz
Up to 20 MHz
6
20 MHz to 100 MHz
2
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
45%
55%
55%
The possible configuration modes are shown in Table 9-33.
8.14.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
NO.
PARAMETER
MIN
TYP
MAX UNIT
(1) (2)
100-MHz device
60-MHz device
10
C1 tc(XCO)
Cycle time, XCLKOUT
ns
16.67
C3 tf(XCO)
C4 tr(XCO)
C5 tw(XCOL)
C6 tw(XCOH)
tp
Fall time, XCLKOUT
2
2
ns
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H – 2
H – 2
H + 2
ns
ns
H + 2
(3)
131072tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
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C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 8-8. Clock Timing
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8.14.4 Peripherals
8.14.4.1 General-Purpose Input/Output (GPIO)
8.14.4.1.1 GPIO - Output Timing
8.14.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 8-9. General-Purpose Output Timing
8.14.4.1.2 GPIO - Input Timing
8.14.4.1.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
2tc(SCO)
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
(B)
w(SP)
by GPxCTRL[QUALPRD]
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
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D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 8-10. Sampling Mode
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8.14.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using 3 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0
Case 2:
Qualification using 6 samples
Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 8-11. General-Purpose Input Timing
Note
The pulse-width requirement for general-purpose input is applicable for the XINT2_ADCSOC signal as
well.
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8.14.4.1.4 Low-Power Mode Wakeup Timing
Section 8.14.4.1.4.1 shows the timing requirements, Section 8.14.4.1.4.2 shows the switching characteristics,
and Figure 8-12 shows the timing diagram for IDLE mode.
8.14.4.1.4.1 IDLE Mode Timing Requirements
MIN(1)
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
8.14.4.1.4.2 IDLE Mode Switching Characteristics
PARAMETER(1)
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program
execution resume (2)
•
•
•
Wake-up from Flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
cycles
cycles
cycles
–
20tc(SCO) + tw(IQSW)
1050tc(SCO)
td(WAKE-IDLE)
Wake-up from Flash
Flash module in sleep state
–
1050tc(SCO) + tw(IQSW)
20tc(SCO)
Wake-up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 8-12. IDLE Entry and Exit Timing
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8.14.4.1.4.3 STANDBY Mode Timing Requirements
TEST CONDITIONS
MIN
3tc(OSCCLK)
MAX
UNIT
Without input qualification
With input qualification(1)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
8.14.4.1.4.4 STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO) cycles
Delay time, external wake signal to
program execution resume(1)
•
Wake up from flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
cycles
–
100tc(SCO) + tw(WAKE-INT)
td(WAKE-STBY)
•
Wake up from flash
Flash module in sleep state
1125tc(SCO)
1125tc(SCO) + tw(WAKE-INT)
100tc(SCO)
cycles
cycles
–
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake−up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0) or 64 cycles (if
CLKINDIV = 1) before being turned off. This delay enables the CPU pipe and any other pending operations to flush properly.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 8-13. STANDBY Entry and Exit Timing Diagram
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8.14.4.1.4.5 HALT Mode Timing Requirements
MIN
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Section 8.14.2.1 for an explanation of toscst
.
8.14.4.1.4.6 HALT Mode Switching Characteristics
PARAMETER
MIN
32tc(SCO)
MAX
45tc(SCO)
UNIT
cycles
cycles
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
131072tc(OSCCLK)
Delay time, PLL lock to program execution resume
•
Wake up from flash
– Flash module in sleep state
1125tc(SCO)
cycles
td(WAKE-HALT)
•
Wake up from SARAM
35tc(SCO)
cycles
(G)
(A)
(C)
(E)
(B)
(D)
HALT
(F)
Device
Status
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for approximately 32 cycles (if CLKINDIV = 0) or 64 cycles (if
CLKINDIV = 1) before the oscillator is turned off and the CLKIN to the core is stopped. This delay enables the CPU pipe and any other
pending operations to flush properly.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be taken
to maintain a low noise environment prior to entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this
duration even when the PLL is disabled).
F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
G. Normal operation resumes.
Figure 8-14. HALT Wake-Up Using GPIOn
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8.14.4.2 Enhanced Control Peripherals
8.14.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 8.14.4.2.1.1 shows the PWM timing requirements and
Section 8.14.4.2.1.2, switching characteristics.
8.14.4.2.1.1 ePWM Timing Requirements
TEST CONDITIONS(1)
Asynchronous
MIN
2tc(SCO)
MAX
UNIT
cycles
cycles
cycles
tw(SYCIN)
Sync input pulse width
Synchronous
2tc(SCO)
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
8.14.4.2.1.2 ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
td(PWM)tza
8tc(SCO)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
no pin load
25
20
ns
ns
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
8.14.4.2.2 Trip-Zone Input Timing
8.14.4.2.2.1 Trip-Zone input Timing Requirements
MIN(1)
1tc(SCO)
2tc(SCO)
MAX UNIT
cycles
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
SYSCLK
tw(TZ)
TZ(A)
td(TZ-PWM)HZ
PWM(B)
A. TZ: TZ1, TZ2, TZ3, TZ4 , TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 8-15. PWM Hi-Z Characteristics
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8.14.4.2.3 High-Resolution PWM Timing
Section 8.14.4.2.3.1 shows the high-resolution PWM switching characteristics.
8.14.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz
MIN
TYP MAX UNIT
150 310 ps
Micro Edge Positioning (MEP) step size(1)
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
8.14.4.2.4 Enhanced Capture (eCAP) Timing
Section 8.14.4.2.4.1 shows the eCAP timing requirement and Section 8.14.4.2.4.2 shows the eCAP switching
characteristics.
8.14.4.2.4.1 Enhanced Capture (eCAP) Timing Requirement
TEST CONDITIONS(1)
Asynchronous
MIN
2tc(SCO)
MAX UNIT
tw(CAP)
Capture input pulse width
Synchronous
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
8.14.4.2.4.2 eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
8.14.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 8.14.4.2.5.1 shows the eQEP timing requirement and Section 8.14.4.2.5.2 shows the eQEP switching
characteristics.
8.14.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
TEST CONDITIONS(1)
Asynchronous(2)/synchronous
With input qualifier
MIN
MAX
UNIT
2tc(SCO)
tw(QEPP)
QEP input period
cycles
2[1tc(SCO) + tw(IQSW)
]
Asynchronous(2)/synchronous
2tc(SCO)
2tc(SCO) +tw(IQSW)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous(2)/synchronous
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) +tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
(2) Refer to the TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon errata for limitations in the asynchronous mode.
8.14.4.2.5.2 eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO) cycles
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PARAMETER
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output
TEST CONDITIONS
MIN
MAX
UNIT
6tc(SCO) cycles
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8.14.4.2.6 ADC Start-of-Conversion Timing
8.14.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCAL)
Pulse duration, ADCSOCAO low
32tc(HCO )
cycles
t
w(ADCSOCAL)
ADCSOCAO
or
ADCSOCBO
Figure 8-16. ADCSOCAO or ADCSOCBO Timing
8.14.4.3 External Interrupt Timing
8.14.4.3.1 External Interrupt Timing Requirements
MIN(1)
1tc(SCO)
MAX
UNIT
Synchronous
With qualifier
(2)
tw(INT)
Pulse duration, INT input low/high
cycles
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
8.14.4.3.2 External Interrupt Switching Characteristics
PARAMETER(1)
MIN
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see Section 8.14.4.1.2.1.
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 8-17. External Interrupt Timing
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8.14.4.4 I2C Electrical Specification and Timing
8.14.4.4.1 I2C Timing
TEST CONDITIONS
MIN
MAX
400
UNIT
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
fSCL
SCL clock frequency
kHz
Vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
Low level output voltage
3 mA sink current
0.4
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tLOW Low period of SCL clock
tHIGH High period of SCL clock
1.3
μs
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
0.6
μs
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
lI
–10
10
μA
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8.14.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
8.14.4.5.1 SPI Master Mode Timing
Section 8.14.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 8.14.4.5.1.2 lists the master
mode timing (clock phase = 1). Figure 8-18 and Figure 8-19 show the timing waveforms.
8.14.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(5)
BRR EVEN
MIN
BRR ODD
MIN
(4) (3) (2)
PARAMETER
UNIT
(1)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
+
2
3
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
–
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
4
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
5
0.5tc(SPC)M – 10
Setup time, SPISOMI before
SPICLK
8
35
0
35
0
Hold time, SPISOMI valid after
SPICLK
9
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M –
3tc(SYSCLK) – 10
23
24
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 8-18. SPI Master Mode External Timing (Clock Phase = 0)
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UNIT
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8.14.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
(5)
MAX
MAX
127tc(LSPCLK)
0.5tc(SPC)M –
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
ns
ns
Pulse duration, SPICLK first
pulse
–
2
3
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
0.5tc(LSPCLK) + 10
+
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
6
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
35
0
35
Hold time, SPISOMI valid after
SPICLK
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
0.5tc(SPC) – 10
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 8-19. SPI Master Mode External Timing (Clock Phase = 1)
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8.14.4.5.2 SPI Slave Mode Timing
Section 8.14.4.5.2.1 lists the slave mode timing (clock phase = 0) and Section 8.14.4.5.2.2 lists the slave mode
timing (clock phase = 1). Figure 8-20 and Figure 8-21 show the timing waveforms.
8.14.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(4) (3)
(5)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 8-20. SPI Slave Mode External Timing (Clock Phase = 0)
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8.14.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(3) (4)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 8-21. SPI Slave Mode External Timing (Clock Phase = 1)
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8.14.5 Emulator Connection Without Signal Buffering for the DSP
Figure 8-22 shows the connection between the DSP and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 8-22 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see Section 7.2.
6 inches or less
VDDIO
VDDIO
13
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
PD
14
2
4
6
8
GND
GND
GND
GND
GND
TRST
TMS
1
3
TDI
7
10
12
TDO
TCK
TDO
11
TCK
9
TCK_RET
DSP
JTAG Header
Figure 8-22. Emulator Connection Without Signal Buffering for the DSP
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8.14.6 Flash Timing
8.14.6.1 Flash Endurance for A and S Temperature Material
ERASE/PROGRAM
MIN
TYP
MAX
UNIT
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
0°C to 85°C (ambient)
0°C to 85°C (ambient)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.6.2 Flash Endurance for Q Temperature Material
ERASE/PROGRAM
MIN
TYP
MAX
UNIT
TEMPERATURE(1)
Nf
Flash endurance for the array (write/erase cycles)
–40°C to 125°C (ambient)
–40°C to 125°C (ambient)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
8.14.6.3 Flash Parameters at 100-MHz SYSCLKOUT
PARAMETER
16-Bit Word
TEST CONDITIONS
MIN
TYP
50
500
250
125
2
MAX
UNIT
μs
16K Sector
8K Sector
4K Sector
16K Sector
2000(2)
2000(2)
2000(2)
15(2)
ms
ms
ms
s
Program
Time(1)
Erase Time(3) 8K Sector
2
15(2)
s
4K Sector
2
15(2)
s
Erase
Program
75
35
mA
mA
VDD3VFL current consumption during the Erase/
Program cycle
(4)
IDD3VFLP
VDD current consumption during Erase/
Program cycle
(4)
IDDP
140
20
mA
mA
VDDIO current consumption during Erase/
Program cycle
(4)
IDDIOP
(1) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
•
•
•
the code that uses flash API to program the flash
the Flash API itself
Flash data to be programmed
(2) The parameters mentioned in the MAX column are for the first 100 Erase/Program cycles.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
before programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brownout or interruption to power during erasing/
programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during flash
programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed during
the programming process.
8.14.6.4 Flash/OTP Access Timing
PARAMETER
MIN
36
MAX UNIT
ta(fp)
ta(fr)
Paged flash access time
Random flash access time
ns
ns
36
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PARAMETER
MIN
MAX UNIT
ta(OTP)
OTP access time
60
ns
8.14.6.5 Flash Data Retention Duration
PARAMETER
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX UNIT
tretention
Data retention duration
years
Table 8-2. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT
(MHz)
FLASH PAGE
WAIT-STATE
FLASH RANDOM
WAIT-STATE(1)
SYSCLKOUT (ns)
OTP WAIT-STATE
100
75
60
50
30
25
15
4
10
13.33
16.67
20
3
2
2
1
1
0
0
0
3
2
2
1
1
1
1
1
5
4
3
2
1
1
1
1
33.33
40
66.67
250
(1) Random wait-state must be greater than or equal to 1.
Equations to compute the Flash page wait-state and random wait-state in Table 8-2 are as follows:
ta(fp)
Flash Page Wait-State
+
ǒ Ǔ* 1
ƪ ƫ(round up to the next highest integer) or 0, whichever is larger
tc(SCO)
ta(fr)
(round up to the next highest integer) or 1, whichever is larger
Flash Random Wait-State
+
ǒ Ǔ* 1
ƪ ƫ
tc(SCO)
Equation to compute the OTP wait-state in Table 8-2 is as follows:
ta(OTP)
OTP Wait-State
+
ǒ Ǔ* 1
ƪ ƫ(round up to the next highest integer) or 1, whichever is larger
tc(SCO)
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8.15 On-Chip Analog-to-Digital Converter
8.15.1 ADC Electrical Characteristics
over recommended operating conditions
PARAMETER(1) (2)
MIN
TYP
MAX
UNIT
Bits
DC SPECIFICATIONS
Resolution
12
0.001
0.001
0.001
60-MHz device
7.5
12.5
25
ADC clock
100-MHz device
MHz
100-MHz device (F2809 only)
ACCURACY
1–12.5 MHz ADC clock (6.25 MSPS)
12.5–25 MHz ADC clock (12.5 MSPS)
±1.5
±2
INL (Integral nonlinearity)
LSB
DNL (Differential nonlinearity)(3)
Offset error(4)
±1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
–60
+60
Offset error with hardware trimming
Overall gain error with internal reference(5)
Overall gain error with external reference
Channel-to-channel offset variation
Channel-to-channel gain variation
ANALOG INPUT
±4
–60
–60
+60
+60
±4
±4
Analog input voltage (ADCINx to ADCLO)(6)
0
3
5
V
ADCLO
–5
0
mV
pF
μA
Input capacitance
10
Input leakage current
±5
INTERNAL VOLTAGE REFERENCE (5)
VADCREFP - ADCREFP output voltage at the pin
based on internal reference
1.275
0.525
V
V
VADCREFM - ADCREFM output voltage at the pin
based on internal reference
Voltage difference, ADCREFP - ADCREFM
0.75
50
V
Temperature coefficient
PPM/°C
EXTERNAL VOLTAGE REFERENCE (5) (7)
ADCREFSEL[15:14] = 11b
ADCREFSEL[15:14] = 10b
ADCREFSEL[15:14] = 01b
1.024
1.500
2.048
V
V
V
VADCREFIN - External reference voltage input on
ADCREFIN pin 0.2% or better accurate
reference recommended
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio +
distortion
67.5
dB
SNR (100 kHz) Signal-to-noise ratio
68
–79
10.9
83
dB
dB
THD (100 kHz) Total harmonic distortion
ENOB (100 kHz) Effective number of bits
SFDR (100 kHz) Spurious free dynamic range
Bits
dB
(1) Tested at 12.5 MHz ADCCLK.
(2) All voltages listed in this table are with respect to VSSA2
(3) TI specifies that the ADC will have no missing codes.
(4) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
.
(5) A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal
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reference is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external
reference option will depend on the temperature profile of the source used.
(6) Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
(7) TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
8.15.2 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
t
d(BGR)
PWDNADC
t
d(PWD)
Request for
ADC
Conversion
Figure 8-23. ADC Power-Up Control Bit Timing
8.15.2.1 ADC Power-Up Delays
PARAMETER(1)
MIN
TYP
MAX
UNIT
ms
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register
(ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
td(BGR)
5
Delay time for power-down control to be stable. Bit delay time for band-gap reference
to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0) must be set to
1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3 register
20
50
μs
td(PWD)
1
ms
(PWDNADC)must be set to 1 before any ADC conversions are initiated.
(1) Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waiting
td(BGR) ms before first conversion.
8.15.2.2 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)
ADC OPERATING MODE(1)
CONDITIONS
BG and REF enabled
VDDA18
VDDA3.3
UNIT
(2)
•
•
Mode A (Operational Mode):
30
2
mA
PWD disabled
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
Mode B:
Mode C:
Mode D:
9
5
5
0.5
20
15
mA
μA
μA
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
(1) Test Conditions:
SYSCLKOUT = 100 MHz
ADC module clock = 12.5 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO
.
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R
on
Switch
R
s
ADCIN0
1 kΩ
C
C
h
p
Source
Signal
ac
10 pF
1.64 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R ):
on
Sampling Capacitor (C ):
1 kΩ
1.64 pF
h
Parasitic Capacitance (C ): 10 pF
p
Source Resistance (R ):
s
50 Ω
Figure 8-24. ADC Analog Input Impedance Model
8.15.3 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time.
These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
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8.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx).
The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC
signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on every Sample/Hold pulse.
The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are
set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled at every
falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock
wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Sample n
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger from
ePWM or Other Sources
t
SH
Figure 8-25. Sequential Sampling Mode (Single-Channel) Timing
8.15.4.1 Sequential Sampling Mode Timing
AT 12.5 MHz
ADC CLOCK,
SAMPLE n
SAMPLE n + 1
REMARKS
tc(ADCCLK) = 80 ns
Delay time from event trigger to
sampling
td(SH)
2.5tc(ADCCLK)
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
Acqps value = 0–15
ADCTRL1[8:11]
tSH
80 ns with Acqps = 0
320 ns
Delay time for first result to appear
in Result register
td(schx_n)
td(schx_n+1)
4tc(ADCCLK)
Delay time for successive results to
appear in Result register
(2 + Acqps) *
tc(ADCCLK)
160 ns
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8.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to
A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external
ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected channels on every Sample/
Hold pulse. The conversion time and latency of the result register update are explained below. The ADC interrupt
flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled
simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed
to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Note
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7, and not in
other combinations (such as A1/B3, and so forth).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschA0_n+1
t
SH
ADC Event Trigger from
ePWM or Other Sources
t
t
dschA0_n
dschB0_n+1
t
dschB0_n
Figure 8-26. Simultaneous Sampling Mode Timing
8.15.5.1 Simultaneous Sampling Mode Timing
AT 12.5 MHz
ADC CLOCK,
SAMPLE n
SAMPLE n + 1
REMARKS
tc(ADCCLK) = 80 ns
Delay time from event trigger to
sampling
td(SH)
2.5tc(ADCCLK)
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
Acqps value = 0–15
ADCTRL1[8:11]
tSH
80 ns with Acqps = 0
320 ns
Delay time for first result to
appear in Result register
td(schA0_n)
td(schB0_n )
td(schA0_n+1)
td(schB0_n+1 )
4tc(ADCCLK)
5tc(ADCCLK)
Delay time for first result to
appear in Result register
400 ns
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
(3 + Acqps) * tc(ADCCLK)
240 ns
Delay time for successive results
to appear in Result register
240 ns
8.15.6 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as
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level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(
)
SINAD * 1.76
N +
6.02
it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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8.16 Migrating From F280x Devices to C280x Devices
8.16.1 Migration Issues
The migration issues to be considered while migrating from the F280x devices to C280x devices are as follows:
•
•
The 1K OTP memory available in F280x devices has been replaced by 1K ROM C280x devices.
Current consumption differs for F280x and C280x devices for all four possible modes. See the appropriate
electrical section for exact numbers.
•
•
The VDD3VFL pin is the 3.3-V Flash core power pin in F280x devices but is a VDDIO pin in C280x devices.
F280x and C280x devices are pin-compatible and code-compatible; however, they are electrically different
with different EMI/ESD profiles. Before ramping production with C280x devices, evaluate performance of the
hardware design with both devices.
•
•
Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF0 through 0x3F 7FF5 in the
main ROM array are reserved for ROM part-specific information and are not available for user applications.
The paged and random wait-state specifications for the Flash and ROM parts are different. While migrating
from Flash to ROM parts, the same wait-state values must be used for best-performance compatibility (for
example, in applications that use software delay loops or where precise interrupt latencies are critical).
The analog input switch resistance is smaller in C280x devices compared to F280x devices. While migrating
from a Flash to a ROM device care should be taken to design the analog input circuits to meet the application
performance required by the sampling network.
•
•
•
The PART-ID register value is different for Flash and ROM parts.
From a silicon functionality/errata standpoint, rev A ROM devices are equivalent to rev C flash devices. See
the errata applicable to 280x devices for details.
•
As part of the ROM code generation process, all unused memory locations in the customer application are
automatically filled with 0xFFFF. Unused locations should not be manually filled with any other data.
Note
Requests for ROM versions of the F280x device are not accepted by TI anymore.
For errata applicable to 280x devices, see the TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon
errata.
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8.17 ROM Timing (C280x only)
8.17.1 ROM/OTP Access Timing
PARAMETER
MIN
19
MAX
UNIT
ns
ta(rp)
Paged ROM access time
ta(rr)
Random ROM access time
19
ns
ta(ROM)
ROM (OTP area) access time (1)
60
ns
(1) In C280x devices, a 1K X 16 ROM block replaces the OTP block found in Flash devices.
Table 8-3. ROM/ROM (OTP area) Minimum Required
Wait-States at Different Frequencies
SYSCLKOUT
(MHz)
SYSCLKOUT
(ns)
PAGE WAIT- RANDOM WAIT-
STATE
STATE(1)
100
75
50
30
25
15
4
10
13.33
20
1
1
0
0
0
0
0
1
1
1
1
1
1
1
33.33
40
66.67
250
(1) Random wait-state must be greater than or equal to 1.
Equations to compute the page wait-state and random wait-state in Table 8-3 are as follows:
ta(rp)
+
ǒ Ǔ* 1
ROM Page Wait-State ƪ ƫ(round up to the next highest integer) or 0, whichever is larger
tc(SCO)
ta(rr)
+
ǒ Ǔ* 1
ƪ ƫ(round up to the next highest integer) or 1, whichever is larger
ROM Random Wait-State
tc(SCO)
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9 Detailed Description
9.1 Brief Descriptions
9.1.1 C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is a very
efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language,
but also enables math algorithms to be developed using C/C++. The C28x is as efficient in DSP math tasks as it
is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need
for a second processor in many systems. The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing
capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise
demand a more expensive floating-point processor solution. Add to this the fast interrupt response with
automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous
events with minimal latency. The C28x has an 8-level-deep protected pipeline with pipelined memory accesses.
This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories.
Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store
conditional operations further improve performance.
9.1.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to
the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be
summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
9.1.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the 280x
devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16
or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on the 280x.
One version only supports 16-bit accesses (called peripheral frame 2). The other version supports both 16- and
32-bit accesses (called peripheral frame 1).
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9.1.4 Real-Time JTAG and Analysis
The 280x implements the standard IEEE 1149.1 JTAG interface. Additionally, the 280x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through non-
time critical code while enabling time-critical interrupts to be serviced without interference. The 280x implements
the real-time mode in hardware within the CPU. This is a unique feature to the 280x, no software monitor is
required. Additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or
data/address watch-points and generate various user-selectable break events when a match occurs.
9.1.5 Flash
The F2809 contains 128K x 16 of embedded flash memory, segregated into eight 16K x 16 sectors. The F2808
contains 64K x 16 of embedded flash memory, segregated into four 16K x 16 sectors. The F2806 and F2802
have 32K x 16 of embedded flash, segregated into four 8K x 16 sectors. The F2801 device contains 16K x 16 of
embedded flash, segregated into four 4K x 16 sectors. All five devices also contain a single 1K x 16 of OTP
memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a
flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or
the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to
enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data
space; therefore, it can be used to execute code or store data information. Note that addresses 0x3F7FF0 –
0x3F7FF5 are reserved for data variables and should not contain program code.
Note
The F2809/F2808/F2806/F2802/F2801 Flash and OTP wait-states can be configured by the
application. This allows applications running at slower frequencies to configure the flash to use fewer
wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the
TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide.
9.1.6 ROM
The C2802 contains 32K x 16 of ROM, while the C2801 contains 16K x 16 of ROM.
Note
Requests for ROM devices are not accepted by TI anymore.
9.1.7 M0, M1 SARAMs
All 280x devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or
for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory
map to the programmer. This makes for easier programming in high-level languages.
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9.1.8 L0, L1, H0 SARAMs
The F2809 and F2808 each contain an additional 16K x 16 of single-access RAM, divided into three blocks
(L0-4K, L1-4K, H0-8K). The F2806 contains an additional 8K x 16 of single-access RAM, divided into two blocks
(L0-4K, L1-4K). The F2802, F2801, C2802, and C2801 each contain an additional 4K x 16 of single-access RAM
(L0-4K). Each block can be independently accessed to minimize CPU pipeline stalls. Each block is mapped to
both program and data space.
9.1.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal Flash/
ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related
algorithms.
Table 9-1. Boot Mode Selection
GPIO18
GPIO29
MODE
DESCRIPTION
SPICLKA
SCITXDB
GPIO34
SCITXDA
Jump to Flash/ROM address 0x3F 7FF6
Boot to Flash/ROM
You must have programmed a branch instruction here prior
to reset to redirect code execution as desired.
1
1
1
SCI-A Boot
SPI-A Boot
Load a data stream from SCI-A
1
1
1
0
0
1
Load from an external serial SPI EEPROM on SPI-A
Load data from an external EEPROM at address 0x50 on
the I2C bus
I2C Boot
1
0
0
eCAN-A Boot
Call CAN_Boot to load from eCAN-A mailbox 1.
Jump to M0 SARAM address 0x00 0000.
Jump to OTP address 0x3D 7800
0
0
0
0
1
1
0
0
1
0
1
0
Boot to M0 SARAM
Boot to OTP
Parallel I/O Boot
Load data from GPIO0 - GPIO15
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9.1.10 Security
The 280x devices support high levels of security to protect the user firmware from being reverse engineered.
The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash.
One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security
feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code
from external memory or trying to boot-load some undesirable software that would export the secure memory
contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which
matches the value stored in the password locations within the Flash.
Note
The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would
permanently lock the device.
Note
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR
FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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9.1.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the 280x, 43 of the possible 96 interrupts are used by peripherals.
The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to
INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be
overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU
clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt
events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be
enabled/disabled within the PIE block.
9.1.12 External Interrupts (XINT1, XINT2, XNMI)
The 280x supports three masked external interrupts (XINT1, XINT2, XNMI). XNMI can be connected to the
INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative
and positive edge triggering and can also be enabled/disabled (including the XNMI). The masked interrupts also
contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This
counter can be used to accurately time stamp the interrupt. Unlike the 281x devices, there are no dedicated pins
for the external interrupts. Rather, any Port A GPIO pin can be configured to trigger any external interrupt.
9.1.13 Oscillator and PLL
The 280x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL
is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software,
enabling the user to scale back on operating frequency if lower power operation is desired. See Section 8 for
timing details. The PLL block can be set in bypass mode.
9.1.14 Watchdog
The 280x devices contain a watchdog timer. The user software must regularly reset the watchdog counter within
a certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
9.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) and the ADC
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from
increasing CPU clock speeds.
9.1.16 Low-Power Modes
The 280x devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog
timer will wake the processor from IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible
power consumption mode. A reset or external signal can wake the device from this mode.
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9.1.17 Peripheral Frames 0, 1, 2 (PFn)
The 280x segregate peripherals into three sections. The mapping of peripherals is as follows:
PF0:
PF1:
PF2:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
Flash:
Timers:
CSM:
ADC:
eCAN:
GPIO:
ePWM:
eCAP:
eQEP:
SYS:
Code Security Module KEY Registers
ADC Result Registers (dual-mapped)
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
SPI:
ADC:
I2C:
Inter-Integrated Circuit Module and Registers
9.1.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables
the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured
as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific
inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches.
The GPIO signals can also be used to bring the device out of specific low-power modes.
9.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the SYS/BIOS Real-
Time OS, and is connected to INT14 of the CPU. If SYS/BIOS is not being used, CPU-Timer 2 is available for
general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for
general use and is connected to the PIE block.
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9.1.20 Control Peripherals
The 280x devices support the following peripherals which are used for embedded control and communication:
ePWM:
eCAP:
eQEP:
The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band
generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some of the PWM pins support
HRPWM features.
The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture
unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous
edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter, single-ended, 16-channels. It contains two sample-and-hold units for
simultaneous sampling.
9.1.21 Serial Port Peripherals
The 280x devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is
compliant with ISO11898-1 (CAN 2.0B).
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to
sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used
for communications between the DSP controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. On the 280x,
the SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
I2C:
The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. On the
280x, the SCI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between a DSP and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP
through the I2C module. On the 280x, the I2C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
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9.2 Peripherals
The integrated peripherals of the 280x are described in the following subsections:
•
•
•
•
•
•
•
•
•
•
Three 32-bit CPU-Timers
Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)
Up to four enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4)
Up to two enhanced QEP modules (eQEP1, eQEP2)
Enhanced analog-to-digital converter (ADC) module
Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
Up to two serial communications interface modules (SCI-A, SCI-B)
Up to four serial peripheral interface (SPI) modules (SPI-A, SPI-B, SPI-C, SPI-D)
Inter-integrated circuit module (I2C)
Digital I/O and shared pin functions
9.2.1 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the 280x devices (CPU-TIMER0/1/2).
CPU-Timer 0 and CPU-Timer 1 can be used in user applications. Timer 2 is reserved for SYS/BIOS. These
timers are different from the timers that are present in the ePWM modules.
Note
If the application is not using SYS/BIOS, then CPU-Timer 2 can be used in the application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 9-1. CPU-Timers
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In the 280x devices, the timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in Figure 9-2.
INT1
to
INT12
TINT0
PIE
CPU-TIMER 0
C28x
TINT1
INT13
INT14
CPU-TIMER 1
XINT13
CPU-TIMER 2
(Reserved for
SYS/BIOS)
TINT2
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 9-2. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value
in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in
Table 9-2 are used to configure the timers. For more information, see the TMS320x280x, 2801x, 2804x DSP
system control and interrupts reference guide.
Table 9-2. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
TIMER0TIM
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
0x0C12
0x0C13
0x0C14
0x0C15
0x0C16
SIZE (x16)
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CPU-Timer 0, Counter Register
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
Reserved
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
Reserved
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
Reserved
TIMER2TPR
CPU-Timer 2, Prescale Register
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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Table 9-2. CPU-Timers 0, 1, 2 Configuration and Control Registers (continued)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
TIMER2TPRH
Reserved
0x0C17
1
CPU-Timer 2, Prescale Register High
0x0C18 –
0x0C3F
40
Reserved
9.2.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6)
The 280x device contains up to six enhanced PWM modules (ePWM). Figure 9-3 shows a block diagram of
multiple ePWM modules. Figure 9-4 shows the signal interconnections with the ePWM. See the TMS320x280x,
2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide for more details.
EPWM1SYNCI
EPWM1SYNCI
EPWM1INT
EPWM1A
EPWM1SOC
ePWM1 Module
EPWM1B
TZ1 to TZ6
EPWM1SYNCO
EPWM2SYNCI
To eCAP1
Module
(Sync in)
EPWM1SYNCO
EPWM2INT
EPWM2A
EPWM2SOC
PIE
ePWM2 Module
EPWM2SYNCO
EPWM2B
GPIO
MUX
TZ1 to TZ6
EPWMxSYNCI
ePWMx Module
EPWMxSYNCO
EPWMxINT
EPWMxA
EPWMxSOC
EPWMxB
TZ1 to TZ6
ADCSOCx0
Peripheral Bus
ADC
Copyright © 2016, Texas Instruments Incorporated
Figure 9-3. Multiple PWM Modules in a 280x System
Table 9-3 shows the complete ePWM register set per module.
Table 9-3. ePWM Control and Status Registers
SIZE (x16) /
#SHADOW
NAME
ePWM1 ePWM2 ePWM3 ePWM4
0x6800 0x6840 0x6880 0x68C0
ePWM5
ePWM6
DESCRIPTION
TBCTL
0x6900
0x6940
1 / 0
Time Base Control Register
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Table 9-3. ePWM Control and Status Registers (continued)
SIZE (x16) /
#SHADOW
NAME
ePWM1 ePWM2 ePWM3 ePWM4
ePWM5
0x6901
N/A
ePWM6
0x6941
N/A
DESCRIPTION
TBSTS
0x6801
0x6802
0x6841
0x6842
0x6881
0x6882
0x68C1
0x68C2
1 / 0
Time Base Status Register
TBPHSH
R
1 / 0
Time Base Phase HRPWM Register
TBPHS
TBCTR
TBPRD
CMPCTL
0x6803
0x6804
0x6805
0x6807
0x6843
0x6844
0x6845
0x6847
0x6848
0x6849
0x684A
0x6883
0x6884
0x6885
0x6887
0x6888
0x6889
0x688A
0x68C3
0x68C4
0x68C5
0x68C7
0x68C8
0x68C9
0x68CA
0x6903
0x6904
0x6905
0x6907
N/A
0x6943
0x6944
0x6945
0x6947
N/A
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
CMPAHR 0x6808
CMPA
CMPB
0x6809
0x680A
0x6909
0x690A
0x6949
0x694A
Action Qualifier Control Register For
Output A
AQCTLA
AQCTLB
0x680B
0x680C
0x684B
0x688B
0x68CB
0x690B
0x694B
1 / 0
Action Qualifier Control Register For
Output B
0x684C
0x684D
0x684E
0x684F
0x6850
0x688C 0x68CC
0x688D 0x68CD
0x690C
0x690D
0x690E
0x690F
0x6910
0x694C
0x694D
0x694E
0x694F
0x6950
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
AQSFRC 0x680D
Action Qualifier Software Force Register
AQCSFR
0x680E
C
Action Qualifier Continuous S/W Force
Register Set
0x688E
0x688F
0x6890
0x68CE
0x68CF
0x68D0
DBCTL
DBRED
0x680F
0x6810
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
Count Register
Dead-Band Generator Falling Edge Delay
Count Register
DBFED
0x6811
0x6851
0x6891
0x68D1
0x6911
0x6951
1 / 0
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
ETSEL
ETPS
0x6812
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6852
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6892
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x68D2
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x6912
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6952
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Trip Zone Select Register(1)
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETFLG
ETCLR
ETFRC
PCCTL
0x689C 0x68DC
0x689D 0x68DD
0x689E
0x68A0
0x68DE
0x68E0
HRCNFG 0x6820
0x6920(2) 0x6960(2)
(1) Registers that are EALLOW protected.
(2) Applicable to F2809 only
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Time-Base (TB)
Sync
CTR = ZERO
CTR = CMPB
Disabled
In/Out
Select
Mux
TBPRD Shadow (16)
TBPRD Active (16)
EPWMxSYNCO
CTR = PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
EPWMxSYNCI
Counter
Up/Down
(16-Bit)
TBCTL[SWFSYNC]
(Software-Forced Sync)
CTR = ZERO
CTR_Dir
TBCNT
Active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
CTR = CMPA
CTR = CMPB
CTR_Dir
Phase
Control
Event
Trigger
and
Interrupt
(ET)
EPWMxINT
TBPHS Active (24)
EPWMxSOCA
EPWMxSOCB
Counter Compare (CC)
Action
Qualifier
(AQ)
CTR = CMPA
CMPAHR (8)
16
8
HiRes PWM (HRPWM)
CMPA Active (24)
EPWMA
EPWMxAO
CMPA Shadow (24)
Dead
Band
(DB)
PWM
Chopper
(PC)
Trip
Zone
(TZ)
CTR = CMPB
16
EPWMB
EPWMxBO
CMPB Active (16)
EPWMxTZINT
TZ1 to TZ6
CMPB Shadow (16)
CTR = ZERO
Copyright © 2016, Texas Instruments Incorporated
Figure 9-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
9.2.3 Hi-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
Typically used when effective PWM resolution falls below ~ 9–10 bits. This occurs at PWM frequencies
greater than ~200 kHz when using a CPU/System clock of 100 MHz.
•
•
This capability can be utilized in both duty cycle and phase-shift control methods.
Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase
registers of the ePWM module.
•
HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
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9.2.4 Enhanced CAP Modules (eCAP1/2/3/4)
The 280x device contains up to four enhanced capture (eCAP) modules. Figure 9-5 shows a functional block
diagram of a module. See the TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module reference guide
for more details.
CTRPHS
(Phase Register - 32-bit)
APWM Mode
SYNCIn
CTR_OVF
OVF
CTR [0-31]
PRD [0-31]
CMP [0-31]
TSCTR
(Counter - 32-bit)
SYNCOut
PWM
Compare
Logic
Delta Mode
RST
32
CTR=PRD
CTR=CMP
CTR [0-31]
PRD [0-31]
32
32
LD1
CAP1
(APRD Active)
Polarity
Select
eCAPx
LD
APRD
Shadow
32
CMP [0-31]
32
Polarity
Select
LD2
32
CAP2
(ACMP Active)
LD
Event
Qualifier
ACMP
Shadow
Event
Prescale
32
Polarity
Select
LD3
LD4
32
32
CAP3
(APRD Shadow)
LD
CAP4
(ACMP Shadow)
Polarity
Select
LD
4
Capture Events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Control
Continuous/
One-Shot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Copyright © 2016, Texas Instruments Incorporated
Figure 9-5. eCAP Functional Block Diagram
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1/2/3/4ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules
individually (for low power operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, and
ECAP4ENCLK are set to low, indicating that the peripheral clock is off.
Table 9-4. eCAP Control and Status Registers
SIZE
(x16)
NAME
TSCTR
eCAP1
eCAP2
eCAP3
eCAP4
DESCRIPTION
Time-Stamp Counter
0x6A00
0x6A02
0x6A04
0x6A06
0x6A08
0x6A0A
0x6A20
0x6A22
0x6A24
0x6A26
0x6A28
0x6A2A
0x6A40
0x6A42
0x6A44
0x6A46
0x6A48
0x6A4A
0x6A60
0x6A62
0x6A64
0x6A66
0x6A68
0x6A6A
2
2
2
2
2
2
CTRPHS
CAP1
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
0x6A0C –
0x6A12
0x6A2C –
0x6A32
0x6A4C –
0x6A52
0x6A6C –
0x6A72
Reserved
8
Reserved
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
0x6A14
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
0x6A34
0x6A35
0x6A36
0x6A37
0x6A38
0x6A39
0x6A54
0x6A55
0x6A56
0x6A57
0x6A58
0x6A59
0x6A74
0x6A75
0x6A76
0x6A77
0x6A78
0x6A79
1
1
1
1
1
1
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
0x6A1A –
0x6A1F
0x6A3A –
0x6A3F
0x6A5A –
0x6A5F
0x6A7A –
0x6A7F
Reserved
6
Reserved
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9.2.5 Enhanced QEP Modules (eQEP1/2)
The 280x device contains up to two enhanced quadrature encoder (eQEP) modules. See the TMS320x280x,
2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide for more details.
System Control
Registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
Capture
Unit
QCTMRLAT
QCPRDLAT
(QCAP)
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
16
PIE
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) Peripheral
Copyright © 2016, Texas Instruments Incorporated
Figure 9-6. eQEP Functional Block Diagram
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Table 9-5 provides a summary of the eQEP registers.
Table 9-5. eQEP Control and Status Registers
eQEP1
SIZE(x16)/
#SHADOW
eQEP1
ADDRESS
eQEP2
ADDRESS
NAME
REGISTER DESCRIPTION
QPOSCNT
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
0x6B40
0x6B42
0x6B44
0x6B46
0x6B48
0x6B4A
0x6B4C
0x6B4E
0x6B50
0x6B52
0x6B53
0x6B54
0x6B55
0x6B56
0x6B57
0x6B58
0x6B59
0x6B5A
0x6B5B
0x6B5C
0x6B5D
0x6B5E
0x6B5F
0x6B60
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
eQEP Position Counter
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
0x6B21–
0x6B3F
0x6B61 –
0x6B7F
Reserved
31/0
Reserved
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9.2.6 Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 9-7. The ADC module consists of a
12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be
programmed to select anyone of 16 input channels
•
•
Sequencer can be operated as two independent 8-channel sequencers or as one large 16-channel
sequencer (that is, two cascaded 8-channel sequencers)
Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
, when ADCIN £ ADCLO
, when ADCLO < ADCIN < 3 V
, when ADCIN ³ 3 V
Digital Value = 0
ADCIN - ADCLO
4096 ´
(
Digital Value = floor
(
3
Digital Value = 4095
A. All fractional values are truncated.
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM start of conversion
– XINT2 ADC start of conversion
•
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize
conversions.
•
•
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals. The ADC
interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25-MHz ADC
clock. The ADC module has a 16-channel sequencer, configurable as two independent 8-channel sequencers.
The two independent 8-channel sequencers can be cascaded to form a 16-channel sequencer. Although there
are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 9-7
shows the block diagram of the ADC module.
The two 8-channel sequencer modules have the capability to autosequence a series of conversions, each
module has the choice of selecting any one of the respective eight channels available through an analog MUX.
In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer,
once the conversion is complete, the selected channel value is stored in its respective RESULT register.
Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform
oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
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SYSCLKOUT
System
Control Block
High-Speed
Prescaler
DSP
ADCENCLK
HALT
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
Result Reg 1
ADCINA0
70A8h
S/H
ADCINA7
ADCINB0
ADCINB7
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
S/W
Sequencer 1
Sequencer 2
EPWMSOCA
SOC
SOC
EPWMSOCB
GPIO/XINT2_
ADCSOC
Figure 9-7. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDD1A18, VDD2A18, VDDA2, VDDAIO) from the
digital supply. Figure 9-8 and Figure 9-9 show the ADC pin connections for the 280x devices.
Note
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module
is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as
follows:
•
ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) the clock to the
register will still function. This is necessary to make sure all registers and modes go into their
default reset state. The analog module, however, will be in a low-power inactive state. As soon
as reset goes high, then the clock to the registers will be disabled. When the user sets the
ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module
will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can
be used.
•
HALT: This mode only affects the analog module. It does not affect the registers. In this mode,
the ADC module goes into low-power mode. This mode also will stop the clock to the CPU,
which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.
Figure 9-8 shows the ADC pin-biasing for internal reference and Figure 9-9 shows the ADC pin-biasing for
external reference.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0-3 V with respect to ADCLO
Connect to analog ground
Float or ground if internal reference is used
ADCREFIN
22 k
ADC External Current Bias Resistor
ADCRESEXT
2.2 μF(A)
2.2 μF(A)
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Power
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
ADC Analog and Reference I/O Power
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 9-8. ADC Pin Connections With Internal Reference
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ADCINA[7:0]
ADC 16-Channel Analog Inputs
Analog input 0-3 V with respect to ADCLO
ADCINB[7:0]
ADCLO
ADCREFIN
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source(D)
22 k
ADC External Current Bias Resistor
ADCRESEXT
ADCREFP
2.2 μF(A)
2.2 μF(A)
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP and ADCREFM should not
be loaded by external circuitry
ADCREFM
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.8 V)
ADC Analog Power Pin (1.8 V)
ADC Analog Ground Pin
ADC Analog Power
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
ADC Analog and Reference I/O Power
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on the voltage used
on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracy will be determined by accuracy
of this voltage source.
Figure 9-9. ADC Pin Connections With External Reference
Note
The temperature rating of any recommended component must match the rating of the end product.
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9.2.6.1 ADC Connections if the ADC Is Not Used
It is recommended to keep the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
•
•
•
•
•
•
•
•
VDD1A18/VDD2A18 – Connect to VDD
VDDA2, VDDAIO – Connect to VDDIO
VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS
ADCLO – Connect to VSS
ADCREFIN – Connect to VSS
ADCREFP/ADCREFM – Connect a 100-nF cap to VSS
ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS
ADCINAn, ADCINBn - Connect to VSS
.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSS1AGND/VSS2AGND
)
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TMS320C2801, TMS320F28016, TMS320F28015
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9.2.6.2 ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 9-6.
Table 9-6. ADC Registers
NAME(1)
ADCTRL1
ADDRESS(1) ADDRESS(2) SIZE (x16)
DESCRIPTION
0x7100
0x7101
0x7102
0x7103
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x710D
0x710E
0x710F
0x7110
0x7111
0x7112
0x7113
0x7114
0x7115
0x7116
0x7117
0x7118
0x7119
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1
ADC Control Register 2
ADCTRL2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
0x0B00
0x0B01
0x0B02
0x0B03
0x0B04
0x0B05
0x0B06
0x0B07
0x0B08
0x0B09
0x0B0A
0x0B0B
0x0B0C
0x0B0D
0x0B0E
0x0B0F
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x711A –
0x711B
Reserved
2
Reserved
ADCREFSEL
ADCOFFTRIM
0x711C
0x711D
1
1
ADC Reference Select Register
ADC Offset Trim Register
0x711E –
0x711F
Reserved
2
Reserved
(1) The registers in this column are Peripheral Frame 2 Registers.
(2) The ADC result registers are dual mapped in the 280x DSP. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait-states and
left justified. Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high-speed/continuous
conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory.
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9.2.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
•
•
•
Fully compliant with CAN protocol, version 2.0B
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
•
•
•
•
•
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps.
For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps.
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eCAN0INT
eCAN1INT
Controls Address
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 x 32-Bit Words
Message Objects Control
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 9-10. eCAN Block Diagram and Interface Circuit
Table 9-7. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–
–
–
–
–
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
Yes
Sleep
Yes
None
None
None
None
None
None
Standby
Adjustable
Diagnostic
Loopback
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Standby & Sleep
Standby
Adjustable
Adjustable
None
None
–
–40°C to 125°C
–40°C to 125°C
Autobaud
Loopback
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eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
Control and Status Registers
6000h
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
603Fh
6040h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
607Fh
6080h
Master Control - CANMC
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
60BFh
60C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
60FFh
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
6108h-610Fh
6110h-6117h
6118h-611Fh
6120h-6127h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
61E8h-61EFh
61F0h-61F7h
61F8h-61FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
61E8h-61E9h
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
Figure 9-11. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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eCAN-B Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
eCAN-B Memory (512 Bytes)
Control and Status Registers
Abort Acknowledge - CANAA
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
6200h
623Fh
6240h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
627Fh
6280h
Master Control - CANMC
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
62BFh
62C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
62FFh
eCAN-B Memory RAM (512 Bytes)
6300h-6307h
6308h-630Fh
6310h-6317h
6318h-631Fh
6320h-6327h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
63E0h-63E7h
63E8h-63EFh
63F0h-63F7h
63F8h-63FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
63E8h-63E9h
63EAh-63EBh
63ECh-63EDh
63EEh-63EFh
Figure 9-12. eCAN-B Memory Map
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The CAN registers listed in Table 9-8 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 9-8. CAN Register Map
REGISTER
NAME(1)
eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
DESCRIPTION
CANME
CANMD
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
0x6200
0x6202
0x6204
0x6206
0x6208
0x620A
0x620C
0x620E
0x6210
0x6212
0x6214
0x6216
0x6218
0x621A
0x621C
0x621E
0x6220
0x6222
0x6224
0x6226
0x6228
0x622A
0x622C
0x622E
0x6230
0x6232
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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9.2.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
The 280x devices include two serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
NOTE: Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
16
•
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
•
•
100 MHz
Max bit rate =
= 6.25 ´ 6 b/s (for 100 -MHz devices)
10
16
60 MHz
16
Max bit rate =
= 3.75 ´ 6 b/s (for 60 -MHz devices)
10
•
•
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
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Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 9-9 and Table 9-10.
Table 9-9. SCI-A Registers
NAME(1)
SCICCRA
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 9-10. SCI-B Registers
NAME(1) (2)
SCICCRB
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Figure 9-13 shows the SCI module block diagram.
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SCICTL1.1
SCITXD
SCITXD
TXSHF
Register
Frame Format and Mode
Parity
Even/Odd Enable
TXENA
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TX INT ENA
TXRDY
Transmitter-Data
Buffer Register
SCICTL2.7
SCICTL2.0
8
TXWAKE
TXINT
TX FIFO _0
SCICTL1.3
TX Interrupt Logic
TX FIFO _1
- - - - -
To CPU
TX
FIFO
Interrupts
1
SCI TX Interrupt Select Logic
TX FIFO _15
WUT
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
AutoBaud Detect Logic
SCIRXD
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
RXRDY
RX/BK INT ENA
Receive-Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
- - - - -
RX
FIFO
Interrupts
RX FIFO _1
RX FIFO _0
RXINT
To CPU
RX Interrupt Logic
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 9-13. Serial Communications Interface (SCI) Module Block Diagram
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9.2.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
The 280x devices include the four-pin serial peripheral interface (SPI) module. Up to four SPI modules (SPI-A,
SPI-B, SPI-C, and SPI-D) are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial
bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable
bit-transfer rate. Normally, the SPI is used for communications between the DSP controller and external
peripherals or another processor. Typical applications include external I/O or peripheral expansion through
devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the
master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
•
Baud rate =
when SPIBRR = 3 to127
(SPIBRR + 1)
LSPCLK
4
when SPIBRR = 0,1, 2
Baud rate =
•
•
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced feature:
•
•
16-level transmit/receive FIFO
Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 9-11 through Table 9-14 .
Table 9-11. SPI-A Registers
SIZE (x16)
NAME
SPICCR
SPICTL
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Baud Rate Register
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 9-12. SPI-B Registers
SIZE (x16)
NAME
SPICCR
SPICTL
ADDRESS
0x7740
0x7741
0x7742
0x7744
0x7746
0x7747
0x7748
0x7749
0x774A
0x774B
0x774C
0x774F
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-B Configuration Control Register
SPI-B Operation Control Register
SPI-B Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-B Baud Rate Register
SPI-B Receive Emulation Buffer Register
SPI-B Serial Input Buffer Register
SPI-B Serial Output Buffer Register
SPI-B Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-B FIFO Transmit Register
SPI-B FIFO Receive Register
SPI-B FIFO Control Register
SPI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Table 9-13. SPI-C Registers
SIZE (x16)
NAME
SPICCR
SPICTL
ADDRESS
0x7760
0x7761
0x7762
0x7764
0x7766
0x7767
0x7768
0x7769
0x776A
0x776B
0x776C
0x776F
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-C Configuration Control Register
SPI-C Operation Control Register
SPI-C Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-C Baud Rate Register
SPI-C Receive Emulation Buffer Register
SPI-C Serial Input Buffer Register
SPI-C Serial Output Buffer Register
SPI-C Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-C FIFO Transmit Register
SPI-C FIFO Receive Register
SPI-C FIFO Control Register
SPI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 9-14. SPI-D Registers
SIZE (x16)
NAME
SPICCR
SPICTL
ADDRESS
0x7780
0x7781
0x7782
0x7784
0x7786
0x7787
0x7788
0x7789
0x778A
0x778B
0x778C
0x778F
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
SPI-D Configuration Control Register
SPI-D Operation Control Register
SPI-D Status Register
SPISTS
SPIBRR
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-D Baud Rate Register
SPI-D Receive Emulation Buffer Register
SPI-D Serial Input Buffer Register
SPI-D Serial Output Buffer Register
SPI-D Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-D FIFO Transmit Register
SPI-D FIFO Receive Register
SPI-D FIFO Control Register
SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Figure 9-14 is a block diagram of the SPI in slave mode.
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SPIFFENA
SPIFFTX.14
Overrun
INT ENA
Receiver
Overrun Flag
RX FIFO Registers
SPIRXBUF
RX FIFO _0
RX FIFO _1
- - - - -
SPISTS.7
SPICTL.4
RX
FIFO
Interrupt
RX FIFO _15
SPIINT/SPIRXINT
To CPU
RX Interrupt
Logic
16
SPIFFOVF
FLAG
SPIRXBUF Buffer Register
SPIFFRX.15
TX
FIFO
Interrupt
TX FIFO Registers
TX Interrupt
Logic
SPITXBUF
SPITXINT
TX FIFO _15
- - - - -
SPI
INT FLAG
SPI
INT ENA
TX FIFO _1
16
SPISTS.6
TX FIFO _0
SPICTL.0
16
SPITXBUF Buffer Register
16
M
S
M
S
SW1
SW2
SPIDAT Data Register
SPISIMO
M
S
M
S
SPIDAT.15 - 0
SPISOMI
Talk
SPICTL.1
SPISTE(A)
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 - 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
SPICCR.6
SPICTL.3
LSPCLK
SPICLK
SPIBRR.6 - 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 9-14. SPI Module Block Diagram (Slave Mode)
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9.2.10 Inter-Integrated Circuit (I2C)
The 280x device contains one I2C Serial Port. Figure 9-15 shows how the I2C peripheral module interfaces
within the 280x device.
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 16-word receive FIFO and one 16-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
•
•
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module enable/disable capability
Free data format mode
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System Control Block
C28x CPU
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
Data[16]
SDAA
SCLA
I2C-A
Addr[16]
I2CINT1A
I2CINT2A
GPIO
MUX
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 9-15. I2C Peripheral Module Interfaces
The registers in Table 9-15 configure and control the I2C port operation.
Table 9-15. I2C-A Registers
NAME
I2COAR
I2CIER
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
-
DESCRIPTION
I2C own address register
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
-
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9.2.11 GPIO MUX
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in
addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in
Figure 9-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins
differ. See the TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide for details.
GPIOXINT1SEL
GPIOLMPSEL
LPMCR0
GPIOXINT2SEL
GPIOXNMISEL
Low-Power
Modes Block
External Interrupt
MUX
PIE
GPxDAT (read)
Asynchronous
path
GPxQSEL1/2
GPxCTRL
GPxPUD
00
01
N/C
Peripheral 1 Input
Input
Qualification
Internal
Pullup
Peripheral 2 Input
Peripheral 3 Input
10
11
Asynchronous path
GPxTOGGLE
GPxCLEAR
GPxSET
GPIOx pin
00
01
10
11
GPxDAT (latch)
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
High-Impedance
Output Control
00
01
GPxDIR (latch)
Peripheral 1 Output Enable
0 = Input, 1 = Output
XRS
Peripheral 2 Output Enable
Peripheral 3 Output Enable
10
11
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Figure 9-16. GPIO MUX Block Diagram
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The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 9-16 shows the GPIO register
mapping.
Table 9-16. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F80
0x6F82
0x6F84
0x6F86
0x6F88
0x6F8A
0x6F8C
2
2
2
2
2
2
2
GPIO A Control Register (GPIO0 to 31)
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
GPIO A MUX 2 Register (GPIO16 to 31)
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pull Up Disable Register (GPIO0 to 31)
GPAPUD
0x6F8E –
0x6F8F
Reserved
2
Reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F90
0x6F92
0x6F94
0x6F96
0x6F98
0x6F9A
0x6F9C
2
2
2
2
2
2
2
GPIO B Control Register (GPIO32 to 35)
GPIO B Qualifier Select 1 Register (GPIO32 to 35)
Reserved
GPIO B MUX 1 Register (GPIO32 to 35)
Reserved
GPIO B Direction Register (GPIO32 to 35)
GPIO B Pull Up Disable Register (GPIO32 to 35)
GPBPUD
0x6F9E –
0x6F9F
Reserved
Reserved
2
Reserved
Reserved
0x6FA0 –
0x6FBF
32
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
GPASET
0x6FC0
0x6FC2
0x6FC4
0x6FC6
0x6FC8
0x6FCA
0x6FCC
0x6FCE
2
2
2
2
2
2
2
2
GPIO Data Register (GPIO0 to 31)
GPIO Data Set Register (GPIO0 to 31)
GPIO Data Clear Register (GPIO0 to 31)
GPIO Data Toggle Register (GPIO0 to 31)
GPIO Data Register (GPIO32 to 35)
GPACLEAR
GPATOGGLE
GPBDAT
GPBSET
GPIO Data Set Register (GPIO32 to 35)
GPIO Data Clear Register (GPIO32 to 35)
GPIO Data Toggle Register (GPIO32 to 35)
GPBCLEAR
GPBTOGGLE
0x6FD0 –
0x6FDF
Reserved
16
Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
0x6FE0
0x6FE1
0x6FE2
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
0x6FE3 –
0x6FE7
Reserved
GPIOLPMSEL
Reserved
5
2
Reserved
0x6FE8
LPM GPIO Select Register (GPIO0 to 31)
Reserved
0x6FEA –
0x6FFF
22
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
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Table 9-17. F2808 GPIO MUX Table
DEFAULT AT RESET
GPAMUX1/2(3)
REGISTER
BITS
PRIMARY I/O
FUNCTION
(GPxMUX1/2
BITS = 0,0)
PERIPHERAL
SELECTION 1(1)
PERIPHERAL
SELECTION 2
PERIPHERAL
SELECTION 3
(GPxMUX1/2 BITS = 0,1)
(GPxMUX1/2 BITS = 1,0)
(GPxMUX1/2 BITS = 1,1)
GPAMUX1
1–0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
Reserved(2)
SPISIMOD (I/O)
Reserved(2)
Reserved(2)
Reserved(2)
3–2
5–4
Reserved(2)
7–6
SPISOMID (I/O)
Reserved(2)
Reserved(2)
9–8
Reserved(2)
11–10
13–12
15–14
17–16
19–18
21–20
23–22
25–24
27–26
29–28
31–30
SPICLKD (I/O)
EPWMSYNCI (I)
SPISTED (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
ADCSOCAO (O)
ECAP3 (I/O)
ADCSOCBO (O)
ECAP4 (I/O)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ2 (I)
TZ3 (I)
SCITXDB (O)
SCIRXDB (I)
TZ4 (I)
GPAMUX2
1–0
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
SPISIMOC (I/O)
SPISOMIC (I/O)
SPICLKC (I/O)
SPISTEC (I/O)
EQEP2A (I)
TZ5 (I)
TZ6 (I)
3–2
5–4
Reserved(2)
Reserved(2)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
SPISIMOB (I/O)
SPISOMIB (I/O)
SPICLKB (I/O)
SPISTEB (I/O)
TZ5 (I)
7–6
9–8
11–10
13–12
15–14
17–16
19–18
21–20
23–22
25–24
27–26
29–28
31–30
EQEP1B (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
Reserved(2)
Reserved(2)
TZ6 (I)
Reserved(2)
Reserved(2)
Reserved(2)
CANTXA (O)
Reserved(2)
GPBMUX1
1–0
3–2
5–4
GPIO32
GPIO33
GPIO34
SDAA (I/OC)
SCLA (I/OC)
Reserved(2)
EPWMSYNCI (I)
EPWMSYNCO (O)
Reserved(2)
ADCSOCAO (O)
ADCSOCBO (O)
Reserved(2)
(1) This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin
descriptions for more detail.
(2) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of
the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(3) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.
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The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four
choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0,0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2 = 0,1 and 1,0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
Time Between Samples
GPyCTRL Reg
Input Signal
Qualified by
3 or 6 Samples
Qualification
GPIOx
SYNC
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 9-17. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the
same (all 0s or all 1s) as shown in Figure 8-10 (for 6-sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a peripheral
input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input
signal will default to either a 0 or 1 state, depending on the peripheral.
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9.3 Memory Maps
Block Start
Address
Prog Space
Data Space
0x00 0000
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
0x00 0400
0x00 0800
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
0x00 6000
Reserved
Peripheral Frame 1
(protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x00 9000
0x00 A000
0x00 C000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
Reserved
0x3D 7800
OTP
(1K y 16, Secure Zone)
0x3D 7C00
0x3D 8000
Reserved
FLASH
(128K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
0x3F A000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
0x3F C000
0x3F F000
Reserved
Boot ROM (4K y 16)
0x3F FFC0
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-18. F2809 Memory Map
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Block Start
Address
Prog Space
M0 Vector − RAM (32 x 32)
Data Space
0x00 0000
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
0x00 0800
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
0x00 6000
Reserved
Peripheral Frame 1
(protected)
Reserved
0x00 7000
0x00 8000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x00 9000
0x00 A000
0x00 C000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
Reserved
0x3D 7800
0x3D 7C00
OTP
(1K y 16, Secure Zone)
Reserved
0x3E 8000
FLASH
(64K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
0x3F A000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
H0 SARAM (0-wait)
(8K y 16, Dual-Mapped)
0x3F C000
0x3F F000
Reserved
Boot ROM (4K y 16)
0x3F FFC0
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-19. F2808 Memory Map
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Block Start
Address
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
0x00 0800
0x00 0D00
Peripheral Frame 0
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
0x00 6000
Reserved
Peripheral Frame 1
(protected)
0x00 7000
0x00 8000
Reserved
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x00 9000
0x00 A000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3D 7800
0x3D 7C00
OTP
(1K y 16, Secure Zone)
Reserved
0x3F 0000
FLASH
(32K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
0x3F A000
L1 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-20. F2806 Memory Map
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Block Start
Address
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
0x00 0040
0x00 0400
0x00 0800
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
0x00 6000
Reserved
Peripheral Frame 1
(protected)
Reserved
0x00 7000
0x00 8000
0x00 9000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3D 7800
0x3D 7C00
(A)
OTP (F2802 Only)
(1K y 16, Secure Zone)
Reserved
0x3F 0000
FLASH (F2802) or ROM (C2802)
(32K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802.
B. Memory blocks are not to scale.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. Some locations in ROM are reserved for TI. See Table 9-22 for more information.
Figure 9-21. F2802, C2802 Memory Map
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Block Start
Address
Data Space
Prog Space
0x00 0000
M0 Vector − RAM (32 x 32)
(Enabled if VMAP = 0)
M0 SARAM (1K y 16)
M1 SARAM (1K y 16)
0x00 0040
0x00 0400
0x00 0800
Peripheral Frame 0
0x00 0D00
PIE Vector − RAM
(256 x 16)
(Enabled if ENPIE = 1)
Reserved
0x00 0E00
0x00 6000
Reserved
Peripheral Frame 1
(protected)
Reserved
0x00 7000
0x00 8000
0x00 9000
Peripheral Frame 2
(protected)
L0 SARAM (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
Reserved
0x3D 7800
0x3D 7C00
(A)
OTP (F2801/F2801x Only)
(1K y 16, Secure Zone)
Reserved
0x3F 4000
FLASH (F2801) or ROM (C2801)
(16K y 16, Secure Zone)
0x3F 7FF8
0x3F 8000
128-bit Password
L0 (0-wait)
(4K y 16, Secure Zone, Dual-Mapped)
0x3F 9000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K y 16)
Vectors (32 y 32)
(enabled if VMAP = 1, ENPIE = 0)
A. The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2801.
B. Memory blocks are not to scale.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
F. Some locations in ROM are reserved for TI. See Table 9-22 for more information.
Figure 9-22. F2801, F28015, F28016, C2801 Memory Map
Table 9-18. Addresses of Flash Sectors in F2809
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D 8000 – 0x3D BFFF
Sector H (16K x 16)
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Table 9-18. Addresses of Flash Sectors in F2809 (continued)
ADDRESS RANGE
0x3D C000 – 0x3D FFFF
0x3E 0000 – 0x3E 3FFF
0x3E 4000 – 0x3E 7FFF
0x3E 8000 – 0x3E BFFF
0x3E C000 – 0x3E FFFF
0x3F 0000 – 0x3F 3FFF
0x3F 4000 – 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector G (16K x 16)
Sector F (16K x 16)
Sector E (16K x 16)
Sector D (16K x 16)
Sector C (16K x 16)
Sector B (16K x 16)
Sector A (16K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 – 0x3F 7FF5
0x3F 7FF6 – 0x3F 7FF7
0x3F 7FF8 – 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Table 9-19. Addresses of Flash Sectors in F2808
ADDRESS RANGE
0x3E 8000 – 0x3E BFFF
0x3E C000 – 0x3E FFFF
0x3F 0000 – 0x3F 3FFF
0x3F 4000 – 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (16K x 16)
Sector C (16K x 16)
Sector B (16K x 16)
Sector A (16K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 – 0x3F 7FF5
0x3F 7FF6 – 0x3F 7FF7
0x3F 7FF8 – 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Table 9-20. Addresses of Flash Sectors in F2806, F2802
ADDRESS RANGE
0x3F 0000 – 0x3F 1FFF
0x3F 2000 – 0x3F 3FFF
0x3F 4000 – 0x3F 5FFF
0x3F 6000 – 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (8K x 16)
Sector C (8K x 16)
Sector B (8K x 16)
Sector A (8K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 – 0x3F 7FF5
0x3F 7FF6 – 0x3F 7FF7
0x3F 7FF8 – 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
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Table 9-21. Addresses of Flash Sectors in F2801, F28015, F28016
ADDRESS RANGE
0x3F 4000 – 0x3F 4FFF
0x3F 5000 – 0x3F 5FFF
0x3F 6000 – 0x3F 6FFF
0x3F 7000 – 0x3F 7F7F
PROGRAM AND DATA SPACE
Sector D (4K x 16)
Sector C (4K x 16)
Sector B (4K x 16)
Sector A (4K x 16)
Program to 0x0000 when using the
Code Security Module
0x3F 7F80 – 0x3F 7FF5
0x3F 7FF6 – 0x3F 7FF7
0x3F 7FF8 – 0x3F 7FFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do not program to all zeros)
Note
•
•
•
When the code-security passwords are programmed, all addresses between 0x3F7F80 and
0x3F7FF5 cannot be used as program code or data. These locations must be programmed to
0x0000.
If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be used for
code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and should not contain
program code.
On ROM devices, addresses 0x3F7FF0 – 0x3F7FF5 and 0x3D7BFC – 0x3D7BFF are reserved for
TI, irrespective of whether code security has been used or not. User application should not use
these locations in any way.
Table 9-22 shows how to handle these memory locations.
Table 9-22. Impact of Using the Code Security Module
FLASH
ROM
ADDRESS
Code security enabled Code security disabled Code security enabled Code security disabled
0x3F 7F80 – 0x3F 7FEF
0x3F 7FF0 – 0x3F 7FF5
0x3D 7BFC – 0x3D 7BFF
Application code and data
Reserved for data only
Fill with 0x0000
Application code and data
Fill with 0x0000
Reserved for TI. Do not use.
Application code and data
Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be write/read
peripheral block protected. The protected mode ensures that all accesses to these blocks happen as written.
Because of the C28x pipeline, a write immediately followed by a read, to different memory locations, will appear
in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications
where the user expected the write to occur first (as written). The C28x CPU supports a block protection mode
where a region of memory can be protected so as to make sure that operations occur as written (the penalty is
extra cycles are added to align the operations). This mode is programmable and by default, it will protect the
selected zones.
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The wait-states for the various spaces in the memory map area are listed in Table 9-23.
Table 9-23. Wait-states
AREA
WAIT-STATES
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
0-wait
Fixed
Fixed
0-wait
0-wait (writes) Fixed. The eCAN peripheral can extend a cycle as
2-wait (reads) needed. Back-to-back writes will introduce a 1-cycle delay.
Peripheral Frame 1
0-wait (writes)
Fixed
Peripheral Frame 2
L0 and L1 SARAMs
2-wait (reads)
0-wait
Programmed via the Flash registers. 1-wait-state
Programmable,
OTP
operation is possible at a reduced CPU frequency. See
1-wait minimum
Section 9.1.5 for more information.
Programmed via the Flash registers. 0-wait-state
Programmable, operation is possible at reduced CPU frequency. The CSM
0-wait minimum password locations are hardwired for 16 wait-states. See
Section 9.1.5 for more information.
Flash
H0 SARAM
Boot-ROM
0-wait
1-wait
Fixed
Fixed
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9.4 Register Map
The 280x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral
Frame 0:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 9-24.
Peripheral
Frame 1
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 9-25 .
Peripheral
Frame 2:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 9-26 .
Table 9-24. Peripheral Frame 0 Registers
NAME(1) (2)
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE(3)
Device Emulation Registers
0x0880 – 0x09FF
384
EALLOW protected
EALLOW protected
CSM Protected
FLASH Registers(4)
0x0A80 – 0x0ADF
96
Code Security Module Registers
ADC Result Registers (dual-mapped)
CPU-TIMER0/1/2 Registers
PIE Registers
0x0AE0 – 0x0AEF
0x0B00 – 0x0B0F
0x0C00 – 0x0C3F
0x0CE0 – 0x0CFF
0x0D00 – 0x0DFF
16
16
EALLOW protected
Not EALLOW protected
Not EALLOW protected
Not EALLOW protected
EALLOW protected
64
32
PIE Vector Table
256
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) Missing segments of memory space are reserved and should not be used in applications.
(3) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(4) The Flash Registers are also protected by the Code Security Module (CSM).
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Table 9-25. Peripheral Frame 1 Registers
NAME(1) (2)
ADDRESS RANGE
0x6000 – 0x60FF
0x6100 – 0x61FF
0x6200 – 0x62FF
SIZE (x16)
ACCESS TYPE
Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.
eCANA Registers
eCANA Mailbox RAM
eCANB Registers
256
256
Not EALLOW-protected
Some eCAN control registers (and selected
bits in other eCAN control registers) are
EALLOW-protected.
256
eCANB Mailbox RAM
ePWM1 Registers
0x6300 – 0x63FF
0x6800 – 0x683F
0x6840 – 0x687F
0x6880 – 0x68BF
0x68C0 – 0x68FF
0x6900 – 0x693F
0x6940 – 0x697F
0x6A00 – 0x6A1F
0x6A20 – 0x6A3F
0x6A40 – 0x6A5F
0x6A60 – 0x6A7F
0x6B00 – 0x6B3F
0x6B40 – 0x6B7F
0x6F80 – 0x6FBF
0x6FC0 – 0x6FDF
0x6FE0 – 0x6FFF
256
64
64
64
64
64
64
32
32
32
32
64
64
128
32
32
Not EALLOW-protected
ePWM2 Registers
ePWM3 Registers
Some ePWM registers are EALLOW
protected. See Table 9-3.
ePWM4 Registers
ePWM5 Registers
ePWM6 Registers
eCAP1 Registers
eCAP2 Registers
eCAP3 Registers
Not EALLOW protected
eCAP4 Registers
eQEP1 Registers
eQEP2 Registers
GPIO Control Registers
GPIO Data Registers
GPIO Interrupt and LPM Select Registers
EALLOW protected
Not EALLOW protected
EALLOW protected
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
(2) Missing segments of memory space are reserved and should not be used in applications.
Table 9-26. Peripheral Frame 2 Registers
NAME(1) (2)
System Control Registers
SPI-A Registers
ADDRESS RANGE
0x7010 – 0x702F
0x7040 – 0x704F
0x7050 – 0x705F
0x7070 – 0x707F
0x7100 – 0x711F
0x7740 – 0x774F
0x7750 – 0x775F
0x7760 – 0x776F
0x7780 – 0x778F
0x7900 – 0x792F
SIZE (x16)
ACCESS TYPE
32
16
16
16
32
16
16
16
16
48
EALLOW Protected
SCI-A Registers
External Interrupt Registers
ADC Registers
SPI-B Registers
Not EALLOW Protected
SCI-B Registers
SPI-C Registers
SPI-D Registers
I2C Registers
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
(2) Missing segments of memory space are reserved and should not be used in applications.
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9.4.1 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 9-27.
Table 9-27. Device Emulation Registers
ADDRESS
RANGE
NAME
SIZE (x16)
DESCRIPTION
0x0880
0x0881
DEVICECNF
PARTID
2
1
Device Configuration Register
0x0882
Part ID Register
0x002C(1) - F2801
0x0024 – F2802
0x0034 – F2806
0x003C – F2808
0x00FE – F2809
0x0014 – F28016
0x001C – F28015
0xFF2C – C2801
0xFF24 – C2802
REVID
0x0883
1
Revision ID Register
Revision ID Register
0x0000 – Silicon Rev. 0 – TMX
0x0001 – Silicon Rev. A – TMX
0x0002 – Silicon Rev. B – TMS
0x0003 – Silicon Rev. C – TMS
0x0000 – Silicon rev. 0 – TMS (F2809 only)
0x0001 – Silicon rev. A – TMS (F2809 only)
PROTSTART
PROTRANGE
0x0884
0x0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
(1) The first byte (00) denotes flash devices. FF denotes ROM devices. Other values are reserved for future devices.
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9.5 Interrupts
Figure 9-23 shows how the various interrupt sources are multiplexed within the 280x devices.
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the 280x, 43 of these are used by peripherals as shown in Table
9-28.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector.
The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when
the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from
INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.
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Peripherals
(SPI, SCI, I2C, eCAN, ePWM, eCAP, eQEP, ADC)
WDINT
Watchdog
Low-Power Modes
WAKEINT
LPMINT
XINT1
XINT1
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1
to
INT12
GPIOXINT1SEL(4:0)
XINT2SOC
ADC
XINT2
XINT2
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28x
CPU
GPIOXINT2SEL(4:0)
TINT0
TINT2
TINT1
CPU TIMER 0
INT14
INT13
CPU TIMER 2 (Reserved for SYS/BIOS)
CPU TIMER 1
int13_select
nmi_select
GPIO0.int
XNMI_XINT13
GPIO
MUX
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
Figure 9-23. External and PIE Interrupt Sources
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IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
Figure 9-24. Multiplexing of Interrupts Using the PIE Block
Table 9-28. PIE Peripheral Interrupts
CPU
PIE INTERRUPTS
INTERRUPTS
(1)
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT(2)
(ADC)
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT1
INT2
INT3
INT4
INT5
XINT2
XINT1
Reserved
EPWM6_TZINT EPWM5_TZINT EPWM4_TZINT EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT
(ePWM6)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(ePWM5)
(ePWM4)
(ePWM3)
(ePWM2)
(ePWM1)
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
Reserved
Reserved
Reserved
Reserved
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
Reserved
Reserved
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
SPITXINTC
(SPI-C)
SPIRXINTC
(SPI-C)
SPITXINTB
(SPI-B)
SPIRXINTB
(SPI-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
INT6
INT7
INT8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT9
INT10
INT11
INT12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1) Out of the 96 possible interrupts, 43 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 12).
(2) ADCINT is sourced as a logical "OR" of both the SEQ1INT and SEQ2INT signals. This is to support backward compatibility with the
implementation found on the TMS320F281x series of devices, where SEQ1INT and SEQ2INT did not exist, only ADCINT. For new
implementations, TI recommends using SEQ1INT and SEQ2INT and not enabling ADCINT in the PIEIER register.
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Table 9-29. PIE Configuration and Control Registers
NAME
PIECTRL
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
SIZE (x16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
0x0CFA –
0x0CFF
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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9.5.1 External Interrupts
Table 9-30. External Interrupt Registers
NAME
XINT1CR
XINT2CR
Reserved
XNMICR
ADDRESS
SIZE (x16)
DESCRIPTION
0x7070
1
1
5
1
1
1
5
1
XINT1 control register
0x7071
XINT2 control register
Reserved
0x7072 – 0x7076
0x7077
XNMI control register
XINT1 counter register
XINT2 counter register
Reserved
XINT1CTR
XINT2CTR
Reserved
XNMICTR
0x7078
0x7079
0x707A – 0x707E
0x707F
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x280x, 2801x, 2804x DSP system control and interrupts
reference guide.
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9.6 System Control
This section describes the 280x oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 9-25 shows the various clock and reset domains in the 280x devices that will be discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT(A)
Peripheral Reset
CLKIN(A)
X1
28x
CPU
PLL
OSC
X2
Power
Modes
Control
XCLKIN
Peripheral
Registers
CPU
Timers
System
Control
Registers
Clock Enables
Peripheral
Registers
ePWM 1/2/3/4/5/6
eCAP 1/2/3/4 eQEP 1/2
I/O
I/O
I/O
Peripheral
Registers
eCAN-A/B
I2C-A
GPIO
MUX
GPIOs
Low-Speed Prescaler
LSPCLK
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI-A/B/C/D
High-Speed Prescaler
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT).
Figure 9-25. Clock and Reset Domains
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 9-31.
Table 9-31. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME(1)
XCLK
ADDRESS
SIZE (x16)
DESCRIPTION
XCLKOUT Pin Control, X1 and XCLKIN Status Register
PLL Status Register
0x7010
1
1
8
1
1
1
1
1
1
1
1
1
1
1
3
1
6
PLLSTS
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PLLCR
0x7011
0x7012 – 0x7019
0x701A
Reserved
High-Speed Peripheral Clock Prescaler Register (for HSPCLK)
Low-Speed Peripheral Clock Prescaler Register (for LSPCLK)
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low-Power Mode Control Register 0
Reserved
0x701B
0x701C
0x701D
0x701E
0x701F – 0x7020
0x7021
PLL Control Register
SCSR
0x7022
System Control and Status Register
Watchdog Counter Register
Reserved
WDCNTR
Reserved
WDKEY
Reserved
WDCR
0x7023
0x7024
0x7025
Watchdog Reset Key Register
Reserved
0x7026 – 0x7028
0x7029
Watchdog Control Register
Reserved
0x702A – 0x702F
Reserved
(1) All of the registers in this table are EALLOW protected.
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9.6.1 OSC and PLL Block
Figure 9-26 shows the OSC and PLL block on the 280x.
OSCCLK
OSCCLK
VCOCLK
OSCCLK
or
VCOCLK
XCLKIN
(3.3-V Clock Input)
0
n
XOR
CLKIN
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
PLL
n
0
/2
PLLSTS[CLKINDIV]
X1
On-Chip
Oscillator
4-bit PLL Select
(PLLCR)
X2
Figure 9-26. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 280x devices using the X1 and X2
pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO
2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected
and the XCLKIN pin tied low. The logic-high level in this case should not exceed VDD
The three possible input-clock configurations are shown in Figure 9-27 through Figure 9-29.
.
.
XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0-VDDIO
)
Figure 9-27. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
)
NC
(Toggling 0-VDD
Figure 9-28. Using a 1.8-V External Oscillator
XCLKIN
X1
X2
CL1
CL2
Crystal
Figure 9-29. Using the Internal Oscillator
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9.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below:
•
•
•
•
•
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 30 to 60 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with
the DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor
can also advise the customer regarding the proper tank component values that will produce proper start up and
stability over the entire operating range.
9.6.1.2 PLL-Based Clock Module
The 280x devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking
signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV]
to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR
register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK
cycles.
Table 9-32. PLLCR Register Bit Definitions
SYSCLKOUT
PLLCR[DIV](1)
(CLKIN)(2)
0000 (PLL bypass)
0001
OSCCLK/n
(OSCCLK*1)/n
(OSCCLK*2)/n
(OSCCLK*3)/n
(OSCCLK*4)/n
(OSCCLK*5)/n
(OSCCLK*6)/n
(OSCCLK*7)/n
(OSCCLK*8)/n
(OSCCLK*9)/n
(OSCCLK*10)/n
Reserved
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011–1111
(1) This register is EALLOW protected.
(2) CLKIN is the input clock to the CPU. SYSCLKOUT is the output
clock from the CPU. The frequency of SYSCLKOUT is the same
as CLKIN. If CLKINDIV = 0, n = 2; if CLKINDIV = 1, n = 1.
Note
PLLSTS[CLKINDIV] enables or bypasses the divide-by-two block before the clock is fed to the core.
This bit must be 0 before writing to the PLLCR and must only be set after PLLSTS[PLLLOCKS] = 1.
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The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the
device.
•
External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks
are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 9-33. Possible PLL Configuration Modes
PLLSTS[CLKINDIV
]
SYSCLKOUT
(CLKIN)
PLL MODE
REMARKS
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0
OSCCLK/2
PLL Off
1
OSCCLK
PLL Bypass is the default PLL configuration upon power-up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0
1
OSCCLK/2
OSCCLK
PLL Bypass
PLL Enable
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0
OSCCLK*n/2
9.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a
limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–
5 MHz. Limp mode is not specified to work from power-up, only after input clocks have been present initially. In
PLL bypass mode, the limp mode clock from the PLL is automatically routed to the CPU if the input clock is
removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or
WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (that is,
the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and
the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could be used by the application
firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an
R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged.
An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully
charged. Such a circuit would also help in detecting failure of the flash memory and the VDD3VFL rail.
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9.6.2 Watchdog Block
The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has
reached its maximum value. To prevent this, the user disables the counter or the software must periodically write
a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 9-30
shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
WDCLK
Watchdog
Prescaler
8-Bit
Watchdog
Counter
CLR
/512
Clear Counter
Internal
Pullup
WDKEY[7:0]
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
WDRST(A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
1
0
1
Figure 9-30. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that
it can wake the device from STANDBY (if enabled). See Section 9.7, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE
mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
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9.7 Low-Power Modes Block
The low-power modes on the 280x are similar to the 240x devices. Table 9-34 summarizes the various modes.
Table 9-34. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, Watchdog interrupt, any enabled
interrupt, XNMI
IDLE
00
On
On
On(2)
On
XRS, Watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
STANDBY
HALT
01
1X
Off
Off
Off
Off
(watchdog still running)
Off
XRS, GPIO Port A signal, XNMI,
debugger(3)
(oscillator and PLL turned off,
watchdog not functional)
(1) The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the signals, will
exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise the
IDLE mode will not be exited and the device will go back into the indicated low power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The
LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT Mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The
user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the TMS320x280x,
2801x, 2804x DSP system control and interrupts reference guide for more details.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
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10 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 TI Design or Reference Design
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at TIDesigns.
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TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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11 Device and Documentation Support
11.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail
on each of these steps, see the following:
•
•
C2000 Real-Time Control MCUs – Getting started
C2000 Real-Time Control MCUs – Tools & software
Step 1. Acquire the appropriate development tools
The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial development, which,
in one package, includes:
•
•
•
On-board JTAG emulation via USB or parallel port
Appropriate emulation driver
Code Composer Studio™ IDE for eZdsp
Once you have become familiar with the device and begin developing on your own hardware, purchase Code
Composer Studio™ IDE separately for software development and a JTAG emulation tool to get started on your
project.
Step 2. Download starter software
To simplify programming for C28x devices, it is recommended that users download and use the C/C++ Header
Files and Example(s) to begin developing software for the C28x devices and their various peripherals.
After downloading the appropriate header file package for your device, refer to the following resources for step-
by-step instructions on how to run the peripheral examples and use the header file structure for your own
software
•
•
The Quick Start Readme in the /doc directory to run your first application.
Programming TMS320x28xx and 28xxx peripherals in C/C++ application report
Step 3. Download flash programming software
Many C28x devices include on-chip flash memory and tools that allow you to program the flash with your
software IP.
•
•
•
Flash Tools: C28x Flash Tools
TMS320F281x™ flash programming solutions
Running an application from internal flash memory on the TMS320F28xxx DSP
Step 4. Move on to more advanced topics
For more application software and other advanced topics, visit C2000 real-time control MCUs – Tools &
software.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
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11.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320™ DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS 320F2808). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PZ) and temperature range (for example, S). Figure 11-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the Package Option Addendum of this document,
the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F280x,
TMS320C280x, TMS320F2801x DSPs silicon errata.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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Figure 11-1. Example of TMS320x280x/2801x Device Nomenclature
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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11.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software, visit
the Tools & software page for each device.
Software
C28x IQMath Library - A Virtual Floating Point Engine
Texas Instruments TMS320C28x IQmath Library is collection of highly optimized and high precision
mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed
point code on TMS320C28x devices. These routines are typically used in computationally intensive real-time
applications where optimal execution speed & high accuracy is critical. By using these routines you can achieve
execution speeds considerable faster than equivalent code written in standard ANSI C language. In addition, by
providing ready-to-use high precision functions, TI IQmath library can shorten significantly your DSP application
development time. (Please find the IQ Math User's Guide in the /docs folder once the file is extracted and
installed).
C280x, C2801x C/C++ Header Files and Peripheral Examples
This utility contains Hardware Abstraction Layer (HAL) for TMS320x280x and TMS320x280xx DSP devices. This
HAL facilitates peripheral configuration using "C". It also contains a simple test program for each peripheral to
exemplify the usage of HAL to control & configure the on-chip peripheral.
Development Tools
C2000 Gang Programmer
The C2000 Gang Programmer is a C2000 device programmer that can program up to eight identical C2000
devices at the same time. The C2000 Gang Programmer connects to a host PC using a standard RS-232 or
USB connection and provides flexible programming options that allow the user to fully customize the process.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Uniflash Standalone Flash Tool
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
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TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
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11.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F280x, TMS320C280x, TMS320F2801x DSPs silicon errata describes the advisories and usage notes
for different versions of silicon.
CPU User's Guides
TMS320C28x CPU and instruction set reference guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide describes the various interrupts
and system control features of the 280x digital signal processors (DSPs).
Peripheral Guides
C2000 real-time control peripherals reference guide describes the peripheral reference guides of the 28x digital
signal processors (DSPs).
TMS320x280x, 2801x, 2804x DSP Analog-to-Digital Converter (ADC) reference guide describes how to
configure and use the on-chip ADC module, which is a 12-bit pipelined ADC.
TMS320x280x, 2801x, 2804x Enhanced Pulse Width Modulator (ePWM) module reference guide describes the
main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply
control, UPS (uninterruptible power supplies), and other forms of power conversion.
TMS320x280x, 2801x, 2804x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide describes
the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position,
direction, and speed information from a rotating machine in high performance motion and position control
systems. It includes the module description and registers.
TMS320x280x, 2801x, 2804x Enhanced Capture (eCAP) module reference guide describes the enhanced
capture module. It includes the module description and registers.
TMS320x280x, 2801x, 2804x High Resolution Pulse Width Modulator (HRPWM) reference guide describes the
operation of the high-resolution extension to the pulse width modulator (HRPWM).
TMS320x280x/2801x Enhanced Controller Area Network (eCAN) reference guide describes the enhanced
controller area network (eCAN) on the x280x and x2801x devices.
TMS320x280x, 2801x, 2804x Serial Communications Interface (SCI) reference guide describes the features and
operation of the serial communication interface (SCI) module that is available on the TMS320x280x, 2801x,
2804x devices.
TMS320x280x, 2801x, 2804x Serial Peripheral Interface reference guide describes how the serial peripheral
interface works.
TMS320x280x, 2801x, 2804x Inter-Integrated Circuit (I2C) module reference guide describes the features and
operation of the inter-integrated circuit (I2C) module.
TMS320x280x, 2801x, 2804x Boot ROM reference guide describes the purpose and features of the bootloader
(factory-programmed boot-loading software). It also describes other contents of the device on-chip boot ROM
and identifies where all of the information is located within that memory.
Copyright © 2021 Texas Instruments Incorporated
136 Submit Document Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
Tools Guides
TMS320C28x Assembly language tools v18.12.0.LTS user's guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x optimizing C/C++ compiler v18.12.0.LTS user's guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) reference guide describes development
using DSP/BIOS.
Application Reports
TMS320x281x to TMS320x2833x or 2823x migration overview describes how to migrate from the 281x device
design to 2833x or 2823x designs.
TMS320x280x to TMS320x2833x or 2823x migration overview describes how to migrate from a 280x device
design to 2833x or 2823x designs.
TMS320C28x FPU primer provides an overview of the floating-point unit (FPU) in the C2000™ Delfino
microcontroller devices.
Running an application from internal flash memory on the TMS320F28xxx DSP covers the requirements needed
to properly configure application software for execution from on-chip flash memory. Requirements for both DSP/
BIOS and non-DSP/BIOS projects are presented. Example code projects are included.
Programming TMS320x28xx and 28xxx peripherals in C/C++ explores a hardware abstraction layer
implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define
macros and topics of code efficiency and special case registers are also addressed.
Using PWM output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller presents a
method for using the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of
digital signal controllers as a digital-to-analog converter (DAC).
TMS320F280x digital signal controller USB connectivity using the TUSB3410 USB-to-UART bridge chip
presents hardware connections as well as software preparation and operation of the development system using
a simple communication echo program.
Using the Enhanced Quadrature Encoder Pulse (eQEP) module in TMS320x280x, 28xxx as a dedicated capture
provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the
TMS320x280x, 28xxx family of processors.
Using the ePWM module for 0% - 100% duty cycle control provides a guide for the use of the ePWM module to
provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.
TMS320x280x and TMS320F2801x ADC calibration describes a method for improving the absolute accuracy of
the 12-bit ADC found on the TMS320x280x and TMS320F2801x devices. Inherent gain and offset errors affect
the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of
the ADC to levels better than 0.5%. This application report has an option to download an example program that
executes from RAM on the F2808 EzDSP.
Online stack overflow detection on the TMS320C28x DSP presents the methodology for online stack overflow
detection on the TMS320C28x DSP. C-source code is provided that contains functions for implementing the
overflow detection on both DSP/BIOS and non-DSP/BIOS applications.
TMS320x281x to TMS320x280x migration overview describes differences between the Texas Instruments
TMS320x281x and the TMS320x280x/2801x/2804x DSPs to assist in application migration.
Semiconductor packing methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 137
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
An introduction to IBIS (I/O Buffer Information Specification) modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Calculating useful lifetimes of embedded processors provides a methodology for calculating the useful lifetime of
TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general engineers
who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC package thermal metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
Calculating FIT for a mission profile explains how use TI’s reliability de-rating tools to calculate a component
level FIT under power on conditions for a system mission profile.
Serial flash programming of C2000™ microcontrollers discusses using a flash kernel and ROM loaders for serial
programming a device.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
Code Composer Studio™, MicroStar BGA™, Delfino™, TMS320C2000™, TMS320™, TI E2E™ are trademarks of
Texas Instruments.
eZdsp™ is a trademark of Spectrum Digital.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
138 Submit Document Feedback
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28016, TMS320F28015
SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021
www.ti.com
12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 139
Product Folder Links: TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801
TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320C2801PZA
TMS320C2802PZA
TMS320F28015NMFA
NRND
NRND
LQFP
LQFP
PZ
PZ
100
100
100
TBD
TBD
Call TI
Call TI
SNAGCU
Call TI
Call TI
ACTIVE
NFBGA
NMF
184
90
RoHS & Green
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 125
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 125
-40 to 85
TMS320
F28015NMFA
TMS320F28015PZA
TMS320F28015PZQ
TMS320F28015PZS
TMS320F28015PZSR
TMS320F28016PZA
TMS320F28016PZQ
TMS320F28016PZS
TMS320F2801NMFA
TMS320F2801PZA
TMS320F2801PZA-60
TMS320F2801PZQ
TMS320F2801PZS
TMS320F2801PZS-60
TMS320F2802PZA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
NFBGA
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
PZ
PZ
PZ
PZ
PZ
PZ
PZ
NMF
PZ
PZ
PZ
PZ
PZ
PZ
100
100
100
100
100
100
100
100
100
100
100
100
100
100
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
320F28015PZA
TMS
90
320F28015PZQ
TMS
90
320F28015PZS
TMS
1000 RoHS & Green
320F28015PZS
TMS
90
90
90
184
90
90
90
90
90
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
320F28016PZA
TMS
320F28016PZQ
TMS
320F28016PZS
TMS
TMS320
F2801NMFA
320F2801PZA
TMS
320F2801PZA-60
TMS
320F2801PZQ
TMS
320F2801PZS
TMS
320F2801PZS-60
TMS
320F2802PZA
TMS
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320F2802PZA-60
TMS320F2802PZQ
TMS320F2802PZS
TMS320F2802PZS-60
TMS320F2806NMFA
TMS320F2806NMFAR
TMS320F2806NMFS
TMS320F2806PZA
TMS320F2806PZQ
TMS320F2806PZS
TMS320F2808GBAA
TMS320F2808GBAS
TMS320F2808NMFA
TMS320F2808NMFS
TMS320F2808PZA
TMS320F2808PZAR
TMS320F2808PZQ
TMS320F2808PZS
ACTIVE
LQFP
LQFP
PZ
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 125
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 125
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 125
-40 to 85
-40 to 125
-40 to 85
-40 to 85
-40 to 125
-40 to 125
320F2802PZA-60
TMS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PZ
90
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNPB
320F2802PZQ
TMS
LQFP
PZ
90
320F2802PZS
TMS
LQFP
PZ
90
320F2802PZS-60
TMS
NFBGA
NFBGA
NFBGA
LQFP
NMF
NMF
NMF
PZ
184
TMS320
F2806NMFA
1000 RoHS & Green
TMS320
F2806NMFA
184
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
TMS320
F2806NMFS
320F2806PZA
TMS
LQFP
PZ
90
320F2806PZQ
TMS
LQFP
PZ
90
320F2806PZS
TMS
NFBGA
NFBGA
NFBGA
NFBGA
LQFP
GBA
GBA
NMF
NMF
PZ
184
184
184
184
90
Non-RoHS
& Green
TMS320
F2808GBAA
Non-RoHS
& Green
SNPB
TMS320
F2808GBAS
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TMS320
F2808NMFA
TMS320
F2808NMFS
320F2808PZA
TMS
LQFP
PZ
1000 RoHS & Green
320F2808PZA
TMS
LQFP
PZ
90
90
RoHS & Green
RoHS & Green
320F2808PZQ
TMS
LQFP
PZ
320F2808PZS
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS
TMS320F2809NMFA
TMS320F2809PZA
TMS320F2809PZQ
TMS320F2809PZS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NFBGA
LQFP
LQFP
LQFP
NMF
PZ
100
100
100
100
184
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
NIPDAU
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 125
-40 to 125
TMS320
F2809NMFA
320F2809PZA
TMS
PZ
90
320F2809PZQ
TMS
PZ
90
320F2809PZS
TMS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F2801, TMS320F2801-Q1, TMS320F28015, TMS320F28015-Q1, TMS320F28016, TMS320F28016-Q1, TMS320F2802, TMS320F2802-
Q1, TMS320F2806, TMS320F2806-Q1, TMS320F2808, TMS320F2808-Q1, TMS320F2809, TMS320F2809-Q1 :
Catalog : TMS320F2801, TMS320F28015, TMS320F28016, TMS320F2802, TMS320F2806, TMS320F2808, TMS320F2809
•
Automotive : TMS320F2801-Q1, TMS320F28015-Q1, TMS320F28016-Q1, TMS320F2802-Q1, TMS320F2806-Q1, TMS320F2808-Q1, TMS320F2809-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 4
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
GBA0100A
A
10.1
9.9
B
BALL A1 CORNER
10.1
9.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
BALL TYP
7.2 TYP
(1.4) TYP
K
(1.4) TYP
J
H
G
F
SYMM
7.2
TYP
E
D
C
0.55
100X Ø
0.45
B
A
0.8 TYP
0.15
0.05
C A B
C
1
2
3
4
5
6
7
8
9 10
0.8 TYP
SYMM
4224887/A 05/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
GBA0100A
(0.8) TYP
1
2
3
4
5
6
7
8
9
10
A
B
(0.8) TYP
C
D
E
F
SYMM
G
H
J
100X (Ø0.4)
K
SYMM
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
0.05 MAX
ALL AROUND
ALL AROUND
EXPOSED
METAL
METAL UNDER
SOLDER MASK
(Ø 0.25)
SOLDER MASK
OPENING
(Ø 0.25)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4224887/A 05/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
GBA0100A
(0.8) TYP
1
2
3
4
5
6
7
8
9
10
A
B
(0.8) TYP
C
D
E
F
SYMM
G
H
J
100X (Ø0.4)
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 8X
4224887/A 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
NMF0100A
10.1
9.9
B
A
BALL A1 CORNER
10.1
9.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
(1.4) TYP
(1.4) TYP
7.2 TYP
K
J
H
G
F
SYMM
7.2
TYP
E
D
C
0.55
100X Ø
0.45
B
A
0.15
0.05
C A B
C
0.8 TYP
1
2
3
4
5
6
7
8
9
10
0.8 TYP
SYMM
4225038/A 08/2019
NOTES:
NanoFree is a trademark of Texas Instruments.
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
NMF0100A
SYMM
(0.8) TYP
A
B
(0.8) TYP
C
D
E
F
SYMM
G
H
J
100X (Ø 0.4)
K
1
2
3
4
5
6
7
8
9
10
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
0.05 MAX
ALL AROUND
ALL AROUND
EXPOSED
METAL
METAL UNDER
SOLDER MASK
(Ø 0.40)
SOLDER MASK
OPENING
(Ø 0.40)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225038/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
NMF0100A
SYMM
(0.8) TYP
A
B
(0.8) TYP
C
D
E
F
SYMM
G
H
J
100X (Ø 0.4)
K
1
2
3
4
5
6
7
8
9
10
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 8X
4225038/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MPBG028B FEBRUARY 1997 – REVISED MAY 2002
GGM (S–PBGA–N100)
PLASTIC BALL GRID ARRAY
10,10
9,90
SQ
7,20 TYP
0,80
0,40
K
J
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6
7
8
9
10
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,08
0,45
0,35
4145257–3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA configuration.
1
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