TMS320F2810_V02 [TI]
TMS320F281x Digital Signal Processors;
| 型号： | TMS320F2810_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F281x Digital Signal Processors |
| 文件： | 总175页 (文件大小：4795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
TMS320F281x Digital Signal Processors
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128-bit security key/lock
1 Features
– Protects flash/OTP and L0/L1 SARAM
– Prevents firmware reverse-engineering
Motor control peripherals
– Two Event Managers (EVA, EVB)
– Compatible to 240xA devices
Serial port peripherals
– Serial Peripheral Interface (SPI)
– Two Serial Communications Interfaces (SCIs),
standard UART
– Enhanced Controller Area Network (eCAN)
– Multichannel Buffered Serial Port (McBSP)
12-bit ADC, 16 channels
– 2 × 8 channel input multiplexer
– Two Sample-and-Hold
– Single/simultaneous conversions
– Fast conversion rate: 80 ns/12.5 MSPS
Up to 56 General-Purpose I/O (GPIO) pins
Advanced emulation features
– Analysis and breakpoint functions
– Real-time debug via hardware
Development tools include
– ANSI C/C++ compiler/assembler/linker
– Code Composer Studio™ IDE
– DSP/BIOS™
•
•
•
High-performance static CMOS technology
– 150 MHz (6.67-ns cycle time)
– Low-power (1.8-V core at 135 MHz,
1.9-V core at 150 MHz, 3.3-V I/O) design
JTAG boundary scan support
– IEEE Standard 1149.1-1990 IEEE Standard
Test Access Port and Boundary-Scan
Architecture
High-performance 32-bit CPU (TMS320C28x)
– 16 × 16 and 32 × 32 MAC operations
– 16 × 16 dual MAC
•
– Harvard bus architecture
– Atomic operations
– Fast interrupt response and processing
– Unified memory programming model
– 4M linear program/data address reach
– Code-efficient (in C/C++ and Assembly)
– TMS320F24x/LF240x processor source code
compatible
•
•
•
On-chip memory
•
– Up to 128K × 16 flash
(Four 8K × 16 and six 16K × 16 sectors)
– 1K × 16 OTP ROM
– L0 and L1: 2 blocks of 4K × 16 each Single-
Access RAM (SARAM)
– JTAG scan controllers
•
IEEE Standard 1149.1-1990 IEEE Standard
Test Access Port and Boundary-Scan
Architecture
– H0: 1 block of 8K × 16 SARAM
– M0 and M1: 2 blocks of 1K × 16 each SARAM
Boot ROM (4K × 16)
•
•
•
•
Low-power modes and power savings
– IDLE, STANDBY, HALT modes supported
– Disable individual peripheral clocks
Package options
– With software boot modes
– Standard math tables
External interface (F2812)
– Over 1M × 16 total memory
– Programmable wait states
– Programmable read/write strobe timing
– Three individual chip selects
Endianness: Little endian
Clock and system control
– On-chip oscillator
– Watchdog timer module
Three external interrupts
– 179-ball MicroStar BGA™ with external memory
interface (GHH, ZHH) (F2812)
– 176-pin Low-Profile Quad Flatpack (LQFP) with
external memory interface (PGF) (F2812)
– 128-pin LQFP without external memory
interface (PBK) (F2810, F2811)
•
•
•
Temperature options
– A: –40°C to 85°C (GHH, ZHH, PGF, PBK)
– S: –40°C to 125°C (GHH, ZHH, PGF, PBK)
– Q: –40°C to 125°C (PGF, PBK)
(AEC-Q100 qualification for automotive
applications)
•
•
Peripheral Interrupt Expansion (PIE) block that
supports 45 peripheral interrupts
Three 32-bit CPU timers
•
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
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•
•
•
•
•
•
Grid infrastructure
2 Applications
Industrial transport
Medical, healthcare, and fitness
Motor drives
Power delivery
Telecom infrastructure
Test and measurement
•
•
•
•
Advanced Driver Assistance Systems (ADAS)
Building automation
Electronic point of sale
Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)
powertrain
•
Factory automation
3 Description
The TMS320F2810, TMS320F2811, and TMS320F2812-Q1 devices, members of the TMS320C28x DSP
generation, are highly integrated, high-performance solutions for demanding control applications.
Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812-Q1 are abbreviated as F2810,
F2811, and F2812-Q1, respectively. F281x denotes all three devices.
Device Information
PART NUMBER(1)
TMS320F2812ZHH
PACKAGE
MicroStar BGA (179)
MicroStar BGA (179)
LQFP (176)
BODY SIZE
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
24.0 mm × 24.0 mm
14.0 mm × 14.0 mm
14.0 mm × 14.0 mm
TMS320F2812GHH
TMS320F2812PGF
TMS320F2811PBK
TMS320F2810PBK
LQFP (128)
LQFP (128)
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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4 Functional Block Diagram
Memory Bus
TINT0
CPU-Timer 0
CPU-Timer 1
Real-Time JTAG
CPU-Timer 2
TINT2
Control
INT14
External
Interface
(XINTF)(B)
Address (19)
Data (16)
PIE
(96 Interrupts)(A)
INT[12:1]
TINT1
INT13
NMI
XINT13
XNMI
M0 SARAM
1K x 16
External Interrupt
Control
(XINT1/2/13, XNMI)
M1 SARAM
1K x 16
G
P
I
SCIA/SCIB
SPI
FIFO
FIFO
FIFO
L0 SARAM
4K x 16
O
GPIO Pins
McBSP
L1 SARAM
4K x 16
M
U
X
C28x CPU
eCAN
Flash
EVA/EVB
128K x 16 (F2812)
128K x 16 (F2811)
64K x 16 (F2810)
12-Bit ADC
16 Channels
OTP
1K x 16
XRS
X1/XCLKIN
X2
System Control
RS
CLKIN
(Oscillator and PLL
+
Peripheral Clocking
H0 SARAM
8K x 16
+
Low-Power Modes
+
XF_XPLLDIS
Memory Bus
Boot ROM
4K x 16
Watchdog)
Peripheral Bus
Protected by the code-security module.
A. 45 of the possible 96 interrupts are used on the devices.
B. XINTF is available on the F2812 device only.
Figure 4-1. Functional Block Diagram
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TMS320F2812-Q1
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Revision History.............................................................. 4
6 Device Comparison.........................................................5
6.1 Related Products........................................................ 6
7 Terminal Configuration and Functions..........................7
7.1 Pin Diagrams.............................................................. 7
7.2 Signal Descriptions................................................... 10
8 Specifications................................................................ 19
8.1 Absolute Maximum Ratings...................................... 19
8.2 ESD Ratings – Commercial...................................... 20
8.3 ESD Ratings – Automotive....................................... 20
8.4 Recommended Operating Conditions.......................21
8.5 Power Consumption Summary................................. 22
8.6 Electrical Characteristics...........................................25
8.7 Thermal Resistance Characteristics for 179-Ball
9.1 Brief Descriptions......................................................87
9.2 Peripherals................................................................94
9.3 Memory Maps......................................................... 126
9.4 Register Map...........................................................131
9.5 Device Emulation Registers....................................133
9.6 External Interface, XINTF (F2812 Only)................. 134
9.7 Interrupts.................................................................136
9.8 System Control....................................................... 140
9.9 OSC and PLL Block................................................142
9.10 PLL-Based Clock Module..................................... 144
9.11 External Reference Oscillator Clock Option..........144
9.12 Watchdog Block.................................................... 145
9.13 Low-Power Modes Block...................................... 146
10 Applications, Implementation, and Layout............. 147
10.1 TI Reference Design.............................................147
11 Device and Documentation Support........................148
11.1 Getting Started......................................................148
11.2 Device and Development Support Tool
GHH Package............................................................. 25
8.8 Thermal Resistance Characteristics for 179-Ball
ZHH Package..............................................................25
8.9 Thermal Resistance Characteristics for 176-Pin
PGF Package..............................................................26
8.10 Thermal Resistance Characteristics for 128-Pin
PBK Package.............................................................. 26
8.11 Thermal Design Considerations..............................26
8.12 Timing and Switching Characteristics..................... 27
9 Detailed Description......................................................87
Nomenclature............................................................148
11.3 Tools and Software................................................149
11.4 Documentation Support........................................ 150
11.5 Support Resources............................................... 151
11.6 Trademarks........................................................... 152
11.7 Electrostatic Discharge Caution............................152
11.8 Glossary................................................................152
12 Mechanical, Packaging, and Orderable
Information.................................................................. 153
12.1 Packaging Information.......................................... 153
5 Revision History
Changes from July 12, 2019 to January 14, 2021 (from Revision U (July 2019) to Revision V
(January 2021))
Page
•
•
Global: Updated the numbering format for tables, figures and cross-references throughout the document...... 1
Device Comparison: Updated part numbers.......................................................................................................5
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TMS320F2812-Q1
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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6 Device Comparison
Table 6-1 provides a summary of each device’s features.
Table 6-1. Device Comparison
F2810
F2810-Q1
F2811
F2811-Q1
F2812
F2812-Q1
FEATURE(1)
Instruction Cycle (at 150 MHz)
TYPE(2)
–
–
–
–
–
–
0
–
–
0
0
–
6.67 ns
6.67 ns
6.67 ns
Single-Access RAM (SARAM) (16-bit word)
3.3-V On-Chip Flash (16-bit word)
Code Security for On-Chip Flash/SARAM/OTP
Boot ROM
18K
18K
18K
64K
128K
128K
Yes
Yes
Yes
Yes
Yes
Yes
OTP ROM (1K x 16)
Yes
Yes
Yes
External Memory Interface
Event Managers A and B (EVA and EVB)
● General-Purpose (GP) Timers
● Compare (CMP)/PWM
–
–
Yes
EVA, EVB
EVA, EVB
EVA, EVB
4
4
4
16
16
16
● Capture (CAP)/QEP Channels
Watchdog Timer
6/2
6/2
6/2
Yes
Yes
Yes
12-Bit ADC
Yes
Yes
Yes
0
● Channels
16
16
16
32-Bit CPU Timers
–
0
0
0
0
–
–
–
3
3
3
Serial Peripheral Interface (SPI)
Serial Communications Interfaces A and B (SCIA and SCIB)
Controller Area Network (CAN)
Multichannel Buffered Serial Port (McBSP)
Digital I/O Pins (Shared)
Yes
Yes
Yes
SCIA, SCIB
SCIA, SCIB
SCIA, SCIB
Yes
Yes
56
Yes
Yes
56
Yes
Yes
56
External Interrupts
3
3
3
Supply Voltage
1.8-V Core (135 MHz), 1.9-V Core (150 MHz), 3.3-V I/O
128-pin PBK
Yes
–
Yes
–
–
176-pin PGF
Yes
Yes
Yes
Yes
Yes
Packaging
–
179-ball GHH
–
–
179-ball ZHH
–
–
A: –40°C to 85°C
–
–
Yes
Yes
Yes
Yes
S: –40°C to 125°C
Temperature Options
Q: –40°C to 125°C
(AEC-Q100 Qualification)
–
Yes
Yes
PGF only
(1) The TMS320F281x DSPs Silicon Errata has been posted on the Texas Instruments (TI) website. It will be updated as needed.
(2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
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Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812
TMS320F2812-Q1
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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6.1 Related Products
For information about other devices in this family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000™ MCU that is offered with a floating-point unit
(FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo™
families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The
F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA
package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™
TMS320F2807x series.
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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the ball locations for the 179-ball GHH and ZHH ball grid array (BGA) packages. Figure 7-2
shows the pin assignments for the 176-pin PGF low-profile quad flatpack (LQFP) and Figure 7-3 shows the pin
assignments for the 128-pin PBK LQFP. Table 7-1 describes the function(s) of each pin.
CAP6_
QEPI2
T3CTRIP_ T4CTRIP/
PDPINTB EVBSOC
VSS
VDD
VSS
VDD
VDD
XD[8]
PWM8
PWM10
PWM9
SCITXDB
P
N
M
L
XZCS0AND1
XZCS2
T4PWM_
T4CMP
VDD3VFL
VDDIO
XD[11]
XA[2]
XWE
SPISOMIA PWM7
TEST2
CANTXA CANRXA
XR/W
C4TRIP
CAP4_
QEP3
CAP5_
QEP4
VSS
XA[1]
XD[9]
XA[3]
SPISIMOA
PWM12
TEST1
X2
PWM1 SCIRXDB PWM2
XRD
VDD
VSS
VDDIO
VDDIO
VSS
XD[6]
XD[7]
XD[10]
XD[12]
PWM11
SPISTEA
VDDIO
TDIRB
TCLKINB
PWM3
PWM4
C5TRIP
T3PWM_
T3CMP
X1/
XCLKIN
VSS
VSS
VDD
VSS
XD[4]
XD[3]
XD[1]
XD[0]
VSSA1
SPICLKA
PWM5
PWM6
K
J
C6TRIP
XHOLDA
XD[13]
T1PWM_
T1CMP
T2PWM_
T2CMP
VSS
XD[5]
XD[2]
XA[4]
MCLKXA MFSRA
CAP1_
QEP1
CAP2_
QEP2
CAP3_
QEPI1
T1CTRIP_
PDPINTA
VDD
XA[5]
MCLKRA
MFSXA
H
G
F
T2CTRIP/
EVASOC
VSS
VDDIO
VDD
VSS
XA[0]
XA[6]
MDXA
XMP/MC
MDRA
ADC-
RESEXT
VDDA1
XA[7]
XA[8]
ADCINB7
ADCINA5
XCLKOUT
TCLKINA TDIRA
C3TRIP
XA[13]
VSS
ADC-
REFP
ADC-
REFM
ADC-
BGREFIN
XNMI_
XINT13
VDDIO
VSS
AVDDREFBG
AVSSREFBG
E
D
C
B
A
XHOLD
XA[18]
C2TRIP
EMU0
C1TRIP
XINT2_
ADCSOC
XINT1_
XBIO
XA[9]
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
TDO
TMS
TDI
XRS
VSS1
VSSA2
VDD
VSS
VDD
XA[12]
XD[14]
XA[10]
ADCINB3 ADCINB0 ADCINB1 ADCINA2
SCITXDA
XA[17]
EMU1
XA[15]
XD[15]
VDDAIO
VSS
VDD
VSS
ADCINB2
ADCLO ADCINA3 ADCINA7 XREADY
TRST XZCS6AND7
XF_
XPLLDIS
VSSAIO
VDDA2
VDD1
XA[16]
XA[14]
XA[11]
ADCINA0 ADCINA4
SCIRXDA
TCK
TESTSEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 7-1. TMS320F2812 179-Ball GHH/ZHH MicroStar BGA™ (Bottom View)
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132
89
133
88
XZCS6AND7
TESTSEL
XZCS2
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
87
CANTXA
VSS
XA[3]
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
TRST
TCK
EMU0
XA[12]
XD[14]
XWE
T4CTRIP/EVBSOC
XHOLDA
VDDIO
XA[2]
XF_XPLLDIS
XA[13]
VSS
T3CTRIP_PDPINTB
VSS
VDD
XA[14]
VDDIO
X1/XCLKIN
X2
VDD
XD[11]
XD[10]
EMU1
XD[15]
XA[15]
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
XA[16]
TCLKINB
TDIRB
VSS
VDD3VFL
XD[9]
VSS
VDD
TEST1
TEST2
XD[8]
VDDIO
SCITXDA
XA[17]
SCIRXDA
XA[18]
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
CAP5_QEP4
VSS
XHOLD
XRS
XREADY
VDD1
VSS1
CAP4_QEP3
VDD
ADCBGREFIN
VSSA2
VDDA2
T4PWM_T4CMP
XD[7]
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
T3PWM_T3CMP
VSS
XR/W
PWM12
PWM11
PWM10
PWM9
PWM8
PWM7
ADCLO
VSSAIO
176
45
1
44
Figure 7-2. TMS320F2812 176-Pin PGF LQFP (Top View)
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TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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96
65
97
64
TESTSEL
TRST
TCK
CANTXA
VDD
VSS
98
99
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
EMU0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
T4CTRIP/EVBSOC
T3CTRIP_PDPINTB
VSS
X1/XCLKIN
X2
VDD
TCLKINB
TDIRB
VSS
XF_XPLLDIS
VDD
VSS
VDDIO
EMU1
XINT1_XBIO
XNMI_XINT13
XINT2_ADCSOC
VSS
VDD3VFL
VDD
SCITXDA
SCIRXDA
TEST1
TEST2
VDDIO
XRS
VDD1
VSS1
C6TRIP
C5TRIP
C4TRIP
CAP6_QEPI2
ADCBGREFIN
VSSA2
VDDA2
CAP5_QEP4
CAP4_QEP3
VDD
T4PWM_T4CMP
T3PWM_T3CMP
VSS
PWM12
PWM11
PWM10
PWM9
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCLO
PWM8
VSSAIO
PWM7
128
33
1
32
Figure 7-3. TMS320F2810 and TMS320F2811 128-Pin PBK LQFP (Top View)
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TMS320F2812-Q1
TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
7.2 Signal Descriptions
Table 7-1 specifies the signals on the F281x devices. All digital inputs are TTL-compatible. All outputs are 3.3 V
with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.
Table 7-1. Signal Descriptions
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
XINTF SIGNALS (F2812 ONLY)
XA[18]
XA[17]
XA[16]
XA[15]
XA[14]
XA[13]
XA[12]
XA[11]
XA[10]
XA[9]
D7
B7
158
156
152
148
144
141
138
132
130
125
121
118
111
108
103
85
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
O/Z
O/Z
–
–
A8
O/Z
–
B9
O/Z
–
A10
E10
C11
A14
C12
D14
E12
F12
G14
H13
J12
M11
N10
M2
G5
O/Z
–
O/Z
–
O/Z
–
O/Z
–
O/Z
–
O/Z
–
19-bit XINTF Address Bus
XA[8]
O/Z
–
XA[7]
O/Z
–
XA[6]
O/Z
–
XA[5]
O/Z
–
XA[4]
O/Z
–
XA[3]
O/Z
–
XA[2]
80
O/Z
–
XA[1]
43
O/Z
–
XA[0]
18
O/Z
–
XD[15]
XD[14]
XD[13]
XD[12]
XD[11]
XD[10]
XD[9]
XD[8]
XD[7]
XD[6]
XD[5]
XD[4]
XD[3]
XD[2]
XD[1]
XD[0]
A9
147
139
97
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
B11
J10
L14
N9
96
74
L9
73
M8
P7
68
65
16-bit XINTF Data Bus
L5
54
L3
39
J5
36
K3
33
J3
30
H5
27
H3
24
G3
21
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TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
Microprocessor/Microcomputer Mode Select.
Switches between microprocessor and
microcomputer mode. When high, Zone 7 is
enabled on the external interface. When low,
Zone 7 is disabled from the external interface,
and on-chip boot ROM may be accessed
instead. This signal is latched into the
XMP/ MC
F1
17
–
I
PD
XINTCNF2 register on a reset and the user can
modify this bit in software. The state of the
XMP/ MC pin is ignored after reset.
External Hold Request. XHOLD, when active
(low), requests the XINTF to release the
external bus and place all buses and strobes
into a high-impedance state. The XINTF will
release the bus when any current access is
complete and there are no pending accesses
on the XINTF.
XHOLD
E7
159
–
–
I
PU
External Hold Acknowledge. XHOLDA is driven
active (low) when the XINTF has granted a
XHOLD request. All XINTF buses and strobe
signals will be in a high-impedance state.
XHOLDA is released when the XHOLD signal
is released. External devices should only drive
the external bus when XHOLDA is active (low).
XHOLDA
K10
82
O/Z
–
XINTF Zone 0 and Zone 1 Chip Select.
XZCS0AND1 is active (low) when an access to
the XINTF Zone 0 or Zone 1 is performed.
XZCS0AND1
XZCS2
P1
44
88
–
–
–
O/Z
O/Z
O/Z
–
–
–
XINTF Zone 2 Chip Select. XZCS2 is active
(low) when an access to the XINTF Zone 2 is
performed.
P13
B13
XINTF Zone 6 and Zone 7 Chip Select.
XZCS6AND7 is active (low) when an access to
the XINTF Zone 6 or Zone 7 is performed.
XZCS6AND7
133
Write Enable. Active-low write strobe. The write
strobe waveform is specified, per zone basis,
by the Lead, Active, and Trail periods in the
XTIMINGx registers.
XWE
N11
M3
N4
84
42
–
–
–
–
O/Z
O/Z
O/Z
I
–
–
Read Enable. Active-low read strobe. The read
strobe waveform is specified, per zone basis,
by the Lead, Active, and Trail periods in the
XTIMINGx registers. NOTE: The XRD and
XWE signals are mutually exclusive.
XRD
Read Not Write Strobe. Normally held high.
When low, XR/ W indicates write cycle is active;
when high, XR/ W indicates read cycle is
active.
XR/ W
XREADY
51
–
Ready Signal. Indicates peripheral is ready to
complete the access when asserted to 1.
XREADY can be configured to be a
B6
161
PU
synchronous or an asynchronous input. See
the timing diagrams for more details.
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TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
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Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input – input to the internal oscillator.
This pin is also used to feed an external clock.
The 28x can be operated with an external clock
source, provided that the proper voltage levels
be driven on the X1/XCLKIN pin. It should be
noted that the X1/XCLKIN pin is referenced to
the 1.8-V (or 1.9-V) core digital power supply
(VDD), rather than the 3.3-V I/O supply (VDDIO).
A clamping diode may be used to clamp a
buffered clock signal to ensure that the logic-
high level does not exceed VDD (1.8 V or 1.9 V)
or a 1.8-V oscillator may be used.
X1/XCLKIN
K9
77
58
I
–
X2
M9
76
57
87
O
O
–
–
Oscillator Output
Output clock derived from SYSCLKOUT to be
used for external wait-state generation and as a
general-purpose clock source. XCLKOUT is
either the same frequency, 1/2 the frequency,
or 1/4 the frequency of SYSCLKOUT. At reset,
XCLKOUT = SYSCLKOUT/4. The XCLKOUT
signal can be turned off by setting bit 3
(CLKOFF) of the XINTCNF2 register to 1.
Unlike other GPIO pins, the XCLKOUT pin is
not placed in a high-impedance state during
reset.
XCLKOUT
F11
119
Test Pin. Reserved for TI. Must be connected to
ground.
TESTSEL
A13
134
97
I
PD
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to
terminate execution. The PC will point to the
address contained at the location 0x3FFFC0.
When XRS is brought to a high level, execution
begins at the location pointed to by the PC.
This pin is driven low by the DSP when a
watchdog reset occurs. During watchdog reset,
the XRS pin will be driven low for the watchdog
reset duration of 512 XCLKIN cycles. The
output buffer of this pin is an open-drain with an
internal pullup (100 µA, typical). If this pin is
driven by an external device, it should be done
using an open-drain device.
XRS
D6
160
113
I/O
PU
Test Pin. Reserved for TI. On F281x devices,
TEST1 must be left unconnected.
TEST1
TEST2
M7
N7
67
66
51
50
I/O
I/O
–
–
Test Pin. Reserved for TI. On F281x devices,
TEST2 must be left unconnected.
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TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
JTAG
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system
control of the operations of the device. If this
signal is not connected or driven low, the
device operates in its functional mode, and the
test reset signals are ignored. NOTE: Do not
use pullup resistors on TRST; it has an internal
pulldown device. TRST is an active-high test
pin and must be maintained low at all times
during normal device operation. In a low-noise
environment, TRST may be left floating. In
other instances, an external pulldown resistor is
highly recommended. The value of this resistor
should be based on drive strength of the
debugger pods applicable to the design. A 2.2-
kΩ resistor generally offers adequate
TRST
B12
135
98
I
PD
protection. Since this is application-specific, it is
recommended that each target board be
validated for proper operation of the debugger
and the application.
TCK
TMS
A12
D13
136
126
99
92
I
I
PU
PU
JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal
pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
JTAG test data input (TDI) with internal pullup.
TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDI
C13
D12
131
127
96
93
I
PU
–
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge
of TCK.
TDO
O/Z
Emulator pin 0. When TRST is driven high, this
pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With
the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on
the TRST pin would latch the device into
boundary-scan mode. NOTE: An external
pullup resistor is recommended on this pin. The
value of this resistor should be based on the
drive strength of the debugger pods applicable
to the design. A 2.2-kΩ to 4.7-kΩ resistor is
generally adequate. Since this is application-
specific, it is recommended that each target
board be validated for proper operation of the
debugger and the application.
EMU0
D11
137
100
I/O/Z
PU
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TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
Emulator pin 1. When TRST is driven high, this
pin is used as an interrupt to or from the
emulator system and is defined as input/output
through the JTAG scan. This pin is also used to
put the device into boundary-scan mode. With
the EMU0 pin at a logic-high state and the
EMU1 pin at a logic-low state, a rising edge on
the TRST pin would latch the device into
boundary-scan mode. NOTE: An external
pullup resistor is recommended on this pin. The
value of this resistor should be based on the
drive strength of the debugger pods applicable
to the design. A 2.2-kΩ to 4.7-kΩ resistor is
generally adequate. Since this is application-
specific, it is recommended that each target
board be validated for proper operation of the
debugger and the application.
EMU1
C9
146
105
I/O/Z
PU
ADC ANALOG INPUT SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
B5
D5
E5
A4
B4
C4
D4
A3
F5
D1
D2
D3
C1
B1
C3
C2
167
168
169
170
171
172
173
174
9
119
120
121
122
123
124
125
126
9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
8-channel analog inputs for
Sample-and-Hold A. The ADC pins should not
be driven before the VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
8
8
7
7
8-channel analog inputs for
6
6
Sample-and-Hold B. The ADC pins should not
be driven before the VDDA1, VDDA2, and VDDAIO
pins have been fully powered up.
5
5
4
4
3
3
2
2
ADC Voltage Reference Output (2 V). Requires
a low ESR (under 1.5 Ω) ceramic bypass
capacitor of 10 µF to analog ground.
[Can accept external reference input (2 V) if the
software bit is enabled for this mode. 1–10 µF
low ESR capacitor can be used in the external
reference mode.]
ADCREFP
E2
11
11
I/O
–
NOTE: Use the ADC Clock rate to derive the
ESR specification from the capacitor data sheet
that is used in the system.
ADC Voltage Reference Output (1 V). Requires
a low ESR (under 1.5 Ω) ceramic bypass
capacitor of 10 µF to analog ground.
[Can accept external reference input (1 V) if the
software bit is enabled for this mode. 1–10 µF
low ESR capacitor can be used in the external
reference mode.]
ADCREFM
E4
10
10
I/O
–
NOTE: Use the ADC Clock rate to derive the
ESR specification from the capacitor data sheet
that is used in the system.
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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
ADC External Current Bias Resistor. Use 24.9
kΩ ± 5% for ADC clock range 1–18.75 MHz;
use 20 kΩ ± 5% for ADC clock range
18.75 MHz–25 MHz.
ADCRESEXT
ADCBGREFIN
F2
16
16
O
–
–
–
Test Pin. Reserved for TI. Must be left
unconnected.
E6
164
116
AVSSREFBG
AVDDREFBG
E3
E1
12
13
12
13
–
–
–
–
ADC Analog GND
ADC Analog Power (3.3-V)
Common Low Side Analog Input. Connect to
analog ground.
ADCLO
B3
175
127
–
–
VSSA1
VSSA2
VDDA1
VDDA2
VSS1
F3
C5
F4
A5
C6
A6
B2
A2
15
165
14
15
117
14
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC Analog GND
ADC Analog GND
ADC Analog 3.3-V Supply
ADC Analog 3.3-V Supply
ADC Digital GND
166
163
162
1
118
115
114
1
VDD1
ADC Digital 1.8-V (or 1.9-V) Supply
3.3-V Analog I/O Power Pin
Analog I/O Ground Pin
VDDAIO
VSSAIO
176
128
POWER SIGNALS
20
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H1
L1
23
37
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
29
42
56
63
74
82
94
102
110
17
26
30
39
–
P5
56
P9
75
1.8-V or 1.9-V Core Digital Power Pins. See
Section 8.4, Recommended Operating
Conditions, for voltage requirements.
P12
K12
G12
C14
B10
C8
–
100
112
128
143
154
19
G4
K1
32
L2
38
P4
52
K6
58
P8
70
53
59
62
73
–
M10
L11
K13
J14
G13
E14
B14
D10
C10
B8
78
86
Core and Digital I/O Ground Pins
99
105
113
120
129
142
–
–
88
95
–
103
109
153
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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
SPRS174V – APRIL 2001 – REVISED FEBRUARY 2021
www.ti.com
Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
J4
31
25
49
–
–
–
–
–
–
–
–
–
–
–
–
–
L7
64
L10
81
3 3-V I/O Digital Power Pins
N14
G11
E9
–
–
114
145
83
104
3.3-V Flash Core Power Pin. This pin should be
connected to 3.3 V at all times after power-up
sequence requirements have been met.
VDD3VFL
N8
69
52
–
–
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOA0 - PWM1 (O)
GPIOA1 - PWM2 (O)
GPIOA2 - PWM3 (O)
GPIOA3 - PWM4 (O)
GPIOA4 - PWM5 (O)
GPIOA5 - PWM6 (O)
M12
M14
L12
L13
K11
K14
92
93
68
69
70
71
72
75
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
PU
PU
GPIO or PWM Output Pin #1
GPIO or PWM Output Pin #2
GPIO or PWM Output Pin #3
GPIO or PWM Output Pin #4
GPIO or PWM Output Pin #5
GPIO or PWM Output Pin #6
94
95
98
101
GPIOA6 -
T1PWM_T1CMP (I)
J11
J13
102
104
76
77
I/O
I/O
PU
PU
GPIO or Timer 1 Output
GPIO or Timer 2 Output
GPIOA7 -
T2PWM_T2CMP (I)
GPIOA8 - CAP1_QEP1 (I)
GPIOA9 - CAP2_QEP2 (I)
GPIOA10 - CAP3_QEPI1 (I)
GPIOA11 - TDIRA (I)
H10
H11
H12
F14
F13
E13
E11
F10
106
107
109
116
117
122
123
124
78
79
80
85
86
89
90
91
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
PU
PU
PU
PU
GPIO or Capture Input #1
GPIO or Capture Input #2
GPIO or Capture Input #3
GPIO or Timer Direction
GPIOA12 - TCLKINA (I)
GPIOA13 - C1TRIP (I)
GPIOA14 - C2TRIP (I)
GPIOA15 - C3TRIP (I)
GPIO or Timer Clock Input
GPIO or Compare 1 Output Trip
GPIO or Compare 2 Output Trip
GPIO or Compare 3 Output Trip
GPIOB OR EVB SIGNALS
GPIOB0 - PWM7 (O)
GPIOB1 - PWM8 (O)
GPIOB2 - PWM9 (O)
GPIOB3 - PWM10 (O)
GPIOB4 - PWM11 (O)
GPIOB5 - PWM12 (O)
N2
P2
N3
P3
L4
45
46
47
48
49
50
33
34
35
36
37
38
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
PU
PU
GPIO or PWM Output Pin #7
GPIO or PWM Output Pin #8
GPIO or PWM Output Pin #9
GPIO or PWM Output Pin #10
GPIO or PWM Output Pin #11
GPIO or PWM Output Pin #12
M4
GPIOB6 -
T3PWM_T3CMP (I)
K5
N5
53
55
40
41
I/O
I/O
PU
PU
GPIO or Timer 3 Output
GPIO or Timer 4 Output
GPIOB7 -
T4PWM_T4CMP (I)
GPIOB8 - CAP4_QEP3 (I)
GPIOB9 - CAP5_QEP4 (I)
GPIOB10 - CAP6_QEPI2 (I)
GPIOB11 - TDIRB (I)
M5
M6
P6
L8
57
59
60
71
72
61
43
44
45
54
55
46
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
PU
PU
GPIO or Capture Input #4
GPIO or Capture Input #5
GPIO or Capture Input #6
GPIO or Timer Direction
GPIOB12 - TCLKINB (I)
GPIOB13 - C4TRIP (I)
K8
N6
GPIO or Timer Clock Input
GPIO or Compare 4 Output Trip
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Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
GPIOB14 - C5TRIP (I)
GPIOB15 - C6TRIP (I)
L6
K7
62
47
48
I/O
I/O
PU
PU
GPIO or Compare 5 Output Trip
GPIO or Compare 6 Output Trip
63
GPIOD OR EVA SIGNALS
GPIOD0 -
T1CTRIP_PDPINTA (I)
H14
G10
110
115
81
84
I/O
I/O
PU
PU
GPIO or Timer 1 Compare Output Trip
GPIOD1 - T2CTRIP/
EVASOC (I)
GPIO or Timer 2 Compare Output Trip or
External ADC Start-of-Conversion EV-A
GPIOD OR EVB SIGNALS
GPIOD5 -
T3CTRIP_PDPINTB (I)
P10
P11
79
83
60
61
I/O
I/O
PU
PU
GPIO or Timer 3 Compare Output Trip
GPIOD6 - T4CTRIP/
EVBSOC (I)
GPIO or Timer 4 Compare Output Trip or
External ADC Start-of-Conversion EV-B
GPIOE OR INTERRUPT SIGNALS
GPIOE0 - XINT1_ XBIO (I)
D9
D8
E8
149
151
150
106
108
107
I/O/Z
I/O/Z
I/O
–
–
GPIO or XINT1 or XBIO input
GPIOE1 -
XINT2_ADCSOC (I)
GPIO or XINT2 or ADC start-of-conversion
GPIO or XNMI or XINT13
GPIOE2 - XNMI_XINT13 (I)
PU
GPIOF OR SPI SIGNALS
GPIOF0 - SPISIMOA (O)
GPIOF1 - SPISOMIA (I)
GPIOF2 - SPICLKA (I/O)
GPIOF3 - SPISTEA (I/O)
M1
N1
K2
K4
40
41
34
35
31
32
27
28
I/O/Z
I/O/Z
I/O/Z
I/O/Z
–
–
–
–
GPIO or SPI slave in, master out
GPIO or SPI slave out, master in
GPIO or SPI clock
GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIOF4 - SCITXDA (O)
GPIOF5 - SCIRXDA (I)
C7
A7
155
157
111
112
I/O
I/O
PU
PU
GPIO or SCI asynchronous serial port TX data
GPIO or SCI asynchronous serial port RX data
GPIOF OR CAN SIGNALS
GPIOF6 - CANTXA (O)
GPIOF7 - CANRXA (I)
N12
N13
87
89
64
65
I/O
I/O
PU
PU
GPIO or eCAN transmit data
GPIO or eCAN receive data
GPIOF OR McBSP SIGNALS
GPIOF8 - MCLKXA (I/O)
GPIOF9 - MCLKRA (I/O)
GPIOF10 - MFSXA (I/O)
GPIOF11 - MFSRA (I/O)
GPIOF12 - MDXA (O)
GPIOF13 - MDRA (I)
J1
H2
H4
J2
28
25
26
29
22
20
23
21
22
24
19
18
I/O
I/O
I/O
I/O
I/O
I/O
PU
PU
PU
PU
–
GPIO or McBSP transmit clock
GPIO or McBSP receive clock
GPIO or McBSP transmit frame synch
GPIO or McBSP receive frame synch
GPIO or McBSP transmitted serial data
GPIO or McBSP received serial data
G1
G2
PU
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Table 7-1. Signal Descriptions (continued)
PIN NO. (1)
NAME
I/O/Z(2)
PU/PD(3)
DESCRIPTION
179-BALL 176-PIN
128-PIN
PBK
GHH/ZHH
PGF
GPIOF OR XF CPU OUTPUT SIGNAL
This pin has three functions:
1. XF – General-purpose output pin.
2. XPLLDIS – This pin is sampled during reset
to check whether the PLL must be
GPIOF14 - XF_
XPLLDIS (O)
A11
140
101
I/O
PU
disabled. The PLL will be disabled if this pin
is sensed low. HALT and STANDBY modes
cannot be used when the PLL is disabled.
3. GPIO – GPIO function
GPIOG OR SCI-B SIGNALS
GPIO or SCI asynchronous serial port transmit
data
GPIOG4 - SCITXDB (O)
GPIOG5 - SCIRXDB (I)
P14
M13
90
91
66
67
I/O/Z
I/O/Z
–
–
GPIO or SCI asynchronous serial port receive
data
(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are
8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 8.6, Electrical Characteristics
Over Recommended Operating Conditions. The pullups/pulldowns are enabled in boundary scan mode.
Note
Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached
recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with the
3.3-V supply.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating temperature ranges (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.5
–0.5
–0.3
–0.3
–20
MAX
4.6
4.6
4.6
4.6
4.6
4.6
2.5
2.5
4.6
4.6
20
UNIT
VDDIO
VDD3VFL
VDDA1
Supply voltage
V
VDDA2
VDDAIO
AVDDREFBG
VDD
Supply voltage
VDD1
V
Input voltage
VIN
V
V
Output voltage
VO
(2)
Input clamp current
Output clamp current
IIK (VIN < 0 or VIN > VDDIO
)
mA
mA
IOK (VO < 0 or VO > VDDIO
)
–20
20
A version (GHH, ZHH, PGF, PBK)(3)
S version (GHH, ZHH, PGF, PBK)(3)
Q version (PGF, PBK)(3)
TJ
–40
85
Operating ambient temperature, TA
–40
125
125
150
150
°C
–40
Junction temperature
Storage temperature
–40
°C
°C
(3)
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 8.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect
to VSS
.
(2) Continuous clamp current per pin is ±2 mA
(3) Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall
device life. For additional information, see the Semiconductor and IC Package Thermal Metrics Application Report.
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8.2 ESD Ratings – Commercial
VALUE
UNIT
TMS320F2812 in 179-ball ZHH package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
TMS320F2812 in 179-ball GHH package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge (ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 ESD Ratings – Automotive
VALUE
UNIT
TMS320F2812 in 176-pin PGF package
Human body model (HBM), per
AEC Q100-002(1)
All pins
All pins
±2000
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner pins on 176-pin PGF:
1, 44, 45, 88, 89, 132, 133, 176
TMS320F2810 and TMS320F2811 in 128-pin PBK package
Human body model (HBM), per
All pins
All pins
±2000
AEC Q100-002(1)
V(ESD)
Electrostatic discharge
Charged device model (CDM),
per AEC Q100-011
±500
±750
V
Corner pins on 128-pin PBK:
1, 32, 33, 64, 65, 96, 97, 128
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.4 Recommended Operating Conditions
MIN(1)
3.14
NOM
3.3
1.8
1.9
0
MAX
3.47
1.89
2
UNIT
Device supply voltage, I/O, VDDIO
V
1.8 V (135 MHz)
1.71
Device supply voltage, CPU, VDD, VDD1
V
1.9 V (150 MHz)
1.81
Supply ground, VSS
V
V
ADC supply voltage, VDDA1, VDDA2, AVDDREFBG,
VDDAIO
3.14
3.3
3.47
Flash programming supply voltage, VDD3VFL
3.14
3.3
3.47
150
135
VDDIO
VDD
0.8
V
Device clock frequency (system clock), fSYSCLKOUT
VDD = 1.9 V ± 5%
VDD = 1.8 V ± 5%
All inputs except X1/XCLKIN
X1/XCLKIN (@ 50 µA max)
All inputs except X1/XCLKIN
X1/XCLKIN (@ 50 µA max)
All I/Os except Group 2
Group 2(2)
2
MHz
2
2
High-level input voltage, VIH
V
V
0.7VDD
Low-level input voltage, VIL
0.3VDD
–4
High-level output source current, VOH = 2.4 V, IOH
mA
mA
–8
Low-level output sink current,
VOL = VOL MAX, IOL
All I/Os except Group 2
Group 2(2)
4
8
A version
–40
–40
–40
85
Ambient temperature, TA
S version
125
125
°C
Q version
(1) See Section 8.12.2 for power sequencing of VDDIO, VDDAIO, VDD, VDDA1/VDDA2/AVDDREFBG, and VDD3VFL
.
(2) Group 2 pins are as follows: XINTF pins, T1CTRIP_PDPINTA, TDO, XCLKOUT, XF, EMU0, and EMU1.
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8.5 Power Consumption Summary
8.5.1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating
Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
(1)
(2)
IDD
IDDIO
TYP
IDD3VFL
IDDA
MODE
TEST CONDITIONS
TYP
MAX(3)
MAX(3)
TYP
MAX(3)
TYP
MAX(3)
All peripheral clocks are enabled. All
PWM pins are toggled at 100 kHz.
Data is continuously transmitted out
of the SCIA, SCIB, and CAN ports.
The hardware multiplier is exercised.
Code is running out of flash with
5 wait-states.
Operational
195 mA(4) 230 mA 15 mA
30 mA
40 mA
45 mA
40 mA
50 mA
•
•
•
Flash is powered down
XCLKOUT is turned off
IDLE
125 mA
5 mA
150 mA
10 mA
5 mA
5 µA
10 mA
20 µA
2 µA
2 µA
4 µA
4 µA
1 µA
1 µA
20 µA
20 µA
All peripheral clocks are on,
except ADC
•
•
•
Flash is powered down
Peripheral clocks are turned off
STANDBY
Pins without an internal PU/PD
are tied high/low
•
•
•
Flash is powered down
Peripheral clocks are turned off
Pins without an internal PU/PD
are tied high/low
HALT
70 µA
5 µA
20 µA
2 µA
4 µA
1 µA
20 µA
•
Input clock is disabled
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA includes current into VDDA1, VDDA2, AVDDREFBG, and VDDAIO pins.
(3) MAX numbers are at 125°C, and MAX voltage (VDD = 1.89 V; VDDIO, VDD3VFL, VDDA = 3.47 V).
(4) IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1
.
Note
HALT and STANDBY modes cannot be used when the PLL is disabled.
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8.5.2 Current Consumption Graphs
250
200
150
100
50
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
IDD
IDDIO
IDD3VFL
IDDA
Total 3.3-V current
A. Test conditions are as defined in Section 8.5.1 for operational currents.
B. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1
C. IDDA represents the current drawn by VDDA1 and VDDA2 rails.
.
D. Total 3.3-V current is the sum of IDDIO, IDD3VFL, and IDDA. It includes a small amount of current (<1 mA) drawn by VDDAIO
.
Figure 8-1. Typical Current Consumption Over Frequency
700
600
500
400
300
200
100
0
0
20
40
60
80
100
120
140
160
SYSCLKOUT (MHz)
Total Power
Figure 8-2. Typical Power Consumption Over Frequency
8.5.3 Reducing Current Consumption
28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current
consumption can be achieved by turning off the clock to any peripheral module which is not used in a given
application. Table 8-1 indicates the typical reduction in current consumption achieved by turning off the clocks to
various peripherals.
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Table 8-1. Typical Current Consumption by Various Peripherals (at 150 MHz)
PERIPHERAL MODULE(1) (3)
IDD CURRENT REDUCTION (mA)
eCAN
EVA
12
6
EVB
6
ADC
SCI
8(2)
4
SPI
5
McBSP
13
(1) All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible
only after the peripheral clocks are turned on.
(2) This number represents the current drawn by the digital portion of the ADC module. Turning off the
clock to the ADC module results in the elimination of the current drawn by the analog portion of the
ADC (IDDA) as well.
(3) Power savings can be achieved by powering down the flash. This must be done by code running off
RAM (not flash).
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8.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
VOH
High-level output voltage
IOH = IOH MAX
IOH = 50 µA
V
VDDIO – 0.2
VOL
IIL
Low-level output voltage
IOL = IOL MAX
0.4
V
Input current
(low level)
With pullup
VDDIO = 3.3 V,
VIN = 0 V
All I/Os(1) (including
XRS) except EVB
–80
–13
–140
–25
–190
µA
GPIOB/EVB
–35
±2
With pulldown
With pullup
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDD
VDDIO = 3.3 V, VIN = VDD
IIH
Input current
(high level)
±2
µA
µA
With pulldown(2)
28
50
80
±2
IOZ
Leakage current (for pins without internal PU/ VO = VDDIO or 0 V
PD), high-impedance state (off-state)
Ci
Input capacitance
Output capacitance
2
3
pF
pF
Co
(1) The following pins have no internal PU/PD: GPIOE0, GPIOE1, GPIOF0, GPIOF1, GPIOF2, GPIOF3, GPIOF12, GPIOG4, and
GPIOG5.
(2) The following pins have an internal pulldown: XMP/ MC, TESTSEL, and TRST.
8.7 Thermal Resistance Characteristics for 179-Ball GHH Package
°C/W(1)
RΘJC
RΘJA
PsiJT
Junction-to-case thermal resistance
Junction-to-free air thermal resistance
Junction-to-package top
16.08
42.57
0.658
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
8.8 Thermal Resistance Characteristics for 179-Ball ZHH Package
°C/W(1)
16.08
42.57
0.658
RΘJC
RΘJA
PsiJT
Junction-to-case thermal resistance
Junction-to-free air thermal resistance
Junction-to-package top
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
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8.9 Thermal Resistance Characteristics for 176-Pin PGF Package
°C/W(1)
RΘJC
RΘJA
PsiJT
Junction-to-case thermal resistance
Junction-to-free air thermal resistance
Junction-to-package top
9.73
41.88
0.247
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
8.10 Thermal Resistance Characteristics for 128-Pin PBK Package
°C/W(1)
10.76
41.65
0.271
RΘJC
RΘJA
PsiJT
Junction-to-case thermal resistance
Junction-to-free air thermal resistance
Junction-to-package top
(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
8.11 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC Package Thermal Metrics helps to understand the thermal metrics and
definitions.
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8.12 Timing and Switching Characteristics
8.12.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
8.12.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
8.12.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
W
3.5 nH
Output
Under
Test
42
Transmission Line
(A)
Z0 = 50 W
Device Pin(A)
4.0 pF
1.85 pF
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns)
at the device pin.
Figure 8-3. 3.3-V Test Load Circuit
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8.12.1.3 Signal Transition Levels
Note that some of the signals use different reference voltages, see the recommended operating conditions table.
Output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.4 V.
Figure 8-4 shows output levels.
2.4 V (VOH
)
0.4 V (VOL
)
Figure 8-4. Output Levels
Output transition times are specified as follows:
•
For a high-to-low transition, the level at which the output is said to be no longer high is below VOH(MIN) and
the level at which the output is said to be low is VOL(MAX) and lower.
•
For a low-to-high transition, the level at which the output is said to be no longer low is above VOL(MAX) and the
level at which the output is said to be high is VOH(MIN) and higher.
Figure 8-5 shows the input levels.
2.0 V (VIH)
0.8 V (VIL)
Figure 8-5. Input Levels
Input transition times are specified as follows:
•
For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is below
VIH(MIN) and the level at which the input is said to be low is VIL(MAX) and lower.
•
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is above
VIL(MAX) and the level at which the input is said to be high is VIH(MIN) and higher.
Note
See the individual timing diagrams for levels used for testing timing parameters.
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8.12.2 Power Supply Sequencing
TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU,
Flash, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some
requirements to be met while powering up/powering down the device.
•
Option 1:
In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1
(1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2
/
AVDDREFBG) modules are ramped up. While option 1 is still valid, TI has simplified the requirement.
Option 2 is the recommended approach.
•
Option 2:
Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then ramp
1.8 V (or 1.9 V) (VDD/VDD1) supply pins.
1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset signal
from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the
device. See Figure 8-7 for power-on reset timing.
•
Power-Down Sequencing:
During power-down, the device reset should be asserted low (8 µs, minimum) before the VDD supply reaches
1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies ramping down.
It is recommended that the device reset control from “Low-Dropout (LDO)” regulators or voltage supervisors
be used to meet this constraint. LDO regulators that facilitate power-sequencing (with the aid of additional
external components) may be used to meet the power sequencing requirement. See
www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.
Note
The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.
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2.5 V(C)
(E)
3.3 V
3.3 V
(A)
VDD_3.3V
<10 ms
1.5 V
1.8 V
(or 1.9 V)
1.8 V
(or 1.9 V)
(B)
VDD_1.8V
>1 ms(D)
>8 μs(F)
XRS
XRS
Power-Up Sequence
Power-Down Sequence
A. VDD_3.3V – VDDIO, VDD3VFL, VDDAIO, VDDA1, VDDA2, AVDDREFBG
B. VDD_1.8V – VDD, VDD1
C. 1.8-V (or 1.9-V) supply should ramp after the 3.3-V supply reaches at least 2.5 V.
D. Reset ( XRS) should remain low until supplies and clocks are stable. See Figure 8-7, Power-on Reset in Microcomputer Mode (XMP/ MC
= 0), for minimum requirements.
E. Voltage supervisor or LDO reset control will trip reset ( XRS) first when the 3.3-V supply is off regulation. Typically, this occurs a few
milliseconds before the 1.8-V (or 1.9-V) supply reaches 1.5 V.
F. Keeping reset low ( XRS) at least 8 µs prior to the 1.8-V (or 1.9-V) supply reaching 1.5 V will keep the flash module in complete reset
before the supplies ramp down.
G. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9-V) supply reaches at least 1 V, this supply should be ramped as quickly
as possible (after the 3.3-V supply reaches at least 2.5 V).
H. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.
Figure 8-6. F2812/F2811/F2810 Typical Power-Up and Power-Down Sequence – Option 2
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8.12.3 Reset Timing
8.12.3.1 Reset ( XRS) Timing Requirements
MIN(1)
8tc(CI)
8tc(CI)
NOM
MAX
UNIT
cycles
cycles
tw(RSL1)
tw(RSL2)
Pulse duration, stable XCLKIN to XRS high
Pulse duration, XRS low
Warm reset
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
td(EX)
512tc(CI)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(CI)
10
cycles
ms
(2)
tOSCST
1
16tc(CI)
16tc(CI)
tsu(XPLLDIS)
th(XPLLDIS)
th(XMP/MC)
th(boot-mode)
Setup time for XPLLDIS pin
Hold time for XPLLDIS pin
cycles
cycles
cycles
cycles
Hold time for XMP/ MC pin
16tc(CI)
(3)
Hold time for boot-mode pins
2520tc(CI)
(1) If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
(3) The boot ROM reads the password locations. Therefore, this timing requirement includes the wakeup time for flash. See the
TMS320x281x DSP Boot ROM Reference Guide and the TMS320x281x DSP System Control and Interrupts Reference Guide for
further information.
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VDDIO, VDD3VFL
VDDAn(A), VDDAIO
2.5 V
(3.3 V)
0.3 V
VDD, VDD1
[1.8 V (or 1.9 V)]
XCLKIN
X1
XCLKIN/8(B)
XCLKOUT
User-Code Dependent
tOSCST
tw(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/
Data/
Control
td(EX)
tsu(XPLLDIS)
XPLLDIS Sampling
User-Code Execution Phase
User-Code Dependent
th(XPLLDIS)
XF/XPLLDIS
XMP/MC
(Don’t Care)
GPIOF14
th(XMP/MC)
(Don’t Care)
(C)
th(boot-mode)
User-Code Dependent
Boot-Mode Pins
(D)
GPIO Pins as Input
Peripheral/GPIO Function
Based on Boot Code
Boot-ROM Execution Starts
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. VDDAn – VDDA1/VDDA2 and AVDDREFBG
B. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
XCLKIN/8 during this phase.
C. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples
BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in
ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection
of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based
on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
D. The state of the GPIO pins is undefined (that is, they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V and
3.3-V supply reaches 2.5 V.
Figure 8-7. Power-on Reset in Microcomputer Mode (XMP/ MC = 0) (See Note D)
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VDDIO, VDD3VFL
VDDAn, VDDAIO
(3.3 V)
2.5 V
0.3 V
VDD, VDD1
[1.8 V (or 1.9 V)]
XCLKIN
X1
tOSCST
XCLKIN/8(A)
XCLKOUT
User-Code Dependent
tw(RSL)
XRS
Address/Data/Control Valid Execution
Begins From External Boot Address 0x3FFFC0
td(EX)
Address/
Data/
Control
(Don’t Care)
(Don’t Care)
th(XPLLDIS)
XPLLDIS Sampling
GPIOF14/XF (User-Code Dependent)
XF/XPLLDIS
XMP/MC
tsu(XPLLDIS)
th(XMP/MC)
(Don’t Care)
User-Code Dependent
I/O Pins
(B)
Input Configuration (State Depends on Internal PU/PD)
A. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT =
XCLKIN/8 during this phase.
B. The state of the GPIO pins is undefined (that is, they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least 1 V and
3.3-V supply reaches 2.5 V.
Figure 8-8. Power-on Reset in Microprocessor Mode (XMP/ MC = 1)
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XCLKIN
X1
XCLKOUT
XCLKIN/8
(XCLKIN * 5)
User-Code Dependent
tw(RSL2)
XRS
User-Code Execution Phase
td(EX)
Address/
Data/
Control
(Don’t Care)
tsu(XPLLDIS)
User-Code Execution
GPIOF14/XF
th(XPLLDIS)
(Don’t Care)
GPIOF14
XF/XPLLDIS
XMP/MC
User-Code Dependent
(Don’t Care)
XPLLDIS Sampling
th(XMP/MC)
(Don’t Care)
(A)
th(boot-mode)
Boot-ROM Execution Starts
Boot-Mode Pins
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples
BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in
ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection
of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based
on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.
Figure 8-9. Warm Reset in Microcomputer Mode
X1/XCLKIN
Write to PLLCR
SYSCLKOUT
XCLKIN * 2
XCLKIN/2
XCLKIN * 4
(Current
CPU Frequency)
[CPU Frequency While PLL is Stabilizing
With the Desired Frequency.
(Changed CPU Frequency)
This Period (PLL Lock-up Time, tp)
is 131 072 XCLKIN Cycles Long.]
Figure 8-10. Effect of Writing Into PLLCR Register
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8.12.4 Clock Specifications
8.12.4.1 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on the F281x DSPs. Section 8.12.4.1.1 lists the cycle times of various clocks.
8.12.4.1.1 Clock Table and Nomenclature
MIN
28.6
20
NOM
MAX UNIT
50 ns
35 MHz
tc(OSC), Cycle time
Frequency
On chip oscillator clock
XCLKIN
tc(CI), Cycle time
Frequency
6.67
4
250
ns
150 MHz
tc(SCO), Cycle time
Frequency
6.67
2
500
150 MHz
2000 ns
ns
SYSCLKOUT
XCLKOUT
HSPCLK
tc(XCO), Cycle time
Frequency
6.67
0.5
150 MHz
ns
tc(HCO), Cycle time
Frequency
6.67
13.3(1)
75(1)
150 MHz
ns
tc(LCO), Cycle time
Frequency
13.3
40
26.6(1)
37.5(1)
LSPCLK
75 MHz
ns
tc(ADCCLK), Cycle time(2)
ADC clock
SPI clock
Frequency
25 MHz
ns
tc(SPC), Cycle time
Frequency
50
20 MHz
ns
tc(CKG), Cycle time
Frequency
50
McBSP
20 MHz
ns
tc(XTIM), Cycle time
Frequency
6.67
XTIMCLK
150 MHz
(1) This is the default reset value if SYSCLKOUT = 150 MHz.
(2) The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be
SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
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8.12.4.2 Clock Requirements and Characteristics
8.12.4.2.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
8.12.4.2.1.1 Input Clock Frequency
PARAMETER
Resonator
Crystal
MIN
20
20
4
TYP
MAX UNIT
35
35
MHz
150
fx
Input clock frequency
Without PLL
With PLL
XCLKIN
5
100
fl
Limp mode clock frequency
2
MHz
8.12.4.2.1.2 XCLKIN Timing Requirements – PLL Bypassed or Enabled
NO.
MIN
MAX UNIT
C8
C9
tc(CI)
tf(CI)
Cycle time, XCLKIN
6.67
250
6
ns
ns
ns
%
Fall time, XCLKIN
C10 tr(CI)
Rise time, XCLKIN
6
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
40
40
60
60
%
8.12.4.2.1.3 XCLKIN Timing Requirements – PLL Disabled
NO.
MIN MAX UNIT
C8
tc(CI)
tf(CI)
Cycle time, XCLKIN
Fall time, XCLKIN
6.67
250
6
ns
Up to 30 MHz
C9
ns
30 MHz to 150 MHz
Up to 30 MHz
2
6
C10 tr(CI)
Rise time, XCLKIN
ns
%
%
30 MHz to 150 MHz
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
XCLKIN ≤ 120 MHz
120 < XCLKIN ≤ 150 MHz
2
40
45
40
45
60
55
60
55
C11 tw(CIL)
Pulse duration, X1/XCLKIN low as a percentage of tc(CI)
Pulse duration, X1/XCLKIN high as a percentage of tc(CI)
C12 tw(CIH)
Table 8-2. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
PLL Disabled
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at
the X1/XCLKIN pin.
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
bypassed. However, the /2 module in the PLL block divides the clock input at the
X1/XCLKIN pin by two before feeding it to the CPU.
PLL Bypassed
PLL Enabled
XCLKIN/2
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL block now divides the output of the PLL by two before feeding it to the CPU.
(XCLKIN * n) / 2
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8.12.4.2.2 Output Clock Characteristics
8.12.4.2.2.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
NO.(1) (2)
C1
PARAMETER
Cycle time, XCLKOUT
MIN
TYP
MAX UNIT
tc(XCO)
tf(XCO)
tr(XCO)
tw(XCOL)
tw(XCOH)
tp
6.67(3)
ns
ns
ns
C3
Fall time, XCLKOUT
2
2
C4
Rise time, XCLKOUT
C5
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time(4)
H – 2
H – 2
H + 2
H + 2
ns
ns
ns
C6
C7
131072tc(CI)
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) The PLL must be used for maximum frequency operation.
(4) This parameter has changed from 4096 XCLKIN cycles in the earlier revisions of the silicon.
C10
C8
C9
XCLKIN(A)
C6
C3
C1
C4
C5
XCLKOUT(A)(B)
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 8-11 is
intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 8-11. Clock Timing
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8.12.5 Peripherals
8.12.5.1 General-Purpose Input/Output (GPIO) – Output Timing
8.12.5.1.1 General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
1tc(SCO)
10
UNIT
cycle
ns
td(XCOH-GPO)
tr(GPO)
Delay time, XCLKOUT high to GPIO low/high
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
All GPIOs
All GPIOs
All GPIOs
tf(GPO)
10
ns
fGPO
20
MHz
XCLKOUT(A)
td(XCOH-GPO)
GPIO
tr(GPO)
tf(GPO)
A. XCLKOUT = SYSCLKOUT
Figure 8-12. General-Purpose Output Timing
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8.12.5.2 General-Purpose Input/Output (GPIO) – Input Timing
See Note (A)
GPIO
Signal
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
Sampling period, determined by GPxQUAL
[QUALPRD]
(SYSCLKOUT cycle x 2 x QUALPRD) x 5
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
Output
From Qualifier
A. This glitch is ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF.
Input qualification is not applicable when QUALPRD = 00. For any other value “n”, the qualification sampling period is 2n SYSCLKOUT
cycles (that is, at every 2n SYSCLKOUT cycle, the GPIO pin will be sampled). Six consecutive samples must be of the same value for a
given input to be recognized.
B. For the qualifier to detect the change, the input must be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should
be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would enable five sampling periods for detection to occur. Since external
signals are driven asynchronously, a 13-SYSCLKOUT-wide pulse provides reliable recognition.
Figure 8-13. GPIO Input Qualifier – Example Diagram for QUALPRD = 1
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8.12.5.2.1 General-Purpose Input Timing Requirements
MIN
2tc(SCO)
MAX
UNIT
With no qualifier
With qualifier
Pulse duration GPIO low/
high
tw(GPI)
All GPIOs
cycles
1tc(SCO) + IQT(1)
(1) Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
SYSCLK
GPIOxn
tw(GPI)
Figure 8-14. General-Purpose Input Timing
Note
The pulse width requirement for general-purpose input is applicable for the XBIO and ADCSOC pins
as well.
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8.12.5.3 Event Manager Interface
8.12.5.3.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB.
8.12.5.3.1.1 PWM Switching Characteristics
PARAMETER(1) (2)
TEST CONDITIONS
MIN
MAX
UNIT
(3)
tw(PWM)
Pulse duration, PWMx output high/low
25
ns
Delay time, XCLKOUT high to PWMx
output switching
td(PWM)XCO
XCLKOUT = SYSCLKOUT/4
10
ns
(1) See the GPIO output timing for fall/rise times for PWM pins.
(2) PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz).
(3) PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.
8.12.5.3.1.2 Timer and Capture Unit Timing Requirements
MIN MAX(2) (1)
2tc(SCO)
1tc(SCO) + IQT(3)
2tc(SCO)
UNIT
Without input qualifier
tw(TDIR)
Pulse duration, TDIRx low/high
cycles
With input qualifier
Without input qualifier
With input qualifier
tw(CAP)
Pulse duration, CAPx input low/high
cycles
1tc(SCO) + IQT(3)
tw(TCLKINL)
tw(TCLKINH)
tc(TCLKIN)
Pulse duration, TCLKINx low as a percentage of TCLKINx cycle time
Pulse duration, TCLKINx high as a percentage of TCLKINx cycle time
Cycle time, TCLKINx
40
60
60
%
%
ns
40
4tc(HCO)
(1) The QUALPRD bit field value can range from 0 (no qualification) through 0xFF (510 SYSCLKOUT cycles). The qualification sampling
period is 2n SYSCLKOUT cycles, where “n” is the value stored in the QUALPRD bit field. As an example, when QUALPRD = 1, the
qualification sampling period is 1 × 2 = 2 SYSCLKOUT cycles (that is, the input is sampled every 2 SYSCLKOUT cycles). Six such
samples will be taken over five sampling windows, each window being 2n SYSCLKOUT cycles. For QUALPRD = 1, the minimum width
that is needed is 5 × 2 = 10 SYSCLKOUT cycles. However, since the external signal is driven asynchronously, a 11-SYSCLKOUT-wide
pulse ensures reliable recognition.
(2) Maximum input frequency to the QEP = min[HSPCLK/2, 20 MHz]
(3) Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
XCLKOUT(A)
td(PWM)XCO
tw(PWM)
PWMx
A. XCLKOUT = SYSCLKOUT
Figure 8-15. PWM Output Timing
XCLKOUT(A)
tw(TDIR)
TDIRx
A. XCLKOUT = SYSCLKOUT
Figure 8-16. TDIRx Timing
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8.12.5.3.1.3 External ADC Start-of-Conversion – EVA – Switching Characteristics
PARAMETER(1)
MIN
MAX
UNIT
cycle
ns
td(XCOH-EVASOCL)
tw(EVASOCL)
Delay time, XCLKOUT high to EVASOC low
Pulse duration, EVASOC low
1tc(SCO)
32tc(HCO)
(1) XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVASOCL)
tw(EVASOCL)
EVASOC
Figure 8-17. EVASOC Timing
8.12.5.3.1.4 External ADC Start-of-Conversion – EVB – Switching Characteristics
PARAMETER(1)
MIN
MAX
UNIT
cycle
ns
td(XCOH-EVBSOCL)
tw(EVBSOCL)
Delay time, XCLKOUT high to EVBSOC low
Pulse duration, EVBSOC low
1tc(SCO)
32tc(HCO)
(1) XCLKOUT = SYSCLKOUT
XCLKOUT
td(XCOH-EVBSOCL)
tw(EVBSOCL)
EVBSOC
Figure 8-18. EVBSOC Timing
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8.12.5.4 Low-Power Mode Wakeup Timing
8.12.5.4.1 IDLE Mode Timing Requirements
MIN
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
1tc(SCO) + IQT(1)
(1) Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
8.12.5.4.2 IDLE Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to program execution resume(1)
•
•
Wake-up from Flash
Flash module in active state
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
8tc(SCO)
cycles
cycles
cycles
–
8tc(SCO) + IQT(2)
1050tc(SCO)
td(WAKE-IDLE)
Wake-up from Flash
Flash module in sleep state
–
1050tc(SCO) + IQT(2)
8tc(SCO)
•
Wake-up from SARAM
8tc(SCO) + IQT(2)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
(2) Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
td(WAKE-IDLE)
A0-A15
XCLKOUT(A)
tw(WAKE-INT)
WAKE INT(B)
A. XCLKOUT = SYSCLKOUT
B. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 8-19. IDLE Entry and Exit Timing
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8.12.5.4.3 STANDBY Mode Timing Requirements
MIN
MAX
UNIT
Without input qualifier
With input qualifier
12tc(CI)
Pulse duration, external wake-up
signal
tw(WAKE-INT)
cycles
(1)
(2 + QUALSTDBY) * tc(CI)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
8.12.5.4.4 STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
32tc(SCO)
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT high
td(IDLE-XCOH)
45tc(SCO)
cycles
Delay time, external wake signal to program execution
resume(1)
•
•
Wake-up from Flash
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
12tc(CI)
–
Flash module in active
state
cycles
12tc(CI) + tw(WAKE-INT)
1125tc(SCO)
td(WAKE-STBY)
Wake-up from Flash
–
Flash module in sleep
state
cycles
cycles
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
With input qualifier
12tc(CI)
•
Wake-up from SARAM
12tc(CI) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up) signal involves additional latency.
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A
C
E
B
D
F
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
tw(WAKE-INT)
td(WAKE-STBY)
X1/XCLKIN
XCLKOUT
td(IDLE-XCOH)
32 SYSCLKOUT Cycles
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its
access time is longer than this number, then it will fail. It is recommended that STANDBY mode be entered from SARAM without an
XINTF access in progress.
C. Clocks to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 8-20. STANDBY Entry and Exit Timing
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8.12.5.4.5 HALT Mode Timing Requirements
MIN
2tc(CI)
8tc(CI)
MAX
UNIT
cycles
cycles
tw(WAKE-XNMI)
tw(WAKE-XRS)
Pulse duration, XNMI wakeup signal
Pulse duration, XRS wakeup signal
8.12.5.4.6 HALT Mode Switching Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
cycles
cycles
td(IDLE-XCOH)
tp
Delay time, IDLE instruction executed to XCLKOUT high
32tc(SCO)
45tc(SCO)
PLL lock-up time
131072tc(CI)
Delay time, PLL lock to program execution resume
•
•
Wake up from flash
Flash module in sleep state
1125tc(SCO)
35tc(SCO)
cycles
cycles
td(WAKE)
–
Wake up from SARAM
A
C
E
G
B
D
F
Device
Status
HALT
HALT
PLL Lock-up Time
Flushing Pipeline
Normal
Execution
Wake-up Latency
XNMI
tw(WAKE-XNMI)
td(wake)
tp
X1/XCLKIN
td(IDLE-XCOH)
Oscillator Start-up Time
XCLKOUT(H)
32 SYSCLKOUT Cycles
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN
to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly.
C. Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and
consumes absolute minimum power.
D. When XNMI is driven active, the oscillator is turned on; but the PLL is not activated. The pulse duration of 2tc(CI) is applicable when an
external oscillator is used. If the internal oscillator is used, the oscillator wake-up time should be added to this parameter.
E. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles.
F. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited.
G. Normal operation resumes.
H. XCLKOUT = SYSCLKOUT
Figure 8-21. HALT Wakeup Using XNMI
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8.12.5.5 Serial Peripheral Interface (SPI) Master Mode Timing
Section 8.12.5.5.1 lists the master mode timing (clock phase = 0) and Section 8.12.5.5.2 lists the master mode
timing (clock phase = 1). Figure 8-22 and Figure 8-23 show the timing waveforms.
8.12.5.5.1 SPI Master Mode External Timing (Clock Phase = 0)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
+
2
3
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
–
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
4
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
5
0.5tc(SPC)M – 10
Setup time, SPISOMI before
SPICLK
8
35
0
35
0
Hold time, SPISOMI valid after
SPICLK
9
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M –
3tc(SYSCLK) – 10
23
24
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 8-22. SPI Master Mode External Timing (Clock Phase = 0)
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8.12.5.5.2 SPI Master Mode External Timing (Clock Phase = 1)
NO.(1)
BRR EVEN
MIN
BRR ODD
MIN
(2) (3) (4)
PARAMETER
UNIT
(5)
MAX
MAX
1
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
0.5tc(SPC)M
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
–
0.5tc(SPC)M
–
2
3
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
+
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
6
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(SPC)M – 10
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
35
0
35
Hold time, SPISOMI valid after
SPICLK
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
0.5tc(SPC) – 10
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 8-23. SPI Master Mode External Timing (Clock Phase = 1)
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8.12.5.6 Serial Peripheral Interface (SPI) Slave Mode Timing
Section 8.12.5.6.1 lists the slave mode timing (clock phase = 0) and Section 8.12.5.6.2 lists the slave mode
timing (clock phase = 1). Figure 8-24 and Figure 8-25 show the timing waveforms.
8.12.5.6.1 SPI Slave Mode External Timing (Clock Phase = 0)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(4) (3)
(5)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 8-24. SPI Slave Mode External Timing (Clock Phase = 0)
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8.12.5.6.2 SPI Slave Mode External Timing (Clock Phase = 1)
NO.
(1) (2)
PARAMETER
MIN
MAX UNIT
(3) (4)
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
Cycle time, SPICLK
4tc(SYSCLK)
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
ns
ns
ns
Pulse duration, SPICLK first pulse
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 8-25. SPI Slave Mode External Timing (Clock Phase = 1)
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8.12.5.7 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 8-3 shows the
relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of
XTIMCLK cycles.
Table 8-3. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)
DESCRIPTION(1) (2)
X2TIMING = 0
XRDLEAD × tc(XTIM)
X2TIMING = 1
LR
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
(XRDLEAD × 2) × tc(XTIM)
AR
TR
LW
AW
TW
(XRDACTIVE + WS + 1) × tc(XTIM)
XRDTRAIL × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
(XWRACTIVE + WS + 1) × tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1) tc(XTIM) – Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
8.12.5.7.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
1.
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions (no hardware to detect
illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 0
≥ 0
≥ 1
≥ 0
≥ 0
0, 1
Examples of valid and invalid timing when not sampling XREADY (no hardware to detect illegal XTIMING
configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Valid
0
1
0
0
0
0
0
1
0
0
0
0
0, 1
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8.12.5.7.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1.
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2.
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (no hardware to detect
illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
≥ 0
≥ 1
≥ 2
≥ 0
0, 1
Examples of valid and invalid timing when using synchronous XREADY (no hardware to detect illegal XTIMING
configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid
Invalid
Valid
0
1
1
0
0
2
0
0
0
0
1
1
0
0
2
0
0
0
0, 1
0, 1
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8.12.5.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1.
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2.
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states
3.
Lead + Active:
LR + AR ≥ 4 × tc(XTIM)
LW + AW ≥ 4 × tc(XTIM)
NOTE: Restriction does not include external hardware wait states
These requirements result in the following XTIMING register configuration restrictions (no hardware to detect
illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
or (no hardware to detect illegal XTIMING configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 2
0
≥ 2
≥ 2
0
0, 1
Examples of valid and invalid timing when using asynchronous XREADY (no hardware to detect illegal XTIMING
configurations):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid
Invalid
Invalid
Valid
0
1
1
1
1
2
0
0
1
2
2
2
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
2
2
2
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
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Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 8-4.
Table 8-4. XINTF Clock Configurations
MODE
SYSCLKOUT
XTIMCLK
XCLKOUT
1
SYSCLKOUT
150 MHz
SYSCLKOUT
150 MHz
Example:
150 MHz
2
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
Example:
150 MHz
3
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
Example:
150 MHz
4
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
Example:
150 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 8-26.
XTIMING0
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XBANK
LEAD/ACTIVE/TRAIL
SYSCLKOUT
C28x
CPU
1(A)
0
XCLKOUT
1
0
XTIMCLK
0
/2
1(A)
0
/2
XINTCNF2
(CLKOFF)
XINTCNF2
(XTIMCLK)
XINTCNF2
(CLKMODE)
(A)
Default value after reset
Figure 8-26. Relationship Between XTIMCLK and SYSCLKOUT
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8.12.5.8 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE, and zone chip-select ( XZCS) change state in relationship to the rising edge of
XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the frequency of
XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either
on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation
XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or
XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the notation
XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active-low
XRNWL
XR/ W active-low
•
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the total
number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd, then
the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XRD active-low
XWEL
XWE active-low
•
•
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be
with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XRD inactive-high
XWEH
XWE inactive-high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number of
lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead + active +
trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the
falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive-high
XRNWH
XR/ W inactive-high
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8.12.5.9 External Interface Read Timing
8.12.5.9.1 External Memory Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high/low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
1
3
2
1
1
–2
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active-low
Delay time, XCLKOUT high/low to XRD inactive-high
Hold time, address valid after zone chip-select inactive-high
Hold time, address valid after XRD inactive-high
ns
–2
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
8.12.5.9.2 External Memory Interface Read Timing Requirements
MIN
MAX
(LR + AR) – 14(1)
AR – 12(1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active-low
Setup time, read data valid before XRD strobe inactive-high
Hold time, read data valid after XRD inactive-high
ns
tsu(XD)XRD
th(XD)XRD
12
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 8-3.
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Trail
Active
Lead
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
td(XCOHL-XRDH)
tsu(XD)XRD
td(XCOHL-XRDL)
XRD
XWE
XR/W
ta(A)
th(XD)XRD
ta(XRD)
DIN
XD[0:15]
XREADY
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 8-27. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE XRDTRAIL
≥ 0 ≥ 0
USEREADY
X2TIMING
XWRLEAD XWRACTIVE XWRTRAIL READYMODE
N/A(1) N/A(1) N/A(1) N/A(1)
≥ 1
0
0
(1) N/A = “Don’t care” for this example
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8.12.5.10 External Interface Write Timing
8.12.5.10.1 External Memory Interface Write Switching Characteristics
PARAMETER
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high or low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
1
3
2
2
2
1
1
–2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/ W low
Delay time, XCLKOUT high/low to XR/ W high
–2
0
Enable time, data bus driven from XWE low
td(XWEL-XD)
Delay time, data valid after XWE active-low
4
(1)
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
Hold time, write data valid after XWE inactive-high
Maximum time for DSP to release the data bus after XR/ W inactive-high
th(XD)XWE
TW – 2(2)
tdis(XD)XRNW
4
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
(2) TW = Trail period, write access. See Table 8-3.
Active
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XRNWH)
td(XCOHL-XWEL)
XWE
XR/W
td(XCOH-XRNWL)
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
XD[0:15]
XREADY
DOUT
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
Figure 8-28. Example Write Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE XRDTRAIL
N/A(1) N/A(1)
USEREADY
X2TIMING
XWRLEAD XWRACTIVE XWRTRAIL READYMODE
≥ 1 ≥ 0 ≥ 0
N/A(1)
N/A(1)
0
0
(1) N/A = “Don’t care” for this example
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8.12.5.11 External Interface Ready-on-Read Timing With One External Wait State
8.12.5.11.1 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high/low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
1
3
2
1
1
–2
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active-low
Delay time, XCLKOUT high/low to XRD inactive-high
Hold time, address valid after zone chip-select inactive-high
Hold time, address valid after XRD inactive-high
ns
–2
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
8.12.5.11.2 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
MIN
MAX
(LR + AR) – 14(1)
AR – 12(1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active-low
Setup time, read data valid before XRD strobe inactive-high
Hold time, read data valid after XRD inactive-high
ns
tsu(XD)XRD
th(XD)XRD
12
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 8-3.
8.12.5.11.3 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN(1)
15
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
12
ns
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
te(XRDYsynchH)
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip-select high
15
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 8-29:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample (n), the setup time (D) with respect to the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
8.12.5.11.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
MIN(1)
11
MAX
UNIT
ns
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
8
ns
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
te(XRDYAsynchH)
3
ns
tsu(XRDYAsynchH)XCOHL
th(XRDYAsynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip-select high
11
0
ns
ns
(1) The first XREADY (asynchronous) sample occurs with respect to E in Figure 8-30:
E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYAsynchL)XCOHL
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where n is the sample number (n = 1, 2, 3, and so forth).
WS (Synch)
Active
See Notes (A) and (B)
See Note (C)
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
td(XCOH-XA)
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
td(XCOHL-XRDH)
td(XCOHL-XRDL)
tsu(XD)XRD
ta(XRD)
XWE
XR/W
ta(A)
th(XD)XRD
XD[0:15]
DIN
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
th(XRDYsynchL)
th(XRDYsynchH)XZCSH
tsu(XRDHsynchH)XCOHL
XREADY(Synch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as: D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM)
tsu(XRDYsynchL)XCOHL
–
E. Reference for the first sample is with respect to this point E = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number (n = 1,
2, 3, and so forth).
Figure 8-29. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE XRDTRAIL
≥ 1
USEREADY
X2TIMING
XWRLEAD XWRACTIVE XWRTRAIL READYMODE
0 = XREADY
≥ 1
3
1
0
N/A(1)
N/A(1)
N/A(1)
(Synch)
(1) N/A = “Don’t care” for this example
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See
Notes (A)
and (B)
WS (Async)
Active
See Note (C)
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOHL-XZCSH)
td(XCOH-XZCSL)
td(XCOH-XA)
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
td(XCOHL-XRDH)
td(XCOHL-XRDL)
XRD
XWE
XR/W
tsu(XD)XRD
ta(XRD)
ta(A)
th(XD)XRD
XD[0:15]
DIN
tsu(XRDYasynchL)XCOHL
te(XRDYasynchH)
th(XRDYasynchH)XZCSH
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as: D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM)
tsu(XRDYAsynchL)XCOHL where n is the sample number (n = 1, 2, 3, and so forth).
–
E. Reference for the first sample is with respect to this point: E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)
Figure 8-30. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE XRDTRAIL
≥ 1
USEREADY
X2TIMING
XWRLEAD XWRACTIVE XWRTRAIL READYMODE
1 = XREADY
(Async)
≥ 1
3
1
0
N/A(1)
N/A(1)
N/A(1)
(1) N/A = “Don’t care” for this example
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8.12.5.12 External Interface Ready-on-Write Timing With One External Wait State
8.12.5.12.1 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
PARAMETER
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active-low
Delay time, XCLKOUT high or low to zone chip-select inactive-high
Delay time, XCLKOUT high to address valid
1
3
2
2
2
1
1
–2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE low
Delay time, XCLKOUT high/low to XWE high
Delay time, XCLKOUT high to XR/ W low
Delay time, XCLKOUT high/low to XR/ W high
Enable time, data bus driven from XWE low
–2
0
td(XWEL-XD)
Delay time, data valid after XWE active-low
4
(1)
th(XA)XZCSH
Hold time, address valid after zone chip-select inactive-high
Hold time, write data valid after XWE inactive-high
Maximum time for DSP to release the data bus after XR/ W inactive-high
th(XD)XWE
TW – 2(2)
tdis(XD)XRNW
4
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
(2) TW = trail period, write access. See Table 8-3.
8.12.5.12.2 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN(1)
15
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
12
ns
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
te(XRDYsynchH)
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip-select high
15
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 8-31:
E = (XWRLEAD + XWRACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will complete. If XREADY (synchronous) is found to
be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
8.12.5.12.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
MIN(1)
11
MAX
UNIT
ns
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
8
ns
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
te(XRDYasynchH)
3
ns
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip-select high
11
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 8-32:
E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
When first sampled, if XREADY (asynchronous) is found to be high, then the access will complete. If XREADY (asynchronous) is found
to be low, it will be sampled again each tc(XTIM) until it is found to be high.
For each sample, setup time from the beginning of the access can be calculated as:
D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number (n = 1, 2, 3, and so forth).
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See
Notes (A)
and (B)
WS (Synch)
See Note (C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
td(XCOH-XA)
td(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYsynchH)XZCSH
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XWEL)
XWE
td(XCOHL-XRNWH)
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYsynchL)XCOHL
te(XRDYsynchH)
tsu(XRDHsynchH)XCOHL
th(XRDYsynchL)
XREADY(Synch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as: D = (XWRLEAD + XWRACTIVE + n – 1) tc(XTIM)
tsu(XRDYsynchL)XCOHL where n is the sample number (n = 1, 2, 3 and so forth).
–
E. Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 8-31. Write With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE XRDTRAIL
N/A(1) N/A(1)
USEREADY
X2TIMING
XWRLEAD XWRACTIVE XWRTRAIL READYMODE
0 = XREADY
(Synch)
N/A(1)
1
0
≥ 1
3
≥ 1
(1) N/A = “Don’t care” for this example
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See
Notes (A)
and (B)
WS (Async)
See Note (C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
XZCS0AND1, XZCS2,
XZCS6AND7
th(XRDYasynchH)XZCSH
td(XCOH-XA)
XA[0:18]
XRD
td(XCOHL-XWEH)
td(XCOHL-XRNWH)
td(XCOHL-XWEL)
XWE
td(XCOH-XRNWL)
XR/W
tdis(XD)XRNW
th(XD)XWEH
td(XWEL-XD)
ten(XD)XWEL
XD[0:15]
DOUT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
te(XRDYasynchH)
tsu(XRDYasynchH)XCOHL
XREADY(Asynch)
See Note (D)
See Note (E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
D. For each sample, setup time from the beginning of the access can be calculated as: D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM)
tsu(XRDYasynchL)XCOHL where n is the sample number (n = 1, 2, 3 and so forth).
–
E. Reference for the first sample is with respect to this point E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 8-32. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE XRDTRAIL
N/A(1) N/A(1)
USEREADY
X2TIMING
XWRLEAD XWRACTIVE XWRTRAIL READYMODE
1 = XREADY
(Async)
N/A(1)
1
0
≥ 1
3
≥ 1
(1) N/A = “Don’t care” for this example
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8.12.5.13 XHOLD and XHOLDA
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-
impedance mode.
On a reset ( XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active-low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[18:0]
XD[15:0]
XWE, XRD
XR/ W
XZCS0AND1
XZCS2
XZCS6AND7
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
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8.12.5.14 XHOLD/ XHOLDA Timing
8.12.5.14.1 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
MIN(1) (2)
MAX
4tc(XTIM)
5tc(XTIM)
3tc(XTIM)
4tc(XTIM)
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
ns
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
td(HL-Hiz)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HAL)
td(HH-BV)
XR/W,
XZCS0AND1,
High-Impedance
XZCS2,
XZCS6AND7
XA[18:0]
XD[15:0]
High-Impedance
Valid
Valid
Valid
See Note (A)
See Note (B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 8-33. External Interface Hold Waveform
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8.12.5.14.2 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
MIN(1) (2)
MAX
UNIT
(3)
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to Hi-Z on all Address, Data, and Control
Delay time, XHOLD low to XHOLDA low
4tc(XTIM) + tc(XCO)
4tc(XTIM) + 2tc(XCO)
4tc(XTIM)
ns
ns
ns
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to Bus valid
6tc(XTIM)
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions will occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
td(HL-HAL)
XHOLD
td(HH-HAH)
XHOLDA
td(HL-HiZ)
td(HH-BV)
XR/W,
XZCS0AND1,
XZCS2,
XZCS6AND7
High-Impedance
XA[18:0]
XD[15:0]
High-Impedance
High-Impedance
Valid
Valid
Valid
See Note (B)
See Note (A)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 8-34. XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
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8.12.5.15 On-Chip Analog-to-Digital Converter
8.12.5.15.1 ADC Absolute Maximum Ratings Over Recommended Operating Conditions
(Unless Otherwise Noted)
MIN(1)
–0.3
MAX
4.6
UNIT
V
Supply voltage range
Supply voltage range
VSSA1/VSSA2 to VDDA1/VDDA2/AVDDREFBG
VSS1 to VDD1
–0.3
2.5
V
Analog Input (ADCIN) Clamp
Current, total (max)
–20(2)
20(2)
mA
(1) Unless otherwise noted, the list of absolute maximum ratings are specified over recommended operating conditions. Stresses beyond
those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS. The continuous
clamp current per pin is ±2 mA.
8.12.5.15.2 ADC Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)—AC Specifications
PARAMETER
Signal-to-noise ratio + distortion
Signal-to-noise ratio
MIN
TYP
62
MAX UNIT
SINAD
dB
dB
SNR
62
THD (100 kHz)
ENOB (SNR)
SFDR
Total harmonic distortion
–68
10.1
69
dB
Effective number of bits
Bits
dB
Spurious free dynamic range
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8.12.5.15.3 ADC Electrical Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted)—DC Specifications
PARAMETER(1)
MIN
12
1
TYP
MAX
UNIT
Bits
Resolution
kHz
ADC clock(2)
25
MHz
ACCURACY
INL (Integral nonlinearity)(3)
1–18.75 MHz ADC clock
1–18.75 MHz ADC clock
±1.5
±1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
DNL (Differential nonlinearity)(3)
Offset error(4)
–80
–200
–50
80
Overall gain error with internal reference(5)
Overall gain error with external reference(6)
Channel-to-channel offset variation
Channel-to-channel Gain variation
200
50
If ADCREFP – ADCREFM = 1 V ± 0.1%
±8
±8
ANALOG INPUT
Analog input voltage (ADCINx to ADCLO)(7)
ADCLO
0
3
5
V
–5
0
10
3
mV
pF
µA
Input capacitance
Input leakage current
±5
INTERNAL VOLTAGE REFERENCE (5)
Accuracy, ADCVREFP
1.9
2
1
2.1
V
Accuracy, ADCVREFM
0.95
1.05
V
V
Voltage difference, ADCREFP – ADCREFM
Temperature coefficient
Reference noise
1
50
100
PPM/°C
µV
EXTERNAL VOLTAGE REFERENCE (6)
Accuracy, ADCVREFP
1.9
0.95
0.99
2
1
1
2.1
1.05
1.01
V
V
V
Accuracy, ADCVREFM
Input voltage difference, ADCREFP – ADCREFM
(1) Tested at 12.5-MHz ADCCLK.
(2) If SYSCLKOUT ≤ 25 MHz, ADC clock ≤ SYSCLKOUT/2.
(3) The INL degrades for frequencies beyond 18.75 MHz–25 MHz. Applications that require these sampling rates should use a 20K
resistor as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by the ADC will be a few mA
more than 24.9-kΩ bias.
(4) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
(5) A single internal band gap reference (±5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination of the
gain error shown here and the voltage reference accuracy (ADCREFP – ADCREFM). A software-based calibration procedure is
recommended for better accuracy. See the F2810, F2811, and F2812 ADC Calibration Application Report and Section 11.4 for relevant
documents.
(6) In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP – ADCREFM) will
determine the overall accuracy.
(7) Voltages above VDDA + 0.3 V or below VSS – 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
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8.12.5.15.4 Current Consumption for Different ADC Configurations
8.12.5.15.4.1 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
IDDA (TYP)(1) (2)
IDDAIO (TYP)
IDD1 (TYP)
ADC OPERATING MODE/CONDITIONS
Mode A (Operational Mode):
•
•
BG and REF enabled
PWD disabled
40 mA
1 µA
0.5 mA
Mode B:
•
•
•
ADC clock enabled
7 mA
1 µA
0
0
0
5 µA
5 µA
0
BG and REF enabled
PWD enabled
Mode C:
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
Mode D:
•
•
•
ADC clock disabled
1 µA
BG and REF disabled
PWD enabled
(1) Test Conditions:
•
•
•
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) IDDA – includes current into VDDA1/VDDA2 and AVDDREFBG
Ron
1 kW
Switch
Rs
ADCIN0
Cp
Ch
Source
Signal
ac
10 pF
1.25 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (Ron): 1 kW
Sampling Capacitor (Ch): 1.25 pF
Parasitic Capacitance (Cp): 10 pF
Source Resistance (Rs): 50 W
Figure 8-35. ADC Analog Input Impedance Model
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8.12.5.15.5 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
td(BGR)
PWDNADC
td(PWD)
Request for
ADC Conversion
Figure 8-36. ADC Power-Up Control Bit Timing
8.12.5.15.5.1 ADC Power-Up Delays
MIN(1)
7
TYP
8
MAX UNIT
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
register (ADCBGRFDN1/0) are to be set to 1 before the ADCPWDN bit is
enabled.
td(BGR)
10
ms
Delay time for power-down control to be stable. Bit 5 of the ADCTRL3
register (ADCPWDN) is to be set to 1 before any ADC conversions are
initiated.
20
50
µs
td(PWD)
1
ms
(1) These delays are necessary and recommended to make the ADC analog reference circuit stable before conversions are initiated. If
conversions are started without these delays, the ADC results will show a higher gain. For power down, all three bits can be cleared at
the same time.
8.12.5.15.6 Detailed Description
8.12.5.15.6.1 Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC. ADCVREFP is set
to 2.0 V and ADCVREFM is set to 1.0 V.
8.12.5.15.6.2 Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time.
These inputs are software-selectable.
8.12.5.15.6.3 Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
8.12.5.15.6.4 Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
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8.12.5.15.7 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx).
The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from
an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on
every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below.
The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected
channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be
programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Sample n
Analog Input on
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
tdschx_n+1
td(SH)
tdschx_n
ADC Event Trigger from EV
or Other Sources
tSH
Figure 8-37. Sequential Sampling Mode (Single-Channel) Timing
8.12.5.15.7.1 Sequential Sampling Mode Timing
AT 25-MHz
SAMPLE n
2.5tc(ADCCLK)
SAMPLE n + 1
ADC CLOCK,
tc(ADCCLK) = 40 ns
REMARKS
Delay time from event
trigger to sampling
td(SH)
Sample/
Hold width/
Acquisition width
Acqps value = 0–15
ADCTRL1[8:11]
tSH
(1 + Acqps) * tc(ADCCLK)
40 ns with Acqps = 0
160 ns
Delay time for first
result to appear in the
Result register
td(schx_n)
4tc(ADCCLK)
Delay time for
successive results to
appear in the Result
register
td(schx_n+1)
(2 + Acqps) * tc(ADCCLK)
80 ns
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8.12.5.15.8 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to
A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger,
or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The
selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The Sample/
Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Note
In Simultaneous Mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7, and not in
other combinations (such as A1/B3, and so forth).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
td(SH)
tdschA0_n+1
tSH
ADC Event Trigger from EV
or Other Sources
tdschA0_n
tdschB0_n
tdschB0_n+1
Figure 8-38. Simultaneous Sampling Mode Timing
8.12.5.15.8.1 Simultaneous Sampling Mode Timing
AT 25-MHz
SAMPLE n
SAMPLE n + 1
ADC CLOCK,
REMARKS
tc(ADCCLK) = 40 ns
Delay time from event
trigger to sampling
td(SH)
tSH
2.5tc(ADCCLK)
Sample/Hold width/
Acquisition Width
Acqps value = 0–15
ADCTRL1[8:11]
(1 + Acqps) * tc(ADCCLK)
40 ns with Acqps = 0
160 ns
Delay time for first
result to appear in
Result register
td(schA0_n)
4tc(ADCCLK)
Delay time for first
result to appear in
Result register
td(schB0_n)
5tc(ADCCLK)
200 ns
120 ns
Delay time for
successive results to
appear in Result
register
td(schA0_n+1)
(3 + Acqps) * tc(ADCCLK)
Delay time for
successive results to
appear in Result
register
td(schB0_n+1)
(3 + Acqps) * tc(ADCCLK)
120 ns
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8.12.5.15.9 Definitions of Specifications and Terminology
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2
LSB beyond the last code transition. The deviation is measured from the center of each particular code to the
true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volt. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(SINAD -1.76)
N =
6.02
it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
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8.12.5.16 Multichannel Buffered Serial Port (McBSP) Timing
8.12.5.16.1 McBSP Transmit and Receive Timing
8.12.5.16.1.1 McBSP Timing Requirements
NO.(1)
MIN
MAX UNIT
(2)
1
kHz
20(3) MHz
ns
McBSP module clock (CLKG, CLKX, CLKR) range
McBSP module cycle time (CLKG, CLKX, CLKR) range
50
1
ms
ns
ns
ns
ns
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P – 7
7
7
Fall time, CLKR/X
18
2
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
M20 th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
18
2
0
Hold time, DR valid after CLKR low
6
18
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG/(1 + CLKGDV).
CLKSRG can be LSPCLK, CLKX, CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer
switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (20 MHz).
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8.12.5.16.1.2 McBSP Switching Characteristics
NO.(1)
PARAMETER
MIN
MAX UNIT
(2)
M1
M2
M3
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
FSX int
2P
ns
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 5(3)
D + 5(3)
ns
ns
C – 5(3)
C + 5(3)
0
3
0
3
4
27
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
4
27
8
Disable time, CLKX high to DX high impedance following last
data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
28
8
M7
td(CKXH-DXV)
DXENA = 0
ns
Delay time, CLKX high to DX valid. Only applies to
first bit transmitted when in Data Delay 1 or 2
(XDATDLY = 01b or 10b) modes.
14
P + 8
P + 14
DXENA = 1
0
6
DXENA = 0
Enable time, CLKX high to DX driven. Only
applies to first bit transmitted when in Data Delay
1 or 2 (XDATDLY = 01b or 10b) modes.
M8
M9
ten(CKXH-DX)
ns
ns
ns
P
DXENA = 1
P + 6
8
14
DXENA = 0
Delay time, FSX high to DX valid. Only applies to
first bit transmitted when in Data Delay 0
(XDATDLY = 00b) mode.
FSX ext
td(FXH-DXV)
FSX int
P + 8
P + 14
DXENA = 1
FSX ext
FSX int
0
6
DXENA = 0
Enable time, FSX high to DX driven. Only applies
to first bit transmitted when in Data Delay 0
(XDATDLY = 00b) mode.
FSX ext
M10 ten(FXH-DX)
FSX int
P
DXENA = 1
FSX ext
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M1, M11
M2, M12
M3, M12
M13
CLKR
FSR (int)
FSR (ext)
M4
M4
M14
M15
M17
M16
M18
DR
(RDATDLY=00b)
Bit (n-1)
M17
(n-2)
(n-3)
(n-2)
(n-4)
M18
DR
(RDATDLY=01b)
Bit (n-1)
(n-3)
(n-2)
M17
M18
DR
(RDATDLY=10b)
Bit (n-1)
Figure 8-39. McBSP Receive Timing
M1, M11
M2, M12
M13
M14
M3, M12
CLKX
FSX (int)
FSX (ext)
M5
M5
M19
M20
M9
M7
M10
DX
(XDATDLY=00b)
Bit (n-1)
(n-2)
(n-3)
(n-4)
(n-3)
(n-2)
Bit 0
M7
M8
DX
(XDATDLY=01b)
Bit (n-1)
M8
(n-2)
M7
Bit 0
M6
DX
(XDATDLY=10b)
Bit (n-1)
Bit 0
Figure 8-40. McBSP Transmit Timing
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8.12.5.16.2 McBSP as SPI Master or Slave Timing
8.12.5.16.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.(1) (2)
UNIT
MIN
30
1
MAX
M30
M31
M32
M33
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(BFXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
8.12.5.16.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.(1)
PARAMETER
UNIT
MIN
2P
P
MAX
M24
M25
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
Disable time, DX high impedance following last data bit
from FSX high
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M33
M32
M25
LSB
MSB
CLKX
M24
FSX
DX
M28
M29
Bit(n-1)
Bit(n-1)
(n-2)
M31
(n-3)
(n-4)
Bit 0
M30
DR
(n-2)
(n-3)
(n-4)
Bit 0
Figure 8-41. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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8.12.5.16.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
MIN
NO.(1) (2)
MIN
30
1
MAX
MAX
M39
M40
M41
M42
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXH)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
8P – 10
16P + 10
16P
ns
ns
ns
ns
2P
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
8.12.5.16.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER
SLAVE
MIN MAX
NO.(1)
PARAMETER
UNIT
MIN
P
MAX
M34
M35
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
ns
ns
2P
Disable time, DX high impedance following last data bit
from CLKX low
M37
M38
tdis(CKXL-DXHZ)
td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M42
LSB
MSB
M41
CLKX
FSX
M34
M35
M37
M38
DX
DR
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
M39
M40
(n-2)
Bit 0
(n-3)
(n-4)
Figure 8-42. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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8.12.5.16.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.(1) (2)
UNIT
MIN
30
1
MAX
M49
M50
M51
M52
tsu(DRV-CKXH)
th(CKXH-DRV)
tsu(FXL-CKXL)
tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
8.12.5.16.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN
NO.(1)
PARAMETER
UNIT
MIN
2P
P
MAX
MAX
M43
M44
th(CKXH-FXL)
td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
Disable time, DX high impedance following last data bit
from FSX high
M47
M48
tdis(FXH-DXHZ)
td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
LSB
MSB
M51
M52
CLKX
M43
M44
M48
FSX
DX
M47
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
Bit 0
M49
M50
DR
(n-2)
(n-3)
Bit 0
Figure 8-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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UNIT
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8.12.5.16.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN
NO.(1) (2)
MIN
30
1
MAX
MAX
M58
M59
M60
M61
tsu(DRV-CKXL)
th(CKXL-DRV)
tsu(FXL-CKXL)
tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
8P – 10
16P + 10
16P
ns
ns
ns
ns
2P
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
8.12.5.16.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.(1)
PARAMETER
UNIT
MIN
P
MAX
M53
M54
M55
th(CKXH-FXL)
td(FXL-CKXL)
td(CLKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
ns
ns
ns
2P
–2
0
3P + 6 5P + 20
7P + 6
Disable time, DX high impedance following last data bit
from CLKX high
M56
M57
tdis(CKXH-DXHZ)
td(FXL-DXV)
P + 6
6
ns
ns
Delay time, FSX low to DX valid
4P + 6
(1) 2P = 1/CLKG
M61
M60
M54
MSB
LSB
CLKX
FSX
DX
M53
M56
M57
M55
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
M58
M59
(n-2)
DR
Bit(n-1)
(n-3)
(n-4)
Bit 0
Figure 8-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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8.12.6 Emulator Connection Without Signal Buffering for the DSP
Figure 8-45 shows the connection between the DSP and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 8-45 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
6 inches or less
VDDIO
VDDIO
13
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
PD
14
2
4
6
8
GND
GND
GND
GND
GND
TRST
TMS
1
3
TDI
7
10
12
TDO
TCK
TDO
11
TCK
9
TCK_RET
DSP
JTAG Header
Figure 8-45. Emulator Connection Without Signal Buffering for the DSP
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8.12.7 Interrupt Timing
8.12.7.1 Interrupt Switching Characteristics
PARAMETER
MIN
MAX
12
UNIT
Without input qualifier
Delay time, PDPINTx low to PWM high-
impedance state
td(PDP-PWM)HZ
ns
With input qualifier
Without input qualifier
With input qualifier
1tc(SCO) + IQT + 12(1)
3 * tc(SCO)
Delay time, CxTRIP/ TxCTRIP signals low to
PWM high-impedance state
td(TRIP-PWM)HZ
td(INT)
ns
ns
2tc(SCO) + IQT(1)
(1)
Delay time, INT low/high to interrupt-vector fetch
IQT + 12tc(SCO)
(1) Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
8.12.7.2 Interrupt Timing Requirements
MIN
MAX
UNIT
With no qualifier
2tc(SCO)
tw(INT)
Pulse duration, INT input low/high
Pulse duration, PDPINTx input low
Pulse duration, CxTRIP input low
Pulse duration, TxCTRIP input low
cycles
With qualifier
1tc(SCO) + IQT(1)
2tc(SCO)
1tc(SCO) + IQT(1)
2tc(SCO)
1tc(SCO) + IQT(1)
2tc(SCO)
With no qualifier
With qualifier
tw(PDP)
cycles
cycles
cycles
With no qualifier
With qualifier
tw(CxTRIP)
With no qualifier
With qualifier
tw(TxCTRIP)
1tc(SCO) + IQT(1)
(1) Input Qualification Time (IQT) = [tc(SCO) × 2 × QUALPRD] × 5 + [tc(SCO) × 2 × QUALPRD].
XCLKOUT(A)
tw(PDP), tw(CxTRIP), tw(TxCTRIP)
TxCTRIP,
CxTRIP,
PDPINTx(B)
td(PDP-PWM)HZ, td(TRIP-PWM)HZ
PWM(C)
tw(INT)
XNMI,
XINT1, XINT2
td(INT)
Interrupt Vector
A0-A15
A. XCLKOUT = SYSCLKOUT
B. TxCTRIP – T1CTRIP, T2CTRIP, T3CTRIP, T4CTRIP CxTRIP – C1TRIP, C2TRIP, C3TRIP, C4TRIP, C5TRIP, or C6TRIP PDPINTx –
PDPINTA or PDPINTB
C. PWM refers to all the PWM pins in the device (that is, PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin). The state
of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit.
Figure 8-46. External Interrupt Timing
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8.12.8 Flash Timing
8.12.8.1 Flash Endurance for A and S Temperature Material
ERASE/PROGRAM
MIN
TYP
MAX UNIT
TEMPERATURE(1)
Nf
Flash endurance for the array (Write/Erase cycles) 0°C to 85°C (ambient)
20000(2)
50000(2)
cycles
NOTP
OTP endurance for the array (Write cycles)
0°C to 85°C (ambient)
1
write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
(2) The Write/Erase cycle numbers of 20000 (MIN) and 50000 (TYP) are applicable only for silicon revision G. For older silicon revisions,
the Write/Erase cycle numbers of 100 (MIN) and 1000 (TYP) are applicable.
8.12.8.2 Flash Endurance for Q Temperature Material
ERASE/PROGRAM
MIN
TYP
MAX UNIT
TEMPERATURE(1)
Nf
Flash endurance for the array (Write/Erase cycles) –40°C to 125°C (ambient)
20000(2)
50000(2)
cycles
NOTP
OTP endurance for the array (Write cycles)
–40°C to 125°C (ambient)
1
write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
(2) The Write/Erase cycle numbers of 20000 (MIN) and 50000 (TYP) are applicable only for silicon revision G. For older silicon revisions,
the Write/Erase cycle numbers of 100 (MIN) and 1000 (TYP) are applicable.
8.12.8.3 Flash Parameters at 150-MHz SYSCLKOUT
PARAMETER(1)
MIN
TYP
35
MAX UNIT
Using Flash API v1(2)
Using Flash API v2.10
Using Flash API v1(2)
Using Flash API v2.10
Using Flash API v1(2)
Using Flash API v2.10
16-Bit Word
8K Sector
µs
50
170
250
320
500
10
Program Time
ms
ms
s
16K Sector
8K Sector
Erase Time(3)
16K Sector
11
Erase
75
IDD3VFLP
VDD3VFL current consumption during the Erase/Program cycle
mA
Program
35
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
140
20
mA
mA
IDDIOP
(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
(2) Flash API v1.00 is useable on rev. C silicon only.
(3) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
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8.12.8.4 Flash/OTP Access Timing
PARAMETER
MIN
36
MAX UNIT
ta(fp)
Paged Flash access time
Random Flash access time
OTP access time
ns
ns
ns
ta(fr)
36
ta(OTP)
60
8.12.8.5 Flash Data Retention Duration
PARAMETER
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX UNIT
tretention
Data retention duration
years
Table 8-5. Minimum Required Flash Wait States at Different Frequencies
PAGE
RANDOM
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
OTP
WAIT STATE(1)
WAIT STATE(1) (2)
150
120
100
75
6.67
8.33
10
5
4
3
2
1
1
0
0
0
5
4
3
2
1
1
1
1
1
8
7
5
4
2
1
1
1
1
13.33
20
50
30
33.33
40
25
15
66.67
250
4
(1) Formulas to compute page wait state and random wait state:
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(fp)
Flash Page Wait State =
-1 (round up to the next highest integer, or 0, whichever is larger)
ú
tc(SCO)
ê
ú
û
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(fr)
Flash Random Wait State =
-1 (round up to the next highest integer, or 1, whichever is larger)
ú
tc(SCO)
ê
ú
û
é
ê
ë
ù
æ
ç
ç
è
ö
÷
÷
ø
ta(OTP)
OTP Wait State =
-1 (round up to the next highest integer, or 1, whichever is larger)
ú
tc(SCO)
ê
ú
û
(2) Random wait state must be greater than or equal to 1.
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9 Detailed Description
9.1 Brief Descriptions
9.1.1 C28x CPU
The C28x DSP generation is the newest member of the TMS320C2000™ DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software
investment. Additionally, the C28x is a very efficient C/C++ engine, enabling users to develop not only their
system control software in a high-level language, but also enables math algorithms to be developed using C/C+
+. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by
microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-
bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle
higher numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a
device that is capable of servicing many asynchronous events with minimal latency. The C28x has an 8-level-
deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high
speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes
the latency for conditional discontinuities. Special store conditional operations further improve performance.
9.1.2 Memory Bus (Harvard Bus Architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to
the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses can be
summarized as follows:
Highest:
Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)
9.1.3 Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F281x
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various
busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and 16 or
32 data lines and associated control signals. Two versions of the peripheral bus are supported on the F281x.
One version only supports 16-bit accesses (called peripheral frame 2). The other version supports both 16- and
32-bit accesses (called peripheral frame 1).
9.1.4 Real-Time JTAG and Analysis
The F281x implements the standard IEEE 1149.1 JTAG interface. Additionally, the F281x supports real-time
mode of operation whereby the contents of memory, peripheral, and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through non-
time critical code while enabling time-critical interrupts to be serviced without interference. The F281x
implements the real-time mode in hardware within the CPU. This is a unique feature to the F281x, no software
monitor is required. Additionally, special analysis hardware is provided that allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
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9.1.5 External Interface (XINTF) (F2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The chip-
select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single chip-select;
Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with a different
number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait
states externally or not. The programmable wait-state, chip-select and programmable strobe timing enables
glueless interface to external memories and peripherals.
9.1.6 Flash
The F2812 and F2811 contain 128K x 16 of embedded flash memory, segregated into four 8K x 16 sectors, and
six 16K x 16 sectors. The F2810 has 64K x 16 of embedded flash, segregated into two 8K x 16 sectors, and
three 16K x 16 sectors. All three devices also contain a single 1K x 16 of OTP memory at address range 0x3D
7800–0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other
sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash
algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to
achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be
used to execute code or store data information.
Note
The F2810/F2811/F2812 Flash and OTP wait states can be configured by the application. This allows
applications running at slower frequencies to configure the flash to use fewer wait states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the
TMS320x281x DSP System Control and Interrupts Reference Guide.
9.1.7 M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks and
hence the mapping of data variables on the 240x devices can remain at the same physical address on C28x
devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and
data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is
performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for
easier programming in high-level languages.
9.1.8 L0, L1, H0 SARAMs
The F281x contains an additional 16K x 16 of single-access RAM, divided into three blocks (4K + 4K + 8K).
Each block can be independently accessed hence minimizing pipeline stalls. Each block is mapped to both
program and data space.
9.1.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. The Boot ROM program executes after device
reset and checks several GPIO pins to determine which boot mode to enter. For example, the user can select to
execute code already present in the internal Flash or download new software to internal RAM through one of
several serial ports. Other boot modes exist as well. The Boot ROM also contains standard tables, such as
SIN/COS waveforms, for use in math-related algorithms. Table 9-1 shows the details of how various boot modes
may be invoked. See the TMS320x281x DSP Boot ROM Reference Guide, for more information.
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Table 9-1. Boot Mode Selection
GPIOF4
(SCITXDA)
GPIOF12
(MDXA)
GPIOF3
(SPISTEA)
GPIOF2
(SPICLK)
BOOT MODE SELECTED(1) (2)
GPIO PU status(3)
PU
No PU
No PU
x
No PU
x
Jump to Flash address 0x3F 7FF6.
A branch instruction must have been programmed here prior to
reset to re-direct code execution as desired.
1
x
Call SPI_Boot to load from an external serial SPI EEPROM
Call SCI_Boot to load from SCI-A
0
0
0
0
0
1
0
0
0
0
x
1
1
0
0
x
1
0
1
0
Jump to H0 SARAM address 0x3F 8000
Jump to OTP address 0x3D 7800
Call Parallel_Boot to load from GPIO Port B
(1) Extra care must be taken due to any effect toggling SPICLK to select a boot mode may have on external logic.
(2) If the boot mode selected is Flash, H0, or OTP, then no external code is loaded by the bootloader.
(3) PU = pin has an internal pullup. No PU = pin does not have an internal pullup.
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9.1.10 Security
The F281x supports high levels of security to protect the user firmware from being reverse-engineered. The
security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. One
code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature
prevents unauthorized users from examining the memory contents via the JTAG port, executing code from
external memory or trying to boot-load some undesirable software that would export the secure memory
contents. To enable access to the secure blocks, the user must write the correct 128-bit ”KEY” value, which
matches the value stored in the password locations within the Flash.
Note
•
When the code-security passwords are programmed, all addresses between 0x3F 7F80 and
0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to
0x0000.
•
•
If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for
code or data.
The 128-bit password (at 0x3F 7FF8–0x3F 7FFF) must not be programmed to zeros. Doing so
would permanently lock the device.
Table 9-2. Impact of Using the Code Security Module
CODE SECURITY STATUS
ADDRESS
Code Security Enabled
Code Security Disabled
0x3F 7F80 – 0x3F 7FEF
0x3F 7FF0 – 0x3F 7FF5
0x3D 7BFC – 0x3D 7BFF
Fill with 0x0000
Application code and data(1)
Application code and data
(1) See the TMS320F281x DSPs Silicon Errata for some restrictions.
Note
Code Security Module Disclaimer
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR
FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANT ABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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9.1.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the F281x, 45 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes
8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to
interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can
be enabled/disabled within the PIE block.
9.1.12 External Interrupts (XINT1, XINT2, XINT13, XNMI)
The F281x supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked
external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected
for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked
interrupts also contain a 16-bit free-running up-counter, which is reset to zero when a valid interrupt edge is
detected. This counter can be used to accurately time-stamp the interrupt.
9.1.13 Oscillator and PLL
The F281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL
is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in software,
enabling the user to scale back on operating frequency if lower power operation is desired. Refer to Section 8 for
timing details. The PLL block can be set in bypass mode.
9.1.14 Watchdog
The F281x supports a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
9.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event managers,
CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be
decoupled from increasing CPU clock speeds.
9.1.16 Low-Power Modes
The F281x devices are fully static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that must
function during IDLE are left operating. An enabled interrupt from an active peripheral will wake the processor from
IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event.
Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible power
consumption mode. Only a reset or XNMI can wake the device from this mode.
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9.1.17 Peripheral Frames 0, 1, 2 (PFn)
The F281x segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0:
XINTF:
PIE:
External Interface Configuration Registers (F2812 only)
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Control, Programming, Erase, Verify Registers
CPU-Timers 0, 1, 2 Registers
Flash:
Timers:
CSM:
eCAN:
SYS:
Code Security Module KEY Registers
PF1:
PF2:
eCAN Mailbox and Control Registers
System Control Registers
GPIO:
EV:
GPIO Mux Configuration and Control Registers
Event Manager (EVA/EVB) Control Registers
McBSP Control and TX/RX Registers
McBSP:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Peripheral Interface (SPI) Control and RX/TX Registers
12-Bit ADC Registers
SPI:
ADC:
9.1.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing
enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are
configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal mode.
For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise
glitches.
9.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the DSP/BIOS Real-
Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for
general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for
general use and is connected to the PIE block.
9.1.20 Control Peripherals
The F281x supports the following peripherals that are used for embedded control and communication:
EV:
The event manager module includes general-purpose timers, full-compare/PWM units, capture inputs (CAP) and
quadrature-encoder pulse (QEP) circuits. Two such event managers are provided which enable two three-phase
motors to be driven or four two-phase motors. The event managers on the F281x are compatible to the event
managers on the 240x devices (with some minor enhancements).
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-and-hold units for
simultaneous sampling.
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9.1.21 Serial Port Peripherals
The F281x supports the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time stamping of messages, and is
compliant with ISO 11898-1 (CAN 2.0B).
McBSP:
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality codecs for modem applications
or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported by a 16-level
FIFO that significantly reduces the overhead for servicing this peripheral.
SPI:
SCI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to
sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-
device communications are supported by the master/slave operation of the SPI. On the F281x, the port supports a 16-
level, receive-and-transmit FIFO for reducing servicing overhead.
The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. On the
F281x, the port supports a 16-level, receive-and-transmit FIFO for reducing servicing overhead.
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9.2 Peripherals
The integrated peripherals of the F281x are described in the following subsections:
•
•
•
•
•
•
•
•
Three 32-bit CPU-Timers
Two event-manager modules (EVA, EVB)
Enhanced analog-to-digital converter (ADC) module
Enhanced controller area network (eCAN) module
Multichannel buffered serial port (McBSP) module
Serial communications interface modules (SCI-A, SCI-B)
Serial peripheral interface (SPI) module
Digital I/O and shared pin functions
9.2.1 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the F281x devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user applications. These
timers are different from the general-purpose (GP) timers that are present in the Event Manager modules (EVA,
EVB).
Note
If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 9-1. CPU-Timers
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In the F281x devices, the timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 9-2.
INT1
to
INT12
TINT0
PIE
CPU-TIMER 0
C28x
CPU
TINT1
INT13
INT14
CPU-TIMER 1
XINT13
CPU-TIMER 2
(Reserved for
DSP/BIOS)
TINT2
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 9-2. CPU-Timer Interrupts Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register “TIMH:TIM” is loaded with the value
in the period register “PRDH:PRD”. The counter register decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in
Table 9-3 are used to configure the timers. For more information, see the TMS320x281x DSP System Control
and Interrupts Reference Guide.
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Table 9-3. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
TIMER0TIM
ADDRESS
SIZE (x16)
DESCRIPTION
0x00 0C00
1
CPU-Timer 0, Counter Register
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
0x00 0C01
0x00 0C02
0x00 0C03
0x00 0C04
0x00 0C05
0x00 0C06
0x00 0C07
0x00 0C08
0x00 0C09
0x00 0C0A
0x00 0C0B
0x00 0C0C
0x00 0C0D
0x00 0C0E
0x00 0C0F
0x00 0C10
0x00 0C11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
40
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
0x00 0C12
0x00 0C13
0x00 0C14
0x00 0C15
0x00 0C16
0x00 0C17
0x00 0C18 – 0x00 0C3F
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
Reserved
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
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9.2.2 Event Manager Modules (EVA, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and
quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function
identically. However, timer/unit names differ for EVA and EVB. Table 9-4 shows the module and signal names
used. Table 9-4 shows the features and functionality available for the event-manager modules and highlights
EVA nomenclature.
Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at
7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and
QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function—however,
module/signal names would differ. Table 9-5 lists the EVA registers. For more information, see the TMS320x281x
DSP Event Manager (EV) Reference Guide.
Table 9-4. Module and Signal Names for EVA and EVB
EVA
EVB
EVENT MANAGER
MODULES
MODULE
SIGNAL
MODULE
SIGNAL
GP Timer 1
GP Timer 2
T1PWM/T1CMP
T2PWM/T2CMP
GP Timer 3
GP Timer 4
T3PWM/T3CMP
T4PWM/T4CMP
GP Timers
Compare 1
Compare 2
Compare 3
PWM1/2
PWM3/4
PWM5/6
Compare 4
Compare 5
Compare 6
PWM7/8
PWM9/10
PWM11/12
Compare Units
Capture 1
Capture 2
Capture 3
CAP1
CAP2
CAP3
Capture 4
Capture 5
Capture 6
CAP4
CAP5
CAP6
Capture Units
QEP1
QEP2
QEPI1
QEP3
QEP4
QEPI2
QEP1
QEP2
QEP3
QEP4
QEP Channels
Direction
External Clock
TDIRA
TCLKINA
Direction
External Clock
TDIRB
TCLKINB
External Clock Inputs
External Trip Inputs
External Trip Inputs
C1TRIP
C2TRIP
C3TRIP
C4TRIP
C5TRIP
C6TRIP
Compare
Compare
T1CTRIP_PDPINTA (1)
T2CTRIP/ EVASOC
T3CTRIP_PDPINTB (1)
T4CTRIP/ EVBSOC
(1) In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as
PDPINTB.
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Table 9-5. EVA Registers
SIZE (x16)
NAME(1)
GPTCONA
ADDRESS
0x00 7400
0x00 7401
0x00 7402
0x00 7403
0x00 7404
0x00 7405
0x00 7406
0x00 7407
0x00 7408
0x00 7409
0x00 7411
0x00 7413
0x00 7415
0x00 7417
0x00 7418
0x00 7419
0x00 7420
0x00 7422
0x00 7423
0x00 7424
0x00 7425
0x00 7427
0x00 7428
0x00 7429
0x00 742C
0x00 742D
0x00 742E
0x00 742F
0x00 7430
0x00 7431
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GP Timer Control Register A
GP Timer 1 Counter Register
GP Timer 1 Compare Register
GP Timer 1 Period Register
GP Timer 1 Control Register
GP Timer 2 Counter Register
GP Timer 2 Compare Register
GP Timer 2 Period Register
GP Timer 2 Control Register
T1CNT
T1CMPR
T1PR
T1CON
T2CNT
T2CMPR
T2PR
T2CON
EXTCONA(2)
COMCONA
ACTRA
GP Extension Control Register A
Compare Control Register A
Compare Action Control Register A
Dead-Band Timer Control Register A
Compare Register 1
DBTCONA
CMPR1
CMPR2
Compare Register 2
CMPR3
Compare Register 3
CAPCONA
CAPFIFOA
CAP1FIFO
CAP2FIFO
CAP3FIFO
CAP1FBOT
CAP2FBOT
CAP3FBOT
EVAIMRA
EVAIMRB
EVAIMRC
EVAIFRA
EVAIFRB
EVAIFRC
Capture Control Register A
Capture FIFO Status Register A
Two-Level-Deep Capture FIFO Stack 1
Two-Level-Deep Capture FIFO Stack 2
Two-Level-Deep Capture FIFO Stack 3
Bottom Register of Capture FIFO Stack 1
Bottom Register of Capture FIFO Stack 2
Bottom Register of Capture FIFO Stack 3
Interrupt Mask Register A
Interrupt Mask Register B
Interrupt Mask Register C
Interrupt Flag Register A
Interrupt Flag Register B
Interrupt Flag Register C
(1) The EV-B register set is identical except the address range is from 0x00 7500 to 0x00 753F. The above registers are mapped to Zone
2. This space allows only 16-bit accesses. 32-bit accesses produce undefined results.
(2) New register compared to 24x/240x
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GPTCONA[12:4], CAPCONA[8], EXTCONA[0]
EVAENCLK
EVATO ADC (Internal)
T1CTRIP/PDPINTA, T2CTRIP, C1TRIP, C2TRIP, C3TRIP
EVASOC ADC (External)
Control Logic
Output
Logic
T1PWM_T1CMP
Timer 1 Compare
T1CON[5,4]
GPTCONA[1,0]
Prescaler
T1CON[1]
TCLKINA
HSPCLK
clock
GP Timer 1
dir
T1CON[10:8]
TDIRA
T1CON[15:11,6,3,2]
PWM1
PWM2
PWM3
Full Compare 1
Full Compare 2
Full Compare 3
SVPWM
State
Machine
Dead-Band
Logic
Output
Logic
PWM4
PWM5
PWM6
DBTCONA[15:0]
COMCONA[15:5,2:0]
ACTRA[15:12],
COMCONA[12],
T1CON[13:11]
ACTRA[11:0]
Output
Logic
Timer 2 Compare
T2PWM_T2CMP
T2CON[5,4]
T2CON[1]
GPTCONA[3,2]
TCLKINA
HSPCLK
clock
dir
reset
Prescaler
GP Timer 2
QEPCLK
QEPDIR
T2CON[10:8]
T2CON[15:11,7,6,3,2,0]
QEP
Logic
CAPCONA[10,9]
TDIRA
CAP1_QEP1
CAP2_QEP2
Capture Units
CAP3_QEPI1
Index Qual
CAPCONA[15:12,7:0]
EXTCONA[1:2]
A. The EVB module is similar to the EVA module.
Figure 9-3. Event Manager A Functional Block Diagram
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9.2.2.1 General-Purpose (GP) Timers
There are two GP timers. The GP timer x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:
•
•
•
•
•
•
•
A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes
A 16-bit timer-control register, TxCON, for reads or writes
Selectable internal or external input clocks
A programmable prescaler for internal or external clock inputs
Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period
interrupts
•
A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is
selected)
The GP timers can be operated independently or synchronized with each other. The compare register
associated with each GP timer can be used for compare function and PWM-waveform generation. There are
three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or
external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time
base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1
for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare
registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as
needed.
9.2.2.2 Full-Compare Units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time
base and generate six outputs for compare and PWM-waveform generation using programmable deadband
circuit. The state of each of the six outputs is configured independently. The compare registers of the compare
units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
9.2.2.3 Programmable Deadband Generator
Deadband generation can be enabled/disabled for each compare unit output individually. The deadband-
generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The
output states of the deadband generator are configurable and changeable as needed by way of the double-
buffered ACTRx register.
9.2.2.4 PWM Waveform Generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three
independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two
independent PWMs by the GP-timer compares.
9.2.2.5 Double Update PWM Mode
The F281x Event Manager supports “Double Update PWM Mode.” This mode refers to a PWM operation mode
in which the position of the leading edge and the position of the trailing edge of a PWM pulse are independently
modifiable in each PWM period. To support this mode, the compare register that determines the position of the
edges of a PWM pulse must allow (buffered) compare value update once at the beginning of a PWM period and
another time in the middle of a PWM period. The compare registers in F281x Event Managers are all buffered
and support three compare value reload/update (value in buffer becoming active) modes. These modes have
earlier been documented as compare value reload conditions. The reload condition that supports double update
PWM mode is reloaded on Underflow (beginning of PWM period) OR Period (middle of PWM period). Double
update PWM mode can be achieved by using this condition for compare value reload.
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9.2.2.6 PWM Characteristics
Characteristics of the PWMs are as follows:
•
•
•
•
•
•
16-bit registers
Wide range of programmable deadband for the PWM output pairs
Change of the PWM carrier frequency for PWM frequency wobbling as needed
Change of the PWM pulse widths within and after each PWM period as needed
External-maskable power and drive-protection interrupts
Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space
vector PWM waveforms
•
•
Minimized CPU overhead using auto-reload of the compare and period registers
The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx
signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register.
– PDPINTA pin status is reflected in bit 8 of COMCONA register.
– PDPINTB pin status is reflected in bit 8 of COMCONB register.
•
EXTCON register bits provide options to individually trip control for each PWM pair of signals
9.2.2.7 Capture Unit
The capture unit provides a logging function for different events or transitions. The values of the selected GP
timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected
on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three
capture circuits.
Capture units include the following features:
•
•
•
•
•
One 16-bit capture control register, CAPCONx (R/W)
One 16-bit capture FIFO status register, CAPFIFOx
Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base
Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit. [All inputs
are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at
its current level to meet the input qualification circuitry requirements. The input pins CAP1/2 and CAP4/5 can
also be used as QEP inputs to the QEP circuit.]
•
•
•
User-specified transition (rising edge, falling edge, or both edges) detection
Three maskable interrupt flags, one for each capture unit
The capture pins can also be used as general-purpose interrupt pins, if they are not used for the capture
function.
9.2.2.8 Quadrature-Encoder Pulse (QEP) Circuit
Two capture inputs (CAP1 and CAP2 for EVA; CAP4 and CAP5 for EVB) can be used to interface the on-chip
QEP circuit with a quadrature encoder pulse. Full synchronization of these inputs is performed on-chip. Direction
or leading-quadrature pulse sequence is detected, and GP timer 2/4 is incremented or decremented by the rising
and falling edges of the two input signals (four times the frequency of either input pulse).
With EXTCONA register bits, the EVA QEP circuit can use CAP3 as a capture index pin as well. Similarly, with
EXTCONB register bits, the EVB QEP circuit can use CAP6 as a capture index pin.
9.2.2.9 External ADC Start-of-Conversion
EVA/EVB start-of-conversion (SOC) can be sent to an external pin ( EVASOC/ EVBSOC) for external ADC
interface. EVASOC and EVBSOC are MUXed with T2CTRIP and T4CTRIP, respectively.
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9.2.3 Enhanced Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 9-4. The ADC module consists of a
12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (voltages above 3.0 V produce full-scale conversion results)
Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
16-channel, MUXed inputs
Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be
programmed to select any 1 of 16 input channels
•
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (that
is, two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
, when ADCIN £ ADCLO
, when ADCLO < ADCIN < 3 V
, when ADCIN ³ 3 V
Digital Value = 0
ADCIN - ADCLO
4096 ´
(
Digital Value = floor
(
3
Digital Value = 4095
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W – software immediate start
– EVA – Event manager A (multiple event sources within EVA)
– EVB – Event manager B (multiple event sources within EVB)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize
conversions
•
•
•
•
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
The ADC module in the F281x has been enhanced to provide flexible interface to event managers A and B. The
ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC
clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event
managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module.
Although there are multiple input channels and two sequencers, there is only one converter in the ADC module.
Figure 9-4 shows the block diagram of the F281x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the
choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion
is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the
system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This
gives increased resolution over traditional single-sampled conversion results.
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SYSCLKOUT
System
Control Block
High-Speed
Prescaler
C28x
ADCENCLK
HSPCLK
Analog
MUX
Result Registers
Result Reg 0
Result Reg 1
ADCINA0
70A8h
S/H
ADCINA7
ADCINB0
ADCINB7
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
EVA
ADCSOC
S/W
EVB
Sequencer 1
Sequencer 2
SOC
SOC
Figure 9-4. Block Diagram of the F281x ADC Module
To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible, traces
leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2, AVDDREFBG) from the digital
supply. For better accuracy and ESD protection, unused ADC inputs should be connected to analog ground.
Notes:
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is
controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:
ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) the clock to the register will still
function. This is necessary to make sure all registers and modes go into their default reset state. The analog
module will, however, be in a low-power inactive state. As soon as reset goes high, then the clock to the
registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will
be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the
ADC is stable and can be used.
HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is
powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU,
which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.
Figure 9-5 shows the ADC pin-biasing for internal reference and Figure 9-6 shows the ADC pin-biasing for
external reference.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0-3 V with respect to ADCLO
Connect to Analog Ground
Test Pin ADCBGREFIN(A)
(B)
24.9 k /20 k
ADC External Current Bias Resistor
ADCRESEXT
ADCREFP
10 μF(C)
10 μF(C)
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP and ADCREFM should not
be loaded by external circuitry
ADCREFM
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Analog Power
Analog 3.3 V
AVDDREFBG
AVSSREFBG
VDDAIO
ADC Reference Power
ADC Analog I/O Power
Analog 3.3 V
VSSAIO
Analog Ground
VDD1
VSS1
1.8 V can use the same 1.8-V (or 1.9-V) supply as
the digital core but separate the two with a
ferrite bead or a filter
ADC Digital Power
Digital Ground
A. Provide access to this pin in PCB layouts. Intended for test purposes only.
B. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.
C. TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor
D. External decoupling capacitors are recommended on all power pins.
E. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 9-5. ADC Pin Connections With Internal Reference
Note
The temperature rating of any recommended component must match the rating of the end product.
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ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog Input 0-3 V With Respect to ADCLO
Connect to Analog Ground
Test Pin ADCBGREFIN
(C)
24.9 k /20 k
ADC External Current Bias Resistor
ADCRESEXT
ADCREFP
ADC Reference Positive Input
ADC Reference Medium Input
2 V
(D)
1 V
ADCREFM
1 μF - 10 μF
1 μF - 10 μF
VDDA1
VDDA2
VSSA1
VSSA2
Analog 3.3 V
Analog 3.3 V
ADC Analog Power
AVDDREFBG
AVSSREFBG
Analog 3.3 V
ADC Reference Power
ADC Analog I/O Power
ADC Digital Power
VDDAIO
VSSAIO
Analog 3.3 V
Analog Ground
VDD1
VSS1
1.8 V can use the same 1.8-V (or 1.9-V)
supply as the digital core but separate the
two with a ferrite bead or a filter
Digital Ground
A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.
D. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP – ADCREFM) = 1 V ± 0.1% or
better. External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external
reference is critical for overall gain. The voltage ADCREFP – ADCREFM will determine the overall accuracy. Do not enable internal
references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital
Converter (ADC) Reference Guide for more information.
Figure 9-6. ADC Pin Connections With External Reference
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The ADC operation is configured, controlled, and monitored by the registers listed in Table 9-6.
Table 9-6. ADC Registers
NAME(1)
ADDRESS
0x00 7100
0x00 7101
0x00 7102
0x00 7103
0x00 7104
0x00 7105
0x00 7106
0x00 7107
0x00 7108
0x00 7109
0x00 710A
0x00 710B
0x00 710C
0x00 710D
0x00 710E
0x00 710F
0x00 7110
0x00 7111
SIZE (x16)
DESCRIPTION
ADCTRL1
ADCTRL2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
ADC Control Register 1
ADC Control Register 2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
0x00 7112
0x00 7113
0x00 7114
0x00 7115
0x00 7116
0x00 7117
0x00 7118
0x00 7119
0x00 711C – 0x00 711F
ADCST
ADC Status Register
Reserved
(1) The above registers are Peripheral Frame 2 Registers.
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9.2.4 Enhanced Controller Area Network (eCAN) Module
The CAN module has the following features:
•
•
•
Fully compliant with ISO 11898-1 (CAN 2.0B)
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit time stamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
•
•
•
•
•
Self-test mode
– Operates in a loopback mode receiving its own message. A “dummy” acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
NOTE: For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 23.4 kbps.
The 28x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for details.
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eCAN0INT
eCAN1INT
Controls Address
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 x 32-Bit Words
Message Objects Control
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 9-7. eCAN Block Diagram and Interface Circuit
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Table 9-7. 3.3-V eCAN Transceivers for the TMS320F281x DSPs
PART
NUMBER
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
VREF
OTHER
TA
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
–
Yes
–
Sleep
Yes
–
None
None
None
None
–
None
None
–
Standby
Adjustable
Diagnostic Loopback
Standby
and
Sleep
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Adjustable
Adjustable
None
None
–
–40°C to 125°C
–40°C to 125°C
Standby
Autobaud Loopback
Built-in Isolation
Low Prop Delay
ISO1050
3–5.5 V
None
None
None
Thermal Shutdown
Failsafe Operation
Dominant Time-out
–55°C to 105°C
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eCAN Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
Control and Status Registers
603Fh
6040h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
607Fh
6080h
Master Control - CANMC
Message Object Time Stamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
60BFh
60C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
60FFh
eCAN Memory RAM (512 Bytes)
6100h-6107h
6108h-610Fh
6110h-6117h
6118h-611Fh
6120h-6127h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Time Stamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
61E8h-61EFh
61F0h-61F7h
61F8h-61FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
61E8h-61E9h
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
Figure 9-8. eCAN Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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The CAN registers listed in Table 9-8 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
Table 9-8. CAN Registers
SIZE (x32)
NAME(1)
CANME
ADDRESS
0x00 6000
0x00 6002
0x00 6004
0x00 6006
0x00 6008
0x00 600A
0x00 600C
0x00 600E
0x00 6010
0x00 6012
0x00 6014
0x00 6016
0x00 6018
0x00 601A
0x00 601C
0x00 601E
0x00 6020
0x00 6022
0x00 6024
0x00 6026
0x00 6028
0x00 602A
0x00 602C
0x00 602E
0x00 6030
0x00 6032
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
CANMD
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Time stamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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9.2.5 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
•
•
Compatible to McBSP in TMS320C54x/TMS320C55x DSP devices, except the DMA features
Full-duplex communication
Double-buffered data registers which allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Support A-bis mode
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
•
•
•
Works with SPI-compatible devices
Two 16 x 16-level FIFO for Transmit channel
Two 16 x 16-level FIFO for Receive channel
The following application interfaces can be supported on the McBSP:
•
•
T1/E1 framers
MVIP switching-compatible and ST-BUS-compliant devices including:
– MVIP framers
– H.100 framers
– SCSA framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS-compliant devices
•
McBSP clock rate = CLKG = CLKSRG/(1 + CLKGDIV) , where CLKSRG source could be LSPCLK, CLKX, or
CLKR. 1
1
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20-MHz maximum.
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Figure 9-9 shows the block diagram of the McBSP module with FIFO, interfaced to the F281x version of
Peripheral Frame 2.
Peripheral Write Bus
TX FIFO
Interrupt
TX FIFO _15
TX FIFO _15
MXINT
TX Interrupt Logic
To CPU
TX FIFO _1
TX FIFO _0
TX FIFO _1
TX FIFO _0
McBSP Transmit
Interrupt Select Logic
TX FIFO Registers
16
16
DXR2 Transmit Buffer
16
DXR1 Transmit Buffer
16
LSPCLK
McBSP Registers
and
Control Logic
FSX
CLKX
Compand Logic
XSR2
DX
XSR1
DR
RSR1
16
RSR2
16
CLKR
Expand Logic
FSR
RBR1 Register
16
RBR2 Register
16
McBSP
DRR2 Receive Buffer
16
DRR1 Receive Buffer
16
McBSP Receive
Interrupt Select Logic
RX FIFO _15
RX FIFO _15
RX FIFO
Interrupt
RX FIFO _1
RX FIFO _0
RX FIFO _1
RX FIFO _0
RX Interrupt Logic
MRINT
To CPU
RX FIFO Registers
Peripheral Read Bus
Figure 9-9. McBSP Module With FIFO
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Table 9-9 provides a summary of the McBSP registers.
Table 9-9. McBSP Registers
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT (1)
–
–
–
–
–
–
–
–
–
0x0000
0x0000
0x0000
McBSP Receive Buffer Register
McBSP Receive Shift Register
McBSP Transmit Shift Register
McBSP Data Receive Register 2
•
Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 1
•
Read Second if the word size is greater than 16 bits,
else read DRR1 only
McBSP Data Transmit Register 2
•
Write First if the word size is greater than 16 bits,
else ignore DXR2
W
W
McBSP Data Transmit Register 1
•
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
SPCR2
SPCR1
RCR2
04
05
06
07
08
09
0A
0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
MULTICHANNEL CONTROL REGISTERS
MCR2
MCR1
0C
0D
0E
0F
10
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
12
13
14
15
16
17
18
19
1A
1B
1C
1D
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
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Table 9-9. McBSP Registers (continued)
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
XCERH
DESCRIPTION
1E
R/W
0x0000
McBSP Transmit Channel Enable Register Partition H
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Table 9-9. McBSP Registers (continued)
ADDRESS
0x00 78xxh
TYPE
(R/W)
RESET VALUE
(HEX)
NAME
DESCRIPTION
FIFO MODE REGISTERS (applicable only in FIFO mode)
FIFO Data Registers (2)
McBSP Data Receive Register 2 – Top of receive FIFO
Read First FIFO pointers will not advance
DRR2
DRR1
DXR2
DXR1
00
01
02
03
R
R
0x0000
0x0000
0x0000
0x0000
•
McBSP Data Receive Register 1 – Top of receive FIFO
Read Second for FIFO pointers to advance
•
McBSP Data Transmit Register 2 – Top of transmit FIFO
Write First FIFO pointers will not advance
W
W
•
McBSP Data Transmit Register 1 – Top of transmit FIFO
Write Second for FIFO pointers to advance
•
FIFO Control Registers
MFFTX
MFFRX
MFFCT
MFFINT
MFFST
20
21
22
23
24
R/W
R/W
R/W
R/W
R/W
0xA000
0x201F
0x0000
0x0000
0x0000
McBSP Transmit FIFO Register
McBSP Receive FIFO Register
McBSP FIFO Control Register
McBSP FIFO Interrupt Register
McBSP FIFO Status Register
(1) DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
(2) FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
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9.2.6 Serial Communications Interface (SCI) Module
The F281x devices include two serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
NOTE: Both pins can be used as GPIO if not used for SCI.
•
Baud rate programmable to 64K different rates 2
LSPCLK
=
Baud rate
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
=
16
•
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
Max bit rate = 75 MHz/16 = 4.688 x 106 b/s
•
•
•
•
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE: All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros.
Writing to the upper byte has no effect.
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
2
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
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The SCI port operation is configured and controlled by the registers listed in Table 9-10 and Table 9-11.
Table 9-10. SCI-A Registers
NAME
SCICCRA
ADDRESS
0x00 7050
0x00 7051
0x00 7052
0x00 7053
0x00 7054
0x00 7055
0x00 7056
0x00 7057
0x00 7059
0x00 705A
0x00 705B
0x00 705C
0x00 705F
SIZE (x16)
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
SCI-A Communications Control Register
SCICTL1A
SCI-A Control Register 1
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(1)
SCIFFRXA(1)
SCIFFCTA(1)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) These registers are new registers for the FIFO mode.
Table 9-11. SCI-B Registers
SIZE (x16)
NAME(1)
SCICCRB
ADDRESS
0x00 7750
0x00 7751
0x00 7752
0x00 7753
0x00 7754
0x00 7755
0x00 7756
0x00 7757
0x00 7759
0x00 775A
0x00 775B
0x00 775C
0x00 775F
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
SCI-B Communications Control Register
SCI-B Control Register 1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Figure 9-10 shows the SCI module block diagram.
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SCICTL1.1
SCITXD
SCITXD
TXSHF
Register
Frame Format and Mode
Parity
Even/Odd Enable
TXENA
TX EMPTY
SCICTL2.6
8
SCICCR.6 SCICCR.5
TX INT ENA
TXRDY
Transmitter-Data
Buffer Register
SCICTL2.7
SCICTL2.0
8
TXWAKE
TXINT
TX FIFO _0
SCICTL1.3
TX Interrupt Logic
TX FIFO _1
- - - - -
To CPU
TX
FIFO
Interrupts
1
SCI TX Interrupt Select Logic
TX FIFO _15
WUT
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
AutoBaud Detect Logic
SCIRXD
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
RXRDY
RX/BK INT ENA
Receive-Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
- - - - -
RX
FIFO
Interrupts
RX FIFO _1
RX FIFO _0
RXINT
To CPU
RX Interrupt Logic
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 9-10. Serial Communications Interface (SCI) Module Block Diagram
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9.2.7 Serial Peripheral Interface (SPI) Module
The F281x devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be
shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSP controller and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
NOTE: All four pins can be used as GPIO, if the SPI module is not used.
Two operational modes: master and slave
Baud rate: 125 different programmable rates
•
•
LSPCLK
=
Baud rate
when SPIBRR ¹ 0
(SPIBRR + 1)
LSPCLK
4
when SPIBRR = 0,1, 2, 3
=
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such
that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.
Data word length: one to sixteen data bits
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
•
•
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros.
Writing to the upper byte has no effect.
•
•
•
Enhanced features:
•
•
16-level transmit/receive FIFO
Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 9-12.
Table 9-12. SPI Registers
SIZE (x16)
NAME(1)
SPICCR
ADDRESS
0x00 7040
0x00 7041
0x00 7042
0x00 7044
0x00 7046
0x00 7047
0x00 7048
0x00 7049
0x00 704A
0x00 704B
0x00 704C
0x00 704F
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
SPI Configuration Control Register
SPICTL
SPI Operation Control Register
SPI Status Register
SPISTS
SPIBRR
SPI Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI Receive Emulation Buffer Register
SPI Serial Input Buffer Register
SPI Serial Output Buffer Register
SPI Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI FIFO Transmit Register
SPI FIFO Receive Register
SPI FIFO Control Register
SPI Priority Control Register
(1) These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
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Figure 9-11 is a block diagram of the SPI in slave mode.
SPIFFENA
SPIFFTX.14
Overrun
INT ENA
Receiver
Overrun Flag
RX FIFO Registers
SPIRXBUF
SPISTS.7
RX FIFO _0
SPICTL.4
RX FIFO _1
- - - - -
RX
FIFO
Interrupt
RX FIFO _15
SPIINT/SPIRXINT
To CPU
RX Interrupt
Logic
16
SPIFFOVF
FLAG
SPIRXBUF Buffer Register
SPIFFRX.15
TX
FIFO
Interrupt
TX FIFO Registers
TX Interrupt
Logic
SPITXBUF
SPITXINT
TX FIFO _15
- - - - -
SPI
INT FLAG
SPI
INT ENA
TX FIFO _1
16
SPISTS.6
TX FIFO _0
SPICTL.0
16
SPITXBUF Buffer Register
16
M
S
M
S
SW1
SW2
SPIDAT Data Register
SPISIMO
M
S
M
S
SPIDAT.15 - 0
SPISOMI
Talk
SPICTL.1
SPISTE(A)
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 - 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
SPICCR.6
SPICTL.3
LSPCLK
SPICLK
SPIBRR.6 - 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 9-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)
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9.2.8 GPIO MUX
The GPIO Mux registers are used to select the operation of shared pins on the F281x devices. The pins can be
individually selected to operate as “Digital I/O” or connected to “Peripheral I/O” signals (via the GPxMUX
registers). If selected for “Digital I/O”mode, registers are provided to configure the pin direction (via the GPxDIR
registers) and to qualify the input signal to remove unwanted noise (via the GPxQUAL) registers). Table 9-13
lists the GPIO Mux Registers.
Table 9-13. GPIO Mux Registers
NAME(1) (2) (3)
GPAMUX
ADDRESS
0x00 70C0
0x00 70C1
0x00 70C2
0x00 70C3
0x00 70C4
0x00 70C5
0x00 70C6
0x00 70C7
0x00 70C8
0x00 70C9
0x00 70CA
0x00 70CB
0x00 70CC
0x00 70CD
0x00 70CE
0x00 70CF
0x00 70D0
0x00 70D1
0x00 70D2
0x00 70D3
0x00 70D4
0x00 70D5
0x00 70D6
0x00 70D7
0x00 70D8
0x00 70D9
0x00 70DA
0x00 70DB
0x00 70DC – 0x00 70DF
SIZE (x16)
DESCRIPTION
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
GPIO A Mux Control Register
GPADIR
GPIO A Direction Control Register
GPAQUAL
Reserved
GPBMUX
GPBDIR
GPIO A Input Qualification Control Register
GPIO B Mux Control Register
GPIO B Direction Control Register
GPIO B Input Qualification Control Register
GPBQUAL
Reserved
Reserved
Reserved
Reserved
Reserved
GPDMUX
GPDDIR
GPDQUAL
Reserved
GPEMUX
GPEDIR
GPIO D Mux Control Register
GPIO D Direction Control Register
GPIO D Input Qualification Control Register
GPIO E Mux Control Register
GPIO E Direction Control Register
GPIO E Input Qualification Control Register
GPEQUAL
Reserved
GPFMUX
GPFDIR
GPIO F Mux Control Register
GPIO F Direction Control Register
Reserved
Reserved
GPGMUX
GPGDIR
Reserved
Reserved
Reserved
GPIO G Mux Control Register
GPIO G Direction Control Register
(1) Reserved locations return undefined values and writes are ignored.
(2) Not all inputs support input signal qualification.
(3) These registers are EALLOW protected. This prevents spurious writes from overwriting the contents and corrupting the system.
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If configured for ”Digital I/O” mode, additional registers are provided for setting individual I/O signals (via the
GPxSET registers), for clearing individual I/O signals (via the GPxCLEAR registers), for toggling individual I/O
signals (via the GPxTOGGLE registers), or for reading/writing to the individual I/O signals (via the GPxDAT
registers). Table 9-14 lists the GPIO Data Registers. For more information, see the TMS320x281x DSP System
Control and Interrupts Reference Guide.
Table 9-14. GPIO Data Registers
NAME(1) (2)
ADDRESS
0x00 70E0
0x00 70E1
0x00 70E2
0x00 70E3
0x00 70E4
0x00 70E5
0x00 70E6
0x00 70E7
0x00 70E8
0x00 70E9
0x00 70EA
0x00 70EB
0x00 70EC
0x00 70ED
0x00 70EE
0x00 70EF
0x00 70F0
0x00 70F1
0x00 70F2
0x00 70F3
0x00 70F4
0x00 70F5
0x00 70F6
0x00 70F7
0x00 70F8
0x00 70F9
0x00 70FA
0x00 70FB
0x00 70FC – 0x00 70FF
SIZE (x16)
DESCRIPTION
GPADAT
GPASET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
GPIO A Data Register
GPIO A Set Register
GPACLEAR
GPATOGGLE
GPBDAT
GPIO A Clear Register
GPIO A Toggle Register
GPIO B Data Register
GPIO B Set Register
GPIO B Clear Register
GPIO B Toggle Register
GPBSET
GPBCLEAR
GPBTOGGLE
Reserved
Reserved
Reserved
Reserved
GPDDAT
GPIO D Data Register
GPIO D Set Register
GPIO D Clear Register
GPIO D Toggle Register
GPIO E Data Register
GPIO E Set Register
GPIO E Clear Register
GPIO E Toggle Register
GPIO F Data Register
GPIO F Set Register
GPIO F Clear Register
GPIO F Toggle Register
GPIO G Data Register
GPIO G Set Register
GPIO G Clear Register
GPIO G Toggle Register
GPDSET
GPDCLEAR
GPDTOGGLE
GPEDAT
GPESET
GPECLEAR
GPETOGGLE
GPFDAT
GPFSET
GPFCLEAR
GPFTOGGLE
GPGDAT
GPGSET
GPGCLEAR
GPGTOGGLE
Reserved
(1) Reserved locations will return undefined values and writes will be ignored.
(2) These registers are NOT EALLOW protected. The above registers will typically be accessed regularly by the user.
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Figure 9-12 shows how the various register bits select the various modes of operation for GPIO function.
GPxDAT/SET/CLEAR/TOGGLE
Register Bit(s)
Digital I/O
Peripheral I/O
High-
Impedance
Control
GPxQUAL
Register
GPxMUX GPxDIR
Register Bit Register Bit
0
1
0
1
MUX
MUX
SYSCLKOUT
Input Qualification
High-Impedance
Enable (1)
XRS
Internal (Pullup or Pulldown)
PIN
A. In the GPIO mode, when the GPIO pin is configured for output operation, reading the GPxDAT data register only gives the value written,
not the value at the pin. In the peripheral mode, the state of the pin can be read through the GPxDAT register, provided the
corresponding direction bit is zero (input mode).
B. Some selected input signals are qualified by the SYSCLKOUT. The GPxQUAL register specifies the qualification sampling period. The
sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0's or all 1's). This feature
removes unwanted spikes from the input signal.
Figure 9-12. GPIO/Peripheral Pin Multiplexing
Note
The input function of the GPIO pin and the input path to the peripheral are always enabled. It is the
output function of the GPIO pin that is multiplexed with the output path of the primary (peripheral)
function. Since the output buffer of a pin connects back to the input buffer, any GPIO signal present at
the pin will be propagated to the peripheral module as well. Therefore, when a pin is configured for
GPIO operation, the corresponding peripheral functionality (and interrupt-generating capability) must
be disabled. Otherwise, interrupts may be inadvertently triggered. This is especially critical when the
PDPINTA and PDPINTB pins are used as GPIO pins, since a value of zero for GPDDAT.0 or
GPDDAT.5 ( PDPINTx) will put PWM pins in a high-impedance state. The CxTRIP and TxCTRIP pins
will also put the corresponding PWM pins in high impedance, if they are driven low (as GPIO pins) and
bit EXTCONx.0 = 1.
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9.3 Memory Maps
Block
Start Address
On-Chip Memory
Data Space
Prog Space
External Memory XINTF
Data Space
Prog Space
0x00 0000
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
0x00 0800
0x00 0D00
Reserved
Peripheral Frame 0
PIE Vector - RAM
(256 x 16)
(Enabled if
Reserved
VMAP = 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
0x00 2000
0x00 4000
XINTF Zone 0 (8K x 16, XZCS0AND1)
Reserved
XINTF Zone 1 (8K x 16, XZCS0AND1) (Protected)
0x00 6000
0x00 7000
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
Reserved
0x00 8000
0x00 9000
0x00 A000
L0 SARAM (4K x 16, Secure Block)
L1 SARAM (4K x 16, Secure Block)
0x08 0000
0x10 0000
0x18 0000
XINTF Zone 2 (0.5M x 16, XZCS2)
Reserved
XINTF Zone 6 (0.5M x 16, XZCS6AND7)
0x3D 7800
0x3D 7C00
0x3D 8000
OTP (1K x 16, Secure Block)
Reserved (1K)
Reserved
Flash (128K x 16, Secure Block)
128-Bit Password
0x3F 7FF8
0x3F 8000
H0 SARAM (8K x 16)
0x3F A000
Reserved
0x3F C000
XINTF Zone 7 (16K x 16, XZCS6AND7)
(Enabled if MP/MC = 1)
0x3F F000
0x3F FFC0
Boot ROM (4K x 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
XINTF Vector - RAM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps - M0 vector, PIE vector, BROM vector, XINTF vector - should be enabled at a time.
A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Boot ROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/ MC, not in both.
D. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
E. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.
Figure 9-13. F2812 Memory Map
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Block
Start Address
On-Chip Memory
Data Space
Prog Space
0x00 0000
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Peripheral Frame 0
PIE Vector - RAM
(256 x 16)
(Enabled if
Reserved
VMAP = 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 9000
0x00 A000
L0 SARAM (4K x 16, Secure Block)
L1 SARAM (4K x 16, Secure Block)
Reserved
0x3D 7800
0x3D 7C00
0x3D 8000
OTP (1K x 16, Secure Block)
Reserved (1K)
Flash (128K x 16, Secure Block)
128-Bit Password
0x3F 7FF8
0x3F 8000
H0 SARAM (8K x 16)
0x3F A000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K x 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.
A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-14. F2811 Memory Map
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Block
Start Address
On-Chip Memory
Data Space
Prog Space
M0 Vector - RAM (32 x 32)
0x00 0000
(Enabled if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
0x00 0040
0x00 0400
0x00 0800
0x00 0D00
Peripheral Frame 0
PIE Vector - RAM
(256 x 16)
(Enabled if
Reserved
VMAP = 1, ENPIE = 1)
0x00 0E00
0x00 2000
Reserved
Reserved
0x00 6000
0x00 7000
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 9000
0x00 A000
L0 SARAM (4K x 16, Secure Block)
L1 SARAM (4K x 16, Secure Block)
Reserved
0x3D 7800
0x3D 7C00
0x3E 8000
OTP (1K x 16, Secure Block)
Reserved
Flash (64K x 16, Secure Block)
128-Bit Password
0x3F 7FF8
0x3F 8000
H0 SARAM (8K x 16)
0x3F A000
Reserved
0x3F F000
0x3F FFC0
Boot ROM (4K x 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
LEGEND:
Only one of these vector maps - M0 vector, PIE vector, BROM vector - should be enabled at a time.
A. Memory blocks are not to scale.
B. Reserved locations are reserved for future expansion. Application should not access these areas.
C. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only. User program
cannot access these memory maps in program space.
D. “Protected” means the order of Write followed by Read operations is preserved rather than the pipeline order.
E. Certain memory ranges are EALLOW protected against spurious writes after configuration.
Figure 9-15. F2810 Memory Map
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Table 9-15. Addresses of Flash Sectors in F2812 and F2811
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3D 8000
0x3D 9FFF
Sector J, 8K x 16
0x3D A000
0x3D BFFF
Sector I, 8K x 16
Sector H, 16K x 16
Sector G, 16K x 16
Sector F, 16K x 16
Sector E, 16K x 16
Sector D, 16K x 16
Sector C, 16K x 16
Sector B, 8K x 16
0x3D C000
0x3D FFFF
0x3E 0000
0x3E 3FFF
0x3E 4000
0x3E 7FFF
0x3E 8000
0x3E BFFF
0x3E C000
0x3E FFFF
0x3F 0000
0x3F 3FFF
0x3F 4000
0x3F 5FFF
Sector A, 8K x 16 Program to 0x0000 when using
the
Code Security Module Boot-to-Flash Entry Point
(program branch instruction here) Security
Password (128-Bit)
0x3F 6000 0x3F 7F80
0x3F 7FF5 0x3F 7FF6
0x3F 7FF7 0x3F 7FF8
0x3F 7FFF
(Do not program to all zeros)
Table 9-16. Addresses of Flash Sectors in F2810
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x3E 8000
0x3E BFFF
Sector E, 16K x 16
Sector D, 16K x 16
Sector C, 16K x 16
Sector B, 8K x 16
0x3E C000
0x3E FFFF
0x3F 0000
0x3F 3FFF
0x3F 4000
0x3F 5FFF
Sector A, 8K x 16 Program to 0x0000 when using
the
Code Security Module Boot-to-Flash Entry Point
(program branch instruction here) Security
Password (128-Bit)
0x3F 6000 0x3F 7F80
0x3F 7FF5 0x3F 7FF6
0x3F 7FF7 0x3F 7FF8
0x3F 7FFF
(Do not program to all zeros)
The “Low 64K” of the memory address range maps into the data space of the 240x. The “High 64K” of the
memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will execute
only from the “High 64K”memory area. Hence, the top 32K of Flash and H0 SARAM block can be used to run
24x/240x-compatible code (if MP/ MC mode is low) or, on the F2812, code can be executed from XINTF Zone 7
(if MP/ MC mode is high).
The XINTF consists of five independent zones. One zone has its own chip select and the remaining four zones
share two chip selects. Each zone can be programmed with its own timing (wait states) and to either sample or
ignore external ready signal. This makes interfacing to external peripherals easy and glueless.
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Note
The chip selects of XINTF Zone 0 and Zone 1 are merged into a single chip select ( XZCS0AND1);
and the chip selects of XINTF Zone 6 and Zone 7 are merged into a single chip select ( XZCS6AND7).
See Section 9.6, External Interface, XINTF (F2812 only), for details.
Peripheral Frame 1, Peripheral Frame 2, and XINTF Zone 1 are grouped together to enable these blocks to be
“write/read peripheral block protected”. The “protected” mode ensures that all accesses to these blocks happen
as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations,
will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The C28x CPU supports a block
protection mode where a region of memory can be protected to make sure that operations occur as written (the
penalty is extra cycles that are added to align the operations). This mode is programmable and, by default, it will
protect the selected zones.
On the F2812, at reset, XINTF Zone 7 is accessed if the XMP/ MC pin is pulled high. This signal selects
microprocessor or microcomputer mode of operation. In microprocessor mode, Zone 7 is mapped to high
memory such that the vector table is fetched externally. The Boot ROM is disabled in this mode. In
microcomputer mode, Zone 7 is disabled such that the vectors are fetched from Boot ROM. This allows the user
to either boot from on-chip memory or from off-chip memory. The state of the XMP/ MC signal on reset is stored
in an MP/ MC mode bit in the XINTCNF2 register. The user can change this mode in software and hence control
the mapping of Boot ROM and XINTF Zone 7. No other memory blocks are affected by XMP/ MC.
I/O space is not supported on the F2812 XINTF.
The wait states for the various spaces in the memory map area are listed in Table 9-17.
Table 9-17. Wait States
AREA
WAIT-STATES
0-wait
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
Fixed
Fixed
0-wait
0-wait (writes)
2-wait (reads)
Peripheral Frame 1
Fixed
0-wait (writes)
2-wait (reads)
Peripheral Frame 2
L0 and L1 SARAMs
OTP
Fixed
Fixed
0-wait
Programmable, Programmed via the Flash registers. 1-wait-state operation is possible at a
1-wait minimum reduced CPU frequency. See Section 9.1.6, Flash, for more information.
Programmed via the Flash registers. 0-wait-state operation is possible at
Programmable,
Flash
reduced CPU frequency. The CSM password locations are hardwired for
0-wait minimum
16 wait states. See Section 9.1.6, Flash, for more information.
H0 SARAM
Boot-ROM
0-wait
1-wait
Fixed
Fixed
Programmed via the XINTF registers.
Cycles can be extended by external memory or peripheral.
0-wait operation is not possible.
Programmable,
1-wait minimum
XINTF
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9.4 Register Map
The F281x devices contain three peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
Peripheral Frame 1:
Peripheral Frame 2:
These are peripherals that are mapped directly to the CPU memory bus.
See Table 9-18.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 9-19.
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 9-20.
Table 9-18. Peripheral Frame 0 Registers
NAME(1)
ADDRESS RANGE
0x00 0880 – 0x00 09FF
0x00 0A00 – 0x00 0A7F
SIZE (x16)
ACCESS TYPE(2)
EALLOW protected
Device Emulation Registers
Reserved
384
128
EALLOW protected
CSM Protected
FLASH Registers(3)
0x00 0A80 – 0x00 0ADF
96
Code Security Module Registers
Reserved
0x00 0AE0 – 0x00 0AEF
0x00 0AF0 – 0x00 0B1F
0x00 0B20 – 0x00 0B3F
0x00 0B40 – 0x00 0BFF
0x00 0C00 – 0x00 0C3F
0x00 0C40 – 0x00 0CDF
0x00 0CE0 – 0x00 0CFF
0x00 0D00 – 0x00 0DFF
0x00 0E00 – 0x00 0FFF
16
48
EALLOW protected
XINTF Registers
Reserved
32
Not EALLOW protected
Not EALLOW protected
192
64
CPU-TIMER0/1/2 Registers
Reserved
160
32
PIE Registers
Not EALLOW protected
EALLOW protected
PIE Vector Table
Reserved
256
512
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the user executes the EALLOW instruction. The EDIS
instruction disables writes. This prevents stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 9-19. Peripheral Frame 1 Registers
NAME(1)
eCAN Registers
ADDRESS RANGE
SIZE (x16)
ACCESS TYPE
256
(128 x 32)
Some eCAN control registers (and selected bits in
other eCAN control registers) are EALLOW-protected.
0x00 6000 – 0x00 60FF
256
(128 x 32)
eCAN Mailbox RAM
Reserved
0x00 6100 – 0x00 61FF
0x00 6200 – 0x00 6FFF
Not EALLOW-protected
3584
(1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries.
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Table 9-20. Peripheral Frame 2 Registers
NAME(1)
ADDRESS RANGE
0x00 7000 – 0x00 700F
0x00 7010 – 0x00 702F
0x00 7030 – 0x00 703F
0x00 7040 – 0x00 704F
0x00 7050 – 0x00 705F
0x00 7060 – 0x00 706F
0x00 7070 – 0x00 707F
0x00 7080 – 0x00 70BF
0x00 70C0 – 0x00 70DF
0x00 70E0 – 0x00 70FF
0x00 7100 – 0x00 711F
0x00 7120 – 0x00 73FF
0x00 7400 – 0x00 743F
0x00 7440 – 0x00 74FF
0x00 7500 – 0x00 753F
0x00 7540 – 0x00 774F
0x00 7750 – 0x00 775F
0x00 7760 – 0x00 77FF
0x00 7800 – 0x00 783F
0x00 7840 – 0x00 7FFF
SIZE (x16)
ACCESS TYPE
Reserved
16
System Control Registers
Reserved
32
EALLOW Protected
16
SPI-A Registers
SCI-A Registers
Reserved
16
Not EALLOW Protected
Not EALLOW Protected
16
16
External Interrupt Registers
Reserved
16
Not EALLOW Protected
64
GPIO Mux Registers
GPIO Data Registers
ADC Registers
Reserved
32
EALLOW Protected
32
Not EALLOW Protected
Not EALLOW Protected
32
736
64
EV-A Registers
Reserved
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
Not EALLOW Protected
192
64
EV-B Registers
Reserved
528
16
SCI-B Registers
Reserved
160
64
McBSP Registers
Reserved
1984
(1) Peripheral Frame 2 only allows 16-bit accesses. All 32-bit accesses are ignored (invalid data may be returned or written).
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9.5 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 9-21.
Table 9-21. Device Emulation Registers
SIZE
(x16)
NAME
ADDRESS RANGE
DESCRIPTION
DEVICECNF
PARTID
0x00 0880 – 0x00 0881
0x00 0882
2
1
Device Configuration Register
Part ID Register
0x0001 or 0x0002 – F281x
0x0001 – Silicon Revision A
0x0002 – Silicon Revision B
0x0003 – Silicon Revisions C, D
0x0004 – Reserved
REVID
0x00 0883
1
Revision ID Register
0x0005 – Silicon Revision E
0x0006 – Silicon Revision F
0x0007 – Silicon Revision G
PROTSTART
PROTRANGE
Reserved
0x00 0884
0x00 0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
0x00 0886 – 0x00 09FF
378
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9.6 External Interface, XINTF (F2812 Only)
This section gives a top-level view of the external interface (XINTF) that is implemented on the F2812 device.
The external interface is a non-multiplexed asynchronous bus, similar to the C240x external interface. The
external interface on the F2812 is mapped into five fixed zones shown in Figure 9-16.
Figure 9-16 shows the F2812 XINTF signals.
Data Space
Prog Space
0x00 0000
XD[15:0]
XA[18:0]
0x00 2000
0x00 4000
0x00 6000
0x08 0000
XINTF Zone 0
(8K x 16)
XZCS0
XZCS1
XZCS0AND1
XINTF Zone 1
(8K x 16)
XINTF Zone 2
(512K x 16)
XZCS2
0x10 0000
XINTF Zone 6
(512K x 16)
XZCS6
XZCS7
XZCS6AND7
0x18 0000
0x3F C000
XINTF Zone 7
(16K x 16)
(mapped here if MP/MC = 1)
0x40 0000
XWE
XRD
XR/W
XREADY
XMP/MC
XHOLD
XHOLDA
XCLKOUT(E)
A. The mapping of XINTF Zone 7 is dependent on the XMP/ MC device input signal and the MP/ MC mode bit (bit 8 of XINTCNF2 register).
Zones 0, 1, 2, and 6 are always enabled.
B. Each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects ( XZCS0AND1,
XZCS2, XZCS6AND7), which toggle when an access to a particular zone is performed. These features enable glueless connection to
many external memories and peripherals.
C. The chip selects for Zone 0 and Zone 1 are ANDed internally together to form one chip select ( XZCS0AND1). Any external memory that
is connected to XZCS0AND1 is dually mapped to both Zone 0 and Zone 1.
D. The chip selects for Zone 6 and Zone 7 are ANDed internally together to form one chip select ( XZCS6AND7). Any external memory that
is connected to XZCS6AND7 is dually mapped to both Zone 6 and Zone 7. This means that if Zone 7 is disabled (via the MP/ MC mode),
then any external memory is still accessible via Zone 6 address space.
E. XCLKOUT is also pinned out on the F2810 and F2811 devices.
Figure 9-16. External Interface Block Diagram
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The operation and timing of the external interface, can be controlled by the registers listed in Table 9-22.
Table 9-22. XINTF Configuration and Control Register Mappings
SIZE
(x16)
NAME
XTIMING0
ADDRESS
DESCRIPTION
0x00 0B20
0x00 0B22
0x00 0B24
0x00 0B2C
0x00 0B2E
0x00 0B34
0x00 0B38
0x00 0B3A
2
2
2
2
2
2
1
1
XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register.
XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register.
XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register.
XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register.
XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register.
XINTF Configuration Register can access as two 16-bit registers or one 32-bit register.
XINTF Bank Control Register
XTIMING1
XTIMING2
XTIMING6
XTIMING7
XINTCNF2
XBANK
XREVISION
XINTF Revision Register
9.6.1 Timing Registers
XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times
to strobe signals for contention avoidance and maximizing bus efficiency. The XINTF timing parameters can be
configured individually for each zone based on the requirements of the memory or peripheral accessed by that
particular zone. This allows the programmer to maximize the efficiency of the bus on a per-zone basis. All XINTF
timing values are with respect to XTIMCLK, which is equal to or one-half of the SYSCLKOUT rate, as shown in
Figure 8-26.
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x DSP
External Interface (XINTF) Reference Guide.
9.6.2 XREVISION Register
The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the F2812, this register will be configured as described in Table 9-23.
Table 9-23. XREVISION Register Bit Definitions
BIT(S)
NAME
TYPE
RESET
DESCRIPTION
Current XINTF Revision. For internal use/reference. Test purposes
only. Subject to change.
15–0
REVISION
R
0x0004
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9.7 Interrupts
Figure 9-17 shows how the various interrupt sources are multiplexed within the F281x devices.
Peripherals
(SPI, SCI, McBSP, CAN, EV, ADC)
(41 Interrupts)
WDINT
Watchdog
WAKEINT
LPMINT
Low-Power Modes
XINT1
Interrupt Control
INT1
to
INT12
PIE
XINT1CR[15:0]
XINT1CTR[15:0]
XINT2
Interrupt Control
XINT2CR[15:0]
XINT2CTR[15:0]
C28x CPU
TINT0
TIMER 0
GPIO
MUX
TINT2
TINT1
TIMER 2
(Reserved for DSP/BIOS)
INT14
INT13
TIMER 1
select
enable
NMI
XNMI_XINT13
Interrupt Control
XNMICR[15:0]
XNMICTR[15:0]
A. Out of a possible 96 interrupts, 45 are currently used by peripherals.
Figure 9-17. Interrupt Sources
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the F281x, 45 of these are used by peripherals as shown in Table
9-24.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector.
The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when
the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from
INT1.1, TRAP #2 fetches the vector from INT2.1 and so forth.
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IFR[12:1]
IER[12:1]
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable/Flag)
(Enable)
(Flag)
PIEIERx[8:1]
PIEIFRx[8:1]
Figure 9-18. Multiplexing of Interrupts Using the PIE Block
Table 9-24. PIE Peripheral Interrupts
PIE INTERRUPTS
CPU
INTERRUPTS(1)
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT
(ADC)
PDPINTB
(EV-B)
PDPINTA
(EV-A)
INT1
XINT2
XINT1
Reserved
T1OFINT
(EV-A)
T1UFINT
(EV-A)
T1CINT
(EV-A)
T1PINT
(EV-A)
CMP3INT
(EV-A)
CMP2INT
(EV-A)
CMP1INT
(EV-A)
INT2
INT3
INT4
INT5
INT6
Reserved
Reserved
Reserved
Reserved
Reserved
CAPINT3
(EV-A)
CAPINT2
(EV-A)
CAPINT1
(EV-A)
T2OFINT
(EV-A)
T2UFINT
(EV-A)
T2CINT
(EV-A)
T2PINT
(EV-A)
T3OFINT
(EV-B)
T3UFINT
(EV-B)
T3CINT
(EV-B)
T3PINT
(EV-B)
CMP6INT
(EV-B)
CMP5INT
(EV-B)
CMP4INT
(EV-B)
CAPINT6
(EV-B)
CAPINT5
(EV-B)
CAPINT4
(EV-B)
T4OFINT
(EV-B)
T4UFINT
(EV-B)
T4CINT
(EV-B)
T4PINT
(EV-B)
MXINT
(McBSP)
MRINT
(McBSP)
SPITXINTA
(SPI)
SPIRXINTA
(SPI)
Reserved
Reserved
Reserved
INT7
INT8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ECAN1INT
(CAN)
ECAN0INT
(CAN)
SCITXINTB SCIRXINTB SCITXINTA
SCIRXINTA
(SCI-A)
INT9
Reserved
Reserved
(SCI-B)
Reserved
Reserved
Reserved
(SCI-B)
Reserved
Reserved
Reserved
(SCI-A)
Reserved
Reserved
Reserved
INT10
INT11
INT12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(1) Out of the 96 possible interrupts, 45 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR.
To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
a. No peripheral within the group is asserting interrupts.
b. No peripheral interrupts are assigned to the group (example PIE group 12).
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Table 9-25. PIE Configuration and Control Registers
NAME(1)
PIECTRL
ADDRESS
SIZE (x16)
DESCRIPTION
0x0000 0CE0
1
PIE, Control Register
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
0x0000 0CE1
0x0000 0CE2
0x0000 0CE3
0x0000 0CE4
0x0000 0CE5
0x0000 0CE6
0x0000 0CE7
0x0000 0CE8
0x0000 0CE9
0x0000 0CEA
0x0000 0CEB
0x0000 0CEC
0x0000 0CED
0x0000 0CEE
0x0000 0CEF
0x0000 0CF0
0x0000 0CF1
0x0000 0CF2
0x0000 0CF3
0x0000 0CF4
0x0000 0CF5
0x0000 0CF6
0x0000 0CF7
0x0000 0CF8
0x0000 0CF9
0x0000 0CFA – 0x0000 0CFF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected.
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9.7.1 External Interrupts
Table 9-26. External Interrupts Registers
NAME
XINT1CR
ADDRESS
SIZE (x16)
DESCRIPTION
0x00 7070
0x00 7071
1
1
5
1
1
1
5
1
XINT1 control register
XINT2 control register
XINT2CR
Reserved
0x00 7072 – 0x00 7076
0x00 7077
XNMICR
XNMI control register
XINT1CTR
XINT2CTR
Reserved
0x00 7078
XINT1 counter register
XINT2 counter register
0x00 7079
0x00 707A – 0x00 707E
0x00 707F
XNMICTR
XNMI counter register
Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more
information, see the TMS320x281x DSP System Control and Interrupts Reference Guide.
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9.8 System Control
This section describes the F281x oscillator, PLL and clocking mechanisms, the watchdog function and the low-
power modes. Figure 9-19 shows the various clock and reset domains in the F281x devices that will be
discussed.
Reset
XRS
Watchdog
Block
SYSCLKOUT
Peripheral Reset
CLKIN(A)
X1/XCLKIN
X2
PLL
OSC
C28x CPU
Power
Modes
Control
XF_XPLLDIS
Clock Enables
System
Control
Registers
Peripheral
Registers
I/O
I/O
I/O
eCAN
LSPCLK
Low-Speed Prescaler
Peripheral
Registers
Low-Speed Peripherals
SCI-A/B, SPI, McBSP
GPIO
MUX
GPIOs
HSPCLK
High-Speed Prescaler
Peripheral
Registers
High-Speed Peripherals
EV-A/B
HSPCLK
ADC
Registers
12-Bit ADC
16 ADC Inputs
A. CLKIN is the clock input to the CPU. SYSCLKOUT is the output clock of the CPU. They are of the same frequency.
Figure 9-19. Clock and Reset Domains
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 9-27.
Table 9-27. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME(1)
ADDRESS
0x00 7010 – 0x00 7017
0x00 7018
SIZE (x16)
DESCRIPTION
Reserved
Reserved
Reserved
8
1
1
0x00 7019
High-Speed Peripheral Clock Prescaler Register for
HSPCLK clock
HISPCP
LOSPCP
0x00 701A
0x00 701B
1
1
Low-Speed Peripheral Clock Prescaler Register for
LSPCLK clock
PCLKCR
Reserved
LPMCR0
LPMCR1
Reserved
PLLCR
0x00 701C
0x00 701D
1
1
1
1
1
1
1
1
1
1
3
1
6
Peripheral Clock Control Register
0x00 701E
Low-Power Mode Control Register 0
Low-Power Mode Control Register 1
0x00 701F
0x00 7020
0x00 7021
PLL Control Register(2)
SCSR
0x00 7022
System Control and Status Register
Watchdog Counter Register
WDCNTR
Reserved
WDKEY
Reserved
WDCR
0x00 7023
0x00 7024
0x00 7025
Watchdog Reset Key Register
Watchdog Control Register
0x00 7026 – 0x00 7028
0x00 7029
Reserved
0x00 702A – 0x00 702F
(1) All of the above registers can only be accessed by executing the EALLOW instruction.
(2) The PLL control register (PLLCR) is reset to a known state by the XRS signal only. Emulation reset (through Code Composer Studio)
will not reset PLLCR.
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TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1
TMS320F2812, TMS320F2812-Q1
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9.9 OSC and PLL Block
Figure 9-20 shows the OSC and PLL block on F281x.
XPLLDIS
XF_XPLLDIS
Latch
XRS
OSCCLK (PLL Disabled)
XCLKIN
X1/XCLKIN
0
1
CLKIN
SYSCLKOUT
CPU
On-Chip
Oscillator
(OSC)
PLL
Bypass
/2
4-Bit PLL Select
X2
PLL
4-Bit PLL Select
PLL Block
Figure 9-20. OSC and PLL Block
The on-chip oscillator circuit enables a crystal to be attached to the F281x devices using the X1/XCLKIN and X2
pins. If a crystal is not used, then an external oscillator can be directly connected to the X1/XCLKIN pin and the
X2 pin is left unconnected. The logic-high level in this case should not exceed VDD. The PLLCR bits [3:0] set the
clocking ratio.
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Table 9-28. PLLCR Register Bit Definitions
XRS
BIT(S)
NAME
TYPE
DESCRIPTION
RESET(1)
15:4
Reserved
R = 0
0:0
SYSCLKOUT = (XCLKIN * n)/2, where n is the PLL multiplication
factor.
Bit Value
n
SYSCLKOUT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PLL Bypassed XCLKIN/2
1
XCLKIN/2
2
XCLKIN
3
XCLKIN * 1.5
XCLKIN * 2
XCLKIN * 2.5
XCLKIN * 3
XCLKIN * 3.5
XCLKIN * 4
XCLKIN * 4.5
XCLKIN * 5
Reserved
4
5
3:0
DIV
R/W
0,0,0,0
6
7
8
9
10
11
12
13
14
15
Reserved
Reserved
Reserved
Reserved
(1) The PLLCR register is reset to a known state by the XRS reset line. If a reset is issued by the debugger, the PLL clocking ratio is
not changed.
9.9.1 Loss of Input Clock
In PLL enabled mode, if the input clock XCLKIN or the oscillator clock is removed or absent, the PLL will still
issue a “limp-mode” clock. The limp-mode clock will continue to clock the CPU and peripherals at a typical
frequency of 1–4 MHz. The PLLCR register should have been written to with a non-zero value for this feature to
work.
Normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset or
WDINT interrupt. However, when the external input clock fails, the watchdog counter will stop decrementing (that
is, the watchdog counter does not change with the limp-mode clock). This condition could be used by the
application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.
Note
Applications in which the correct CPU operating frequency is absolutely critical must implement a
mechanism by which the DSP will be held in reset, should the input clocks ever fail. For example, an
R-C circuit may be used to trigger the XRS pin of the DSP, should the capacitor ever get fully charged.
An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully
charged. Such a circuit would also help in detecting failure of the VDD3VFL rail.
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9.10 PLL-Based Clock Module
The F281x has an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for
the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control to select different CPU
clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled
(if need be) after the PLL module has stabilized, which takes 131072 XCLKIN cycles.
The PLL-based clock module provides two modes of operation:
•
Crystal operation: This mode allows the use of an external crystal/resonator to provide the time base to the
device.
•
External clock source operation: This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1/XCLKIN pin.
X1/XCLKIN
X2
X1/XCLKIN
X2
(A)
(A)
CL1
CL2
External Clock Signal
)
NC
(Toggling 0-VDD
Crystal
(a)
(b)
A. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip. The
resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding
the proper tank component values that will ensure start-up and stability over the entire operating range.
Figure 9-21. Recommended Crystal/Clock Connection
Table 9-29. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the
X1/XCLKIN pin.
PLL Disabled
XCLKIN
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
bypassed. However, the /2 module in the PLL block divides the clock input at the X1/
XCLKIN pin by two before feeding it to the CPU.
PLL Bypassed
PLL Enabled
XCLKIN/2
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL block now divides the output of the PLL by two before feeding it to the CPU.
(XCLKIN * n) / 2
9.11 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
•
•
•
•
•
Fundamental mode, parallel resonant
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 25 to 40 Ω
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9.12 Watchdog Block
The watchdog block on the F281x is identical to the one used on the 240x devices. The watchdog module
generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has
reached its maximum value. To prevent this, the user disables the counter or the software must periodically write
a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 9-22
shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
WDCLK
Watchdog
Prescaler
8-Bit
Watchdog
Counter
CLR
/512
Clear Counter
Internal
Pullup
WDKEY[7:0]
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Bad Key
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
WDCR (WDCHK[2:0])
SCSR (WDENINT)
WDRST(A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
1
0
1
Figure 9-22. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off the PLL clock or the oscillator clock. The WDINT signal is
fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 9.13, Low-Power
Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE
mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence, so is the
WATCHDOG.
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9.13 Low-Power Modes Block
The low-power modes on F281x are similar to the 240x devices. Table 9-30 summarizes the various modes.
Table 9-30. Low-Power Modes
MODE
LPM[1:0]
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
Normal
X,X
on
on
on
–
XRS,
WDINT,
IDLE
0,0
on
on
on(2)
Any Enabled Interrupt,
XNMI,
Debugger(3)
XRS,
WDINT,
XINT1,
XNMI,
on
T1/2/3/4CTRIP,
C1/2/3/4/5/6TRIP,
SCIRXDA,
SCIRXDB,
CANRX,
STANDBY
0,1
1,X
off
off
off
off
(watchdog still running)
Debugger(3)
off
XRS,
XNMI,
HALT
(oscillator and PLL turned off,
watchdog not functional)
Debugger(3)
(1) The Exit column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals, will
exit the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the
IDLE mode will not be exited and the device will go back into the indicated low-power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the core (SYSCLKOUT) is
still functional; while on the 24x/240x, the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the core clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE Mode
This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The
LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY Mode
All other signals (including XNMI) will wake the device from STANDBY mode if selected by the
LPMCR1 register. The user will need to select which signal(s) will wake the device. The selected
signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is
specified in the LPMCR0 register.
HALT Mode
Only the XRS and XNMI external signals can wake the device from HALT mode. The XNMI input to
the core has an enable/disable bit. Hence, it is safe to use the XNMI signal for this function.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them when the IDLE instruction was executed.
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10 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 TI Reference Design
The TI Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all reference designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at Select TI reference designs.
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TMS320F2812, TMS320F2812-Q1
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11 Device and Documentation Support
11.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail
on each of these steps, see the following:
•
C2000 real-time control MCUs – Tools & software
11.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSP devices and support tools. Each TMS320 DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS320F2810). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
TMX
TMP
Experimental device that is not necessarily representative of the final device’s electrical specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, PBK) and temperature range (for example, A). Figure 11-1 provides a legend for reading the
complete device name for any TMS320F281x family member.
For device part numbers and further ordering information, see the Package Option Addendum of this document,
the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F281x DSPs Silicon
Errata.
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Figure 11-1. TMS320F281x Device Nomenclature
11.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software, visit
the Tools & software page for each device.
Development Tools
TMS320F2812 eZdsp Start Kit (DSK)
The F2812 eZdsp™ is a standalone module that lets evaluators examine certain characteristics of the F2812
digital signal processor (DSP) to determine if this DSP meets their application requirements. This module has a
single chip parallel port to JTAG scan controller. Therefore the module can be operated without additional
development tools such as an emulator. Furthermore, the module is an excellent platform to develop,
demonstrate, and run software for the F2812 processor.
Uniflash Standalone Flash Tool
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs.
Software Tools
controlSUITE™ Software Suite: Software and Development Tools for C2000™ Microcontrollers
controlSUITE™ for C2000™ microcontrollers is a cohesive set of software infrastructure, tools, and
documentation designed to minimize system development time. From device-specific drivers and support
software to complete examples in sophisticated system applications, controlSUITE provides the needed
resources at every stage of development and evaluation.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
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Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
11.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F281x DSPs Silicon Errata describes the advisories and usage notes for different versions of silicon.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
Peripheral Guides
C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the 28x
digital signal processors (DSPs).
TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide describes the ADC module. The
module is a 12-bit pipelined ADC. The analog circuits of this converter, referred to as the core in this document,
include the front-end analog multiplexers (MUXs), sample-and-hold (S/H) circuits, the conversion core, voltage
regulators, and other analog supporting circuits. Digital circuits, referred to as the wrapper in this document,
include programmable conversion sequencer, result registers, interface to analog circuits, interface to device
peripheral bus, and interface to other on-chip modules.
TMS320x281x DSP Boot ROM Reference Guide describes the purpose and features of the bootloader (factory-
programmed boot-loading software). It also describes other contents of the device on-chip boot ROM and
identifies where all of the information is located within that memory.
TMS320x281x DSP Event Manager (EV) Reference Guide describes the EV modules that provide a broad range
of functions and features that are particularly useful in motion control and motor control applications. The EV
modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder
pulse (QEP) circuits.
TMS320x281x DSP External Interface (XINTF) Reference Guide describes the external interface (XINTF) of the
281x digital signal processors (DSPs).
TMS320x281x DSP Multichannel Buffered Serial Port (McBSP) Reference Guide describes the McBSP available
on the 281x devices. The McBSPs allow direct interface between a DSP and other devices in a system.
TMS320x281x DSP System Control and Interrupts Reference Guide describes the various interrupts and system
control features of the 281x digital signal processors (DSPs).
TMS320x281x Enhanced Controller Area Network (eCAN) Reference Guide describes the eCAN that uses
established protocol to communicate serially with other controllers in electrically noisy environments. With 32
fully configurable mailboxes and time-stamping feature, the eCAN module provides a versatile and robust serial
communication interface. The eCAN module implemented in the C28x DSP is compatible with the ISO11898-1
(CAN 2.0B) standard (active).
TMS320x281x Serial Communications Interface (SCI) Reference Guide describes the SCI that is a two-wire
asynchronous serial port, commonly known as a UART. The SCI modules support digital communications
between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
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TMS320x281x Serial Peripheral Interface Reference Guide describes the SPI—a high-speed synchronous serial
input/output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into
and out of the device at a programmed bit-transfer rate. The SPI is used for communications between the DSP
controller and external peripherals or another controller.
Tools Guides
TMS320C28x Assembly Language Tools v18.12.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v18.12.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) Reference Guide describes development
using DSP/BIOS.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
Programming Examples for the TMS320x28xx eCAN Application Report contains several programming
examples to illustrate how the eCAN module is set up for different modes of operation. The objective is to help
you come up to speed quickly in programming the eCAN. All programs have been extensively commented to aid
easy understanding.
F2810, F2811, and F2812 ADC Calibration Application Report describes a method for improving the absolute
accuracy of the 12-bit analog-to-digital converter (ADC) found on the F2810/F2811/F2812 devices. Due to
inherent gain and offset errors, the absolute accuracy of the ADC is impacted. The methods described in this
application note can improve the absolute accuracy of the ADC to achieve levels better than 0.5%. This
application note is accompanied by an example program (ADCcalibration, spra989.zip) that executes from RAM
on the F2812 eZdsp.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Calculating FIT for a Mission Profile explains how to use TI's reliability de-rating tools to calculate a component-
level FIT under power-on conditions for a system mission profile.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders for
serial programming a device.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
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TMS320F2812, TMS320F2812-Q1
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11.6 Trademarks
Code Composer Studio™, DSP/BIOS™, MicroStar BGA™, and are trademarks of TI.
C2000™, Piccolo™, TMS320C2000™, TMS320™, controlSUITE™, TI E2E™ are trademarks of Texas Instruments.
eZdsp™ is a trademark of Spectrum Digital Incorporated.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
To learn more about TI packaging, visit the Packaging information website.
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Product Folder Links: TMS320F2810 TMS320F2810-Q1 TMS320F2811 TMS320F2811-Q1 TMS320F2812
TMS320F2812-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
ZHH
PBK
PBK
PBK
PBK
PBK
PBK
PBK
GBB
GBB
GBB
GHH
GHH
GHH
GHH
PGF
PGF
Qty
(1)
(2)
(3)
(4/5)
(6)
DFDF2812ZHHAR
TMS320F2810PBKA
TMS320F2810PBKQ
TMS320F2810PBKQR
TMS320F2810PBKS
TMS320F2811PBKA
TMS320F2811PBKQ
TMS320F2811PBKS
TMS320F2812GBBA
TMS320F2812GBBAR
TMS320F2812GBBS
TMS320F2812GHHA
TMS320F2812GHHAR
TMS320F2812GHHQ
TMS320F2812GHHS
TMS320F2812PGFA
TMS320F2812PGFAG4
LIFEBUY
BGA
MICROSTAR
179
128
128
128
128
128
128
128
179
179
179
179
179
179
179
176
176
1000 RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 125
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 125
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 85
320F2812ZHHA
TMS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
LIFEBUY
LIFEBUY
LIFEBUY
ACTIVE
ACTIVE
LQFP
LQFP
90
90
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Call TI
320F2810PBKA
TMS
320F2810PBKQ
TMS
LQFP
1000 RoHS & Green
320F2810PBKQ
TMS
LQFP
90
90
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
320F2810PBKS
TMS
LQFP
320F2811PBKA
TMS
LQFP
90
320F2811PBKQ
TMS
LQFP
90
320F2811PBKS
TMS
NFBGA
NFBGA
NFBGA
160
1000
160
160
1000
160
160
40
Non-RoHS
& Green
TMS
320F2812GBBA
Non-RoHS
& Green
Call TI
Call TI
TMS
320F2812GBBA
Non-RoHS
& Green
Call TI
Call TI
TMS
320F2812GBBS
BGA
MICROSTAR
Non-RoHS
& Green
SNPB
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
320F2812GHHA
TMS
BGA
MICROSTAR
Non-RoHS
& Green
SNPB
320F2812GHHA
TMS
BGA
MICROSTAR
Non-RoHS
& Green
SNPB
320F2812GHHQ
TMS
BGA
MICROSTAR
Non-RoHS
& Green
SNPB
320F2812GHHS
TMS
LQFP
RoHS & Green
NIPDAU
NIPDAU
320F2812PGFA
TMS
LQFP
40
RoHS & Green
320F2812PGFA
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS
TMS320F2812PGFQ
TMS320F2812PGFS
TMS320F2812ZAYA
TMS320F2812ZAYAR
TMS320F2812ZAYS
TMS320F2812ZHHA
TMS320F2812ZHHAR
TMS320F2812ZHHS
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
LIFEBUY
LIFEBUY
LQFP
LQFP
PGF
PGF
ZAY
ZAY
ZAY
ZHH
ZHH
ZHH
176
176
179
179
179
179
179
179
40
40
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 125
-40 to 85
-40 to 85
-40 to 125
320F2812PGFQ
TMS
320F2812PGFS
TMS
NFBGA
NFBGA
NFBGA
160
TMS
320F2812ZAYA
1000 RoHS & Green
TMS
320F2812ZAYA
160
160
RoHS & Green
RoHS & Green
TMS
320F2812ZAYS
BGA
MICROSTAR
320F2812ZHHA
TMS
BGA
MICROSTAR
1000 RoHS & Green
160 RoHS & Green
320F2812ZHHA
TMS
BGA
MICROSTAR
320F2812ZHHS
TMS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
4-Feb-2021
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320F2810, TMS320F2810-Q1, TMS320F2811, TMS320F2811-Q1, TMS320F2812, TMS320F2812-Q1 :
Catalog: TMS320F2810, TMS320F2811, SM320F2812, TMS320F2812
•
Automotive: TMS320F2810-Q1, TMS320F2811-Q1, TMS320F2812-Q1
•
Enhanced Product: SM320F2812-EP
•
Military: SMJ320F2812, SMJ320F2812
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMS320F2812GBBAR
TMS320F2812ZAYAR
NFBGA
NFBGA
GBB
ZAY
179
179
1000
1000
330.0
330.0
24.4
24.4
12.35 12.35
12.35 12.35
2.3
2.3
16.0
16.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMS320F2812GBBAR
TMS320F2812ZAYAR
NFBGA
NFBGA
GBB
ZAY
179
179
1000
1000
336.6
336.6
336.6
336.6
41.3
41.3
Pack Materials-Page 2
PACKAGE OUTLINE
PGF0176A
LQFP - 1.6 mm max height
SCALE 0.550
PLASTIC QUAD FLATPACK
24.2
23.8
NOTE 3
B
PIN 1 ID
133
176
1
132
24.2
23.8
26.2
TYP
25.8
NOTE 3
44
89
45
88
0.27
0.17
A
176X
172X 0.5
0.08
C A B
4X 21.5
C
SEATING PLANE
1.6 MAX
SEE DETAIL A
(0.13)
TYP
0.25
(1.4)
GAGE PLANE
0.15
0.05
0.08 C
0 -7
0.75
0.45
A
12
DETAIL A
TYPICAL
4215177/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PGF0176A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
176
133
176X (1.5)
1
132
176X (0.3)
172X (0.5)
SYMM
(25.4)
(R0.05) TYP
89
44
SEE DETAILS
45
88
(25.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215177/A 05/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PGF0176A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
176
133
176X (1.5)
176X (0.3)
1
132
172X (0.5)
SYMM
(25.4)
(R0.05) TYP
44
89
45
88
(25.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4215177/A 05/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
GBB0179A
A
12.1
11.9
B
BALL A1 CORNER
12.1
11.9
1.4 MAX
C
SEATING PLANE
0.12 C
0.45
0.35
BALL TYP
(0.8) TYP
(0.8) TYP
10.4 TYP
P
N
M
L
K
J
SYMM
H
G
F
10.4
TYP
0.55
179X Ø
0.45
E
D
C
0.15
0.05
C A B
C
B
A
0.8 TYP
0.8 TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SYMM
4225682/A 02/2020
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
GBB0179A
(0.8) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
(0.8) TYP
G
H
J
SYMM
K
L
179X (Ø 0.4)
M
N
P
SYMM
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
0.05 MAX
ALL AROUND
ALL AROUND
EXPOSED
METAL
METAL UNDER
SOLDER MASK
(Ø 0.40)
SOLDER MASK
OPENING
(Ø 0.40)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225682/A 02/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
GBB0179A
(0.8) TYP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
A
B
C
D
E
F
(0.8) TYP
G
H
J
SYMM
K
L
179X (Ø 0.4)
M
N
P
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 8X
4225682/A 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ZHH0179A
UBGA - 1.4 mm max height
SCALE 1.200
BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
0.9
C
SEATING PLANE
0.1 C
BALL TYP
1.4 MAX
0.45
0.35
10.4 TYP
SYMM
P
N
M
L
K
10.4
TYP
J
H
G
F
SYMM
E
D
0.8
C
TYP
B
A
9
10
1
2
3
4
5
6
7
8
11
12
13 14
0.55
0.45
179X
0.15
0.08
C A B
C
0.8 TYP
4220265/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This is a Pb-free solder ball design.
www.ti.com
EXAMPLE BOARD LAYOUT
ZHH0179A
UBGA - 1.4 mm max height
BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
1
3
4
5
6
7
8
2
9
10 11 12 13 14
A
(0.8) TYP
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.4)
METAL
(
0.4)
EXPOSED
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4220265/A 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
EXAMPLE STENCIL DESIGN
ZHH0179A
UBGA - 1.4 mm max height
BALL GRID ARRAY
(0.8) TYP
179X 0.4
(0.8) TYP
2
3
4
5
6
7
8
9
10
11
12
13
14
1
A
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 10X
4220265/A 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ZAY0179A
NFBGA - 1.4 mm max height
S
C
A
L
E
1
.
2
0
0
PLASTIC BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
1.4 MAX
C
SEATING PLANE
0.45
0.35
⌓ 0.12 C
10.4 TYP
(0.8)
(0.8)
SYMM
℄
P
N
M
L
K
J
SYMM
℄
H
G
10.4 TYP
F
E
D
C
0.55
179X
0.45
B
A
⌀0.15Ⓜ C A B
⌖
⌀0.08Ⓜ C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.8 TYP
0.8 TYP
4225014/C 07/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZAY0179A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.4)
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225014/C 07/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZAY0179A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 10X
4225014/C 07/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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costs, losses, and liabilities arising out of your use of these resources.
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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