TMS320F28235PTP [TI]
TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs);
| 型号： | TMS320F28235PTP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs) |
| 文件： | 总208页 (文件大小：6019K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1,TMS320F28232,TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)
(6 for eCAPs and 2 for eQEPs)
– Up to 9 16-bit timers
(6 for ePWMs and 3 XINTCTRs)
Three 32-bit CPU timers
Serial port peripherals
– Up to 2 CAN modules
– Up to 3 SCI (UART) modules
– Up to 2 McBSP modules (configurable as SPI)
– One SPI module
– One Inter-Integrated Circuit (I2C) bus
12-bit ADC, 16 channels
1 Features
•
High-performance static CMOS technology
– Up to 150 MHz (6.67-ns cycle time)
– 1.9-V/1.8-V core, 3.3-V I/O design
High-performance 32-bit CPU (TMS320C28x)
– IEEE 754 single-precision Floating-Point Unit
(FPU) (F2833x only)
•
•
•
– 16 × 16 and 32 × 32 MAC operations
– 16 × 16 dual MAC
– Harvard bus architecture
•
– Fast interrupt response and processing
– Unified memory programming model
– Code-efficient (in C/C++ and Assembly)
Six-channel DMA controller (for ADC, McBSP,
ePWM, XINTF, and SARAM)
16-bit or 32-bit External Interface (XINTF)
– More than 2M × 16 address reach
On-chip memory
– F28335, F28333, F28235:
256K × 16 flash, 34K × 16 SARAM
– F28334, F28234:
128K × 16 flash, 34K × 16 SARAM
– F28332, F28232:
64K × 16 flash, 26K × 16 SARAM
– 1K × 16 OTP ROM
– 80-ns conversion rate
– 2 × 8 channel input multiplexer
– Two sample-and-hold
– Single/simultaneous conversions
– Internal or external reference
Up to 88 individually programmable, multiplexed
GPIO pins with input filtering
•
•
•
•
•
JTAG boundary scan support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
Advanced emulation features
•
•
– Analysis and breakpoint functions
– Real-time debug using hardware
Development support includes
– ANSI C/C++ compiler/assembler/linker
– Code Composer Studio™ IDE
– DSP/BIOS™ and SYS/BIOS
– Digital motor control and digital power software
libraries
Low-power modes and power savings
– IDLE, STANDBY, HALT modes supported
– Disable individual peripheral clocks
Endianness: Little endian
•
•
Boot ROM (8K × 16)
– With software boot modes (through SCI, SPI,
CAN, I2C, McBSP, XINTF, and parallel I/O)
– Standard math tables
Clock and system control
– On-chip oscillator
•
– Watchdog timer module
•
•
•
GPIO0 to GPIO63 pins can be connected to one of
the eight external core interrupts
Peripheral Interrupt Expansion (PIE) block that
supports all 58 peripheral interrupts
128-bit security key/lock
– Protects flash/OTP/RAM blocks
– Prevents firmware reverse-engineering
Enhanced control peripherals
– Up to 18 PWM outputs
– Up to 6 HRPWM outputs with 150-ps MEP
resolution
– Up to 6 event capture inputs
– Up to 2 Quadrature Encoder interfaces
– Up to 8 32-bit timers
•
•
Package options:
– Lead-free, green packaging
– 176-ball plastic Ball Grid Array (BGA) (ZJZ)
– 179-ball MicroStar BGA™ (ZHH)
– 176-pin Low-Profile Quad Flatpack (LQFP)
(PGF)
– 176-pin Thermally Enhanced Low-Profile Quad
Flatpack (HLQFP) (PTP)
Temperature options:
•
•
– A: –40°C to 85°C (PGF, ZHH, ZJZ)
– S: –40°C to 125°C (PTP, ZJZ)
– Q: –40°C to 125°C (PTP, ZJZ)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
(AEC Q100 qualification for automotive
applications)
•
•
•
•
•
•
•
•
Factory automation
Grid infrastructure
Industrial transport
Medical, healthcare and fitness
Motor drives
Power delivery
Telecom infrastructure
Test and measurement
2 Applications
•
•
•
•
Advanced Driver Assistance Systems (ADAS)
Building automation
Electronic point of sale
Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)
powertrain
3 Description
C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-loop
performance in real-time control applications such as industrial motor drives; solar inverters and digital power;
electrical vehicles and transportation; motor control; and sensing and signal processing. The C2000 line includes
the Delfino™ Premium Performance family and the Piccolo™ Entry Performance family.
TMS320C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-
loop performance in real-time control applications. The C2000™ microcontrollers line includes the Delfino™
Premium Performance microcontroller family and the Piccolo™ Entry Performance microcontroller family.
The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234,
and TMS320F28232 devices, members of the TMS320C28x/ Delfino™ DSC/MCU generation, are highly
integrated, high-performance solutions for demanding control applications.
Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234,
and F28232, respectively. F2833x Device Comparison and F2823x Device Comparison provide a summary of
features for each device.
To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.
Device Information (1)
PART NUMBER
TMS320F28335ZHH
PACKAGE
BGA MicroStar (179)
BGA MicroStar (179)
BGA MicroStar (179)
BGA MicroStar (179)
BGA MicroStar (179)
BGA MicroStar (179)
BGA (176)
BODY SIZE
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
15.0 mm × 15.0 mm
15.0 mm × 15.0 mm
15.0 mm × 15.0 mm
15.0 mm × 15.0 mm
15.0 mm × 15.0 mm
15.0 mm × 15.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
TMS320F28334ZHH
TMS320F28332ZHH
TMS320F28235ZHH
TMS320F28234ZHH
TMS320F28232ZHH
TMS320F28335ZJZ
TMS320F28334ZJZ
TMS320F28332ZJZ
TMS320F28235ZJZ
TMS320F28234ZJZ
TMS320F28232ZJZ
TMS320F28335PGF
TMS320F28334PGF
TMS320F28333PGF
TMS320F28332PGF
TMS320F28235PGF
TMS320F28234PGF
TMS320F28232PGF
TMS320F28335PTP
TMS320F28334PTP
BGA (176)
BGA (176)
BGA (176)
BGA (176)
BGA (176)
LQFP (176)
LQFP (176)
LQFP (176)
LQFP (176)
LQFP (176)
LQFP (176)
LQFP (176)
HLQFP (176)
HLQFP (176)
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Device Information (1) (continued)
PART NUMBER
TMS320F28332PTP
PACKAGE
HLQFP (176)
HLQFP (176)
HLQFP (176)
HLQFP (176)
BODY SIZE
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
24.0 mm × 24.0 mm
TMS320F28235PTP
TMS320F28234PTP
TMS320F28232PTP
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
3.1 Functional Block Diagram
M0 SARAM 1Kx16
(0-Wait)
L0 SARAM 4K x 16
(0-Wait, Dual Map)
OTP 1K x 16
M1 SARAM 1Kx16
(0-Wait)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
Flash
256K x 16
8 Sectors
L2 SARAM 4K x 16
(0-Wait, Dual Map)
Code
Security
Module
L3 SARAM 4K x 16
(0-Wait, Dual Map)
TEST2
TEST1
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
Pump
PSWD
L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
Boot ROM
8K x 16
Flash
Wrapper
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
XD31:0
FPU
TCK
TDI
XHOLDA
XHOLD
XREADY
XR/W
TMS
32-bit CPU
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
TDO
GPIO
MUX
88 GPIOs
TRST
EMU0
EMU1
XZCS0
XZCS7
XZCS6
XWE0
XCLKIN
X1
CPU Timer 0
XA0/XWE1
XA19:1
OSC,
DMA
6 Ch
PLL,
LPM,
WD
CPU Timer 1
CPU Timer 2
X2
XRS
XCLKOUT
XRD
PIE
(Interrupts)
88 GPIOs
A7:0
8 External Interrupts
GPIO
MUX
XINTF
Memory Bus
12-Bit
ADC
2-S/H
B7:0
DMA Bus
REFIN
32-bit peripheral bus
(DMA accessible)
32-bit peripheral bus
16-bit peripheral bus
FIFO
(16 Levels)
FIFO
(16 Levels)
FIFO
(16 Levels)
ePWM-1/../6
CAN-A/B
(32-mbox)
eQEP-1/2
McBSP-A/B
eCAP-1/../6
SCI-A/B/C
SPI-A
I2C
HRPWM-1/../6
GPIO MUX
88 GPIOs
Secure zone
Figure 3-1. Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
3.1 Functional Block Diagram...........................................4
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 8
6 Terminal Configuration and Functions..........................9
6.1 Pin Diagrams.............................................................. 9
6.2 Signal Descriptions................................................... 19
7 Specifications................................................................ 30
7.1 Absolute Maximum Ratings...................................... 30
7.2 ESD Ratings – Automotive....................................... 31
7.3 ESD Ratings – Commercial...................................... 31
7.4 Recommended Operating Conditions.......................32
7.5 Power Consumption Summary................................. 33
7.6 Electrical Characteristics...........................................37
7.7 Thermal Resistance Characteristics......................... 38
7.8 Thermal Design Considerations................................41
7.9 Timing and Switching Characteristics....................... 42
7.10 On-Chip Analog-to-Digital Converter...................... 96
7.11 Migrating Between F2833x Devices and
8 Detailed Description....................................................104
8.1 Brief Descriptions....................................................104
8.2 Peripherals..............................................................112
8.3 Memory Maps......................................................... 156
8.4 Register Map...........................................................163
8.5 Interrupts.................................................................166
8.6 System Control....................................................... 171
8.7 Low-Power Modes Block........................................ 177
9 Applications, Implementation, and Layout............... 178
9.1 TI Design or Reference Design...............................178
10 Device and Documentation Support........................179
10.1 Getting Started......................................................179
10.2 Device and Development Support Tool
Nomenclature............................................................179
10.3 Tools and Software............................................... 181
10.4 Documentation Support........................................ 182
10.5 Support Resources............................................... 185
10.6 Trademarks...........................................................185
10.7 Electrostatic Discharge Caution............................185
10.8 Glossary................................................................185
11 Mechanical, Packaging, and Orderable
Information.................................................................. 186
11.1 Packaging Information.......................................... 186
F2823x Devices.........................................................103
4 Revision History
Changes from April 22, 2019 to February 1, 2021 (from Revision O (April 2019) to Revision P
(February 2021))
Page
•
•
•
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1, Table 5-2: Added Q1 Part Numbers...................................................................................................6
Figure 10-1: Added GPN information............................................................................................................. 179
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
5 Device Comparison
Table 5-1. F2833x Device Comparison
F28335
F28335-Q1
(150 MHz)
F28334
(150 MHz)
F28333
(100 MHz)
F28332
(100 MHz)
FEATURE
Instruction cycle
TYPE(1)
–
–
–
6.67 ns
Yes
6.67 ns
Yes
10 ns
Yes
10 ns
Yes
Floating-point unit
3.3-V on-chip flash (16-bit word)
256K
128K
256K
64K
Single-access RAM (SARAM)
(16-bit word)
–
–
–
34K
1K
34K
1K
34K
1K
26K
1K
One-time programmable (OTP) ROM
(16-bit word)
Code security for on-chip flash/
SARAM/OTP blocks
Yes
Yes
Yes
Yes
Boot ROM (8K × 16)
–
1
0
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
16/32-bit External Interface (XINTF)
6-channel Direct Memory Access (DMA)
PWM channels
Yes
Yes
Yes
Yes
ePWM1/2/3/4/5/6
ePWM1/2/3/4/5/6
ePWM1/2/3/4/5/6
ePWM1/2/3/4/5/6
ePWM1A/2A/3A/4A/ ePWM1A/2A/3A/4A/ ePWM1A/2A/3A/4A/
HRPWM channels
0
0
ePWM1A/2A/3A/4A
eCAP1/2/3/4
eQEP1/2
5A/6A
5A/6A
5A/6A
32-bit capture inputs or auxiliary PWM
outputs
eCAP1/2/3/4/5/6
eCAP1/2/3/4
eCAP1/2/3/4/5/6
32-bit QEP channels (four inputs/
channel)
0
–
eQEP1/2
eQEP1/2
eQEP1/2
Watchdog timer
No. of channels
Yes
16
Yes
16
Yes
16
Yes
16
12-bit ADC
MSPS
2
12.5
80 ns
3
12.5
80 ns
3
12.5
80 ns
3
12.5
80 ns
3
Conversion time
32-bit CPU timers
–
1
Multichannel Buffered Serial Port
(McBSP)/SPI
2 (A/B)
2 (A/B)
2 (A/B)
1 (A)
Serial Peripheral Interface (SPI)
0
0
1
1
1
1
Serial Communications Interface (SCI)
3 (A/B/C)
3 (A/B/C)
3 (A/B/C)
2 (A/B)
Enhanced Controller Area Network
(eCAN)
0
2 (A/B)
2 (A/B)
2 (A/B)
2 (A/B)
Inter-Integrated Circuit (I2C)
General-purpose I/O pins (shared)
External interrupts
0
–
–
–
–
–
–
–
–
1
1
1
88
8
1
88
88
88
8
Yes
8
Yes
8
Yes
176-Pin PGF
Yes
–
176-Pin PTP
Packaging
Yes
Yes
Yes
179-Ball ZHH
Yes
Yes
–
Yes
176-Ball ZJZ
Yes
Yes
–
Yes
A: –40°C to 85°C
PGF, ZHH, ZJZ
PTP, ZJZ
PGF, ZHH, ZJZ
PTP, ZJZ
PGF
–
PGF, ZHH, ZJZ
PTP, ZJZ
S: –40°C to 125°C
Temperature
Q: –40°C to 125°C
options
(AEC Q100
–
PTP, ZJZ
PTP, ZJZ
–
PTP, ZJZ
Qualification)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 5-2. F2823x Device Comparison
F28235
F28235-Q1
(150 MHz)
F28234
F28234-Q1
(150 MHz)
F28232
F28232-Q1
(100 MHz)
FEATURE
TYPE(1)
Instruction cycle
–
–
–
6.67 ns
No
6.67 ns
No
10 ns
No
Floating-point unit
3.3-V on-chip flash (16-bit word)
256K
128K
64K
Single-access RAM (SARAM)
(16-bit word)
–
–
–
34K
1K
34K
1K
26K
1K
One-time programmable (OTP) ROM
(16-bit word)
Code security for on-chip flash/
SARAM/OTP blocks
Yes
Yes
Yes
Boot ROM (8K × 16)
–
1
0
0
0
Yes
Yes
Yes
Yes
Yes
Yes
16/32-bit External Interface (XINTF)
6-channel Direct Memory Access (DMA)
PWM channels
Yes
Yes
Yes
ePWM1/2/3/4/5/6
ePWM1/2/3/4/5/6
ePWM1/2/3/4/5/6
ePWM1A/2A/3A/4A
HRPWM channels
ePWM1A/2A/3A/4A/5A/6A ePWM1A/2A/3A/4A/5A/6A
32-bit capture inputs or auxiliary PWM
outputs
0
eCAP1/2/3/4/5/6
eCAP1/2/3/4
eCAP1/2/3/4
32-bit QEP channels (four inputs/channel)
Watchdog timer
0
–
eQEP1/2
Yes
eQEP1/2
Yes
eQEP1/2
Yes
No. of channels
16
16
16
12-bit ADC
MSPS
2
12.5
80 ns
3
12.5
80 ns
3
12.5
80 ns
3
Conversion time
32-bit CPU timers
–
1
Multichannel Buffered Serial Port
(McBSP)/SPI
2 (A/B)
2 (A/B)
1 (A)
Serial Peripheral Interface (SPI)
Serial Communications Interface (SCI)
Enhanced Controller Area Network (eCAN)
Inter-Integrated Circuit (I2C)
General-purpose I/O pins (shared)
External interrupts
0
0
0
0
–
–
–
–
–
–
–
–
1
1
1
3 (A/B/C)
3 (A/B/C)
2 (A/B)
2 (A/B)
2 (A/B)
2 (A/B)
1
1
1
88
88
88
8
Yes
8
Yes
8
Yes
176-Pin PGF
176-Pin PTP
Packaging
Yes
Yes
Yes
179-Ball ZHH
Yes
Yes
Yes
176-Ball ZJZ
Yes
Yes
Yes
A: –40°C to 85°C
S: –40°C to 125°C
PGF, ZHH, ZJZ
PTP, ZJZ
PGF, ZHH, ZJZ
PTP, ZJZ
PGF, ZHH, ZJZ
PTP, ZJZ
Temperature options
Q: –40°C to 125°C
(AEC Q100
–
PTP, ZJZ
PTP, ZJZ
PTP, ZJZ
Qualification)
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 real-time control peripherals reference guide and in the peripheral reference guides.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
5.1 Related Products
For information about other devices in the Delfino family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000™ MCU that is offered with a floating-point unit
(FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo™
families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The
F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA
package.
TMS320C2834x Delfino™ Microcontrollers
The C2834x series removes the on-chip Flash memory and integrated ADC to enable the fastest available clock
speeds of up to 300 MHz. It is available in a 179-ball BGA or 256-ball BGA package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™
TMS320F2807x series.
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
6 Terminal Configuration and Functions
6.1 Pin Diagrams
The 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 6-1. The 179-ball
ZHH ball grid array (BGA) terminal assignments are shown in Figure 6-2 through Figure 6-5. The 176-ball ZJZ
plastic BGA terminal assignments are shown in Figure 6-6 through Figure 6-9. Table 6-1 describes the
function(s) of each pin.
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
GPIO76/XD3
GPIO77/XD2
GPIO78/XD1
GPIO79/XD0
88 GPIO48/ECAP5/XD31
87 TCK
86 EMU1
85
84
83
EMU0
V
DD3VFL
GPIO38/XWE0
XCLKOUT
V
SS
V
82 TEST2
81 TEST1
80
79 TMS
78
DD
CIRXDA/XZCS6
V
SS
XRS
GPIO28/SCIRXDA/XZCS6
GPIO34/ECAP1/XREADY
V
TRST
DDIO
V
77 TDO
76 TDI
SS
GPIO36/SCIRXDA/XZCS0
V
75 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO
74 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO
73 GPIO27/ECAP4/EQEP2S/MFSXB
72 GPIO26/ECAP3/EQEP2I/MCLKXB
DD
V
SS
GPIO35/SCITXDA/XR/W
XRD
GPIO37/ECAP2/XZCS7
GPIO40/XA0/XWE1
V
71
70
DDIO
V
SS
GPIO41/XA1
GPIO42/XA2
69 GPIO25/ECAP2/EQEP2B/MDRB
68 GPIO24/ECAP1/EQEP2A/MDXB
67 GPIO23/EQEP1I/MFSXA/SCIRXDB
66 GPIO22/EQEP1S/MCLKXA/SCITXDB
65 GPIO21/EQEP1B/MDRA/CANRXB
64 GPIO20/EQEP1A/MDXA/CANTXB
63 GPIO19/SPISTEA/SCIRXDB/CANTXA
62 GPIO18/SPICLKA/SCITXDB/CANRXA
V
V
DD
V
SS
GPIO43/XA3
GPIO44/XA4
GPIO45/XA5
V
DDIO
V
61
60
59
58
SS
GPIO46/XA6
GPIO47/XA7
DD
V
V
V
SS
DD2A18
SS2AGND
GPIO80/XA8 163
164
165
166
167
168
169
170
171
GPIO81/XA9
GPIO82/XA10
57 ADCRESEXT
56 ADCREFP
55 ADCREFM
54 ADCREFIN
53 ADCINB7
V
SS
V
DD
GPIO83/XA11
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
GPIO84/XA12
V
52
51
50
49
48
47
46
45
DDIO
V
SS
GPIO85/XA13 172
GPIO86/XA14
GPIO87/XA15
173
174
175
176
GPIO39/XA16
GPIO31/CANTXA/XA17
V
DDAIO
Figure 6-1. F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Note
The thermal pad should be soldered to the ground (GND) plane of the PCB because this will provide
the best thermal conduction path. For this device, the thermal pad is not electrically shorted to the
internal die VSS; therefore, the thermal pad does not provide an electrical connection to the PCB
ground. To make optimum use of the thermal efficiencies designed into the PowerPAD™ package, the
PCB must be designed with this technology in mind. A thermal land is required on the surface of the
PCB directly underneath the thermal pad. The thermal land should be soldered to the thermal pad; the
thermal land should be as large as needed to dissipate the required heat. An array of thermal vias
should be used to connect the thermal pad to the internal GND plane of the board. See PowerPAD™
thermally enhanced package for more details on using the PowerPAD package.
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
1
2
3
4
5
6
7
GPIO21/
EQEP1B/
MDRA/
VSSAIO
VSS
P
N
ADCINB0
ADCINB2
ADCINB6
ADCREFP
P
N
CANRXB
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
VDDAIO
VDD
ADCINA1
ADCINB1
ADCINB5
ADCREFM
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
VDD2A18
M
ADCINA2
ADCINA5
VSS1AGND
ADCLO
ADCINA4
VDDA2
ADCINA0
ADCINA3
VSSA2
ADCINB4
ADCINB3
ADCRESEXT
ADCREFIN
ADCINB7
M
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO20/
EQEP1A/
MDXA/
L
L
CANTXB
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
VSS2AGND
K
ADCINA7
K
6
7
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDD
VSS
VDD1A18
J
ADCINA6
GPIO16/
J
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
GPIO13/
TZ2/
GPIO15/
TZ4/XHOLDA/ SPISIMOA/
H
H
VDD
CANRXB/
MDRB
SCIRXDB/
MFSXB
CANTXB/
TZ5
1
2
3
4
5
Figure 6-2. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper-Left Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8
9
10
11
12
13
14
GPIO33/
SCLA/
GPIO48/
ECAP5/
XD31
GPIO50/
EQEP1A/
XD29
VSS
P
N
TMS
TEST2
EMU1
P
N
EPWMSYNCO/
ADCSOCBO
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO32/
SDAA/
GPIO49/
ECAP6/
XD30
VSS
VSS
VDDIO
TCK
EPWMSYNCI/
ADCSOCAO
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO51/
EQEP1B/
XD28
GPIO52/
EQEP1S/
XD27
VDD3VFL
VSS
M
TDI
M
TRST
GPIO27/
ECAP4/
EQEP2S/
MFSXB
GPIO53/
EQEP1I/
XD26
GPIO54/
SPISIMOA/
XD25
GPIO55/
SPISOMIA/
XD24
VDDIO
L
EMU0
L
XRS
TEST1
VSS
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO56/
SPICLKA/
XD23
GPIO58/
MCLKRA/
XD21
GPIO57/
SPISTEA/
XD22
VDD
K
TDO
K
8
9
VSS
J
X2
X1
XCLKIN
J
GPIO59/
MFSRA/
XD20
VSS
VDDIO
VDD
VSS
H
H
10
11
12
13
14
Figure 6-3. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Upper-Right Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
1
2
3
4
5
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
GPIO12/
TZ1/
GPIO10/
EPWM6A/
CANRXB/
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
VSS
G
G
CANTXB/
MDXB
ADCSOCBO
GPIO8/
EPWM5A/
CANTXB/
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
VDD
VSS
VDDIO
F
F
ADCSOCAO
6
7
GPIO6/
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
EPWM4A/
GPIO4/
GPIO84/
XA12
GPIO81/
XA9
VDDIO
E
D
E
EPWMSYNCI/
EPWMSYNCO
EPWM3A
MCLKRB
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO2/
GPIO86/
XA14
GPIO83/
XA11
GPIO45/
XA5
VSS
VSS
D
EPWM2A
GPIO29/
SCITXDA/
XA19
GPIO0/
GPIO85/
XA13
GPIO82/
XA10
GPIO80/
XA8
VSS
VSS
C
B
C
B
EPWM1A
GPIO30/
CANRXA/
XA18
GPIO39/
XA16
GPIO46/
XA6
GPIO43/
XA3
VDD
VSS
VDD
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
GPIO47/
XA7
GPIO44/
XA4
VDDIO
VSS
A
A
1
2
3
4
5
6
7
Figure 6-4. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower-Left Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
10
11
12
13
14
GPIO63/
SCITXDC/
XD16
GPIO61/
MFSRB/
XD18
GPIO62/
SCIRXDC
XD17
GPIO60/
MCLKRB/
XD19
GPIO64/
XD15
G
G
GPIO69/
XD10
GPIO66/
XD13
GPIO65/
XD14
VSS
VDD
F
F
8
9
GPIO28/
SCIRXDA/
XZCS6
GPIO68/
XD11
GPIO67/
XD12
VSS
VDD
VDDIO
VSS
E
D
C
B
A
E
D
C
B
A
GPIO40/
XA0/
GPIO37/
ECAP2/
XZCS7
GPIO34/
ECAP1/
XREADY
GPIO38/
XWE0
GPIO70/
XD9
VDD
VSS
XWE1
GPIO36/
SCIRXDA/
XZCS0
GPIO73/
XD6
GPIO74/
XD5
GPIO71/
XD8
VDD
VSS
XCLKOUT
GPIO42/
XA2
GPIO78/
XD1
GPIO76/
XD3
GPIO72/
XD7
VDD
VDDIO
XRD
GPIO35/
GPIO41/
XA1
GPIO79/
XD0
GPIO77/
XD2
GPIO75/
XD4
VSS
VSS
SCITXDA/
XR/W
8
9
10
11
12
13
14
Figure 6-5. F2833x, F2823x 179-Ball ZHH MicroStar BGA (Lower-Right Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
1
2
3
4
5
6
7
P
N
ADCINB0
ADCREFM
ADCREFP ADCRESEXT ADCREFIN
VSSA2
VSS2AGND
ADCLO
ADCINB1
ADCINB3
ADCINB5
ADCINB7
EMU0
VSSAIO
M
ADCINA2
ADCINA5
ADCINA1
ADCINA4
ADCINA0
ADCINA3
VDD1A18
ADCINB2
VSS1AGND
VDDA2
ADCINB4
ADCINB6
TEST1
TEST2
VDDAIO
VDD2A18
L
ADCINA7
GPIO15/
ADCINA6
GPIO16/
K
GPIO17/
SPISOMIA/
CANRXB/
TZ6
TZ4/XHOLDA/ SPISIMOA/
VDD
VSS
VSS
J
SCIRXDB/
MFSXB
CANTXB/
TZ5
GPIO12/
TZ1/
GPIO13/
TZ2/
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VDD
VSS
VSS
H
CANTXB/
MDXB
CANRXB/
MDRB
Figure 6-6. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper-Left Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8
9
10
11
12
13
14
GPIO20/
EQEP1A/
MDXA/
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
GPIO33/
SCLA/
VSS
VSS
EMU1
P
N
M
L
EPWMSYNCO/
ADCSOCBO
CANTXB
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO21/
EQEP1B/
MDRA/
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
VDDIO
TDI
TDO
XRS
CANRXB
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO25/
ECAP2/
GPIO32/
SDAA/
TMS
TCK
EQEP2B/ EPWMSYNCI/
MDRB
ADSOCAO
GPIO50/
EQEP1A/
XD29
GPIO49/
ECAP6/
XD30
GPIO48/
ECAP5/
XD31
VDD
VDD3VFL
VDDIO
TRST
GPIO53
EQEP1I/
XD26
GPIO52/
EQEP1S/
XD27
GPIO51/
EQEP1B/
XD28
VDD
K
GPIO56/
SPICLKA/
XD23
GPIO55/
SPISOMIA/
XD24
GPIO54/
SPISIMOA/
XD25
VSS
VSS
VDD
J
GPIO59/
MFSRA/
XD20
GPIO58/
MCLKRA/
XD21
GPIO57/
SPISTEA/
XD22
VSS
VSS
X2
H
Figure 6-7. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper-Right Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO10/
EPWM6A/
CANRXB/
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
VDDIO
VSS
VSS
G
ADCSOCBO
GPIO6/
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO8/
EPWM5A/
CANTXB/
EPWM4A/
VDD
VSS
VSS
F
EPWMSYNCI/
EPWMSYNCO
ADCSOCAO
GPIO3/
EPWM2B/
ECAP5/
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO4/
VDDIO
E
D
C
B
A
EPWM3A
MCLKRB
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO0/
GPIO2/
GPIO47/
XA7
VDD
VDD
VDDIO
EPWM1A
EPWM2A
GPIO29/
SCITXDA/
XA19
GPIO30/
CANRXA/
XA18
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO46/
XA6
GPIO43/
XA3
GPIO31/
CANTXA/
XA17
GPIO87/
XA15
GPIO84/
XA12
GPIO81/
XA9
GPIO45/
XA5
GPIO42/
XA2
VDDIO
GPIO86/
XA14
GPIO83/
XA11
GPIO80/
XA8
GPIO44/
XA4
GPIO41/
XA1
VSS
VSS
1
2
3
4
5
6
7
Figure 6-8. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower-Left Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
GPIO60/
MCLKRB/
XD19
VSS
VSS
VDDIO
XCLKIN
X1
G
GPIO63/
SCITXDC/
XD16
GPIO62/
SCIRXDC/
XD17
GPIO61/
MFSRB/
XD18
VSS
VSS
VDD
F
GPIO66/
XD13
GPIO65/
XD14
GPIO64/
XD15
VDD
E
D
C
B
A
GPIO28/
SCIRXDA/
XZCS6
GPIO69/
XD10
GPIO68/
XD11
GPIO67/
XD12
VDD
VDD
VDDIO
GPIO36/
SCIRXDA/
XZCS0
GPIO40/
GPIO38/
XWE0
GPIO78/
XD1
GPIO75/
XD4
GPIO71/
XD8
GPIO70/
XD9
XA0/XWE1
GPIO37/
ECAP2/
XZCS7
GPIO35/
SCITXDA/
XR/W
GPIO79/
XD0
GPIO77/
XD2
GPIO74/
XD5
GPIO72
XD7
VSS
GPIO34/
ECAP1/
XREADY
GPIO76/
XD3
GPIO73/
XD6
VDDIO
VSS
XCLKOUT
XRD
8
9
10
11
12
13
14
Figure 6-9. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower-Right Quadrant) (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
6.2 Signal Descriptions
Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available in all
devices. See Table 5-1 and Table 5-2 for details. Inputs are not 5-V tolerant. All pins capable of producing an
XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for
XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All
GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin
basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 pins are not enabled at reset.
The pullups on GPIO12–GPIO87 are enabled upon reset.
Table 6-1. Signal Descriptions
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
NAME
ZHH
ZJZ
BALL # BALL #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
normal device operation. An external pulldown resistor is required on this pin. The value of
this resistor should be based on drive strength of the debugger pods applicable to the
design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-
specific, TI recommends validating each target board for proper operation of the debugger
and the application. (I, ↓)
TRST
78
M10
L11
TCK
TMS
87
79
N12
P10
M14
M12
JTAG test clock with internal pullup (I, ↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into
the TAP controller on the rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK. (I, ↑)
TDI
76
77
M9
K9
N12
N13
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
TDO
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
EMU0
85
L11
N7
NOTE: An external pullup resistor is required on this pin. The value of this resistor should
be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to
4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
EMU1
86
P12
P8
NOTE: An external pullup resistor is required on this pin. The value of this resistor should
be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to
4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application.
FLASH
VDD3VFL
TEST1
TEST2
84
81
82
M11
K10
P11
L9
M7
L7
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
NAME
ZHH
ZJZ
BALL # BALL #
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half
the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16
(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =
SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF]
to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state
during a reset. (O/Z, 8 mA drive).
XCLKOUT
XCLKIN
138
105
C11
J14
A10
G13
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V
oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a
ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
1.9-V/1.8-V core digital power supply. A 1.9-V/1.8-V external oscillator may be connected
to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V
external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)
X1
X2
104
102
J13
J11
G14
H14
Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected
across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the
address contained at the location 0x3FFFC0. When XRS is brought to a high level,
execution begins at the location pointed to by the PC. This pin is driven low by the DSC
when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
XRS
80
L10
M13
The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by
an external device, it should be done using an open-drain device.
ADC SIGNALS
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0
ADCLO
35
36
37
38
39
40
41
42
53
52
51
50
49
48
47
46
43
57
54
K4
J5
K1
K2
L1
ADC Group A, Channel 7 input (I)
ADC Group A, Channel 6 input (I)
ADC Group A, Channel 5 input (I)
ADC Group A, Channel 4 input (I)
ADC Group A, Channel 3 input (I)
ADC Group A, Channel 2 input (I)
ADC Group A, Channel 1 input (I)
ADC Group A, Channel 0 input (I)
ADC Group B, Channel 7 input (I)
ADC Group B, Channel 6 input (I)
ADC Group B, Channel 5 input (I)
ADC Group B, Channel 4 input (I)
ADC Group B, Channel 3 input (I)
ADC Group B, Channel 2 input (I)
ADC Group B, Channel 1 input (I)
ADC Group B, Channel 0 input (I)
Low Reference (connect to analog ground) (I)
ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
External reference input (I)
L1
L2
L2
L3
L3
M1
N1
M3
K5
P4
N4
M4
L4
M1
M2
M3
N6
M6
N5
M5
N4
M4
N3
P3
N2
P6
P7
P3
N3
P2
M2
M5
L5
ADCRESEXT
ADCREFIN
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
NAME
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
PIN NO.
ZHH
DESCRIPTION (1)
PGF,
PTP
PIN #
ZJZ
BALL # BALL #
Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass
capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data
sheet that is used in the system.
ADCREFP
ADCREFM
56
55
P5
N5
P5
P4
Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass
capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data
sheet that is used in the system.
CPU AND I/O POWER PINS
ADC Analog Power Pin
VDDA2
VSSA2
VDDAIO
VSSAIO
VDD1A18
VSS1AGND
VDD2A18
VSS2AGND
VDD
34
33
K2
K3
K4
P1
L5
ADC Analog Ground Pin
ADC Analog I/O Power Pin
ADC Analog I/O Ground Pin
ADC Analog Power Pin
45
N2
P1
44
N1
K3
L4
31
J4
32
K1
ADC Analog Ground Pin
ADC Analog Power Pin
59
M6
K6
L6
58
P2
D4
D5
D8
D9
E11
F4
ADC Analog Ground Pin
4
B1
VDD
15
B5
VDD
23
B11
C8
D13
E9
VDD
29
VDD
61
VDD
101
109
117
126
139
146
154
167
9
VDD
F3
F11
H4
J4
CPU and Logic Digital Power Pins
VDD
F13
H1
H12
J2
VDD
VDD
J11
K11
L8
VDD
VDD
K14
N6
A4
VDD
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
A13
B1
71
B10
E7
93
D7
107
121
143
159
170
E12
F5
D11
E4
Digital I/O Power Pin
L8
G4
H11
N14
G11
L10
N14
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
NAME
ZHH
ZJZ
BALL # BALL #
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
A5
A10
A11
B4
A1
A2
A14
B14
F6
8
14
22
30
C3
60
C7
F7
70
C9
F8
83
D1
F9
92
D6
G6
G7
G8
G9
H6
H7
H8
H9
J6
103
106
108
118
120
125
140
144
147
155
160
166
171
D14
E8
E14
F4
Digital Ground Pins
F12
G1
H10
H13
J3
J7
J10
J12
M12
N10
N11
P6
J8
J9
P13
P14
P8
GPIO AND PERIPHERAL SIGNALS
GPIO0
General-purpose input/output 0 (I/O/Z)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
5
6
C1
D3
D2
E4
E2
D1
D2
D3
E1
E2
GPIO1
General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
EPWM1B
ECAP6
MFSRB
GPIO2
EPWM2A
-
-
General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
7
GPIO3
EPWM2B
ECAP5
General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
10
11
MCLKRB
GPIO4
EPWM3A
-
-
General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
NAME
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
PIN NO.
ZHH
DESCRIPTION (1)
PGF,
PTP
PIN #
ZJZ
BALL # BALL #
GPIO5
General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
EPWM3B
MFSRA
ECAP1
12
13
16
17
18
19
20
21
24
E3
E1
F2
F1
G5
G4
G2
G3
H3
E3
F1
F2
F3
G1
G2
G3
H1
H2
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
EPWM4B
MCLKRA
ECAP2
Enhanced capture input/output 2 (I/O)
GPIO8
General-purpose Input/Output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
EPWM5A
CANTXB
ADCSOCAO
ADC start-of-conversion A (O)
GPIO9
General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
EPWM5B
SCITXDB
ECAP3
Enhanced capture input/output 3 (I/O)
GPIO10
General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
EPWM6A
CANRXB
ADCSOCBO
ADC start-of-conversion B (O)
GPIO11
General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
EPWM6B
SCIRXDB
ECAP4
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
General-purpose input/output 14 (I/O/Z)
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external
interface (XINTF) to release the external bus and place all buses and strobes into a high-
impedance state. To prevent this from happening when TZ3 signal goes active, disable this
function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into
high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by
default, unless they are enabled by the code. The XINTF will release the bus when any
current access is complete and there are no pending accesses on the XINTF. (I)
TZ3/ XHOLD
25
H2
H3
SCITXDB
MCLKXB
SCI-B Transmit (O)
McBSP-B transmit clock (I/O)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
NAME
ZHH
ZJZ
BALL # BALL #
GPIO15
General-purpose input/output 15 (I/O/Z)
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on
the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4
function is chosen. If the pin is configured as an output, then XHOLDA function is chosen.
XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF
buses and strobe signals will be in a high-impedance state. XHOLDA is released when the
XHOLD signal is released. External devices should only drive the external bus when
XHOLDA is active (low). (I/O)
TZ4/ XHOLDA
26
H4
J1
SCIRXDB
MFSXB
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
27
28
62
63
64
65
66
67
68
69
72
H5
J1
J2
J3
GPIO17
SPISOMIA
CANRXB
TZ6
General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
SPICLKA
SCITXDB
CANRXA
L6
N8
Enhanced CAN-A receive (I)
GPIO19
General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
SPISTEA
SCIRXDB
CANTXA
K7
L7
M8
P9
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
CANTXB
GPIO21
EQEP1B
MDRA
General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
P7
N7
M7
M8
N8
K8
N9
CANRXB
GPIO22
General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
EQEP1S
MCLKXA
SCITXDB
M9
P10
N10
M10
P11
GPIO23
EQEP1I
MFSXA
SCIRXDB
General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
NAME
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
PIN NO.
ZHH
DESCRIPTION (1)
PGF,
PTP
PIN #
ZJZ
BALL # BALL #
GPIO27
ECAP4
EQEP2S
MFSXB
General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
73
L9
N11
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
141
2
E10
C2
B2
D10
C1
C2
B2
GPIO29
SCITXDA
XA19
General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
1
GPIO31
CANTXA
XA17
General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
176
A2
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
74
75
N9
P9
M11
P12
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
General-purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
General-purpose Input/Output 34 (I/O/Z)
GPIO34
ECAP1
XREADY
Enhanced Capture input/output 1 (I/O)
142
D10
A9
External Interface Ready signal. Note that this pin is always (directly) connected to the
XINTF. If an application uses this pin as a GPIO while also using the XINTF, it should
configure the XINTF to ignore READY.
GPIO35
SCITXDA
XR/ W
General-purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
148
145
150
137
175
151
152
153
A9
C10
D9
B9
C9
B8
GPIO36
SCIRXDA
XZCS0
General-purpose Input/Output 36 (I/O/Z)
SCI receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7
General-purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0
General-purpose Input/Output 38 (I/O/Z)
-
External Interface Write Enable 0 (O)
D11
B3
C10
C3
C8
A7
GPIO39
-
XA16
General-purpose Input/Output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0/ XWE1
General-purpose Input/Output 40 (I/O/Z)
-
External Interface Address Line 0/External Interface Write Enable 1 (O)
D8
GPIO41
-
XA1
General-purpose Input/Output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
A8
GPIO42
-
General-purpose Input/Output 42 (I/O/Z)
-
B8
B7
XA2
External Interface Address Line 2 (O)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
NAME
ZHH
ZJZ
BALL # BALL #
GPIO43
General-purpose Input/Output 43 (I/O/Z)
-
156
157
158
161
162
88
B7
A7
C7
A6
-
XA3
External Interface Address Line 3 (O)
GPIO44
-
XA4
General-purpose Input/Output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5
General-purpose Input/Output 45 (I/O/Z)
D7
B6
-
External Interface Address Line 5 (O)
GPIO46
-
XA6
General-purpose Input/Output 46 (I/O/Z)
B6
C6
-
External Interface Address Line 6 (O)
GPIO47
-
XA7
General-purpose Input/Output 47 (I/O/Z)
A6
D6
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
General-purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (I/O/Z)
P13
N13
P14
M13
M14
L12
L13
L14
K11
K13
K12
H14
G14
L14
L13
L12
K14
K13
K12
J14
J13
J12
H13
H12
H11
G12
GPIO49
ECAP6
XD30
General-purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (I/O/Z)
89
GPIO50
EQEP1A
XD29
General-purpose Input/Output 50 (I/O/Z)
Enhanced QEP1 input A (I)
External Interface Data Line 29 (I/O/Z)
90
GPIO51
EQEP1B
XD28
General-purpose Input/Output 51 (I/O/Z)
Enhanced QEP1 input B (I)
External Interface Data Line 28 (I/O/Z)
91
GPIO52
EQEP1S
XD27
General-purpose Input/Output 52 (I/O/Z)
Enhanced QEP1 Strobe (I/O)
External Interface Data Line 27 (I/O/Z)
94
GPIO53
EQEP1I
XD26
General-purpose Input/Output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (I/O/Z)
95
GPIO54
SPISIMOA
XD25
General-purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (I/O/Z)
96
GPIO55
SPISOMIA
XD24
General-purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (I/O/Z)
97
GPIO56
SPICLKA
XD23
General-purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (I/O/Z)
98
GPIO57
SPISTEA
XD22
General-purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (I/O/Z)
99
GPIO58
MCLKRA
XD21
General-purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (I/O/Z)
100
110
111
GPIO59
MFSRA
XD20
General-purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (I/O/Z)
GPIO60
MCLKRB
XD19
General-purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (I/O/Z)
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
NAME
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
PIN NO.
ZHH
DESCRIPTION (1)
PGF,
PTP
PIN #
ZJZ
BALL # BALL #
GPIO61
MFSRB
XD18
General-purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (I/O/Z)
112
113
114
115
116
119
122
123
124
127
128
129
130
131
132
133
134
135
G12
G13
G11
G10
F14
F11
E13
E11
F10
D12
C14
B14
C12
C13
A14
B13
A13
B12
F14
F13
F12
E14
E13
E12
D14
D13
D12
C14
C13
B13
A12
B12
C12
A11
B11
C11
GPIO62
SCIRXDC
XD17
General-purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (I/O/Z)
GPIO63
SCITXDC
XD16
General-purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (I/O/Z)
GPIO64
-
XD15
General-purpose Input/Output 64 (I/O/Z)
-
External Interface Data Line 15 (I/O/Z)
GPIO65
-
XD14
General-purpose Input/Output 65 (I/O/Z)
-
External Interface Data Line 14 (I/O/Z)
GPIO66
-
XD13
General-purpose Input/Output 66 (I/O/Z)
-
External Interface Data Line 13 (I/O/Z)
GPIO67
-
XD12
General-purpose Input/Output 67 (I/O/Z)
-
External Interface Data Line 12 (I/O/Z)
GPIO68
-
XD11
General-purpose Input/Output 68 (I/O/Z)
-
External Interface Data Line 11 (I/O/Z)
GPIO69
-
XD10
General-purpose Input/Output 69 (I/O/Z)
-
External Interface Data Line 10 (I/O/Z)
GPIO70
-
XD9
General-purpose Input/Output 70 (I/O/Z)
-
External Interface Data Line 9 (I/O/Z)
GPIO71
-
XD8
General-purpose Input/Output 71 (I/O/Z)
-
External Interface Data Line 8 (I/O/Z)
GPIO72
-
XD7
General-purpose Input/Output 72 (I/O/Z)
-
External Interface Data Line 7 (I/O/Z)
GPIO73
-
XD6
General-purpose Input/Output 73 (I/O/Z)
-
External Interface Data Line 6 (I/O/Z)
GPIO74
-
XD5
General-purpose Input/Output 74 (I/O/Z)
-
External Interface Data Line 5 (I/O/Z)
GPIO75
-
XD4
General-purpose Input/Output 75 (I/O/Z)
-
External Interface Data Line 4 (I/O/Z)
GPIO76
-
XD3
General-purpose Input/Output 76 (I/O/Z)
-
External Interface Data Line 3 (I/O/Z)
GPIO77
-
XD2
General-purpose Input/Output 77 (I/O/Z)
-
External Interface Data Line 2 (I/O/Z)
GPIO78
-
General-purpose Input/Output 78 (I/O/Z)
-
XD1
External Interface Data Line 1 (I/O/Z)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
PIN NO.
DESCRIPTION (1)
PGF,
PTP
PIN #
NAME
ZHH
ZJZ
BALL # BALL #
GPIO79
General-purpose Input/Output 79 (I/O/Z)
-
136
163
164
165
168
169
172
173
A12
C6
E6
C5
D5
E5
C4
D4
B10
A5
B5
C5
A4
B4
C4
A3
-
XD0
External Interface Data Line 0 (I/O/Z)
GPIO80
-
XA8
General-purpose Input/Output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9
General-purpose Input/Output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10
General-purpose Input/Output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
GPIO83
-
XA11
General-purpose Input/Output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12
General-purpose Input/Output 84 (I/O/Z)
External Interface Address Line 12 (O)
GPIO85
-
XA13
General-purpose Input/Output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
General-purpose Input/Output 86 (I/O/Z)
-
XA14
External Interface Address Line 14 (O)
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
NAME
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
PIN NO.
ZHH
DESCRIPTION (1)
PGF,
PTP
PIN #
ZJZ
BALL # BALL #
GPIO87
-
XA15
General-purpose Input/Output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
174
149
A3
B9
B3
A8
XRD
External Interface Read Enable
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
7.1 Absolute Maximum Ratings
Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges.
MIN (1) (2)
MAX
UNIT
VDDIO, VDD3VFL with respect to VSS
VDDA2, VDDAIO with respect to VSSA
VDD with respect to VSS
–0.3
4.6
4.6
2.5
2.5
–0.3
–0.3
Supply voltage
V
VDD1A18, VDD2A18 with respect to VSSA
–0.3
VSSA2, VSSAIO, VSS1AGND, VSS2AGND
with respect to VSS
–0.3
0.3
Input voltage
VIN
–0.3
–0.3
–20
–20
–40
–40
–40
–40
–65
4.6
4.6
20
V
V
Output voltage
VO
(3)
Input clamp current
Output clamp current
IIK (VIN < 0 or VIN > VDDIO
)
mA
mA
IOK (VO < 0 or VO > VDDIO
A version(4)
)
20
85
Operating ambient temperature, TA
S version
125
125
150
150
°C
Q version
(4)
Junction temperature
Storage temperature
TJ
°C
°C
(4)
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA. This includes the analog inputs which have an internal clamping circuit that clamps the
voltage to a diode drop above VDDA2 or below VSSA2
.
(4) One or both of the following conditions may result in a reduction of overall device life:
•
•
long-term high-temperature storage
extended use at maximum temperature
For additional information, see Semiconductor and IC package thermal metrics.
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.2 ESD Ratings – Automotive
VALUE
UNIT
TMS320F2833x, TMS320F2823x in PTP Package
Human body model (HBM), per AEC Q100-002(1)
±2000
±500
All pins
V(ESD) Electrostatic discharge
V
Corner pins on 176-pin
PTP: 1, 44, 45, 88, 89,
132, 133, 176
Charged-device model (CDM), per AEC Q100-011
±750
TMS320F2833x, TMS320F2823x in ZJZ Package
Human body model (HBM), per AEC Q100-002(1)
±2000
±500
All pins
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
Corner pins on 176-ball
ZJZ: A1, A14, P1, P14
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings – Commercial
VALUE
UNIT
TMS320F2833x, TMS320F2823x in PGF Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±500
TMS320F2833x, TMS320F2823x in ZHH Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
1.805
1.71
NOM
3.3
MAX UNIT
Device supply voltage, I/O, VDDIO
3.465
1.995
1.89
V
Device operation @ 150 MHz
Device supply voltage CPU, VDD
1.9
V
Device operation @ 100 MHz
1.8
Supply ground, VSS, VSSIO, VSSAIO
VSSA2, VSS1AGND, VSS2AGND
,
0
V
V
ADC supply voltage (3.3 V),
VDDA2, VDDAIO
3.135
3.3
3.465
Device operation @ 150 MHz
Device operation @ 100 MHz
1.805
1.9
1.8
3.3
1.995
ADC supply voltage,
VDD1A18, VDD2A18
V
V
1.71
1.89
Flash supply voltage, VDD3VFL
3.135
3.465
F28335/F28334/F28235/F28234
F28333/F28332/F28232
All inputs except X1
X1
2
150
Device clock frequency (system clock),
fSYSCLKOUT
MHz
2
2
100
VDDIO
High-level input voltage, VIH
Low-level input voltage, VIL
V
V
0.7 * VDD – 0.05
VDD
All inputs except X1
X1
0.8
0.3 * VDD + 0.05
All I/Os except Group 2
Group 2(1)
–4
–8
High-level output source current,
VOH = 2.4 V, IOH
mA
mA
All I/Os except Group 2
Group 2(1)
4
Low-level output sink current,
VOL = VOL MAX, IOL
8
A version
–40
–40
–40
85
Ambient temperature, TA
Junction temperature, TJ
S version
125
125
125
°C
°C
Q version
(1) Group 2 pins are as follows: GPIO28, GPIO29, GPIO30, GPIO31, TDO, XCLKOUT, EMU0, EMU1, XINTF pins, GPIO35-87, XRD.
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.5 Power Consumption Summary
7.5.1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
(1)
(9)
(2)
(3)
IDD
IDDIO
TYP(4)
IDD3VFL
TYP
IDDA18
TYP(4)
IDDA33
TYP(4)
MODE
TEST CONDITIONS
TYP(4)
MAX
MAX
MAX
MAX
MAX
The following peripheral clocks
are enabled:
•
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6
•
eCAP1, eCAP2, eCAP3,
eCAP4, eCAP5, eCAP6
•
•
•
eQEP1, eQEP2
eCAN-A
SCI-A, SCI-B
(FIFO mode)
Operational
(Flash)(6)
290 mA
315 mA
30 mA
50 mA
35 mA
40 mA
30 mA
35 mA
1.5 mA
2 mA
•
•
•
•
SPI-A (FIFO mode)
ADC
I2C
CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
150 kHz.
All I/O pins are left
unconnected.(5)
Flash is powered down.
XCLKOUT is turned off.
The following peripheral clocks
are enabled:
IDLE
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
100 mA
120 mA
15 mA
60 μA
120 μA
2 μA
10 μA
5 μA
60 μA
15 μA
20 μA
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT(8)
8 mA
60 μA
60 μA
120 μA
120 μA
2 μA
2 μA
10 μA
10 μA
5 μA
5 μA
60 μA
60 μA
15 μA
15 μA
20 μA
20 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(7)
150 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins. To realize the IDDA18 currents shown for IDLE, STANDBY, and HALT, clock to the
ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD
2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
=
(5) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(6) When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
(8) HALT mode IDD currents will increase with temperature in a nonlinear fashion.
(9) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 7.9.7.3. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O pin.
It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
7.5.2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
(1)
(9)
(2)
(3)
IDD
IDDIO
TYP(4)
IDD3VFL
TYP
IDDA18
TYP(4)
IDDA33
TYP(4)
MODE
TEST CONDITIONS
TYP(4)
MAX
MAX
MAX
MAX
MAX
The following peripheral
clocks are enabled:
•
ePWM1, ePWM2,
ePWM3, ePWM4,
ePWM5, ePWM6
•
eCAP1, eCAP2,
eCAP3, eCAP4,
eCAP5, eCAP6
•
•
•
eQEP1, eQEP2
eCAN-A
SCI-A, SCI-B
(FIFO mode)
Operational
(Flash)(6)
290 mA
315 mA
30 mA
50 mA
35 mA
40 mA
30 mA
35 mA
1.5 mA
2 mA
•
•
•
•
SPI-A (FIFO mode)
ADC
I2C
CPU-Timer 0,
CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
150 kHz.
All I/O pins are left
unconnected. (5)
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
•
•
•
•
eCAN-A
SCI-A
SPI-A
I2C
100 mA
120 mA
15 mA
60 μA
120 mA
2 μA
10 μA
5 μA
60 μA
15 μA
20 μA
Flash is powered down.
Peripheral clocks are off.
STANDBY
HALT(8)
8 mA
60 μA
60 μA
120 μA
120 μA
2 μA
2 μA
10 μA
10 μA
5 μA
5 μA
60 μA
60 μA
15 μA
15 μA
20 μA
20 μA
Flash is powered down.
Peripheral clocks are off.
Input clock is disabled.(7)
150 μA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) IDDA18 includes current into VDD1A18 and VDD2A18 pins. To realize the IDDA18 currents shown for IDLE, STANDBY, and HALT, clock to the
ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(3) IDDA33 includes current into VDDA2 and VDDAIO pins.
(4) The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD
2.0 V; VDDIO, VDD3VFL, VDDA = 3.6 V).
=
(5) The following is done in a loop:
•
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(6) When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
(8) HALT mode IDD currents will increase with temperature in a nonlinear fashion.
(9) The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Section 7.9.7.3. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.5.3 Reducing Current Consumption
The 2833x and 2823x DSCs incorporate a method to reduce the device current consumption. Because each
peripheral unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning
off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 7-1
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 7-1. Typical Current Consumption by Various
Peripherals (at 150 MHz) (1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION/MODULE (mA)(2)
ADC
I2C
8(3)
2.5
5
eQEP
ePWM
eCAP
SCI
5
2
5
SPI
4
eCAN
McBSP
CPU-Timer
XINTF
DMA
8
7
2
10(4)
10
15
FPU
(1) All peripheral clocks are disabled upon reset. Writing to or
reading from peripheral registers is possible only after the
peripheral clocks are turned on.
(2) For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for
one ePWM module.
(3) This number represents the current drawn by the digital portion
of the ADC module. Turning off the clock to the ADC module
results in the elimination of the current drawn by the analog
portion of the ADC (IDDA18) as well.
(4) Operating the XINTF bus has a significant effect on IDDIO
current. It will increase considerably based on the following:
•
How many address/data pins toggle from one cycle to
another
•
•
•
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Following are other methods to reduce power consumption further:
•
The Flash module may be powered down if code is run off SARAM. This results in a current reduction of 35
mA (typical) in the VDD3VFL rail.
•
•
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Significant savings in IDDIO may be realized by disabling the pullups on pins that assume an output function
and on XINTF pins. A savings of 35 mW (typical) can be achieved by this.
The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 165
mA, (typical). To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled
by that application) must be added to the baseline IDD current.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.5.4 Current Consumption Graphs
Current Vs Frequency
350.00
300.00
250.00
200.00
150.00
100.00
50.00
0.00
10 20
30 40 50 60 70
80 90 100 110 120 130 140 150
SYSCLKOUT (MHz)
IDD
IDDIO
IDDA18
IDD3VFL
1.8-V Current
3.3-V Current
Figure 7-1. Typical Operational Current Versus Frequency (F28335, F28235, F28334, F28234)
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Device Power Vs SYSCLKOUT
1000.0
900.0
800.0
700.0
600.0
500.0
400.0
300.0
200.0
100.0
0.0
SYSCLKOUT (MHz)
Figure 7-2. Typical Operational Power Versus Frequency (F28335, F28235, F28334, F28234)
Note
Typical operational current for 100-MHz devices (28x32) can be estimated from Figure 7-1. Compared
to 150-MHz devices, the analog and flash module currents remain unchanged. While a marginal
decrease in IDDIO current can be expected due to the reduced external activity of peripheral pins,
current reduction is primarily in IDD
.
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOH MAX
IOH = 50 μA
VOH High-level output voltage
V
VDDIO – 0.2
VOL
Low-level output voltage
Pin with pullup
IOL = IOL MAX
0.4
V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
All I/Os (including XRS)
–80
–140
–190
enabled
Input current
(low level)
IIL
μA
Pin with pulldown
enabled
±2
±2
80
±2
Pin with pullup
enabled
Input current
(high level)
IIH
μA
Pin with pulldown
enabled
28
50
2
Output current, pullup or pulldown
disabled
IOZ
CI
μA
pF
Input capacitance
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.7 Thermal Resistance Characteristics
7.7.1 PGF Package
°C/W(1) (2)
8.2
AIR FLOW (lfm)(3)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0
28.1
44
0
0
34.5
33
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air
Junction-to-package top
Junction-to-board
31
0.12
0.48
0.57
0.74
28.1
26.3
25.9
25.2
150
250
500
0
PsiJT
150
250
500
PsiJB
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.7.2 PTP Package
°C/W(1) (2)
12.1
5.1
AIR FLOW (lfm)(3)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0
0
17.4
11.7
10.1
8.8
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air
Junction-to-package top
Junction-to-board
0.2
0.3
150
250
500
0
PsiJT
0.4
0.5
5.0
4.7
150
250
500
PsiJB
4.7
4.6
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
•
•
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.7.3 ZHH Package
°C/W(1) (2)
8.8
AIR FLOW (lfm)(3)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0
12.5
32.8
24.1
22.9
20.9
0.09
0.3
0
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air
Junction-to-package top
Junction-to-board
150
250
500
0
PsiJT
0.36
0.48
12.4
11.8
11.7
11.5
150
250
500
PsiJB
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.7.4 ZJZ Package
°C/W(1) (2)
11.4
12
AIR FLOW (lfm)(3)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0
0
29.6
20.9
19.7
18
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air
Junction-to-package top
Junction-to-board
0.2
0.78
0.91
1.11
12.2
11.6
11.5
11.3
150
250
500
0
PsiJT
150
250
500
PsiJB
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
•
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems with
more than 1 Watt power dissipation may require a product level thermal design. Care should be taken to keep Tj
within specified limits. In the end applications, Tcase should be measured to estimate the operating junction
temperature Tj. Tcase is normally measured at the center of the package top side surface. The thermal
application note Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9 Timing and Switching Characteristics
7.9.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
7.9.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.9.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
(Α)
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-3. 3.3-V Test Load Circuit
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Section 7.9.1.3.1 and Section 7.9.1.3.2 list the cycle times of various clocks.
7.9.1.3.1 Clocking and Nomenclature (150-MHz Devices)
MIN
28.6
20
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator clock
XCLKIN(1)
tc(CI), Cycle time
Frequency
6.67
4
250
150
500
150
2000
150
MHz
ns
tc(SCO), Cycle time
Frequency
6.67
2
SYSCLKOUT
XCLKOUT
MHz
ns
tc(XCO), Cycle time
Frequency
6.67
0.5
MHz
ns
tc(HCO), Cycle time
Frequency
6.67
13.3(3)
75(3)
HSPCLK(2)
150
75(4)
25
MHz
ns
tc(LCO), Cycle time
Frequency
13.3
40
26.7(3)
37.5(3)
LSPCLK(2)
MHz
ns
tc(ADCCLK), Cycle time
Frequency
ADC clock
MHz
(1) This also applies to the X1 pin if a 1.9-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default value if SYSCLKOUT = 150 MHz.
(4) Although LSPCLK is capable of reaching 100 MHz, it is specified at 75 MHz because the smallest valid "Low-speed peripheral clock
prescaler register" value is "1" for 150-MHz devices.
7.9.1.3.2 Clocking and Nomenclature (100-MHz Devices)
MIN
28.6
20
10
4
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
50
35
ns
MHz
ns
On-chip oscillator clock
XCLKIN(1)
tc(CI), Cycle time
Frequency
250
100
500
100
2000
100
MHz
ns
tc(SCO), Cycle time
Frequency
10
2
SYSCLKOUT
XCLKOUT
MHz
ns
tc(XCO), Cycle time
Frequency
10
0.5
10
MHz
ns
tc(HCO), Cycle time
Frequency
20(3)
50(3)
40(3)
25(3)
HSPCLK(2)
100
100
25
MHz
ns
tc(LCO), Cycle time
Frequency
10
40
LSPCLK(2)
MHz
ns
tc(ADCCLK), Cycle time
Frequency
ADC clock
MHz
(1) This also applies to the X1 pin if a 1.8-V oscillator is used.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the default value if SYSCLKOUT = 100 MHz.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.2 Power Sequencing
No requirements are placed on the power-up and power-down sequences of the various power pins to ensure
the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of
the I/O pins are powered prior to the 1.9-V/1.8-V transistors, it is possible for the output buffers to turn on,
causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or
simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach
0.7 V.
There are some requirements on the XRS pin:
1. During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable (see Section
7.9.2.2). This is to enable the entire device to start from a known condition.
2. During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V. Meeting this
requirement is important to help prevent unintended flash program or erase.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this
value is 0.7 V above VDDA) before powering up the device. Furthermore, VDDIO and VDDA should always be
within 0.3 V of each other. Voltages applied to pins on an unpowered device can bias internal P-N junctions in
unintended ways and produce unpredictable results.
7.9.2.1 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power Management page
for a list of TI power management ICs. Click the Reference designs tab for specific power management
reference designs.
Copyright © 2021 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
, V
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
V
DDIO DD3VFL
V , V
DDA2 DDAIO
(3.3 V)
V , V
DD DD1A18,
V
DD2A18
(1.9 V/1.8 V)
XCLKIN
X1/X2
(A)
OSCCLK/8
OSCCLK/16
XCLKOUT
User-Code Dependent
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/4. Because both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a
reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/16 during
this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCCLK/2. Because the XTIMCLK register is unchanged by the boot
ROM, XCLKOUT is OSCCLK/8 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
C. See Section 7.9.2 for requirements to ensure a high-impedance state for GPIO pins during power up.
Figure 7-4. Power-on Reset
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.2.2 Reset ( XRS) Timing Requirements
MIN
32tc(OSCCLK)
32tc(OSCCLK)
NOM
MAX UNIT
(1)
tw(RSL1)
tw(RSL2)
Pulse duration, stable input clock to XRS high
Pulse duration, XRS low
cycles
cycles
Warm reset
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
td(EX)
512tc(OSCCLK)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
tOSCST
1
th(boot-mode)
Hold time for boot-mode pins
200tc(OSCCLK)
cycles
(1) In addition to the tw(RSL1) requirement, XRS must be low at least for 1 ms after VDD reaches 1.5 V.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Internal)
(Don’t Care)
User-Code Execution
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-5. Warm Reset
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Figure 7-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is
written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is
complete (which takes 131072 OSCCLK cycles), SYSCLKOUT reflects the new operating frequency, OSCCLK ×
4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t ) is
(Changed CPU Frequency)
p
131072 OSCCLK Cycles Long.)
Figure 7-6. Example of Effect of Writing Into PLLCR Register
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.3 Clock Requirements and Characteristics
7.9.3.1 Input Clock Frequency
PARAMETER
MIN
20
20
4
TYP MAX UNIT
Resonator (X1/X2)
Crystal (X1/X2)
35
35
MHz
150
fx
Input clock frequency
150-MHz device
100-MHz device
External oscillator/clock
source (XCLKIN or X1 pin)
4
100
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
1 - 5
MHz
7.9.3.2 XCLKIN Timing Requirements – PLL Enabled
NO.
MIN
MAX UNIT
C8
C9
tc(CI)
tf(CI)
Cycle time, XCLKIN
33.3
200
6
ns
ns
ns
Fall time, XCLKIN(1)
C10 tr(CI)
Rise time, XCLKIN(1)
6
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(CI)
45%
45%
55%
55%
(1)
Pulse duration, XCLKIN high as a percentage of tc(CI)
(1) This applies to the X1 pin also.
7.9.3.3 XCLKIN Timing Requirements – PLL Disabled
NO.
MIN
6.67
10
MAX UNIT
150-MHz device
100-MHz device
Up to 30 MHz
250
ns
250
C8 tc(CI)
C9 tf(CI)
C10 tr(CI)
Cycle time, XCLKIN
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
6
ns
2
30 MHz to 150 MHz
Up to 30 MHz
6
ns
2
30 MHz to 150 MHz
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(CI)
Pulse duration, XCLKIN high as a percentage of tc(CI)
45%
45%
55%
55%
(1)
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 8-38.
7.9.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO.
PARAMETER
Cycle time, XCLKOUT
MIN
6.67
10
TYP
MAX UNIT
150-MHz device
100-MHz device
C1 tc(XCO)
ns
C3 tf(XCO)
C4 tr(XCO)
C5 tw(XCOL)
C6 tw(XCOH)
tp
Fall time, XCLKOUT
2
2
ns
ns
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H – 2
H – 2
H + 2
ns
ns
H + 2
(3)
131072tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
Copyright © 2021 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.3.5 Timing Diagram
C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-7. Clock Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4 Peripherals
7.9.4.1 General-Purpose Input/Output (GPIO)
7.9.4.1.1 GPIO - Output Timing
7.9.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
8
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
All GPIOs
All GPIOs
8
ns
25
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 7-8. General-Purpose Output Timing
Copyright © 2021 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.1.2 GPIO - Input Timing
7.9.4.1.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
QUALPRD = 0
QUALPRD ≠ 0
tw(SP)
Sampling period
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
(B)
w(SP)
by GPxCTRL[QUALPRD]
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-9. Sampling Mode
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using three samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using six samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 7-10. General-Purpose Input Timing
Copyright © 2021 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.1.4 Low-Power Mode Wakeup Timing
Section 7.9.4.1.4.1 shows the timing requirements, Section 7.9.4.1.4.2 shows the switching characteristics, and
Figure 7-11 shows the timing diagram for IDLE mode.
7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
MIN
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, external wake signal to
program execution resume (2)
Wake-up from flash
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
20tc(SCO)
cycles
cycles
cycles
•
Flash module in active state
20tc(SCO) + tw(IQSW)
1050tc(SCO)
td(WAKE-IDLE)
Wake-up from flash
Flash module in sleep state
•
1050tc(SCO) + tw(IQSW)
20tc(SCO)
Wake-up from SARAM
20tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
7.9.4.1.4.3 IDLE Mode Timing Diagram
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)(B)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-11. IDLE Entry and Exit Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.1.4.4 STANDBY Mode Timing Requirements
MIN
3tc(OSCCLK)
MAX
UNIT
Without input qualification
With input qualification(1)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.4.1.4.5 STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal to
program execution resume(1)
•
•
Wake up from flash
Without input qualifier
With input qualifier
Without input qualifier
With input qualifier
100tc(SCO)
–
Flash module in active
state
cycles
100tc(SCO) + tw(WAKE-INT)
1125tc(SCO)
td(WAKE-STBY)
Wake up from flash
–
Flash module in sleep
state
cycles
cycles
1125tc(SCO) + tw(WAKE-INT)
Without input qualifier
With input qualifier
100tc(SCO)
•
Wake up from SARAM
100tc(SCO) + tw(WAKE-INT)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
7.9.4.1.4.6 STANDBY Mode Timing Diagram
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
(G)
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to
XINTF is in progress and its access time is longer than this number then it will fail. It is recommended to
enter STANDBY mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
Copyright © 2021 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
G. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-12. STANDBY Entry and Exit Timing Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.1.4.7 HALT Mode Timing Requirements
MIN
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Section 7.9.2.2 for an explanation of toscst
.
7.9.4.1.4.8 HALT Mode Switching Characteristics
PARAMETER
MIN
32tc(SCO)
MAX
45tc(SCO)
UNIT
cycles
cycles
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
131072tc(OSCCLK)
Delay time, PLL lock to program execution resume
•
Wake up from flash
Flash module in sleep state
1125tc(SCO)
cycles
cycles
td(WAKE-HALT)
–
•
Wake up from SARAM
35tc(SCO)
7.9.4.1.4.9 HALT Mode Timing Diagram
(G)
(A)
(C)
(E)
(B)
(D)
(F)
Device
Status
HALT
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
(H)
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off
and the CLKIN to the core is stopped:
•
•
•
16 cycles, when DIVSEL = 00 or 01
32 cycles, when DIVSEL = 10
64 cycles, when DIVSEL = 11
This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its
access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF access in
progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 131,072 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
Note that these 131,072 clock cycles are applicable even when the PLL is disabled (that is, code execution will be delayed by this
duration even when the PLL is disabled).
Copyright © 2021 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
F. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
G. Normal operation resumes.
H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at
least 4 OSCCLK cycles have elapsed.
Figure 7-13. HALT Wakeup Using GPIOn
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.2 Enhanced Control Peripherals
7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 7.9.4.2.1.1 shows the ePWM timing requirements and
Section 7.9.4.2.1.2, ePWM switching characteristics.
7.9.4.2.1.1 ePWM Timing Requirements (1)
MIN
2tc(SCO)
MAX
UNIT
Asynchronous
Synchronous
tw(SYCIN)
Sync input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.1.2 ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SCO)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(PWM)tza
no pin load
25
20
ns
ns
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
7.9.4.2.2 Trip-Zone Input Timing
SYSCLK
tw(TZ)
TZ(A)
td(TZ-PWM)HZ
PWM(B)
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-14. PWM Hi-Z Characteristics
7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
MIN
1tc(SCO)
MAX UNIT
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
Copyright © 2021 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.2.3 High-Resolution PWM Timing
Section 7.9.4.2.3.1 shows the high-resolution PWM switching characteristics.
7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
MIN
TYP
MAX UNIT
310 ps
Micro Edge Positioning (MEP) step size(1)
150
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
7.9.4.2.4 Enhanced Capture (eCAP) Timing
Section 7.9.4.2.4.1 shows the eCAP timing requirement and Section 7.9.4.2.4.2 shows the eCAP switching
characteristics.
7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
MIN
2tc(SCO)
MAX UNIT
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.4.2 eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 7.9.4.2.5.1 shows the eQEP timing requirement and Section 7.9.4.2.5.2 shows the eQEP switching
characteristics.
7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
MIN
MAX
UNIT
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
tw(QEPP)
QEP input period
cycles
2[1tc(SCO) + tw(IQSW)
]
Asynchronous(2)/synchronous
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous(2)/synchronous
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) Refer to the TMS320F2833x, TMS320F2823x DSC silicon errata for limitations in the asynchronous mode.
7.9.4.2.5.2 eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO)
cycles
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
UNIT
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
PARAMETER
TEST CONDITIONS
MIN
MAX
Delay time, QEP input edge to position compare sync
output
td(PCS-OUT)QEP
6tc(SCO)
cycles
Copyright © 2021 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.2.6 ADC Start-of-Conversion Timing
7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(HCO )
cycles
7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
t
w(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-15. ADCSOCAO or ADCSOCBO Timing
7.9.4.3 External Interrupt Timing
7.9.4.3.1 External Interrupt Timing Requirements (1)
MIN
1tc(SCO)
MAX
UNIT
Synchronous
With qualifier
(2)
tw(INT)
Pulse duration, INT input low/high
cycles
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.9.4.3.2 External Interrupt Switching Characteristics (1)
PARAMETER
MIN
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.3.3 External Interrupt Timing Diagram
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-16. External Interrupt Timing
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.4 I2C Electrical Specification and Timing
7.9.4.4.1 I2C Timing
TEST CONDITIONS
MIN
MAX
400
UNIT
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
fSCL
SCL clock frequency
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
Low level output voltage
3-mA sink current
0.4
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tLOW
Low period of SCL clock
High period of SCL clock
1.3
μs
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tHIGH
0.6
μs
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
lI
–10
10
μA
Copyright © 2021 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
7.9.4.5.1 Master Mode Timing
Section 7.9.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 7.9.4.5.1.2 lists the master mode
timing (clock phase = 1). Figure 7-17 and Figure 7-18 show the timing waveforms.
7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
BRR EVEN
MIN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
+
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
–
3
4
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
5
0.5tc(SPC)M – 10
Setup time, SPISOMI before
SPICLK
8
35
0
35
0
Hold time, SPISOMI valid after
SPICLK
9
Delay time, SPISTE active to
SPICLK
1.5tc(SPC)M
–
1.5tc(SPC)M –
3tc(SYSCLK) – 10
23
24
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M – 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 7-17. SPI Master Mode External Timing (Clock Phase = 0)
Copyright © 2021 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
BRR EVEN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M
–
0.5tc(SPC)M
–
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
35
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
+
3
6
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
35
Hold time, SPISOMI valid after
SPICLK
0
0
Delay time, SPISTE active to
SPICLK
2tc(SPC)M
–
2tc(SPC)M
–
3tc(SYSCLK) – 10
3tc(SYSCLK) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
0.5tc(SPC) – 10
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 7-18. SPI Master Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.5.2 Slave Mode Timing
Section 7.9.4.5.2.1 lists the slave mode timing (clock phase = 0) and Section 7.9.4.5.2.2 lists the slave mode
timing (clock phase = 1). Figure 7-19 and Figure 7-20 show the timing waveforms.
7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (4) (3) (5)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-19. SPI Slave Mode External Timing (Clock Phase = 0)
Copyright © 2021 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
35
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-20. SPI Slave Mode External Timing (Clock Phase = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
7.9.4.6.1 McBSP Transmit and Receive Timing
7.9.4.6.1.1 McBSP Timing Requirements (1) (2)
NO.
MIN
MAX UNIT
1
kHz
MHz
ns
McBSP module clock (CLKG, CLKX, CLKR) range
25 (3)
40
McBSP module cycle time (CLKG, CLKX, CLKR) range
1
ms
ns
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P – 7
ns
7
7
ns
Fall time, CLKR/X
ns
18
2
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
M20 th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
18
2
0
Hold time, DR valid after CLKR low
6
18
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (25 MHz).
Copyright © 2021 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.6.1.2 McBSP Switching Characteristics (1) (2)
NO.
M1
M2
M3
PARAMETER
MIN
MAX UNIT
tc(CKRX)
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
2P
ns
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 5 (3)
D + 5 (3)
ns
ns
C – 5 (3)
C + 5 (3)
0
3
0
3
4
27
4
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
27
8
Disable time, CLKX high to DX high impedance
following last data bit
14
9
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
28
8
Delay time, CLKX high to DX valid
DXENA = 0
M7
td(CKXH-DXV)
ns
ns
14
P + 8
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1
10b) modes
CLKX ext
P + 14
CLKX int
CLKX ext
CLKX int
0
6
Enable time, CLKX high to DX driven
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1
10b) modes
DXENA = 0
M8
M9
ten(CKXH-DX)
P
CLKX ext
P + 6
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
8
14
Delay time, FSX high to DX valid
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
td(FXH-DXV)
ns
ns
P + 8
P + 14
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
0
6
Enable time, FSX high to DX driven
M10 ten(FXH-DX)
P
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
M1, M11
M2, M12
M3, M12
M13
CLKR
M4
M4
M14
FSR (int)
M15
M16
FSR (ext)
M18
M17
DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
M18
DR
(RDATDLY=01b)
Bit (n−1)
(n−3)
(n−2)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
Figure 7-21. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
(XDATDLY=01b)
Bit (n−1)
M8
Bit 0
M6
M7
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 7-22. McBSP Transmit Timing
Copyright © 2021 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.6.2 McBSP as SPI Master or Slave Timing
7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(BFXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle timez, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M24
M25
th(CKXL-FXL)
td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
2P(1)
ns
ns
P
Disable time, DX high impedance following
last data bit from FSX high
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M33
M32
MSB
LSB
CLKX
M25
M24
FSX
M28
M29
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7-23. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
UNIT
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
MASTER
SLAVE
MIN MAX
NO.
MIN
30
1
MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
M41 tsu(FXL-CKXH)
M42 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M34 th(CKXL-FXL)
M35 td(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
P
ns
ns
2P(1)
Disable time, DX high impedance following last data bit
from CLKX low
M37 tdis(CKXL-DXHZ)
M38 td(FXL-DXV)
P + 6
6
7P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M42
MSB
LSB
M41
CLKX
M35
M34
FSX
M37
M38
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
M40
(n-2)
(n-3)
(n-4)
M39
Bit 0
(n-3)
(n-4)
Figure 7-24. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
Copyright © 2021 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M49 tsu(DRV-CKXH)
M50 th(CKXH-DRV)
M51 tsu(FXL-CKXL)
M52 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
M43 th(CKXH-FXL)
M44 td(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
ns
ns
Disable time, DX high impedance following last data bit from
FSX high
M47 tdis(FXH-DXHZ)
M48 td(FXL-DXV)
6
6
6P + 6
4P + 6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M52
M51
MSB
LSB
CLKX
M43
M44
FSX
M48
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
M49
M50
(n-2)
Bit 0
(n-3)
(n-4)
Figure 7-25. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
UNIT
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
MASTER
SLAVE
MIN MAX
NO.
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
MASTER(2)
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
M53 th(CKXH-FXL)
M54 td(FXL-CKXL)
M55 td(CLKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
P
ns
ns
ns
2P(1)
–2
0
3P + 6
7P + 6
4P + 6
5P + 20
Disable time, DX high impedance following last data
bit from CLKX high
M56 tdis(CKXH-DXHZ)
M57 td(FXL-DXV)
P + 6
6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
M61
M60
MSB
M54
LSB
CLKX
M53
FSX
M56
M55
M57
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
M58
M59
Bit 0
Bit(n-1)
(n-2)
(n-3)
Figure 7-26. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
Copyright © 2021 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.5 Emulator Connection Without Signal Buffering for the DSP
Figure 7-27 shows the connection between the DSP and JTAG header for a single-processor configuration. If the
distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 7-27 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on
buffering JTAG signals and multiple processor connections, see the TMS320F/C24x DSP controllers CPU and
instruction set reference guide.
6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
GND
1
6
GND
GND
GND
GND
3
8
TDI
7
10
12
TDO
TDO
11
9
TCK
TCK
TCK_RET
DSC
JTAG Header
Figure 7-27. Emulator Connection Without Signal Buffering for the DSP
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
75
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.6 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 7-2 shows the
relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of
XTIMCLK cycles.
Table 7-2. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)(1) (2)
DESCRIPTION
X2TIMING = 0
XRDLEAD × tc(XTIM)
X2TIMING = 1
(XRDLEAD × 2) × tc(XTIM)
LR
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
AR
TR
LW
AW
TW
(XRDACTIVE + WS + 1) × tc(XTIM)
XRDTRAIL × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
(XWRACTIVE + WS + 1) × tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1) tc(XTIM) − Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait-state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
7.9.6.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 0
≥ 0
≥ 1
≥ 0
≥ 0
0, 1
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Valid
0
1
0
0
0
0
0
1
0
0
0
0
0, 1
(1) No hardware to detect illegal XTIMING configurations
Copyright © 2021 Texas Instruments Incorporated
76
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
2
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
Note
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
≥ 0
≥ 1
≥ 2
≥ 0
0, 1
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Invalid(1)
Valid
0
1
1
0
0
2
0
0
0
0
1
1
0
0
2
0
0
0
0, 1
0, 1
(1) No hardware to detect illegal XTIMING configurations
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
77
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
2
3
Lead:
LR ≥ tc(XTIM)
LW ≥ tc(XTIM)
Active:
AR ≥ 2 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
LR + AR ≥ 4 × tc(XTIM)
LW + AW ≥ 4 × tc(XTIM)
Lead + Active:
Note
Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions :
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 1
≥ 2
0
≥ 1
≥ 2
0
0, 1
or
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 1
0
≥ 2
≥ 1
0
0, 1
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
Invalid(1)
Invalid(1)
Valid
0
1
1
1
1
2
0
0
1
2
2
1
0
0
0
0
0
0
0
1
1
1
1
2
0
0
1
2
2
1
0
0
0
0
0
0
0, 1
0, 1
0
1
Valid
0, 1
0, 1
Valid
(1) No hardware to detect illegal XTIMING configurations
Copyright © 2021 Texas Instruments Incorporated
78
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Unless otherwise specified, all XINTF timing is applicable for the clock configurations listed in Table 7-3.
Table 7-3. XINTF Clock Configurations
MODE
SYSCLKOUT
XTIMCLK
SYSCLKOUT
150 MHz
XCLKOUT
SYSCLKOUT
150 MHz
1
Example:
2
150 MHz
SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
75 MHz
Example:
3
150 MHz
1/2 SYSCLKOUT
75 MHz
1/2 SYSCLKOUT
75 MHz
Example:
4
150 MHz
1/2 SYSCLKOUT
75 MHz
1/4 SYSCLKOUT
37.5 MHz
Example:
150 MHz
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 7-28.
PCLKR3[XINTFENCLK]
XTIMING0
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
0
0
1
SYSCLKOUT
C28x
CPU
XTIMCLK
/2
1
0
XCLKOUT
/2
1
0
XINTCNF2 (XTIMCLK)
XINTCNF2
(CLKMODE)
XINTCNF2
(CLKOFF)
Figure 7-28. Relationship Between SYSCLKOUT and XTIMCLK
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
79
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.6.4 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE0, XWE1, and zone chip-select ( XZCS) change state in relationship to the rising
edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be either equal to or one-half the
frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half XTIMCLK, some strobes will change state either
on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the notation
XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge (high) or
XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT, the notation
XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active low
XRNWL
XR/ W active low
•
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the total
number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd, then
the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XRD active low
XWEL
XWE1 or XWE0 active low
•
•
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be
with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XRD inactive high
XWEH
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number of
lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead + active +
trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the
falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XRNWH
XR/ W inactive high
Copyright © 2021 Texas Instruments Incorporated
80
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.6.5 External Interface Read Timing
7.9.6.5.1 External Interface Read Timing Requirements
MIN
MAX
(LR + AR) – 16 (1)
AR – 14 (1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 7-2.
7.9.6.5.2 External Interface Read Switching Characteristics
PARAMETER
MIN
MAX
1
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–1
0.5
1.5
0.5
0.5
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
–1.5
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
Trail
(A)(B)
(C)
Active
Lead
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
XA[0:19]
t
d(XCOH-XA)
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE0, XWE1(D)
XR/W
t
su(XD)XRD
t
a(A)
t
h(XD)XRD
t
a(XRD)
XD[0:31], XD[0:15]
XREADY(E)
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 7-29. Example Read Access
XTIMING register parameters used for this example :
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
81
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
≥ 0
≥ 0
0
0
N/A(1)
N/A(1)
N/A(1)
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
Copyright © 2021 Texas Instruments Incorporated
82
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.6.6 External Interface Write Timing
7.9.6.6.1 External Interface Write Switching Characteristics
PARAMETER
MIN
MAX
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–1
0.5
1.5
2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE0, XWE1 (3) low
Delay time, XCLKOUT high/low to XWE0, XWE1 high
Delay time, XCLKOUT high to XR/ W low
2
1
Delay time, XCLKOUT high/low to XR/ W high
–1
0
0.5
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high
Maximum time for DSP to release the data bus after XR/ W inactive high
td(XWEL-XD)
1
(1)
th(XA)XZCSH
th(XD)XWE
TW – 2 (2)
tdis(XD)XRNW
4
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
(2) TW = Trail period, write access. See Table 7-2.
(3) XWE1 is used in 32-bit data bus mode only. In 16-bit mode, this signal is XA0.
Active
(A) (B)
(C)
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE0, XWE1(D)
XR/W
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
XD[0:31], XD[0:15]
XREADY(E)
DOUT
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high.
D. XWE1 is used in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 7-30. Example Write Access
XTIMING register parameters used for this example :
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
83
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
N/A(1)
0
0
≥ 1
≥ 0
≥ 0
(1) N/A = Not applicable (or “Don’t care”) for this example
Copyright © 2021 Texas Instruments Incorporated
84
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
PARAMETER
MIN
MAX
1
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–1
0.5
1.5
0.5
0.5
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
ns
– 1.5
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus, except XA0, which remains high. This
includes alignment cycles.
7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
MIN
MAX
(LR + AR) – 16 (1)
AR – 14 (1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
14
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 7-2.
7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
MIN
12
6
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
ns
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
te(XRDYsynchH)
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
12
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 7-31:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
MIN
11
MAX UNIT
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
ns
ns
6
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
te(XRDYAsynchH)
3
ns
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
11
0
ns
ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
85
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
WS (Synch)
(C)
(A) (B)
Active
Lead
Trail
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0 XZCS6, XZCS7
t
d(XCOH-XA)
XA[0:19]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
(D)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:31], XD[0:15]
DIN
t
su(XRDYsynchL)XCOHL
t
e(XRDYsynchH)
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
Legend:
(E)
(F)
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access (E) can be calculated as: D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM)
tsu(XRDYsynchL)XCOHL
–
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number: n = 1,
2, 3, and so forth.
Figure 7-31. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
3
≥ 1
1
0
N/A(1)
N/A(1)
N/A(1)
0 = XREADY
(Synch)
(1) N/A = “Don’t care” for this example
Copyright © 2021 Texas Instruments Incorporated
86
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
WS (Async)
Active
(A) (B)
Lead
Trail
(C)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
t
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
d(XCOH-XA)
XA[0:19]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
(D)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
DIN
XD[0:31], XD[0:15]
t
su(XRDYasynchL)XCOHL
t
e(XRDYasynchH)
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access can be calculated as: E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM)
tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
–
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 7-32. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 1
3
≥ 1
1
0
N/A(1)
N/A(1)
N/A(1)
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
87
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
PARAMETER
MIN
MAX
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
– 1
0.5
1.5
2
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE0, XWE1 low(3)
Delay time, XCLKOUT high/low to XWE0, XWE1 high(3)
Delay time, XCLKOUT high to XR/ W low
2
1
Delay time, XCLKOUT high/low to XR/ W high
– 1
0
0.5
Enable time, data bus driven from XWE0, XWE1 low(3)
Delay time, data valid after XWE0, XWE1 active low(3)
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high(3)
Maximum time for DSP to release the data bus after XR/ W inactive high
td(XWEL-XD)
1
(1)
th(XA)XZCSH
th(XD)XWE
TW – 2 (2)
tdis(XD)XRNW
4
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
(2) TW = trail period, write access (see Table 7-2)
(3) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 8-27
MIN
12
6
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
ns
Earliest time XREADY (synchronous) can go high before the sampling
XCLKOUT edge
te(XRDYsynchH)
3
ns
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
12
0
ns
ns
7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
MIN
MAX UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
11
6
ns
ns
Earliest time XREADY (asynchronous) can go high before the sampling
XCLKOUT edge
te(XRDYasynchH)
3
ns
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
11
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 7-33:
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
Copyright © 2021 Texas Instruments Incorporated
88
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
WS (Synch)
(A) (B)
(C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK(D)
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0AND1, XZCS2,
XZCS6AND7
t
t
h(XRDYsynchH)XZCSH
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY (Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE + n –1) tc(XTIM)
tsu(XRDYsynchL)XCOH where n is the sample number: n = 1, 2, 3, and so forth.
–
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 7-33. Write With Synchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 1
3
≥ 1
0 = XREADY
(Synch)
(1) N/A = "Don't care" for this example.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
89
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
WS (Async)
Active
(A) (B)
(C)
Trail
Lead 1
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
(D)
XWE0, XWE1
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[31:0], XD[15:0]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
e(XRDYasynchH)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(D)
(E)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
E. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE -3 + n) tc(XTIM)
tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
–
F. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 7-34. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example :
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 1
3
≥ 1
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
Copyright © 2021 Texas Instruments Incorporated
90
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.6.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-
impedance mode.
On a reset ( XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XZCS6
XZCS7
XD[31:0], XD[15:0]
XWE0, XWE1, XRD
XR/ W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
91
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) (1) (2)
MIN
MAX
4tc(XTIM) + 30
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
td(HL-HAL)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
5tc(XTIM) + 30
ns
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
3tc(XTIM) + 30
ns
4tc(XTIM) + 30
ns
Delay time, XHOLD low to XHOLDA low
4tc(XTIM) + 2tc(XCO) + 30
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
XR/W
High-Impedance
XZCS0, XZCS6, XZCS7
Valid
XA[19:0]
Valid
High-Impedance
XD[31:0], XD[15:0]
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 7-35. External Interface Hold Waveform
Copyright © 2021 Texas Instruments Incorporated
92
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.9.6.9.2 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) (1) (2) (3)
MIN
MAX
UNIT
Delay time, XHOLD low to Hi-Z on all address, data, and
control
td(HL-HiZ)
4tc(XTIM) + tc(XCO) + 30
ns
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
4tc(XTIM) + 2tc(XCO) + 30
4tc(XTIM) + 30
ns
ns
ns
6tc(XTIM) + 30
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
XCLKOUT
(1/2 XTIMCLK)
t
d(HL-HAL)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HiZ)
t
d(HH-BV)
XR/W,
XZCS0,
XZCS6,
XZCS7
High-Impedance
High-Impedance
High-Impedance
Valid
XA[19:0]
Valid
XD[0:31]XD[15:0]
Valid
(B)
(A)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 7-36. XHOLD/ XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
93
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.9.7 Flash Timing
7.9.7.1 Flash Endurance for A and S Temperature Material (1)
ERASE/PROGRAM
MIN
TYP
MAX
UNIT
TEMPERATURE
0°C to 85°C (ambient)
0°C to 85°C (ambient)
Nf
Flash endurance for the array (write/erase cycles)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.9.7.2 Flash Endurance for Q Temperature Material (1)
ERASE/PROGRAM
TEMPERATURE
MIN
TYP
MAX
UNIT
Nf
Flash endurance for the array (write/erase cycles)
–40°C to 125°C (ambient)
–40°C to 125°C (ambient)
20000
50000
cycles
write
NOTP OTP endurance for the array (write cycles)
1
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
7.9.7.3 Flash Parameters at 150-MHz SYSCLKOUT
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
16-Bit Word
32K Sector
16K Sector
32K Sector
16K Sector
32K Sector
16K Sector
50
1000
500
2
μs
ms
ms
Program
Time(3)
2000(2)
2000(2)
12(2)
Erase Time(1)
Erase Time(1)
Q grade
s
s
2
12(2)
2
15(2)
A, S grade
2
15(2)
Erase
75
35
180
20
mA
mA
mA
mA
VDD3VFL current consumption during the Erase/Program
cycle
(4)
IDD3VFLP
Program
(4)
IDDP
VDD current consumption during Erase/Program cycle
VDDIO current consumption during Erase/Program cycle
(4)
IDDIOP
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Maximum flash parameter mentioned are for the first 100 program and erase cycles.
(3) Program time is at the maximum device frequency. The programming time indicated in this table is applicable only when all the
required code/data is available in the device RAM, ready for programming. Program time includes overhead of the flash state machine
but does not include the time to transfer the following into RAM:
•
•
•
the code that uses flash API to program the flash
the Flash API itself
Flash data to be programmed
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure VMIN on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board
(during flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands
placed during the programming process.
7.9.7.4 Flash/OTP Access Timing
PARAMETER
MIN
37
MAX UNIT
ta(fp)
ta(fr)
Paged Flash access time
Random Flash access time
ns
ns
37
Copyright © 2021 Texas Instruments Incorporated
94
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
PARAMETER
MIN
MAX UNIT
ta(OTP)
OTP access time
60
ns
7.9.7.5 Flash Data Retention Duration
PARAMETER
TEST CONDITIONS
TJ = 55°C
MIN
15
MAX UNIT
tretention
Data retention duration
years
Table 7-4. Minimum Required Flash/OTP Wait-States at Different Frequencies
SYSCLKOUT (MHz)
SYSCLKOUT (ns)
PAGE WAIT-STATE
RANDOM WAIT-STATE(1)
OTP WAIT-STATE
150
120
100
75
6.67
8.33
10
5
4
3
2
1
1
1
1
1
5
4
3
2
1
1
1
1
1
8
7
5
4
2
1
1
1
1
13.33
20
50
30
33.33
40
25
15
66.67
250
4
(1) Page and random wait-state must be ≥ 1.
The equations to compute the Flash page wait-state and random wait-state in Table 7-4 are as follows:
ta(f@p)
ǒ Ǔ* 1 round up to the next highest integer or 1, whichever is larger
Flash Page Wait State
+
+
ƪ ƫ
tc(SCO)
ta(f@r)
Flash Random Wait State
round up to the next highest integer or 1, whichever is larger
ǒ Ǔ* 1
ƪ ƫ
tc(SCO)
The equation to compute the OTP wait-state in Table 7-4 is as follows:
ta(OTP)
ǒ Ǔ* 1 round up to the next highest integer or 1, whichever is larger
OTP Wait State
+
ƪ ƫ
tc(SCO)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
95
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.10 On-Chip Analog-to-Digital Converter
7.10.1 ADC Electrical Characteristics (over recommended operating conditions) (1) (2)
PARAMETER
MIN
TYP
MAX
UNIT
DC SPECIFICATIONS (3)
Resolution
12
Bits
ADC clock
0.001
25
MHz
ACCURACY
1-12.5 MHz ADC clock (6.25 MSPS)
±1.5
±2
LSB
LSB
INL (Integral nonlinearity)
12.5-25 MHz ADC clock
(12.5 MSPS)
DNL (Differential nonlinearity)(4)
Offset error(5) (3)
±1
15
30
30
LSB
LSB
LSB
LSB
LSB
LSB
–15
–30
–30
Overall gain error with internal reference(6) (3)
Overall gain error with external reference(3)
Channel-to-channel offset variation
Channel-to-channel gain variation
ANALOG INPUT
±4
±4
Analog input voltage (ADCINx to ADCLO)(7)
0
3
5
V
ADCLO
–5
0
mV
pF
μA
Input capacitance
10
Input leakage current
±5
INTERNAL VOLTAGE REFERENCE (6)
VADCREFP - ADCREFP output voltage at the pin based on
internal reference
1.275
0.525
V
V
VADCREFM - ADCREFM output voltage at the pin based on
internal reference
Voltage difference, ADCREFP - ADCREFM
0.75
50
V
Temperature coefficient
PPM/°C
EXTERNAL VOLTAGE REFERENCE (6) (8)
ADCREFSEL[15:14] = 11b
ADCREFSEL[15:14] = 10b
ADCREFSEL[15:14] = 01b
1.024
1.500
2.048
V
V
V
VADCREFIN - External reference voltage input on ADCREFIN
pin 0.2% or better accurate reference recommended
AC SPECIFICATIONS
SINAD (100 kHz) Signal-to-noise ratio + distortion
SNR (100 kHz) Signal-to-noise ratio
THD (100 kHz) Total harmonic distortion
ENOB (100 kHz) Effective number of bits
SFDR (100 kHz) Spurious free dynamic range
67.5
68
dB
dB
–79
10.9
83
dB
Bits
dB
(1) Tested at 25 MHz ADCCLK.
(2) All voltages listed in this table are with respect to VSSA2
.
(3) ADC parameters for gain error and offset error are only specified if the ADC calibration routine is executed from the Boot ROM. See
Section 8.2.7.3 for more information.
(4) TI specifies that the ADC will have no missing codes.
(5) 1 LSB has the weighted value of 3.0/4096 = 0.732 mV.
(6) A single internal/external band gap reference sources both ADCREFP and ADCREFM signals, and hence, these voltages track
together. The ADC converter uses the difference between these two as its reference. The total gain error listed for the internal
reference is inclusive of the movement of the internal bandgap over temperature. Gain error over temperature for the external
reference option will depend on the temperature profile of the source used.
(7) Voltages above VDDA + 0.3 V or below VSS - 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin.
To avoid this, the analog inputs should be kept within these limits.
Copyright © 2021 Texas Instruments Incorporated
96
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
(8) TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
97
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.10.2 ADC Power-Up Control Bit Timing
ADC Power Up Delay
ADC Ready for Conversions
PWDNBG
PWDNREF
t
d(BGR)
PWDNADC
t
d(PWD)
Request for
ADC
Conversion
Figure 7-37. ADC Power-Up Control Bit Timing
7.10.2.1 ADC Power-Up Delays
PARAMETER(1)
MIN
TYP
MAX
UNIT
ms
Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3 register
(ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
td(BGR)
5
Delay time for power-down control to be stable. Bit delay time for band-gap reference
to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0) must be set to
1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3 register (PWDNADC)
must be set to 1 before any ADC conversions are initiated.
20
50
μs
td(PWD)
1
ms
(1) Timings maintain compatibility to the 281x ADC module. The 2833x/2823x ADC also supports driving all 3 bits at the same time and
waiting td(BGR) ms before first conversion.
7.10.2.2 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) (1) (2)
ADC OPERATING MODE
CONDITIONS
BG and REF enabled
VDDA18
VDDA3.3
UNIT
•
•
Mode A (Operational Mode):
30
2
mA
PWD disabled
•
•
•
ADC clock enabled
BG and REF enabled
PWD enabled
Mode B:
Mode C:
Mode D:
9
5
5
0.5
20
15
mA
μA
μA
•
•
•
ADC clock enabled
BG and REF disabled
PWD enabled
•
•
•
ADC clock disabled
BG and REF disabled
PWD enabled
(1) Test Conditions:
SYSCLKOUT = 150 MHz
ADC module clock = 25 MHz
ADC performing a continuous conversion of all 16 channels in Mode A
(2) VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO
.
Copyright © 2021 Texas Instruments Incorporated
98
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
R
on
Switch
R
s
ADCIN0
1 kΩ
C
C
h
p
Source
Signal
ac
10 pF
1.64 pF
28x DSP
Typical Values of the Input Circuit Components:
Switch Resistance (R ):
on
Sampling Capacitor (C ):
1 kΩ
1.64 pF
h
Parasitic Capacitance (C ): 10 pF
p
Source Resistance (R ):
s
50 Ω
Figure 7-38. ADC Analog Input Impedance Model
7.10.3 Definitions
Reference Voltage
The on-chip ADC has a built-in reference, which provides the reference voltages for the ADC.
Analog Inputs
The on-chip ADC consists of 16 analog inputs, which are sampled either one at a time or two channels at a time.
These inputs are software-selectable.
Converter
The on-chip ADC uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low
power consumption.
Conversion Modes
The conversion can be performed in two different conversion modes:
•
•
Sequential sampling mode (SMODE = 0)
Simultaneous sampling mode (SMODE = 1)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
99
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.10.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx).
The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC
signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on every Sample/Hold pulse.
The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are
set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled at every
falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock
wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2
Sample n+1
Analog Input on
Sample n
Channel Ax or Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschx_n+1
t
dschx_n
ADC Event Trigger from
ePWM or Other Sources
t
SH
Figure 7-39. Sequential Sampling Mode (Single-Channel) Timing
7.10.4.1 Sequential Sampling Mode Timing
AT 25-MHz
ADC CLOCK,
SAMPLE n
SAMPLE n + 1
REMARKS
tc(ADCCLK) = 40 ns
Delay time from event trigger to
sampling
td(SH)
2.5tc(ADCCLK)
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
Acqps value = 0-15
ADCTRL1[8:11]
tSH
40 ns with Acqps = 0
160 ns
Delay time for first result to appear
in Result register
td(schx_n)
td(schx_n+1)
4tc(ADCCLK)
Delay time for successive results to
appear in Result register
(2 + Acqps) *
tc(ADCCLK)
80 ns
Copyright © 2021 Texas Instruments Incorporated
100 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.10.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to
A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external
ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected channels on every Sample/
Hold pulse. The conversion time and latency of the result register update are explained below. The ADC interrupt
flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled
simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed
to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Note
In simultaneous mode, the ADCIN channel pair select must be A0/B0, A1/B1, ..., A7/B7, and not in
other combinations (such as A1/B3, and so on).
Sample n
Sample n+2
Sample n+1
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
t
dschA0_n+1
t
SH
ADC Event Trigger from
ePWM or Other Sources
t
t
dschA0_n
dschB0_n+1
t
dschB0_n
Figure 7-40. Simultaneous Sampling Mode Timing
7.10.5.1 Simultaneous Sampling Mode Timing
AT 25-MHz
SAMPLE n
SAMPLE n + 1
ADC CLOCK,
REMARKS
tc(ADCCLK) = 40 ns
Delay time from event trigger to
sampling
td(SH)
2.5tc(ADCCLK)
Sample/Hold width/Acquisition
Width
(1 + Acqps) *
tc(ADCCLK)
Acqps value = 0-15
ADCTRL1[8:11]
tSH
40 ns with Acqps = 0
160 ns
Delay time for first result to
appear in Result register
td(schA0_n)
td(schB0_n )
td(schA0_n+1)
td(schB0_n+1 )
4tc(ADCCLK)
5tc(ADCCLK)
Delay time for first result to
appear in Result register
200 ns
Delay time for successive results
to appear in Result register
(3 + Acqps) * tc(ADCCLK)
(3 + Acqps) * tc(ADCCLK)
120 ns
Delay time for successive results
to appear in Result register
120 ns
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 101
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
7.10.6 Detailed Descriptions
Integral Nonlinearity
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as
level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular
code to the true straight line between these two points.
Differential Nonlinearity
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A
differential nonlinearity error of less than ±1 LSB ensures no missing codes.
Zero Offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value one-half LSB above negative full scale. The last
transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the
deviation of the actual difference between first and last code transitions and the ideal difference between first
and last code transitions.
Signal-to-Noise Ratio + Distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
(
)
SINAD * 1.76
N +
6.02
it is possible to get a measure of performance expressed as N, the effective number of
bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated
directly from its measured SINAD.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input
signal and is expressed as a percentage or in decibels.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.
Copyright © 2021 Texas Instruments Incorporated
102 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
7.11 Migrating Between F2833x Devices and F2823x Devices
The principal difference between these two devices is the absence of the floating-point unit (FPU) in the F2823x
devices. This section describes how to build an application for each:
•
For F2833x devices:
– Code Composer Studio 3.3 with Service Release 9 or later is required for debug support of C28x +
floating-point devices.
– Use -v28 --float_support = fpu32 compiler options. The --float_support option is available in compiler
v5.0.2 or later. In Code Composer Studio, the --float_support option is located on the advanced tab of the
compiler options (Project → Build_Options → Compiler → Advanced tab).
– Include the compiler’s run-time support library for native 32-bit floating-point. For example, use
rts2800_fpu32.lib for C code or rts2800_fpu32_eh.lib for C++ code.
– Consider using the C28x FPU Fast RTS Library for high-performance floating-point math functions such
as sin, cos, div, sqrt, and atan. The Fast RTS library should be linked in before the normal run-time
support library.
•
For F2823x devices:
– Either leave off the --float_support switch or use -v28 --float_support=none
– Include the appropriate run-time support library for fixed point code. For example, use rts2800_ml.lib for C
code or rts2800_ml_eh.lib for C++ code.
– Consider using the C28x IQmath library - A Virtual Floating Point Engine to achieve a performance boost
from math functions such as sin, cos, div, sqrt, and atan.
Code built in this manner will also run on F2833x devices, but it will not make use of the on-chip floating-
point unit.
In either case, to allow for quick portability between native floating-point and fixed-point devices, TI suggests
writing your code using the IQmath macro language described in C28x IQMath Library.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 103
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8 Detailed Description
8.1 Brief Descriptions
8.1.1 C28x CPU
The F2833x (C28x+FPU)/F2823x (C28x) family is a member of the TMS320C2000™ digital signal controller
(DSC) platform. The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing
C28x DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient
C/C++ engine, enabling users to develop their system control software in a high-level language. It also enables
math algorithms to be developed using C/C++. The device is as efficient at DSP math tasks as it is at system
control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second
processor in many systems. The 32 × 32-bit MAC 64-bit processing capabilities enable the controller to handle
higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context
save of critical registers, resulting in a device that is capable of servicing many asynchronous events with
minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This
pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special
branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional
operations further improve performance.
The F2823x family is also a member of the TMS320C2000™ digital signal controller (DSC) platform but it does
not include a floating-point unit (FPU).
8.1.2 Memory Bus (Harvard Bus Architecture)
As with many DSC type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write buses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to
the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be
summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
8.1.3 Peripheral Bus
To enable migration of peripherals between various TI DSC family of devices, the 2833x/2823x devices adopt a
peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various buses that
make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and
associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit
accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral
frame 1). The third version supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).
8.1.4 Real-Time JTAG and Analysis
The 2833x/2823x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices support
real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified
while the processor is running and executing code and servicing interrupts. The user can also single step
through nontime-critical code while enabling time-critical interrupts to be serviced without interference. The
device implements the real-time mode in hardware within the CPU. This is a feature unique to the 2833x/2823x
device, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of
hardware breakpoint or data/address watch-points and generate various user-selectable break events when a
match occurs.
Copyright © 2021 Texas Instruments Incorporated
104 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.1.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The chip-
select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be programmed
with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
8.1.6 Flash
The F28335/F28333/F28235 devices contain 256K × 16 of embedded flash memory, segregated into eight 32K
× 16 sectors. The F28334/F28234 devices contain 128K × 16 of embedded flash memory, segregated into eight
16K × 16 sectors. The F28332/F28232 devices contain 64K × 16 of embedded flash, segregated into four 16K ×
16 sectors. All the devices also contain a single 1K × 16 of OTP memory at address range 0x380400–0x3807FF.
The user can individually erase, program, and validate a flash sector while leaving other sectors untouched.
However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/
program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher
performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute
code or store data information. Note that addresses 0x33FFF0–0x33FFF5 are reserved for data variables and
should not contain program code.
Note
The Flash and OTP wait-states can be configured by the application. This allows applications running
at slower frequencies to configure the flash to use fewer wait-states.
Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options
register. With this mode enabled, effective performance of linear code execution will be much faster
than the raw performance indicated by the wait-state configuration alone. The exact performance gain
when using the Flash pipeline mode is application-dependent.
For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the
TMS320x2833x, 2823x system control and interrupts reference guide.
8.1.7 M0, M1 SARAMs
All 2833x/2823x devices contain these two blocks of single access memory, each 1K × 16 in size. The stack
pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on
C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute
code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified
memory map to the programmer. This makes for easier programming in high-level languages.
8.1.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
The F28335/F28333/F28235 and F28334/F28234 each contain 32K × 16 of single-access RAM, divided into
8 blocks (L0–L7 with 4K each). The F28332/F28232 contain 24K × 16 of single-access RAM, divided into
6 blocks (L0–L5 with 4K each). Each block can be independently accessed to minimize CPU pipeline stalls.
Each block is mapped to both program and data space. L4, L5, L6, and L7 are DMA-accessible.
8.1.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal Flash/
ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related
algorithms.
Table 8-1. Boot Mode Selection
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
MODE(1)
F
E
1
1
1
1
1
1
1
0
Jump to Flash
SCI-A boot
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 105
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-1. Boot Mode Selection (continued)
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
MODE(1)
D
C
B
A
9
8
7
6
5
4
3
2
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
SPI-A boot
I2C-A boot
eCAN-A boot
McBSP-A boot
Jump to XINTF x16
Jump to XINTF x32
Jump to OTP
Parallel GPIO I/O boot
Parallel XINTF boot
Jump to SARAM
Branch to check boot mode
Branch to Flash, skip ADC calibration
Branch to SARAM, skip ADC
calibration
1
0
0
0
0
0
0
0
1
0
Branch to SCI, skip ADC calibration
(1) All four GPIO pins have an internal pullup.
Note
Modes 0, 1, and 2 in Table 8-1 are for TI debug only. Skipping the ADC calibration function in an
application will cause the ADC to operate outside of the stated specifications
Copyright © 2021 Texas Instruments Incorporated
106 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.1.9.1 Peripheral Pins Used by the Bootloader
Table 8-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if
these conflict with any of the peripherals you would like to use in your application.
Table 8-2. Peripheral Bootload Pins
BOOTLOADER
PERIPHERAL LOADER PINS
SCIRXDA (GPIO28)
SCITXDA (GPIO29)
SCI-A
SPI-A
SPISIMOA (GPIO16)
SPISOMIA (GPIO17)
SPICLKA (GPIO18)
SPISTEA (GPIO19)
SDAA (GPIO32)
SCLA (GPIO33)
I2C
CANRXA (GPIO30)
CANTXA (GPIO31)
CAN
MDXA (GPIO20)
MDRA (GPIO21)
MCLKXA (GPIO22)
MFSXA (GPIO23)
MCLKRA (GPIO7)
MFSRA (GPIO5)
McBSP
8.1.10 Security
The devices support high levels of security to protect the user firmware from being reverse engineered. The
security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One
code security module (CSM) is used to protect the flash/OTP and the L0/L1/L2/L3 SARAM blocks. The security
feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code
from external memory or trying to boot-load some undesirable software that would export the secure memory
contents. To enable access to the secure blocks, the user must write the correct 128-bit KEY value, which
matches the value stored in the password locations within the Flash.
In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized
users from stepping through secure code. Any code or data access to flash, user OTP, L0, L1, L2, or L3 memory
while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of
secure code, while maintaining the CSM protection against secure memory reads, the user must write the
correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the
password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still
be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value
does not need to match.
When initially debugging a device with the password locations in flash programmed (that is, secured), the
emulator takes some time to take control of the CPU. During this time, the CPU will start running and may
execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and
cause the emulator connection to be cut. Two solutions to this problem exist:
1. The first is to use the Wait-In-Reset emulation mode, which will hold the device in reset until the emulator
takes control. The emulator must support this mode for this option.
2. The second option is to use the “Branch to check boot mode” boot option. This will sit in a loop and
continuously poll the boot mode select pins. The user can select this boot mode and then exit this mode once
the emulator is connected by re-mapping the PC to another address or by changing the boot mode selection
pin to the desired boot mode.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 107
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Note
•
•
When the code-security passwords are programmed, all addresses from 0x33FF80 to 0x33FFF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
If the code security feature is not used, addresses 0x33FF80 to 0x33FFEF may be used for code
or data. Addresses 0x33FFF0 to 0x33FFF5 are reserved for data and should not contain program
code.
The 128-bit password (at 0x33FFF8 to 0x33FFFF) must not be programmed to zeros. Doing so would
permanently lock the device.
Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR
FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS
STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS
FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
Copyright © 2021 Texas Instruments Incorporated
108 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.1.11 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the 2833x/2823x, 58 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes
eight CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond
to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can
be enabled or disabled within the PIE block.
8.1.12 External Interrupts (XINT1–XINT7, XNMI)
The devices support eight masked external interrupts (XINT1–XINT7, XNMI). XNMI can be connected to the
INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative
and positive edge triggering and can also be enabled or disabled (including the XNMI). XINT1, XINT2, and XNMI
also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is detected. This
counter can be used to accurately time-stamp the interrupt. Unlike the 281x devices, there are no dedicated pins
for the external interrupts. XINT1 XINT2, and XNMI interrupts can accept inputs from GPIO0–GPIO31 pins.
XINT3–XINT7 interrupts can accept inputs from GPIO32–GPIO63 pins.
8.1.13 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A
PLL is provided supporting up to 10 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in
software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to
Section 7.9.4.4 for timing details. The PLL block can be set in bypass mode.
8.1.14 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
8.1.15 Peripheral Clocking
The clocks to each individual peripheral can be enabled or disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) and the ADC
blocks can be scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from
increasing CPU clock speeds.
8.1.16 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog
timer will wake the processor from IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible
power consumption mode. A reset or external signal can wake the device from this mode.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 109
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash Waitstate Registers
Flash:
XINTF:
DMA
External Interface Registers
DMA Registers
Timers:
CSM:
ADC:
eCAN:
GPIO:
ePWM:
eCAP:
eQEP:
SYS:
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC Result Registers (dual-mapped)
PF1:
PF2:
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
SPI:
ADC:
I2C:
XINT
PF3:
McBSP
ePWM:
Multichannel Buffered Serial Port Registers
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
8.1.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with GPIO signals. This enables the user to use a pin as GPIO if
the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can
individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also
select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can
also be used to bring the device out of specific low-power modes.
8.1.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/
BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS or SYS/BIOS is not being used, CPU-Timer
2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-
Timer 0 is also for general use and is connected to the PIE block.
Copyright © 2021 Texas Instruments Incorporated
110
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.1.20 Control Peripherals
The 2833x/2823x devices support the following peripherals which are used for embedded control and
communication:
ePWM:
The enhanced PWM peripheral supports independent and complementary PWM generation, adjustable dead-
band generation for leading and trailing edges, latched and cycle-by-cycle trip mechanism. Some of the PWM
pins support HRPWM features. The ePWM registers are supported by the DMA to reduce the overhead for
servicing this peripheral.
eCAP:
eQEP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture
unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous
edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-and-hold units for
simultaneous sampling. The ADC registers are supported by the DMA to reduce the overhead for servicing this
peripheral.
8.1.21 Serial Port Peripherals
The devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time-stamping of messages, and is
compliant with ISO 11898-1 (CAN 2.0B).
McBSP:
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality codecs for modem
applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported
by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module can be
configured as an SPI as required.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSC and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI. On the 2833x/2823x, the
SPI contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
I2C:
The serial communications interface is a 2-wire asynchronous serial port, commonly known as UART. The SCI
contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between a DSC and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSC
through the I2C module. On the 2833x/2823x, the I2C contains a 16-level receive and transmit FIFO for reducing
interrupt servicing overhead.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
111
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2 Peripherals
The integrated peripherals of the 2833x and 2823x devices are described in the following subsections:
•
•
•
•
•
•
•
•
•
•
•
•
•
6-channel Direct Memory Access (DMA)
Three 32-bit CPU-Timers
Up to six enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6)
Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)
Up to two enhanced QEP modules (eQEP1, eQEP2)
Enhanced analog-to-digital converter (ADC) module
Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)
One serial peripheral interface (SPI) module (SPI-A)
Inter-integrated circuit (I2C) module
Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules
Digital I/O and shared pin functions
External Interface (XINTF)
8.2.1 DMA Overview
Features:
•
•
6 channels with independent PIE interrupts
Trigger sources:
– ePWM SOCA/SOCB
– ADC Sequencer 1 and Sequencer 2
– McBSP-A and McBSP-B transmit and receive logic
– XINT1–7 and XINT13
– CPU timers
– Software
•
Data sources and destinations:
– L4–L7 16K × 16 SARAM
– All XINTF zones
– ADC Memory Bus mapped RESULT registers
– McBSP-A and McBSP-B transmit and receive buffers
– ePWM registers
•
•
Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
Copyright © 2021 Texas Instruments Incorporated
112
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
CPU bus
INT7
ADC
CPU
PF0
I/F
External
interrupts
CPU
timers
ADC
control
and
ADC
RESULT
PIE
ADC
PF2
I/F
ADC
DMA
PF0
I/F
registers RESULT
registers
L4
SARAM
(4Kx16)
L4
I/F
CPU
L5
SARAM
(4Kx16)
McBSP A
L5
I/F
Event
triggers
DMA
6-ch
McBSP B
ePWM/
HRPWM(A)
registers
PF3
I/F
L6
SARAM
(4Kx16)
L6
I/F
L7
SARAM
(4Kx16)
L7
I/F
DMA bus
A. The ePWM and HRPWM registers must be remapped to PF3 (through bit 0 of the MAPCNF register) before they can be accessed by the
DMA. The ePWM or HRPWM connection to DMA is not present in silicon revision 0.
Figure 8-1. DMA Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
113
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
There are three 32-bit CPU-timers on the devices (CPU-Timer 0, CPU-Timer 1, CPU-Timer 2).
CPU-Timer 2 is reserved for DSP/BIOS or SYS/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user
applications. These timers are different from the timers that are present in the ePWM modules.
Note
If the application is not using DSP/BIOS or SYS/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 8-2. CPU-Timers
The timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in Figure 8-3.
INT1
TINT0
PIE
CPU-TIMER 0
to
INT12
28x
CPU
TINT1
CPU-TIMER 1
INT13
INT14
XINT13
CPU-TIMER 2
(Reserved for
DSP/BIOS or SYS/BIOS)
TINT2
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 8-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value
in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in
Table 8-3 are used to configure the timers. For more information, see the TMS320x2833x, 2823x system control
and interrupts reference guide .
Copyright © 2021 Texas Instruments Incorporated
114
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-3. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
SIZE (x16)
DESCRIPTION
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
40
CPU-Timer 0, Counter Register
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
0x0C12
0x0C13
0x0C14
0x0C15
0x0C16
0x0C17
0x0C18 – 0x0C3F
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
Reserved
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
115
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.3 Enhanced PWM Modules
The 2833x/2823x devices contain up to six enhanced PWM (ePWM) modules (ePWM1 to ePWM6). Figure 8-4
shows the time-base counter synchronization scheme 3. Figure 8-5 shows the signal interconnections with the
ePWM.
Table 8-4 shows the complete ePWM register set per module and Table 8-5 shows the remapped register
configuration.
eCAP4
EPWM1SYNCI
GPIO
ePWM1
MUX
EPWM1SYNCO
SYNCI
eCAP1
EPWM4SYNCI
ePWM4
EPWM2SYNCI
ePWM2
EPWM4SYNCO
EPWM2SYNCO
EPWM5SYNCI
ePWM5
EPWM3SYNCI
ePWM3
EPWM5SYNCO
EPWM3SYNCO
EPWM6SYNCI
ePWM6
A. By default, ePWM and HRPWM registers are mapped to Peripheral Frame 1 (PF1). Table 8-4 shows this configuration. To re-map the
registers to Peripheral Frame 3 (PF3) to enable DMA access, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to
1. Table 8-5 shows the remapped configuration.
Figure 8-4. Time-Base Counter Synchronization Scheme 3
Table 8-4. ePWM Control and Status Registers (Default Configuration in PF1)
SIZE (x16) /
#SHADOW
NAME
ePWM1 ePWM2 ePWM3 ePWM4
ePWM5
ePWM6
DESCRIPTION
TBCTL
TBSTS
0x6800
0x6801
0x6802
0x6840
0x6841
0x6842
0x6880
0x6881
0x6882
0x68C0
0x68C1
0x68C2
0x6900
0x6901
0x6902
0x6940
0x6941
0x6942
1 / 0
Time Base Control Register
Time Base Status Register
1 / 0
TBPHSH
R
Time Base Phase HRPWM Register
1 / 0
TBPHS
TBCTR
TBPRD
CMPCTL
0x6803
0x6804
0x6805
0x6807
0x6843
0x6844
0x6845
0x6847
0x6848
0x6883
0x6884
0x6885
0x6887
0x6888
0x68C3
0x68C4
0x68C5
0x68C7
0x68C8
0x6903
0x6904
0x6905
0x6907
0x6908
0x6943
0x6944
0x6945
0x6947
0x6948
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
CMPAHR 0x6808
Copyright © 2021 Texas Instruments Incorporated
116
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-4. ePWM Control and Status Registers (Default Configuration in PF1) (continued)
SIZE (x16) /
#SHADOW
NAME
CMPA
ePWM1 ePWM2 ePWM3 ePWM4
ePWM5
ePWM6
DESCRIPTION
0x6809
0x680A
0x680B
0x6849
0x684A
0x684B
0x6889
0x688A
0x688B
0x68C9
0x68CA
0x68CB
0x6909
0x690A
0x690B
0x6949
0x694A
0x694B
1 / 1
Counter Compare A Register Set
Counter Compare B Register Set
CMPB
1 / 1
AQCTLA
Action Qualifier Control Register For
Output A
1 / 0
AQCTLB
0x680C
0x684C
0x688C 0x68CC
0x688D 0x68CD
0x690C
0x694C
Action Qualifier Control Register For
Output B
1 / 0
1 / 0
1 / 1
1 / 1
1 / 0
AQSFRC 0x680D
0x684D
0x684E
0x690D
0x690E
0x694D
0x694E
Action Qualifier Software Force Register
AQCSFR 0x680E
C
0x688E
0x68CE
Action Qualifier Continuous S/W Force
Register Set
DBCTL
DBRED
0x680F
0x6810
0x684F
0x6850
0x688F
0x6890
0x68CF
0x68D0
0x690F
0x6910
0x694F
0x6950
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
Count Register
DBFED
0x6811
0x6851
0x6891
0x68D1
0x6911
0x6951
Dead-Band Generator Falling Edge Delay
Count Register
1 / 0
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
ETSEL
ETPS
0x6812
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6852
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6892
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x68D2
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x6912
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6920
0x6952
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
0x6960
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Trip Zone Select Register(1)
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETFLG
ETCLR
ETFRC
PCCTL
0x689C 0x68DC
0x689D 0x68DD
0x689E
0x68A0
0x68DE
0x68E0
HRCNFG 0x6820
(1) Registers that are EALLOW protected.
Table 8-5. ePWM Control and Status Registers (Remapped Configuration in PF3 - DMA-Accessible)
SIZE (x16) /
#SHADOW
NAME
ePWM1 ePWM2 ePWM3 ePWM4
ePWM5
ePWM6
DESCRIPTION
TBCTL
TBSTS
0x5800
0x5801
0x5802
0x5840
0x5841
0x5842
0x5880
0x5881
0x5882
0x58C0
0x58C1
0x58C2
0x5900
0x5901
0x5902
0x5940
0x5941
0x5942
1 / 0
Time Base Control Register
Time Base Status Register
1 / 0
TBPHSH
R
Time Base Phase HRPWM Register
1 / 0
TBPHS
TBCTR
TBPRD
CMPCTL
0x5803
0x5804
0x5805
0x5807
0x5843
0x5844
0x5845
0x5847
0x5848
0x5849
0x584A
0x584B
0x5883
0x5884
0x5885
0x5887
0x5888
0x5889
0x588A
0x588B
0x58C3
0x58C4
0x58C5
0x58C7
0x58C8
0x58C9
0x58CA
0x58CB
0x5903
0x5904
0x5905
0x5907
0x5908
0x5909
0x590A
0x590B
0x5943
0x5944
0x5945
0x5947
0x5948
0x5949
0x594A
0x594B
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
Time Base Phase Register
Time Base Counter Register
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
Counter Compare B Register Set
CMPAHR 0x5808
CMPA
0x5809
0x580A
0x580B
CMPB
AQCTLA
Action Qualifier Control Register For
Output A
1 / 0
AQCTLB
0x580C
0x584C
0x584D
0x588C 0x58CC
0x588D 0x58CD
0x590C
0x590D
0x594C
0x594D
Action Qualifier Control Register For
Output B
1 / 0
1 / 0
AQSFRC 0x580D
Action Qualifier Software Force Register
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
117
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-5. ePWM Control and Status Registers (Remapped Configuration in PF3 - DMA-Accessible)
(continued)
SIZE (x16) /
#SHADOW
NAME
ePWM1 ePWM2 ePWM3 ePWM4
ePWM5
ePWM6
DESCRIPTION
AQCSFR 0x580E
C
0x584E
0x588E
0x58CE
0x590E
0x594E
Action Qualifier Continuous S/W Force
Register Set
1 / 1
DBCTL
DBRED
0x580F
0x5810
0x584F
0x5850
0x588F
0x5890
0x58CF
0x58D0
0x590F
0x5910
0x594F
0x5950
1 / 1
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
Count Register
1 / 0
DBFED
0x5811
0x5851
0x5891
0x58D1
0x5911
0x5951
Dead-Band Generator Falling Edge Delay
Count Register
1 / 0
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
ETSEL
ETPS
0x5812
0x5814
0x5815
0x5816
0x5817
0x5818
0x5819
0x581A
0x581B
0x581C
0x581D
0x581E
0x5852
0x5854
0x5855
0x5856
0x5857
0x5858
0x5859
0x585A
0x585B
0x585C
0x585D
0x585E
0x5860
0x5892
0x5894
0x5895
0x5896
0x5897
0x5898
0x5899
0x589A
0x589B
0x58D2
0x58D4
0x58D5
0x58D6
0x58D7
0x58D8
0x58D9
0x58DA
0x58DB
0x5912
0x5914
0x5915
0x5916
0x5917
0x5918
0x5919
0x591A
0x591B
0x591C
0x591D
0x591E
0x5920
0x5952
0x5954
0x5955
0x5956
0x5957
0x5958
0x5959
0x595A
0x595B
0x595C
0x595D
0x595E
0x5960
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Trip Zone Select Register(1)
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETFLG
ETCLR
ETFRC
PCCTL
0x589C 0x58DC
0x589D 0x58DD
0x589E
0x58A0
0x58DE
058E0
HRCNFG 0x5820
(1) Registers that are EALLOW protected.
Copyright © 2021 Texas Instruments Incorporated
118
Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Time−base (TB)
Sync
CTR=ZERO
CTR=CMPB
Disabled
in/out
select
Mux
TBPRD shadow (16)
TBPRD active (16)
EPWMxSYNCO
EPWMxSYNCI
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCTR
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
Phase
control
Event
trigger
and
interrupt
(ET)
EPWMxINT
TBPHS active (24)
CTR = CMPA
CTR = CMPB
CTR_Dir
EPWMxSOCA
EPWMxSOCB
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HRPWM
CMPA active (24)
EPWMA
EPWMB
EPWMxAO
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxBO
EPWMxTZINT
TZ1 to TZ6
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 8-5. ePWM Submodules Showing Critical Internal Signal Interconnections
8.2.4 High-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
Typically used when effective PWM resolution falls below approximately 9 or 10 bits. This occurs at PWM
frequencies greater than approximately 200 kHz when using a CPU/System clock of 100 MHz.
This capability can be used in both duty cycle and phase-shift control methods.
Finer time granularity control or edge positioning is controlled through extensions to the Compare A and
Phase registers of the ePWM module.
•
•
•
HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
119
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.5 Enhanced CAP Modules
The 2833x/2823x device contains up to six enhanced capture (eCAP) modules (eCAP1 to eCAP6). Figure 8-6
shows a functional block diagram of a module.
CTRPHS
(Phase Register - 32-bit)
APWM Mode
SYNCIn
CTR_OVF
OVF
CTR [0-31]
PRD [0-31]
CMP [0-31]
TSCTR
(Counter - 32-bit)
SYNCOut
PWM
Compare
Logic
Delta Mode
RST
32
CTR=PRD
CTR=CMP
CTR [0-31]
PRD [0-31]
32
32
LD1
CAP1
(APRD Active)
Polarity
Select
eCAPx
LD
APRD
Shadow
32
CMP [0-31]
32
Polarity
Select
LD2
32
CAP2
(ACMP Active)
LD
Event
Qualifier
ACMP
Shadow
Event
Prescale
32
Polarity
Select
LD3
LD4
32
32
CAP3
(APRD Shadow)
LD
CAP4
(ACMP Shadow)
Polarity
Select
LD
4
Capture Events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Control
Continuous/
One-Shot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Figure 8-6. eCAP Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
120 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK,
ECAP6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power
operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and
ECAP6ENCLK are set to low, indicating that the peripheral clock is off.
Table 8-6. eCAP Control and Status Registers
SIZE
(x16)
NAME
TSCTR
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
DESCRIPTION
Timestamp Counter
0x6A00
0x6A02
0x6A04
0x6A06
0x6A08
0x6A0A
0x6A20
0x6A22
0x6A24
0x6A26
0x6A28
0x6A2A
0x6A40
0x6A42
0x6A44
0x6A46
0x6A48
0x6A4A
0x6A60
0x6A62
0x6A64
0x6A66
0x6A68
0x6A6A
0x6A80
0x6A82
0x6A84
0x6A86
0x6A88
0x6A8A
0x6AA0
0x6AA2
0x6AA4
0x6AA6
0x6AA8
0x6AAA
2
2
2
2
2
2
CTRPHS
CAP1
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
0x6A0C- 0x6A2C-0x6
0x6A4C-
0x6A52
0x6A6C-
0x6A72
0x6A8C-0 0x6AAC-
Reserved
8
Reserved
0x6A12
0x6A14
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
A32
x6A92
0x6A94
0x6A95
0x6A96
0x6A97
0x6A98
0x6A99
0x6AB2
0x6AB4
0x6AB5
0x6AB6
0x6AB7
0x6AB8
0x6AB9
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
0x6A34
0x6A35
0x6A36
0x6A37
0x6A38
0x6A39
0x6A54
0x6A55
0x6A56
0x6A57
0x6A58
0x6A59
0x6A74
0x6A75
0x6A76
0x6A77
0x6A78
0x6A79
1
1
1
1
1
1
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
0x6A1A-
0x6A1F
0x6A3A-
0x6A3F
0x6A5A-
0x6A5F
0x6A7A-
0x6A7F
0x6A9A-0x 0x6ABA-
6A9F 0x6ABF
Reserved
6
Reserved
8.2.6 Enhanced QEP Modules
The device contains up to two enhanced quadrature encoder (eQEP) modules (eQEP1, eQEP2). Figure 8-7
shows the block diagram of the eQEP module.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 121
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
System Control
Registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
Capture
Unit
QCTMRLAT
QCPRDLAT
(QCAP)
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
16
PIE
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) Peripheral
Figure 8-7. eQEP Functional Block Diagram
Copyright © 2021 Texas Instruments Incorporated
122 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-7 provides a summary of the eQEP registers.
Table 8-7. eQEP Control and Status Registers
eQEP1
SIZE(x16)/
#SHADOW
eQEP1
ADDRESS
eQEP2
ADDRESS
NAME
REGISTER DESCRIPTION
QPOSCNT
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
0x6B40
0x6B42
0x6B44
0x6B46
0x6B48
0x6B4A
0x6B4C
0x6B4E
0x6B50
0x6B52
0x6B53
0x6B54
0x6B55
0x6B56
0x6B57
0x6B58
0x6B59
0x6B5A
0x6B5B
0x6B5C
0x6B5D
0x6B5E
0x6B5F
0x6B60
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
eQEP Position Counter
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
0x6B21 –
0x6B3F
0x6B61 –
0x6B7F
Reserved
31/0
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 123
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.7 Analog-to-Digital Converter (ADC) Module
A simplified functional block diagram of the ADC module is shown in Figure 8-8. The ADC module consists of a
12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
•
•
•
•
•
12-bit ADC core with built-in S/H
Analog input: 0.0 V to 3.0 V (Voltages above 3.0 V produce full-scale conversion results.)
Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12.5 MSPS
16 dedicated ADC channels. 8 channels multiplexed per Sample/Hold
Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be
programmed to select any 1 of 16 input channels
•
•
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (that
is, two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
– The digital value of the input analog voltage is derived by:
, when ADCIN £ ADCLO
, when ADCLO < ADCIN < 3 V
, when ADCIN ³ 3 V
Digital Value = 0
ADCIN - ADCLO
4096 ´
(
Digital Value = floor
(
3
Digital Value = 4095
•
Multiple triggers as sources for the start-of-conversion (SOC) sequence
– S/W - software immediate start
– ePWM start of conversion
– XINT2 ADC start of conversion
•
•
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS.
Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize
conversions.
•
•
SOCA and SOCB triggers can operate independently in dual-sequencer mode.
Sample-and-hold (S/H) acquisition time window has separate prescale control.
The ADC module in the 2833x/2823x devices has been enhanced to provide flexible interface to ePWM
peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80
ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel
modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although
there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 8-8
shows the block diagram of the ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the
choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded
mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion
is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the
system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This
gives increased resolution over traditional single-sampled conversion results.
Copyright © 2021 Texas Instruments Incorporated
124 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
SYSCLKOUT
System
Control Block
High-Speed
Prescaler
DSP
HALT
HSPCLK
ADCENCLK
Analog
MUX
Result Registers
70A8h
Result Reg 0
Result Reg 1
ADCINA0
S/H
ADCINA7
ADCINB0
ADCINB7
12-Bit
ADC
Module
Result Reg 7
Result Reg 8
70AFh
70B0h
S/H
Result Reg 15
70B7h
ADC Control Registers
S/W
S/W
EPWMSOCB
EPWMSOCA
GPIO/
SOC
SOC
Sequencer 2
Sequencer 1
XINT2_ADCSOC
Figure 8-8. Block Diagram of the ADC Module
To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible,
traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize
switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation
techniques must be used to isolate the ADC module power pins ( VDD1A18, VDD2A18 , VDDA2, VDDAIO) from the
digital supply.Figure 8-9 shows the ADC pin connections for the devices.
Note
1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module
is controlled by the high-speed peripheral clock (HSPCLK).
2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as
follows:
•
ADCENCLK: On reset, this signal will be low. While reset is active-low ( XRS) the clock to the
register will still function. This is necessary to make sure all registers and modes go into their
default reset state. The analog module, however, will be in a low-power inactive state. As soon
as reset goes high, then the clock to the registers will be disabled. When the user sets the
ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module
will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can
be used.
•
HALT: This mode only affects the analog module. It does not affect the registers. In this mode,
the ADC module goes into low-power mode. This mode also will stop the clock to the CPU,
which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 125
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Figure 8-9 shows the ADC pin-biasing for internal reference and Figure 8-10 shows the ADC pin-biasing for
external reference.
ADCINA[7:0]
ADCINB[7:0]
ADCLO
ADC 16-Channel Analog Inputs
Analog input 0−3 V with respect to ADCLO
Connect to analog ground
Connect to analog ground if internal reference is used
ADCREFIN
22 k
ADC External Current Bias Resistor ADCRESEXT
2.2 μF(A)
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
2.2 μF(A)
V
ADC Analog Power Pin (1.9 V/1.8 V)
ADC Analog Power Pin (1.9 V/1.8 V)
ADC Analog Ground Pin
DD1A18
V
DD2A18
V
V
SS1AGND
SS2AGND
ADC Analog Ground Pin
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
V
DDA2
V
SSA2
V
V
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
DDAIO
Reference I/O Power
SSAIO
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 8-9. ADC Pin Connections With Internal Reference
Copyright © 2021 Texas Instruments Incorporated
126 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
ADCINA[7:0]
ADC 16-Channel Analog Inputs
Analog input 0-3 V with respect to ADCLO
ADCINB[7:0]
ADCLO
ADCREFIN
Connect to Analog Ground
Connect to 1.500, 1.024, or 2.048-V precision source(D)
22 k
ADC External Current Bias Resistor ADCRESEXT
2.2 μF(A)
2.2 μF(A)
ADC Reference Positive Output
ADC Reference Medium Output
ADCREFP
ADCREFM
ADCREFP and ADCREFM should not
be loaded by external circuitry
VDD1A18
VDD2A18
VSS1AGND
VSS2AGND
ADC Analog Power Pin (1.9 V/1.8 V)
ADC Analog Power Pin (1.9 V/1.8 V)
ADC Analog Ground Pin
ADC Analog Ground Pin
VDDA2
VSSA2
ADC Analog Power Pin (3.3 V)
ADC Analog Ground Pin
VDDAIO
VSSAIO
ADC Analog Power Pin (3.3 V)
ADC Analog I/O Ground Pin
Reference I/O Power
A. TAIYO YUDEN LMK212BJ225MG-T or equivalent
B. External decoupling capacitors are recommended on all power pins.
C. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
D. External voltage on ADCREFIN is enabled by changing bits 15:14 in the ADC Reference Select register depending on the voltage used
on this pin. TI recommends TI part REF3020 or equivalent for 2.048-V generation. Overall gain accuracy will be determined by accuracy
of this voltage source.
Figure 8-10. ADC Pin Connections With External Reference
Note
The temperature rating of any recommended component must match the rating of the end product.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 127
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.7.1 ADC Connections if the ADC Is Not Used
It is recommended to keep the connections for the analog power pins, even if the ADC is not used. Following is a
summary of how the ADC pins should be connected, if the ADC is not used in an application:
•
•
•
•
•
•
•
•
VDD1A18/VDD2A18 – Connect to VDD
VDDA2, VDDAIO – Connect to VDDIO
VSS1AGND/VSS2AGND, VSSA2, VSSAIO – Connect to VSS
ADCLO – Connect to VSS
ADCREFIN – Connect to VSS
ADCREFP/ADCREFM – Connect a 100-nF cap to VSS
ADCRESEXT – Connect a 20-kΩ resistor (very loose tolerance) to VSS
ADCINAn, ADCINBn – Connect to VSS
.
When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings.
When the ADC module is used in an application, unused ADC input pins should be connected to analog ground
(VSS1AGND/VSS2AGND
)
Note
ADC parameters for gain error and offset error are specified only if the ADC calibration routine is
executed from the Boot ROM. See Section 8.2.7.3 for more information.
Copyright © 2021 Texas Instruments Incorporated
128 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.2.7.2 ADC Registers
The ADC operation is configured, controlled, and monitored by the registers listed in Table 8-8.
Table 8-8. ADC Registers (1)
NAME
ADDRESS(1) ADDRESS(2) SIZE (x16)
DESCRIPTION
ADCTRL1
0x7100
0x7101
0x7102
0x7103
0x7104
0x7105
0x7106
0x7107
0x7108
0x7109
0x710A
0x710B
0x710C
0x710D
0x710E
0x710F
0x7110
0x7111
0x7112
0x7113
0x7114
0x7115
0x7116
0x7117
0x7118
0x7119
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADC Control Register 1
ADC Control Register 2
ADCTRL2
ADCMAXCONV
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
ADCASEQSR
ADCRESULT0
ADCRESULT1
ADCRESULT2
ADCRESULT3
ADCRESULT4
ADCRESULT5
ADCRESULT6
ADCRESULT7
ADCRESULT8
ADCRESULT9
ADCRESULT10
ADCRESULT11
ADCRESULT12
ADCRESULT13
ADCRESULT14
ADCRESULT15
ADCTRL3
ADC Maximum Conversion Channels Register
ADC Channel Select Sequencing Control Register 1
ADC Channel Select Sequencing Control Register 2
ADC Channel Select Sequencing Control Register 3
ADC Channel Select Sequencing Control Register 4
ADC Auto-Sequence Status Register
0x0B00
0x0B01
0x0B02
0x0B03
0x0B04
0x0B05
0x0B06
0x0B07
0x0B08
0x0B09
0x0B0A
0x0B0B
0x0B0C
0x0B0D
0x0B0E
0x0B0F
ADC Conversion Result Buffer Register 0
ADC Conversion Result Buffer Register 1
ADC Conversion Result Buffer Register 2
ADC Conversion Result Buffer Register 3
ADC Conversion Result Buffer Register 4
ADC Conversion Result Buffer Register 5
ADC Conversion Result Buffer Register 6
ADC Conversion Result Buffer Register 7
ADC Conversion Result Buffer Register 8
ADC Conversion Result Buffer Register 9
ADC Conversion Result Buffer Register 10
ADC Conversion Result Buffer Register 11
ADC Conversion Result Buffer Register 12
ADC Conversion Result Buffer Register 13
ADC Conversion Result Buffer Register 14
ADC Conversion Result Buffer Register 15
ADC Control Register 3
ADCST
ADC Status Register
0x711A –
0x711B
Reserved
2
ADCREFSEL
ADCOFFTRIM
0x711C
0x711D
1
1
ADC Reference Select Register
ADC Offset Trim Register
0x711E –
0x711F
Reserved
2
(1) The registers in this column are Peripheral Frame 2 Registers.
(2) The ADC result registers are dual mapped. Locations in Peripheral Frame 2 (0x7108–0x7117) are 2 wait-states and left justified.
Locations in Peripheral frame 0 space (0x0B00–0x0B0F) are 1 wait-state for CPU accesses and 0 wait state for DMA accesses and
right justified. During high speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results
to user memory.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 129
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.7.3 ADC Calibration
The ADC_cal() routine is programmed into TI reserved OTP memory by the factory. The boot ROM automatically
calls the ADC_cal() routine to initialize the ADCREFSEL and ADCOFFTRIM registers with device specific
calibration data. During normal operation, this process occurs automatically and no action is required by the
user.
If the boot ROM is bypassed by Code Composer Studio during the development process, then ADCREFSEL and
ADCOFFTRIM must be initialized by the application. Methods for calling the ADC_cal() routine from an
application are described in the TMS320x2833x, F2823x Analog-to-Digital Converter (ADC) module reference
guide.
CAUTION
FAILURE TO INITIALIZE THESE REGISTERS WILL CAUSE THE ADC TO FUNCTION OUT OF
SPECIFICATION.
If the system is reset or the ADC module is reset using Bit 14 (RESET) from the ADC Control
Register 1, the routine must be repeated.
8.2.8 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
•
•
•
•
•
•
•
•
Compatible to McBSP in TMS320C54x/TMS320C55x DSP devices
Full-duplex communication
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
•
•
Works with SPI-compatible devices
The following application interfaces can be supported on the McBSP:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS-compliant devices
– SPI
•
McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer
switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O
buffer speed limit.
Note
See Section 7 for maximum I/O pin toggling speed.
Copyright © 2021 Texas Instruments Incorporated
130 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Figure 8-11 shows the block diagram of the McBSP module.
TX
Interrupt
MXINT
Peripheral Write Bus
CPU
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
16
DXR1 Transmit Buffer
16
LSPCLK
MFSXx
MCLKXx
Compand Logic
XSR2
XSR1
MDXx
MDRx
CPU
DMA Bus
RSR1
16
RSR2
16
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
16
16
Interrupt Select Logic
RX
Interrupt
RX Interrupt Logic
MRINT
CPU
Peripheral Read Bus
To CPU
Figure 8-11. McBSP Module
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 131
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-9 provides a summary of the McBSP registers.
Table 8-9. McBSP Register Summary
McBSP-A
ADDRESS
McBSP-B
ADDRESS
NAME
TYPE
RESET VALUE
DESCRIPTION
Data Registers, Receive, Transmit
DRR2
0x5000
0x5001
0x5002
0x5003
0x5040
0x5041
0x5042
0x5043
R
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 2
DRR1
DXR2
DXR1
McBSP Data Receive Register 1
McBSP Data Transmit Register 2
McBSP Data Transmit Register 1
W
W
McBSP Control Registers
SPCR2
SPCR1
RCR2
0x5004
0x5005
0x5006
0x5007
0x5008
0x5009
0x500A
0x500B
0x5044
0x5045
0x5046
0x5047
0x5048
0x5049
0x504A
0x504B
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
Multichannel Control Registers
MCR2
0x500C
0x500D
0x500E
0x500F
0x5010
0x5011
0x5012
0x5013
0x5014
0x5015
0x5016
0x5017
0x5018
0x5019
0x501A
0x501B
0x501C
0x501D
0x501E
0x5023
0x504C
0x504D
0x504E
0x504F
0x5050
0x5051
0x5052
0x5053
0x5054
0x5055
0x5056
0x5057
0x5058
0x5059
0x505A
0x505B
0x505C
0x505D
0x505E
0x5063
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
McBSP Multichannel Register 1
MCR1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
MFFINT
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
McBSP Interrupt Enable Register
Copyright © 2021 Texas Instruments Incorporated
132 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.2.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
•
•
•
Fully compliant with ISO 11898-1 (CAN 2.0B)
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit timestamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
•
•
•
•
•
Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 7.812 kbps.
For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 11.719 kbps.
The F2833x/F2823x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and
exceptions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 133
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
eCAN0INT
eCAN1INT
Controls Address
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 x 32-Bit Words
Message Objects Control
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 8-12. eCAN Block Diagram and Interface Circuit
Copyright © 2021 Texas Instruments Incorporated
134 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-10. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230
SN65HVD230Q
SN65HVD231
SN65HVD231Q
SN65HVD232
SN65HVD232Q
SN65HVD233
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Standby
Standby
Sleep
Adjustable
Adjustable
Adjustable
Adjustable
None
Yes
Yes
–
–
–
–
–
–
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
Yes
Sleep
Yes
None
None
None
None
None
None
Standby
Adjustable
Diagnostic
Loopback
SN65HVD234
SN65HVD235
3.3 V
3.3 V
Standby and Sleep
Standby
Adjustable
Adjustable
None
None
–
–40°C to 125°C
–40°C to 125°C
Autobaud
Loopback
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 135
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
Control and Status Registers
603Fh
6040h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
607Fh
6080h
Master Control - CANMC
Message Object Timestamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
60BFh
60C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
60FFh
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
6108h-610Fh
6110h-6117h
6118h-611Fh
6120h-6127h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Timestamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
61E8h-61EFh
61F0h-61F7h
61F8h-61FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
61E8h-61E9h
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
Figure 8-13. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
Copyright © 2021 Texas Instruments Incorporated
136 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
eCAN-B Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
eCAN-B Memory (512 Bytes)
Abort Acknowledge - CANAA
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
6200h
Control and Status Registers
623Fh
6240h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
627Fh
6280h
Master Control - CANMC
Message Object Timestamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
62BFh
62C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
62FFh
eCAN-B Memory RAM (512 Bytes)
6300h-6307h
6308h-630Fh
6310h-6317h
6318h-631Fh
6320h-6327h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Timestamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
63E0h-63E7h
63E8h-63EFh
63F0h-63F7h
63F8h-63FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
63E8h-63E9h
63EAh-63EBh
63ECh-63EDh
63EEh-63EFh
Figure 8-14. eCAN-B Memory Map
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 137
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
The CAN registers listed in Table 8-11 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. Thirty-two-bit accesses are aligned to an even boundary.
Table 8-11. CAN Register Map (1)
eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
REGISTER NAME
DESCRIPTION
CANME
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
0x6200
0x6202
0x6204
0x6206
0x6208
0x620A
0x620C
0x620E
0x6210
0x6212
0x6214
0x6216
0x6218
0x621A
0x621C
0x621E
0x6220
0x6222
0x6224
0x6226
0x6228
0x622A
0x622C
0x622E
0x6230
0x6232
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
CANMD
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Timestamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
Copyright © 2021 Texas Instruments Incorporated
138 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
The devices include three serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to more than 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
Baud rate =
16
Note
See Section 7 for maximum I/O pin toggling speed.
•
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (nonreturn-to-zero) format
•
•
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as
zeros. Writing to the upper byte has no effect.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 139
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 8-12, Table 8-13, and Table
8-14.
Table 8-12. SCI-A Registers (1)
NAME
SCICCRA
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 8-13. SCI-B Registers (1) (2)
NAME
SCICCRB
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Copyright © 2021 Texas Instruments Incorporated
140 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-14. SCI-C Registers (1) (2)
NAME
ADDRESS
0x7770
0x7771
0x7772
0x7773
0x7774
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
SIZE (x16)
DESCRIPTION
SCI-C Communications Control Register
SCI-C Control Register 1
SCICCRC
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1C
SCIHBAUDC
SCILBAUDC
SCICTL2C
SCI-C Baud Register, High Bits
SCI-C Baud Register, Low Bits
SCI-C Control Register 2
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC(2)
SCIFFRXC(2)
SCIFFCTC(2)
SCIPRC
SCI-C Receive Status Register
SCI-C Receive Emulation Data Buffer Register
SCI-C Receive Data Buffer Register
SCI-C Transmit Data Buffer Register
SCI-C FIFO Transmit Register
SCI-C FIFO Receive Register
SCI-C FIFO Control Register
SCI-C Priority Control Register
Figure 8-15 shows the SCI module block diagram.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 141
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
SCICTL1.1
SCITXD
SCITXD
TXSHF
Register
Frame Format and Mode
TXENA
TX EMPTY
Parity
Even/Odd Enable
SCICTL2.6
8
SCICCR.6 SCICCR.5
TX INT ENA
TXRDY
Transmitter-Data
Buffer Register
SCICTL2.7
SCICTL2.0
8
TXWAKE
TXINT
To CPU
TX FIFO _0
SCICTL1.3
TX Interrupt Logic
TX FIFO _1
- - - - -
TX
FIFO
Interrupts
1
SCI TX Interrupt Select Logic
TX FIFO _15
WUT
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
AutoBaud Detect Logic
SCIRXD
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
RXRDY
RX/BK INT ENA
Receive-Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
- - - - -
RX
FIFO
Interrupts
RX FIFO _1
RX FIFO _0
RXINT
To CPU
RX Interrupt Logic
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 8-15. Serial Communications Interface (SCI) Module Block Diagram
Copyright © 2021 Texas Instruments Incorporated
142 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available.
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the DSC controller and external peripherals or another processor. Typical applications
include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to127
when SPIBRR = 0,1, 2
(SPIBRR + 1)
LSPCLK
4
Baud rate =
Note
See Section 7 for maximum I/O pin toggling speed.
Data word length: 1 to 16 data bits
•
•
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
16-level transmit/receive FIFO
Delayed transmit control
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 143
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
The SPI port operation is configured and controlled by the registers listed in Table 8-15 .
Table 8-15. SPI-A Registers
SIZE (x16)
NAME
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
DESCRIPTION(1)
SPICCR
SPICTL
SPISTS
SPIBRR
1
1
1
1
1
1
1
1
1
1
1
1
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
SPI-A Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Figure 8-16 is a block diagram of the SPI in slave mode.
Copyright © 2021 Texas Instruments Incorporated
144 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX FIFO _15
RX Interrupt
Logic
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPISTS.6
SPITXBUF
Buffer Register
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 − 0
S
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 8-16. SPI Module Block Diagram (Slave Mode)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 145
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.12 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 8-17 shows how the I2C peripheral module interfaces within the
device.
System Control Block
C28x CPU
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
Data[16]
SDAA
SCLA
I2C-A
Addr[16]
I2CINT1A
I2CINT2A
GPIO
MUX
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 8-17. I2C Peripheral Module Interfaces
Copyright © 2021 Texas Instruments Incorporated
146 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 16-word receive FIFO and one 16-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
•
•
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module-enable and module-disable capability
Free data format mode
The registers in Table 8-16 configure and control the I2C port operation.
Table 8-16. I2C-A Registers
NAME
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
–
DESCRIPTION
I2COAR
I2CIER
I2C own address register
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
–
8.2.13 GPIO MUX
On the 2833x/2823x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a
single GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block diagram
per pin is shown in Figure 8-18. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 147
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
diagram for these pins differ. See the TMS320x2833x, 2823x system control and interrupts reference guide for
details.
Note
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers
occurs to when the action is valid.
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
GPIOXINT7SEL
GPIOXNMISEL
Low-Power
Modes Block
External Interrupt
MUX
PIE
GPxDAT (read)
Asynchronous
path
GPxQSEL1/2
GPxCTRL
GPxPUD
00
01
N/C
Peripheral 1 Input
Input
Qualification
Internal
Pullup
Peripheral 2 Input
Peripheral 3 Input
10
11
Asynchronous path
GPxTOGGLE
GPxCLEAR
GPxSET
GPIOx pin
00
01
10
11
GPxDAT (latch)
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
High-Impedance
Output Control
00
01
GPxDIR (latch)
Peripheral 1 Output Enable
0 = Input, 1 = Output
XRS
Peripheral 2 Output Enable
Peripheral 3 Output Enable
10
11
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Copyright © 2021 Texas Instruments Incorporated
148 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2833x, 2823x system
control and interrupts reference guide for pin-specific variations.
Figure 8-18. GPIO MUX Block Diagram
The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 8-17 shows the GPIO register
mapping.
Table 8-17. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control Register (GPIO0 to 31)
SIZE (x16)
DESCRIPTION
GPACTRL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
2
2
2
2
18
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F82
0x6F84
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
0x6F86
0x6F88
GPIO A MUX 2 Register (GPIO16 to 31)
0x6F8A
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pullup Disable Register (GPIO0 to 31)
GPAPUD
0x6F8C
Reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F8E – 0x6F8F
0x6F90
GPIO B Control Register (GPIO32 to 63)
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPIO B MUX 1 Register (GPIO32 to 47)
0x6F92
0x6F94
0x6F96
0x6F98
GPIO B MUX 2 Register (GPIO48 to 63)
0x6F9A
GPIO B Direction Register (GPIO32 to 63)
GPIO B Pullup Disable Register (GPIO32 to 63)
GPBPUD
Reserved
GPCMUX1
GPCMUX2
GPCDIR
0x6F9C
0x6F9E – 0x6FA5
0x6FA6
GPIO C MUX1 Register (GPIO64 to 79)
GPIO C MUX2 Register (GPIO80 to 87)
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pullup Disable Register (GPIO64 to 87)
0x6FA8
0x6FAA
GPCPUD
Reserved
0x6FAC
0x6FAE – 0x6FBF
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
0x6FC2
2
2
2
2
2
2
2
2
2
2
2
2
8
GPIO A Data Register (GPIO0 to 31)
GPASET
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 63)
GPACLEAR
GPATOGGLE
GPBDAT
0x6FC4
0x6FC6
0x6FC8
GPBSET
0x6FCA
GPIO B Data Set Register (GPIO32 to 63)
GPIO B Data Clear Register (GPIO32 to 63)
GPIOB Data Toggle Register (GPIO32 to 63)
GPIO C Data Register (GPIO64 to 87)
GPIO C Data Set Register (GPIO64 to 87)
GPIO C Data Clear Register (GPIO64 to 87)
GPIO C Data Toggle Register (GPIO64 to 87)
GPBCLEAR
GPBTOGGLE
GPCDAT
0x6FCC
0x6FCE
0x6FD0
GPCSET
0x6FD2
GPCCLEAR
GPCTOGGLE
Reserved
0x6FD4
0x6FD6
0x6FD8 – 0x6FDF
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
0x6FE0
0x6FE1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 149
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-17. GPIO Registers (continued)
NAME
GPIOXNMISEL
GPIOXINT3SEL
GPIOXINT4SEL
GPIOXINT5SEL
GPIOXINT6SEL
GPIOINT7SEL
GPIOLPMSEL
Reserved
ADDRESS
SIZE (x16)
DESCRIPTION
0x6FE2
1
1
XNMI GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO32 to 63)
XINT4 GPIO Input Select Register (GPIO32 to 63)
XINT5 GPIO Input Select Register (GPIO32 to 63)
XINT6 GPIO Input Select Register (GPIO32 to 63)
XINT7 GPIO Input Select Register (GPIO32 to 63)
LPM GPIO Select Register (GPIO0 to 31)
0x6FE3
0x6FE4
1
0x6FE5
1
0x6FE6
1
0x6FE7
1
0x6FE8
2
0x6FEA – 0x6FFF
22
Table 8-18. GPIO-A Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPADIR
GPADAT
GPASET
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1 = 0,0
PER1
GPAMUX1 = 0, 1
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
GPACLR
GPATOGGLE
0
1
1, 0
GPIO0 (I/O)
GPIO1 (I/O)
GPIO2 (I/O)
GPIO3 (I/O)
GPIO4 (I/O)
GPIO5 (I/O)
GPIO6 (I/O)
GPIO7 (I/O)
GPIO8 (I/O)
GPIO9 (I/O)
GPIO10 (I/O)
GPIO11 (I/O)
GPIO12 (I/O)
GPIO13 (I/O)
GPIO14 (I/O)
GPIO15 (I/O)
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
Reserved
ECAP6 (I/O)
Reserved
Reserved
MFSRB (I/O)
Reserved
3, 2
2
5, 4
3
7, 6
ECAP5 (I/O)
Reserved
MCLKRB (I/O)
Reserved
QUALPRD0
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
MFSRA (I/O)
EPWMSYNCI (I)
MCLKRA (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
ADCSOCAO (O)
ECAP3 (I/O)
ADCSOCBO (O)
ECAP4 (I/O)
MDXB (O)
6
7
8
9
10
11
12
13
14
15
QUALPRD1
TZ2 (I)
MDRB (I)
TZ3 (I)/ XHOLD (I)
TZ4 (I)/ XHOLDA (O)
MCLKXB (I/O)
MFSXB (I/O)
GPAMUX2
GPAQSEL2
GPAMUX2 = 0, 0
GPAMUX2 = 0, 1
GPAMUX2 = 1, 0
GPAMUX2 = 1, 1
16
17
18
19
20
21
22
23
1, 0
3, 2
GPIO16 (I/O)
GPIO17 (I/O)
GPIO18 (I/O)
GPIO19 (I/O)
GPIO20 (I/O)
GPIO21 (I/O)
GPIO22 (I/O)
GPIO23 (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXA (O)
TZ5 (I)
TZ6 (I)
5, 4
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
7, 6
QUALPRD2
9, 8
11, 10
13, 12
15, 14
EQEP1B (I)
MDRA (I)
EQEP1S (I/O)
EQEP1I (I/O)
MCLKXA (I/O)
MFSXA (I/O)
Copyright © 2021 Texas Instruments Incorporated
150 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-18. GPIO-A Mux Peripheral Selection Matrix (continued)
REGISTER BITS
PERIPHERAL SELECTION
GPADIR
GPADAT
GPASET
GPACLR
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1 = 0,0
PER1
GPAMUX1 = 0, 1
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
GPATOGGLE
24
25
26
27
28
29
30
31
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPIO24 (I/O)
GPIO25 (I/O)
GPIO26 (I/O)
GPIO27 (I/O)
GPIO28 (I/O)
GPIO29 (I/O)
GPIO30 (I/O)
GPIO31 (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
CANTXA (O)
EQEP2A (I)
EQEP2B (I)
MDXB (O)
MDRB (I)
EQEP2I (I/O)
EQEP2S (I/O)
MCLKXB (I/O)
MFSXB (I/O)
QUALPRD3
XZCS6 (O)
XA19 (O)
XA18 (O)
XA17 (O)
Table 8-19. GPIO-B Mux Peripheral Selection Matrix
REGISTER BITS
GPBDIR
PERIPHERAL SELECTION
GPBDAT
GPBSET
GPBCLR
GPBMUX1
GPBQSEL1
GPIOx
GPBMUX1 = 0, 0
PER1
GPBMUX1 = 0, 1
PER2
GPBMUX1 = 1, 0
PER3
GPBMUX1 = 1, 1
GPBTOGGLE
0
1
1, 0
GPIO32 (I/O)
GPIO33 (I/O)
GPIO34 (I/O)
GPIO35 (I/O)
GPIO36 (I/O)
GPIO37 (I/O)
GPIO38 (I/O)
GPIO39 (I/O)
GPIO40 (I/O)
GPIO41 (I/O)
GPIO42 (I/O)
GPIO43 (I/O)
GPIO44 (I/O)
GPIO45 (I/O)
GPIO46 (I/O)
GPIO47 (I/O)
SDAA (I/OC)(1)
SCLA (I/OC)(1)
ECAP1 (I/O)
SCITXDA (O)
SCIRXDA (I)
ECAP2 (I/O)
EPWMSYNCI (I)
ADCSOCAO (O)
ADCSOCBO (O)
3, 2
EPWMSYNCO (O)
2
5, 4
XREADY (I)
3
7, 6
XR/ W (O)
XZCS0 (O)
XZCS7 (O)
XWE0 (O)
XA16 (O)
XA0/ XWE1 (O)
XA1 (O)
QUALPRD0
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
6
7
8
9
10
11
12
13
14
15
XA2 (O)
Reserved
XA3 (O)
QUALPRD1
XA4 (O)
XA5 (O)
XA6 (O)
XA7 (O)
GPBMUX2
GPBQSEL2
GPBMUX2 = 0, 0
GPBMUX2 = 0, 1
GPBMUX2 = 1, 0
GPBMUX2 = 1, 1
16
17
18
19
20
21
22
23
1, 0
3, 2
GPIO48 (I/O)
GPIO49 (I/O)
GPIO50 (I/O)
GPIO51 (I/O)
GPIO52 (I/O)
GPIO53 (I/O)
GPIO54 (I/O)
GPIO55 (I/O)
ECAP5 (I/O)
ECAP6 (I/O)
EQEP1A (I)
XD31 (I/O)
XD30 (I/O)
XD29 (I/O)
XD28 (I/O)
XD27 (I/O)
XD26 (I/O)
XD25 (I/O)
XD24 (I/O)
5, 4
7, 6
EQEP1B (I)
QUALPRD2
9, 8
EQEP1S (I/O)
EQEP1I (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
11, 10
13, 12
15, 14
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 151
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-19. GPIO-B Mux Peripheral Selection Matrix (continued)
REGISTER BITS
PERIPHERAL SELECTION
GPBDIR
GPBDAT
GPBSET
GPBCLR
GPBMUX1
GPBQSEL1
GPIOx
GPBMUX1 = 0, 0
PER1
GPBMUX1 = 0, 1
PER2
GPBMUX1 = 1, 0
PER3
GPBMUX1 = 1, 1
GPBTOGGLE
24
25
26
27
28
29
30
31
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPIO56 (I/O)
GPIO57 (I/O)
GPIO58 (I/O)
GPIO59 (I/O)
GPIO60 (I/O)
GPIO61 (I/O)
GPIO62 (I/O)
GPIO63 (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
XD23 (I/O)
XD22 (I/O)
XD21 (I/O)
XD20 (I/O)
XD19 (I/O)
XD18 (I/O)
XD17 (I/O)
XD16 (I/O)
QUALPRD3
(1) Open drain
Table 8-20. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPCDIR
GPCDAT
GPCSET
GPCCLR
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
GPCMUX1
GPCTOGGLE
0
1
2
3
4
5
6
7
8
9
1, 0
3, 2
GPIO64 (I/O)
GPIO65 (I/O)
GPIO66 (I/O)
GPIO67 (I/O)
GPIO68 (I/O)
GPIO69 (I/O)
GPIO70 (I/O)
GPIO71 (I/O)
GPIO72 (I/O)
GPIO73 (I/O)
GPIO74 (I/O)
GPIO75 (I/O)
GPIO76 (I/O)
GPIO77 (I/O)
GPIO78 (I/O)
GPIO79 (I/O)
GPCMUX2 = 0, 0 or 0, 1
GPIO80 (I/O)
GPIO81 (I/O)
GPIO82 (I/O)
GPIO83 (I/O)
GPIO84 (I/O)
GPIO85 (I/O)
GPIO86 (I/O)
GPIO87 (I/O)
XD15 (I/O)
XD14 (I/O)
XD13 (I/O)
XD12 (I/O)
XD11 (I/O)
XD10 (I/O)
XD9 (I/O)
5, 4
7, 6
no qual
9, 8
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPCMUX2
1, 0
XD8 (I/O)
XD7 (I/O)
XD6 (I/O)
10
11
12
13
14
15
XD5 (I/O)
XD4 (I/O)
no qual
XD3 (I/O)
XD2 (I/O)
XD1 (I/O)
XD0 (I/O)
GPCMUX2 = 1, 0 or 1, 1
XA8 (O)
16
17
18
19
20
21
22
23
3, 2
XA9 (O)
5, 4
XA10 (O)
7, 6
XA11 (O)
no qual
9, 8
XA12 (O)
11, 10
13, 12
15, 14
XA13 (O)
XA14 (O)
XA15 (O)
Copyright © 2021 Texas Instruments Incorporated
152 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
Time Between Samples
GPyCTRL Reg
Input Signal
Qualified by
3 or 6 Samples
Qualification
GPIOx
SYNC
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 8-19. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when all samples are the same
(all 0s or all 1s) as shown in Figure 8-19 (for 6-sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 153
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.2.14 External Interface (XINTF)
This section gives a top-level view of the external interface (XINTF) that is implemented on the 2833x/2823x
devices.
The XINTF is a nonmultiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three
fixed zones shown in Figure 8-20.
Data Space
Prog Space
0x0000-0000
XD[31:0]
XA[19:0]
XZCS0
0x0000-4000
0x0000-5000
XINTF Zone 0
(8K x 16)
0x0010-0000
0x0020-0000
0x0030-0000
XINTF Zone 6
(1M x 16)
XZCS6
XINTF Zone 7
(1M x 16)
XZCS7
XA0/XWE1
XWE0
XRD
XR/W
XREADY
XHOLD
XHOLDA
XCLKOUT
A. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip selects that toggle when
an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals.
B. Zones 1 – 5 are reserved for future expansion.
C. Zones 0, 6, and 7 are always enabled.
Figure 8-20. External Interface Block Diagram
Copyright © 2021 Texas Instruments Incorporated
154 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Figure 8-21 and Figure 8-22 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how the
functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 8-21 defines XINTF
configuration and control registers.
XINTF
External
wait-state
generator
XREADY
16-bits
XCLKOUT
XZCS0, XZCS6, XZCS7
XA(19:1)
CS
A(19:1)
A(0)
XA0/XWE1
XRD
OE
WE
XWE0
D(15:0)
XD(15:0)
Figure 8-21. Typical 16-Bit Data Bus XINTF Connections
XINTF
External
wait-state
generator
XREADY
Low 16-bits
XCLKOUT
CS
A(18:0)
OE
XA(19:1)
XRD
WE
XWE0
D(15:0)
XD(15:0)
High 16-bits
A(18:0)
XZCS0, XZCS6, XZCS7
CS
OE
WE
XA0/XWE1
(select XWE1)
D(31:16)
XD(31:16)
Figure 8-22. Typical 32-Bit Data Bus XINTF Connections
Table 8-21. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
0x00−0B20
0x00−0B2C
0x00−0B2E
0x00−0B34
0x00−0B38
0x00−0B3A
0x00−0B3D
SIZE (x16)
DESCRIPTION
XTIMING0
XTIMING6(1)
XTIMING7
XINTCNF2(2)
XBANK
2
2
2
2
1
1
1
XINTF Timing Register, Zone 0
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XREVISION
XRESET
XINTF Reset Register
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 155
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.3 Memory Maps
In Figure 8-23 to Figure 8-25, the following apply:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are
restricted to data memory only. A user program cannot access these memory maps in program space.
Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order.
See the TMS320x2833x, 2823x system control and interrupts reference guide for more details.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
Locations 0x38 0080–0x38 008F contain the ADC calibration routine. It is not programmable by the user.
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox
RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.
•
•
•
•
Copyright © 2021 Texas Instruments Incorporated
156 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
0x00 0800
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA-Accessible
Reserved
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA-Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L3 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L4 SARAM (4K x 16, DMA-Accessible)
0x00 9000
0x00 A000
0x00 B000
0x00 C000
Reserved
0x00 D000
0x00 E000
0x00 F000
0x01 0000
L5 SARAM (4K x 16, DMA-Accessible)
L6 SARAM (4K x 16, DMA-Accessible)
L7 SARAM (4K x 16, DMA-Accessible)
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA-Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA-Accessible)
Reserved
0x30 0000
0x33 FFF8
FLASH (256K x 16, Secure Zone)
128-bit Password
Reserved
0x34 0000
0x38 0080
ADC Calibration Data and PARTID (Secure Zone)
0x38 0091
Reserved
0x38 0400
0x38 0800
User OTP (1K x 16, Secure Zone)
Reserved
0x3F 8000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L3 SARAM (4K x 16, Secure Zone, Dual-Mapped)
0x3F 9000
0x3F A000
0x3F B000
0x3F C000
Reserved
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector- should be enabled at a time.
Figure 8-23. F28335, F28333, F28235 Memory Map
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 157
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Block
On-Chip Memory
Start Address
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
0x00 0040
0x00 0400
0x00 0800
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
Reserved
(Enabled if
VMAP = 1,
ENPIE = 1)
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
Reserved
XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA-Accessible
0x00 5000
0x00 5000
Peripheral Frame 3
(Protected)
DMA-Accessible
0x00 6000
0x00 7000
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L3 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L4 SARAM (4K x 16, DMA-Accessible)
0x00 9000
0x00 A000
0x00 B000
Reserved
0x00 C000
0x00 D000
0x00 E000
0x00 F000
0x01 0000
L5 SARAM (4K x 16, DMA-Accessible)
L6 SARAM (4K x 16, DMA-Accessible)
L7 SARAM (4K x 16, DMA-Accessible)
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA-Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA-Accessible)
Reserved
0x32 0000
0x33 FFF8
FLASH (128K x 16, Secure Zone)
128-bit Password
0x34 0000
0x38 0080
Reserved
ADC Calibration Data and PARTID (Secure Zone)
0x38 0091
0x38 0400
Reserved
User OTP (1K x 16, Secure Zone)
Reserved
0x38 0800
0x3F 8000
0x3F 9000
0x3F A000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
Reserved
L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L3 SARAM (4K x 16, Secure Zone, Dual-Mapped)
0x3F B000
0x3F C000
0x3F E000
Reserved
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
Figure 8-24. F28334, F28234 Memory Map
Copyright © 2021 Texas Instruments Incorporated
158 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enabled if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARAM (1K x 16)
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE = 1)
Reserved
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
XINTF Zone 0 (4K x 16, XZCS0)
(Protected) DMA-Accessible
Reserved
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA-Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L3 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L4 SARAM (4K x 16, DMA-Accessible)
Reserved
0x00 9000
0x00 A000
0x00 B000
0x00 C000
0x00 D000
0x00 E000
L5 SARAM (4K x 16, DMA-Accessible)
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA-Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA-Accessible)
Reserved
0x33 0000
0x33 FFF8
FLASH (64K x 16, Secure Zone)
128-bit Password
0x34 0000
0x38 0080
Reserved
ADC Calibration Data and PARTID (Secure Zone)
Reserved
0x38 0091
0x38 0400
User OTP (1K x 16, Secure Zone)
Reserved
0x38 0800
0x3F 8000
0x3F 9000
0x3F A000
L0 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L1 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L2 SARAM (4K x 16, Secure Zone, Dual-Mapped)
L3 SARAM (4K x 16, Secure Zone, Dual-Mapped)
Reserved
0x3F B000
0x3F C000
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enabled if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
Figure 8-25. F28332, F28232 Memory Map
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 159
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-22. Addresses of Flash Sectors in F28335, F28333, F28235
ADDRESS RANGE
0x30 0000 - 0x30 7FFF
0x30 8000 - 0x30 FFFF
0x31 0000 - 0x31 7FFF
0x31 8000 - 0x31 FFFF
0x32 0000 - 0x32 7FFF
0x32 8000 - 0x32 FFFF
0x33 0000 - 0x33 7FFF
0x33 8000 - 0x33 FF7F
PROGRAM AND DATA SPACE
Sector H (32K × 16)
Sector G (32K × 16)
Sector F (32K × 16)
Sector E (32K × 16)
Sector D (32K × 16)
Sector C (32K × 16)
Sector B (32K × 16)
Sector A (32K × 16)
Program to 0x0000 when using the
Code Security Module
0x33 FF80 - 0x33 FFF5
0x33 FFF6 - 0x33 FFF7
0x33 FFF8 - 0x33 FFFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password
(128-Bit) (Do Not Program to all zeros)
Table 8-23. Addresses of Flash Sectors in F28334, F28234
ADDRESS RANGE
0x32 0000 - 0x32 3FFF
0x32 4000 - 0x32 7FFF
0x32 8000 - 0x32 BFFF
0x32 C000 - 0x32 FFFF
0x33 0000 - 0x33 3FFF
0x33 4000 - 0x33 7FFFF
0x33 8000 - 0x33 BFFF
0x33 C000 - 0x33 FF7F
PROGRAM AND DATA SPACE
Sector H (16K × 16)
Sector G (16K × 16)
Sector F (16K × 16)
Sector E (16K × 16)
Sector D (16K × 16)
Sector C (16K × 16)
Sector B (16K × 16)
Sector A (16K × 16)
Program to 0x0000 when using the
Code Security Module
0x33 FF80 - 0x33 FFF5
0x33 FFF6 - 0x33 FFF7
0x33 FFF8 - 0x33 FFFF
Boot-to-Flash Entry Point
(program branch instruction here)
Security Password (128-Bit)
(Do Not Program to all zeros)
Table 8-24. Addresses of Flash Sectors in F28332, F28232
ADDRESS RANGE
PROGRAM AND DATA SPACE
0x33 0000 - 0x33 3FFF
0x33 4000 - 0x33 7FFFF
0x33 8000 - 0x33 BFFF
0x33 C000 - 0x33 FF7F
0x33 FF80 - 0x33 FFF5
0x33 FFF6 - 0x33 FFF7
0x33 FFF8 - 0x33 FFFF
Sector D (16K × 16)
Sector C (16K × 16)
Sector B (16K × 16)
Sector A (16K × 16)
Program to 0x0000 when using the Code Security Module
Boot-to-Flash Entry Point (program branch instruction here)
Security Password (128-Bit) (Do Not Program to all zeros)
Note
•
•
When the code-security passwords are programmed, all addresses from 0x33FF80 to 0x33FFF5
cannot be used as program code or data. These locations must be programmed to 0x0000.
If the code security feature is not used, addresses 0x33FF80 to 0x33FFEF may be used for code
or data. Addresses 0x33FFF0 to 0x33FFF5 are reserved for data and should not contain program
code.
Table 8-25 shows how to handle these memory locations.
Copyright © 2021 Texas Instruments Incorporated
160 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-25. Handling Security Code Locations
FLASH
ADDRESS
CODE SECURITY ENABLED
CODE SECURITY DISABLED
Application code and data
Reserved for data only
0x33FF80 – 0x33FFEF
0x33FFF0 – 0x33FFF5
Fill with 0x0000
Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to
be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen
as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations,
will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The C28x CPU supports a block
protection mode where a region of memory can be protected so as to make sure that operations occur as written
(the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will
protect the selected zones.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 161
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
The wait states for the various spaces in the memory map area are listed in Table 8-26.
Table 8-26. Wait States
WAIT STATES
(CPU)
WAIT STATES
(DMA)(1)
AREA
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
0-wait
Fixed
0-wait (writes)
1-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (reads)
No access (writes)
0-wait (writes)
1-wait (reads)
No access
Peripheral Frame 3
Peripheral Frame 1
Assumes no conflicts between CPU and DMA.
Cycles can be extended by peripheral generated ready.
Consecutive (back-to-back) writes to Peripheral Frame 1
registers will experience a 1-cycle pipeline hit (1-cycle delay)
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
0-wait
No access
No access
Fixed. Cycles cannot be extended by the peripheral.
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM
L5 SARAM
L6 SARAM
L7 SARAM
XINTF
Assumes no CPU conflicts
0-wait data (reads)
0-wait data (writes)
1-wait program (reads)
1-wait program (writes)
Programmable
0-wait
Assumes no conflicts between CPU and DMA.
Programmable
Programmed through the XTIMING registers or extendable
through external XREADY signal to meet system timing
requirements.
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes 0-wait minimum writes 0-wait minimum for writes assumes write buffer enabled and
with write buffer
enabled
with write buffer enabled not full.
Assumes no conflicts between CPU and DMA. When DMA and
CPU try simultaneously (conflict), a 1-cycle delay is added for
arbitration.
OTP
Programmable
1-wait minimum
No access
No access
Programmed via the Flash registers.
1-wait is minimum number of wait states allowed. 1-wait-state
operation is possible at a reduced CPU frequency.
FLASH
Programmable
Programmed via the Flash registers.
1-wait Paged min
0-wait minimum for paged access is not allowed
1-wait Random min
Random ≥ Paged
FLASH Password
Boot-ROM
16-wait fixed
1-wait
No access
No access
Wait states of password locations are fixed.
0-wait speed is not possible.
(1) The DMA has a base of four cycles/word.
Copyright © 2021 Texas Instruments Incorporated
162 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.4 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
Peripheral Frame 1
These are peripherals that are mapped directly to the CPU memory bus. See Table 8-27.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 8-28.
Peripheral Frame 2:
Peripheral Frame 3:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 8-29.
These are peripherals that are mapped to the 32-bit DMA-accessible peripheral bus. See Table 8-30.
Table 8-27. Peripheral Frame 0 Registers (1)
NAME
Device Emulation Registers
FLASH Registers(3)
ADDRESS RANGE
0x00 0880 – 0x00 09FF
0x00 0A80 – 0x00 0ADF
0x00 0AE0 – 0x00 0AEF
SIZE (x16)
ACCESS TYPE(2)
EALLOW protected
384
96
EALLOW protected
EALLOW protected
Code Security Module Registers
16
ADC registers (dual-mapped)
0 wait (DMA), 1 wait (CPU), read only
0x00 0B00 – 0x00 0B0F
0x00 0B20 – 0x00 0B3F
0x00 0C00 – 0x00 0C3F
16
32
64
Not EALLOW protected
EALLOW protected
XINTF Registers
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
Registers
Not EALLOW protected
PIE Registers
0x00 0CE0 – 0x00 0CFF
0x00 0D00 – 0x00 0DFF
0x00 1000 – 0x00 11FF
32
Not EALLOW protected
EALLOW protected
EALLOW protected
PIE Vector Table
DMA Registers
256
512
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
(3) The Flash Registers are also protected by the Code Security Module (CSM).
Table 8-28. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6000 – 0x00 61FF
0x00 6200 – 0x00 63FF
0x00 6800 – 0x00 683F
0x00 6840 – 0x00 687F
0x00 6880 – 0x00 68BF
0x00 68C0 – 0x00 68FF
0x00 6900 – 0x00 693F
0x00 6940 – 0x00 697F
0x00 6A00 – 0x00 6A1F
0x00 6A20 – 0x00 6A3F
0x00 6A40 – 0x00 6A5F
0x00 6A60 – 0x00 6A7F
0x00 6A80 – 0x00 6A9F
0x00 6AA0 – 0x00 6ABF
0x00 6B00 – 0x00 6B3F
0x00 6B40 – 0x00 6B7F
0x00 6F80 – 0x00 6FFF
SIZE (x16)
512
512
64
eCAN-A Registers
eCAN-B Registers
ePWM1 + HRPWM1 Registers
ePWM2 + HRPWM2 Registers
ePWM3 + HRPWM3 Registers
ePWM4 + HRPWM4 Registers
ePWM5 + HRPWM5 Registers
ePWM6 + HRPWM6 Registers
eCAP1 Registers
64
64
64
64
64
32
eCAP2 Registers
32
eCAP3 Registers
32
eCAP4 Registers
32
eCAP5 Registers
32
eCAP6 Registers
32
eQEP1 Registers
64
eQEP2 Registers
64
GPIO Registers
128
Table 8-29. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
SIZE (x16)
System Control Registers
0x00 7010 – 0x00 702F
32
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 163
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
Table 8-29. Peripheral Frame 2 Registers (continued)
NAME
ADDRESS RANGE
SIZE (x16)
SPI-A Registers
SCI-A Registers
0x00 7040 – 0x00 704F
0x00 7050 – 0x00 705F
0x00 7070 – 0x00 707F
0x00 7100 – 0x00 711F
0x00 7750 – 0x00 775F
0x00 7770 – 0x00 777F
0x00 7900 – 0x00 793F
16
16
16
32
16
16
64
External Interrupt Registers
ADC Registers
SCI-B Registers
SCI-C Registers
I2C-A Registers
Table 8-30. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
SIZE (x16)
McBSP-A Registers (DMA)
McBSP-B Registers (DMA)
ePWM1 + HRPWM1 (DMA)(1)
ePWM2 + HRPWM2 (DMA)
ePWM3 + HRPWM3 (DMA)
ePWM4 + HRPWM4 (DMA)
ePWM5 + HRPWM5 (DMA)
ePWM6 + HRPWM6 (DMA)
0x5000 – 0x503F
0x5040 – 0x507F
0x5800 – 0x583F
0x5840 – 0x587F
0x5880 – 0x58BF
0x58C0 – 0x58FF
0x5900 – 0x593F
0x5940 – 0x597F
64
64
64
64
64
64
64
64
(1) The ePWM and HRPWM modules can be re-mapped to Peripheral Frame 3 where they can be accessed by the DMA module. To
achieve this, bit 0 (MAPEPWM) of MAPCNF register (address 0x702E) must be set to 1. This register is EALLOW protected. When
this bit is 0, the ePWM and HRPWM modules are mapped to Peripheral Frame 1.
Copyright © 2021 Texas Instruments Incorporated
164 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.4.1 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 8-31.
Table 8-31. Device Emulation Registers
ADDRESS
RANGE
NAME
SIZE (x16)
DESCRIPTION
0x0880
0x0881
DEVICECNF
PARTID
2
1
Device Configuration Register
0x380090
Part ID Register
TMS320F28335
0x00EF
TMS320F28334
TMS320F28333
TMS320F28332
TMS320F28235
TMS320F28234
TMS320F28232
TMS320F28335
TMS320F28334
TMS320F28333
TMS320F28332
TMS320F28235
TMS320F28234
TMS320F28232
0x00EE
0x00E0
0x00ED
0x00E8
0x00E7
0x00E6
0x00EF
0x00EF
0x00EF
0x00EF
0x00E8
0x00E8
0x00E8
CLASSID
0x0882
1
TMS320F2833x
Floating-Point
Class Device
TMS320F2823x
Fixed-Point
Class Device
REVID
0x0883
1
Revision ID
Register
0x0001 – Silicon Rev. A – TMS
PROTSTART
PROTRANGE
0x0884
0x0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 165
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.5 Interrupts
Figure 8-26 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, I2C, CAN, McBSP(A),
ePWM(A), eCAP, eQEP, ADC(A))
Clear
DMA
WDINT
Watchdog
Low-Power Models
WAKEINT
DMA
Sync
LPMINT
SYSCLKOUT
XINT1
XINT1
Latch
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1
to
INT12
GPIOXINT1SEL(4:0)
XINT2SOC
XINT2
DMA
XINT2
ADC
Latch
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
C28
Core
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
CPU Timer 1
INT14
INT13
TINT1
GPIO0.int
XNMI_
XINT13
GPIO
Mux
Latch
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
DMA
A. DMA-accessible
Figure 8-26. External and PIE Interrupt Sources
Copyright © 2021 Texas Instruments Incorporated
166 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
DMA
XINT3
Interrupt Control
XINT3CR(15:0)
Latch
GPIOXINT3SEL(4:0)
DMA
XINT4
Interrupt Control
XINT4CR(15:0)
Latch
GPIOXINT4SEL(4:0)
DMA
XINT5
INT1
to
INT12
PIE
Latch
Interrupt Control
XINT5CR(15:0)
C28
Core
GPIOXINT5SEL(4:0)
DMA
XINT6
Interrupt Control
XINT6CR(15:0)
Latch
GPIOXINT6SEL(4:0)
DMA
XINT7
GPIO32.int
GPIO63.int
GPIO
Mux
Interrupt Control
XINT7CR(15:0)
Latch
GPIOXINT7SEL(4:0)
Figure 8-27. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the 2833x/2823x devices, 58 of these are used by peripherals as
shown in Table 8-32.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. TRAP #0 tries to transfer program control to the address pointed to by the reset vector. The
PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the
PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 to TRAP #12 will transfer program control to the interrupt service routine
corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1,
TRAP #2 fetches the vector from INT2.1, and so forth.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 167
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 8-28. Multiplexing of Interrupts Using the PIE Block
Table 8-32. PIE Peripheral Interrupts (1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
ADCINT(2)
(ADC)
SEQ2INT
(ADC)
SEQ1INT
(ADC)
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
XINT2
XINT1
Reserved
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP6_INT
(eCAP6)
ECAP5_INT
(eCAP5)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
Reserved
Reserved
Reserved
Reserved
MXINTA
(McBSP-A)
MRINTA
(McBSP-A)
MXINTB
(McBSP-B)
MRINTB
(McBSP-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
DINTCH6
(DMA)
DINTCH5
(DMA)
DINTCH4
(DMA)
DINTCH3
(DMA)
DINTCH2
(DMA)
DINTCH1
(DMA)
SCITXINTC
(SCI-C)
SCIRXINTC
(SCI-C)
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
Reserved
Reserved
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
INT10
INT11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LUF
(FPU)
LVF
(FPU)
INT12
Reserved
XINT7
XINT6
XINT5
XINT4
XINT3
(1) Out of the 96 possible interrupts, 58 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
2) No peripheral interrupts are assigned to the group (example PIE group 11).
(2) ADCINT is sourced as a logical "OR" of both the SEQ1INT and SEQ2INT signals. This is to support backward compatibility with the
implementation found on the TMS320F281x series of devices, where SEQ1INT and SEQ2INT did not exist, only ADCINT. For new
implementations, TI recommends using SEQ1INT and SEQ2INT and not enabling ADCINT in the PIEIER register.
Copyright © 2021 Texas Instruments Incorporated
168 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-33. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
0x0CFA – 0x0CFF
SIZE (x16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 169
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.5.1 External Interrupts
Table 8-34. External Interrupt Registers
NAME
XINT1CR
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7073
0x00 7074
0x00 7075
0x00 7076
0x00 7077
0x00 7078
0x00 7079
0x707A – 0x707E
0x00 707F
SIZE (x16)
DESCRIPTION
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT4 configuration register
XINT5 configuration register
XINT6 configuration register
XINT7 configuration register
XNMI configuration register
XINT1 counter register
1
1
1
1
1
1
1
1
1
1
5
1
XINT2CR
XINT3CR
XINT4CR
XINT5CR
XINT6CR
XINT7CR
XNMICR
XINT1CTR
XINT2CTR
Reserved
XNMICTR
XINT2 counter register
XNMI counter register
Each external interrupt can be enabled or disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2833x, 2823x system control and interrupts reference
guide.
Copyright © 2021 Texas Instruments Incorporated
170 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low-power
modes. Figure 8-29 shows the various clock and reset domains that will be discussed.
C28x Core
SYSCLKOUT
CLKIN
System
Control
Register
Clock Enables
LSPCLK
LOSPCP
Bridge
I/O
Peripheral
Registers
SPI-A, SCI-A/B/C
Clock Enables
I2C-A
Clock Enables
/2
Bridge
Bridge
Bridge
I/O
I/O
I/O
Peripheral
Registers
eCAN-A/B
GPIO
Mux
Clock Enables
Peripheral
Registers
ePWM1/../6, HRPWM1/../6,
eCAP1/../6, eQEP1/2
Clock Enables
LSPCLK
LOSPCP
Peripheral
Registers
McBSP-A/B
Clock Enables
HSPCLK
HISPCP
16 Channels
ADC
Registers
12-Bit ADC
Result
Registers
DMA
Clock Enables
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT).
See Figure 8-30 for an illustration of how CLKIN is derived.
Figure 8-29. Clock and Reset Domains
Note
There is a 2-SYSCLKOUT cycle delay from when the write to the PCLKCR0, PCLKCR1, and
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay must be
considered before trying to access the peripheral configuration registers.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 171
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 8-35.
Table 8-35. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
PLLSTS
0x00 7011
1
7
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
4
1
PLL Status Register
Reserved
Reserved
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
0x00 7012 – 0x00 7018
0x00 7019
Reserved
0x00 701A
High-Speed Peripheral Clock Prescaler Register
Low-Speed Peripheral Clock Prescaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low-Power Mode Control Register 0
Reserved
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
Peripheral Clock Control Register 3
PLL Control Register
0x00 7021
SCSR
0x00 7022
System Control and Status Register
Watchdog Counter Register
Reserved
WDCNTR
Reserved
WDKEY
0x00 7023
0x00 7024
0x00 7025
Watchdog Reset Key Register
Reserved
Reserved
WDCR
0x00 7026 – 0x00 7028
0x00 7029
Watchdog Control Register
Reserved
Reserved
MAPCNF
0x00 702A – 0x00 702D
0x00 702E
ePWM/HRPWM Re-map Register
Copyright © 2021 Texas Instruments Incorporated
172 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.6.1 OSC and PLL Block
Figure 8-30 shows the OSC and PLL block.
OSCCLK
OSCCLK
VCOCLK
/1
/2
/4
XCLKIN
(3.3-V clock input
from external
0
n
OSCCLK or
VCOCLK
CLKIN
To
CPU
PLLSTS[OSCOFF]
PLLSTS[PLLOFF]
oscillator)
PLL
n ≠ 0
PLLSTS[DIVSEL]
4-bit Multiplier PLLCR[DIV]
X1
On-chip
oscillator
External
Crystal or
Resonator
X2
Figure 8-30. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 2833x/2823x devices using the X1
and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
•
A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO
.
•
A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2 pin
should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed
VDD
.
The three possible input-clock configurations are shown in Figure 8-31 to Figure 8-33.
XCLKIN
X1
X2
NC
External Clock Signal
(Toggling 0-VDDIO
)
Figure 8-31. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
)
NC
(Toggling 0-VDD
Figure 8-32. Using a 1.9-V External Oscillator
XCLKIN
X1
X2
C
L2
C
L1
Crystal
Figure 8-33. Using the Internal Oscillator
8.6.1.1 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz follow:
Fundamental mode, parallel resonant
•
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 173
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
•
•
•
•
CL (load capacitance) = 12 pF
CL1 = CL2 = 24 pF
Cshunt = 6 pF
ESR range = 25 to 40 Ω
TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with
the DSC chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor
can also advise the customer regarding the proper tank component values that will produce proper start-up and
stability over the entire operating range.
8.6.1.2 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
It can be re-enabled (if need be) after the PLL module has stabilized, which takes 131072 OSCCLK cycles. The
input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL
(VCOCLK) does not exceed 300 MHz.
Table 8-36. PLL Settings (1)
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(2) (3)
PLLSTS[DIVSEL] = 0 or 1
PLLSTS[DIVSEL] = 2
OSCCLK/2
PLLSTS[DIVSEL] = 3(4)
0000 (PLL bypass)
0001
OSCCLK/4 (Default)
(OSCCLK * 1)/4
(OSCCLK * 2)/4
(OSCCLK * 3)/4
(OSCCLK * 4)/4
(OSCCLK * 5)/4
(OSCCLK * 6)/4
(OSCCLK * 7)/4
(OSCCLK * 8)/4
(OSCCLK * 9)/4
(OSCCLK * 10)/4
Reserved
OSCCLK
(OSCCLK * 1)/2
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
Reserved
–
0010
–
0011
–
0100
–
0101
–
0110
–
0111
–
1000
–
1001
–
–
1010
1011 – 1111
Reserved
(1) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(3) This register is EALLOW protected. See the TMS320x2833x, 2823x system control and interrupts reference guide for more
information.
(4) A divider at the output of the PLL is necessary to ensure correct duty cycle of the clock fed to the core. For this reason, a DIVSEL
value of 3 is not allowed when the PLL is active.
Copyright © 2021 Texas Instruments Incorporated
174 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Table 8-37. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/4
/4
/2
/1(1)
(1) This mode can be used only when the PLL is bypassed or off.
The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the
device.
•
External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks
are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 8-38. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL]
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0, 1
2
3
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
0, 1
2
OSCCLK*n/4
OSCCLK*n/2
8.6.1.3 Loss of Input Clock
In PLL-enabled and PLL-bypass mode, if the input clock OSCCLK is removed or absent, the PLL will still issue a
limp-mode clock. The limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–
5 MHz. Limp mode is not specified to work from power up, only after input clocks have been present initially. In
PLL bypass mode, the limp mode clock from the PLL is automatically routed to the CPU if the input clock is
removed or absent.
Normally, when the input clocks are present, the watchdog counter decrements to initiate a watchdog reset or
WDINT interrupt. However, when the external input clock fails, the watchdog counter stops decrementing (that is,
the watchdog counter does not change with the limp-mode clock). In addition to this, the device will be reset and
the “Missing Clock Status” (MCLKSTS) bit will be set. These conditions could be used by the application
firmware to detect the input clock failure and initiate necessary shut-down procedure for the system.
Note
Applications in which the correct CPU operating frequency is absolutely critical should implement a
mechanism by which the DSC will be held in reset, should the input clocks ever fail. For example, an
R-C circuit may be used to trigger the XRS pin of the DSC, should the capacitor ever get fully
charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from
getting fully charged. Such a circuit would also help detect failure of the flash memory and the VDD3VFL
rail.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 175
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
8.6.2 Watchdog Block
The watchdog block on the 2833x/2823x device is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the
watchdog counter. Figure 8-34 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
WDCLK
Watchdog
Prescaler
8-Bit
Watchdog
Counter
CLR
/512
Clear Counter
Internal
Pullup
WDKEY[7:0]
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
WDRST(A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
1
0
1
Figure 8-34. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that
it can wake the device from STANDBY (if enabled). See Section 8.7, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
Copyright © 2021 Texas Instruments Incorporated
176 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
8.7 Low-Power Modes Block
The low-power modes on the 2833x/2823x devices are similar to the 240x devices. Table 8-39 summarizes the
various modes.
Table 8-39. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, watchdog interrupt, any enabled
interrupt, XNMI
IDLE
00
On
On
On(2)
On
XRS, watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
STANDBY
HALT
01
1X
Off
Off
Off
Off
(watchdog still running)
Off
XRS, GPIO port A signal, XNMI,
debugger(3)
(oscillator and PLL turned off,
watchdog not functional)
(1) The EXIT column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals,
will exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise,
the IDLE mode will not be exited and the device will go back into the indicated low-power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The
LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The
user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the
TMS320x2833x, 2823x system control and interrupts reference guide for more details.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 177
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Design or Reference Design
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at TIDesigns.
EtherCAT Interface for High Performance MCU Reference Design
This reference design demonstrates how to connect a C2000 Delfino MCU to an EtherCAT® ET1100 slave
controller. The interface supports both demultiplexed address/data busses for maximum bandwidth and
minimum latency and a SPI mode for low pin-count EtherCAT communication. The slave controller offloads the
processing of 100Mbps Ethernet-based fieldbus communication, thereby eliminating CPU overhead for these
tasks.
C2000 Resolver to Digital Conversion Kit
This is a motherboard-style Resolver to Digital conversion kit used to experiment with various C2000
microcontrollers for software-based resolver to digital conversion using on-chip ADCs. The Resolver Kit also
allows interface to resolvers and inverter control processor.
Copyright © 2021 Texas Instruments Incorporated
178 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
10 Device and Documentation Support
10.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail
on each of these steps, see the following:
•
•
•
•
C2000 Real-Time Control MCUs – Getting started
C2000 Real-Time Control MCUs – Tools & software
Motor drive and control
Digital power
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ DSC devices and support tools. Each TMS320™ DSP commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS 320F28335). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ZJZ) and temperature range (for example, A). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the Package Option Addendum of this document,
the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320F2833x,
TMS320F2823x DSC silicon errata .
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 179
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
A. BGA = Ball Grid Array LQFP = Low-Profile Quad Flatpack
Figure 10-1. Example of F2833x, F2823x Device Nomenclature
Copyright © 2021 Texas Instruments Incorporated
180 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page.
Design Kits and Evaluation Modules
C2000 DesignDRIVE Development Kit for Industrial Motor Control
DesignDRIVE is a single hardware and software platform that makes it easy to develop and evaluate solutions
for many industrial drive, motor control, and servo topologies. DesignDRIVE offers support for a wide variety of
motor types, sensing technologies, encoder standards and communications networks, as well as easy expansion
to develop with industrial communications and functional safety topologies, thus enabling more comprehensive,
integrated drive system solutions. Based on the real-time control architecture of TI’s C2000 microcontrollers
(MCUs), DesignDRIVE is ideal for the development of industrial inverter and servo drives used in robotics,
computer numerical control machinery (CNC), elevators, materials conveyance and other industrial
manufacturing applications.
C2000 Delfino MCUs F28377S LaunchPad Development Kit
The C2000™ Delfino™ MCUs LaunchPad™ development kit is an inexpensive evaluation platform that provides
designers with a low-cost development kit for high-performance digital control applications. This tool provides a
great starting point for development of many high-end digital control applications such as industrial drives and
automation; power line communications; solar inverters; and more.
TMS320F28335 Experimenter Kit
C2000™ MCU Experimenter Kits provide a robust hardware prototyping platform for real-time, closed loop
control development with C2000 microcontrollers. This platform is a great tool to customize and prove-out
solutions for many common power electronics applications, including motor control, digital power supplies, solar
inverters, digital LED lighting, precision sensing, and more.
Software
C2000 DesignDRIVE Software for Industrial Drives and Motor Control
The DesignDRIVE platform combines software solutions with DesignDRIVE Development Kits to make it easy to
develop and evaluate solutions for many industrial drive and servo topologies. DesignDRIVE offers support for a
wide variety of motor types, sensing technologies, position sensors and communications networks, including
specific examples for vector control of motors, incorporating current, speed and position loops, to help
developers jumpstart their evaluation and development. Based on the real-time control architecture of TI’s
C2000™ microcontrollers (MCUs), DesignDRIVE is ideal for the development of industrial inverter and servo
drives used in robotics, computer numerical control machinery (CNC), elevators, materials conveyance and
other industrial manufacturing applications.
C2000 SafeTI™ 60730 SW Packages
The C2000 MCU SafeTI-60730 Software package includes UL-certified, as recognized components, SafeTI™
software packages that help make designing for functional safety consumer applications with TI C2000™ real-
time control microcontrollers (MCUs) easier and faster. The software in these SafeTI software packages is UL-
certified, as recognized components, to the UL 1998:2008 Class 1 standard, and is compliant with IEC
60730-1:2010 Class B, both of which include home appliances, arc detectors, power converters, power tools, e-
bikes, and many others. SafeTI software packages are available for select TI C2000 MCUs and can be
embedded in applications using these MCUs to help customers simplify certification for functional safety-
compliant consumer devices. Because of the similarity of the two standards, the IEC 60730 software libraries
can also help assist customers developing consumer applications compliant with the IEC 60335-1:2010
standard.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 181
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
powerSUITE Digital Power Supply Software Frequency Response Analyzer Tool for C2000™ MCUs
The Software Frequency Response Analyzer (SFRA) is one of several tools included in the powerSUITE Digital
Power Supply Design Software Tools for C2000™ Microcontrollers. The SFRA includes a software library that
enables developers to quickly measure the frequency response of their digital power converter. The SFRA library
contains software functions that inject a frequency into the control loop and measure the response of the system
using the C2000 MCUs’ on-chip analog to digital converter (ADC). This process provides the plant frequency
response characteristics and the open loop gain frequency response of the closed loop system. The user can
then view the plant and open loop gain frequency response on a PC-based GUI. All of the frequency response
data is exported into a CSV file, or optionally an Excel spreadsheet, which can then be used to design the
compensation loop using the Compensation Designer.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
Development Tools
C2000 Gang Programmer
The C2000 Gang Programmer is a C2000 device programmer that can program up to eight identical C2000
devices at the same time. The C2000 Gang Programmer connects to a host PC using a standard RS-232 or
USB connection and provides flexible programming options that allow the user to fully customize the process.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Uniflash Standalone Flash Tool
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320F2833x, TMS320F2823x DSC silicon errata describes the advisories and usage notes for different
versions of silicon.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
Copyright © 2021 Texas Instruments Incorporated
182 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control MCU Peripherals Reference Guide describes the peripheral reference guides of the
28x digital signal processors (DSPs).
TMS320x2833x, 2823x system control and interrupts reference guide describes the various interrupts and
system control features of the 2833x and 2823x digital signal controllers (DSCs).
TMS320x2833x Analog-to-Digital Converter (ADC) module reference guide describes how to configure and use
the on-chip ADC module, which is a 12-bit pipelined ADC.
TMS320x2833x, 2823x DSC External Interface (XINTF) reference guide describes the XINTF, which is a
nonmultiplexed asynchronous bus, as it is used on the 2833x and 2823x devices.
TMS320x2833x, 2823x Boot ROM reference guide describes the purpose and features of the bootloader
(factory-programmed boot-loading software) and provides examples of code. It also describes other contents of
the device on-chip boot ROM and identifies where all of the information is located within that memory.
TMS320F2833x/2823x Multichannel Buffered Serial Port (McBSP) reference guide describes the McBSP
available on the 2833x and 2823x devices. The McBSPs allow direct interface between a DSP and other devices
in a system.
TMS320x2833x, 2823x Direct Memory Access (DMA) module reference guide describes the DMA on the 2833x
and 2823x devices.
TMS320x2833x, 2823x Enhanced Pulse Width Modulator (ePWM) module reference guide describes the main
areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply
control, UPS (uninterruptible power supplies), and other forms of power conversion.
TMS320x2833x, 2823x High Resolution Pulse Width Modulator (HRPWM) reference guide describes the
operation of the high-resolution extension to the pulse width modulator (HRPWM).
TMS320x2833x, 2823x Enhanced Capture (eCAP) module reference guide describes the enhanced capture
module. It includes the module description and registers.
TMS320x2833x, 2823x Enhanced Quadrature Encoder Pulse (eQEP) module reference guide describes the
eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get position, direction,
and speed information from a rotating machine in high-performance motion and position control systems. It
includes the module description and registers.
TMS320F2833x, 2823x Enhanced Controller Area Network (eCAN) reference guide describes the eCAN that
uses established protocol to communicate serially with other controllers in electrically noisy environments.
TMS320x2833x, 2823x Serial Communications Interface (SCI) reference guide describes the SCI, which is a
two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format.
TMS320x2833x, 2823x Serial Peripheral Interface (SPI) reference guide describes the SPI - a high-speed
synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen
bits) to be shifted into and out of the device at a programmed bit-transfer rate.
TMS320x2833x, 2823x Inter-Integrated Circuit (I2C) module reference guide describes the features and
operation of the inter-integrated circuit (I2C) module.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 183
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) Reference Guide describes development
using DSP/BIOS.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
TMS320x281x to TMS320x2833x or 2823x migration overview describes how to migrate from the 281x device
design to 2833x or 2823x designs.
TMS320x280x to TMS320x2833x or 2823x migration overview describes how to migrate from a 280x device
design to 2833x or 2823x designs.
TMS320C28x FPU Primer provides an overview of the floating-point unit (FPU) in the C2000™ Delfino
microcontroller devices.
Running an Application from Internal Flash Memory on the TMS320F28xxx DSP covers the requirements
needed to properly configure application software for execution from on-chip flash memory. Requirements for
both DSP/BIOS and non-DSP/BIOS projects are presented. Example code projects are included.
Programming TMS320x28xx and TMS320x28xxx Peripherals in C/C++ explores a hardware abstraction layer
implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define
macros and topics of code efficiency and special case registers are also addressed.
Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller presents a
method for using the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of
digital signal controllers as a digital-to-analog converter (DAC).
TMS320F280x Digital Signal Controller USB Connectivity using the TUSB3410 USB-to-UART Bridge Chip
presents hardware connections as well as software preparation and operation of the development system using
a simple communication echo program.
Using the Enhanced Quadrature Encoder Pulse (eQEP) Module in TMS320x280x, 28xxx as a Dedicated
Capture provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the
TMS320x280x, 28xxx family of processors.
Using the ePWM Module for 0% - 100% Duty Cycle Control provides a guide for the use of the ePWM module to
provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.
TMS320x280x and TMS320F2801x ADC calibration describes a method for improving the absolute accuracy of
the 12-bit ADC found on the TMS320x280x and TMS320F2801x devices. Inherent gain and offset errors affect
the absolute accuracy of the ADC. The methods described in this report can improve the absolute accuracy of
the ADC to levels better than 0.5%. This application report has an option to download an example program that
executes from RAM on the F2808 EzDSP.
Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow
detection on the TMS320C28x DSP. C-source code is provided that contains functions for implementing the
overflow detection on both DSP/BIOS and non-DSP/BIOS applications.
PowerPAD™ thermally enhanced package focuses on the specifics of integrating a PowerPAD™ package into
the PCB design.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Copyright © 2021 Texas Instruments Incorporated
184 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
www.ti.com
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
Serial flash programming of C2000™ microcontrollers discusses using a flash kernel and ROM loaders for serial
programming a device.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
Code Composer Studio™, DSP/BIOS™, MicroStar BGA™, TMS320C2000™, Delfino™, C2000™, Piccolo™,
PowerPAD™, TI E2E™ are trademarks of Texas Instruments.
EtherCAT® is a registered trademark of Beckhoff Automation GmbH, Germany.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 185
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
TMS320F28335, TMS320F28335-Q1, TMS320F28334, TMS320F28333
TMS320F28332, TMS320F28235, TMS320F28235-Q1
TMS320F28234, TMS320F28234-Q1, TMS320F28232, TMS320F28232-Q1
SPRS439P – JUNE 2007 – REVISED FEBRUARY 2021
www.ti.com
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
For packages with a thermal pad, the MECHANICAL DATA figure shows a generic thermal pad without
dimensions. For the actual thermal pad dimensions that are applicable to this device, see the THERMAL PAD
MECHANICAL DATA figure.
To learn more about TI packaging, visit the Packaging information website.
Copyright © 2021 Texas Instruments Incorporated
186 Submit Document Feedback
Product Folder Links: TMS320F28335 TMS320F28335-Q1 TMS320F28334 TMS320F28333 TMS320F28332
TMS320F28235 TMS320F28235-Q1 TMS320F28234 TMS320F28234-Q1 TMS320F28232 TMS320F28232-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
PGF
PTP
PTP
ZAY
ZHH
PGF
PTP
PTP
ZAY
ZHH
ZJZ
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS320F28232PGFA
TMS320F28232PTPQ
TMS320F28232PTPS
TMS320F28232ZAYA
TMS320F28232ZHHA
TMS320F28234PGFA
TMS320F28234PTPQ
TMS320F28234PTPS
TMS320F28234ZAYA
TMS320F28234ZHHA
TMS320F28234ZJZA
TMS320F28234ZJZQ
TMS320F28234ZJZS
TMS320F28235PGFA
TMS320F28235PTPQ
TMS320F28235PTPS
TMS320F28235ZJZA
ACTIVE
LQFP
HLQFP
HLQFP
NFBGA
176
176
176
179
179
176
176
176
179
179
176
176
176
176
176
176
176
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 125
-40 to 125
-40 to 85
F28232PGFA
TMS320
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
40
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
TMS320
F28232PTPQ
40
TMS320
F28232PTPS
160
160
40
TMS320
F28232ZAYA
BGA
MICROSTAR
F28232ZHHA
TMS320
LQFP
HLQFP
HLQFP
NFBGA
F28234PGFA
TMS320
40
TMS320
F28234PTPQ
40
TMS320
F28234PTPS
160
160
126
126
126
40
TMS320
F28234ZAYA
BGA
MICROSTAR
F28234ZHHA
TMS320
BGA
320F28234ZJZA
TMS
BGA
ZJZ
320F28234ZJZQ
TMS
BGA
ZJZ
320F28234ZJZS
TMS
LQFP
HLQFP
HLQFP
BGA
PGF
PTP
PTP
ZJZ
F28235PGFA
TMS320
40
TMS320
F28235PTPQ
40
TMS320
F28235PTPS
126
320F28235ZJZA
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMS
TMS320F28235ZJZQ
TMS320F28235ZJZQR
TMS320F28235ZJZS
TMS320F28332PGFA
TMS320F28332PTPS
TMS320F28333PGFA
TMS320F28334PGFA
TMS320F28334PTPS
TMS320F28334ZAYA
TMS320F28334ZHHA
TMS320F28334ZJZA
TMS320F28334ZJZS
TMS320F28335PGFA
TMS320F28335PTPQ
TMS320F28335PTPS
TMS320F28335ZAYA
TMS320F28335ZAYAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
BGA
BGA
ZJZ
ZJZ
176
176
176
176
176
176
176
176
179
179
176
176
176
176
176
179
179
126
RoHS & Green
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-4-260C-72 HR
Level-4-260C-72 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 85
-40 to 125
-40 to 85
-40 to 85
320F28235ZJZQ
TMS
1000 RoHS & Green
320F28235ZJZQ
TMS
BGA
ZJZ
126
40
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
320F28235ZJZS
TMS
LQFP
HLQFP
LQFP
LQFP
HLQFP
NFBGA
PGF
PTP
PGF
PGF
PTP
ZAY
ZHH
ZJZ
F28332PGFA
TMS320
40
TMS320
F28332PTPS
40
F28333PGFA
TMS320
40
F28334PGFA
TMS320
40
TMS320
F28334PTPS
160
160
126
126
40
-40 to 85
-40 to 85
-40 to 85
-40 to 125
-40 to 85
-40 to 125
-40 to 125
-40 to 85
-40 to 85
TMS320
F28334ZAYA
BGA
MICROSTAR
F28334ZHHA
TMS320
BGA
320F28334ZJZA
TMS
BGA
ZJZ
320F28334ZJZS
TMS
LQFP
PGF
PTP
PTP
ZAY
ZAY
F28335PGFA
TMS320
HLQFP
HLQFP
NFBGA
NFBGA
40
TMS320
F28335PTPQ
40
TMS320
F28335PTPS
160
TMS320
F28335ZAYA
1000 RoHS & Green
TMS320
F28335ZAYA
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
ZHH
ZJZ
Qty
160
126
126
(1)
(2)
(3)
(4/5)
(6)
TMS320F28335ZHHA
TMS320F28335ZJZA
TMS320F28335ZJZQ
TMS320F28335ZJZQR
TMS320F28335ZJZS
LIFEBUY
BGA
MICROSTAR
179
176
176
176
176
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 125
-40 to 125
-40 to 125
F28335ZHHA
TMS320
ACTIVE
ACTIVE
ACTIVE
ACTIVE
BGA
BGA
BGA
BGA
SNAGCU
SNAGCU
SNAGCU
SNAGCU
320F28335ZJZA
TMS
ZJZ
320F28335ZJZQ
TMS
ZJZ
1000 RoHS & Green
126 RoHS & Green
320F28335ZJZQ
TMS
ZJZ
320F28335ZJZS
TMS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE OUTLINE
PGF0176A
LQFP - 1.6 mm max height
SCALE 0.550
PLASTIC QUAD FLATPACK
24.2
23.8
NOTE 3
B
PIN 1 ID
133
176
1
132
24.2
23.8
26.2
TYP
25.8
NOTE 3
44
89
45
88
0.27
0.17
A
176X
172X 0.5
0.08
C A B
4X 21.5
C
SEATING PLANE
1.6 MAX
SEE DETAIL A
(0.13)
TYP
0.25
(1.4)
GAGE PLANE
0.15
0.05
0.08 C
0 -7
0.75
0.45
A
12
DETAIL A
TYPICAL
4215177/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs.
4. Reference JEDEC registration MS-026.
www.ti.com
EXAMPLE BOARD LAYOUT
PGF0176A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
176
133
176X (1.5)
1
132
176X (0.3)
172X (0.5)
SYMM
(25.4)
(R0.05) TYP
89
44
SEE DETAILS
45
88
(25.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:4X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4215177/A 05/2017
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PGF0176A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
176
133
176X (1.5)
176X (0.3)
1
132
172X (0.5)
SYMM
(25.4)
(R0.05) TYP
44
89
45
88
(25.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:4X
4215177/A 05/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
ZHH0179A
UBGA - 1.4 mm max height
SCALE 1.200
BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
0.9
C
SEATING PLANE
0.1 C
BALL TYP
1.4 MAX
0.45
0.35
10.4 TYP
SYMM
P
N
M
L
K
10.4
TYP
J
H
G
F
SYMM
E
D
0.8
C
TYP
B
A
9
10
1
2
3
4
5
6
7
8
11
12
13 14
0.55
0.45
179X
0.15
0.08
C A B
C
0.8 TYP
4220265/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This is a Pb-free solder ball design.
www.ti.com
EXAMPLE BOARD LAYOUT
ZHH0179A
UBGA - 1.4 mm max height
BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
1
3
4
5
6
7
8
2
9
10 11 12 13 14
A
(0.8) TYP
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.4)
METAL
(
0.4)
EXPOSED
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4220265/A 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
EXAMPLE STENCIL DESIGN
ZHH0179A
UBGA - 1.4 mm max height
BALL GRID ARRAY
(0.8) TYP
179X 0.4
(0.8) TYP
2
3
4
5
6
7
8
9
10
11
12
13
14
1
A
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 10X
4220265/A 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
PBGA - 2.05 mm max height
PLASTIC BALL GRID ARRAY
ZJZ0176A
15.2
14.8
A
B
13.2
12.8
BALL A1 CORNER
13.2 15.2
12.8 14.8
2.05 MAX
C
SEATING PLANE
0.10 C
(0.56)
BALL TYP
0.6
0.3
13 TYP
SYMM
TYP
(0.5) TYP
(0.5) TYP
P
N
M
L
K
J
H
G
F
13
TYP
SYMM
E
D
C
0.7
176X Ø
B
A
0.4
0.10
C A B
1 TYP
1
2
3
5
6
8
9
10
4
7
11 12 14
13
1 TYP
4223413/C 02/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This is a lead-free solder ball design.
www.ti.com
EXAMPLE BOARD LAYOUT
PBGA - 2.05 mm max height
PLASTIC BALL GRID ARRAY
ZJZ0176A
176X (Ø 0.5)
(1) TYP
SYMM
A
B
C
(1) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
1
2
3
4
5
6
7
8
9
10 11 12 13 14
LAND PATTERN EXAMPLE
SCALE: 6X
0.05 MAX
0.05 MIN
(Ø0.5)
METAL
EXPOSED METAL
EXPOSED METAL
(Ø0.5)
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
NON -SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223413/C 02/2019
NOTES: (continued)
4. Final dimension may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas
Instruments literature number SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
EXAMPLE STENCIL DESIGN
PBGA - 2.05 mm max height
PLASTIC BALL GRID ARRAY
ZJZ0176A
176X (Ø 0.5)
(1) TYP
SYMM
A
B
C
(1) TYP
D
E
F
G
H
J
SYMM
K
L
M
N
P
1
2
3
4
5
7
6
8
9
10 11 12 13 14
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 6X
4223413/C 02/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ZAY0179A
NFBGA - 1.4 mm max height
S
C
A
L
E
1
.
2
0
0
PLASTIC BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
1.4 MAX
C
SEATING PLANE
0.45
0.35
⌓ 0.12 C
10.4 TYP
(0.8)
(0.8)
SYMM
℄
P
N
M
L
K
J
SYMM
℄
H
G
10.4 TYP
F
E
D
C
0.55
179X
0.45
B
A
⌀0.15Ⓜ C A B
⌖
⌀0.08Ⓜ C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.8 TYP
0.8 TYP
4225014/C 07/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZAY0179A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.4)
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225014/C 07/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZAY0179A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 10X
4225014/C 07/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
GENERIC PACKAGE VIEW
PTP 176
24 x 24, 0.5 mm pitch
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226435/A
www.ti.com
PACKAGE OUTLINE
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
PTP0176E
24.2
23.8
NOTE 3
B
PIN 1 ID
176
133
1
132
24.2
23.8
NOTE 3
26.2
25.8
TYP
44
89
45
88
0.27
0.17
176X
172X 0.5
A
4X 21.5
0.08
C A B
C
1.6 MAX
SEATING PLANE
(0.127) TYP
SEE DETAIL A
7.16
6.62
88
45
89
44
0.25
GAGE PLANE
(1.4)
0°-7°
0.15
0.05
0.08 C
7.18
6.64
177
0.75
0.45
0.48 KEEPOUT 9 PLACES
0.75 KEEPOUT 9 PLACES
132
1
176
133
4218967/A 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
www.ti.com
EXAMPLE BOARD LAYOUT
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
PTP0176E
(
22)
NOTE 7
(7.16)
176
133
SOLDER MASK
DEFINED PAD
176X (1.5)
1
132
176X (0.3)
177
172X (0.5)
SYMM
(7.18) (25.4)
(Ø0.2) VIA
TYP
(1 TYP)
(R0.05) TYP
44
89
(1 TYP)
SYMM
45
88
METAL COVERED
BY SOLDER MASK
SEE DETAILS
(25.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 3X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218967/A 01/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. See technical brief. Powerpad thermally enhanced
package, Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
HLQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
PTP0176E
(7.16)
BASED ON
0.125 THICK STENCIL
176
133
176X (1.5)
1
132
176X (0.3)
177
172X (0.5)
SYMM
(7.18)(25.4)
(Ø0.2) VIA
TYP
44
89
45
88
METAL COVERED
BY SOLDER MASK
SYMM
(25.4)
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 3X
4218967/A 01/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号：
TMS320F28235PTPQ
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235PTPS
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZHH
TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZHHA
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZJZ
TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZJZA
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZJZQ
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZJZQR
TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28235ZJZS
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28332
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28332PGF
TMS320F2833x, TMS320F2823x Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
TMS320F28332PGFA
Digital Signal Controllers (DSCs)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明